© Semiconductor Components Industries, LLC, 2015
August, 2015 − Rev. 4 1Publication Order Number:
KAI−0330/D
KAI-0330
648 (H) x 484 (V) Interline
CCD Image Sensor
Description
The KAI−0330 Image Sensor is a high performance, low cost,
progressive scan 648 (H) × 484 (V) (1/2″ optical format) Interline
CCD Image Sensor designed specifically for demanding machine
vision, surveillance, and computer input imaging applications.
Available in both single- and dual-output configurations, frame
rates up to 120 Hz are available, providing the ability to design an
image capture device that is up to 4× faster than traditional CCD
image sensors. In addition, 9 mm square pixels with micolenses and
anti-blooming structure provide high sensitivity and excellent
specular reflection blooming control. Coupled with the additional
benefits of electronic shutter, rapid clearing of horizontal lines for
faster sub-region readout, and availability in color and monochrome
configurations, this sensor is an ideal choice for challenging imaging
applications.
Table 1. GENERAL SPECIFICATIONS
Parameter Typical Value
Architecture Interline CDD; Progressive Scan
Total Number of Pixels 680 (H) × 496 (V)
Number of Effective Pixels 648 (H) × 484 (V)
Number of Active Pixels 648 (H) × 484 (V)
Pixel Size 9.0 mm(H) × 9.0 mm (V)
Active Image Size 5.832 mm (H) × 4.356 mm (V),
7.28 mm (Diagonal),
1/2″ Optical Format
Aspect Ratio 4:3
Number of Outputs 1 or 2
Saturation Signal 30.000 e−
Output Sensitivity 11.5 mV/e−
Quantum Efficiency
−ABA (490 nm)
−CBA (620 nm, 530 nm, 460 nm) 36%
25%, 26%, 32%
Total Sensor Noise 0.5 mV rms
Dynamic Range 57 dB
Dark Current < 0.5 nA/cm2
Dark Current Doubling Temperature 8°C
Charge Transfer Efficiency 0.99999
Smear 0.01%
Image Lag Negligible
Maximum Data Rate 30 MHz
Package 20-Pin CERDIP
Cover Glass Clear Glass
NOTE: All Parameters are specified at T = 40°C unless otherwise noted.
Features
•Front Illuminated Interline Architecture
•Progressive Scan
•Electronic Shutter
•Integral RGB Color Filter Array (Optional
)
•On-Chip Dark Reference Pixels
•Low Dark Current
•Dual Output Shift Registers
•Anti-Blooming Protection
•Negligible Lag
•Low Smear
Applications
•Machine Vision
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Figure 1. KAI−0330 Interline
CCD Image Sensor
See detailed ordering and shipping information on page 2 o
f
this data sheet.
ORDERING INFORMATION
KAI−0330
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2
ORDERING INFORMATION
Table 2. ORDERING INFORMATION − KAI−0330 IMAGE SENSOR
Part Number Description Marking Code
KAI−0330−AAA−CP−BA−Dual Output Monochrome, No Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass (No Coatings), Standard Grade,
Dual Output KAI−0330D
Serial Number
KAI−0330−AAA−CP−AE−Dual Output Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Taped Clear Cover Glass (No Coatings), Engineering Grade,
Dual Output
KAI−0330−ABA−CB−AA−Single Output Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass (No Coatings), Standard Grade, Single Output KAI−0330SM
Serial Number
KAI−0330−ABA−CB−BA−Dual Output Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass (No Coatings), Standard Grade, Dual Output KAI−0330DM
Serial Number
KAI−0330−ABA−CB−AE−Dual Output Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed),
Clear Cover Glass (No Coatings), Engineering Grade, Dual Output
KAI−0330−CBA−CB−BA−Dual Output Color (Bayer RGB), Telecentric Microlens, CERDIP Package
(Sidebrazed), Clear Cover Glass (No Coatings), Standard Grade,
Dual Output KAI−0330DCM
Serial Number
KAI−0330−CBA−CB−AE−Dual Output Color (Bayer RGB), Telecentric Microlens, CERDIP Package
(Sidebrazed), Clear Cover Glass (No Coatings), Engineering Grade,
Dual Output
Table 3. ORDERING INFORMATION − EVALUATION SUPPORT
Part Number Description
KAI−0330−12−30−A−GEVK Evaluation Board (Complete Kit)
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
KAI−0330
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DEVICE DESCRIPTION
Architecture
Figure 2. Functional Block Diagram
fV1
fV2 fV2
fV1
fR
Horizontal Register A
10 dummies 4 dummies
Horizontal Register B
H1A
H2
H1B
WELL
GG
R
B
Color Filter Pattern
8 Dark Lines at Top of Image
4 Dark Lines at Bottom of Image
8 Dark Columns
24 Dark Columns
KAI−0330
Active Image Area
648 (H) × 484 (V)
9.0 × 9.0 mm Pixels
VRD
VDD
VOUTA
VSS/OG
VDD
VOUTB
VSS/OG
VSUB
The KAI−0330 consists of 648 × 484 photodiodes, 680
vertical (parallel) CCD shift registers (VCCDs), and dual
496 pixel horizontal (serial) CCD shift registers (HCCDs)
with independent output structures. The device can be
operated in either single or dual line mode. The advanced,
progressive-scan architecture of the device allows the entire
image area to be read out in a single scan. The active pixels
are surrounded by an additional 32 columns and 12 rows of
light-shielded dark reference pixels.
Image Acquisition
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron-hole pairs within the individual silicon
photodiodes. These photoelectrons are collected locally by
the formation of potential wells at each photosite. Below
photodiode saturation, the number of photoelectrons
collected at each pixel is linearly dependent on light level
and exposure time and non-linearly dependent on
wavelength. When the photodiode’s charge capacity is
reached, excess electrons are discharged into the substrate to
prevent blooming.
Charge Transport
The accumulated or integrated charge from each
photodiode is transported to the output by a three-step
process. The charge is first transported from the photodiodes
to the VCCDs by applying a large positive voltage to the
phase-one vertical clock (fV1). This reads out every row, or
line, of photodiodes into the VCCDs.
The charge is then transported from the VCCDs to the
HCCDs line by line. Finally, the HCCDs transport these
rows of charge packets to the output structures pixel by
pixel. On each falling edge of the horizontal clock, fH2,
these charge packets are dumped over the output gate (OG,
Figure 3) onto the floating diffusion (FDA and FDB,
Figure 3).
Both the horizontal and vertical shift registers use
traditional two-phase complementary clocking for charge
transport. Transfer to the HCCDs begins when fV2 is
clocked high and then low (while holding fH1A high)
causing charge to be transferred from fV1 to fV2 and
subsequently into the A HCCD. The A register can now be
read out in single line mode. If it is desired to operate the
device i n a dual line readout mode for higher frame rates, this
line is transferred into the B HCCD by clocking fH1A to
a low state, and fH1B to a high state while holding fH2 low.
After fH1A is returned to a high state, the next line can be
transferred into the A HCCD. After this clocking sequence,
both HCCDs are read out in parallel.
The charge capacity of the horizontal CCDs is slightly
more than twice that of the vertical CCDs. This feature
allows the user to perform two-to-one line aggregation in the
charge domain during V-to-H transfer. This device is also
equipped with a fast dump feature that allows the user to
selectively dump complete lines (or rows) of pixels at a time.
This dump, or line clear, is also accomplished during the
V-to-H transfer time by clocking the fast dump gate.
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Output Structure
Charge packets contained in the horizontal register are
dumped pixel by pixel, onto the floating diffusion output
node whose potential varies linearly with the quantity of
charge in each packet. The amount of potential change is
determined by the expression DVFD =DQ/C
FD.
A three-stage source-follower amplifier is used to buffer
this signal voltage of f chip with slightly less than unity gain.
The translation from the charge domain to the voltage
domain is quantified by the output sensitivity or charge to
voltage conversion in terms of mV/e−. After the signal has
been sampled off-chip, the reset clock (fR) removes the
charge from the floating diffusion and resets its potential to
the reset-drain voltage (VRD).
Figure 3. Output Structure
f
R
HCCDA
HCCDB
RD
FDB (n/c)
FDA (n/c)
NOTE: For the single output version, VOUTB is not active.
VWELL VSUB
VOUTB
VOUTA
VDD
VSS & OG
Electronic Shutter
The KAI−0330 provides a structure for the prevention of
blooming which may be used to realize a variable exposure
time as well as performing the anti-blooming function. The
anti-blooming function limits the charge capacity of the
photodiode by draining excess electrons vertically into the
substrate (hence the name Vertical Overflow Drain or
VOD). This function is controlled by applying a large
potential to the device substrate (device terminal SUB). If a
sufficiently large voltage pulse (VES ≈ 40 V) is applied to
the substrate, all photodiodes will be emptied of charge
through the substrate, beginning the integration period.
After returning the substrate voltage to the nominal value,
charge can accumulate in the diodes and the charge packet
is subsequently readout onto the VCCD at the next
occurrence o f the high level on fV1. The integration time is
then the time between the falling edges of the substrate
shutter pulse and fV1. This scheme allows electronic
variation of the exposure time by a variation in the clock
timing while maintaining a standard video frame rate.
Application of the large shutter pulse must be avoided
during the horizontal register readout or an image artifact
will appear due to feed-through. The shutter pulse VES must
be “hidden” in the horizontal retrace interval. The
integration time is changed by skipping the shutter pulse
from one horizontal retrace interval to another.
The smear specification is not met under electronic shutter
operation. Under constant light intensity and spot size, if the
electronic exposure time is decreased, the smear signal will
remain the same while the image signal will decrease
linearly with exposure. Smear is quoted as a percentage of
the image signal and so the percent smear will increase by
the same factor that the integration time has decreased. This
effect is basic to interline devices.
Extremely bright light can potentially harm solid state
imagers such as Charge-Coupled Devices (CCDs). Refer to
Application Note Using Interline CCD Image Sensors in
High Intensity Visible Lighting Conditions.
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Physical Description
Pin Description and Device Orientation
Figure 4. Pinout Diagram (Top View)
VOUTA 1
VSS/OG 2
fR3
VRD 4
VOUTB 5
VWELL 6
fH2 7
VWELL 8
fH1B 9
20 VDD
19 FDG
18 fV2O
17 fV2E
16 VWELL
15 fV1E
14 fV1O
13 VWELL
12 fH1A
Pixel 1, 1
VSUB 10 11 VSUB
Table 4. PIN DESCRIPTION
Pin No. Symbol Description
1 VOUTA Video Output Channel A
2 VSS/OG Output Amplifier Return and OG
3fRReset Clock
4 VRD Reset Drain
5 VOUTB Video Output Channel B (Note 1)
6, 8, 13, 16 VWELL P-Well (Ground)
7fH2 A & B Horizontal CCD Clock − Phase 2
9fH1B B Horizontal CCD Clock − Phase 1
10, 11 VSUB Substrate
12 fH1A A Horizontal CCD Clock − Phase 1
14 fV1O Vertical CCD Clock − Phase 1, Odd Field (Note 2)
15 fV1E Vertical CCD Clock − Phase 1, Even Field (Note 2)
17 fV2E Vertical CCD Clock − Phase 2, Even Field (Note 3)
18 fV2O Vertical CCD Clock − Phase 2, Odd Field (Note 3)
19 FDG Fast Dump Gate
20 VDD Output Amplifier Supply
1. For the single output version, VOUTB is not active.
2. Pins 14 and 15 must be connected together − only 1 Phase 1 clock driver is required.
3. Pins 17 and 18 must be connected together − only 1 Phase 2 clock driver is required.
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IMAGING PERFORMANCE
All the following values were derived using nominal
operating conditions using the recommended timing. Unless
otherwise stated, readout time = 40 ms, integration time =
40 ms and sensor temperature = 40°C. Correlated double
sampling of the output is assumed and recommended. Many
units are expressed in electrons, to convert to voltage,
multiply by the amplifier sensitivity.
Defects are excluded from the following tests and the
signal output is referenced to the dark pixels at the end of
each line unless otherwise specified.
Table 5. ELECTRO-OPTICAL FOR KAI−0330−CBA
Parameter Symbol Min. Nom. Max. Unit
Optical Fill Factor F − 55.0 − %
Saturation Exposure (Note 1) ESAT − 0.046 − mJ/cm2
Red Peak Quantum Efficiency l = 620 nm (Note 2) QER− 25 − %
Green Peak Quantum Efficiency l = 530 nm (Note 2) QEG− 26 − %
Blue Peak Quantum Efficiency l = 460 nm (Note 2) QEB− 32 − %
Green Photoresponse Shading (Note 4) RGS − 6 − %
Photoresponse Non-Uniformity (Note 3) PRNU − 5.0 − p-p %
Photoresponse Non-Linearity PRNL − 5.0 − %
Amplifier Sensitivity DV/DN− 11.5 − mV/e−
1. For l = 530 nm wavelength, and VSAT = 350 mV.
2. Refer to typical values from Figure 5.
3. Under uniform illumination with output signal equal to 280 mV.
4. This is the global variation in chip output for green pixels across the entire chip.
5. It is recommended to use low-pass filter with lCUT-OFF at ~ 680 nm for high performance.
Table 6. ELECTRO-OPTICAL FOR KAI−0330−ABA
Parameter Symbol Min. Nom. Max. Unit
Optical Fill Factor F − 55.0 − %
Saturation Exposure (Note 1) ESAT − 0.037 − mJ/cm2
Peak Quantum Efficiency (Note 2) QE − 36 − %
Photoresponse Non-Uniformity (Note 3) PRNU − 5.0 − p-p %
Photoresponse Non-Linearity PRNL − 5.0 − %
1. For l = 550 nm wavelength, and VSAT = 350 mV.
2. Refer to typical values from Figure 6.
3. Under uniform illumination with output signal equal to 280 mV.
Table 7. CCD IMAGE SPECIFICATIONS
Parameter Symbol Min. Nom. Max. Unit
Output Saturation Voltage (Notes 1, 2, 8) VSAT − 350 − mV
Dark Current ID− − 0.5 nA
Dark Current Doubling Temperature DCDT 7 8 10 °C
Charge Transfer Efficiency (Notes 2, 3) CTE − 0.99999 −
Horizontal CCD Frequency (Note 4) fH− − 30 MHz
Image Lag (Note 5) IL − − 100 e−
Blooming Margin (Notes 6, 8) XAB − 100 −
Vertical Smear (Note 7) Smr − 0.01 − %
1. VSAT is the green pixel mean value at saturation as measured at the output of the device with XAB = 1. VSAT can be varied by adjusting VSUB.
2. Measured at sensor output.
3. With stray output load capacitance of CL = 10 pF between the output and AC ground.
4. Using maximum CCD frequency and/or minimum CCD transfer times may compromise performance.
5. This is the first field decay lag measured by strobe illuminating the device at (HSAT,VSAT), and by then measuring the subsequent frame’s
average pixel output in the dark.
6. XAB represents the increase above the saturation-irradiance level (HSAT) that the device can be exposed to before blooming of the vertical
shift register will occur. It should also be noted that VOUT rises above VSAT for irradiance levels above HSAT, as shown in Figure 8.
7. Measured under 10% (~100 lines) image height illumination with white light source and without electronic shutter operation and below V SAT.
8. It should be noted that there is tradeoff between XAB and VSAT.
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Table 8. OUTPUT AMPLIFIER @ VDD = 15 V, VSS = 0.0 V
Description Symbol Min. Nom. Max. Unit
Output DC Offset (Notes 1, 2) VODC − 7 − V
Power Dissipation (Note 3) PD− 55 − mW
Output Amplifier Bandwidth (Notes 1, 4) f−3db − 140 − MHz
Off-Chip Load CL− − 10 pF
1. Measured at sensor output with constant current load of IOUT = 5 mA per output.
2. Measured with VRD = 9 V during the floating-diffusion reset interval, (fR high), at the sensor output terminals.
3. Both channels.
4. With stray output load capacitance of CL = 10 pF between the output and AC ground.
Table 9. GENERAL
Description Symbol Min. Nom. Max. Unit
Total Sensor Noise (Note 1) Vn−TOTAL − 0.5 − mV, rms
Dynamic Range (Note 2) DR − − 58 dB
1. Includes amplifier noise and dark current shot noise at data rates of 10 MHz. The number is based on the full bandwidth of the amplifier. It
can be reduced when a low pass filter is used.
2. Uses 20 Log (VSAT / Vn−TOTAL) where VSAT refers to the output saturation signal.
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TYPICAL PERFORMANCE CUR VES
Color with Microlens Quantum Efficiency
Figure 5. Nominal KAI−0330−CBA Spectral Response
0%
5%
10%
15%
20%
25%
30%
35%
400 450 500 550 600 650 700 750 800 850 900
Quantum Efficiency (%)
Wavelength (nm)
Red
Green
Blue
Monochrome with Microlens Quantum Efficiency
Figure 6. Nominal KAI−0330−ABA Spectral Response
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
400 450 500 550 600 650 700 750 800 850 900 950 1000
Absolute Quantum Efficiency
Wavelength (nm)
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Angular Quantum Efficiency
Monochrome with Microlens
For the curve marked “Horizontal”, the incident light angle is varied in a plane parallel to the HCCD.
For the curve marked “Vertical”, the incident light angle is varied in a plane parallel to the VCCD.
Figure 7. Angular Dependence on Quantum Efficiency
0
10
20
30
40
50
60
70
80
90
100
110
0 5 10 15 20 25 30
Quantum Efficiency
Angle from Normal Incidence (degrees)
Vertical
(Percent Relative to Normal Incidence)
Horizontal
Typical Photoresponse
Figure 8. Typical KAI−0330 Photoresponse
0
50
100
150
200
250
300
350
400
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
Sensor Plane Irradiance − H − (arbitrary)
Output Signal − Vout − (mV)
(HSAT, VSAT)
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Saturation Signal vs. Substrate Voltage
As VSUB is decreased, VSAT increases and anti-blooming protection decreases.
As VSUB is increased, VSAT decreases and anti-blooming protection increases.
Figure 9. Example of V
SAT
vs V
SUB
0
100
200
300
400
500
600
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
Sensor Plane Irradiance − H − (arbitrary)
Output Signal − Vout − (mV)
VSUB = 8 V
VSUB = 9 V
VSUB = 10 V
VSUB = 11 V
VSUB = 12 V
VSUB = 13 V
VSUB = 14 V
VSUB = 15 V
Frame Rate
Figure 10. Frame Rate vs. Horizontal Clock Frequency
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
0 5 10 15 20 25 30
Horizontal Clock Frequency (MHz)
Frame Rate (fps)
Single Channel Dual Channel
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DEFECT DEFINITIONS
Table 10. OPERATIONAL CONDITIONS
Description Symbol Condition
Junction Temperature TJ40°C
Integration Time tINT 40 ms
Readout Rate tREADOUT 40 ms
Table 11. SPECIFICATIONS
Point Defects (Major) Point Defects (Minor) Cluster Defects Column Defects
≤ 2 ≤ 15 0 0
Table 12. DEFECT DEFINITIONS
Defect Type Defect Definition
Major Defective Pixel A pixel whose signal deviates by more than 25 mV from the mean value of all active pixels under
dark field condition or by more than 15% from the mean value of all active pixels under uniform
illumination at 80% of saturation.
Minor Defective Pixel A pixel whose signal deviates by more than 6 mV from the mean value of all active pixels under dark
field condition.
Point Defect An isolated defective pixel.
Cluster Defect A group of 2 to 4 contiguous major defective pixels.
Column Defect A group of more than 4 contiguous major defective pixels along a single column or row.
NOTE: No row defect are allowed.
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OPERATION
Table 13. ABSOLUTE MAXIMUM RATINGS
Rating Description Min. Max. Unit Notes
Temperature (@ 10% ±5%RH) Operation Without Damage −50 70 °C
Voltage (Between Pins) SUB−WELL 0 40 V 1, 5
VRD, VDD, OG & VSS − WELL 0 15 V 2
VOUTA & VOUTB – WELL 0 15 V 2
fV1 − fV2 −12 20 V 2
fH1A, fH1B − fH2 −12 15 V 2
fH1A, fH1B, fH2, FDG − fV2 −12 15 V 2
fH2 − OG & VSS −12 15 V 2
fR – SUB −20 0 V 1, 2, 4
All Clocks – WELL −12 15 V 2
Current Output Bias Current (IOUT) − 10 mA 3
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
1. Under normal operating conditions the substrate voltage should be above +7 V, but may be pulsed to 40 V for electronic shuttering.
2. Care must be taken in handling so as not to create static discharge which may permanently damage the device.
3. Per Output, lOUT affects the band-width of the outputs.
4. fR should never be more positive than VSUB.
5. Refer to Application Note Using Interline CCD Image Sensors s in High Intensity Visible Lighting Conditions.
DC Operating Conditions
Table 14. DC OPERATING CONDITIONS
Description Symbol Min. Nom. Max. Unit Pin Impedance
Reset Drain VRD 8.5 9 9.5 V 5 pF, > 1.2 MW
Reset Drain Current IRD − 0.2 − mA
Output Amplifier Return & OG VSS − 0 − V 30 pF, > 1.2 MW
Output Amplifier Return Current ISS − 5 − mA
Output Amplifier Supply VDD 12 15.0 15.5 V 30 pF, > 1.2 M W
Output Bias Current (Note 4) IOUT − 5 10 mA
P-Well (Note 1) WELL − 0.0 − V Common
Ground (Note 1) GND − 0.0 − V
Fast Dump Gate (Note 2) FDG −5.5 −5.0 −4.5 V20 pF, > 1.2 MW
Substrate (Notes 3, 7) SUB 7 VSUB 15 V 1 nF, > 1.2 MW
1. The WELL and GND pins should be connected to P-well ground.
2. The voltage level specified will disable the fast dump feature.
3. This pin may be pulsed to VES = 40 V for electronic shuttering.
4. Per output. Note also that IOUT affects the bandwidth of the outputs.
5. Pins shown with impedance greater than 1.2 MW are expected resistances. These pins are only verified to 1.2 MW.
6. The operating levels are for room temperature operation. Operation at other temperatures may or may not require adjustments of these
voltages.
7. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.
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Figure 11. Recommended Output Structure Load Diagram
+15 V
0.1 mF
5 mA
140 W1 kW
VOUT 2N3904 or
Equivalent
Buffered
Output
AC Clock Level Conditions
Table 15. CLOCK LEVELS
Description Symbol Level Min. Nom. Max. Unit Pin Impedance
Vertical CCD Clock fV1 Low −10.0 −9.5 −9.0 V25 nF, > 1.2 MW
Mid 0.0 0.2 0.4 V
High 8.5 9.0 9.5 V
Vertical CCD Clock fV2 Low −10.0 −9.5 −9.0 V25 nF, > 1.2 MW
High 0.0 0.2 0.4 V
f1 Horizontal CCD A Clock fH1A Low −7.5 −7.0 −6.5 V100 pF, > 1.2 MW
High 2.5 3.0 3.5 V
f1 Horizontal CCD B Clock
(Single Register Mode)
(Note 4)
fH1B Low −7.5 −7.0 −6.5 V100 pF, > 1.2 MW
f1 Horizontal CCD B Clock
(Dual Register Mode)
(Note 4)
fH1B Low −7.5 −7.0 −6.5 V100 pF, > 1.2 M W
High 2.5 3.0 3.5 V
f2 Horizontal CCD Clock fH2 Low −7.5 −7.0 −6.5 V125 pF, > 1.2 MW
High 2.5 3.0 3.5 V
Reset Clock fR Low −6.5 −6.0 −5.5 V5 pF, > 1.2 MW
High −0.5 0.0 0.5 V
Fast Dump Gate Clock
(Note 3) fFDG Low −5.5 −5.0 −4.5 V20 pF, > 1.2 MW
High 4.5 5.0 5.5 V
1. The AC and DC operating levels are for room temperature operation. Operation at other temperatures may or may not require adjustments
of these voltages.
2. Pins shown with impedance greater than 1.2 MW are expected resistances. These pins are only verified to 1.2 MW.
3. When not used, refer to DC operating condition.
4. For single register mode, set fH1B to −7.0 V at all times rather than clocking it.
This device is suitable for a wide range of applications
requiring a variety o f di fferent operating conditions. Consult ON Semiconductor in those situations in which operating
conditions meet or exceed minimum or maximum levels.
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TIMING
Table 16. REQUIREMENTS AND CHARACTERISTICS (For 30 MHz Operation)
Description Symbol Min. Nom. Max. Unit Figure
Reset Pulse Width tfR− 10 − ns Figure 14
Electronic Shutter Pulse Width tES 10 25 − msFigure 15
Integration Time (Note 1) tINT 0.1 − − ms Figure 15
Photodiode to VCCD Transfer Pulse Width
(Note 2) tfVh 45−msFigure 12
Clamp Delay tCD − 15 − ns Figure 14
Clamp Pulse Width tCP − 15 − ns Figure 14
Sample Delay tSD − 35 − ns Figure 14
Sample Pulse Width tSP − 15 − ns Figure 14
Vertical Readout Delay tRD 10 − − msFigure 12
fV1, fV2 Pulse Width tfV2 2.5 − msFigure 13
fH1A, fH1B, fH2 Clock Frequency tfH− − 30 MHz Figure 14
Line A to Line B Transfer Pulse Width tfAB 2 2.5 − msFigure 17
Horizontal Delay tfHd 2 2.5 − msFigure 13
Vertical Delay tfVd 25 − − ns Figure 13
Horizontal Delay with Electronic Shutter tfHVES 1 − − msFigure 15
1. Integration time varies with shutter speed. It is to be noted that smear increases when integration time decreases below readout time (frame
time). Photodiode dark current increases when integration time increases, while CCD dark current increases with readout time (frame time).
2. Anti-blooming function is off during photodiode to VCCD transfer.
Frame Timing − Single Register Readout
Figure 12. Frame Timing Diagram − Single Register Readout
NOTE: When no electronic shutter is used, the integration time is equal to the frame time.
1
2
2
1
3
4
5
6
7
8
9
10
496
496
495
494
493
492
491
490
489
495
496
495
494 1
fV1
fV2
fV1
fV2
tRD
tfVh
1 Frame = 496 Lines
Frame Time
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Line Timing − Single Register Readout
Figure 13. Line Timing Diagram − Single Register Output
fV1
fV2 tfHd
tfVd
Empty Shift Register Phases Dark Reference Pixels Photoactive Pixels
tfV
fH1A
fH2
fR
Line Content
H1B Held Low for Single Register Operation
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
694
693
692
691
690
689
688
687
686
685
684
683
682
681
680
fH1B
Pixel Timing − Single Register Readout
Figure 14. Pixel Timing Diagram − Single Register Readout
Reference
1 Count = 1 Pixel
Signal
tfR
fH1A
tSD
tCD
fH2
fR
VOUTA
CLAMP
SAMPLE
Video after Double
Correlated Sampling
(Inverted)
tfH = 33 ns min
Reference
Signal
tCP
tSP
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17
Frame Timing − Dual Register Readout
Figure 16. Frame Timing Diagram − Dual Register Readout
NOTE: When no electronic shutter is used, the integration time is equal to the frame time.
fV1
fV2
fV1
fV2
tRD
tfVh
1 Frame = 242 Lines Pairs
Frame Time
1,2
3,4
5,6
7,8
9,10
11,12
13,14
15,16
17,18
485,486
487,488
489,490
491,492
493,494
495,496
1,2
1,2
3,4
3,4
1,2495,496493,494491,492
Line Timing − Dual Register Readout
Figure 17. Line Timing Diagram − Dual Register Output
fV1
fV2
tfHd
tfVd
Empty Shift Register Phases Dark Reference Pixels Photoactive Pixels
tfV
fH1A
fH2
fR
Line Content
fH1B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
694
693
692
691
690
689
688
687
686
685
684
683
682
681
680
t
fV
t
fV
tfA/B
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19
Fast Line Dump Timing − Removing Four Lines
Figure 19. Fast Line Dump Timing − Removing Four Lines
fV1
fR
FDG
Fast Dump Rising Edge wrt V2
Falling Edge
Dumped Line #1
Dumped Line #2
Dumped Line #3
Dumped Line #4
Valid Line
End of a Valid Line
Valid Line
fV2
fH2
fH1B
fH1A
Fast Dump Falling Edge wrt V2
Falling Edge
Fast Dump Falling Edge wrt V2
Rising Edge
FDG
fV2
Max 0.1 ms
Min 0.5 msMin 0.5 ms
FDG
fV2
FDG
fV2
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21
STORAGE AND HANDLING
Table 17. CLIMATIC REQUIREMENTS
Item Description Min. Max. Units Conditions Notes
Operation to Specification Temperature −25 40 °C@ 10% ±5% RH 1, 2
Humidity 10±5 86±5% RH @ 36±2°C Temp. 1, 2
Storage Temperature −55 70 °C@ 10% ±5% RH 2, 4
Humidity − 95±5% RH @ 49±2°C Temp. 2, 4
1. The image sensor shall meet the specifications of this document while operating at these conditions.
2. The tolerance on all relative humidity values is provided due to limitations in measurement instrument accuracy.
3. The image sensor shall continue to function but not necessarily meet the specifications of this document while operating at the specified
conditions.
4. The image sensor shall meet the specifications of this document after storage for 15 days at the specified conditions.
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For information on environmental exposure, please
download the Using Interline CCD Image Sensors in High
Intensity Lighting Conditions Application Note
(AND9183/D) from www.onsemi.com.
For information on soldering recommendations, please
download the Soldering and Mounting Techniques
Reference Manual (SOLDERRM/D) from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on device numbering and ordering codes,
please download the Device Nomenclature technical note
(TND310/D) from www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
KAI−0330
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25
Cover Glass Transmission
Figure 25. Cover Glass Transmission
0
10
20
30
40
50
60
70
80
90
100
200 300 400 500 600 700 800 900
Wavelength (nm)
Transmission (%)
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