SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
SHARC Processor
ADSP-21371/ADSP-21375
Rev. D Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
SUMMARY
High performance 32-bit/40-bit floating point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory, ADSP-21371—1M bits of on-chip SRAM
and 4M bits of on-chip mask-programmable ROM
On-chip memory, ADSP-21375—0.5M bits of on-chip
SRAM and 2M bits of on-chip mask-programmable ROM
Code compatible with all other members of the SHARC family
The ADSP-21371/ADSP-21375 processors are available with a
200/266 MHz core instruction rate with unique audiocen-
tric peripherals such as the digital applications interface,
S/PDIF transceiver, serial ports, precision clock generators,
and more. For complete ordering information, see Order-
ing Guide on Page 56.
DEDICATED AUDIO COMPONENTS
ADSP-21371—S/PDIF-compatible digital audio
receiver/transmitter
ADSP-21371—8 dual data line serial ports that operate at up
to 33 Mbps on each data line — each has a clock, frame
sync, and two data lines that can be configured as either a
receiver or transmitter pair
16 PWM outputs configured as four groups of four outputs
ROM-based security features include
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
access under program control to sensitive code
PLL has a wide variety of software and hardware multi-
plier/divider ratios
Available in a 208-lead LQFP_EP package
Figure 1. Functional Block Diagram
Internal Memory I/F
Block 0
RAM/ROM
B0D
64-BIT
Instruction
Cache
5 stage
Sequencer
PEx PEy
PMD 64-BIT
IODO 32-BIT
EPD BUS 48-BIT
Core Bus
Cross Bar
DAI Routing/Pins
PCG
A
-
D
DPI Routing/Pins
SPI/B UART
Block 1
RAM/ROM
Block 2
RAM
Block 3
RAM
AMI SDRAM
EP
External Port Pin MUX
TIMER
1
-
0
SPORT
7
-
0
PWM
3
-
0
DAG1/2 Timer
IDP/
PDAP
7
-
0
TWI
IOD0 BUS
MTM/
PCG
C
-
D
PERIPHERAL BUS
32-BIT
CORE
FLAGS
FLAGx/IRQx/
TMREXP JTAG
Internal Memory
DMD 64-BIT
PMD 64-BIT
CORE
FLAGS
IOD1
32-BIT
PERIPHERAL BUS
B1D
64-BIT
B2D
64-BIT
B3D
64-BIT
DPI Peripherals DAI Peripherals Peripherals External
Port
SIMD Core
S
DTCP
S/PDIF
Tx/Rx
DMD 64-BIT
Rev. D | Page 2 of 56 | April 2013
ADSP-21371/ADSP-21375
TABLE OF CONTENTS
Summary ............................................................... 1
Dedicated Audio Components ................................. 1
General Description ................................................. 3
SHARC Family Core Architecture ............................ 4
Family Peripheral Architecture ................................ 6
I/O Processor Features ......................................... 10
System Design .................................................... 10
Development Tools ............................................. 11
Additional Information ........................................ 12
Related Signal Chains .......................................... 12
Pin Function Descriptions ....................................... 13
ADSP-21371/ADSP-21375 Specifications .................... 16
Operating Conditions .......................................... 16
Electrical Characteristics ....................................... 17
Package Information ............................................ 18
Maximum Power Dissipation ................................. 18
Absolute Maximum Ratings ................................... 18
ESD Sensitivity ................................................... 18
Timing Specifications ........................................... 18
Output Drive Currents ......................................... 49
Test Conditions .................................................. 49
Capacitive Loading .............................................. 49
Thermal Characteristics ........................................ 50
208-Lead LQFP_EP Pinout ....................................... 51
Package Dimensions ............................................... 55
Automotive Products .............................................. 56
Ordering Guide ..................................................... 56
REVISION HISTORY
4/13—Rev. C to Rev. D
Corrected Extended Precision Normal or Instruction Word
(48 bits) ADSP-21375 Internal Memory Space .................7
Updated Development Tools ..................................... 11
Added section Related Signal Chains ...........................12
Revised MS
1-0
pin description in
Pin Function Descriptions ........................................ 13
Corrected EMU pin Type from O/T (pu) to O (O/D) (pu) in
Pin Function Descriptions ........................................ 13
Corrected T
JUNCTION
specifications in
Operating Conditions .............................................. 16
Added footnote 3 to Table 25 in
Memory Read—Bus Master .......................................29
Updated Serial Ports timing parameter data in Serial Ports—
External Clock ....................................................... 33
Updated Serial Ports timing parameter data in Serial Ports—
Internal Clock ........................................................ 34
Changed Max values in Table 33 in Pulse-Width Modulation
Generators (PWM) ................................................. 40
Updated timing parameters in Table 37 and in Figure 31 in
SPI Interface—Master .............................................. 44
Added 1.0 V, 200 MHz specifications to the following timing
specifications.
Clock Input ............................................................21
Precision Clock Generator (Direct Pin Routing) .............26
SDRAM Interface Timing ..........................................28
Memory Read—Bus Master .......................................29
Memory Write—Bus Master ......................................31
Serial Ports ............................................................33
Input Data Port (IDP) ..............................................38
S/PDIF Transmitter Input Data Timing ........................42
S/PDIF Receiver ......................................................43
SPI Interface—Slave .................................................45
ADSP-21371/ADSP-21375
Rev. D | Page 3 of 56 | April 2013
GENERAL DESCRIPTION
The ADSP-21371/ADSP-21375 SHARC
®
processors are mem-
bers of the SIMD SHARC family of DSPs that feature Analog
Devices’ Super Harvard Architecture. The processors are source
code compatible with the ADSP-2126x, ADSP-2136x, and
ADSP-2116x DSPs, as well as with first generation ADSP-2106x
SHARC processors in SISD (single-instruction, single-data)
mode. The processors are 32-bit/40-bit floating-point proces-
sors optimized for high performance automotive audio
applications with their large on-chip SRAM and mask-pro-
grammable ROM, multiple internal buses to eliminate I/O
bottlenecks, and an innovative digital applications interface
(DAI).
As shown in the functional block diagram on Page 1, the pro-
cessors use two computational units to deliver a significant
performance increase over the previous SHARC processors on a
range of DSP algorithms. Fabricated in a state-of-the-art, high
speed, CMOS process, the processors achieve an instruction
cycle time of 3.75 ns at 266 MHz. With its SIMD computational
hardware, the processors can perform 1.596 GFLOPS running
at 266 MHz.
Table 1 shows performance benchmarks for these devices.
Table 2 shows the features of the individual product offerings.
The diagram on Page 1 shows the two clock domains that make
up the ADSP-2137x processors. The core clock domain contains
the following features:
• Two processing elements, each of which comprises an
ALU, multiplier, shifter, and data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core pro-
cessor cycle
• One periodic interval timer with pinout
• On-chip SRAM (1M bit, ADSP-21371; 0.5M bit,
ADSP-21375)
• On-chip mask-programmable ROM (4M bit, ADSP-21371;
2M bit, ADSP-21375)
• JTAG test access port for emulation and boundary scan.
The JTAG provides software debug through user break-
points which allow flexible exception handling.
The diagram on Page 1 also shows the peripheral clock domains
(also known as the I/O processor) and contains the following
features:
•IOD0 (peripheral DMA) and IOD1 (external port DMA)
buses for 32-bit data transfers
• Peripheral and external port bus for core connection
• Digital applications interface that includes four precision
clock generators (PCG), an S/PDIF-compatible digital
audio receiver/transmitter, an input data port (IDP), eight
serial ports, eight serial interfaces, a 20-bit parallel input
port (PDAP), and a flexible signal routing unit (DAI SRU).
• Digital peripheral interface that includes two timers, one
UART, two serial peripheral interfaces (SPI), a 2-wire
interface (TWI), and a flexible signal routing unit
(DPI SRU).
• External port with AMI and SDRAM controller
• Four units for PWM control
• One MTM for internal to internal memory transfers
Table 1. Processor Benchmarks (at 266 MHz)
Benchmark Algorithm
Speed
(at 266 MHz)
1024 Point Complex FFT (Radix 4, With Reversal) 34.5 s
FIR Filter (per Tap)
1
1
Assumes two files in multichannel SIMD mode
1.88 ns
IIR Filter (per Biquad)
1
7.5 ns
Matrix Multiply (Pipelined)
[3 × 3] × [3 × 1]
[4 × 4] × [4 × 1]
16.91 ns
30.07 ns
Divide (y/x) 13.1 ns
Inverse Square Root 20.4 ns
Table 2. ADSP-21371/ADSP-21375 Features
Feature ADSP-21371 ADSP-21375
Frequency 266 MHz
(3.75 ns)
266 MHz
(3.75 ns)
RAM 1M bit 0.5M bit
ROM 4M bits 2M bits
Pulse-Width Modulation Yes No
Serial Ports 8 4
UART 1
Digital Application
Interface (DAI)
Yes
Digital Peripheral Interface
(DPI)
Yes
S/PDIF Transceiver Yes No
SPI 2
TWI Yes
Package 208-Lead LQFP_EP
Table 2. ADSP-21371/ADSP-21375 Features (Continued)
Feature ADSP-21371 ADSP-21375
Rev. D | Page 4 of 56 | April 2013
ADSP-21371/ADSP-21375
SHARC FAMILY CORE ARCHITECTURE
The ADSP-21371/ADSP-21375 processors are code compatible
at the assembly level with the ADSP-2136x, ADSP-2126x,
ADSP-21160x, and ADSP-21161N, and with the first generation
ADSP-2106x SHARC processors. The ADSP-21371/
ADSP-21375 processors share architectural features with the
ADSP-2126x, ADSP-2136x, and ADSP-2116x SIMD SHARC
processors, as shown in Figure 2 and detailed in the following
sections.
SIMD Computational Engine
The processors contain two computational processing elements
that operate as a single-instruction, multiple-data (SIMD)
engine. The processing elements are referred to as PEX and
PEY, and each contains an ALU, multiplier, shifter, and register
file. PEX is always active, and PEY may be enabled by setting the
PEYEN mode bit in the MODE1 register. When this mode is
enabled, the same instruction is executed in both processing ele-
ments, but each processing element operates on different data.
This architecture is efficient at executing math intensive DSP
algorithms.
Entering SIMD mode also has an effect on the way data is trans-
ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the band-
width between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera-
tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing ele-
ments. These computation units support IEEE 32-bit single-
precision floating-point, 40-bit extended precision floating-
point, and 32-bit fixed-point data formats.
Figure 2. SHARC Core Block Diagram
S
SIMD Core CACHEINTERRUPT
5 STAGE
PROGRAM SEQUENCER
PM ADDRESS 32
DM ADDRESS 32
DM DATA 64
PM DATA 64
DAG1
16x32
MRF
80-BIT
ALU
MULTIPLIER SHIFTER
RF
Rx/Fx
PEx
16x40-BIT
JTAG
DMD/PMD 64
PM DATA 48
ASTATx
STYKx
ASTATy
STYKy
TIMER
RF
Sx/SFx
PEy
16x40-BIT
MRB
80-BIT
MSB
80-BIT
MSF
80-BIT
FLAG
SYSTEM
I/F
USTAT
4x32-BIT
PX
64-BIT
DAG2
16x32
ALU MULTIPLIER
SHIFTER
DATA
SWAP
PM ADDRESS 24
ADSP-21371/ADSP-21375
Rev. D | Page 5 of 56 | April 2013
Data Register File
Each processing element contains a general-purpose data regis-
ter file. The register files transfer data between the computation
units and the data buses, and store intermediate results. These
10-port, 32-register (16 primary, 16 secondary) register files,
combined with the SHARC’s enhanced Harvard architecture,
allow unconstrained data flow between computation units and
internal memory. The registers in PEX are referred to as
R0–R15 and in PEY as S0–S15.
Context Switch
Many of the processor’s registers have secondary registers that
can be activated during interrupt servicing for a fast context
switch. The data registers in the register file, the DAG registers,
and the multiplier result register all have secondary registers.
The primary registers are active at reset, while the secondary
registers are activated by control bits in a mode control register.
Universal Registers
Universal registers can be used for general purpose tasks. The
USTAT (4) registers allow easy bit manipulations (Set, Clear,
Toggle, Test, XOR) for all system registers (control/status) of
the core.
The data bus exchange register PX permits data to be passed
between the 64-bit PM data bus and the 64-bit DM data bus, or
between the 40-bit register file and the PM data bus. These reg-
isters contain hardware to handle the data width difference.
Timer
The processors contain a core timer that can generate periodic
software interrupts. The core timer can be configured to use
FLAG3 as a timer expired signal.
Single-Cycle Fetch of an Instruction and Four Operands
The processors feature an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see Figure 2). With the processor’s separate program and data
memory buses and on-chip instruction cache, the processor can
simultaneously fetch four operands (two over each data bus)
and one instruction (from the cache), all in a single cycle.
Instruction Cache
The processors include an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.
Data Address Generators with Zero-Overhead Hardware
Circular Buffer Support
The processors’s two data address generators (DAGs) are used
for indirect addressing and implementing circular data buffers
in hardware. Circular buffers allow efficient programming of
delay lines and other data structures required in digital signal
processing, and are commonly used in digital filters and Fourier
transforms. The two DAGs contain sufficient registers to allow
the creation of up to 32 circular buffers (16 primary register sets,
16 secondary). The DAGs automatically handle address pointer
wraparound, reduce overhead, increase performance, and sim-
plify implementation. Circular buffers can start and end at any
memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the proces-
sors can conditionally execute a multiply, an add, and a subtract
in both processing elements while branching and fetching up to
four 32-bit values from memory—all in a single instruction.
On-Chip Memory
The ADSP-21371 processor contains 1 megabit of internal RAM
and four megabits of internal mask-programmable ROM (see
Table 3 on Page 6) and the ADSP-21375 processor contains 0.5
megabits of internal RAM and two megabits of internal mask-
programmable ROM (see Table 4 on Page 7). Each block can be
configured for different combinations of code and data storage.
Each memory block supports single-cycle, independent accesses
by the core processor and I/O processor. The processor’s mem-
ory architecture, in combination with its separate on-chip buses,
allow two data transfers from the core and one from the I/O
processor, in a single cycle.
The ADSP-21371 processor’s SRAM can be configured as a
maximum of 32k words of 32-bit data, 64k words of 16-bit data,
21.3k words of 48-bit instructions (or 40-bit data), or combina-
tions of different word sizes up to 1 megabit. All of the memory
can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-
bit floating-point storage format is supported that effectively
doubles the amount of data that may be stored on-chip. Conver-
sion between the 32-bit floating-point and 16-bit floating-point
formats is performed in a single instruction. While each mem-
ory block can store combinations of code and data, accesses are
most efficient when one block stores data using the DM bus for
transfers, and the other block stores instructions and data using
the PM bus for transfers.
Using the DM bus and PM buses, with one bus dedicated to a
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in
the cache.
On-Chip Memory Bandwidth
The internal memory architecture allows four accesses at the
same time to any of the four blocks, assuming no block con-
flicts. The total bandwidth is gained with DMD and PMD buses
(2 64-bits, core CLK) and the IOD0/1 buses (2 32-bit,
PCLK).
ROM-Based Security
The processors have a ROM security feature that provides hard-
ware support for securing user software code by preventing
unauthorized reading from the internal code when enabled.
When using this feature, the processor does not boot-load any
Rev. D | Page 6 of 56 | April 2013
ADSP-21371/ADSP-21375
external code, executing exclusively from internal ROM. Addi-
tionally, the processor is not freely accessible via the JTAG port.
Instead, a unique 64-bit key, which must be scanned in through
the JTAG or Test Access Port will be assigned to each customer.
The device will ignore a wrong key. Emulation features and
external boot modes are only available after the correct key is
scanned.
FAMILY PERIPHERAL ARCHITECTURE
The ADSP-21371/ADSP-21375 family contains a rich set of
peripherals that support a wide variety of applications, includ-
ing high quality audio, medical imaging, communications,
military, test equipment, 3D graphics, speech recognition, mon-
itor control, imaging, and other applications.
External Port
The external port on the ADSP-21371/ADSP-21375 SHARC
processors provide a high performance, glueless interface to a
wide variety of industry-standard memory devices. The 32-bit
wide bus (ADSP-21371) may be used to interface to synchro-
nous and/or asynchronous memory devices through the use of
its separate internal memory controllers: the first is an SDRAM
controller for connection of industry-standard synchronous
DRAM devices and DIMMs (dual inline memory module),
while the second is an asynchronous memory controller
intended to interface to a variety of memory devices. Four
memory select pins enable up to four separate devices to coexist,
supporting any desired combination of synchronous and asyn-
chronous device types.
Table 3. ADSP-21371 Internal Memory Space
IOP Registers 0x0000 0000–0x0003 FFFF
Long Word (64 bits)
Extended Precision Normal or
Instruction Word (48 bits) Normal Word (32 bits) Short Word (16 bits)
BLOCK 0 ROM
0x0004 0000–0x0004 7FFF
BLOCK 0 ROM
0x0008 0000–0x0008 AAA9
BLOCK 0 ROM
0x0008 0000–0x0008 FFFF
BLOCK 0 ROM
0x0010 0000–0x0011 FFFF
Reserved
0x0004 8000–0x0004 BFFF
Reserved
0x0008 AAAA–0x0008 FFFF
Reserved
0x0009 0000–0x0009 7FFF
Reserved
0x0012 0000–0x0012 FFFF
BLOCK 0 RAM
0x0004 C000–0x0004 CFFF
BLOCK 0 RAM
0x0009 0000–0x0009 1554
BLOCK 0 RAM
0x0009 8000–0x0009 9FFF
BLOCK 0 RAM
0x0013 0000–0x0013 3FFF
Reserved
0x0004 D000–0x0004 FFFF
Reserved
0x0009 1555–0x0009 FFFF
Reserved
0x0009 A000–0x0009 FFFF
Reserved
0x0013 4000–0x0013 FFFF
BLOCK 1 ROM
0x0005 0000–0x0005 7FFF
BLOCK 1 ROM
0x000A 0000–0x000A AAA9
BLOCK 1 ROM
0x000A 0000–0x000A FFFF
BLOCK 1 ROM
0x0014 0000–0x0015 FFFF
Reserved
0x0005 8000–0x0005 BFFF
Reserved
0x000A AAAA–0x000A FFFF
Reserved
0x000B 0000–0x000B 7FFF
Reserved
0x0016 0000–0x0016 FFFF
BLOCK 1 RAM
0x0005 C000–0x0005 CFFF
BLOCK 1 RAM
0x000B 0000–0x000B 1554
BLOCK 1 RAM
0x000B 8000–0x000B 9FFF
BLOCK 1 RAM
0x0017 0000–0x0017 3FFF
Reserved
0x0005 D000–0x0005 FFFF
Reserved
0x000B 1555–0x000B FFFF
Reserved
0x000B A000–0x000B FFFF
Reserved
0x0017 4000–0x0017 FFFF
BLOCK 2 RAM
0x0006 0000–0x0006 0FFF
BLOCK 2 RAM
0x000C 0000–0x000C 1554
BLOCK 2 RAM
0x000C 0000–0x000C 1FFF
BLOCK 2 RAM
0x0018 0000–0x0018 3FFF
Reserved
0x0006 1000–0x0006 FFFF
Reserved
0x000C 1555–0x000D FFFF
Reserved
0x000C 2000–0x000D FFFF
Reserved
0x0018 4000–0x001B FFFF
BLOCK 3 RAM
0x0007 0000–0x0007 0FFF
BLOCK 3 RAM
0x000E 0000–0x000E 1554
BLOCK 3 RAM
0x000E 0000–0x000E 1FFF
BLOCK 3 RAM
0x001C 0000–0x001C 3FFF
Reserved
0x0007 1000–0x0007 FFFF
Reserved
0x000E 1555–0x000F FFFF
Reserved
0x000E 2000–0x000F FFFF
Reserved
0x001C 4000–0x001F FFFF
ADSP-21371/ADSP-21375
Rev. D | Page 7 of 56 | April 2013
SDRAM Controller
The SDRAM controller provides an interface to up to four sepa-
rate banks of industry-standard SDRAM devices or DIMMs.
Fully compliant with the SDRAM standard, each bank has its
own memory select line (MS0–MS3), and can be configured to
contain between 16M bytes and 256M bytes of memory.
SDRAM external memory address space is shown in Table 5.
The controller maintains all of the banks as a contiguous
address space so that the processor sees this as a single address
space, even if different size devices are used in the
different banks.
A set of programmable timing parameters is available to config-
ure the SDRAM banks to support slower memory devices. The
memory banks can be configured as 16 bits wide or as
32 bits wide. The SDRAM controller address, data, clock, and
command pins can drive loads up to 30 pF. For larger memory
systems, the SDRAM controller external buffer timing should
be selected and external buffering should be provided so that the
load on the SDRAM controller pins does not exceed 30 pF.
Note that the external memory bank addresses shown in Table 5
are for normal word accesses. If 48-bit instructions are placed in
any such bank (with two instructions packed into three 32-bit
locations), then care must be taken to map data buffers in the
same bank. For example, if 2k instructions are placed starting at
the bank 0 base address (0x0020 0000), then the data buffers can
be placed starting at an address that is offset by 3k words
(0x0020 0C00).
External Memory Code Execution
The program sequencer can execute code directly from external
memory bank 0 (SRAM, SDRAM) over the 48-bit external port
data bus (EPD). This allows a reduction in internal memory
size, thereby reducing the die area. Because instructions on the
Table 4. ADSP-21375 Internal Memory Space
IOP Registers 0x0000 0000–0x0003 FFFF
Long Word (64 bits)
Extended Precision Normal or
Instruction Word (48 bits) Normal Word (32 bits) Short Word (16 bits)
BLOCK 0 ROM
0x0004 0000–0x0004 3FFF
BLOCK 0 ROM
0x0008 0000–0x0008 5554
BLOCK 0 ROM
0x0008 0000–0x0008 7FFF
BLOCK 0 ROM
0x0010 0000–0x0010 FFFF
Reserved
0x0004 4000–0x0004 BFFF
Reserved
0x0008 5555–0x0008 FFFF
Reserved
0x0008 8000–0x0009 7FFF
Reserved
0x0011 0000–0x0012 FFFF
BLOCK 0 RAM
0x0004 C000–0x0004 C7FF
BLOCK 0 RAM
0x0009 0000–0x0009 0AA9
BLOCK 0 RAM
0x0009 8000–0x0009 8FFF
BLOCK 0 RAM
0x0013 0000–0x0013 1FFF
Reserved
0x0004 C800–0x0004 FFFF
Reserved
0x0009 0AAA–0x0009 FFFF
Reserved
0x0009 9000–0x0009 FFFF
Reserved
0x0013 2000–0x0013 FFFF
BLOCK 1 ROM
0x0005 0000–0x0005 3FFF
BLOCK 1 ROM
0x000A 0000–0x000A 5554
BLOCK 1 ROM
0x000A 0000–0x000A 7FFF
BLOCK 1 ROM
0x0014 0000–0x0014 FFFF
Reserved
0x0005 4000–0x0005 BFFF
Reserved
0x000A 5555–0x000A FFFF
Reserved
0x000A 8000–0x000B 7FFF
Reserved
0x0015 0000–0x0016 FFFF
BLOCK 1 RAM
0x0005 C000–0x0005 C7FF
BLOCK 1 RAM
0x000B 0000–0x000B 0AA9
BLOCK 1 RAM
0x000B 8000–0x000B 8FFF
BLOCK 1 RAM
0x0017 0000–0x0017 1FFF
Reserved
0x0005 C800–0x0005 FFFF
Reserved
0x000B 0AAA–0x000B FFFF
Reserved
0x000B 9000–0x000B FFFF
Reserved
0x0017 2000–0x0017 FFFF
BLOCK 2 RAM
0x0006 0000–0x0006 07FF
BLOCK 2 RAM
0x000C 0000–0x000C 0AA9
BLOCK 2 RAM
0x000C 0000–0x000C 0FFF
BLOCK 2 RAM
0x0018 0000–0x0018 1FFF
Reserved
0x0006 0800–0x0006 FFFF
Reserved
0x000C 0AAA–0x000D FFFF
Reserved
0x000C 1000–0x000D FFFF
Reserved
0x0018 2000–0x001B FFFF
BLOCK 3 RAM
0x0007 0000–0x0007 07FF
BLOCK 3 RAM
0x000E 0000–0x000E 0AA9
BLOCK 3 RAM
0x000E 0000–0x000E 0FFF
BLOCK 3 RAM
0x001C 0000–0x001C 1FFF
Reserved
0x0007 0800–0x0007 FFFF
Reserved
0x000E 0AAA–0x000F FFFF
Reserved
0x000E 1000–0x000F FFFF
Reserved
0x001C 2000–0x001F FFFF
Table 5. External Memory for SDRAM Addresses
Bank Size in Words Address Range
Bank 0 62M 0x0020 0000–0x03FF FFFF
Bank 1 64M 0x0400 0000–0x07FF FFFF
Bank 2 64M 0x0800 0000–0x0BFF FFFF
Bank 3 64M 0x0C00 0000–0x0FFF FFFF
Rev. D | Page 8 of 56 | April 2013
ADSP-21371/ADSP-21375
SHARC processor are 48 bits wide, instruction throughput
when executing code from external SDRAM memory is 2
instructions every 3 SDCLK (peripheral) clock cycles over a 32-
bit wide external port, and 2 instructions every 6 SDCLK clock
cycles over a 16-bit external port. Non SDRAM external mem-
ory address space is shown in Table 6.
External Port Throughput
The throughput for the external port, based on 133 MHz clock
and 32-bit data bus, is 177M bytes/s for the AMI and 532M
bytes/s for SDRAM.
Asynchronous Memory Controller
The asynchronous memory controller provides a configurable
interface for up to four separate banks of memory or I/O
devices. Each bank can be independently programmed with dif-
ferent timing parameters, enabling connection to a wide variety
of memory devices including SRAM, ROM, flash, and EPROM,
as well as I/O devices that interface with standard memory con-
trol lines. Bank 0 occupies a 14.7M word window and banks 1, 2,
and 3 occupy a 16M word window in the processor’s address
space but, if not fully populated, these windows are not made
contiguous by the memory controller logic. The banks can also
be configured as 8-bit or 16-bit wide buses for ease of interfac-
ing to a range of memories and I/O devices tailored either to
high performance or to low cost and power.
Pulse-Width Modulation
The PWM module is a flexible, programmable, PWM waveform
generator that can be programmed to generate the required
switching patterns for various applications related to motor and
engine control or audio power control. The PWM generator can
generate either center-aligned or edge-aligned PWM wave-
forms. In addition, it can generate complementary signals on
two outputs in paired mode or independent signals in non-
paired mode (applicable to a single group of four PWM
waveforms).
The entire PWM module has four groups of four PWM outputs
each. Therefore, this module generates 16 PWM outputs in
total. Each PWM group produces two pairs of PWM signals on
the four PWM outputs.
The PWM generator is capable of operating in two distinct
modes while generating center-aligned PWM waveforms: single
update mode or double update mode. In single update mode the
duty cycle values are programmable only once per PWM period.
This results in PWM patterns that are symmetrical about the
mid-point of the PWM period. In double update mode, a sec-
ond updating of the PWM registers is implemented at the mid-
point of the PWM period. In this mode, it is possible to produce
asymmetrical PWM patterns that produce lower harmonic dis-
tortion in three-phase PWM inverters.
Digital Applications Interface (DAI)
The digital applications interface (DAI) provides the ability to
connect various peripherals to any of the processor’s DAI pins
(DAI_P1 to DAI_P20).
Programs make these connections using the signal routing unit
(SRU), shown in Figure 1.
The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be intercon-
nected under software control. This allows easy use of the DAI
associated peripherals for a much wider variety of applications
by using a larger set of algorithms than is possible with noncon-
figurable signal paths.
In the ADSP-21371, the DAI includes eight serial ports, four
precision clock generators (PCG), and an input data port (IDP).
For the ADSP-21375, the DAI includes four serial ports, four
precision clock generators (PCG) and an input data port (IDP).
The IDP provides an additional input path to the core of the
processor, configurable as either eight channels of I
2
S serial
data, or a single 20-bit wide synchronous parallel data acquisi-
tion port. Each data channel has its own DMA channel that is
independent from the processor’s serial ports.
Serial Ports
The processors feature eight synchronous serial ports on the
ADSP-21371 and four on the ADSP-21375. The SPORTs pro-
vide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices such as Analog Devices’
AD183x family of audio codecs, ADCs, and DACs. The serial
ports are made up of two data lines, a clock, and frame sync. The
data lines can be programmed to either transmit or receive and
each data line has a dedicated DMA channel.
For the ADSP-21371, serial ports are enabled via 16 program-
mable pins and simultaneous receive or transmit pins that
support up to 32 transmit or 32 receive channels of audio data
when all eight SPORTs are enabled, or eight duplex TDM
streams of 128 channels per frame.
For the ADSP-21375, serial ports are enabled via eight program-
mable pins and simultaneous receive or transmit pins that
support up to 16 transmit or 16 receive channels of audio data
when all four SPORTs are enabled, or four duplex TDM streams
of 128 channels per frame.
The serial ports operate at a maximum data rate of f
PCLK
/4.
Serial port data can be automatically transferred to and from
on-chip memory via dedicated DMA channels. Each of the
serial ports can work in conjunction with another serial port to
provide TDM support. One SPORT provides two transmit sig-
nals while the other SPORT provides the two receive signals.
The frame sync and clock are shared.
Table 6. External Memory for Non SDRAM Addresses
Bank Size in Words Address Range
Bank 0 14M 0x0020 0000–0x00FF FFFF
Bank 1 16M 0x0400 0000–0x04FF FFFF
Bank 2 16M 0x0800 0000–0x08FF FFFF
Bank 3 16M 0x0C00 0000–0x0CFF FFFF
ADSP-21371/ADSP-21375
Rev. D | Page 9 of 56 | April 2013
Serial ports operate in five modes:
• Standard DSP serial mode
•Multichannel (TDM) mode with support for packed I
2
S
mode
•I
2
S mode
•Packed I
2
S mode
• Left-justified sample pair mode
Left-justified sample pair mode is a mode where in each frame
sync cycle two samples of data are transmitted/received—one
sample on the high segment of the frame sync, the other on the
low segment of the frame sync. Programs have control over var-
ious attributes of this mode.
Each of the serial ports supports the left-justified sample pair
and I
2
S protocols (I
2
S is an industry-standard interface com-
monly used by audio codecs, ADCs, and DACs such as the
Analog Devices AD183x family), with two data pins, allowing
four left-justified sample pair or I
2
S channels (using two stereo
devices) per serial port, with a maximum of up to 32 I
2
S chan-
nels. The serial ports permit little-endian or big-endian
transmission formats and word lengths selectable from 3 bits to
32 bits. For the left-justified sample pair and I
2
S modes, data-
word lengths are selectable between 8 bits and 32 bits. Serial
ports offer selectable synchronization and transmit modes as
well as optional -law or A-law companding selection on a per
channel basis. Serial port clocks and frame syncs can be inter-
nally or externally generated.
The serial ports also contain frame sync error detection logic
where the serial ports detect frame syncs that arrive early (for
example frame syncs that arrive while the transmission/recep-
tion of the previous word is occurring). All the serial ports also
share one dedicated error interrupt.
S/PDIF-Compatible Digital Audio Receiver/Transmitter
The ADSP-21371 S/PDIF receiver/transmitter has no separate
DMA channels. It receives audio data in serial format and con-
verts it into a biphase encoded signal. The serial data input to
the receiver/transmitter can be formatted as left justified, I
2
S or
right justified with word widths of 16, 18, 20, or
24 bits.
The serial data, clock, and frame sync inputs to the S/PDIF
receiver/transmitter are routed through the signal routing unit
(SRU). They can come from a variety of sources such as the
SPORTs, external pins, the precision clock generators (PCGs),
and are controlled by the SRU control registers.
The ADSP-21375 does not have an S/PDIF-compatible digital
receiver/transmitter.
Input Data Port (IDP)
The IDP provides up to eight serial input channels—each with
its own clock, frame sync, and data inputs. The eight channels
are automatically multiplexed into a single 32-bit by eight-deep
FIFO. Data is always formatted as a 64-bit frame and divided
into two 32-bit words. The serial protocol is designed to receive
audio channels in I
2
S, left-justified sample pair, or right-justified
mode. One frame sync cycle indicates one 64-bit left/right pair,
but data is sent to the FIFO as 32-bit words (that is, one-half of a
frame at a time). The processor supports 24- and 32-bit I
2
S, 24-
and 32-bit left-justified, and 24-, 20-, 18- and 16-bit right-justi-
fied formats.
Precision Clock Generator (PCG)
The precision clock generators (PCG) consist of four units, each
of which generates a pair of signals (clock and frame sync)
derived from a clock input signal. The units, A B, C, and D, are
identical in functionality and operate independently of each
other. The two signals generated by each unit are normally used
as a serial bit clock/frame sync pair.
Digital Peripheral Interface (DPI)
The digital peripheral interface provides connections to two
serial peripheral interface (SPI) ports, one universal asynchro-
nous receiver-transmitter (UART), 12 flags, a 2-wire interface
(TWI), and two general-purpose timers.
Serial Peripheral (Compatible) Interface
The ADSP-21371/ADSP-21375 SHARC processors contain two
serial peripheral interface ports (SPIs). The SPI is an industry-
standard synchronous serial link, enabling the SPI-compatible
ports of the processors to communicate with other SPI compati-
ble devices. The SPI consists of two data pins, one device select
pin, and one clock pin. It is a full-duplex synchronous serial
interface, supporting both master and slave modes. The SPI port
can operate in a multimaster environment by interfacing with
up to four other SPI-compatible devices, either acting as a mas-
ter or slave device.
The SPI-compatible peripheral implementation also features
programmable baud rates and clock phases and polarities. The
SPI-compatible port uses open drain drivers to support a multi-
master configuration and to avoid data contention.
UART Port
The processors provide a full-duplex Universal Asynchronous
Receiver/Transmitter (UART) port, which is fully compatible
with PC-standard UARTs. The UART port provides a simpli-
fied UART interface to other peripherals or hosts, supporting
full-duplex, DMA-supported, asynchronous transfers of serial
data. The UART also has multiprocessor communication capa-
bility using 9-bit address detection. This allows it to be used in
multidrop networks through the RS-485 data interface stan-
dard. The UART port also includes support for 5 to 8 data bits, 1
or 2 stop bits, and none, even, or odd parity. The UART port
supports two modes of operation:
• PIO (programmed I/O) – The processor sends or receives
data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.
• DMA (direct memory access) – The DMA controller trans-
fers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
Rev. D | Page 10 of 56 | April 2013
ADSP-21371/ADSP-21375
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
The UART port’s baud rate, serial data format, error code gen-
eration and status, and interrupts are programmable. The port:
• Supports bit rates ranging from (f
PCLK
/1,048,576) to
(f
PCLK
/16) bits per second.
• Supports data formats from 7 to 12 bits per frame.
• Can be configured to generate maskable interrupts for both
transmit and receive operations.
In conjunction with the general-purpose timer functions, auto-
baud detection is supported.
Peripheral Timers
Two general-purpose timers can generate periodic interrupts
and be independently set to operate in one of three modes:
• Pulse waveform generation mode
• Pulse width count/capture mode
• External event watchdog mode
Each general-purpose timer has one bidirectional pin and four
registers that implement its mode of operation: a 6-bit configu-
ration register, a 32-bit count register, a 32-bit period register,
and a 32-bit pulse width register. A single control and status
register enables or disables the general-purpose timers
independently.
2-Wire Interface Port (TWI)
The TWI is a bidirectional 2-wire serial bus used to move 8-bit
data while maintaining compliance with the I
2
C bus protocol.
The TWI master incorporates the following features:
• Simultaneous master and slave operation on multiple
device systems with support for multi master data
arbitration
• Digital filtering and timed event processing
• 7-bit addressing
• 100 kbps and 400 kbps data rates
• Low interrupt rate
I/O PROCESSOR FEATURES
The I/O processor provides many channels of DMA and con-
trols the extensive set of peripherals described in the previous
sections.
DMA Controller
The processor’s on-chip DMA controller allows data transfers
without processor intervention. The DMA controller operates
independently and invisibly to the processor core, allowing
DMA operations to occur while the core is simultaneously exe-
cuting its program instructions. DMA transfers can occur
between the ADSP-2137x processor’s internal memory and its
serial ports, the SPI-compatible (serial peripheral interface)
ports, the IDP (input data port), the parallel data acquisition
port (PDAP), or the UART (see Table 7).
Delay Line DMA
The processors provide delay line DMA functionality. This
allows processor reads and writes to external delay line buffers
(and hence to external memory) with limited core interaction.
Scatter/Gather DMA
The ADSP-2137x processor provides scatter/gather DMA func-
tionality. This allows processor DMA reads/writes to/from non-
contiguous memory blocks.
SYSTEM DESIGN
The following sections provide an introduction to system design
options and power supply issues. For complete system design
information, see the ADSP-2137x SHARC Processor Hardware
Reference.
Program Booting
The internal memory of the processor boots at system power-up
from an 8-bit EPROM via the external port, an SPI master, or an
SPI slave. Booting is determined by the boot configuration
(BOOT_CFG1–0) pins in Table 8. Selection of the boot source
is controlled via the SPI as either a master or slave device, or it
can immediately begin executing from ROM.
The “Running Reset” feature allows programs to perform a reset
of the processor core and peripherals, but without resetting the
PLL and SDRAM controller, or performing a boot. The RESET-
OUT pin acts as the input for initiating a running reset.
Table 7. DMA Channels
Peripheral ADSP-21371 ADSP-21375
SPORT 16 8
PDAP 8 8
SPI 2 2
UART 2 2
EP 2 2
MTM/DTCP 2 2
Total DMA Channels 32 24
Table 8. Boot Mode Selection
BOOT_CFG1–0 Booting Mode
00 SPI Slave Boot
01 SPI Master Boot
10 EPROM/FLASH Boot
11 No boot (processor executes from
internal ROM after reset)
ADSP-21371/ADSP-21375
Rev. D | Page 11 of 56 | April 2013
Power Supplies
The processors have separate power supply connections for the
internal (V
DDINT
), and external (V
DDEXT
) power supplies. The
internal supplies must meet the 1.2 V requirement. The external
supply must meet the 3.3 V requirement. All external supply
pins must be connected to the same power supply.
Target Board JTAG Emulator Connector
Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the processor to moni-
tor and control the target board processor during emulation.
Analog Devices DSP Tools product line of JTAG emulators pro-
vides emulation at full processor speed, allowing inspection and
modification of memory, registers, and processor stacks. The
processor’s JTAG interface ensures that the emulator will not
affect target system loading
or timing.
For complete information on Analog Devices’ SHARC DSP
Tools product line of JTAG emulator operation, see the appro-
priate “Emulator Hardware User’s Guide”.
DEVELOPMENT TOOLS
Analog Devices supports its processors with a complete line of
software and hardware development tools, including integrated
development environments (which include CrossCore
®
Embed-
ded Studio and/or VisualDSP++
®
), evaluation products,
emulators, and a wide variety of software add-ins.
Integrated Development Environments (IDEs)
For C/C++ software writing and editing, code generation, and
debug support, Analog Devices offers two IDEs.
The newest IDE, CrossCore Embedded Studio, is based on the
Eclipse
TM
framework. Supporting most Analog Devices proces-
sor families, it is the IDE of choice for future processors,
including multicore devices. CrossCore Embedded Studio
seamlessly integrates available software add-ins to support real
time operating systems, file systems, TCP/IP stacks, USB stacks,
algorithmic software modules, and evaluation hardware board
support packages. For more information visit
www.analog.com/cces.
The other Analog Devices IDE, VisualDSP++, supports proces-
sor families introduced prior to the release of CrossCore
Embedded Studio. This IDE includes the Analog Devices VDK
real time operating system and an open source TCP/IP stack.
For more information visit www.analog.com/visualdsp. Note
that VisualDSP++ will not support future Analog Devices
processors.
EZ-KIT Lite Evaluation Board
For processor evaluation, Analog Devices provides wide range
of EZ-KIT Lite
®
evaluation boards. Including the processor and
key peripherals, the evaluation board also supports on-chip
emulation capabilities and other evaluation and development
features. Also available are various EZ-Extenders
®
, which are
daughter cards delivering additional specialized functionality,
including audio and video processing. For more information
visit www.analog.com and search on “ezkit” or “ezextender”.
EZ-KIT Lite Evaluation Kits
For a cost-effective way to learn more about developing with
Analog Devices processors, Analog Devices offer a range of EZ-
KIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT
Lite evaluation board, directions for downloading an evaluation
version of the available IDE(s), a USB cable, and a power supply.
The USB controller on the EZ-KIT Lite board connects to the
USB port of the user’s PC, enabling the chosen IDE evaluation
suite to emulate the on-board processor in-circuit. This permits
the customer to download, execute, and debug programs for the
EZ-KIT Lite system. It also supports in-circuit programming of
the on-board Flash device to store user-specific boot code,
enabling standalone operation. With the full version of Cross-
Core Embedded Studio or VisualDSP++ installed (sold
separately), engineers can develop software for supported EZ-
KITs or any custom system utilizing supported Analog Devices
processors.
Software Add-Ins for CrossCore Embedded Studio
Analog Devices offers software add-ins which seamlessly inte-
grate with CrossCore Embedded Studio to extend its capabilities
and reduce development time. Add-ins include board support
packages for evaluation hardware, various middleware pack-
ages, and algorithmic modules. Documentation, help,
configuration dialogs, and coding examples present in these
add-ins are viewable through the CrossCore Embedded Studio
IDE once the add-in is installed.
Board Support Packages for Evaluation Hardware
Software support for the EZ-KIT Lite evaluation boards and EZ-
Extender daughter cards is provided by software add-ins called
Board Support Packages (BSPs). The BSPs contain the required
drivers, pertinent release notes, and select example code for the
given evaluation hardware. A download link for a specific BSP is
located on the web page for the associated EZ-KIT or EZ-
Extender product. The link is found in the Product Download
area of the product web page.
Middleware Packages
Analog Devices separately offers middleware add-ins such as
real time operating systems, file systems, USB stacks, and
TCP/IP stacks. For more information see the following web
pages:
•www.analog.com/ucos3
•www.analog.com/ucfs
•www.analog.com/ucusbd
•www.analog.com/lwip
Algorithmic Modules
To speed development, Analog Devices offers add-ins that per-
form popular audio and video processing algorithms. These are
available for use with both CrossCore Embedded Studio and
VisualDSP++. For more information visit www.analog.com
and search on “Blackfin software modules” or “SHARC software
modules”.
Rev. D | Page 12 of 56 | April 2013
ADSP-21371/ADSP-21375
Designing an Emulator-Compatible DSP Board (Target)
For embedded system test and debug, Analog Devices provides
a family of emulators. On each JTAG DSP, Analog Devices sup-
plies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit
emulation is facilitated by use of this JTAG interface. The emu-
lator accesses the processor’s internal features via the
processor’s TAP, allowing the developer to load code, set break-
points, and view variables, memory, and registers. The
processor must be halted to send data and commands, but once
an operation is completed by the emulator, the DSP system is set
to run at full speed with no impact on system timing. The emu-
lators require the target board to include a header that supports
connection of the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, signal buffering, signal ter-
mination, and emulator pod logic, see the Engineer-to-Engineer
Note “Analog Devices JTAG Emulation Technical Reference”
(EE-68) on the Analog Devices website (www.analog.com)—use
site search on “EE-68.” This document is updated regularly to
keep pace with improvements to emulator support.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the processor’s
architecture and functionality. For detailed information on the
core architecture and instruction set, refer to the ADSP-2137x
SHARC Processor Hardware Reference.
RELATED SIGNAL CHAINS
A signal chain is a series of signal conditioning electronic com-
ponents that receive input (data acquired from sampling either
real-time phenomena or from stored data) in tandem, with the
output of one portion of the chain supplying input to the next.
Signal chains are often used in signal processing applications to
gather and process data or to apply system controls based on
analysis of real-time phenomena. For more information about
this term and related topics, see the “signal chain” entry in the
Glossary of EE Terms on the Analog Devices website.
Analog Devices eases signal processing system development by
providing signal processing components that are designed to
work together well. A tool for viewing relationships between
specific applications and related components is available on the
www.analog.com website.
The Circuits from the Lab
TM
site (www.analog.com/signal
chains) provides:
• Graphical circuit block diagram presentation of signal
chains for a variety of circuit types and applications
• Drill down links for components in each chain to selection
guides and application information
• Reference designs applying best practice design techniques
ADSP-21371/ADSP-21375
Rev. D | Page 13 of 56 | April 2013
PIN FUNCTION DESCRIPTIONS
The following symbols appear in the Type column of Table 9:
A = asynchronous, I = input, O = output, S = synchronous,
(A/D) = active drive, (O/D) = open drain, and T = three-state,
(pd) = pull-down resistor, (pu) = pull-up resistor.
Table 9. Pin Descriptions
Name Type
State During
and After
Reset Description
ADDR
23–0
O/T (pu) Pulled high/
driven low
External Address.
The processor outputs addresses for external memory and periph-
erals on these pins.
DATA
31–0
I/O (pu) Pulled high/
pulled high
External Data.
The data pins can be multiplexed to support the external memory
interface data (I/O), the PDAP (I) (PDAP for ADSP-21371), FLAGS (I/O) and PWM (O). After
reset, all DATA pins are in EMIF mode and FLAG(0–3) pins are in FLAGS mode (default).
When configured in the IDP_PDAP_CTL register, IDP channel 0 scans the external port
data pins for parallel input data. PDAP over 16-bit external port DATA is not supported
on the ADSP-21375 processor.
DAI _P
20–1
I/O with
programmable
(pu)
1
Pulled high/
pulled high
Digital Applications Interface Pins
. These pins provide the physical interface to the
DAI SRU. The DAI SRU configuration registers define the combination of on-chip audio-
centric peripheral inputs or outputs connected to the pin and to the pin’s output enable.
The configuration registers of these peripherals then determine the exact behavior of
the pin. Any input or output signal present in the DAI SRU may be routed to any of these
pins. The DAI SRU provides the connection from the serial ports, the S/PDIF module
(ADSP-21371), IDP (2), and the PCGs (4), to the DAI_P20–1 pins. Pullups can be disabled
via the DAI_PIN_PULLUP register.
DPI _P
14–1
I/O with
programmable
(pu)
1
Pulled high/
pulled high
Digital Peripheral Interface.
These pins provide the physical interface to the DPI SRU.
The DPI SRU configuration registers define the combination of on-chip peripheral inputs
or outputs connected to the pin and to the pin’s output enable. The configuration
registers of these peripherals then determines the exact behavior of the pin. Any input
or output signal present in the DPI SRU may be routed to any of these pins. The DPI SRU
provides the connection from the timers (2), SPIs (2), UART (1), flags (12), and general-
purpose I/O (9) to the DPI_P14–1 pins. Pull-ups can be disabled via the DPI_PIN_PULLUP
register.
ACK I (pu)
Memory Acknowledge.
External devices can deassert ACK (low) to add wait states to
an external memory access. ACK is used by I/O devices, memory controllers, or other
peripherals to hold off completion of an external memory access.
RD O/T (pu) Pulled high/
driven high
External Port Read Enable.
RD is asserted whenever the processor reads a word from
external memory. RD has a 22.5 k
internal pull-up resistor.
WR O/T (pu) Pulled high/
driven high
External Port Write Enable.
WR is asserted when the processor writes a word to
external memory. WR has a 22.5 k
internal pull-up resistor.
SDRAS O/T (pu) Pulled high/
driven high
SDRAM Row Address Strobe.
Connect to SDRAM’s RAS pin. In conjunction with other
SDRAM command pins, defines the operation for the SDRAM to perform.
SDCAS O/T (pu) Pulled high/
driven high
SDRAM Column Address Select.
Connect to SDRAM's CAS pin. In conjunction with
other SDRAM command pins, defines the operation for the SDRAM to perform.
SDWE O/T (pu) Pulled high/
driven high
SDRAM Write Enable.
Connect to SDRAM’s WE or W buffer pin.
Rev. D | Page 14 of 56 | April 2013
ADSP-21371/ADSP-21375
SDCKE O/T (pu) Pulled high/
driven high
SDRAM Clock Enable.
Connect to SDRAM’s CKE pin. Enables and disables the CLK
signal. For details, see the data sheet supplied with the SDRAM device.
SDA10 O/T (pu) Pulled high/
driven low
SDRAM A10 Pin.
Enables applications to refresh an SDRAM in parallel with a non-
SDRAM accesses. This pin replaces the DSP’s A10 pin only during SDRAM accesses.
SDCLK O/T High-Z/driving
SDRAM Clock.
MS
0–1
O/T (pu) Pulled high/
driven high
Memory Select Lines 0–1.
These lines are asserted (low) as chip selects for the corre-
sponding banks of external memory. The MS
1-0
lines are decoded memory address lines
that change at the same time as the other address lines. The MS1 pin can be used in
EPORT/FLASH boot mode. For more information, see the
ADSP-2137x SHARC Processor
Hardware Reference.
FLAG[0]/IRQ0 I/O FLAG[0] INPUT
FLAG0/Interrupt Request0.
FLAG[1]/IRQ1 I/O FLAG[1] INPUT
FLAG1/Interrupt Request1.
FLAG[2]/IRQ2/
MS2
I/O with
programmable pu
(for MS mode)
FLAG[2] INPUT
FLAG2/Interrupt Request/Memory Select2.
FLAG[3]/
TMREXP/ MS3
I/O with
programmable pu
(for MS mode)
FLAG[3] INPUT
FLAG3/Timer Expired/Memory Select3.
TDI I (pu)
Test Data Input (JTAG).
Provides serial data for the boundary scan logic. TDI has a
22.5 k
internal pull-up resistor.
TDO O/T
Test Data Output (JTAG).
Serial scan output of the boundary scan path.
TMS I (pu)
Test Mode Select (JTAG).
Used to control the test state machine. TMS has a 22.5 k
internal pull-up resistor.
TCK I
Test Clock (JTAG).
Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up or held low for proper operation of the processor.
TRST I (pu)
Test Reset (JTAG).
Resets the test state machine. TRST must be asserted (pulsed low)
after power-up or held low for proper operation of the processor. TRST has a 22.5 k
internal pull-up resistor.
EMU O (O/D) (pu)
Emulation Status.
Must be connected to the processor. Analog Devices DSP Tools
product line of JTAG emulators target board connector only. EMU has a 22.5 k
internal
pull-up resistor.
CLK_CFG
1–0
I
Core to CLKIN Ratio Control.
These pins set the start up clock frequency. See the
ADSP-2137x SHARC Processor Hardware Reference
for a description of the clock configu-
ration modes.
Note that the operating frequency can be changed by programming the PLL multiplier
and divider in the PMCTL register at any time after the core comes out of reset.
BOOT_CFG
1–0
I
Boot Configuration Select.
These pins select the boot mode for the processor. The
BOOT_CFG pins must be valid before reset is asserted. See the
ADSP-2137x SHARC
Processor Hardware Reference
for information about boot modes.
Table 9. Pin Descriptions (Continued)
Name Type
State During
and After
Reset Description
ADSP-21371/ADSP-21375
Rev. D | Page 15 of 56 | April 2013
RESET I
Processor Reset.
Resets the processor to a known state. Upon deassertion, there is a
4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program
execution from the hardware reset vector address. The RESET input must be asserted
(low) at power-up.
XTAL O
Crystal Oscillator Terminal.
Used in conjunction with CLKIN to drive an external crystal.
CLKIN I
Local Clock In.
Used in conjunction with XTAL. CLKIN is the processor clock input. It
configures the processor to use either its internal clock generator or an external clock
source. Connecting the necessary components to CLKIN and XTAL enables the internal
clock generator. Connecting the external clock to CLKIN while leaving XTAL uncon-
nected configures the processor to use the external clock source such as an external
clock oscillator. CLKIN may not be halted, changed, or operated below the specified
frequency.
RESETOUT/
RUNRSTIN
I/O (pu)
Reset Out/Running Reset In.
The default setting is reset out. This pin also has a second
function as RUNRSTIN, which is enabled by setting bit 0 of the RUNRSTCTL register. For
more information, see the
ADSP-2137x SHARC Processor Hardware Reference
.
1
Pull-up can be enabled/disabled, value of pull-up cannot be programmed.
Table 9. Pin Descriptions (Continued)
Name Type
State During
and After
Reset Description
Rev. D | Page 16 of 56 | April 2013
ADSP-21371/ADSP-21375
ADSP-21371/ADSP-21375 SPECIFICATIONS
OPERATING CONDITIONS
Parameter
1
1
Specifications subject to change without notice.
Description
1.0 V, 200 MHz 1.2 V, 266 MHz
UnitMin Max Min Max
V
DDINT
Internal (Core) Supply Voltage 0.95 1.05 1.14 1.26 V
V
DDEXT
External (I/O) Supply Voltage 3.13 3.47 3.13 3.47 V
V
IH
2
2
Applies to input and bidirectional pins: ADDR23–0, DATA31–0 (DATA15–0 on ADSP-21375), FLAG3–0, DAI_Px, DPI_Px, SPIDS, BOOT_CFGx, CLK_CFGx, RUNRSTIN,
RESET, TCK, TMS, TDI, TRST.
High Level Input Voltage @ V
DDEXT
= Max 2.0 V
DDEXT
+ 0.5 2.0 V
DDEXT
+ 0.5 V
V
IL
2
Low Level Input Voltage @ V
DDEXT
= Min –0.5 +0.8 –0.5 +0.8 V
V
IH
_
CLKIN
3
3
Applies to input pin CLKIN.
High Level Input Voltage @ V
DDEXT
= Max 1.74 V
DDEXT
+ 0.5 1.74 V
DDEXT
+ 0.5 V
V
IL
_
CLKIN
3
Low Level Input Voltage @ V
DDEXT
= Min –0.5 +1.10 –0.5 +1.10 V
T
JUNCTION
Junction Temperature 208-Lead LQFP_EP @ T
AMBIENT
0°C to +70°C
N/A N/A 0 95 ºC
T
JUNCTION
Junction Temperature 208-Lead LQFP_EP @ T
AMBIENT
–40°C to +85°C
N/A N/A –40 +110 ºC
T
JUNCTION
Junction Temperature 208-Lead LQFP_EP @ T
AMBIENT
–40°C to +105°C
–40 +120 N/A N/A ºC
ADSP-21371/ADSP-21375
Rev. D | Page 17 of 56 | April 2013
ELECTRICAL CHARACTERISTICS
1.0 V, 200 MHz 1.2 V, 266 MHz
Parameter
1
Description Test Conditions Min Typ Max Min Typ Max Unit
V
OH
2
High Level Output Voltage @ V
DDEXT
= Min, I
OH
= –1.0 mA
3
2.4 2.4 V
V
OL
2
Low Level Output Voltage @ V
DDEXT
= Min, I
OL
= 1.0 mA
3
0.4 0.4 V
I
IH
4, 5
High Level Input Current @ V
DDEXT
= Max, V
IN
= V
DDEXT
max 10 10 μA
I
IL
4
Low Level Input Current @ V
DDEXT
= Max, V
IN
= 0 V 10 10 μA
I
ILPU
5
Low Level Input Current
Pull-up
@ V
DDEXT
= Max, V
IN
= 0 V 200 200 μA
I
OZH
6, 7
Three-State Leakage Current @ V
DDEXT
= Max, V
IN
= V
DDEXT
Max 10 10 μA
I
OZL
6
Three-State Leakage Current @ V
DDEXT
= Max, V
IN
= 0 V 10 10 μA
I
OZLPU
7
Three-State Leakage Current
Pull-up
@ V
DDEXT
= Max, V
IN
= 0 V 200 200 μA
I
DD
-
INTYP
8,
9
Supply Current (Internal) 1.0V, 200 MHz: t
CCLK
= 5.00 ns,
V
DDINT
= 1.0 V, 25ºC
1.2V, 266 MHz: t
CCLK
= 3.75 ns,
V
DDINT
= 1.2 V, 25ºC
400
600
mA
mA
C
IN
10,
11
Input Capacitance f
IN
= 1 MHz, T
CASE
= 25°C, V
IN
= 1.2 V 4.7 4.7 pF
1
Specifications subject to change without notice.
2
Applies to output and bidirectional pins: ADDR23–0, DATA31–0 (DATA15–0 on ADSP-21375), RD, WR, FLAG3–0, DAI_Px, DPI_Px, EMU, TDO, SDRAS, SDCAS, SDWE,
SDCKE, SDA10, and SDCLK.
3
See Output Drive Currents on Page 49 for typical drive current capabilities.
4
Applies to input pins: BOOT_CFGx, CLKCFGx, TCK, RESET, CLKIN.
5
Applies to input pins with 22.5 k internal pull-ups: TRST, TMS, TDI.
6
Applies to three-statable pins: FLAG3–0.
7
Applies to three-statable pins with 22.5 k pull-ups: DAI_Px, DPI_Px, EMU.
8
Typical internal current data reflects nominal operating conditions.
9
See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-2137x SHARC Processors” (EE-318) for further information.
10
Applies to all signal pins.
11
Guaranteed, but not tested.
Rev. D | Page 18 of 56 | April 2013
ADSP-21371/ADSP-21375
PACKAGE INFORMATION
The information presented in Figure 3 provides details about
the package branding for the ADSP-21371/ADSP-21375 proces-
sor. For a complete listing of product availability, see Ordering
Guide on Page 56.
MAXIMUM POWER DISSIPATION
See Engineer-to-Engineer Note “Estimating Power Dissipation
for ADSP-2137x SHARC Processors” (EE-318) for detailed ther-
mal and power information regarding maximum power
dissipation. For information on package thermal specifications,
see Thermal Characteristics on Page 50.
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in Table 11 may cause perma-
nent damage to the device. These are stress ratings only;
functional operation of the device at these or any other condi-
tions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
ESD SENSITIVITY
TIMING SPECIFICATIONS
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. See
Figure 38 on Page 49 under Test Conditions for voltage refer-
ence levels.
Switching Characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char-
acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Core Clock Requirements
The processor’s internal clock (a multiple of CLKIN) provides
the clock signal for timing internal memory, processor core, and
serial ports. During reset, program the ratio between the proces-
sor’s internal clock frequency and external (CLKIN) clock
frequency with the CLK_CFG1–0 pins.
The processor’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL,
see Figure 4). This PLL-based clocking minimizes the skew
between the system clock (CLKIN) signal and the processor’s
internal clock.
Figure 3. Typical Package Brand
Table 10. Package Brand Information
Brand Key Field Description
t Temperature Range
pp Package Type
Z RoHS Compliant Part
cc See Ordering Guide
vvvvvv.x Assembly Lot Code
n.n Silicon Revision
yyww Date Code
Table 11. Absolute Maximum Ratings
Parameter Rating
Internal (Core) Supply Voltage (V
DDINT
) –0.3 V to +1.5 V
External (I/O) Supply Voltage (V
DDEXT
) –0.3 V to +4.6 V
Input Voltage –0.5 V to V
DDEXT
+0.5 V
Output Voltage Swing –0.5 V to V
DDEXT
+0.5 V
vvvvvv.x n.n
tppZ-cc
S
ADSP-2137x
a
yyww country_of_origin
Load Capacitance 200 pF
Storage Temperature Range –65C to +150C
Junction Temperature under Bias 125C
Table 11. Absolute Maximum Ratings (Continued)
Parameter Rating
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid
performance degradation or loss of functionality.
ADSP-21371/ADSP-21375
Rev. D | Page 19 of 56 | April 2013
Voltage Controlled Oscillator
In application designs, the PLL multiplier value should be
selected in such a way that the VCO frequency never exceeds
f
VCO
specified in Table 14.
• The product of CLKIN and PLLM must never exceed 1/2
f
VCO
(max) in Table 14 if the input divider is not enabled
(INDIV = 0).
• The product of CLKIN and PLLM must never exceed f
VCO
(max) in Table 14 if the input divider is enabled
(INDIV = 1).
The VCO frequency is calculated as follows:
f
VCO
= 2 × PLLM × f
INPUT
f
CCLK
= (2 × PLLM × f
INPUT
) (2 × PLLD)
where:
f
VCO
= VCO output
PLLM = Multiplier value programmed in the PMCTL register.
During reset, the PLLM value is derived from the ratio selected
using the CLK_CFG pins in hardware.
PLLD = 1, 2, 4, 8 based on the PLLD value programmed on the
PMCTL register. During reset this value is 1.
f
INPUT
= Input frequency to the PLL.
f
INPUT
= CLKIN when the input divider is disabled or
f
INPUT
= CLKIN 2 when the input divider is enabled
Note the definitions of the clock periods that are a function of
CLKIN and the appropriate ratio control shown in Table 12. All
of the timing specifications for the ADSP-2137x peripherals are
defined in relation to t
PCLK
. See the peripheral specific section
for each peripheral’s timing information.
Figure 4 shows core to CLKIN relationships with external oscil-
lator or crystal. The shaded divider/multiplier blocks denote
where clock ratios can be set through hardware or software
using the power management control register (PMCTL). For
more information, see the ADSP-2137x SHARC Processor Hard-
ware Reference.
Table 12. Clock Periods
Timing
Requirements Description
t
CK
CLKIN Clock Period
t
CCLK
Processor Core Clock Period
t
PCLK
Peripheral Clock Period = 2 × t
CCLK
Figure 4. Core Clock and System Clock Relationship to CLKIN
LOOP
FILTER
CLKIN
PCLK
SDCLK
SDRAM
DIVIDER
PMCTL
(PLLBP)
BYPASS
MUX
DIVIDE
BY 2
PMCTL
(SDCKR)
CCLK
BYPASS
MUX
PLL
XTAL
CLKIN
DIVIDER
RESETOUT
RESET
PLL
MULTIPLIER
BUF
VCO
BUF
PMCTL
(INDIV)
PLL
DIVIDER
CLK_CFGx/PMCTL (2xPLLM)
PINMUX
RESETOUT
CLKOUT (TEST ONLY)
DELAY OF
4096 CLKIN
CYCLES
CORERST
CCLK
PCLK
PMCTL
(PLLBP)
PMCTL
(2xPLLD)
fVCO
fCCLK
fINPUT
Rev. D | Page 20 of 56 | April 2013
ADSP-21371/ADSP-21375
Power-Up Sequencing
The timing requirements for processor startup are given in
Table 13.
Note that during power-up, a leakage current of approximately
200 μA may be observed on the RESET pin. This leakage current
results from the weak internal pull-up resistor on this pin being
enabled during power-up.
Table 13. Power Up Sequencing Timing Requirements (Processor Startup)
Parameter Min Max Unit
Timing Requirements
t
RSTVDD
RESET Low Before V
DDINT
/V
DDEXT
On 0 ns
t
IVDDEVDD
V
DDINT
on Before V
DDEXT
–50 +200 ms
t
CLKVDD
1
CLKIN Valid After V
DDINT
/V
DDEXT
Valid 0 200 ms
t
CLKRST
CLKIN Valid Before RESET Deasserted 10
2
μs
t
PLLRST
PLL Control Setup Before RESET Deasserted 20
3
μs
Switching Characteristic
t
CORERST
Core Reset Deasserted After RESET Deasserted 4096 × t
CK
+ 2 × t
CCLK
4,
5
1
Valid V
DDINT
/V
DDEXT
assumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds
depending on the design of the power supply subsystem.
2
Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's datasheet for startup time. Assume
a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3
Based on CLKIN cycles.
4
Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and
propagate default states at all I/O pins.
5
The 4096 cycle count depends on t
SRST
specification in Table 15. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097
cycles maximum.
Figure 5. Power-Up Sequencing
tRSTVDD
tCLKVDD
tCLKRST
tCORERST
tPLLRST
VDDEXT
VDDINT
CLKIN
CLK_CFG1–0
RESET
RESETOUT
tIVDDEVDD
ADSP-21371/ADSP-21375
Rev. D | Page 21 of 56 | April 2013
Clock Input
Clock Signals
The processor can use an external clock or a crystal. See the
CLKIN pin description in Table 9. Programs can configure the
processor to use its internal clock generator by connecting the
necessary components to CLKIN and XTAL. Figure 7 shows the
component connections used for a crystal operating in funda-
mental mode. Note that the clock rate is achieved using a
16.67 MHz crystal and a PLL multiplier ratio 16:1
(CCLK:CLKIN achieves a clock speed of 266 MHz). To achieve
the full core clock rate, programs need to configure the multi-
plier bits in the PMCTL register.
Table 14. Clock Input
Parameter
200 MHz 266 MHz
Unit
Min Max Min Max
Timing Requirements
t
CK
CLKIN Period 30
1
1
Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in the PMCTL register.
100 22.5
1
100 ns
t
CKL
CLKIN Width Low 15
1
45 11.25
1
45 ns
t
CKH
CLKIN Width High 15
1
45 11.25
1
45 ns
t
CKRF
CLKIN Rise/Fall (0.4 V to 2.0 V) 6 6 ns
t
CCLK
2
2
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t
CCLK
.
CCLK Period 5 103.7510ns
f
VCO
VCO Frequency 200 800 200 800 MHz
Figure 6. Clock Input
CLKIN
tCK
tCKL
tCKH
Figure 7. 266 MHz Operation (Fundamental Mode Crystal)
C1
22pF Y1
R1
1M⍀*
XTAL
CLKIN
C2
22pF
16.67 MHz
R2
47⍀*
R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL
DRIVE POWER. REFER TO CRYSTAL
MANUFACTURER’SSPECIFICATIONS
*TYPICAL VALUES
ADSP-2137x
Rev. D | Page 22 of 56 | April 2013
ADSP-21371/ADSP-21375
Reset
Running Reset
The following timing specification applies to the RESETOUT/
RUNRSTIN pin when it is configured as RUNRSTIN.
Table 15. Reset
Parameter Min Max Unit
Timing Requirements
t
WRST
1
RESET Pulse Width Low 4 × t
CK
ns
t
SRST
RESET Setup Before CLKIN Low 8 ns
1
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 s while RESET is low, assuming stable
V
DD
and CLKIN (not including start-up time of external clock oscillator).
Figure 8. Reset
CLKIN
RESET
tSRST
tWRST
Table 16. Running Reset
Parameter Min Max Unit
Timing Requirements
t
WRUNRST
Running RESET Pulse Width Low 4 × t
CK
ns
t
SRUNRST
Running RESET Setup Before CLKIN High 8 ns
Figure 9. Running Reset
CLKIN
RUNRSTIN
tWRUNRST tSRUNRST
ADSP-21371/ADSP-21375
Rev. D | Page 23 of 56 | April 2013
Core Timer
The following timing specification applies to FLAG3 when it is
configured as the core timer (TMREXP pin).
Interrupts
The following timing specification applies to the FLAG0,
FLAG1, and FLAG2 pins when they are configured as IRQ0,
IRQ1, and IRQ2 interrupts as well as the DAI_P20–1 and
DPI_P14–1 pins when they are configured as interrupts.
Table 17. Core Timer
Parameter Min Max Unit
Switching Characteristic
t
WCTIM
TMREXP Pulse Width 4 × t
PCLK
– 1 ns
Figure 10. Core Timer
FLAG3
(TMREXP)
tWCTIM
Table 18. Interrupts
Parameter Min Max Unit
Timing Requirement
t
IPW
IRQx Pulse Width 2 × t
PCLK
+2 ns
Figure 11. Interrupts
INTERRUPT
INPUTS
tIPW
Rev. D | Page 24 of 56 | April 2013
ADSP-21371/ADSP-21375
Timer PWM_OUT Cycle Timing
The following timing specification applies to Timer0 and
Timer1 in PWM_OUT (pulse-width modulation) mode. Timer
signals are routed to the DPI_P14–1 pins through the DPI SRU.
Therefore, the specifications provided below are valid at the
DPI_P14–1 pins.
Timer WDTH_CAP Timing
The following timing specification applies to Timer0 and
Timer1 in WDTH_CAP (pulse width count and capture) mode.
Timer signals are routed to the DPI_P14–1 pins through the
SRU. Therefore, the specifications provided below are valid at
the DPI_P14–1 pins.
Table 19. Timer PWM_OUT Timing
Parameter Min Max Unit
Switching Characteristic
t
PWMO
Timer Pulse Width Output 2 × t
PCLK
– 2 2 × (2
31
– 1) × t
PCLK
ns
Figure 12. Timer PWM_OUT Timing
PWM
OUTPUTS
tPWMO
Table 20. Timer Width Capture Timing
Parameter Min Max Unit
Timing Requirement
t
PWI
Timer Pulse Width 2 × t
PCLK
2 × (2
31
– 1) × t
PCLK
ns
Figure 13. Timer Width Capture Timing
TIMER
CAPTURE
INPUTS
tPWI
ADSP-21371/ADSP-21375
Rev. D | Page 25 of 56 | April 2013
Pin to Pin Direct Routing (DAI and DPI)
For direct pin connections only (for example, DAI_PB01_I to
DAI_PB02_O).
Table 21. DAI/DPI Pin to Pin Routing
Parameter Min Max Unit
Timing Requirement
t
DPIO
Delay DAI/DPI Pin Input Valid to DAI/DPI Output Valid 1.5 10 ns
Figure 14. DAI/DPI Pin to Pin Direct Routing
DAI_Pn
DPI_Pn
DAI_Pm
DPI_Pm
tDPIO
Rev. D | Page 26 of 56 | April 2013
ADSP-21371/ADSP-21375
Precision Clock Generator (Direct Pin Routing)
This timing is only valid when the SRU is configured such that
the precision clock generator (PCG) takes its inputs directly
from the DAI pins (via pin buffers) and sends its outputs
directly to the DAI pins. For the other cases, where the PCG’s
inputs and outputs are not directly routed to/from DAI pins (via
pin buffers) there is no timing data available. All timing param-
eters and switching characteristics apply to external DAI pins
(DAI_P01 through DAI_P20).
Table 22. Precision Clock Generator (Direct Pin Routing)
1.0 V, 200 MHz 1.2 V, 266 MHz
Parameter Min Max Min Max Unit
Timing Requirements
t
PCGIP
Input Clock Period t
PCLK
× 4 t
PCLK
× 4 ns
t
STRIG
PCG Trigger Setup Before
Falling Edge of PCG Input Clock
4.5 4.5 ns
t
HTRIG
PCG Trigger Hold After Falling
Edge of PCG Input Clock
33ns
Switching Characteristics
t
DPCGIO
PCG Output Clock and Frame
Sync Active Edge Delay After
PCG Input Clock
2.5 12.8 2.5 10 ns
t
DTRIGCLK
PCG Output Clock Delay After
PCG Trigger
2.5 + ((2.5) × t
PCGIW
) 12.8 + ((2.5) × t
PCGIW
) 2.5 + ((2.5) × t
PCGIW
) 10 + ((2.5) × t
PCGIW
)ns
t
DTRIGFS
PCG Frame Sync Delay After
PCG Trigger
2.5 + ((2.5 + D – PH)
× t
PCGIW
)
12.8 + ((2.5 + D – PH)
× t
PCGIW
)
2.5 + ((2.5 + D – PH)
× t
PCGIW
)
10 + ((2.5 + D – PH)
× t
PCGIW
)
ns
t
PCGOW
1
Output Clock Period 2 × t
PCGIW
– 1 2 × t
PCGIW
– 1 ns
D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-2137x SHARC Processor Hardware Reference, “Precision Clock Generators” chapter.
1
Normal mode of operation.
Figure 15. Precision Clock Generator (Direct Pin Routing)
DAI_Pn
DPI_Pn
PCG_TRIGx_I
DAI_Pm
DPI_Pm
PCG_EXTx_I
(CLKIN)
DAI_Py
DPI_Py
PCG_CLKx_O
DAI_Pz
DPI_Pz
PCG_FSx_O
tDTRIGFS
tDTRIGCLK
tDPCGIO
tSTRIG tHTRIG
tPCGOW
tDPCGIO
tPCGIP
ADSP-21371/ADSP-21375
Rev. D | Page 27 of 56 | April 2013
Flags
The timing specifications provided below apply to the FLAG3–0
and DPI_P14–1 pins, and the DATA31–0 pins. See Table 9 on
Page 13 for more information on flag use.
Table 23. Flags
Parameter Min Max Unit
Timing Requirement
t
FIPW
DPI_P14–1, DATA31–0, FLAG3–0
IN
Pulse Width 2 × t
PCLK
+ 3 ns
Switching Characteristic
t
FOPW
DPI_P14–1, DATA31–0, FLAG3–0
OUT
Pulse Width 2 × t
PCLK
– 2 ns
Figure 16. Flags
FLAG
INPUTS
FLAG
OUTPUTS
tFOPW
tFIPW
Rev. D | Page 28 of 56 | April 2013
ADSP-21371/ADSP-21375
SDRAM Interface Timing
Maximum SDRAM frequency for 1.2 V is 133 MHz SDCLK.
Table 24. SDRAM Interface Timing
1
1.0 V, 200 MHz 1.2 V, 266 MHz
Parameter Min Max Min Max Unit
Timing Requirements
t
SSDAT
DATA Setup Before SDCLK 0.58 0.58 ns
t
HSDAT
DATA Hold After SDCLK 2.2 2.2 ns
Switching Characteristics
t
SDCLK
SDCLK Period 10 7.5 ns
t
SDCLKH
SDCLK Width High43ns
t
SDCLKL
SDCLK Width Low 43ns
t
DCAD
Command, ADDR, Data Delay After SDCLK
2
6.4 5.3 ns
t
HCAD
Command, ADDR, Data Hold After SDCLK
2
1.3 1.3 ns
t
DSDAT
Data Disable After SDCLK 5.3 5.3 ns
t
ENSDAT
Data Enable After SDCLK 1.6 1.6 ns
1
For F
CCLK
= 133 MHz (SDCLK ratio = 1:2).
2
Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, and SDCKE.
Figure 17. SDRAM Interface Timing for 133 MHz SDCLK
SDCLK
DATA (IN)
DATA (OUT)
COMMAND/ADDR
(OUT)
tSDCLKH
tSDCLKL
tHSDAT
tSSDAT
tHCAD
tDCAD
tENSDAT
tDCAD tDSDAT
tHCAD
tSDCLK
ADSP-21371/ADSP-21375
Rev. D | Page 29 of 56 | April 2013
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries. Note that timing for ACK, DATA, RD, WR, and strobe
timing parameters only apply to asynchronous access mode.
Table 25. Memory Read—Bus Master
1.0 V, 200 MHz 1.2 V, 266 MHz
Parameter Min Max Min Max Unit
Timing Requirements
t
DAD
Address, Selects Delay to Data Valid
1, 2,
3
W + t
SDCLK
– 5.12 W + t
SDCLK
– 5.12 ns
t
DRLD
RD Low to Data Valid
1, 3
W – 3 W – 3 ns
t
SDS
Data Setup to RD High 2.2 2.2 ns
t
HDRH
Data Hold from RD High
4,
5
00ns
t
DAAK
ACK Delay from Address, Selects
2, 6
t
SCDCLK
– 11.4 + W t
SCDCLK
– 10.1 + W ns
t
DSAK
ACK Delay from RD Low
5
W – 7.25 W – 7.0 ns
Switching Characteristics
t
DRHA
Address Selects Hold After RD High RHC + 0.38 RHC + 0.38 ns
t
DARL
Address Selects to RD Low
2
t
SDCLK
– 3.8 t
SDCLK
– 3.3 ns
t
RW
RD Pulse Width W – 1.4 W – 1.4 ns
t
RWR
RD High to WR, RD, Low HI + t
SDCLK
– 0.8 HI + t
SDCLK
– 0.8 ns
W = (number of wait states specified in AMICTLx register) × t
SDCLK
HI = RHC + IC (RHC = (number of Read Hold Cycles specified in AMICTLx register) × t
SDCLK
IC = (number of idle cycles specified in AMICTLx register) × t
SDCLK
)
H = (number of hold cycles specified in AMICTLx register) × t
SDCLK
1
Data delay/setup: System must meet t
DAD
, t
DRLD
, or t
SDS.
2
The falling edge of MSx, is referenced.
3
The maximum limit of timing requirement values for t
DAD
and t
DRLD
parameters are applicable for the case where AMI_ACK is always high and when the ACK feature is not
used.
4
Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode.
5
Data hold: User must meet t
HDRH
in asynchronous access mode. See Test Conditions on Page 49 for the calculation of hold times given capacitive and dc loads.
6
ACK delay/setup: User must meet t
DAAK
, or t
DSAK
, for deassertion of ACK (low). For asynchronous assertion of ACK (high) user must meet t
DAAK
or t
DSAK
.
ADSP-21371/ADSP-21375
Rev. D | Page 31 of 56 | April 2013
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries. Note that timing for ACK, DATA, RD, WR, and strobe
timing parameters only apply to asynchronous access mode.
Table 26. Memory Write—Bus Master
1.0 V, 200 MHz 1.2 V, 266 MHz
Parameter Min Max Min Max Unit
Timing Requirements
t
DAAK
ACK Delay from Address, Selects
1, 2
t
SDCLK
– 11 + W t
SDCLK
– 10.1 + W ns
t
DSAK
ACK Delay from WR Low
1, 3
W – 7.35 W – 7.1 ns
Switching Characteristics
t
DAWH
Address, Selects to WR Deasserted
2
t
SDCLK
–4.3 + W t
SDCLK
–3.6 + W ns
t
DAWL
Address, Selects to WR Low
2
t
SDCLK
– 2.7 t
SDCLK
– 2.7 ns
t
WW
WR Pulse Width W – 1.3 W – 1.3 ns
t
DDWH
Data Setup Before WR High t
SDCLK
– 3.0 + W t
SDCLK
– 3.0 + W ns
t
DWHA
Address Hold After WR Deasserted H + 0.15 H + 0.15 ns
t
DWHD
Data Hold After WR Deasserted H + 0.02 H + 0.02 ns
t
DATRWH
Data Disable After WR Deasserted
4
t
SDCLK
– 1.37 + H t
SDCLK
+ 10.7+ H t
SDCLK
– 1.37 + H t
SDCLK
+ 4.9+ H ns
t
WWR
WR High to WR, RD Low t
SDCLK
– 1.5+ H t
SDCLK
– 1.5+ H ns
t
DDWR
Data Disable Before RD Low 2t
SDCLK
– 12 2t
SDCLK
– 5.1 ns
t
WDE
WR Low to Data Enabled t
SDCLK
– 4.1 t
SDCLK
– 4.1 ns
W = (number of wait states specified in AMICTLx register) × t
SDCLK
, H = (number of hold cycles specified in AMICTLx register) × t
SDCLK
1
ACK delay/setup: System must meet t
DAAK
, or t
DSAK
, for deassertion of ACK (low). For asynchronous assertion of ACK (high) user must meet t
DAAK
or t
DSAK
.
2
The falling edge of MSx is referenced.
3
Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode.
4
See Test Conditions on Page 49 for calculation of hold times given capacitive and dc loads.
ADSP-21371/ADSP-21375
Rev. D | Page 33 of 56 | April 2013
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) serial clock
(SCLK) width.
Serial port signals are routed to the DAI_P20–1 pins using the
SRU. Therefore, the timing specifications provided below are
valid at the DAI_P20–1 pins.
Table 27. Serial Ports—External Clock
1.0 V, 200 MHz 1.2 V, 266 MHz
Parameter Min Max Min Max Unit
Timing Requirements
t
SFSE
1
Frame Sync Setup Before SCLK
(Externally Generated Frame Sync in either Transmit
or Receive Mode)
2.8 2.5 ns
t
HFSE
1
Frame Sync Hold After SCLK
(Externally Generated Frame Sync in either Transmit
or Receive Mode)
2.5 2.5 ns
t
SDRE
1
Receive Data Setup Before Receive SCLK 3.1 2.5 ns
t
HDRE
1
Receive Data Hold After SCLK 2.5 2.5 ns
t
SCLKW
SCLK Width (t
PCLK
× 4) ÷ 2 – 1.5 (t
PCLK
× 4) ÷ 2 – 1.5 ns
t
SCLK
SCLK Period t
PCLK
× 4 t
PCLK
× 4 ns
Switching Characteristics
t
DFSE
2
Frame Sync Delay After SCLK (Internally Generated
Frame Sync in either Transmit or Receive Mode) 13.5 10.5 ns
t
HOFSE
2
Frame Sync Hold After SCLK (Internally Generated
Frame Sync in either Transmit or Receive Mode) 2 2 ns
t
DDTE
2
Transmit Data Delay After Transmit SCLK 13.9 11 ns
t
HDTE
2
Transmit Data Hold After Transmit SCLK 2 2 ns
1
Referenced to sample edge.
2
Referenced to drive edge.
Rev. D | Page 34 of 56 | April 2013
ADSP-21371/ADSP-21375
Table 28. Serial Ports—Internal Clock
1.0 V, 200 MHz 1.2 V, 266 MHz
Parameter Min Max Min Max Unit
Timing Requirements
t
SFSI
1
Frame Sync Setup Before SCLK (Externally Generated Frame
Sync in either Transmit or Receive Mode) 7 7 ns
t
HFSI
1
Frame Sync Hold After SCLK (Externally Generated Frame Sync
in either Transmit or Receive Mode) 2.5 2.5 ns
t
SDRI
1
Receive Data Setup Before SCLK 7 7 ns
t
HDRI
1
Receive Data Hold After SCLK 2.5 2.5 ns
Switching Characteristics
t
DFSI
2
Frame Sync Delay After SCLK (Internally Generated Frame Sync
in Transmit Mode)
44ns
t
HOFSI
2
Frame Sync Hold After SCLK (Internally Generated Frame Sync
in Transmit Mode)
–1.0 –1.0 ns
t
DFSIR
2
Frame Sync Delay After SCLK (Internally Generated Frame Sync
in Receive Mode)
13.5 10.7 ns
t
HOFSIR
2
Frame Sync Hold After SCLK (Internally Generated Frame Sync
in Receive Mode)
–1.0 –1.0 ns
t
DDTI
2
Transmit Data Delay After SCLK 4.6 3.6 ns
t
HDTI
2
Transmit Data Hold After SCLK –1.0 –1.0 ns
t
SCKLIW
3
Transmit or Receive SCLK Width 2 × t
PCLK
– 1.5 2 × t
PCLK
+ 1.5 2 × t
PCLK
– 1.5 2 × t
PCLK
+ 1.5 ns
1
Referenced to the sample edge.
2
Referenced to drive edge.
3
Minimum SPORT divisor register value.
ADSP-21371/ADSP-21375
Rev. D | Page 35 of 56 | April 2013
Figure 20. Serial Ports
DRIVE EDGE SAMPLE EDGE
DAI_P20–1
(DATA
CHANNEL A/B)
DAI_P20–1
(FS)
DAI_P20–1
(SCLK)
tHOFSI tHFSI
tHDRI
DATA RECEIVE—INTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
DAI_P20–1
(DATA
CHANNEL A/B)
DAI_P20–1
(FS)
DAI_P20–1
(SCLK)
tHFSI
tDDTI
DATA TRANSMIT—INTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
DAI_P20–1
(DATA
CHANNEL A/B)
DAI_P20–1
(FS)
DAI_P20–1
(SCLK)
tHOFSE
tHOFSI
tHDTI
tHFSE
tHDTE
tDDTE
DATA TRANSMIT—EXTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
DAI_P20–1
(DATA
CHANNEL A/B)
DAI_P20–1
(FS)
DAI_P20–1
(SCLK)
tHOFSE tHFSE
tHDRE
DATA RECEIVE—EXTERNAL CLOCK
tSCLKIW
tDFSI
tSFSI
tSDRI
tSCLKW
tDFSE
tSFSE
tSDRE
tDFSE
tSFSE
tSFSI
tDFSI
tSCLKIW tSCLKW
Rev. D | Page 36 of 56 | April 2013
ADSP-21371/ADSP-21375
Table 29. Serial Ports—Enable and Three-State
1.0 V, 200 MHz 1.2 V, 266 MHz
Parameter Min Max Min Max Unit
Switching Characteristics
t
DDTEN
1
Data Enable from External Transmit SCLK 2 2 ns
t
DDTTE
1
Data Disable from External Transmit SCLK 11.3 10 ns
t
DDTIN
1
Data Enable from Internal Transmit SCLK –1 –1 ns
1
Referenced to drive edge.
Figure 21. Enable and Three-State
DRIVE EDGE
DRIVE EDGE
DRIVE EDGE
tDDTIN
tDDTEN tDDTTE
DAI_P20–1
(SCLK, INT)
DAI_P20–1
(DATA
CHANNEL A/B)
DAI_P20–1
(SCLK, EXT)
DAI_P20–1
(DATA
CHANNEL A/B)
ADSP-21371/ADSP-21375
Rev. D | Page 37 of 56 | April 2013
Table 30. Serial Ports—External Late Frame Sync
1.0 V, 200 MHz 1.2 V, 266 MHz
Parameter Min Max Min Max Unit
Switching Characteristics
t
DDTLFSE
1
Data Delay from Late External Transmit Frame Sync
or External Receive Frame Sync with
MCE = 1, MFD = 0
12.7 10 ns
t
DDTENFS
1
Data Enable for MCE = 1, MFD = 0 0.5 0.5 ns
1
The t
DDTLFSE
and t
DDTENFS
parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0.
Figure 22. External Late Frame Sync
1
1
This figure reflects changes made to support left-justified sample pair mode.
DRIVE SAMPLE
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
2ND BIT
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DAI_P20–1
(DATA CHANNEL
A/B)
1ST BIT
DRIVE
tDDTE/I
tHDTE/I
tDDTLFSE
tDDTENFS
tSFSE/I
DRIVE SAMPLE
LATE EXTERNAL TRANSMIT FS
2ND BIT
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DAI_P20–1
(DATA CHANNEL
A/B)
1ST BIT
DRIVE
tDDTE/I
tHDTE/I
tDDTLFSE
tDDTENFS
tSFSE/I
tHFSE/I
tHFSE/I
Rev. D | Page 38 of 56 | April 2013
ADSP-21371/ADSP-21375
Input Data Port (IDP)
The timing requirements for the IDP are given in Table 31. IDP
signals are routed to the DAI_P20–1 pins using the SRU. There-
fore, the timing specifications provided below are valid at the
DAI_P20–1 pins.
Table 31. Input Data Port (IDP)
1.0 V, 200 MHz 1.2 V, 266 MHz
Parameter Min Max Min Max Unit
Timing Requirements
t
SISFS
1
Frame Sync Setup Before Serial Clock Rising Edge 4.95 3.8 ns
t
SIHFS
1
Frame Sync Hold After Serial Clock Rising Edge 2.5 2.5 ns
t
SISD
1
Data Setup Before Serial Clock Rising Edge 3.35 2.5 ns
t
SIHD
1
Data Hold After Serial Clock Rising Edge 2.5 2.5 ns
t
IDPCLKW
Clock Width (t
PCLK
× 4) ÷ 2 – 1 (t
PCLK
× 4) ÷ 2 – 1 ns
t
IDPCLK
Clock Period t
PCLK
× 4 t
PCLK
× 4 ns
1
The data, serial clock, and frame sync signals can come from any of the DAI pins. Serial clock and frame sync can also come via PCG or SPORTs. PCG’s input can be either
CLKIN or any of the DAI pins.
Figure 23. IDP Master Timing
DAI_P20–1
(SCLK)
SAMPLE EDGE
DAI_P20–1
(FS)
DAI_P20–1
(SDATA)
tIDPCLK
tIDPCLKW
tSISFS tSIHFS
tSIHD
tSISD
ADSP-21371/ADSP-21375
Rev. D | Page 39 of 56 | April 2013
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table 32. PDAP is the parallel mode operation of Channel 0 of
the IDP. For details on the operation of the PDAP, see the
PDAP chapter of the ADSP-2137x SHARC Processor Hardware
Reference.
Note that the 20-bits of external PDAP data can be provided
through the external port DATA31–12 pins. On the
ADSP-21375 processors, PDAP can not be multiplexed on the
external port (since only DATA15–0). Use the SRU DAI
instead.
Table 32. Parallel Data Acquisition Port (PDAP)
Parameter Min Max Unit
Timing Requirements
t
SPCLKEN
1
PDAP_CLKEN Setup Before PDAP_CLK Sample Edge 2.5 ns
t
HPCLKEN
1
PDAP_CLKEN Hold After PDAP_CLK Sample Edge 2.5 ns
t
PDSD
1
PDAP_DAT Setup Before Serial Clock PDAP_CLK Sample Edge 3.85 ns
t
PDHD
1
PDAP_DAT Hold After Serial Clock PDAP_CLK Sample Edge 2.5 ns
t
PDCLKW
Clock Width (t
PCLK
× 4) ÷ 2 – 3 ns
t
PDCLK
Clock Period t
PCLK
× 4 ns
Switching Characteristics
t
PDHLDD
Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word 2 × t
PCLK
+ 3 ns
t
PDSTRIB
PDAP Strobe Pulse Width 2 × t
PCLK
– 1 ns
1
Data source pins are DATA31–12 or DAI pins. Source pins for serial clock and frame sync are: 1) DATA11–10 pins, 2) DAI pins.
Figure 24. PDAP Timing
DAI_P20–1
(PDAP_CLK)
SAMPLE EDGE
DAI_P20–1
(PDAP_HOLD)
DAI_P20–1
(PDAP_STROBE)
tPDSTRB
tPDHLDD
tPDHD
tPDSD
tSPHOLD tHPHOLD
tPDCLK
tPDCLKW
DAI_P20–1/
ADDR23–4
(PDAP_DATA)
Rev. D | Page 40 of 56 | April 2013
ADSP-21371/ADSP-21375
Pulse-Width Modulation Generators (PWM)
For the ADSP-21371, the following timing specifications apply
when the DATA31–16 pins are configured as PWM.
Pulse-width modulation generator information does not apply
to the ADSP-21375.
Table 33. Pulse-Width Modulation (PWM) Timing
Parameter Min Max Unit
Switching Characteristics
t
PWMW
PWM Output Pulse Width t
PCLK
– 2.5 (2
16
– 2) × t
PCLK
ns
t
PWMP
PWM Output Period 2 × t
PCLK
– 2.5 (2
16
– 1) × t
PCLK
ns
Figure 25. PWM Timing
PWM
OUTPUTS
tPWMW
tPWMP
ADSP-21371/ADSP-21375
Rev. D | Page 41 of 56 | April 2013
S/PDIF Transmitter
For the ADSP-21371, serial data input to the S/PDIF transmitter
can be formatted as left-justified, I
2
S, or right-justified with
word widths of 16-, 18-, 20-, or 24-bits. The following sections
provide timing for the transmitter.
S/PDIF Transmitter-Serial Input Waveforms
Figure 26 shows the right-justified mode. LRCLK is high for the
left channel and low for the right channel. Data is valid on the
rising edge of serial clock. The MSB is delayed 12-bit clock peri-
ods (in 20-bit output mode) or 16-bit clock periods (in 16-bit
output mode) from an LRCLK transition, so that when there are
64 serial clock periods per LRCLK period, the LSB of the data
will be right-justified to the next LRCLK transition.
S/PDIF transmitter information does not apply to the
ADSP-21375.
Figure 27 shows the default I
2
S-justified mode. LRCLK is low
for the left channel and high for the right channel. Data is valid
on the rising edge of serial clock. The MSB is left-justified to an
LRCLK transition but with a single serial clock period delay.
Figure 28 shows the left-justified mode. LRCLK is high for the
left channel and low for the right channel. Data is valid on the
rising edge of serial clock. The MSB is left-justified to an LRCLK
transition with no MSB delay.
Figure 26. Right-Justified Mode
Figure 27. I
2
S-Justified Mode
Figure 28. Left-Justified Mode
MSB
LEFT/RIGHT CHANNEL
LSB LSBMSB–1 MSB–2 LSB+2 LSB+1
DAI_P20–1
FS
DAI_P20–1
SCLK
DAI_P20–1
SDATA
tRJD
MSB
LEFT/RIGHT CHANNEL
LSBMSB–1 MSB–2 LSB+2 LSB+1
DAI_P20–1
FS
DAI_P20–1
SCLK
DAI_P20–1
SDATA
tI2SD
MSB
LEFT/RIGHT CHANNEL
LSBMSB–1 MSB–2 LSB+2 LSB+1
DAI_P20–1
FS
DAI_P20–1
SCLK
DAI_P20–1
SDATA
tLJD
Rev. D | Page 42 of 56 | April 2013
ADSP-21371/ADSP-21375
S/PDIF Transmitter Input Data Timing
The timing requirements for the S/PDIF transmitter are given
in Table 34. Input signals are routed to the DAI_P20–1 pins
using the SRU. Therefore, the timing specifications provided
below are valid at the DAI_P20–1 pins.
Oversampling Clock (HFCLK) Switching Characteristics
The S/PDIF transmitter has an oversampling clock. This
HFCLK input is divided down to generate the biphase clock.
Table 34. S/PDIF Transmitter Input Data Timing
1.0 V, 200 MHz 1.2 V, 266 MHz
Parameter Min Max Min Max Unit
Timing Requirements
t
SISFS
1
Frame Sync Setup Before Serial Clock Rising Edge 3 3 ns
t
SIHRS
1
Frame Sync Hold After Serial Clock Rising Edge 3 3 ns
t
SISD
1
Data Setup Before Serial Clock Rising Edge 3.2 3 ns
t
SIHD
1
Data Hold After Serial Clock Rising Edge 3 3 ns
t
SITXCLKW
Transmit Clock Width 9 9 ns
t
SITXCLK
Transmit Clock Period 20 20 ns
t
SISCLKW
Clock Width 36 36 ns
t
SISCLK
Clock Period 80 80 ns
1
The data, serial clock, and frame sync can come from any of the DAI pins. Serial clock and frame sync can also come via PCG or SPORTs. PCG’s input can be either CLKIN
or any of the DAI pins.
Figure 29. S/PDIF Transmitter Input Timing
SAMPLE EDGE
DAI_P20–1
(TxCLK)
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DAI_P20–1
(SDATA)
tSITXCLKW tSITXCLK
tSISCLKW
tSISCLK
tSISFS tSIHFS
tSISD tSIHD
Table 35. Oversampling Clock HFxCLK) Switching Characteristics
Parameter Max Unit
HFCLK Frequency for HFCLK = 384 × Frame Sync Oversampling Ratio × Frame Sync <= 1/t
SITXCLK
MHz
HFCLK Frequency for HFCLK = 256 × Frame Sync 49.2 MHz
Frame Rate (FS) 192.0 kHz
ADSP-21371/ADSP-21375
Rev. D | Page 43 of 56 | April 2013
S/PDIF Receiver
For the ADSP-21371, the following section describes timing as it
relates to the S/PDIF receiver.
Internal Digital PLL Mode
In the internal digital phase-locked loop mode the internal PLL
(digital PLL) generates the 512 × Frame Sync clock. The S/PDIF
receiver information does not apply to the ADSP-21375.
Table 36. S/PDIF Receiver Internal Digital PLL Mode Timing
1.0 V, 200 MHz 1.2 V, 266 MHz
Parameter Min Max Min Max Unit
Switching Characteristics
t
DFSI
LRCLK Delay After Serial Clock 5 5 ns
t
HOFSI
LRCLK Hold After Serial Clock –2 –2 ns
t
DDTI
Transmit Data Delay After Serial Clock 5 5 ns
t
HDTI
Transmit Data Hold After Serial Clock –2 –2 ns
t
SCLKIW
1
Transmit Serial Clock Width 52 38.5 ns
1
Serial lock frequency is 64 × Frame Sync where FS = the frequency of LRCLK.
Figure 30. S/PDIF Receiver Internal Digital PLL Mode Timing
DAI_P20–1
(SCLK)
SAMPLE EDGE
DAI_P20–1
(FS)
DAI_P20–1
(DATA CHANNEL
A/B)
DRIVE EDGE
tSCLKIW
tDFSI
tHOFSI
tDDTI
tHDTI
Rev. D | Page 44 of 56 | April 2013
ADSP-21371/ADSP-21375
SPI Interface—Master
The processor contains two SPI ports. Both primary and sec-
ondary are available through DPI only. The timing provided in
Table 37 and Table 38 applies to both.
Table 37. SPI Interface Protocol—Master Switching and Timing Specifications
Parameter Min Max Unit
Timing Requirements
t
SSPIDM
Data Input Valid To SPICLK Edge (Data Input Setup Time) 8.2 ns
t
HSPIDM
SPICLK Last Sampling Edge To Data Input Not Valid 2 ns
Switching Characteristics
t
SPICLKM
Serial Clock Cycle 8 × t
PCLK
– 2 ns
t
SPICHM
Serial Clock High Period 4 × t
PCLK
– 2 ns
t
SPICLM
Serial Clock Low Period 4 × t
PCLK
– 2 ns
t
DDSPIDM
SPICLK Edge to Data Out Valid (Data Out Delay Time) 2.5 ns
t
HDSPIDM
SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 4 × t
PCLK
– 2 ns
t
SDSCIM
DPI Pin (SPI Device Select) Low to First SPICLK Edge 4 × t
PCLK
– 2 ns
t
HDSM
Last SPICLK Edge to DPI Pin (SPI Device Select) High 4 × t
PCLK
– 2 ns
t
SPITDM
Sequential Transfer Delay 4 × t
PCLK
– 1 ns
Figure 31. SPI Master Timing
tSPICHM
tSDSCIM tSPICLM tSPICLKM tHDSM tSPITDM
tDDSPIDM
tHSPIDM
tSSPIDM
DPI
(OUTPUT)
MOSI
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
MISO
(INPUT)
CPHASE = 1
CPHASE = 0
tHDSPIDM
tHSPIDM
tHSPIDM
tSSPIDM tSSPIDM
tDDSPIDM
tHDSPIDM
SPICLK
(CP = 0,
CP = 1)
(OUTPUT)
ADSP-21371/ADSP-21375
Rev. D | Page 45 of 56 | April 2013
SPI Interface—Slave
Table 38. SPI Interface Protocol—Slave Switching and Timing Specifications
1.0 V, 200 MHz 1.2 V, 266 MHz
Parameter Min Max Min Max Unit
Timing Requirements
t
SPICLKS
Serial Clock Cycle 4 × t
PCLK
– 2 4 × t
PCLK
– 2 ns
t
SPICHS
Serial Clock High Period 2 × t
PCLK
– 2 2 × t
PCLK
– 2 ns
t
SPICLS
Serial Clock Low Period 2 × t
PCLK
– 2 2 × t
PCLK
– 2 ns
t
SDSCO
SPIDS Assertion to First SPICLK Edge
CPHASE = 0
CPHASE = 1
2 × t
PCLK
2 × t
PCLK
2 × t
PCLK
2 × t
PCLK
ns
t
HDS
Last SPICLK Edge to SPIDS Not Asserted (CPHASE=0) 2 × t
PCLK
2 × t
PCLK
ns
t
SSPIDS
Data Input Valid to SPICLK edge (Data Input Set-up Time) 2 2 ns
t
HSPIDS
SPICLK Last Sampling Edge to Data Input Not Valid 2 2 ns
t
SDPPW
SPIDS Deassertion Pulse Width (CPHASE=0) 2 × t
PCLK
2 × t
PCLK
ns
Switching Characteristics
t
DSOE
SPIDS Assertion to Data Out Active 0 6.8 0 6.8 ns
t
DSDHI
SPIDS Deassertion to Data High Impedance 0 9.9 0 6.8 ns
t
DDSPIDS
SPICLK Edge to Data Out Valid (Data Out Delay Time) 9.5 9.5 ns
t
HDSPIDS
SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 2 × t
PCLK
2 × t
PCLK
ns
t
DSOV
SPIDS Assertion to Data Out Valid (CPHASE = 0) 5 × t
PCLK
5 × t
PCLK
ns
Figure 32. SPI Slave Timing
tSPICHS tSPICLS tSPICLKS tHDS tSDPPW
tSDSCO
tDSOE
tDDSPIDS
tDDSPIDS
tDSDHI
tHDSPIDS
tHSPIDS
tSSPIDS
tDSDHI
tDSOV
tHSPIDS
tHDSPIDS
SPIDS
(INPUT)
MISO
(OUTPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
MOSI
(INPUT)
CPHASE = 1
CPHASE = 0
SPICLK
(CP = 0,
CP = 1)
(INPUT)
tSSPIDS
Rev. D | Page 46 of 56 | April 2013
ADSP-21371/ADSP-21375
Universal Asynchronous Receiver-Transmitter
(UART) Port—Receive and Transmit Timing
Figure 33 describes UART port receive and transmit operations.
The maximum baud rate is PCLK/16 where PCLK = 1/t
PCLK
. As
shown in Figure 33 there is some latency between the
generation of internal UART interrupts and the external data
operations. These latencies are negligible at the data transmis-
sion rates for the UART.
Table 39. UART Port
Parameter Min Max Unit
Timing Requirement
t
TXD
1
Incoming Data Pulse Width 16t
PCLK
–1 ns
Switching Characteristic
t
RXD
1
Incoming Data Pulse Width 16t
PCLK
–1 ns
1
UART signals TXD and RXD are routed through DPI P14-1 pins using the SRU.
Figure 33. UART Port—Receive and Transmit Timing
DPI_P14–1
[RxD]
DPI_P14–1
[TxD]
DATA (5–8)
DATA (5–8)
INTERNAL
UART RECEIVE
INTERRUPT
INTERNAL
UART TRANSMIT
INTERRUPT
UART RECEIVE BIT SET BY DATA STOP;
CLEARED BY FIFO READ
UART TRANSMIT BIT SET BY PROGRAM;
CLEARED BY WRITE TO TRANSMIT
START
STOP
STOP (1–2)
tRXD
tTXD
RECEIVE
TRANSMIT
ADSP-21371/ADSP-21375
Rev. D | Page 47 of 56 | April 2013
TWI Controller Timing
Table 40 and Figure 34 provide timing information for the TWI
interface. Input signals (SCL, SDA) are routed to the
DPI_P14–1 pins using the SRU. Therefore, the timing specifica-
tions provided below are valid at the DPI_P14–1 pins.
Table 40. Characteristics of the SDA and SCL Bus Lines for F/S-Mode TWI Bus Devices
1
Parameter
Standard Mode Fast Mode
Min Max Min Max Unit
f
SCL
SCL Clock Frequency 0 100 0 400 kHz
t
HDSTA
Hold Time (repeated) Start Condition. After This
Period, the First Clock Pulse is Generated. 4.0 0.6 μs
t
LOW
Low Period of the SCL Clock 4.7 1.3 μs
t
HIGH
High Period of the SCL Clock 4.0 0.6 μs
t
SUSTA
Setup Time for a Repeated Start Condition 4.7 0.6 μs
t
HDDAT
Data Hold Time for TWI-Bus Devices 0 0 μs
t
SUDAT
Data Setup Time 250 100 ns
t
SUSTO
Setup Time for Stop Condition 4.0 0.6 μs
t
BUF
Bus Free Time Between a Stop and Start Condition 4.7 1.3 μs
t
SP
Pulse Width of Spikes Suppressed By the Input Filter N/A N/A 0 50 ns
1
All values referred to V
IHmin
and V
ILmax
levels. For more information, see Electrical Characteristics on page 17.
Figure 34. Fast and Standard Mode Timing on the TWI Bus
PSS Sr
DPI_P14–1
SDA
DPI_P14–1
SCL
tBUF
tSUSTO
tSP
tSUSTA
tHIGH
tHDDAT
tHDSTA
tHDSTA
tSUDAT
tLOW
Rev. D | Page 48 of 56 | April 2013
ADSP-21371/ADSP-21375
JTAG Test Access Port and Emulation
Table 41. JTAG Test Access Port and Emulation
Parameter Min Max Unit
Timing Requirements
t
TCK
TCK Period t
CK
ns
t
STAP
TDI, TMS Setup Before TCK High 5 ns
t
HTAP
TDI, TMS Hold After TCK High 6 ns
t
SSYS
1
System Inputs Setup Before TCK High 7 ns
t
HSYS
1
System Inputs Hold After TCK High 18 ns
t
TRSTW
TRST Pulse Width 4 × t
CK
ns
Switching Characteristics
t
DTDO
TDO Delay from TCK Low 7 ns
t
DSYS
2
System Outputs Delay After TCK Low t
CK
2 + 7 ns
1
System Inputs = ADDR15–0, CLKCFG1–0, RESET, BOOT_CFG1–0, DAI_Px, and FLAG3–0.
2
System Outputs = DAI_Px, ADDR15–0, RD, WR, FLAG3–0, EMU, and ALE.
Figure 35. IEEE 1149.1 JTAG Test Access Port
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
tTCK
tSTAP tHTAP
tDTDO
tSSYS tHSYS
tDSYS
ADSP-21371/ADSP-21375
Rev. D | Page 49 of 56 | April 2013
OUTPUT DRIVE CURRENTS
Figure 36 shows typical I-V characteristics for the output driv-
ers of the processors. The curves represent the current drive
capability of the output drivers as a function of output voltage.
TEST CONDITIONS
The ac signal specifications (timing parameters) appear in
Table 15 on Page 22 through Table 41 on Page 48. These include
output disable time, output enable time, and capacitive loading.
The timing specifications for the SHARC apply for the voltage
reference levels in Figure 37.
Timing is measured on signals when they cross the 1.5 V level as
described in Figure 38. All delays (in nanoseconds) are mea-
sured between the point that the first signal reaches 1.5 V and
the point that the second signal reaches 1.5 V.
CAPACITIVE LOADING
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 37). Figure 41 shows graphically
how output delays and holds vary with load capacitance. The
graphs of Figure 39, Figure 40, and Figure 41 may not be linear
outside the ranges shown for Typical Output Delay vs. Load
Capacitance and Typical Output Rise Time (20% to 80%,
V = Min) vs. Load Capacitance.
Figure 36. Typical Drive at Junction Temperature
Figure 37. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Figure 38. Voltage Reference Levels for AC Measurements
SWEEP (VDDEXT)VOLTAGE(V)
-
20
03.50.5 1.0 1.5 2.0 2.5 3.0
0
-
40
-
30
20
40
-
10
SOURCE(V
DDEXT
)CURRENT(mA)
VOL
3.11V, 125°C
3.3V, 25°C
3.47V,
-
45°C
VOH
30
10
3.11V, 125°C
3.3V, 25°C
3.47V,
-
45°C
TO
OUTPUT
PIN
ȍ
VLOAD
30pF
INPUT
OR
OUTPUT
1.5V 1.5V
Figure 39. Typical Output Rise/Fall Time (20% to 80%,
V
DDEXT
= Max)
Figure 40. Typical Output Rise/Fall Time (20% to 80%,
V
DDEXT
= Min)
LOAD CAPACITANCE (pF)
8
0
0100 250
12
4
2
10
6
RISEANDFALLTIMES(ns)
20015050
FALL
y = 0.0467x + 1.6323
y = 0.045x + 1.524
RISE
LOAD CAPACITANCE (pF)
12
0 50 100 150 200 250
10
8
6
4
RISEANDFALLTIMES(ns)
2
0
RISE
FALL
y = 0.049x + 1.5105
y=0.0482x + 1.4604
Rev. D | Page 50 of 56 | April 2013
ADSP-21371/ADSP-21375
THERMAL CHARACTERISTICS
The processor is rated for performance over the temperature
range specified in Operating Conditions on Page 16.
Table 42 airflow measurements comply with JEDEC standards
JESD51-2 and JESD51-6 and the junction-to-board measure-
ment complies with JESD51-8. Test board design complies with
JEDEC standard JESD51-7 (LQFP_EP). The junction-to-case
measurement complies with MIL- STD-883. All measurements
use a 2S2P JEDEC test board.
To determine the junction temperature of the device while on
the application PCB, use
where:
T
J
= junction temperature C
T
CASE
= case temperature (C) measured at the top center of the
package
JT
= junction-to-top (of package) characterization parameter
is the Typical value from Table 42.
P
D
= power dissipation
Values of
JA
are provided for package comparison and PCB
design considerations.
JA
can be used for a first order approxi-
mation of T
J
by the equation
where:
T
A
= ambient temperature C
Values of
JC
are provided for package comparison and PCB
design considerations when an external heatsink is required.
Values of
JB
are provided for package comparison and PCB
design considerations. Note that the thermal characteristics val-
ues provided in Table 42 are modeled values.
Figure 41. Typical Output Delay or Hold vs. Load Capacitance
(at Ambient Temperature)
LOAD CAPACITANCE (pF)
0 20050 100 150
10
8
OUTPUTDELAYORHOLD(ns)
-4
6
0
4
2
-2
Y=0.0488X - 1.5923
TJTCASE
JT PD
+=
TJTA
JA PD
+=
Table 42. Thermal Characteristics for 208-Lead LQFP
E_PAD (With Exposed Pad Soldered to PCB)
Parameter Condition Typical Unit
JA
Airflow = 0 m/s 17.1 C/W
JMA
Airflow = 1 m/s 14.7 C/W
JMA
Airflow = 2 m/s 14.0 C/W
JC
9.6 C/W
JT
Airflow = 0 m/s 0.23 C/W
JMT
Airflow = 1 m/s 0.39 C/W
JMT
Airflow = 2 m/s 0.45 C/W
JB
Airflow = 0 m/s 11.5 C/W
JMB
Airflow = 1 m/s 11.2 C/W
JMB
Airflow = 2 m/s 11.0 C/W
ADSP-21371/ADSP-21375
Rev. D | Page 51 of 56 | April 2013
208-LEAD LQFP_EP PINOUT
Table 43. ADSP-21371, 208-Lead LQFP_EP Pin Assignment (Numerical by Lead Number)
Pin No. Signal Pin No. Signal Pin No. Signal Pin No. Signal
1V
DDINT
53 V
DDINT
105 V
DDINT
157 V
DDINT
2 DATA28 54 GND 106 GND 158 V
DDINT
3DATA27 55 V
DDEXT
107 V
DDEXT
159 GND
4 GND 56 ADDR0 108 SDCAS 160 V
DDINT
5V
DDEXT
57 ADDR2 109 SDRAS 161 V
DDINT
6 DATA26 58 ADDR1 110 SDCKE 162 V
DDINT
7 DATA25 59 ADDR4 111 SDWE 163 TDI
8 DATA24 60 ADDR3 112 WR 164 TRST
9 DATA23 61 ADDR5 113 SDA10 165 TCK
10 GND 62 GND 114 GND 166 GND
11 V
DDINT
63 V
DDINT
115 V
DDEXT
167 V
DDINT
12 DATA22 64 GND 116 SDCLK 168 TMS
13 DATA21 65 V
DDEXT
117 GND 169 CLK_CFG0
14 DATA20 66 ADDR6 118 V
DDINT
170 BOOT_CFG0
15 V
DDEXT
67 ADDR7 119 RD 171 CLK_CFG1
16 GND 68 ADDR8 120 ACK 172 EMU
17 DATA19 69 ADDR9 121 FLAG3 173 BOOT_CFG1
18 DATA18 70 ADDR10 122 FLAG2 174 TDO
19 V
DDINT
71 GND 123 FLAG1 175 DAI_P4 (SFS0)
20 GND 72 V
DDINT
124 FLAG0 176 DAI_P2 (SD0B)
21 DATA17 73 GND 125 DAI_P20 (SFS5) 177 DAI_P3 (SCLK0)
22 V
DDINT
74 V
DDEXT
126 GND 178 DAI_P1 (SD0A)
23 GND 75 ADDR11 127 V
DDINT
179 V
DDEXT
24 V
DDINT
76 ADDR12 128 GND 180 GND
25 GND 77 ADDR13 129 V
DDEXT
181 V
DDINT
26 DATA16 78 GND 130 DAI_P19 (SCLK5) 182 GND
27 DATA15 79 V
DDINT
131 DAI_P18 (SD5B) 183 DPI_P14 (TIMER1)
28 DATA14 80 NC 132 DAI_P17 (SD5A) 184 DPI_P13 (TIMER0)
29 DATA13 81 NC 133 DAI_P16 (SD4B) 185 DPI_P12 (TWI_CLK)
30 DATA12 82 GND 134 DAI_P15 (SD4A) 186 DPI_P11 (TWI_DATA)
31 V
DDEXT
83 CLKIN 135 DAI_P14 (SFS3) 187 DPI_P10 (UART0RX)
32 GND 84 XTAL 136 DAI_P13 (SCLK3) 188 DPI_P09 (UART0TX)
33 V
DDINT
85 V
DDEXT
137 DAI_P12 (SD3B) 189 DPI_P08 (SPIFLG3)
34 GND 86 GND 138 V
DDINT
190 DPI_P07 (SPIFLG2)
35 DATA11 87 V
DDINT
139 V
DDEXT
191 V
DDEXT
36 DATA10 88 ADDR14 140 GND 192 GND
37 DATA9 89 GND 141 V
DDINT
193 V
DDINT
38 DATA8 90 V
DDEXT
142 GND 194 GND
39 DATA7 91 ADDR15 143 DAI_P11 (SD3A) 195 DPI_P06 (SPIFLG1)
40 DATA6 92 ADDR16 144 DAI_P10 (SD2B) 196 DPI_P05 (SPIFLG0)
41 V
DDEXT
93 ADDR17 145 DAI_P8 (SFS1) 197 DPI_P04 (SPIDS)
42 GND 94 ADDR18 146 DAI_P9 (SD2A) 198 DPI_P03 (SPICLK)
43 V
DDINT
95 GND 147 DAI_P6 (SD1B) 199 DPI_P01 (SPIMOSI)
44 DATA4 96 V
DDEXT
148 DAI_P7 (SCLK1) 200 DPI_P02 (SPIMISO)
Rev. D | Page 52 of 56 | April 2013
ADSP-21371/ADSP-21375
45 DATA5 97 ADDR19 149 DAI_P5 (SD1A) 201 RESETOUT/
RUNRSTIN
46 DATA2 98 ADDR20 150 V
DDEXT
202 RESET
47 DATA3 99 ADDR21 151 GND 203 V
DDEXT
48 DATA0 100 ADDR23 152 V
DDINT
204 GND
49 DATA1 101 ADDR22 153 GND 205 DATA30
50 V
DDEXT
102 MS1 154 V
DDINT
206 DATA31
51 GND 103 MS0 155 GND 207 DATA29
52 V
DDINT
104 V
DDINT
156 V
DDINT
208 V
DDINT
Table 43. ADSP-21371, 208-Lead LQFP_EP Pin Assignment (Numerical by Lead Number) (Continued)
Pin No. Signal Pin No. Signal Pin No. Signal Pin No. Signal
ADSP-21371/ADSP-21375
Rev. D | Page 53 of 56 | April 2013
Table 44. ADSP-21375, 208-Lead LQFP_EP Pin Assignment (Numerical by Lead Number)
Pin No. Signal Pin No. Signal Pin No. Signal Pin No. Signal
1V
DDINT
53 V
DDINT
105 V
DDINT
157 V
DDINT
2NC 54GND 106GND 158V
DDINT
3NC 55V
DDEXT
107 V
DDEXT
159 GND
4 GND 56 ADDR0 108 SDCAS 160 V
DDINT
5V
DDEXT
57 ADDR2 109 SDRAS 161 V
DDINT
6NC 58ADDR1 110SDCKE 162V
DDINT
7NC 59ADDR4 111SDWE 163 TDI
8NC 60ADDR3 112WR 164 TRST
9 NC 61 ADDR5 113 SDA10 165 TCK
10 GND 62 GND 114 GND 166 GND
11 V
DDINT
63 V
DDINT
115 V
DDEXT
167 V
DDINT
12 NC 64 GND 116 SDCLK 168 TMS
13 NC 65 V
DDEXT
117 GND 169 CLK_CFG0
14 NC 66 ADDR6 118 V
DDINT
170 BOOT_CFG0
15 NC 67 ADDR7 119 RD 171 CLK_CFG1
16 NC 68 ADDR8 120 ACK 172 EMU
17 NC 69 ADDR9 121 FLAG3 173 BOOT_CFG1
18 NC 70 ADDR10 122 FLAG2 174 TDO
19 NC 71 GND 123 FLAG1 175 DAI_P4 (SFS0)
20 NC 72 V
DDINT
124 FLAG0 176 DAI_P2 (SD0B)
21 NC 73 GND 125 DAI_P20 (SFS5) 177 DAI_P3 (SCLK0)
22 V
DDINT
74 V
DDEXT
126 GND 178 DAI_P1 (SD0A)
23 GND 75 ADDR11 127 V
DDINT
179 V
DDEXT
24 V
DDINT
76 ADDR12 128 GND 180 GND
25 GND 77 ADDR13 129 V
DDEXT
181 V
DDINT
26 NC 78 GND 130 DAI_P19 (SCLK5) 182 GND
27 DATA15 79 V
DDINT
131 DAI_P18 (SD5B) 183 DPI_P14 (TIMER1)
28 DATA14 80 NC 132 DAI_P17 (SD5A) 184 DPI_P13 (TIMER0)
29 DATA13 81 NC 133 DAI_P16 (SD4B) 185 DPI_P12 (TWI_CLK)
30 DATA12 82 GND 134 DAI_P15 (SD4A) 186 DPI_P11 (TWI_DATA)
31 V
DDEXT
83 CLKIN 135 DAI_P14 (SFS3) 187 DPI_P10 (UART0RX)
32 GND 84 XTAL 136 DAI_P13 (SCLK3) 188 DPI_P09 (UART0TX)
33 V
DDINT
85 V
DDEXT
137 DAI_P12 (SD3B) 189 DPI_P08 (SPIFLG3)
34 GND 86 GND 138 V
DDINT
190 DPI_P07 (SPIFLG2)
35 DATA11 87 V
DDINT
139 V
DDEXT
191 V
DDEXT
36 DATA10 88 ADDR14 140 GND 192 GND
37 DATA9 89 GND 141 V
DDINT
193 V
DDINT
38 DATA8 90 V
DDEXT
142 GND 194 GND
39 DATA7 91 ADDR15 143 DAI_P11 (SD3A) 195 DPI_P06 (SPIFLG1)
40 DATA6 92 ADDR16 144 DAI_P10 (SD2B) 196 DPI_P05 (SPIFLG0)
41 V
DDEXT
93 ADDR17 145 DAI_P8 (SFS1) 197 DPI_P04 (SPIDS)
42 GND 94 ADDR18 146 DAI_P9 (SD2A) 198 DPI_P03 (SPICLK)
43 V
DDINT
95 GND 147 DAI_P6 (SD1B) 199 DPI_P01 (SPIMOSI)
44 DATA4 96 V
DDEXT
148 DAI_P7 (SCLK1) 200 DPI_P02 (SPIMISO)
Rev. D | Page 54 of 56 | April 2013
ADSP-21371/ADSP-21375
45 DATA5 97 ADDR19 149 DAI_P5 (SD1A) 201 RESETOUT/
RUNRSTIN
46 DATA2 98 ADDR20 150 V
DDEXT
202 RESET
47 DATA3 99 ADDR21 151 GND 203 V
DDEXT
48 DATA0 100 ADDR23 152 V
DDINT
204 GND
49 DATA1 101 ADDR22 153 GND 205 DATA30
50 V
DDEXT
102 MS1 154 V
DDINT
206 DATA31
51 GND 103 MS0 155 GND 207 DATA29
52 V
DDINT
104 V
DDINT
156 V
DDINT
208 V
DDINT
Table 44. ADSP-21375, 208-Lead LQFP_EP Pin Assignment (Numerical by Lead Number) (Continued)
Pin No. Signal Pin No. Signal Pin No. Signal Pin No. Signal
ADSP-21371/ADSP-21375
Rev. D | Page 55 of 56 | April 2013
PACKAGE DIMENSIONS
The processors are available in a 208-lead RoHS compliant
LQFP_EP package.
Figure 42. 208-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP]
(SW-208-1)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MS-026-BJB-HD
*NOTE:
THE EXPOSED PAD IS REQUIRED TO BE ELECTRICALLY AND THERMALLY CONNECTED TO GND.
THIS SHOULD BE IMPLEMENTED BY SOLDERING THE EXPOSED PAD TO A GND PCB LAND THAT IS THE SAME SIZE
AS THE EXPOSED PAD. THE GND PCB LAND SHOULD BE ROBUSTLY CONNECTED TO THE GND PLANE IN THE PCB
WITH AN ARRAY OF THERMAL VIAS FOR BEST PERFORMANCE.
0.15
0.10
0.05 0.08
COPLANARITY
0.20
0.15
0.09
1.45
1.40
1.35
7°
3.5°
0°
VIEW A
ROTATED 90° CCW
0.27
0.22
0.17
0.75
0.60
0.45
0.50
BSC
LEAD PITCH
28.10
28.00 SQ
27.90
30.20
30.00 SQ
29.80
TOP VIEW
(PINS DOWN)
BOTTOM VIEW
(PINS UP)
*EXPOSED
PAD
1
52
53
52
53
105
104
105
104
156
208
1
208
157
156
157
PIN 1
1.60 MAX
1.00 REF
SEATING
PLANE
VIEW A
8.890
REF
8.712
REF
25.50
REF
Rev. D | Page 56 of 56 | April 2013
ADSP-21371/ADSP-21375
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07170-0-4/13(D)
AUTOMOTIVE PRODUCTS
Some ADSP-21371/ADSP-21375 models are available for automotive applications with controlled manufacturing. Note that this special
model may have specifications that differ from the general release models.
The automotive grade products shown in Table 45 are available for use in automotive applications. Contact your local ADI account repre-
sentative or authorized ADI product distributor for specific product ordering information. Note that all automotive products are RoHS
compliant.
ORDERING GUIDE
Table 45. Automotive Products
Model
Temperature
Range
1
1
Referenced temperature is ambient temperature.
Instruction
Rate
On-Chip
SRAM ROM Package Description Package Option
AD21371WBSWZ2xx –40ºC to 85ºC 266 MHz 1M bit 4M bit 208-Lead LQFP_EP SW-208-1
AD21371WYSWZ1xx –40ºC to 105ºC 200 MHz 1M bit 4M bit 208-Lead LQFP_EP SW-208-1
AD21375WBSWZ2xx –40ºC to 85ºC 266 MHz 0.5M bit 2M bit 208-Lead LQFP_EP SW-208-1
AD21375WYSWZ1xx –40ºC to 105ºC 200 MHz 0.5M bit 2M bit 208-Lead LQFP_EP SW-208-1
Model Notes
Temperature
Range
1
1
Referenced temperature is ambient temperature.
Instruction
Rate
On-Chip
SRAM ROM Package Description Package Option
ADSP-21371KSWZ-2A
2
2
Z = RoHS Compliant Part.
0ºC to +70ºC 266 MHz 1M bit 4M bit 208-Lead LQFP_EP SW-208-1
ADSP-21371KSWZ-2B
2
0ºC to +70ºC 266 MHz 1M bit 4M bit 208-Lead LQFP_EP SW-208-1
ADSP-21371BSWZ-2B
2, 3
3
Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software.
For a complete list, visit our website at www.analog.com/SHARC.
–40ºC to +85ºC 266 MHz 1M bit 4M bit 208-Lead LQFP_EP SW-208-1
ADSP-21375KSWZ-2B
2
0ºC to +70ºC 266 MHz 0.5M bit 2M bit 208-Lead LQFP_EP SW-208-1
ADSP-21375BSWZ-2B
2, 3
–40ºC to +85ºC 266 MHz 0.5M bit 2M bit 208-Lead LQFP_EP SW-208-1
