Data Sheet 100604B
March 23, 2000
Advance Information
This document contains information on a product under development. The parametric information
contai ns target para me te rs tha t are subje ct to c hange.
CN8331/CN8332/CN8333
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
The CN8333 is a three-channel , E3/DS3/STS-1 fully-integrated L ine Interface Unit (LIU).
It is configured via external pins and does not need a microprocessor interface.
Each channel has an independent equalizer on the receive side requiring no user
configuration. Also, each channel has a programmable transmit pulse shaper that can
be set to ensure that the cross-connect pulse mask requirement is met for transmit
cable length up to 450 feet. The CN8332 is a dual-channel, and the CN8331 is a
single-channel LIU with performance identical to the CN8333.
The CN8333 gives the user new economies of scale in concentrator applications
where three DS3 or STS-1 channels are concentrated into a single STS-3 channel. By
including three indepen dent transceivers on a chip, sign ifi cant external components are
eliminated, with the exception of 1:1 coupling transformers, termination resistors, and
supply bypass capacitors.
NOTE: In this document "x" is used to represent the number of channels:
x = 1 (CN8331), x = 2 (CN8332), and x = 3 (CN8333).
Functional Block Diagram (only one Channel is shown)
TPOS
TNEG
TCLK ENCODER
TAIS
Pulse
Shaper
E3MODE
LINE
DRIVER
PDB
DATA
MUX
RLOOP
ENDECDIS
LLOOP
LBO
XOE
TLINEP
TLINEM
DECODER
RPOS
RNEG
RCLK
RLOS
TCLK
Clock/
Data
Recovery
PDATA
NDATA
DATCLK
P
NReceiver
ALOS
RLINEP
RLINEM
REFCLK
REQH
Distinguishing Features
• Can be used as a data transceiver
over a maxi mum of 900 f eet of Type
734/728 coaxial cable or equivalent
in an on-premise environme nt
• Programmable pulse filtering to meet
cross-connect pulse masks (ANSI
T1.102-1993)
• Meets jitter specifications of Bellcore
GR499 and GR253
• Large input dyn amic range
• Alarms for coding violation and loss
of sign al
• Full diagnostic loopback capability
• Uses a minimum of external
components
• Com pa ti ble with ITU-T G .703, G. 823
• Independent power down mode per
channel
• Easily interfaced to the DS3/E3
Framer IC (CN8342/3/4/6/8 and
CN8330)
• Selec table B3Z S/HDB3
encoding/decoding
• Sup eri or in pu t rec ei ver se n si t ivity
(< 25mV)
Physical Characteristics
• 80-pi n ETQFP package
• Single 3.3 V pow er supply
• 1 W maximum power dissipation
(CN8333)
•–40 °C to +85 °C temperature range
•5 V-tolera nt pins
•TTL digital pins
Applications
•Digital Cross Connect Syst ems
•Routers
•ATM Switches
•Channelized Line Aggregation Units
•Test Equipm e nt
•Channel Service Uni ts
•Multiplexers
100604B Conexant
Preliminary Information/Conexant Proprietary and Confidential
© 2000, Conexant Systems, Inc.
All Rights Reserved.
Information in this document is provided in connection with Conexant Systems, Inc. (“Conexant”) products. These materials are
provided by Conexant as a service to its customers and may be used for informational purposes only. Conexant assumes no
responsibility for errors or omissions in these materials. Conexant may make changes to specifications and product descriptions at
any time, without notice. Conexant makes no commitment to update the information and shall have no responsibility whatsoever for
conflicts or incompatibilities arising from future changes to its specifications and product descriptions.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as
provided in Conexant’s Terms and Conditions of Sale for such products, Conexant assumes no liability whatsoever.
THESE MA TERIALS ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELA TING
TO SALE AND/OR USE OF CONEXANT PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, CONSEQUENTIAL OR INCIDENTAL DAMAGES, MERCHANTABILITY, OR INFRINGEMENT OF ANY
PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. CONEXANT FURTHER DOES NOT WARRANT THE
ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE
MATERIALS. CONEXANT SHALL NOT BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL
DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS, WHICH MAY RESULT FROM THE USE
OF THES E MATERIALS.
Conexant products are not intended for use in medical, lifesaving or life sustaining applications. Conexant customers using or selling
Conexant products for use in such applications do so at their own risk and agree to fully indemnify Conexant for any damages
resulting from such improper use or sale.
The following are trademarks of Conexant Systems, Inc.: Conexant™, the Conexant C symbol, and “What’s Next in Communications
Technologies”™. Product names or services listed in this publication are for identification purposes only, and may be trademarks of
third parties. Third-party brands and names are the property of their respective owners.
For additional disclaimer information, please consult Conexant’s Legal Information posted at www.conexant.com, which is incorporated
by reference.
Reader Response: Conexant strives to produce quality documentation and welcomes your feedback. Please send comments and
suggestions to conexant.tech.pubs@conexant.com. For technical questions, contact your local Conexant sales office or field
applications engineer.
CN8333EVM
Ordering Information
Model Number Package Operating Tempera ture
CN8331EXF 80-Pin ETQFP –40 °C to 85 °C
CN8332EXF 80-Pin ETQFP –40 °C to 85 °C
CN8333EXF 80-Pin ETQFP –40 °C to 85 °C
CH2
CH3
CN8333
NRZTX DATA and CLK in
Loss of Signal
Code Violation
Clock Input
Control
TX B3ZS/HDB3 analog out
RX B3ZS/HDB3 analog in
NRZRX DATA and CLK out
NRZTX DATA and CLK in
NRZRX DATA and CLK out
NRZTX DATA and CLK in
NRZRX DATA and CLK out
CH1
CH2
CH3
CH1
TX B3ZS/HDB3 analog out
RX B3ZS/HDB3 analog in
TX B3ZS/HDB3 analog out
RX B3ZS/HDB3 analog in
L
I
N
E
S
I
D
E
F
R
A
M
E
S
I
D
E
100604_009
100604B Conexant iii
Preliminary Information/Conexant Proprietary and Confidential
Table of Contents
Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .vii
1.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1
1.1 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
2.0 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2. 1 AMI B3ZS/HDB3 En coder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2.2 Pulse Shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2.3 Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.2.4 Transmit Pulse Mask Templates and Power Measurements . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.2.5 Alarm Indicatio n Signal (A IS) G enerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.2.6 Jitter Generation (Intrinsic). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.3.1 Receive Sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.3.2 AGC/VGA Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.3.3 Receive Equalizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.3.4 The PLL Clock Recovery Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.3.5 Loss Of Signal (LOS) Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.3.6 J itter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.3.7 B3ZS/HDB3 Decoder With Bipolar Violation Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.3. 8 Data Squelching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.4 Addi t ional CN8331/CN8 332/CN 8333 Functio ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.4.1 Bias Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.4.2 Power-On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.4.3 Loopback Multiplexers (MUXes). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.5 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Table of Contents CN8331/CN8332/CN8333
Single/Dual/Tr iple E3/DS3/STS-1 Line Interface Unit
iv Conexant 100604B
Preliminary Information/Conexant Proprietary and Confidential
2.6.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.6.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.7 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.8 AC C haracteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
3.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 PCB De sign C onsid erations for CN8331/CN8332/ CN83 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1.1 Power Supply and Grou nd Pl ane. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1.2 Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.1.3 Other Passive Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.1.4 IBIS Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.1.5 Recommended Vendors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A.1 Applicable Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Appendix B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
B.1 Evalu ation Module Schem atic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
CN8331/CN8332/CN8333 List of Figures
Single/Dual/Triple E3/DS3/STS-1 Lin e Interface Unit
100604B Conexant v
Preliminary Information/Conexant Proprietary and Confidential
List of Figures
Figure 1-1. CN8331 Pin Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Figure 1-2. CN8332 Pin Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Figure 1-3. CN8333 Pin Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Figure 2-1. Typical Application Of Single CN833x Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Figure 2-2. Pulse Shaper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Figure 2-3. Pulse Measurement Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Figure 2-4. Transmit Pulse Mask for E3 Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Figure 2-5. Transmit Pulse Mask for DS3 and STS-1 Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Figure 2-6. AIS Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Figure 2-7. Minimum Input Jitter Tolerance Requirement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Figure 2-8. Mechanical Drawing—Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -14
Figure 2-9. Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Figure 3-1. Typical Connection of CN8333 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Figure B-1. Recommended Schematic for the CN833x Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
List of Figures CN8331/CN8332/CN8333
Single/Dual/Tr iple E3/DS3/STS-1 Line Interface Unit
vi Conexant 100604B
Preliminary Information/Conexant Proprietary and Confidential
CN8331/CN8332/CN8333 List of Tables
Single/Dual/Triple E3/DS3/STS-1 Lin e Interface Unit
100604B Conexant vii
Preliminary Information/Conexant Proprietary and Confidential
List of Tables
Table 1-1. CN8331/CN8332/CN8333 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Table 2-1. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Table 2-2. Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Table 2-3. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -17
Table 2-4. AC Characteristics (Logic Timing). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
List of Tables CN8331/CN8332/CN8333
Single/Dual/Tr iple E3/DS3/STS-1 Line Interface Unit
viii Conexant 100604B
Preliminary Information/Conexant Proprietary and Confidential
100604B Conexant 1-1
Preliminary Information/Conexant Proprietary and Confidential
1
1.0 Pin Description
1.1 Pin Assignme nts
Figures 1-1 (CN8331), 1-2 (CN8332), and 1-3 (CN8333) illustrate pin
assignments for t he 80-pi n Ex posed Thin Quad Fl at Package (ETQFP). Table 1-1
lists the pin definitions and gives additional information for each pin. The
input/output (I/O) column is coded as follows:
I = Input
O = Output
I/O = Bidirectional
P = Power
When a channel is disabl ed (i.e., the PDBx pin is tied low or not connected),
all recei ve and transmit analo g circuitry po wers do wn. Analo g inputs (RLINE) are
ignored and analog outputs (TLINE) are high impedance. Digital inputs of a
powered-down channel are still active, but ignored. Overall noise on the device
can be lowered by not driving the digital inputs of a powered-down channel.
NOTE: When power is disconnected from the device, TLINE pins are low
impedance to ground if driven by more than one forward-bias diode
voltage (0.7 V) below ground. Additionally, driv ing TLINE, a
forward-bias diode voltage above the VGG pin, creates a low impedance
path from the TLINE pin to the VGG pin. Otherwise, the TLINE pins are
high impedance.
1.0 Pin Descriptio n CN8331/CN8332/CN8333
1.1 Pin Assignments Single/Dual/Tr iple E3/DS3/STS-1 Line Interface Unit
1-2 Conexant 100604B
Preliminary Information/Conexant Proprietary and Confidential
Figure 1-1. CN8331 Pin Diagram
CN8331
76
77
78
79
80
NC
GPD
RESET
VGG
RBIAS
71
72
73
74
75
NC
NC
DVDDIO
NC
NC
66
67
68
69
70
NC
NC
NC
NC
NC
61
62
63
64
65
NC
NC
NC
NC
NC
56
57
58
59
60
LLOOP
RLOOP
PD
ENDECDIS
DVDDC
51
52
53
54
55
TAIS
RLOS
RCLK
RPOS/RNRZ
RNEG/RLCV
46
47
48
49
50
REQH
REFCLK
TCLK
TPOS/TNRZ
TNEG/NC
41
42
43
44
45
DVSSC
NC
E3MODE
LBO
XOE
5
4
3
2
1
10
9
8
7
6
15
14
13
12
11
20
19
18
17
16
25
24
23
22
21
NC
VSS
NC
NC
VDD
30
29
28
27
26
NC
NC
DVSSIO
NC
NC
35
34
33
32
31
NC
NC
NC
NC
NC
40
39
38
37
36
NC
NC
NC
NC
NC
RVSS
RLINEN
RLINEP
RVDD
VDD
NC
NC
VSS
TVDD
TLINEN
TLINEP
TVSS
VSS
VDD
NC
NC
VSS
NC
VDD
NC
100604_002
CN8331/CN8332/CN8333 1.0 Pin Description
Single/Dual/Triple E3/DS3/STS-1 Lin e Interface Unit 1.1 Pi n Assignments
100604B Conexant 1-3
Preliminary Information/Conexant Proprietary and Confidential
Figure 1-2. CN8332 Pin Diagram
CN8332
76
77
78
79
80
PD1
GPD
RESET
VGG
RBIAS
71
72
73
74
75
XOE1
LBO1
DVDDIO
LLOOP1
RLOOP1
66
67
68
69
70
RLOS1
RCLK1
RPOS1/RNRZ1
RNEG1/RLCV1
REQH1
61
62
63
64
65
TAIS1
TCLK1
TPOS1/TNRZ1
TNEG1/NCI
REFCLK1
56
57
58
59
60
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
E3MODE
ENDECDIS
DVDDC
51
52
53
54
55
46
47
48
49
50
41
42
43
44
45
DVSSC
NC
5
4
3
2
1
10
9
8
7
6
15
14
13
12
11
20
19
18
17
16
25
24
23
22
21
PD2
RVSS2
RLINE2N
RLINE2P
RVDD2
30
29
28
27
26
XOE2
LBO2
DVSSIO
LLOOP2
RLOOP2
35
34
33
32
31
RLOS2
RCLK2
RPOS2/RNRZ2
RNEG2/RLCV2
REQH2
40
39
38
37
36
TAIS2
TNEG2/NC2
TPOS2/TNRZ2
TCLK2
REFCLK2
TVDD2
TLINE2N
TLINE2P
TVSS2
VSS
NC
NC
VDD
VDD
NC
NC
VSS
TVSS1
TVDD1
TLINE1N
TLINE1P
RVSS1
RLINE1P
RVDD1
RLINE1N
100604_010
1.0 Pin Descriptio n CN8331/CN8332/CN8333
1.1 Pin Assignments Single/Dual/Tr iple E3/DS3/STS-1 Line Interface Unit
1-4 Conexant 100604B
Preliminary Information/Conexant Proprietary and Confidential
Figure 1-3. CN8333 Pin Diagram
CN8333
76
77
78
79
80
PD1
GPD
RESET
VGG
RBIAS
71
72
73
74
75
XOE1
LBO1
DVDDIO
LLOOP1
RLOOP1
66
67
68
69
70
RLOS1
RCLK1
RPOS1/RNRZ1
RNEG1/RLCV1
REQH1
61
62
63
64
65
TAIS1
TCLK1
TPOS1/TNRZ1
TNEG1/NCI
REFCLK1
56
57
58
59
60
LLOOP2
RLOOP2
PD2
ENDECDIS
DVDDC
51
52
53
54
55
TAIS2
RLOS2
RCLK2
RPOS2/RNRZ2
RNEG2/RLCV2
46
47
48
49
50
REQH2
REFCLK2
TCLK2
TPOS2/TNRZ2
TNEG2/NC2
41
42
43
44
45
DVSSC
E3MODE
NC
LBO2
XOE2
5
4
3
2
1
10
9
8
7
6
15
14
13
12
11
20
19
18
17
16
25
24
23
22
21
PD3
RVSS3
RLINE3N
RLINE3P
RVDD3
30
29
28
27
26
XOE3
LBO3
DVSSIO
LLOOP3
RLOOP3
35
34
33
32
31
RLOS3
RCLK3
RPOS3/RNRZ3
RNEG3/RLCV3
REQH3
40
39
38
37
36
TAIS3
TNEG3/NC3
TPOS3/TNRZ3
TCLK3
REFCLK3
RVSS2
RLINE2N
RLINE2P
RVDD2
TVDD3
TLINE3N
TLINE3P
TVSS3
TVDD2
TLINE2N
TLINE2P
TVSS2
TVSS1
TVDD1
TLINE1N
TLINE1P
RVSS1
RLINE1P
RVDD1
RLINE1N
100604_011
CN8331/CN8332/CN8333 1.0 Pin Description
Single/Dual/Triple E3/DS3/STS-1 Lin e Interface Unit 1.1 Pi n Assignments
100604B Conexant 1-5
Preliminary Information/Conexant Proprietary and Confidential
Table 1-1. CN8331/CN8332/CN8333 Pin Definitions (1 of 6)
Pin # Signal Name Description I/O/P Notes
CN8331 CN8332 CN8333
Coaxial Line Pins
14 6 6 RLINEP/
RLINE1P Line 1 positi ve receive
data I Differential inputs for each channel from its
respective receive coax line. The RX expects
balanced differenti al inputs, usually
achieved using a 1:1 transfo rm e r.
The in puts ar e inter n ally DC biased to 1.9 V.
15 7 7 RLINEN/
RLINE1N Line 1 negative receive
data I
—22 14 RLINE2P Line 2 positive receive
data I
—23 15 RLINE2N Line 2 ne g ative rec ei ve
data I
——22 RLINE3P Line 3 positive receive
data I
——23 RLINE3N Line 3 negative receive
data I
10 2 2 TLINEP/
TLINE1P Line 1 posi tive tra nsmit
data O D ifferential, coax-driver balanced outputs
for pulse-shaped AMI B3ZS/HDB3 encoded
waveforms for each channel .
These pins should be connecte d to the
primary side of the 1:1 transformer through
two backmatch resistors (see Appendix B).
11 3 3 TLINEN/
TLINE1N Line 1 negative transmit
data O
—18 10 TLINE2 P Line 2 po sitive transm it
data O
—19 11 TLINE2N Line 2 negative transmit
data O
——18 TLINE3 P Line 3 po sitive transm it
data O
——19 TLINE3N Line 3 negative transmit
data O
Digital Data Pins
54 68 68 RPOS/
RPOS1/
RNRZ/
RNRZ1
RX1 AMI + data/ NRZ
dat a output O R esynchronized receive data intended to be
strobed out by the co rresponding RCLK .
When END ECDIS = 1, t hese outputs are
positive and negative AMI data (RPO S and
RNEG).
When END ECDIS = 0, t hese outputs are
decoded NRZ data (R NRZ) and li ne code
violat ion (RLC V). A line code violation is
indicat ed when RLCV = 1.
See notes on the ENDECDIS pi n, next pa ge.
55 69 69 RNEG/
RNEG1/
RLCV/ RLCV1
RX1 AMI – data/line
code violation O
—33 54 RPOS2/
RNRZ2 RX2 AMI + data/ NRZ
dat a output O
—32 55 RNEG2/
RLCV2 RX2 AMI – data/li ne
code violation O
——33 RPOS3/
RNRZ3 RX3 AMI + data/ NRZ
dat a output O
——32 RNEG3/
RLCV3 RX3 AMI – data/li ne
code violation O
1.0 Pin Descriptio n CN8331/CN8332/CN8333
1.1 Pin Assignments Single/Dual/Tr iple E3/DS3/STS-1 Line Interface Unit
1-6 Conexant 100604B
Preliminary Information/Conexant Proprietary and Confidential
53 67 67 RCLK/ RCLK1 Rec eive clock Ch1 O Recovered clock for each cha nnel receiver,
intended for str obing the corres pondin g
RDAT into the following framer or logic.
—34 53 RCLK2 Receive clock Ch2 O
——34 RCLK3 Rec eive clock Ch3 O
49 63 63 TPOS/
TPOS1/
TNRZ/ TNRZ1
Ch1 transmit Positive
rail or N RZ data I Synchronized transmit da ta intended to be
strobe d in by the cor responding TCLK.
When ENDECDIS = 1, these inpu ts are
expected to be positive and negative AMI
data (TPO S an d TN EG) .
When ENDECDIS = 0, these inpu ts are
expected to be uncoded NRZ data (TNRZ)
and no connects (NC).
See notes on the ENDE CDIS pin.
48 64 64 TNEG/
TNEG1/
NC/
NC1
Ch1 transmit Negative
rail or no connect data I
—38 49 TPOS2/
TNRZ2 Ch2 transmit
Positive/NRZ data I
—37 48 TNEG 2/ NC2 Ch2 trans mit N ega tiv e
data I
——38 TPOS3/
TNRZ3 Ch3 transmit
Positive/NRZ data I
——37 TNEG3/ NC3 Ch3 transmit Negative
data I
50 62 62 TCLK/ TCLK1 Transmit clock Ch1 I Transmit bit clock input for strobing with
trans mi t dat a into the CN83 3 x.
—39 50 TCLK2 Transmit clock Ch2 I
——39 TCLK3 Transmit clock Ch3 I
52 66 66 RLOS/ RLOS1 Loss of signal Ch1 O Lo ss Of Signal (LOS) indication for each
channel, as determined by insufficient pulse
densit y. Signal loss detected when RLOS =
1. An LOS will be asserted when 175±75
zeros occur in a row and deasserted when
the pulse density is betwee n 28% and 33%
(DS3/STS-1) (i.e., a 1’s den sity).
—35 52 RLOS2 Loss of signal Ch2 O
——35 RLOS3 Loss of s ign a l Ch3 O
Table 1-1. CN8331/CN8332/CN8333 Pin Definitions (2 of 6)
Pin # Signal Name Description I/O/P Notes
CN8331 CN8332 CN8333
CN8331/CN8332/CN8333 1.0 Pin Description
Single/Dual/Triple E3/DS3/STS-1 Lin e Interface Unit 1.1 Pi n Assignments
100604B Conexant 1-7
Preliminary Information/Conexant Proprietary and Confidential
Contr ol Si gn al s
59 59 59 ENDECDIS Encoder/decoder
disable (for all
channels)
I 1 = Du al ra il pu ls e cod e d d a ta fo rmat . In pu t
transmit data pins TPOS, TNRZ, TNEG and
NC are interpreted as TPOS and TNEG
(encoded positive and negative rail data).
Output receive data pins RPOS and RNRZ,
and RNEG and RLC V are interpreted as
RPOS and RNEG, with RPOS hav in g a
positive pulse in place of every positive AMI
pulse a nd RNEG having a negative pulse in
place of every negative AMI pulse.
0 = NRZ format. Transmit data pi ns TPOS
and TNEG are interpreted as TNRZ and NC
(not connected). Receive data pin s RP OS
and RNEG are interpreted as RNRZ and
RLCV. In this mode, all line code violations
are reported as active high on RLC V.
—61 61 T AI S1 Tran smit Ch1 AIS m ode
enable I Transmission of Alarm Indicat ion Signal
(AIS) for a given channel. Replace transmit
data with AIS signal. The AMI form o f AIS
supported is alternating 1s.
(+1, -1, +1, -1, +1, ...)
Looping takes precedence ov er AI S.
1 = AIS mo de enabled
0 = AIS mo de disabl ed
51 —51 TAIS/
TAIS2 T ra nsmit Ch2 A IS mode
enable I
40 40 40 TAIS2/
TAIS3 T ra nsmit Ch3 A IS mode
enable I
43 43 43 E3MODE E3MODE I When the pin is set to high, it enables the
E3 mode on all channel s, instead of the
DS3/STS- 1 mode. This also changes the
pulse shaper to E3 mode and overrides all
LBO pins. It also changes the
encoder/decoder from B3ZS mode to HDB3
mode.
1 = E3 mode
0 = DS3/STS-1 mode
44 72 72 LBO/
LBO1 Transmit line Ch1
build-out mode I Line build-out mode per channel, based on
the leng th of cable on the transmit side of
the cross-connect block. This bit is
overridden and the pulse shaper is disabled
(no pulse sh aping) if E3 MODE = 1.
1 = Inse rts line build- out into the transmit
channel. Usually used whe n the transmit
cable is less than 350 feet in length.
0 = Line build-out bypassed (not inse rt ed).
Usuall y used when the t r ansmit cable is
greater than 350 feet in length.
—29 44 LBO2 Transmit line Ch2
build-out mode I
——29 LBO3 Transmit line Ch3
build-out mode I
Table 1-1. CN8331/CN8332/CN8333 Pin Definitions (3 of 6)
Pin # Signal Name Description I/O/P Notes
CN8331 CN8332 CN8333
1.0 Pin Descriptio n CN8331/CN8332/CN8333
1.1 Pin Assignments Single/Dual/Tr iple E3/DS3/STS-1 Line Interface Unit
1-8 Conexant 100604B
Preliminary Information/Conexant Proprietary and Confidential
56 74 74 LLOOP/
LLOOP1 Local loopback enable
Ch1 I Local loopback enable per channel. The
transmit data is looped back immediately
from the encoder to the decoder in place of
the received data.
1 = local loopback enabled
0 = local loopback disabled
—27 56 LLOOP2 Local loop back enable
Ch2 I
——27 LLOOP3 Local loopback enabl e
Ch3 I
57 75 75 RLOOP/
RLOOP1 Rem ot e lo op ba c k
ena ble Ch1 I Remote loopback enable per channel. The
receive data, retimed after clock recovery , is
looped back into the AMI generator in place
of the transmit data.
1 = remote loopback enabled
0 = remote loopback disabled
—26 57 RLOOP2 Remote loopba c k
ena ble Ch2 I
——26 RLOOP3 Remote loopba c k
ena ble Ch3 I
45 71 71 XOE/
XOE1 Transmit output enable
Ch1 I Transmit output enable per channel.
1 = tran smit line output driver enabled
0 = transmit output driver set to high
impeda nce state
—30 45 XOE2 Trans mit ou tput en able
Ch2 I
——30 XOE3 Transm it outpu t ena ble
Ch3 I
—70 70 REQH1 Ch1 Receive High EQ
Gain Enable I The equalizer in the CN 833x has two gain
settings. The higher gain setting is designed
to optimally equalize a nominal ly-shap e d
(meets the pulse template), pulse-driven
DS3 or STS - 1 wa ve fo r m that is driv e n
thro ug h 0–900 feet of cable.
Squa re-shaped pulses such as E3 or
DS3-H IGH re quir e less high -fr equ ency gain
and shoul d use the low EQ gai n setting.
REQH = 1 high E Q gain ( DS3/STS - 1 modes )
REQH = 0 low EQ gain (E3/DS3
Square Modes)
46 —46 REQH/
REQH2 Ch2 Receive High EQ
Gain Enable I
—31 31 REQH3 Ch3 Receive High EQ
Gain Enable I
Power/Ground
12 4 4 TVDD/ TVDD1 TX powe r Ch1 P Power pins for transmit c ircui try per
chan nel (3.3 V) .
—20 12 TVDD2 TX pow e r Ch2 P
——20 TVDD3 TX power Ch3 P
9 1 1 TVSS/ TVSS1 TX ground Ch1 P Ground pins for transmit circuitry per
channel.
—17 9 TVSS2 TX ground Ch2 P
——17 TVSS3 TX ground Ch3 P
13 5 5 RVDD/
RVDD1 RX power Ch1 P Power pins for receive circuitry per channel
(3.3 V).
Connect to 3.3 V power.
—13 13 RVDD2 RX power Ch2 P
——21 RVDD3 RX power Ch3 P
Table 1-1. CN8331/CN8332/CN8333 Pin Definitions (4 of 6)
Pin # Signal Name Description I/O/P Notes
CN8331 CN8332 CN8333
CN8331/CN8332/CN8333 1.0 Pin Description
Single/Dual/Triple E3/DS3/STS-1 Lin e Interface Unit 1.1 Pi n Assignments
100604B Conexant 1-9
Preliminary Information/Conexant Proprietary and Confidential
16 8 8 RVSS
RVSS1 RX ground Ch1 P Ground pins for receive circuitr y per
channel.
Connect to gro und.
—24 16 RVSS2 RX ground Ch2 P
——24 RVSS3 RX ground Ch3 P
60 60 60 DVDDC Digital core power P Digital core power for all channels (3.3 V).
41 41 41 DVSSC Digital core ground P Digital core gr ound for al l channels .
79 79 79 VGG 5 V/3 .3 V ESD pin (1) P 5 V supply for 5 V-to le ra nt, digital pa d ES D
diodes. No stat ic power is drawn from pin.
73 73 73 DVDDIO Digital I/O power P Connect to 3.3 V digital power.
28 28 28 DVSSIO Digital ground P Digital ground.
4, 5, 20,
21 12, 13 —VDD Power P Connect to 3. 3 V power.
1, 8, 17,
24 9, 16 —VSS Gro und P Co nnect to ground.
Miscellaneous
58 76 76 PD/
PD1 Power down f or Ch1 I Power down t ra nsceiver channel
0 = Power down chann e l (off)
1 = Channel active (on)
Note: A speci al power-down mode exists
whe n all three P DBs are se t low. This
special mod e shuts off the en tire chip
(including biasing). This is useful for static
Idd testing. (See PD pin).
—25 58 PD2 Power down for Ch2 I
——25 PD3 Power down for Ch3 I
47 65 65 REFCLK/
REFCLK1 Reference clock fo r Ch 1 I Ref erence clock from off-chip.
This clock should b e set to one of th e
following:
•E3 rate (34.368 MHz)
•DS3 rate (44.736 MHz)
•STS-1 rate (51.84 MHz)
The clock rat e should correspond to t he
mode of operation that has been chosen for
the channel.
—36 47 REFCLK2 Reference clock for Ch2 I
——36 REFCLK3 Reference clock for Ch3 I
80 80 80 RBIAS Bias resis tor O A 1 2.1 kΩ ±1% resistor tied from this pin to
ground provides the cur rent reference to
the entire ch ip.(2)
78 78 78 Reset Reset I/O Async hronous reset (reset ent ire device).
77 77 77 GPD Global Power Down I/O Power Down (device ente r low power st ate
for Static Idd testing).
Table 1-1. CN8331/CN8332/CN8333 Pin Definitions (5 of 6)
Pin # Signal Name Description I/O/P Notes
CN8331 CN8332 CN8333
1.0 Pin Descriptio n CN8331/CN8332/CN8333
1.1 Pin Assignments Single/Dual/Tr iple E3/DS3/STS-1 Line Interface Unit
1-10 Conexant 100604B
Preliminary Information/Conexant Proprietary and Confidential
2, 3, 6, 7,
18, 19,
22, 23,
25, 26,
27, 29,
30, 31,
32, 33,
34, 35,
36, 37,
38, 39,
40, 42,
61, 62,
63, 64,
65, 66,
67, 68,
69, 70,
71, 72,
74, 75, 76
10, 11,
14, 15,
42, 44,
45, 47,
48, 49,
50, 51,
52, 53,
54, 55,
56, 57, 58
—NC No conn ect —Not connected.
NOTE(S):
(1) This pin should be connected to 3.3 V in an all-3.3 V design.
(2) Placing a capacitor f rom this pin t o ground may result in instabilit ies.
3. All digital input pins contain a 75 KΩ pull-down r esistor from input to DVSS.
Table 1-1. CN8331/CN8332/CN8333 Pin Definitions (6 of 6)
Pin # Signal Name Description I/O/P Notes
CN8331 CN8332 CN8333
100604B Conexant 2-1
Preliminary Information/Conexant Proprietary and Confidential
2
2.0 Functional Description
2.1 Overview
CN8333 is a triple E3/DS3/STS-1 Line Interface Unit (LIU). It is the physical
la y er interface betw ee n the data framer (or other t erminal-side eq uipment) and t he
electrical cable used for data transmission.
The CN8333 LIU consists of three independent data transceivers that can
operate over type 734/728 coaxial cable at the rates of 34.368 Mbps (E3), 44.736
Mbps (DS3), and 51.84 Mbps (STS-1). The transmit side takes an NRZ or
already-encoded dual rail input and encodes it into AMI B3ZS (for DS3/STS-1)
or HDB3 (for E3) analo g w aveforms to be transmitted o v er t he coaxial cab le. The
receiver side takes in the attenuated and distorted analog receive signal and
equalizes, slices, and resynchronizes the signal before decoding it to the NRZ
output or sending out a non-decoded dual rail.
CN8331 and CN8332 are single- and dual-E3/DS3/STS-1 LIUs, respectively.
In all respects, their performance and features are identical to the CN8333.
The architecture of the CN833x includes the following internal functions for
each channel:
General:
• bias gen erator
• power-on reset
• loop back MUXes
Transmitter:
• B3ZS/HDB3 encoder
• Alarm Indication Signal (AIS) insertion
• pulse shaper
• line driver
Receiver:
• Automatic Gain Control
• receive equalizer
• Clock Recovery Circuit
• Loss Of Signal (LOS) detector
• B3ZS/HDB3 decoder with bipolar violation detector
2.0 Functional Descriptio n CN8331/CN8332/CN8333
2.1 Overv iew Single/Dual/Tr iple E3/DS3/STS-1 Line Interface Unit
2-2 Conexant 100604B
Preliminary Information/Conexant Proprietary and Confidential
In addition, each channel has the ability to perform remote and local
loopbacks. Figure 2-1 illustrates a typical application using the CN833x in a
channel.
External pins are provided to configure the various line rates and formats for
each channel.
The CN833x is used as a data transceiver over a coaxial cable that is up to
900 feet long (or up to 450 feet from the DSX) in an on-premise environment
within any public or private networks which use these data rates.
Figure 2-1. Typical Application Of Single CN833x Channel
0–450 ft COAX
(type 734/728) DSX
0–450 ft COAX
(type 734/728) DSX
0–450 ft COAX
(type 734/728)
0–450 ft COAX
(type 734/728)
TX
RX
RX
TX
100604_012
CN8331/CN8332/CN8333 2.0 Functional Description
Single/Dual/Triple E3/DS3/STS-1 Lin e Interface Unit 2.2 Transm itte r
100604B Conexant 2-3
Preliminary Information/Conexant Proprietary and Confidential
2.2 Transmitter
This sect ion descr i bes the detailed op er at ion of th e various blocks in the CN83 3x
transmitter.
2.2.1 AMI B3ZS/HDB3 Encoder
ENDECDIS and the E3MODE pins configure the encoder mode.
When ENDECDIS = 0, the encoder is receiving non-encoded Nonreturn to
Zero (NRZ) data on the TNRZ (TPOS) pin alone, and the NC (no connect)
(TNEG) pin is ignored.
Data is encoded into a representation of a three-level B3ZS (E3MODE = 0) or
HDB3 (E3MODE = 1) signal (conforming to the coding rules as specified in
Appendix A) before g oing on to t he pulse shaper in the form of tw o binary signals
repres enting the positive and negative thre e-level pulse s.
When ENDECDIS = 1, the encoder is disabled. The encoder passes
already-encoded data over TPOS (TNRZ) and TNEG (NC) to the pulse shaper.
The transmit digital data is clocked into the chip via a rising TCLK edge,
w hich must be equa l to the symbol rate ( line rat e). A small del a y added to t he data
provides a certain amount of negative data hold time.
2.0 Functional Descriptio n CN8331/CN8332/CN8333
2.2 Transmitter Single/Dual /Triple E3/DS3/STS-1 Line Interface Unit
2-4 Conexant 100604B
Preliminary Information/Conexant Proprietary and Confidential
2.2.2 Pulse Shaper
The pulse shaper converts the two digital (clocked) positive and negative pulses
into a single analo g three-le vel Alternate Mark In version (AMI) pulse. The pulses
are in Return to Zero (RZ) format, meaning that all positive and negative pulses
have a duration of the first half of the symbol period.
For the E3 rate (E3 MODE = 1), the AMI pulse is a full-amplitude,
square-sh aped pulse with very little slope.
For DS3/STS-1 rates, a pulse-shaper block is used to shape the transmit
waveform and reduce its high-frequency energy content. This ensures that the
transmit pulse template is met at the cross-connect block, which follow s 0–450
feet of transmit-side coaxial cable.
Figure 2-2. Pulse Shaper
100604_008
Pulse
Shaper
LBO
E3
Mode
LBO = 0
LBO = 1
+ Pulse – Pulse
Line Driver
CN8331/CN8332/CN8333 2.0 Functional Description
Single/Dual/Triple E3/DS3/STS-1 Lin e Interface Unit 2.2 Transm itte r
100604B Conexant 2-5
Preliminary Information/Conexant Proprietary and Confidential
2.2.3 Line Driver
The dif ferential lin e driv er takes t he filtered transmit w a v eform, increases it to the
proper level, and drives it into the transmit magnetics. The two external discrete
back-matchi ng resistors (36 Ωs) aid in line matchi ng. The dr i ver is p resented wit h
an approximately 150 Ω differential load. Driver gain accounts for the 6 dB gain
loss in the back-matching resistors.
Figure 2-3 illustrates th e Pulse/Power template mea s urement po ints for the
variou s data rates.
Figure 2-3. Pulse Measurement Points
0–450 ft COAX
(type 734/728) DSX
0–450 ft COAX
Pulse/Power Template for E3
Pulse/Power Template for DS3/STS-1
(type 734/728) DSX
0–450 ft COAX
(type 734/728)
0–450 ft COAX
(type 734/728)
TX
RX
RX
TX
100604_013
2.0 Functional Descriptio n CN8331/CN8332/CN8333
2.2 Transmitter Single/Dual /Triple E3/DS3/STS-1 Line Interface Unit
2-6 Conexant 100604B
Preliminary Information/Conexant Proprietary and Confidential
2.2.4 Transmit Pulse Mask Templates and Power Measurements
Figure 2-4. Transmit Pulse Mask for E3 Rate
Transmit Pulse Mask for E3
0.5 0.33 0.167 0 0.167 0.33 0.5
Normalized Symbol Time
Normalized Pulse Amplitude
1.2
1
0.8
0.6
0.4
0.2
0
0.2
8333_007
CN8331/CN8332/CN8333 2.0 Functional Description
Single/Dual/Triple E3/DS3/STS-1 Lin e Interface Unit 2.2 Transm itte r
100604B Conexant 2-7
Preliminary Information/Conexant Proprietary and Confidential
Figure 2-5. Transmit Pulse Mask for DS3 and STS-1 Rates
Transmit Pulse Mask for DS3 Rates
Transmit Pulse Mask for STS-1 Rates
1 0.5 0 0.5 1 1.5
Normalized Symbol Time
1 0.5 0 0.5 1 1.5
Normalized Symbol Time
Normalized Pulse Amplitude
1.2
1
0.8
0.6
0.4
0.2
0
0.2
Normalized Pulse Amplitude
1.2
1
0.8
0.6
0.4
0.2
0
0.2
8333_008
2.0 Functional Descriptio n CN8331/CN8332/CN8333
2.2 Transmitter Single/Dual /Triple E3/DS3/STS-1 Line Interface Unit
2-8 Conexant 100604B
Preliminary Information/Conexant Proprietary and Confidential
2.2.5 Alarm Indication Signal (AIS) Generator
When selected by asserting TAIS, an AIS replaces th e transmi t data at TPOS and
TNEG. The E3 type of AIS signal (all 1s) is supported. In three-level signal form,
this is a co ntinuously alternating positive and negative pulse stream, as if the
transmit dat a were a conti nuo us st rin g o f l ogical 1s. Figure 2-6 illustrates the AIS
signal.
The TAIS pin has the same data latenc y as the TX data pins and can be used to
replace single symbols within a data stream. When the encoder is disabled
(ENDECDIS = 1), the TAIS mode maintains the proper phase, based upon the
polarity of the last 1 received.
The AIS signal follows the same path as the TX data during remote or local
loopback.
2.2.6 Jitter Generation (Intrinsic)
The CN833x device meets the jitter generation requirements for various rates
with large margins, with the condition that the input transmit clock (TCLK) is
jitter-free. Data ra tes and jitter generation requirements are defined in the
following documents:
•E3 rate—ETSI TBR24, ITU-T 9.823
•DS3 rate—Bellcore Telecardia GR499, AT&T Accunet TR54014,
ITU-T 9.824
•STS-1 rate
—
Bellcore
Telecardia
GR253
Figure 2-6. AIS Signal
POSITIVE
PULSE
NEGATIVE
PULSE
TLINEP
(output voltage)
TLINEM
(output voltage)
8333_009
CN8331/CN8332/CN8333 2.0 Functional Description
Single/Dual/Triple E3/DS3/STS-1 Lin e Interface Unit 2.3 R e ceiver
100604B Conexant 2-9
Preliminary Information/Conexant Proprietary and Confidential
2.3 Receiver
This section describes in detail various blocks in the CN8331/CN8332/CN8333
receiver.
2.3.1 Receive Sensitivity
The receiver recovers data from the coaxial cable that is attenuated due to the
frequency-dependent characteristics of the cable. In addition, the receiver
compensates for the flat loss (across all frequencies) in the various electrical
components and the variation in transmitted signal power.
The CN833x device is able to recover data that has been attenuated by a
maximum of 900 feet of coax having characteristics and attenuation consistent
with ANSI T1.102-1993, Annex C, Figure C.2. This approximates the
characteristics of AT&T type 734/728 cable; almost the same attenuation
characteristic is achieved by one-half the length of AT&T type 735 cable.
2.3.2 AGC/VGA Block
The Variable Gain Amplifier (VGA) receives the AMI input signal from the
coaxial cable. The VGA supplies flat gain (independent of frequ enc y ) t o make up
for various flat losses in the transmission channel and for loss at one-half the
symbol rate that cannot be made up by the equalizer. The VGA gain is controlled
by a feedback loop which senses the amplitude of the equalizer output, acting to
servo this amplitude for optimal slicing.
2.3.3 Receive Equalizer
The receive equalizer receives the differential signal from a VGA and acts to
boost th e high fr equency content of th e signal t o redu ce inter - symbol interf erence
(ISI) to the point that correct decisions can b e made b y the slicer with a mi nimum
of jitter in the recovered data.
The REQH pin is provided to allow lower amounts of equalization (shorter
equivalent cable lengths) for cases where a square-shaped pulse (that does not
meet the DS3/STS-1 standards) is transmitted to the receiver. A square-shaped
input has a much larger high-frequency content and could have overshoots at the
EQ output high enough to cause bit errors. Setting REQH = 0 will lower the gain
and reduce the amount of overshoot.
2.0 Functional Descriptio n CN8331/CN8332/CN8333
2.3 Rece iv er Single/Dual/Triple E3/DS3 /ST S-1 Line Interface Unit
2-10 Conexant 100604B
Preliminary Information/Conexant Proprietary and Confidential
2.3.4 The PLL Clock Recovery Circuit
The clock rec overy circuit (RX PLL) e xtr acts the e mbedded clock from the sliced
data and provides this clock and the retimed data to the decoder (data mode).
Upon startup (after the internal reset is deasserted), the RX PLL uses a reference
clock (REFCLK, running at the symbol rate) and a phase-frequency detector to
lock to the correct data rate (reference mode). During reference mode, the data
outputs are squelched (set to 0). The RX PLL is kept in reference mode until a
valid inp ut is detect ed.
2.3.5 Loss Of Signal (LOS) Detector
The Receive Loss Of Signal (RLOS) is a digital function which monitors the
retimed data from the clock recovery block. The AMI data is checked for a
continuous run of zeroes. When a continuous run of 128 ± 1 consecutive zeroes
occurs, the RLOS signal is asserted. After the RLOS signal is asserted, a 1s count
is made on every block of 128 AMI symbols. The RLOS signal is deasserted
when the 1s count within a block of 128 symbols is at least:
B3ZS: Minimum 1s density = 39 ± 1 count out of 128 (~30.5%)
HDB3: Minimum 1s density = 29 ± 1 count out of 128 (~22.7%)
The RLOS detector will always monitor the cable-side RX inputs. The
detector is not affected by the state of remote or local looping.
2.3.6 Jitter Tolerance
The CN833x receiver is able to tolerate a specified amount of high-frequency
jitter in the received signal while providing error-free operation (generally
defined as a bit error rate of less than 10-9). The specifications (illustrated in
Figure 2-7) for jitter tolerance are discussed in the follow ing docume nts:
•E3 rate – ITU-T G .823 and ETSI TBR24 contain frequen cy mask s for input
jitter tolerance.
NOTE: To meet jitter transfer re quirements for loop-t imed operatio n, an extern a l
jitter atte nuator is required. The ji tter attenuator lessens jitter from the
receive clock.
•DS3 rate – ITU-T G.823 and Bellcore GR499 specify ji tter toleranc e
frequency masks for Category I and Category II interfaces.
•STS-1 rate – Bellcor e GR253 specifies a jitter tolerance. It is noted that the
STS-1 jitter tolerance differs from DS3 requirements only for Category II
interfaces.
CN8331/CN8332/CN8333 2.0 Functional Description
Single/Dual/Triple E3/DS3/STS-1 Lin e Interface Unit 2.3 R e ceiver
100604B Conexant 2-11
Preliminary Information/Conexant Proprietary and Confidential
Figure 2-7. Minimum Input Jitter Tolera nce Req uirement
DS3 / STS-1 Rates
1.0 UI
0.1 UI
1.0 UI
10 UI
0.1 UI
Jitter Frequency
Jitter Frequency
Input Jitter AmplitudeInput Jitter Amplitude
E3 Rate
STS-1
DS3 Category I
DS3 Category II
100 Hz 1 kHz 10 kHz 100 kHz 1 MHz
10 Hz 100 Hz 10 kHz 100 kHz1 kHz
100604_014
2.0 Functional Descriptio n CN8331/CN8332/CN8333
2.3 Rece iv er Single/Dual/Triple E3/DS3 /ST S-1 Line Interface Unit
2-12 Conexant 100604B
Preliminary Information/Conexant Proprietary and Confidential
2.3.7 B3ZS/HDB3 Decoder With Bipolar Violation Detector
In the CN833x device, when ENDECDIS = 0 (encoder/decoder enabled), the
decoder takes the output from the clock recovery circuit and decodes the data
(HDB3 or B3ZS) into a single retimed NRZ data signal. The data signal is then
sent out of the CN833x over the RNRZ (RPOS) pin. Any detected Line Code
Violations (LCV) are sent out over the corresponding RLCV (RNEG) pin. The
RLCV pin is asser ted for one symbol period at the time the violation appears on
the RX output pin (RNRZ).
The following shows data sequence criteria for LCV; violations are indicated
in bold text. A valid bipolar pulse is indicated by a B. A bipolar violation
(non-alter nating positive or negative) pu l se is i ndicated by a V.
•Excessive zeros: 0, 0, 0, 0 (HDB3) or 0, 0, 0 (B3ZS). These violations are
passed on as 0 data on the RNRZ pin.
•Bipolar violation: B, 0, V (i.e., +1, 0, +1 or -1, 0, -1 for HDB3) B, V
(B3ZS and HDB3). These violation s are passed on as 1 data on the RNRZ
pin.
•Coding violation: 0, 0, V (HDB3) or 0, V (B3ZS) with an even number of
Bs since the last valid 0 substitution V (follows coding rule). These
violations are passed on as 0 data on the RNRZ pin.
The e v en /odd co unter ( used to count the numbe r of Bs bet w een Vs) will co unt
a bipolar violation as a B. A coding violation or a valid 0 substitution resets the
counter.
When ENDECDIS = 1, the de coder is disabled, and th e re timed sl icer outputs
are sent out over RPOS (RNRZ) and RNEG (RLCV) pins. These outputs are then
decoded by the CN8340/CN8330 or other downstream device. Line code
violati ons are not det ected in this mode of opera tion. T he decoder is con figurab le
for either :
•E3 mode using HDB3 coding (E3MODE = 1)
•DS3/STS-1 mode using B3ZS coding (E3MO DE = 0 )
The receiver digital data outputs are centered on the rising edge of RCLK
(see Section 2.8).
2.3.8 Data Squelching
A counter in the receiver keeps track of the number of consecutive symbol
periods wit hout a v ali d data pulse. Wh en 128 or more 0s i n a ro w ar e counted, t he
receiver assumes that it has lost the signal and resets itself to try and regain the
signal. While the recei v er is reacquiring the signal, the clock re co ve ry b lock locks
to the ref erence cl ock an d the data squelchi ng i s achi eve d by forcing the data bits
to zero. The data squelching is tr ue in both NRZ and dual rail mode. When the
input signal has been properly amplified and equalized, the clock recovery PLL
will then switch to the inc oming data.
CN8331/CN8332/CN8333 2.0 Functional Description
Single/Dual/Triple E3/DS3/STS-1 Lin e Interface Unit 2.4 Additional CN8331/CN8332/CN8333 Functions
100604B Conexant 2-13
Preliminary Information/Conexant Proprietary and Confidential
2.4 Additional CN8331/CN8332/CN8333
Functions
2.4.1 Bias Generator
To achieve good isolation between the channels, each channel utilizes an
independent power and ground to both transmit and receive. Additionally, each
channel has its own band gap voltage reference. Because only one external
resistor for cu rrent generation e x ist s , only one band gap voltage can be used. The
band gap from Ch1 has been chosen for this task.
The 12.1 kΩ external resistor from pin RBIAS to ground, is specified to have
a tolerance of ±1%. This helps to keep tighter control on power dissipation and
circuit performance.
NOTE: Capacitance should be kept to a minimum on the RBIAS pin.
2.4.2 Power-On Reset (POR)
A POR function is provided in the CN833x device to ensure all of the resettable
digital logic and analog control lines are starting from a known state. This circuit
uses a fixed RC timer (~1µs); add itionall y, 128 clocks from REFC LK are cou nted
(after t he R C t ime r has ti med- out ) b e for e reset i s deasserted, which be gins t i min g
after a minimum supply voltage is reached (see Table 2-2).
2.4.3 Loopback Multiplexers (MUXes)
Two loopback MUXes per channel in the CN833x allow for local loopback
(terminal or framer side), remote loopback (cable side), or both (the AIS signal
follows the same path as the transmit data during loopback). The RLOS signal
monitors the RX cable inputs irrespective of any loopback.
In remote loopback, set by asserting pin RLOOP high, the receive data
(retime d after clock rec overy but not d ecoded) l oops back i nto the pulse sha per in
place of the transmit data. Additionally, this data sent out the RPOS, RNEG, and
RCLK pins.
In local loopback, set by asserting pin LLOOP, the transmit data loops back
immediately from the encoder output to the d ecoder inp ut in plac e of the recei v ed
data. Additionally, this data is sent out the TLINEP and TLINEM pins.
2.0 Functional Descriptio n CN8331/CN8332/CN8333
2.5 Mechanical Specifications Single/Dual/Tr iple E3/DS3/STS-1 Line Interface Unit
2-14 Conexant 100604B
Preliminary Information/Conexant Proprietary and Confidential
2.5 Mechanical Specifications
Figure 2-8. Mechanical Drawing—Dimensions
D3
D3
D
D1
D1
D2
DD1D2
A
L
A1
L1
A2
Pin #1
Ref. Mark
eb
See DETAIL B
TOP
DETAIL B
BOTTOM
c
Dim.
A
A1
A2
D
D1
D2
D3
L
L1
b
c
e
Coplanarity
0.05
0.95
15.75
13.90
0.45
0.09
1.20 MAX.
12.35 REF.
6.50 REF.
1.00 REF.
0.32 REF.
0.65 REF.
0.10 MAX.
0.15
1.05
16.25
14.10
0.75
0.20
0.002
0.040
0.620
0.547
0.018
0.004
0.047 MAX.
0.486 REF.
0.256 REF.
0.039 REF.
0.026 REF.
0.013 REF.
0.004 MAX.
0.006
0.041
0.640
0.555
0.030
0.008
Ref. 80-Pin ETQFP (GP00-D537)
Millimeters Inches
Min. Max. Min. Max.
100604_015
CN8331/CN8332/CN8333 2.0 Functional Description
Single/Dual/Triple E3/DS3/STS-1 Lin e Interface Unit 2.6 Electri cal Charact eristi c s
100604B Conexant 2-15
Preliminary Information/Conexant Proprietary and Confidential
2.6 Electrical Characteristics
2.6.1 Absolute Maximum Ratings
Table 2-1. Absolute Maximum Ratings
Symbol Parameter Min Max Unit
DVDDC
RVDD
TVDD
VDD
Powe r Supp ly Voltage –0.3 6 V
VIVoltage on Any Sig nal
Pin –1.0 VGG + 0.3 V V
TST Storage Temperatu r e –40 125 °C
TVSOL Vapor Phase Soldering
Temperature (1 min.) —220 °C
θJA Thermal Resistance (Still
air, socketed) —40 °C/W
θJA Thermal Resistance (Still
air, soldered) —24 °C/W
θJc ——7.40 °C/W
FIT Failures in t ime @
89,000 device hours,
temperature of 55 °C,
0 failures.
—313 fits
NOTE(S):
1. Stresses above those listed as abs olute maximum rat ings may cause permanent da mage
to the device. This is a stress rating only, and functional operation of the device at these or
any other conditions beyond thos e indicated in the ot her sections of th is document is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
devic e reliability.
2.0 Functional Descriptio n CN8331/CN8332/CN8333
2.6 Ele ctr ic al Character i stics Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2-16 Conexant 100604B
Preliminary Information/Conexant Proprietary and Confidential
2.6.2 Recommended Operating Conditions
Table 2-2 specifies various operating conditions, power supplies, and the bias
resistor.
Table 2-2. Recommended Operating Conditions
Parameter Conditions Min Nom Max Unit
Power supply
voltage DVDDC, RVD D, TVDD ,
VDD 3.135 3.3 3.465 V
ESD vo ltage(1) VGG 3.135 5 5.5 V
Power dissipation
(CN8333) Total ch ip —0.83 1.0 W
Power dissipation
(CN8332) Total ch ip ——0.8 W
Power dissipation
(CN8331) Total ch ip ——.450 W
Externa l bias
resistor Pin RBIAS to GND; ±1 % 11.98 12.1 12.22 kΩ
NOTE(S):
(1) With 5 V lo gic i nput, VGG should be tied to 5 V. Wit h 3.3 V logic i nput, VGG s hould be tied
to 3.3 V.
CN8331/CN8332/CN8333 2.0 Functional Description
Single/Dual/Triple E3/DS3/STS-1 Lin e Interface Unit 2.7 D C Characteri stics
100604B Conexant 2-17
Preliminary Information/Conexant Proprietary and Confidential
2.7 DC Characteristics
Tabl e 2-3. DC Characteristics
Parameter Conditions Min Nom Max Unit
Vih high threshold Digital inputs 2.0 —VGG + 0.3 V
Vil low threshold Digital inputs –0.3 —0.8 V
Voh high threshold Digital outputs,
Ioh = –4 mA 2.4 ——V
Vol low threshold Digital outputs,
Iol = 4 mA —— 0.4 V
ILEAK 0 V ≤ digita l
Vin ≤ VGG –10 —200 µA
Input capacitance ———10 pF
Load capacitance Digi tal outputs —— 15 pF
NOTE(S):
1. The digita l inputs of CN833x are TTL 5 V compliant. These inputs are diode protected to
DVDDIO and DVSSIO pins. Additionally, all of the CN8331/CN8332/CN8333 digital inputs
contain 75 kΩ pull-down resistors.
2. The digital outputs of CN8331/CN8332/CN8333 are also TTL 5 V compliant. However,
these outputs will not drive to 5 V, nor will they accept 5 V external pullups. The output is
DVDDC (3.3 V).
2.0 Functional Descriptio n CN8331/CN8332/CN8333
2.8 AC Chara ct eris ti cs Single/Dual/Tr iple E3/DS3/STS-1 Line Interface Unit
2-18 Conexant 100604B
Preliminary Information/Conexant Proprietary and Confidential
2.8 AC Characteristics
Table 2-4. AC Characteristics (Logic Timing)
Parameter Conditions Min Nom Max Unit
Tosym , Tisym
RCLK and TC LK E3
DS-3
STS-1
—29.10
22.35
19.29
—ns
ns
ns
Cloc k D uty Cycle Towi dth/Tosym, R CLK
Tiwidth/Tisym, TCLK
Tiwidth/Tisym, REFCLK
45
40
40
—55
60
60
%
%
%
Todelay 5 ns
Tisetup TPOS/TNRZ, TNEG,
TAIS 4——ns
Tiho ld TPOS/TNRZ , TNE G,
TAIS 0——ns
NOTE(S):
1. The description applies to the DS3, E3, and STS-1 clock rates and other parameters such
as pu lse width, set-up time, hold time, and dut y cycle.
2. The timin g di ag r a m, illust r ated in Figure 2-9, describes the logical relationship between
various clock and da ta signals, and parameter values.
CN8331/CN8332/CN8333 2.0 Functional Description
Single/Dual/Triple E3/DS3/STS-1 Lin e Interface Unit 2. 8 AC Charac teristics
100604B Conexant 2-19
Preliminary Information/Conexant Proprietary and Confidential
Figure 2-9. Timing Diagram
TCLK
TPOS/TNRZ,
TNEG, TAIS,
Tisym
Tisetup Tihold
DATA INPUTS
Don't
Care Valid Data
Tiwidth
RCLK
RPOS/RNRZ,
RNEG/RLCV
Tosym
Todelay
DATA OUTPUTS
Towidth
Don't
Care
100604_016
2.0 Functional Descriptio n CN8331/CN8332/CN8333
2.8 AC Chara ct eris ti cs Single/Dual/Tr iple E3/DS3/STS-1 Line Interface Unit
2-20 Conexant 100604B
Preliminary Information/Conexant Proprietary and Confidential
100604B Conexant 3-1
Preliminary Information/Conexant Proprietary and Confidential
3
3.0 Applicatio ns
The CN8331/CN8332/CN8333 can be used in a variety of applications.
Figure 3-1 illustrates an example of three DS3 lines being terminated by the
CN8333. The data and clock are extracted and passed on to the framer chip for
further data manipulation and user interface.
It is i mportant to employ high-frequ ency design technique s for the pri nted
board layout.
3.1 PCB Design Considerations for
CN8331/CN8332/CN8333
The CN8333 device is a triple LIU operating at frequencies up to 52 MHz. The
high-speed nature of the device calls for a careful design of the PCB using this
part. Some design considerations are outlined below.
3.1.1 Power Supply and Ground Plane
A unified power plane with properly placed capacitors of the correct size will
mitigate most power rail-related voltage transients. A properly placed bulk
capacitor, where the power enters the board, with noise-bypassing capacitors at
the powe r pins on the i ntegrated circui ts sho uld be adequ ate. T he noise-b yp assing
capacitors must be able to supply all the swi tching current.
Ferrite beads are used with power rails to filter the high-frequency noise. For
e v ery design, noise f reque ncies and le v els ar e dif fe rent. Th erefore, whether beads
are necessary, and the effective frequency where they should operate, is difficult
to determine. It is a good idea to provision for ferrite beads on the boards.
The board trace from the CN8333 power supply pin to the noise-bypassing
capacitor should be minimized. Additionally, ground connections from the
ground plane to the CN8333 ground pins and the noise-bypassing capacitor
ground pins should be minimized.
A unified ground plane is the best way to minimize ground impedance. Most
of th e ground noise i s produced by the return currents and p o w er suppl y transient s
during switching. This effect is minimized by reducing the ground plane
impedance.
3.0 Applic at i ons CN8331/CN8332/CN8333
3.1 PCB Design Considerations for CN8331/CN8332/CN8333 Single/Dual/Triple E3/DS3/ST S-1 Line Interface Unit
3-2 Conexant 100604B
Preliminary Information/Conexant Proprietary and Confidential
3.1.2 Impedance Matching
It is critical that traces around the transformers and matching resistors be kept to a
minimum length and, in the following cases, the trace impedance be matched to
75 Ω:
•The impedance from the BNC connector to the transformer
•The impedance from the transform er to the matching resi stors
3.1.3 Other Passive Parts
The reference design uses the Pulse T3001 extended temperature range 1:1
transformer for the coupling of the BNC connector to the device.
The ferrite beads used t o decouple the recei ve- and t ransmit-VDD pins and the
ferrite beads on all analog input VDD pins are type 2508056017Y0 from
Fair-Rite. The bulk capacitor used for where the power enters the board can be a
electrolytic or tantulum type capacitor, the recommended value and type is a
220µf tantulum capacitor.
3.1.4 IBIS Models
IBIS (Input/Output Buffer Interface Specification) models for the
CN8331/CN8332/CN8333 are available from Conexant.
3.1.5 Recommended Vendors
Part #
T3001, Data Sheet - T619
America
Address:
Telo:
Fax:
Pulse
Corporate Of fice
12220 Wor ld Trade Drive
San Diego, CA 92128
858-674-8100
858-674-8262 Telo:
Fair-Rite Produ cts Corp.
P.O. Box J
One Commercial Row
Wallkil l, NY 12589
914-895-2055
Northern Asia
Telo:
Pulse
3F-4, No. 81, Sec. 1
Hsin Tai Wu Road
Hsi-Chih
Tapei Hs ien, Taiwan
R.O.C.
886-2-26980228
886-2-26980948
Northern Europe
Telo:
Fax:
Pulse
1S2 Huxley Road
The Surrey Research Park
Guildford, Surrey GU2 5RE
United Kingdom
44-1483-401700
44-1483-401701
CN8331/CN8332/CN8333 3.0 Applicatio ns
Single/Dual/Triple E3/DS3/STS-1 Lin e Interface Unit 3. 1 PCB Design Considerations for CN8331/CN8332/CN8333
100604B Conexant 3-3
Preliminary Information/Conexant Proprietary and Confidential
Figure 3-1. Typical Connection of CN8333
NOTE(S):
All transformers are part number T3001 from Pulse Technology. (See Recommended Vendors, page 3.2.)
TX
TPOS
TNEG
TCLK
TLINEP
TLINEM
RX
RLINEP
RNEG RLINEM
RPOS
RCLK
MODE BIAS RESET
Channel 1
CN8333
Framer
37.4
W
37.4
W
31.6
W
31.6
W
0.01µF
1:1
1:1
Type 728, 734, 735
75
W
Type 728, 734, 735
75
W
TX
TPOS
TNEG
TCLK TLINEM
RX
RLINEP
RNEG RLINEM
RPOS
RCLK
MODE BIAS RESET
Channel 2
TLINEP
TLINEP
Framer
37.4
W
37.4
W
31.6
W
31.6
W
0.01µF
1:1
1:1
Type 728, 734, 735
75
W
Type 728, 734, 735
75
W
TX
TPOS
TNEG
TCLK TLINEM
RX
RLINEP
RNEG RLINEM
RPOS
RCLK
MODE BIAS RESET
Channel 2
Framer
37.4
W
37.4
W
31.6
W
31.6
W
0.01µF
1:1
1:1
Type 728, 734, 735
75
W
Type 728, 734, 735
75
W
MODE BIAS RESET
RBIAS 12.1K
W
Mode/Status Pins
100604_004
3.0 Applic at i ons CN8331/CN8332/CN8333
3.1 PCB Design Considerations for CN8331/CN8332/CN8333 Single/Dual/Triple E3/DS3/ST S-1 Line Interface Unit
3-4 Conexant 100604B
Preliminary Information/Conexant Proprietary and Confidential
100604B Conexant A-1
Preliminary Information/Conexant Proprietary and Confidential
A
Appendix A
A.1 Applicable Standards
The applicable standards documents are as follows:
•ANSI T1.102-1993 (DS3 and STS-1 standard)
•ANSI T1.404a-1996 (DS3 metallic interface)
•ITU Recommendation G.703 (DS3 and E3 standard)
•ITU Recommendation G.823 and G.824 (jitter and wander)
•Bellcore GR499, Issue 1, 12/89 (formerly TR-TSY-000499)
(DS3 and STS-1 requirements)
•Bellcore GR253, Issue 2, 12/91 (formerly TA-NWT-000253)
(STS-1 requirements and jitter)
•Bellcore TR-TSY-000191, Issue 1, 5/86 (AIS and LOS)
•ETSI TBR24 and TBR25 (E3 terminal equipment interface)
•ETSI ETS 300 686 and ETS 300 687 (E3 standard)
•AT&T Technical Reference TR54014, May 1992 (Accunet Interface
Specification for DS-3 jitter only)
Appendix A CN8331/CN8332/CN8333
A.1 Applicable Standards Single/Dual/Tr iple E3/DS3/STS-1 Line Interface Unit
A-2 Conexant 100604B
Preliminary Information/Conexant Proprietary and Confidential
100604B Conexant B-1
Preliminary Information/Conexant Proprietary and Confidential
B
Appendix B
B.1 Evaluation Module Schematic
Appendix B CN8331/CN8332/CN8333
B.1 Evaluation Module Schematic Single/Dual/Tr iple E3/DS3/STS-1 Line Interface Unit
B-2 Conexant 100604B
Preliminary Information/Conexant Proprietary and Confidential
Figure B-1. Recommended Schematic for the CN833x Device
Position 7 REQH(1=Enable Equalization 0=Disable)
Pin 2 E3MODE 1=E3 mode is enabled 0=Disabled
Pin 1 ENDECDIS 1=Dual rail pulse coded data format
SOCKET
SOCKET
CHANNEL 3 RECEIVE
CHANNEL 3 TRANSMIT
CHANNEL 2 RECEIVE
DECODER AND E3 SELECTION
CHANNEL 1 RECEIVE
CHANNEL 1 TRANSMIT
CHANNEL 2 TRANSMIT
Position 1 PDB POWERDOWN (0=Powerdown 1=Active)
Position 2 RLOOP (1=Remote LPBK Enabled 0=Disabled)
Position 3 LLOOP (1=Local Loop Enabled 0=Disabled)
Position 4 LBO (1=TX CABLE less than 250ft 0=greater than 250ft)
Position 5 XOE (1=Transmitter Enabled 0=Disabled)
Position 6 TAIS (1=Enable AIS operation 0=disable)
DIGITAL GND
BNC
BNC
BNC
BNC
BNC
CC
CC
CC
CC
CC
CC
CC
BNC
CC
ANALOG GND
CCCC
CC
CC
CC
CC
CC
2 Pin DIP Switch Setting
Seven Position DIP Switch Settings for all Channels
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CH1_LOS
CH2_LOS
CH3_LOS
7
8
9
6
5
4
3
2
12
11
10
1
SW5
N1
T3001
PULSE
1
2
34
5
6
L2
T3001
PULSE
1
2
34
5
6
L3
1
2
34
5
6
T3001
PULSE
6
5
43
2
1
L4
1
2
34
5
6
T3001
PULSE
6
5
43
2
1
L5
1
2
34
5
6
T3001
PULSE
1
2
34
5
6
L6
J2
J3
J4
J5
J6
R3
37.4
37.4
R4
R7
37.4
37.4
R8
0.01
C2
R11
37.4
0.01
C3
R12
37.4
J1
T3001
PULSE
6
5
43
2
1
L1
1
23
44
32
1
SW4
J8
J9
J10
14
87
1
Y1
21 CR3
C1 0.01
31.6
R1
R2
31.6
31.6
R5
31.6
R9
31.6
R10
L15
L7
L11 L10
C4
0.10.1
C5
R6
31.6
L13
L12
C6
0.1
0.1
C7
L14
C8
0.1
12.1K
R13
CR1
12
CR2 SW9
C9
0.1
510
3
4
6
8
9
11
1
2
7
13
12
14 SW1
510
3
4
6
8
9
11
1
2
7
13
12
14
SW2
510
3
4
6
8
9
11
1
2
7
13
12
14 SW3
R14
402
402
R15
402
R16
1/4
42.2
R17
C10
0.1
L16
L17
C11
0.1
60
73
41
28
43
59
31
72
44
29
74
56
27
76
58
25
80
67
53
34
65
47
36
70
46
7
6
15
14
23
22
75
57
26
66
52
35
69
55
32 68
54
33
5
13
21
8
16
24
61
51
40 62
3
2
11
10
19
18
78
77
42
64
63
49
38
4
12
20
1
9
17
79
71
45
30
80EXFP
CN8333
50
48
39
37
U1
0.1
C12
C13
0.1
2
3
1
J7
TAIS3/TMUXA4
XOE3
LBO3
LLOOP3
PDB3
RLOOP3
+3_3V
TAIS1/TMUXA2
XOE1
LBO1
LLOOP1
PDB1
RLOOP1
+3_3V
RLOS1
RLOS2
RLOS3
GND
NC
OUT
VCC
+3_3V
+3_3V
+3_3V
+3_3V+3_3V
+3_3V
+3_3V
+5V
TMUXIO1
TMUXIO2
PDB1
RLOOP1
LLOOP1
LBO1
XOE1
REQH1/TMUXDAT
RNEG1/RLCV1
RPOS1/RNRZ1
RCLK1
RLOS1
REFCLK
TNEG1/NC1
TPOS1/TNRZ1
TCLK1
TAIS1/TMUXA2
PDB2
RLOOP2
LLOOP2
RNEG2/RLCV2
RPOS2/RNRZ2
RCLK2
RLOS2
TAIS2/TMUXA3
TPOS2/TNRZ2
REFCLK
REQH2/TMUXA0
XOE2
LBO2
TMUXLAT
PDB3
RLOOP3
LLOOP3
LBO3
XOE3
REQH3/TMUXA1
RNEG3/RLCV3
RPOS3/RNRZ3
RCLK3
RLOS3
REFCLK
TPOS3/TNRZ3
TAIS3/TMUXA4
+3_3V
+3_3V
+3_3V +3_3V
+3_3V
RLOOP2
PDB2
LLOOP2
LBO2
XOE2
TAIS2/TMUXA3
E3MODE
ENDECDIS
ENDECDIS
E3MODE
REQH1/TMUXDAT REQH2/TMUXA0
REQH3/TMUXA1
TMUXLAT
REFCLK
+3_3V
DVDD
DVDD2
DVSS
DVSS2
E3MODE
ENDECDIS
REQH3/TMUXA1
LBO1
LBO2
LBO3
LLOOP1
LLOOP2
LLOOP3
PDB1
PDB2
PDB3
RBIAS
RCLK1
RCLK2
RCLK3
REFCLK1
REFCLK2
REFCLK3
REQH1/TMUXDAT
REQH2/TMUXA0
RLINE1M
RLINE1P
RLINE2M
RLINE2P
RLINE3M
RLINE3P
RLOOP1
RLOOP2
RLOOP3
RLOS1
RLOS2
RLOS3
RNEG1/RLCV1
RNEG2/RLCV2
RNEG3/RLCV3 RPOS1/RNRZ1
RPOS2/RNRZ2
RPOS3/RNRZ3
RVDD1
RVDD2
RVDD3
RVSS1
RVSS2
RVSS3
TAIS1/TMUXA2
TAIS2/TMUXA3
TAIS3/TMUXA4 TCLK1
TLINE1M
TLINE1P
TLINE2M
TLINE2P
TLINE3M
TLINE3P
TMUXIO1
TMUXIO2
TMUXLAT
TNEG1/NC1
TPOS1/TNRZ1
TPOS2/TNRZ2
TPOS3/TNRZ3
TVDD1
TVDD2
TVDD3
TVSS1
TVSS2
TVSS3
VGG
XOE1
XOE2
XOE3
TCLK2
TNEG2/NC2
TCLK3
TNEG3/NC3
TCLK2
TNEG2/NC2
TCLK3
TNEG3/NC3
+3_3V
REQH2/TMUXA0
REQH3/TMUXA1
TAIS1/TMUXA2
TAIS2/TMUXA3
TAIS3/TMUXA4
REQH1/TMUXDAT
8333_027
Further Information:
literature@conexant.com
1-800-854-8099 (North America)
33-14-906-3980 (International)
Web Site
www.conexant.com
World Hea dquarters
Conexant Systems, Inc.
4311 Jamboree Road,
P.O. Box C
Newport Beach, CA 92658-8902
Phone: (949) 483-4600
Fax: (949) 483-6375
U.S. Florida/ South America
Phone: (727) 799-8406
Fax: (727) 799-8306
U.S. Los Angele s
Phone: (805) 376-0559
Fax: (805) 376-8180
U.S. Mid-Atlantic
Phone: (215) 244-6784
Fax: (215) 244-9292
U.S. North Central
Phone: (630) 773-3454
Fax: (630) 773-3907
U.S. Northeast
Phone: (978) 692-7660
Fax: (978) 692-8185
U.S. Northwest/Pacific West
Phone: (408) 249-9696
Fax: (408) 249-7113
U.S. South Central
Phone: (972) 733-0723
Fax: (972) 407-0639
U.S. Southeast
Phone: (919) 858-9110
Fax: (919) 858-8669
U.S. Southwest
Phone: (949) 483-9119
Fax: (949) 483-9090
APAC Headquarters
Conexant Systems Singapore,
Pte. Ltd.
1 Kim Seng Promenade
Great World City
#09-01 East Tower
Singapore 237994
Phone: (65) 737 7355
Fax: (65) 737 9077
Australia
Phone: (61 2) 9869 4088
Fax: (61 2) 9869 4077
China
Phone: (86 2) 6361 2515
Fax: (86 2) 6361 2516
Hong Kong
Phone: (852) 2 827 0181
Fax: (852) 2 827 6488
India
Phone: (91 11) 692 4780
Fax: (91 11) 692 4712
Korea
Phone: (82 2) 565 2880
Fax: (82 2) 565 1440
Europe Headquarte rs
Conexant Systems France
Les Taissounieres B1
1681 Route des Dolines
BP 283
06905 Sophia An tipolis Cedex
France
Phone: (33 4) 93 00 33 35
Fax: (33 4) 93 00 33 03
Europe Central
Phone: (49 89) 829 1320
Fax: (49 89) 834 2734
Europe Mediterranean
Phone: (39 02) 9317 9911
Fax: (39 02) 9317 9913
Europe North
Phone: (44 1344) 486 444
Fax: (44 1344) 486 555
Europe South
Phone: (33 1) 41 44 36 50
Fax: (33 1) 41 44 36 90
Middle E ast Headquarters
Conexant Systems
Commercial (Israel) Ltd.
P.O. Box 12660
Herzlia 46733, Israel
Phone: (972 9) 952 4064
Fax: (972 9) 951 3924
Japa n He adquarter s
Conexant Systems Japan Co., Lt d.
Shimomoto Buildin g
1-46-3 Hatsudai,
Shibuya-ku, Tokyo
151-0061 Japan
Phone: (81 3) 5371 1567
Fax: (81 3) 5371 1501
Taiwan Headquarters
Conexant Systems, Taiwan Co., Ltd.
Room 2808
International Trade Building
333 Keelung Road, Section 1
Taipei 110, Taiwan, ROC
Phone: (886 2) 2720 0282
Fax: (886 2) 2757 6760
0
.
0
Sa
l
es
Offi
ces
