INTEGRATED CIRCUITS 74LVC16373A/74LVCH16373A 16-bit D-type transparent latch with 5 Volt tolerant inputs/outputs (3-State) Product specification Supersedes data of 1997 Aug 22 IC24 Data Handbook 1998 Mar 17 Philips Semiconductors Product specification 74LVC16373A/ 74LVCH16373A 16-bit D-type transparent latch with 5 Volt tolerant inputs/outputs (3-State) FEATURES PIN CONFIGURATION * 5 volt tolerant inputs/outputs for interfacing with 5V logic * Wide supply voltage range of 1.2V to 3.6V * Complies with JEDEC standard no. 8-1A * CMOS low power consumption * MULTIBYTETM flow-through standard pin-out architecture * Low inductance multiple power and ground pins for minimum 1OE 1 48 1LE 1Q0 2 47 1D0 1Q1 3 46 1D1 GND 4 45 GND 1Q2 5 44 1D2 1Q3 6 43 1D3 VCC 7 42 VCC 1Q4 8 41 1D4 1Q5 9 40 1D5 noise and ground bounce * Direct interface with TTL levels * All data inputs have bus hold (74LVCH167373A only) * High impedance when VCC = 0 DESCRIPTION The 74LVC(H)16373A is a 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. One latch enable (LE) input and one output enable (OE) are provided for each octal. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. These features allow the use of these devices in a mixed 3.3V/5V environment. The 74LVC(H)16373A consists of 2 sections of eight D-type transparent latches with 3-State true outputs. When LE is HIGH, data at the Dn inputs enter the latches. In this condition the latches are transparent, i.e., a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches. GND 10 39 GND 1Q6 11 38 1D6 1Q7 12 37 1D7 2Q0 13 36 2D0 2Q1 14 35 2D1 GND 15 34 GND 2Q2 16 33 2D2 2Q3 17 32 2D3 VCC 18 31 VCC 2Q4 19 30 2D4 2Q5 20 29 2D5 GND 21 28 GND 2Q6 22 27 2D6 2Q7 23 26 2D7 2OE 24 25 2LE SW00066 The 74LVCH16373A bus hold data inputs eliminates the need for external pull up resistors to hold unused inputs. QUICK REFERENCE DATA GND = 0V; Tamb = 25C; tr = tf 2.5ns PARAMETER SYMBOL tPHL/tPLH Propagation delay Dn to Qn LE to Qn CI Input capacitance CPD Power dissipation capacitance per latch CONDITIONS TYPICAL UNIT 3.0 3.4 ns 5.0 pF 26 pF CL = 50pF VCC = 3.3V VCC = 3.3V NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL x VCC2 x fo) = sum of outputs. ORDERING INFORMATION TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 48-Pin Plastic SSOP Type III PACKAGES -40C to +85C 74LVC16373A DL VC16373A DL SOT370-1 48-Pin Plastic TSSOP Type II -40C to +85C 74LVC16373A DGG VC16373A DGG SOT362-1 48-Pin Plastic SSOP Type III -40C to +85C 74LVCH16373A DL VCH16373A DL SOT370-1 48-Pin Plastic TSSOP Type II -40C to +85C 74LVCH16373A DGG VCH16373A DGG SOT362-1 1998 Mar 17 2 853-2027 19112 Philips Semiconductors Product specification 74LVC16373A/ 74LVCH16373A 16-bit D-type transparent latch with 5 Volt tolerant inputs/outputs (3-State) PIN DESCRIPTION LOGIC SYMBOL PIN NUMBER SYMBOL 1 1OE Output enable input (active LOW) 2, 3, 5, 6, 8, 9, 11, 12 1Q0 to 1Q7 Data inputs/outputs 4, 10, 15, 21, 28, 34, 39, 45 GND 7, 18, 31, 42 VCC 13, 14, 16, 17, 19, 20, 22, 23 2Q0 to 2Q7 24 2OE 25 2LE 36, 35, 33, 32, 30, 29, 27, 26 47, 46, 44, 43, 41, 40, 38, 37 2D0 to 2D7 1D0 to 1D7 48 1LE NAME AND FUNCTION Ground (0V) Positive supply voltage Data inputs/outputs Output enable input (active LOW) Latch enable input (active HIGH) Data inputs Data inputs Latch enable input (active HIGH) 1 24 1OE 2OE 47 1D0 1Q0 2 46 1D1 1Q1 3 44 1D2 1Q2 5 43 1D3 1Q3 6 41 1D4 1Q4 8 40 1D5 1Q5 9 38 1D6 1Q6 11 37 1D7 1Q7 12 36 2D0 2Q0 13 35 2D1 2Q1 14 33 2D2 2Q2 16 32 2D3 2Q3 17 30 2D4 2Q4 19 29 2D5 2Q5 20 27 2D6 2Q6 22 26 2D7 2Q7 23 1LE 2LE 48 25 SW00067 LOGIC DIAGRAM 1D0 D Q 1Q0 D 2D0 LATCH 1 LE Q 2Q0 LATCH 9 LE LE 1LE 2LE 1OE 2OE TO 7 OTHER CHANNELS LE TO 7 OTHER CHANNELS SW00068 FUNCTION TABLE (per section of eight bits) INPUTS OPERATING MODES INTERNAL LATCHES OUTPUTS OE LE Dn enable and read register (transparent mode) L L H H L H L H L H latch and read register L L L L l h L H L H latch register and disable outputs H H L L l h L H Z Z H h L l X Z = HIGH voltage level = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition = LOW voltage level = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition = don't care = high impedance OFF-state 1998 Mar 17 3 Q0 to Q7 Philips Semiconductors Product specification 74LVC16373A/ 74LVCH16373A 16-bit D-type transparent latch with 5 Volt tolerant inputs/outputs (3-State) LOGIC SYMBOL (IEEE/IEC) 1OE 1 1EN C3 1LE 48 2OE 25 2LE 24 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 47 BUS HOLD CIRCUIT VCC 2EN C4 2 1Q0 46 3 1Q1 44 5 1Q2 43 6 1Q3 41 8 1Q4 40 9 38 11 1Q6 37 12 1Q7 13 2Q0 35 14 2Q1 33 16 2Q2 32 17 2Q3 30 19 2Q4 29 20 2Q5 27 22 2Q6 26 23 36 1 3D 2 4D Data Input To internal circuit 1Q5 SW00044 2Q7 SW00069 RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VO Tamb tr, tf 1998 Mar 17 PARAMETER CONDITIONS LIMITS UNIT MIN MAX DC supply voltage (for max. speed performance) 2.7 3.6 DC supply voltage (for low-voltage applications) 1.2 3.6 DC input voltage range 0 5.5 DC input voltage range; output HIGH or LOW state 0 VCC DC output voltage range; output 3-State 0 5.5 -40 +85 C 0 0 20 10 ns/V Operating free-air temperature range VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V Input rise and fall times 4 V V V Philips Semiconductors Product specification 74LVC16373A/ 74LVCH16373A 16-bit D-type transparent latch with 5 Volt tolerant inputs/outputs (3-State) ABSOLUTE MAXIMUM RATINGS1 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V). SYMBOL VCC PARAMETER CONDITIONS RATING -0.5 to +6.5 V IIK DC input diode current VI 0 -50 mA VI DC input voltage Note 2 -0.5 to +6.5 V IOK DC output diode current VO VCC or VO 0 50 mA DC output voltage; output HIGH or LOW state Note 2 -0.5 to VCC +0.5 DC output voltage; output 3-State Note 2 -0.5 to 6.5 DC output source or sink current VO = 0 to VCC VO IO IGND, ICC Tstg DC supply voltage UNIT 50 mA 100 mA -65 to +150 C DC VCC or GND current Storage temperature range V Power dissipation per package PTOT - plastic mini-pack (SO) above +70C derate linearly with 8 mW/K 500 - plastic shrink mini-pack (SSOP and TSSOP) above +60C derate linearly with 5.5 mW/K 500 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40C to +85C MIN VIH HIGH level Input In ut voltage VIL Input LOW level In ut voltage VOH O VOL HIGH level output voltage LOW level output voltage VCC = 1.2V VCC VCC = 2.7 to 3.6V 2.0 TYP1 V VCC = 1.2V GND VCC = 2.7 to 3.6V 0.8 VCC = 2.7V; VI = VIH or VIL; IO = -12mA VCC0.5 VCC = 3 3.0V; 0V; VI = VIH or VIL; IO = -100A 100A VCC0.2 02 VCC = 3.0V; VI = VIH or VIL; IO = -18mA VCC0.6 VCC = 3.0V; VI = VIH or VIL; IO = -24mA VCC0.8 V V 0.40 VCC = 3.0V; VI = VIH or VIL; IO = 100A 0.20 VCC = 3.0V; VI = VIH or VIL; IO = 24mA VCC = 3.6V; VI = 5.5V or GND6 IOZ 3-State output OFF-state current VCC = 3.6V; VI = VIH or VIL; VO = 5.5V or GND Ioff Power off leakage supply VCC = 0.0V; VI or VO = 5.5V ICC Quiescent supply current VCC = 3.6V; VI = VCC or GND; IO = 0 Additional quiescent supply current per input pin VCC = 2.7V to 3.6V; VI = VCC -0.6V; IO = 0 ICC 1998 Mar 17 5 V VCC VCC = 2.7V; VI = VIH or VIL; IO = 12mA Input leakage current II UNIT MAX V 0.55 0.1 5 A 0.1 5 A 10 A 0.1 20 A 5 500 A Philips Semiconductors Product specification 74LVC16373A/ 74LVCH16373A 16-bit D-type transparent latch with 5 Volt tolerant inputs/outputs (3-State) DC ELECTRICAL CHARACTERISTICS (Continued) Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40C to +85C MIN TYP1 UNIT MAX Bus hold LOW sustaining current VCC = 3.0V; VI = 0.8V2, 3, 4 75 A IBHH Bus hold HIGH sustaining current VCC = 3.0V; VI = 2.0V2, 3, 4 -75 A IBHLO Bus hold LOW overdrive current VCC = 3.6V2, 3, 5 500 A Bus hold HIGH overdrive current 3.6V2, 3, 5 -500 A IBHL IBHHO VCC = NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25C. 2. Valid for data inputs of bus hold parts (LVCH16-A) only. 3. For data inputs only, control inputs do not have a bus hold circuit. 4. The specified sustaining current at the data input holds the input below the specified VI level. 5. The specified overdrive current at the data input forces the data input to the opposite logic input state. 6. For bus hold parts, the bus hold circuit is switched off when Vi exceeds VCC allowing 5.5V on the input terminal. AC CHARACTERISTICS GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500; Tamb = -40C to +85C. LIMITS SYMBOL PARAMETER VCC = 3.3V 0.3V WAVEFORM VCC = 2.7V VCC = 1.2V MIN TYP1 MAX MIN MAX TYP UNIT tPHL tPLH Propagation delay Dn to Qn 1, 5 1.5 3.0 4.7 1.5 5.7 12 ns tPHL tPLH Propagation delay LE to Qn 2, 5 1.5 3.4 4.8 1.5 5.8 14 ns tPZH tPZL 3-State output enable time OE to Qn 4, 5 1.5 3.5 5.5 1.5 6.5 18 ns tPHZ tPLZ 3-State output disable time OE to Qn 4, 5 1.5 3.9 5.4 1.5 6.4 11 ns tW LE pulse width HIGH 2 3 2.0 - 3 - - ns tsu Set-up time Dn to LE 3 1.7 -0.1 - 1.7 - - ns th Hold time Dn to LE 3 1.2 0.1 - 1.2 - - ns NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25C. AC WAVEFORMS VM = 1.5V at VCC 2.7V; VM = 0.5 VCC at VCC 2.7V. VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3V at VCC 2.7V; VX = VOL + 0.1 VCC at VCC 2.7V VY = VOH -0.3V at VCC 2.7V; VY = VOH - 0.1 VCC at VCC 2.7V VI Dn INPUT VI LE INPUT VM VM VM VM VM GND GND tPHL tw tPHL tPLH Qn OUTPUT Qn OUTPUT VM VM VM VOL VOL SW00071 SW00070 Waveform 2. Latch enable input (LE) pulse width, the latch enable input to output (Qn) propagation delays Waveform 1. Input (Dn) to output (Qn) propagation delays 1998 Mar 17 tPLH VOH VOH 6 Philips Semiconductors Product specification 74LVC16373A/ 74LVCH16373A 16-bit D-type transparent latch with 5 Volt tolerant inputs/outputs (3-State) AC WAVEFORMS (Continued) TEST CIRCUIT VM = 1.5V at VCC 2.7V; VM = 0.5 VCC at VCC 2.7V. VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3V at VCC 2.7V; VX = VOL + 0.1 VCC at VCC 2.7V VY = VOH -0.3V at VCC 2.7V; VY = VOH - 0.1 VCC at VCC 2.7V 2VCC Open GND RL=500 VIN EEE EEEEEEEE EEE EEE EEEEEEEE EEE EEE EEEEEEEE EEE VOUT PULSE GENERATOR VI Dn INPUT S1 VCC D.U.T. RT VM RL=500 CL GND th th Test Circuit for 3-State Outputs tSU tSU VI SWITCH POSITION LE INPUT VM GND NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SW00073 VI VM SWITCH VCC VIN Open tPLZ/tPZL 2VCC 2.7V 2.7 - 3.6V VCC 2.7V tPHZ/tPZH GND DEFINITIONS RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators. Waveform 3. Data set-up and hold times for the Dn input to the LE input OE INPUT TEST tPLH/tPHL VM SW00047 Waveform 5. Load circuitry for switching times GND tPLZ tPZL VCC OUTPUT LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ tPZH VOH VY OUTPUT HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs disabled outputs enabled SW00072 Waveform 4. 3-State enable and disable times 1998 Mar 17 7 Philips Semiconductors Product specification 16-bit D-type transparent latch with 5 Volt tolerant inputs/outputs (3-State) SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm 1998 Mar 17 8 74LVC16373A/ 74LVCH16373A SOT370-1 Philips Semiconductors Product specification 16-bit D-type transparent latch with 5 Volt tolerant inputs/outputs (3-State) TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1mm 1998 Mar 17 9 74LVC16373A/ 74LVCH16373A SOT362-1 Philips Semiconductors Product specification 16-bit D-type transparent latch with 5 Volt Tolerant inputs/outputs (3-State) 74LVC16373A/ 74LVCH16373A DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. 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Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 10 Date of release: 05-96 9397-750-04533