74LVC16373A/74LVCH16373A
16-bit D-type transparent latch with 5 Volt
tolerant inputs/outputs (3-State)
Product specification
Supersedes data of 1997 Aug 22
IC24 Data Handbook
1998 Mar 17
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
74LVC16373A/
74LVCH16373A
16-bit D-type transparent latch with 5 Volt tolerant
inputs/outputs (3-State)
2
1998 Mar 17 853-2027 19112
FEATURES
•5 volt tolerant inputs/outputs for interfacing with 5V logic
•Wide supply voltage range of 1.2V to 3.6V
•Complies with JEDEC standard no. 8-1A
•CMOS low power consumption
•MULTIBYTETM flow-through standard pin-out architecture
•Low inductance multiple power and ground pins for minimum
noise and ground bounce
•Direct interface with TTL levels
•All data inputs have bus hold (74LVCH167373A only)
•High impedance when VCC = 0
DESCRIPTION
The 74LVC(H)16373A is a 16-bit D-type transparent latch featuring
separate D-type inputs for each latch and 3-State outputs for bus
oriented applications. One latch enable (LE) input and one output
enable (OE) are provided for each octal. Inputs can be driven from
either 3.3V or 5V devices. In 3-State operation, outputs can handle
5V. These features allow the use of these devices in a mixed
3.3V/5V environment.
The 74LVC(H)16373A consists of 2 sections of eight D-type
transparent latches with 3-State true outputs. When LE is HIGH,
data at the Dn inputs enter the latches. In this condition the latches
are transparent, i.e., a latch output will change each time its
corresponding D-input changes.
When LE is LOW the latches store the information that was present
at the D-inputs a set-up time preceding the HIGH-to-LOW transition
of LE. When OE is LOW, the contents of the eight latches are
available at the outputs. When OE is HIGH, the outputs go to the
high impedance OFF-state. Operation of the OE input does not
affect the state of the latches.
The 74LVCH16373A bus hold data inputs eliminates the need for
external pull up resistors to hold unused inputs.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20 29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
1OE
1Q0
1Q1
GND
1Q2
1Q3
VCC
1Q5
GND
1Q6
1Q7
2Q0
2Q1
GND
1Q4
2Q2
2Q3
VCC
2Q4
2Q5 2D5
2D4
VCC
2D3
2D2
GND
2D1
2D0
1D7
1D6
GND
1D5
1D4
VCC
1D3
1D2
GND
1D1
1D0
1LE
21
22
23
24 25
26
27
28
GND
2Q6
2Q7
2OE 2LE
2D7
2D6
GND
SW00066
QUICK REFERENCE DATA
GND = 0V ; Tamb = 25°C; tr = tf ≤ 2.5ns
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
tPHL/tPLH Propagation delay
Dn to Qn
LE to Qn CL = 50pF
VCC = 3.3V 3.0
3.4 ns
CIInput capacitance 5.0 pF
CPD Power dissipation capacitance per latch VCC = 3.3V 26 pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V ;
(CL × VCC2 × fo) = sum of outputs.
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
48-Pin Plastic SSOP Type III –40°C to +85°C74LVC16373A DL VC16373A DL SOT370-1
48-Pin Plastic TSSOP Type II –40°C to +85°C74LVC16373A DGG VC16373A DGG SOT362-1
48-Pin Plastic SSOP Type III –40°C to +85°C74LVCH16373A DL VCH16373A DL SOT370-1
48-Pin Plastic TSSOP Type II –40°C to +85°C74LVCH16373A DGG VCH16373A DGG SOT362-1
Philips Semiconductors Product specification
74LVC16373A/
74LVCH16373A
16-bit D-type transparent latch with 5 Volt tolerant
inputs/outputs (3-State)
1998 Mar 17 3
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
1 1OE Output enable input
(active LOW)
2, 3, 5, 6, 8, 9,
11, 12 1Q0 to 1Q7 Data inputs/outputs
4, 10, 15, 21,
28, 34, 39, 45 GND Ground (0V)
7, 18, 31, 42 VCC Positive supply voltage
13, 14, 16, 17,
19, 20, 22, 23 2Q0 to 2Q7 Data inputs/outputs
24 2OE Output enable input
(active LOW)
25 2LE Latch enable input (active
HIGH)
36, 35, 33, 32,
30, 29, 27, 26 2D0 to 2D7 Data inputs
47, 46, 44, 43,
41, 40, 38, 37 1D0 to 1D7 Data inputs
48 1LE Latch enable input (active
HIGH)
LOGIC SYMBOL
1OE 2OE
1LE 2LE
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
48 25
23
22
20
19
17
16
14
13
12
11
9
8
6
5
3
2
241
SW00067
LOGIC DIAGRAM
DQ
LE LE
LATCH
1
1D0
1LE
1OE
1Q0
TO 7 OTHER CHANNELS
DQ
LE LE
LATCH
9
2D0
2LE
2OE
2Q0
TO 7 OTHER CHANNELS
SW00068
FUNCTION TABLE (per section of eight bits)
OPERATING MODES
INPUTS INTERNAL OUTPUTS
OPERATING
MODES
OE LE Dn LATCHES Q0 to Q7
enable and read register
(transparent mode) L
LH
HL
HL
HL
H
latch and read register L
LL
Ll
hL
HL
H
latch register and disable outputs H
HL
Ll
hL
HZ
Z
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
X = don’t care
Z = high impedance OFF-state
Philips Semiconductors Product specification
74LVC16373A/
74LVCH16373A
16-bit D-type transparent latch with 5 Volt tolerant
inputs/outputs (3-State)
1998 Mar 17 4
LOGIC SYMBOL (IEEE/IEC)
SW00069
48 1EN
1 ∇
46
44
43
41
40
38
37
36
C3
C4
2EN
2 ∇4D
1
25
24
47
35
33
32
30
29
27
26
3
2
5
6
8
9
11
12
13
14
16
17
19
20
22
23
1OE
1LE
1D0
1D1
1D2
1D3
1D4
1D5
1D6
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q7
1D7
2Q5
2Q6
3D
2OE
2LE
BUS HOLD CIRCUIT
To internal circuit
VCC
Data Input
SW00044
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
CONDITIONS
MIN MAX
UNIT
VCC
DC supply voltage (for max. speed performance) 2.7 3.6
V
V
CC DC supply voltage (for low-voltage applications) 1.2 3.6
V
VIDC input voltage range 0 5.5 V
VO
DC input voltage range; output HIGH or LOW state 0 VCC
V
V
ODC output voltage range; output 3-State 0 5.5
V
Tamb Operating free-air temperature range –40 +85 °C
tr, tfInput rise and fall times VCC = 1.2 to 2.7V
VCC = 2.7 to 3.6V 0
020
10 ns/V
Philips Semiconductors Product specification
74LVC16373A/
74LVCH16373A
16-bit D-type transparent latch with 5 Volt tolerant
inputs/outputs (3-State)
1998 Mar 17 5
ABSOLUTE MAXIMUM RATINGS1
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC DC supply voltage –0.5 to +6.5 V
IIK DC input diode current VI0 –50 mA
VIDC input voltage Note 2 –0.5 to +6.5 V
IOK DC output diode current VO VCC or VO 0 50 mA
VO
DC output voltage; output HIGH or LOW state Note 2 –0.5 to VCC +0.5
V
V
ODC output voltage; output 3-State Note 2 –0.5 to 6.5
V
IODC output source or sink current VO = 0 to VCC 50 mA
IGND, ICC DC VCC or GND current 100 mA
Tstg Storage temperature range –65 to +150 °C
Power dissipation per package
PTOT – plastic mini-pack (SO) above +70°C derate linearly with 8 mW/K 500
mW
– plastic shrink mini-pack (SSOP and TSSOP) above +60°C derate linearly with 5.5 mW/K 500
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS
SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT
MIN TYP1MAX
VIH
HIGH level In
p
ut voltage
VCC = 1.2V VCC
V
V
IH
HIGH
level
In ut
voltage
VCC = 2.7 to 3.6V 2.0
V
VIL
LOW level In
p
ut voltage
VCC = 1.2V GND
V
V
IL
LOW
level
In ut
voltage
VCC = 2.7 to 3.6V 0.8
V
VCC = 2.7V ; VI = VIH or VIL; IO = –12mA VCC0.5 V
V=30V
;
V=V or V
;
I = 100µA
V02
V
VO
HIGH level out
p
ut voltage
V
CC =
3
.
0V
;
V
I =
V
IH
or
V
IL;
I
O = –
100
µ
A
V
CC
0
.
2
V
CC
V
OH
HIGH
le
v
el
o
u
tp
u
t
v
oltage
VCC = 3.0V ; V I = VIH or VIL; IO = –18mA VCC0.6 V
VCC = 3.0V ; V I = VIH or VIL; IO = –24mA VCC0.8
VCC = 2.7V ; VI = VIH or VIL;I
O = 12mA 0.40
VOL LOW level output voltage VCC = 3.0V; VI = VIH or VIL;I
O = 100µA 0.20 V
VCC = 3.0V ; VI = VIH or VIL; IO = 24mA 0.55
IIInput leakage current VCC = 3.6V; VI = 5.5V or GND60.1 5µA
IOZ 3-State output OFF-state current VCC = 3.6V ; VI = VIH or VIL;V
O = 5.5V or GND 0.1 5µA
Ioff Power of f leakage supply VCC = 0.0V; VI or VO = 5.5V 10 µA
ICC Quiescent supply current VCC = 3.6V ; VI = VCC or GND; IO = 0 0.1 20 µA
∆ICC Additional quiescent supply
current per input pin VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0 5 500 µA
Philips Semiconductors Product specification
74LVC16373A/
74LVCH16373A
16-bit D-type transparent latch with 5 Volt tolerant
inputs/outputs (3-State)
1998 Mar 17 6
DC ELECTRICAL CHARACTERISTICS (Continued)
Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS
SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT
MIN TYP1MAX
IBHL Bus hold LOW sustaining current VCC = 3.0V; VI = 0.8V2, 3, 475 µA
IBHH Bus hold HIGH sustaining current VCC = 3.0V ; V I = 2.0V2, 3, 4–75 µA
IBHLO Bus hold LOW overdrive current VCC = 3.6V2, 3, 5500 µA
IBHHO Bus hold HIGH overdrive current VCC = 3.6V2, 3, 5–500 µA
NOTES:
1. All typical values are at VCC = 3.3V and Tamb = 25°C.
2. Valid for data inputs of bus hold parts (LVCH16-A) only.
3. For data inputs only, control inputs do not have a bus hold circuit.
4. The specified sustaining current at the data input holds the input below the specified VI level.
5. The specified overdrive current at the data input forces the data input to the opposite logic input state.
6. For bus hold parts, the bus hold circuit is switched off when Vi exceeds VCC allowing 5.5V on the input terminal.
AC CHARACTERISTICS
GND = 0V ; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C.
LIMITS
SYMBOL PARAMETER WAVEFORM VCC = 3.3V ±0.3V VCC = 2.7V VCC = 1.2V UNIT
MIN TYP1MAX MIN MAX TYP
tPHL
tPLH Propagation delay
Dn to Qn 1, 5 1.5 3.0 4.7 1.5 5.7 12 ns
tPHL
tPLH Propagation delay
LE to Qn 2, 5 1.5 3.4 4.8 1.5 5.8 14 ns
tPZH
tPZL 3-State output enable time
OE to Qn 4, 5 1.5 3.5 5.5 1.5 6.5 18 ns
tPHZ
tPLZ 3-State output disable time
OE to Qn 4, 5 1.5 3.9 5.4 1.5 6.4 11 ns
tWLE pulse width HIGH 2 3 2.0 – 3 – – ns
tsu Set-up time Dn to LE 3 1.7 –0.1 – 1.7 – – ns
thHold time Dn to LE 3 1.2 0.1 – 1.2 – – ns
NOTE:
1. All typical values are at VCC = 3.3V and Tamb = 25°C.
AC WAVEFORMS
VM = 1.5V at VCC 2.7V ; VM = 0.5 VCC at VCC 2.7V.
VOL and VOH are the typical output voltage drop that occur with the output load.
VX = VOL + 0.3V at VCC 2.7V ; VX = VOL + 0.1 VCC at VCC 2.7V
VY = VOH –0.3V at VCC 2.7V; VY = VOH – 0.1 VCC at VCC 2.7V
SW00070
Dn INPUT VM
tPHL tPLH
VOL
VI
VM
GND
VOH
Qn OUTPUT
VM
W aveform 1. Input (Dn) to output (Qn) propagation delays
VMVMVM
VM
tw
tPHL tPLH
LE INPUT
Qn OUTPUT
SW00071
VI
GND
VOH
VOL
VM
W aveform 2. Latch enable input (LE) pulse width, the latch
enable input to output (Qn) propagation delays
Philips Semiconductors Product specification
74LVC16373A/
74LVCH16373A
16-bit D-type transparent latch with 5 Volt tolerant
inputs/outputs (3-State)
1998 Mar 17 7
AC WAVEFORMS (Continued)
VM = 1.5V at VCC 2.7V ; VM = 0.5 VCC at VCC 2.7V.
VOL and VOH are the typical output voltage drop that occur with the
output load.
VX = VOL + 0.3V at VCC 2.7V ; VX = VOL + 0.1 VCC at VCC 2.7V
VY = VOH –0.3V at VCC 2.7V; VY = VOH – 0.1 VCC at VCC 2.7V
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
VM
Dn
INPUT
VM
LE
INPUT
tSU
th
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
SW00073
tSU
th
VI
GND
VI
GND
W aveform 3. Data set-up and hold times for the Dn input to the
LE input
tPLZ tPZL
VI
OE INPUT
GND
VCC
OUTPUT
LOW-to-OFF
OFF-to-LOW
VOL
VOH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND outputs
enabled outputs
enabled
outputs
disabled
tPHZ
VM
VM
VM
tPZH
VX
VY
SW00072
VM
W aveform 4. 3-State enable and disable times
TEST CIRCUIT
PULSE
GENERATOR
RT
VIN D.U.T.
VOUT
CL
VCC
RL=500 Ω
SWITCH POSITION
TEST SWITCH
tPLH/tPHL Open
tPLZ/tPZL 2VCC
tPHZ/tPZH GND
Test Circuit for 3-State Outputs
Open
GND
S12VCC
DEFINITIONS
VCC
2.7V
2.7 – 3.6V
VIN
VCC
2.7V
RL =Load resistor
CL = Load capacitance includes jig and probe capacitance
RT =Termination resistance should be equal to ZOUT
of pulse generators.
SW00047
RL=500 Ω
W aveform 5. Load circuitry for switching times
Philips Semiconductors Product specification
74LVC16373A/
74LVCH16373A
16-bit D-type transparent latch with 5 Volt tolerant
inputs/outputs (3-State)
1998 Mar 17 8
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1
Philips Semiconductors Product specification
74LVC16373A/
74LVCH16373A
16-bit D-type transparent latch with 5 Volt tolerant
inputs/outputs (3-State)
1998 Mar 17 9
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1mm SOT362-1
Philips Semiconductors Product specification
74LVC16373A/
74LVCH16373A
16-bit D-type transparent latch with 5 Volt Tolerant
inputs/outputs (3-State)
yyyy mmm dd 10
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
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Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appl iances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
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Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
DEFINITIONS
Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 05-96
Document order number: 9397-750-04533
