Data Sheet, Rev 1.2, December 2008
TLE4946-1L
High Precision Bipolar Hall-Effect Latch
Sensors
Edition 2008-12
Published by
Infineon Technologies AG
81726 München, Germany
© 2007 Infineon Technologies AG
All Rights Reserved.
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TLE4946-1L
Revision History: 2008-12 Rev 1.2
Previous Version: 1.1
Page Subjects (major changes since last revision)
TLE4946H version removed (transfered to own datasheet)
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TLE4946-1L
Data Sheet 1 Rev 1.2, 2008-12
1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Pin Configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5 Electrical and Magnetic Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7.1 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7.2 Distance between Chip and Package Surface . . . . . . . . . . . . . . . . . . . . . 11
7.3 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Type Package
TLE4946-1L PG-SSO-3-2
High Precision Bipolar Hall-Effect Latch
TLE4946-1L
Data Sheet 2 Rev 1.2, 2008-12
1Overview
1.1 Features
•2.7 V to 24 V supply voltage operation
Operation from unregulated power supply
High sensitivity and high stability of the magnetic
switching points
High resistance to mechanical stress by
Active Error Compensation
Reverse battery protection (– 18 V)
Superior temperature stability
Peak temperatures up to 195°C without damage
Low jitter (typ. 1 µs)
High ESD performance (± 6 kV HBM)
Digital output signal
Leaded package PG-SSO-3-2
1.2 Functional Description
The TLE4946-1L is an integrated circuit Hall-effect sensor designed specifically for
highly accurate applications.
Precise magnetic switching points and high temperature stability are achieved by active
compensation circuits and chopper techniques on chip.
TLE4946-1L
Overview
Data Sheet 3 Rev 1.2, 2008-12
1.3 Pin Configuration (top view)
Center of
Sensitive Area
321
PG-SSO-3-2
± 0.1
1.35
± 0.1
2.08
Figure 1 Pin Definition and Center of Sensitive Area
Table 1 Pin Definitions and Functions PG-SSO-3-2
Pin No. Symbol Function
1VSSupply voltage
2 GND Ground
3 Q Output
TLE4946-1L
General
Data Sheet 4 Rev 1.2, 2008-12
2 General
2.1 Block Diagram
Figure 2 Block Diagram
2.2 Circuit Description
The chopped Hall IC Switch comprises a Hall probe, bias generator, compensation
circuits, oscillator, and output transistor.
The bias generator provides currents for the Hall probe and the active circuits.
Compensation circuits stabilize the temperature behavior and reduce technology
variations.
The Active Error Compensation rejects offsets in signal stages and the influence of
mechanical stress to the Hall probe caused by molding and soldering processes and
other thermal stresses in the package.
This chopper technique together with the threshold generator and the comparator
ensure high accurate magnetic switching points.
Ref
Chopped
Hall Probe
V
S
Q
GND
Amplifier Low
Pass
Filter
Comparator
with
Hysteresis
Voltage Regulator
reverse polarity protected
Oscillator
and
Sequencer
Bias and
Compensation
Circuits
TLE4946-1L
Maximum Ratings
Data Sheet 5 Rev 1.2, 2008-12
3
Table 2 Absolute Maximum Ratings
Tj = – 40°C to 150°C
Parameter Symbol Limit Values Unit Conditions
min. max.
Supply voltage VS18
18
18
18
24
26
V
for 1 h, Rs 200
for 5 min, Rs 200
Supply current
through
protection device
IS50 + 50 mA
Output voltage VQ– 0.7
0.7
18
26
V
for 5 min @ 1.2 k pull up
Continuous
output current
IQ50 + 50 mA
Junction
temperature
Tj
155
165
175
195
°C for 2000 h (not additive)
for 1000 h (not additive)
for 168 h (not additive)
for 3 x 1 h (additive)
Storage
temperature
TS40 150 °C
Magnetic flux
density
B unlimited mT
Maximum Ratings
Note: Stresses above those listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Table 3 ESD Protection 1)
1) Human Body Model (HBM) tests according to: EOS/ESD Association Standard S5.1-1993 and
Mil. Std. 883D method 3015.7
Parameter Symbol Limit Values Unit Notes
min. max.
ESD voltage VESD ± 6 kV HBM, R = 1.5 k,
C = 100 pF
TA = 25°C
TLE4946-1L
Operating Range
Data Sheet 6 Rev 1.2, 2008-12
4 Operating Range
Table 4 Operating Range
Parameter Symbol Limit Values Unit Conditions
min. typ. max.
Supply voltage VS2.7 18 V
Output voltage VQ– 0.7 18 V
Junction
temperature
Tj– 40 150 °C
Output current IQ0 20 mA
TLE4946-1L
Electrical and Magnetic Parameters
Data Sheet 7 Rev 1.2, 2008-12
5 Electrical and Magnetic Parameters
Table 5 Electrical Characteristics 1).
1) over operating range, unless otherwise specified. Typical values correspond to VS =12 V and TA = 25°C
Parameter Symbol Limit Values Unit Conditions
min. typ. max.
Supply current IS24 6mA VS = 2.7 V ... 18 V
Reverse current ISR 00.2 1mA VS = – 18 V
Output saturation
voltage
VQSAT 0.3 0.6 VIQ = 20 mA
Output leakage
current
IQLEAK 0.05 10 µA for VQ = 18 V
Output fall time tf0.02 1µs RL = 1.2 k; CL = 50 pF
see: Figure 3 “Timing
Definition” on Page 9
Output rise time tr0.4 1µs
Chopper frequency fOSC 320 kHz
Switching
frequency
fSW 0 15
2) To operate the sensor at the max. switching frequency, the value of the magnetic signal amplitude must be
1.4 times higher than for static fields.
This is due to the - 3 dB corner frequency of the low pass filter in the signal path.
2) kHz
Delay time
3) Systematic delay between magnetic threshold reached and output switching
3) td13 µs
Output jitter
4) Jitter is the unpredictable deviation of the output switching delay
4) tQJ –1 µsRMS Typical value for square
wave signal 1 kHz
Power-on time
5) Time from applying VS 2.7 V to the sensor until the output state is valid
5) tPON 13 µs VS 2.7 V
Thermal resistance
6) Thermal resistance from junction to ambient
6)
RthJA 190 K/W PG-SSO-3-2
Note: Typical characteristics specify mean values expected over the production spread.
Table 6 Magnetic Characteristics TLE4946-1L 1)
Parameter Symbol Tj [°C] Limit Values Unit Notes
min. typ. max.
Operate point BOP – 40
25
150
11.3
11.0
10.5
15.4
15.0
14.3
19.5
19.0
18.1
mT
Release point BRP – 40
25
150
19.5
19.0
18.1
15.4
15.0
14.3
11.3
11.0
– 10.5
mT
Hysteresis BHYS – 40
25
150
22.0
30.0
38.0
mT
Magnetic Offset BOFF – 40
25
150
– 2.0
2.0
mT
2) BOFF = (BOP + BRP) / 2
2)
Temperature
compensation of
magn. thresholds
TC - 350 ppm/°C
Repeatability of
magnetic
thresholds
3) BREP is equivalent to the noise constant
3)
BREP 20 µTRMS Typ. value for
B / t
> 12 mT/ms
TLE4946-1L
Electrical and Magnetic Parameters
Data Sheet 8 Rev 1.2, 2008-12
Field Direction Definion
Positive magnetic fields related with south pole of magnet to the branded side of
package.
1) over operating range, unless otherwise specified. Typical values correspond to VS = 12 V.
TLE4946-1L
Timing Diagram
Data Sheet 9 Rev 1.2, 2008-12
6 Timing Diagram
Figure 3 Timing Definition
Applied
Magnetic
Field
90%
10%
V
Q
t
f
t
d
t
r
t
d
B
OP
B
RP
TLE4946-1L
Package Information
Data Sheet 10 Rev 1.2, 2008-12
7 Package Information
7.1 Package Marking
Year (y) = 0 ... 9
Calendar Week (ww) = 01 ... 52
yww
46 1
S
AEP03644
Figure 4 Marking TLE4946-1L
TLE4946-1L
Package Information
Data Sheet 11 Rev 1.2, 2008-12
7.2 Distance between Chip and Package Surface
Figure 5 Distance Chip PG-SSO-3-2 to Upper Side of IC
PG-SSO-3-2 : 0.57
d : Distance chip to upper side of IC
mm
±0.08
AEA02510-1
Hall-Probe
Branded Side
d
TLE4946-1L
Package Information
Data Sheet 12 Rev 1.2, 2008-12
7.3 Package Outlines
GPS09473
Total tolerance at 10 pitches ±1
1) No solder function area
±0.3
±0.4
6.35
12.7
12.7
±1
±0.5
-0.5
+0.75
4
±0.3
9
GPO05358
-0.15
±0.1
Tape
Adhesive
Tape
0.25
0.39
±0.5
A
18
6
23.8
±0.5
38 MAX.
-1
1
132
1.27
±0.25
1.27
±0.25
0.6 MAX.
0.4
±0.05
1)
1 MAX.
0.15 MAX.
1.9 MAX.
4.06
±0.08
4.16
±0.05
±0.08
3.29
3
±0.06
0.2
(0.25)
x 45˚0.8
±0.1
x 45˚
±0.1
0.35
0.2
+0.1
(0.79)
A
2
1.52
±0.05
Figure 6 PG-SSO-3-2
Note: You can find all of our packages, sort of packing and others on our Infineon
Internet page “Products”: http://www.infineon.com/products
TLE4946-1L
Notes
Data Sheet 13 Rev 1.2, 2008-12
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Published by Infineon Technologies AG