TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 POWER MANAGEMENT IC FOR DIGITAL STILL CAMERA FEATURES APPLICATIONS * * * * * * * * * * * Highly Efficient, 8-Channel Power Management IC Fully Integrated Power MOSFETs (Except CH-7) Minimal External Components Input Voltage Range: 1.5 to 5 V Short-Circuit Protection (SCP) (Except for CH-6 and CH-8) Overvoltage Protection (OVP) (CH-2, CH-3, CH-6, and CH-7) Overcurrent Protection (OCP) (CH-6) Thermal Shutdown (TSD) High-Accuracy Output Voltage with Trimming 8 mm x 8 mm BGA Package NAME (1) CIRCUIT CONFIGURATION OUTPUT VOLTAGE [V] ADJUSTABLE PARAMETER Digital Still Cameras DESCRIPTION The TPS65520 is a highly efficient, 8-channel power management IC for digital still cameras (DSCs) integrating power MOSFETs. The device operates from an input voltage range of 1.5 V to 5 V. The optimized circuit configuration maintains stable regulation characteristics while minimizing the number of external components required for phase compensation and other purposes. The TPS65520 controls each output channel by communicating with the Sub-CPU through a serial interface. POWER MOSFET RECTIFICATION PURPOSE CH-1 H-bridge step-up/down 2.65 ~ 3.2 Output voltage Built-in Synchronous CPU, DSP I/F CH-2 Step-down 1.1 ~ 1.8 Output voltage Built-in Synchronous CPU, DSP core Built-in Synchronous Motor, audio CH-3 Step-up 4.5 ~ 5.2 Output voltage, duty cycle CH-4 Step-up 15.0 ~ 16,5 Output voltage, duty cycle Built-in Asynchronous, with external rectification diode LCD, CCD CH-5 Inversion -9.0 ~ -7.5 Output voltage, duty cycle Built-in Asynchronous, with external rectification diode LCD, CCD CH-6 Step-up with constant current control 5.6 ~ 21.0 Output voltage, duty cycle Built-in Asynchronous, with external rectification diode Back light LED Step-down 2.5 ~ 3.2 Step-up 4.4 ~ 5.1 Output voltage, duty cycle External Synchronous Reserved/switchable Built-in Synchronous IC internal power supply CH-7 CH-8 Step-up/pass-through with skip 3.6 ~ VCC LDO-1 2.9 Sub-CPU I/F LDO-2 2.9 Sub-CPU core LDO-3 3.1 Charge backup battery LDO-4 3.1 LDO-5 8.5 ~ 13.5 (1) USB Output voltage LCD CH-N represents switching regulators. LDO-N represents series regulators. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TMS320 is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2005, Texas Instruments Incorporated TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT VI Input voltage range (2) ROMWR -0.3 V to 24 V MODE7, DIN, CLK, LD, PWR_ON, LDO4_ON, TEST, TLD -0.3 V to 7 V VCH2, VCH7, VCC8 -0.3 V to 6.5 V VCC1, VCC2, VCC5, VCC7, VCC_GD VCH5 VO Output voltage range (2) -10.0 V to 0.3 V VCH4, OUT4, VLDO5, VCH6, ICH6, OUT6 -0.3 V to 24 V BOOT11, BOOT12, BOOT2 -0.3 V to 11 V VOS71, DOUT, XRESET, READY -0.3 V to 7 V ROSC -0.3 V to 6.5 V OUT5 -10.0 V to 5.1 V OUT3 -0.3 V to 6 V (3) Others -0.3 V to 6 V VCC1 = OUT11, GND1 = OUT11, OUT12 = VCH1, OUT12 = GND1, OUT3 = VCH3, OUT3 = GND3 Peak current of Power Path -0.3 V to 6 V OUT8 = VCH8, OUT8 = GND8 VCC2 = OUT2, GND2 = OUT2, OUT4 = VCH4, OUT4 = GND4, VCC5 = OUT5, OUT6 = VCH6, OUT6 = GND6 Voltage difference between two of any GND pins (name starts with GND) -4.5 A to 4.5 A -3.0 A to 3 A -1.5 A to 1.5 A -0.5 V to 0.5 V ESD rating, HBM (Human Body Model) JEDEC JESD22-A114 1.5 kV ESD rating, CDM (Charged Device Model) JEDEC JESD22-C101 500 V PD Continuous total power dissipation TJ Operating virtual junction temperature range -20C to 150C TA Operating ambient temperature range -20C to 85C Tstg Storage temperature range -65C to 150C (1) (2) (3) See Dissipation Rating Table Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. All voltage values are with respect to network ground terminal. For the pulse smaller than 5 ns, Maximum rating is 8.6 V. DISSIPATION RATINGS (1) (2) 2 PACKAGE (1) POWER RATING TA < 25C DERATING FACTOR ABOVE TA = 25C POWER RATING TA = 70C nFBGA 113 (2) 2.99 W 23.9 mW/C 1.95 W For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. This data is based on using still air JEDEC environment with 2S2P JEDEC board. TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) VCC (1) VI Supply voltage Input voltage MIN NOM MAX VCC_GD 4.5 5.5 VCC1, VCC2, VCC5, VCC7, VCC8 1.5 5.5 TLD,VCH2,VCH7 0 5.5 MODE7, DIN, CLK, LD, PWR_ON, LDO4_ON, TEST 0 3.3 -9.5 0.0 VCH5 ROMWR UNIT V V 0 0.3 VIH1 (2) High-level input voltage ILDO1 = 0 mA 2.4 2.9 V VIL1 (2) Low-level logic input voltage ILDO1 = 0 mA 0 0.5 V VIH2 TLD high-level logic input voltage 80% 100 % VIL2 TLD low- level logic input voltage 0% 20% Voltage difference between two of any GND pins (name starts with GND) -0.3 0.3 V Operating free-air temperature, -20 85 C 20 Times TA Ratio to VCC1A voltage Acceptable number of EEPROM writing (3) (1) (2) (3) These values are defined in stable state. During the start-up, supply voltage sources are OK to be lower than these values. Logic input pins are PWR_ON, USB ON, DIN, CLK, LD, TEST, and MODE7, except TLD. This defines the number of customer's writing after TI's shipment. ELECTRICAL CHARACTERISTICS TA = 25C, VCC1 = 3.6 V, VCC2 = 3.6 V, VCC5 = 4.9 V, VCC7 = 4.9 V, VCC8 = 3.6 V, VCH8 = 3.6 V, VCH3 = 4.9 V, VCH_GD = 4.9 V, LDO4_ON = L, and all register bits are default value (unless otherwise noted) . PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT ICC1 ICC CTRL Supply current for controller IVCC GD Supply current for gate-drive PWR_ON = H, No load current at all outputs (see Table 1) 2.2 mA 5 mA 40 A 1 A ICC2A IVCH8 Supply current for LDO, control IVCC8 Supply current for CH-8 PWR_ON = L (see Table 2) SUB-CPU CONTROL VRDY1 READY threshold, rising edge VRDY2 READY threshold, falling edge VRST1 XRESET threshold, rising edge VRST2 XRESET threshold, falling edge IREADY Sink current of READY VREADY = 0.5 V Ilkg Leakage current of READY VREADY = 5.25 V, VCH8 = 5.25 V IRST Sink current of XRESET VXRESET = 0.5 V, VLDO2 = 2 V IRSTL Leakage current of XRESET VXRESET = 5.25 V, VCH8 = 5.25 V Sweep VCH8 Sweep VLDO2 3.322 3.4 3.478 3.234 3.3 3.366 2.115 2.184 2.253 1.844 1.884 1.924 250 500 V A 0.1 150 V 300 A A 0.1 A 0.858 V REFERENCE AND PROTECTION VREF BG reference voltage, sensed at CBG IREF = 0 mA VloBG Load regulation of BG reference voltage buffer IREF = 0.1 A ~ 1 mA fosc Oscillator frequency ROSC = 150 k Temperature threshold to shutdown (1) (1) 0.842 0.85 -5 5 mV 475 500 525 kHz 140 155 170 C Not production tested. Assured by design. 3 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 ELECTRICAL CHARACTERISTICS (continued) TA = 25C, VCC1 = 3.6 V, VCC2 = 3.6 V, VCC5 = 4.9 V, VCC7 = 4.9 V, VCC8 = 3.6 V, VCH8 = 3.6 V, VCH3 = 4.9 V, VCH_GD = 4.9 V, LDO4_ON = L, and all register bits are default value (unless otherwise noted) . PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SOFT-START ISS VSS3OK Source current of SS_SYNC VSS_SYNC = 0.5 V 0.7 1 1.3 A Source current of SS2 VSS2 = 0.5 V 0.7 1 1.3 A Source current of SS3 VSS3 = 0.5 V 0.7 1 1.3 A Source current of SS5 VSS5 = 0.5 V 0.7 1 1.3 A Source current of SS6 VSS6 = 0.5 V 0.7 1 Source current of SSLDO5 VSSLDO5 = 0.5 V SS3OK threshold voltage 0.35 1.2 1.6 1.3 A 0.65 A 2 V LOGIC INPUT/OUTPUT VOH (2) High-level logic output voltage VOL (2) Low-level logic output voltage ILDO1 = 0 mA, IDOUT = -0.5 mA 2.5 0.4 V START-UP CIRCUIT VWU Wake-up voltage Monitoring VCC8 1.6 V CH-1 VCH1 Error amp center voltage Vout1 = 0000(bin), TA = -10 ~ 65C 2.744 2.8 2.856 V Vout1 = 0001(bin), TA = -10 ~ 65C 2.695 2.75 2.805 V Vout1 = 0010(bin), TA = -10 ~ 65C 2.646 2.7 2.754 V Vout1 = 0001(bin), TA = -10 ~ 65C 2.597 2.65 2.703 V Vout1 = 0100(bin), TA = -10 ~ 65C 2.548 2.6 2.652 V Vout1 = 0101(bin), TA = -10 ~ 65C 2.499 2.55 2.601 V Vout1 = 0110(bin), TA = -10 ~ 65C 2.450 2.5 2.550 V Vout1 = 0111(bin), TA = -10 ~ 65C 3.138 3.2 3.264 V Vout1 = 1000(bin), TA = -10 ~ 65C 3.087 3.15 3.213 V Vout1 = 1001(bin), TA = -10 ~ 65C 3.038 3.1 3.162 V Vout1 = 1010(bin), TA = -10 ~ 65C 2.989 3.05 3.111 V Vout1 = 1011(bin), TA = -10 ~ 65C 2.940 3 3.060 V Vout1 = 1100(bin), TA = -10 ~ 65C 2.891 2.95 3.009 V Vout1 = 1101(bin), TA = -10 ~ 65C 2.842 2.9 2.958 V Vout1 = 1110(bin), TA = -10 ~ 65C 2.793 2.85 2.907 V Vout1 = 1111(bin), TA = -10 ~ 65C 2.769 2.825 2.88 V 0.8 1 1.2 mS 2.744 2.8 2.856 gm1 gm value of error amp VOCH1 (3) Output voltage On EVM, TA = -10 ~ 65C Vli11 (3) Line regulation (CROSS state) On EVM -28 28 mV Vli12 (3) Line regulation (DOWN state) On EVM -28 28 mV Vlo11 (3) Load regulation (CROSS state) On EVM -28 28 mV Vlo12 (3) Load regulation (DOWN state) On EVM -28 28 mV IOUT1 (3) Minimum Load current On EVM, VCC1=1.8 V 400 VSCP1 SCP detector threshold Ratio to VCH1 75% 80% 85% Vmod11 Mode selector threshold, rising edge Ratio to VCH1 130% 135% 137% Vmod12 Mode selector threshold, falling edge Ratio to VCH1 120% 125% 127% (2) (3) 4 Logic output pin is DOUT. Not production tested. Assured by design. Using reference EVM. V mA TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 ELECTRICAL CHARACTERISTICS (continued) TA = 25C, VCC1 = 3.6 V, VCC2 = 3.6 V, VCC5 = 4.9 V, VCC7 = 4.9 V, VCC8 = 3.6 V, VCH8 = 3.6 V, VCH3 = 4.9 V, VCH_GD = 4.9 V, LDO4_ON = L, and all register bits are default value (unless otherwise noted) . PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CH-2 VCH2 Error amp center voltage Vout2 = 0000(bin), TA = -10 ~ 65C 1.176 1.2 1.224 V Vout2 = 0001(bin), TA = -10 ~ 65C 1.127 1.15 1.173 V Vout2 = 0010(bin), TA = -10 ~ 65C 1.078 1.1 1.122 V Vout2 = 0011(bin), TA = -10 ~ 65C 1.764 1.8 1.836 V Vout2 = 0100(bin), TA = -10 ~ 65C 1.715 1.75 1.785 V Vout2 = 0101(bin), TA = -10 ~ 65C 1.666 1.7 1.734 V Vout2 = 0110(bin), TA = -10 ~ 65C 1.617 1.65 1.683 V Vout2 = 0111(bin), TA = -10 ~ 65C 1.568 1.6 1.632 V Vout2 = 1000(bin), TA = -10 ~ 65C 1.519 1.55 1.581 V Vout2 = 0001(bin), TA = -10 ~ 65C 1.470 1.5 1.530 V Vout2 = 1010(bin), TA = -10 ~ 65C 1.421 1.45 1.479 V Vout2 = 1011(bin), TA = -10 ~ 65C 1.372 1.4 1.428 V Vout2 = 1100(bin), TA = -10 ~ 65C 1.323 1.35 1.377 V Vout2 = 1101(bin), TA = -10 ~ 65C 1.274 1.3 1.326 V Vout2 = 1110(bin), TA = -10 ~ 65C 1.225 1.25 1.275 V Vout2 = 1111(bin), TA = -10 ~ 65C 1.201 1.225 1.250 0.8 1 1.2 1.176 1.2 1.224 V gm2 gm value of error amp mS VoCH2 (3) Output voltage On EVM, TA = -10 ~ 65C Vli12 (3) Line regulation On EVM -12 12 mV Vlo2 (3) Load regulation On EVM -12 12 mV IOUT2 (3) Minimum load current On EVM, VCC2=4.2 V 500 VSCP2 SCP detector threshold Ratio to VCH2 75% 80% 85% VOVP2 OVP detector threshold Ratio to VCH2 115% 120% 125% Vout1 = 0000(bin), TA = -10 ~ 65C 4.802 4.9 4.998 V Vout1 = 0001(bin), TA = -10 ~ 65C 4.753 4.85 4.947 V Vout1 = 0010(bin), TA = -10 ~ 65C 4.704 4.8 4.896 V Vout1 = 0001(bin), TA = -10 ~ 65C 4.655 4.75 4.845 V Vout1 = 0100(bin), TA = -10 ~ 65C 4.606 4.7 4.794 V Vout1 = 0101(bin), TA = -10 ~ 65C 4.557 4.65 4.743 V Vout1 = 0110(bin), TA = -10 ~ 65C 4.508 4.6 4.692 V Vout1 = 0111(bin), TA = -10 ~ 65C 4.459 4.55 4.641 V Vout1 = 1000(bin), TA = -10 ~ 65C 4.410 4.5 4.590 V Vout1 = 1001(bin), TA = -10 ~ 65C 5.096 5.2 5.304 V Vout1 = 1010(bin), TA = -10 ~ 65C 5.047 5.15 5.253 V Vout1 = 1011(bin), TA = -10 ~ 65C 4.998 5.10 5.202 V Vout1 = 1100(bin), TA = -10 ~ 65C 4.949 5.05 5.151 V Vout1 = 1101(bin), TA = -10 ~ 65C 4.900 5 5.100 V Vout1 = 1110(bin), TA = -10 ~ 65C 4.851 4.95 5.049 V Vout1 = 1111(bin), TA = -10 ~ 65C 4.802 4.9 4.998 0.8 1 1.2 4.802 4.90 4.998 V mA CH-3 VCH3 Error amp center voltage V gm3 gm value of error amp VoCH3 (4) Output voltage On EVM, TA = -10 ~ 65C Vli3 (4) Line regulation On EVM -49 49 mV Vlo3 (4) Load regulation On EVM -49 49 mV IOUT3 (4) Minimum Load current On EVM, [CH-3 input voltage]=1.8 V VSCP3 SCP detector threshold Ratio to VCH3 VOVP3 OVP detector threshold Ratio to VCH3 (4) 500 75% mS V mA 80% 5.99 85% V Not production tested. Assured by design. Using reference EVM. 5 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 ELECTRICAL CHARACTERISTICS (continued) TA = 25C, VCC1 = 3.6 V, VCC2 = 3.6 V, VCC5 = 4.9 V, VCC7 = 4.9 V, VCC8 = 3.6 V, VCH8 = 3.6 V, VCH3 = 4.9 V, VCH_GD = 4.9 V, LDO4_ON = L, and all register bits are default value (unless otherwise noted) . PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CH-4 VCH4 Error amp center voltage Vout4 = 00(bin), TA = -10 ~ 65C 14.700 15 15.300 V Vout4 = 01(bin), TA = -10 ~ 65C 15.190 15.5 15.810 V Vout4 = 10(bin), TA = -10 ~ 65C 15.680 16 16.320 V Vout4 = 11(bin), TA = -10 ~ 65C 16.170 16.5 16.830 V 0.8 1 1.2 14.700 15.0 15.300 gm4 gm value of error amp VoCH4 (4) Output voltage On EVM, TA = -10 ~ 65C Vli4 (4) Line regulation On EVM -150 150 mV Vlo4 (4) Load regulation On EVM -150 150 mV IOUT4 (4) Minimum Load current On EVM, [CH-4 input voltage] = 1.8 V VSCP4 SCP detector threshold Ratio to VCH4 50 mS V mA 75% 80% 85% Vout5=00(bin), TA = -10 ~ 65C -7.650 -7.5 -7.350 V Vout5=01(bin), TA = -10 ~ 65C -8.160 -8.0 -7.840 V Vout5=10(bin), TA = -10 ~ 65C -8..670 -8.5 -8.330 V Vout5=11(bin), TA = -10 ~ 65C -9.180 -9.0 -8.820 0.8 1.0 1.2 -7.650 -7.5 -7.350 CH-5 VCH5 Error amp center voltage V gm5 gm value of error amp VoCH5 (5) Output voltage On EVM, TA = -10 ~ 65C Vli5 (5) Line regulation On EVM -75 75 mV Vlo5 (5) Load regulation On EVM -75 75 mV IOUT5 (5) Minimum Load current On EVM,VCC5 = 4.9 V VSCP5 SCP detector threshold 50 mS V mA 75% 80% 85% Vout5 = 00(bin), TA = -10 ~ 65C 0.2482 0.264 0.2798 V Vout5 = 01(bin), TA = -10 ~ 65C 0.4136 0.440 0.4664 V Vout5 = 10(bin), TA = -10 ~ 65C 0.1654 0.176 0.1866 0.8 1 1.2 mS 12 12.72 mA 120 A CH-6 VFB6 Error amp center voltage gm6 gm value of error amp ICH6 (5) Output voltage On EVM, TA = -10 ~ 65C 11.28 Vli6 (5) Line regulation of VFB6 On EVM -120 VOCP OCP detector threshold Monitor at FB6 0.80 0.85 0.90 V VOVP6 OVP detector threshold 21.0 22 23.0 V VREF6L CH-6 disable threshold, low side 0.16 0.21 0.26 V VREF6H CH-6 disable threshold, high side VCH1 = 2.8 V 1.7 2 2.3 V VfDI6 Forward voltage of integrated diode I(OUT6 = VCH6) = 20 mA 0.9 V (5) 6 Not production tested. Assured by design. Using reference EVM. V TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 ELECTRICAL CHARACTERISTICS (continued) TA = 25C, VCC1 = 3.6 V, VCC2 = 3.6 V, VCC5 = 4.9 V, VCC7 = 4.9 V, VCC8 = 3.6 V, VCH8 = 3.6 V, VCH3 = 4.9 V, VCH_GD = 4.9 V, LDO4_ON = L, and all register bits are default value (unless otherwise noted) . PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CH-7 VCH7U VCH7D Error amp center voltage Error amp center voltage Vout7 = 0000(bin), TA = -10 ~ 65C, MODE7 = H 4.802 4.9 4.998 V Vout7 = 0001(bin), TA = -10 ~ 65C, MODE7 = H 4.753 4.85 4.947 V Vout7 = 0010(bin), TA = -10 ~ 65C, MODE7 = H 4.704 4.8 4.896 V Vout7 = 0001(bin), TA = -10 ~ 65C, MODE7 = H 4.655 4.75 4.845 V Vout7 = 0100(bin), TA = -10 ~ 65C, MODE7 = H 4.606 4.7 4.794 V Vout7 = 0101(bin), TA = -10 ~ 65C, MODE7 = H 4.557 4.65 4.743 V Vout7 = 0110(bin), TA = -10 ~ 65C, MODE7 = H 4.508 4.60 4.692 V Vout7 = 0111(bin), TA = -10 ~ 65C, MODE7 = H 4.459 4.55 4.641 V Vout7 = 1000(bin), TA = -10 ~ 65C, MODE7 = H 4.41 4.50 4.590 V Vout7 = 1001(bin), TA = -10 ~ 65C, MODE7 = H 4.361 4.45 4.539 V Vout7 = 1010(bin), TA = -10 ~ 65C, MODE7 = H 4.312 4.40 4.488 V Vout7 = 1011(bin), TA = -10 ~ 65C, MODE7 = H 4.998 5.10 5.202 V Vout7 = 1100(bin), TA = -10 ~ 65C, MODE7 = H 4.949 5.05 5.151 V Vout7 = 1101(bin), TA = -10 ~ 65C, MODE7 = H 4.9 5 5.1 V Vout7 = 1110(bin), TA = -10 ~ 65C, MODE7 = H 4.851 4.95 5.049 V Vout7 = 1111(bin), TA = -10 ~ 65C, MODE7 = L 4.802 4.90 4.998 V Vout7 = 0000(bin), TA = -10 ~ 65C, MODE7 = L 3.038 3.1 3.162 V Vout7 = 0001(bin), TA = -10 ~ 65C, MODE7 = L 2.989 3.05 3.111 V Vout7 = 0010(bin), TA = -10 ~ 65C, MODE7 = L 2.940 3.00 3.060 V Vout7 = 0001(bin), TA = -10 ~ 65C, MODE7 = L 2.891 2.95 3.009 V Vout7 = 0100(bin), TA = -10 ~ 65C, MODE7 = L 2.842 2.9 2.958 V Vout7 = 0101(bin), TA = -10 ~ 65C, MODE7 = L 2.793 2.85 2.907 V Vout7 = 0110(bin), TA = -10 ~ 65C, MODE7 = L 2.744 2.8 2.856 V Vout7 = 0111(bin), TA = -10 ~ 65C, MODE7 = L 2.695 2.75 2.805 V Vout7 = 1000(bin), TA = -10 ~ 65C, MODE7 = L 2.646 2.7 2.754 V Vout7 = 1001(bin), TA = -10 ~ 65C, MODE7 = L 2.597 2.65 2.703 V Vout7 = 1010(bin), TA = -10 ~ 65C, MODE7 = L 2.548 2.6 2.652 V Vout7 = 1011(bin), TA = -10 ~ 65C, MODE7 = L 2.499 2.55 2.601 V Vout7 = 1100(bin), TA = -10 ~ 65C, MODE7 = L 2.450 2.5 2.550 V Vout7 = 1101(bin), TA = -10 ~ 65C, MODE7 = L 3.138 3.2 3.264 V Vout7 = 1110(bin), TA = -10 ~ 65C, MODE7 = L 3.087 3.15 3.213 V Vout7 = 1111(bin), TA = -10 ~ 65C, MODE7 = L 3.038 3.1 3.162 0.8 1 1.2 4.802 4.9 4.998 V gm7 gm value of error amp VoC71 (6) Output voltage Mode7 = H, On EVM, TA = -10 ~ 65C Vli71 (6) Line regulation Mode7 = H, On EVM -49 49 mV Vlo71 (6) Load regulation Mode7 = H, On EVM -49 49 mV IOUT71 (6) Minimum Load current Mode7 = H, On EVM, VCC7=1.8 V 500 VOCH72 (6) Output voltage Mode7 = L, On EVM, TA = -10 ~ 65C Vli72 (6) Line regulation Mode7 = L, On EVM -31 31 mV Vlo72 (6) Load regulation Mode7 = L, On EVM -31 31 mV IOUT72 (6) Minimum load current Mode7 = L, On EVM, [CH-7 input voltage] = 4.9 V 150 VSCP7 SCP detector threshold Ratio to VCH7 VOVP7 OVP detector threshold Ratio to VCH7 IOS71H Source current of OS71 VOS71 = 0 V, VCH3 = VCH7 = 4.9 V IOS71L Sink current of OS71 VOS71 = 4.9 V, VCH3 = VCH7 = 4.9 V IOS72H Source current of OS72 VOS72 = 4.4 V, VCH3 = VCH7 = 4.9 V IOS72L Sink current of OS72 VOS72 = 0.5 V, VCH3 = VCH7 = 4.9 V (6) 3.038 75% V mA 3.1 3.162 V mA 80% 85% 5.99 V -6 mA -100 mA 0.2 100 mS A mA Not production tested. Assured by design. Using reference EVM. 7 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 ELECTRICAL CHARACTERISTICS (continued) TA = 25C, VCC1 = 3.6 V, VCC2 = 3.6 V, VCC5 = 4.9 V, VCC7 = 4.9 V, VCC8 = 3.6 V, VCH8 = 3.6 V, VCH3 = 4.9 V, VCH_GD = 4.9 V, LDO4_ON = L, and all register bits are default value (unless otherwise noted) . PARAMETER TEST CONDITIONS IOS73H Source current of OS73 VOS73 = 0.0 V, VCH3 = VCH7 = 4.9 V IOS73L Sink current of OS73 VOS73 = 0.5 V, VCH3 = VCH7 = 4.9 V ROS71n ON resistance NMOS (OS71, GND GD), VOS71 = 0.1 V, VCH3 = VCH7 = 4.9 V ROS72n ON resistance ROS73n MIN TYP MAX UNIT -100 mA 100 mA 7.5 k NMOS(OS72, GND GD), VOS72 = 0.1 V, VCH3 = VCH7 = 4.9 V 5 ON resistance NMOS(OS73, GND GD), VOS73 = 0.1 V, VCH3 = VCH7 = 4.9 V 5 ROS71p ON resistance PMOS(VCH7, OS71), VOS71 = 4.8 V, VCH3 = VCH7 = 4.9 V 360 ROS72p ON resistance PMOS(VCC7, OS72), VOS72 = 4.8 V, VCH3 = VCH7 = 4.9 V 5 ROS73p ON resistance PMOS(VCC GD, OS73), VOS73 = 4.8 V, VCH3 = VCH7 = 4.9 V 15 V CH-8 VCH81 Error amp center voltage (normal) VCH82 Error detector center voltage (skip) gm8 gm value of error amp VoCH81 (7) Output voltage (skip) VoCH82 (7) Output voltage (normal) Vli81 (7) Line regulation (skip) On EVM, VCC8 = 1.8 ~ 3.6 V (= VoCH81) (8) Vli82 (7) Line regulation (normal) On EVM, VCC8 = 1.8 ~ 3.6 V Vlo81 (7) Load regulation (skip) On EVM, VCC8 = 1.8 ~ 3.6 V, ICH8 < x[mA] Vlo82 (7) Load regulation (normal) IOUT81 (7) IOUT82 (7) (7) (8) PWR_ON = H, TA = -10 ~ 65C On EVM, TA = -10 ~ 65C, VCC8 = 1.5 ~ 3.6 V 3.528 3.6 3.672 3.492 3.6 3.708 0.8 1 1.2 3.492 3.6 3.708 3.528 3.6 3.672 -108 V mS V V 180 mV -36 36 mV -120 120 mV On EVM, VCC8 = 1.8 ~ 3.6 V -36 36 mV Minimum Load current (skip) On EVM, VCC8 = 1.8 V 120 mA Minimum Load current (normal) On EVM, VCC8 = 1.8 V 170 mA Not production tested. Assured by design. Using reference EVM. This parameter Vli81 is covered by VoCH81 and adjusted to VoCH81. PARAMETER TEST CONDITIONS MIN TYP MAX 2.842 2.9 2.958 UNIT LDO-1 VLDO1 Output voltage VCH8 = 3.6 ~ 5.25 V, ILDO1 = 5 mA VliL1 Line regulation VCH8 = 3.6 ~ 5.25 V, ILDO1 = 5 mA V VloL1 Load regulation VCH8 = 3.6 V, ILOD1 = 0.1 ~ 30 mA Output current limit VCH8 = 3.6 ~ 5.25 V VLDO2 Output voltage VCH8 = 3.6 ~ 5.25 V, ILDO2 =6 mA VliL2 Line regulation VCH8 = 3.6 ~ 5.25 V, ILDO2 = 6 mA 30 mV VloL2 Load regulation VCH8 = 3.6 V, ILOD2 = 0.1 ~ 50 mA 100 mV Output current limit VCH8 = 3.6 ~ 5.25 V VLDO3 Output voltage VCH8 = 3.6 ~ 5.25 V, ILDO3 = 10 mA VliL3 Line regulation VCH8 = 3.6 ~ 5.25 V, ILDO3 = 10 mA VloL3 Load regulation VCH8 = 3.6 V, ILOD3 = 0.1 ~ 20 mA Output current limit VCH8 = 3.6 ~ 5.25 V VLDO4 Output voltage VCH8 = 3.6 ~ 5.25 V, ILDO4 = 5 mA VliL4 Line regulation VCH8 = 3.6 ~ 5.25 V, ILDO4 = 5 mA 30 mV VloL4 Load regulation VCH8 = 3.6 V, ILOD1 = 0.5 ~ 100 mA 100 mV Output current limit VCH8 = 3.6 ~ 5.25 V 30 mV 100 mV 36 mA LDO-2 2.842 2.9 2.958 60 V mA LDO-3 3.038 3.1 3.162 V 30 mV 100 mV 24 mA LDO-4 8 3.078 120 3.142 3.202 V mA TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 PARAMETER TEST CONDITIONS MIN TYP MAX LDO5Vo = 00 (bin), TA = -10 ~ 65C, ILDO5 = 15 mA 13.23 13.5 13.778 LDO5Vo = 01 (bin), TA = -10 ~ 65C, ILDO5 = 15 mA 12.25 12.5 12.75 LDO5Vo = 10 (bin), TA = -10 ~ 65C, ILDO5 = 15 mA 11.76 12 12.24 LDO5Vo = 11 (bin), TA = -10 ~ 65C, ILDO5 = 15 mA 8.33 8.5 8.67 UNIT LDO-5 VLDO5 Output voltage V VliL5 Line regulation VCH4 = 15 ~ 16.5 V, ILDO5 = 5 mA 50 mV VloL5 Load regulation VCH4 = 15 V, ILOD5 = 0.1 ~ 15 mA 50 mV Output current limit VCH4 = 15 ~ 16.5 V 36 mA EQUIVALENT INPUT/OUTPUT CIRCUIT DIAGRAMS INPUT CIRCUIT INPUT CIRCUIT VLDO1 VCC1A INPUT INPUT 470 k 470 k GND_REG GND_REG Figure 1. PWR_ON, LDO4_ON, DIN, TEST Figure 2. TLD INPUT CIRCUIT INPUT CIRCUIT VLDO1 VLDO1 470 k INPUT MODE7 GND_REG GND_REG Figure 3. LD Figure 4. MODE7 9 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 EQUIVALENT INPUT/OUTPUT CIRCUIT DIAGRAMS (continued) INPUT CIRCUIT OUTPUT CIRCUIT VLDO1 VLDO1 470 k CLK DOUT GND_REG GND_REG Figure 5. CLK Figure 6. DOUT OUTPUT CIRCUIT OPEN DRAIN GND_REG Figure 7. READY, XRESET ICC1 ICC1 represents the supply current measured when all channels are operating normally with no load. It is difficult to connect coils and other external devices to the TPS65520. Therefore, to measure characteristics in shipping tests, the desired ICC1 is specified using two testable parameters with the pins handled as shown in Table 1. ICC_CTRL represents the supply current from the 2.9-V and 4.2-V power supplies shown in the tables. ICC_GD represents the supply current from the 4.2-V power supplies shown in the tables. IVCC_GD is a self-consumed gate drive current from CH-3. Therefore, it is associated with the desired ICC1 through the CH-3 efficiency. Equation 1 indicates the relationship between IVCC_GD and the supply current from the power supplies in the application circuit (ICC1). ICC1 is specified as the supply current when a voltage of 4.2 V is the input. ICC_CTRL is the current consumed by the TPS65520 (excluding IVCC_GD). ICC1 4.9 1 IVCC_GD ICC_CTRL 4.2 CH3 4.9 IVCC_GD CH3 4.2 (ICC1 ICC_CTRL) 10 (1) TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 Table 1. Pin Handling for Measuring ICC1 Pin Name Connection Note POWER SUPPLY VCC_GD 4.9 V GND_GD GND GNDANA GND GNDLOG GND GNDREG GND GNDLDOA GND Supply gate drive Connection Note CH-2 BOOT2 4.9 V supply gate driver VCH2 GND force MAX DUTY VCC2 2.9 V bias power MOS OUT2 open (not concerned) GND2 GND ERR2 4.2 V force MAX DUTY VCH3A/B/C 4.9 V supply TAKUMI VCH3S open (not concerned) OUT3A/B/C open (not concerned) GND3A/B/C GND ERR3 4.2 V force MAX DUTY VCH4 4.9 V force MAX DUTY OUT4 open (not concerned) GND4 GND ERR4 open (not concerned) VCH5 GND force MAX DUTY VCC5 4.9 V supply gate driver OUT5 open (not concerned) ERR5 open (not concerned) OUT6 open (not concerned) FB6 GND force MAX DUTY VCH6 open (not concerned) ICH6 open (not concerned) GND6 GND REF6 CBG bias ERR6 open (not concerned) VCH7 open (not concerned) VCC7 4.9 V supply gate driver ERR7 4.2 V force MAX DUTY MODE7 GND fix logic value VOS71 open (not concerned) VOS72 open (not concerned) VOS73 open (not concerned) VCH8A/B 4.2 V force through mode VCC8 4.2 V force through mode ERR8 4.2 V force MAX DUTY OUT8A/B open (not concerned) GND8A/B GND CH-3 SUB-CPU CONTROL PWR_ON 2.9 V CSCP GND ROSC 150 k to GND recommended part CREF Cap recommended part CBG Cap recommended part VLDO1 Cap recommended part VLDO2 Cap recommended part VLDO3 Cap recommended part VLDO4 Cap recommended part VLDO5 Cap recommended part avoid shutdown LOGIC ROMWR GND TEST open pull down internally TLD open pull down internally CLK open pull up internally DIN open pull down internally LD open pull up internally DOUT open (not concerned) SS, ETC. READY Pin Name open (not concerned) XRESET open (not concerned) LDO4_ON 2.9 V force LDO-4 ON SS_SYNC open (not concerned) SS2 open (not concerned) SS3 open (not concerned) SS5 open (not concerned) SS6 open (not concerned) SSLDO5 open (not concerned) CH-1 BOOT11 4.9 V supply gate driver BOOT12 4.9 V supply gate driver VCH1A/B/C 2.9 V force output VCC1A/B/C 2.9 V supply CH-1 GND1A/B/C GND OUT11A/B/C open (not concerned) OUT12A/B/C open (not concerned) ERR1 4.2 V force MAX DUTY CH-4 CH-5 CH-6 CH-7 CH-8 11 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 ICC2 ICC2 represents the supply current measured when the system operation is minimized with CH-8 placed in sleep mode. It is difficult to connect coils and other external devices to the TPS65520 to measure its characteristics in shipping tests. Therefore, the desired ICC2 is specified using three testable parameters with the pins handled as shown in Table 2. IVCC8 and IVCH8 represent the supply currents from the VCC8 and VCH8 pins, respectively. Equation 2 indicates the relationship between those currents and the supply current from the power supplies in the application circuit (ICC2). ICC2 is specified as the supply current when a voltage of 3.6 V is input. ICC2 1 IVCH8 IVCC8 CH8:skip (2) Table 2. Pin Handling for Measuring ICC2 Pin Name Connection Note POWER SUPPLY VCC_GD open GND_GD GND GNDANA GND GNDLOG GND GNDREG GND GNDLDOA GND (not concerned) LOGIC ROMWR GND TEST open pull down internally TLD open pull down internally CLK open pull up internally DIN open pull down internally LD open pull up internally DOUT open (not concerned) SUB-CPU CONTROL PWR_ON CSCP ROSC GND GND avoid shutdown 150 k to GND recommended part CREF Cap recommended part CBG Cap recommended part VLDO1 Cap recommended part VLDO2 Cap recommended part VLDO3 Cap recommended part VLDO4 Cap recommended part VLDO5 Cap recommended part READY open (not concerned) XRESET open (not concerned) LDO4_ON GND SS_SYNC open (not concerned) SS2 open (not concerned) SS3 open (not concerned) SS5 open (not concerned) SS6 open (not concerned) SS, ETC. 12 Pin Name SSLDO5 Connection Note open (not concerned) BOOT11 open (not concerned) BOOT12 open (not concerned) VCH1A/B/C open (not concerned) VCC1A/B/C open (not concerned) GND1A/B/C GND OUT11A/B/C open (not concerned) OUT12A/B/C open (not concerned) ERR1 open (not concerned) BOOT2 open (not concerned) VCH2 open (not concerned) VCC2 open (not concerned) OUT2 open (not concerned) GND2 GND ERR2 open (not concerned) VCH3A/B/C open (not concerned) VCH3S open (not concerned) OUT3A/B/C open (not concerned) GND3A/B/C GND ERR3 open (not concerned) VCH4 open (not concerned) OUT4 open (not concerned) GND4 GND ERR4 open (not concerned) VCH5 open (not concerned) VCC5 open (not concerned) OUT5 open (not concerned) ERR5 open (not concerned) open (not concerned) CH-1 CH-2 CH-3 CH-4 CH-5 CH-6 OUT6 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 Pin Name Connection Note Pin Name Connection Note FB6 GND MODE7 GND fix logic value VCH6 open (not concerned) VOS71 open (not concerned) ICH6 open (not concerned) VOS72 open (not concerned) GND6 GND VOS73 open (not concerned) REF6 open (not concerned) CH-8 ERR6 open (not concerned) VCH8A/B 3.7 V stop skip switching VCC8 3.6 V supply to CH-8 circuit CH-7 VCH7 open (not concerned) ERR8 open (not concerned) VCC7 open (not concerned) OUT8A/B open (not concerned) ERR7 open (not concerned) GND8A/B GND PWR_ON td1 SS3 1.6[V] Time A. td1 (Measure SS3 when it is left open.) Figure 8. td1 Measurement Reference VCH3S LD 0.01 [F] td2 47[k ] 90[%] VCH3S VCH3 4.9[V] Time Figure 9. td2 Measuring Circuit and Measurement Reference 13 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 ~ ~ LD td3fr td3f ~ ~ VOS71 50[%] 50[%] ~ ~ Time A. td3r, td3f (Measure VOS71 when it is left open.) Figure 10. td3r and td3f Measurement References LD LDO4_ON td4 td5 90[%] 90[%] VLDO3 VLDO4 Time A. Time td4 (Connect a capacitor, 4.7 F recommended, to VLDO3.) Figure 11. td4 Measurement Reference A. td5 (Connect a capacitor, 4.7 F recommended, to VLDO4.) Figure 12. td5 Measurement Reference CLK td7 td6 DOUT DOUT 20[pF] 50[%] 50[%] 50[%] 50[%] or DOUT ~ Time Figure 13. td6 and td7 Measuring Circuit and Measurement References 14 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 VLDO2 VRST1 10[k ] td8 XRESET XRESET 50[%] Time Figure 14. td8 Measuring Circuit and Measurement Reference TIMING REQUIREMENTS TA = 25C, VCC1 = 3.6 V, VCC2 = 3.6 V, VCC5 = 3.6 V, VCC7 = 3.6 V, VCC8 = 3.6 V, VCH8 = 3.6 V, VCH3 = 4.9 V, VCH_GD = 4.9 V, LDO4_ON = L, and all register bits are default value (unless otherwise noted) PARAMETER MIN MAX UNIT ts1 Setup time, LD before CLK (see Figure 33) 400 ns ts2 Setup time, DIN valid before CLK (see Figure 33) 200 ns ts3 Setup time, TLD after CLK (see Figure 39) 50 ns ts4 Setup time, TLD before CLK (see Figure 39) 50 ns ts5 Setup time, ROMWR before TLD (see Figure 43) 10 s th1 Hold time, DIN valid after CLK (see Figure 33) 50 ns th2 Hold time, LD after last CLK (see Figure 33) 50 ns th3 Hold time, ROMWR after last TLD (see Figure 33) 10 s tw1 Pulse width of TLD = H for Test0 ~ Test5 (see Figure 39) 50 ns tw2 Pulse width of TLD = H for Test6,Test7 (see Figure 43) 20 ms tw3 Pulse width of CLK = H (see Figure 33) 100 ns tcyc Period of CLK (see Figure 33) 500 ns SWITCHING CHARACTERISTICS TYP MAX UNIT td1 Delay time, PWR_ON to start of charging SS3 (see Figure 8 and Figure 30) PARAMETER MIN 1.1 1.15 ms td2 Delay time, LD to VCH3S (see Figure 9 and Figure 30) 500 750 s td3r Delay time, LD to VOS71 , VCH7 = 4.9 V (see Figure 10 and Figure 30) 500 1000 ns td3f Delay time, LD to VOS71 , VCH7 = 4.9 V (see Figure 10 and Figure 30) 60 100 s td4 Delay time, LD to VLDO3 (see Figure 11 and Figure 30) 300 650 s td5 Delay time, LDO4_ON to VLDO4 (see Figure 12 and Figure 30) 300 650 s td6 Delay time, last CLK to DOUT valid for Normal Mode (see Figure 13, Figure 33, and Figure 39) 100 200 ns td7 Delay time, CLK to DOUT valid for Test0, Test2, Test3, Test5 (see Figure 13, Figure 33, and Figure 39) 100 200 ns td8 Delay time, VLDO2 exceeds VRST1 to XRESET (see Figure 14) 300 600 s 200 15 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 PIN LAYOUT (TOP VIEW) 11 VLDO1 VCC8 VCH8B GND8B VCH2 GND2 VCC1A OUT11A OUT11C GND1C OUT12A 10 VLDO3 GND VCH8A GND8A BOOT2 OUT2 VCC1B OUT11B GND1B OUT12B VCH1A 9 GND_LDOA VLDO2 NC OUT8A OUT8B VCC2 VCC1C GND1A OUT12C VCH1B VCH1C Voltage Output 8 CREF VLDO5 VLDO4 NC NC SSLDO5 BOOT11 BOOT12 ROMWR CLK DIN Power Line 7 READY XRESET PWR_ON LDO4_ON ROMWR TEST LD DOUT GND Line 6 ERR1 ERR2 ERR8 ERR8 TLD VCH4 OUT4 GND4 MOS Gate Drive 5 GND_ANA CBG SS_SYNC ERR4 NC TEST VCH5 VCC5 OUT5 Logic Line 4 ERR5 SS5 ERR7 NC NC GND_LOG FB6 VCH3B VCC7 VOS72 GND_GD Analog Line 3 VOS71 MODE7 SS6 GND NC GND6 FB6 VCH3C OUT3A VCH7 VOS73 Analog Line(CAP) 2 SS3 ERR3 SS2 NC ROSC GND6 ICH6 VCH3S OUT3C GND3B GND3A 1 ERR6 REF6 GND_REG GND CSCP OUT6 VCH6 VCC_GD VCH3A OUT3B GND3C A B C D E F G H J K L Figure 15. Pin Layout 16 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 TERMINAL FUNCTIONS TERMINAL PIN ADDRESS NAME 1 1-A ERR6 O Output of gm amp for CH-6 2 1-B REF6 IO Reference resistor of CH-6 3 1-C GND_REG G Ground for analog circuit of regulators 4 1-D NC 5 1-E CSCP IO Current source of short-circuit protection 6 1-F OUT6 IO Output side terminal of coil L6 for CH-6 7 1-G VCH6 O Output voltage of CH-6 8 1-H VCC_GD V Power supply for gate driver of internal power MOS-FET 9 1-J VCH3A O Output of CH-3 (1/3) 10 1-K OUT3B IO Output side terminal of coil L3 for CH-3 (2/3) 11 1-L GND3C G Ground for CH-3 (3/3) 12 2-A SS3 O Current source of soft-start for CH-3 13 2-B ERR3 O Output of gm amp for CH-3 14 2-C SS2 I Current source of soft-start for CH-2 15 2-D NC 16 2-E ROSC O Reference resistor for PWM oscillator 17 2-F(= 3-F) GND6 G Ground for CH-6(same pin as No.28, 3-F) 18 2-G ICH6 IO LEDs cathode of CH-6 19 2-H VCH3S O Analog switched output of CH-3 NO. I/O DESCRIPTION No connection (recommended to be GND) No connection (recommended to be GND) 20 2-J OUT3C IO Output side terminal of coil L3 for CH-3 (3/3) 21 2-K GND3B G Ground for CH-3 (2/3) 22 2-L GND3A G Ground for CH-3 (1/3)n 23 3-A VOS71 O Gate drive of external PMOS switch for CH-7 24 3-B MODE7 I Mode selection of CH-7 25 3-C SS6 O Current source of soft-start for CH-6 26 3-D NC 27 3-E NC 28 3-F(= 2-F) GND6 G Ground for CH-6 (same pin as No.17, 2-F) 29 3-G(= 4-G) FB6 IO Current sense input of CH-6 (same pin as No.40, 4-G) 30 3-H VCH3C O Output of CH-3 (3/3) 31 3-J OUT3A IO Output side terminal of coil L3 for CH-3 (1/3) 32 3-K VCH7 O Output of CH-7 33 3-L VOS73 O Gate drive of low side NMOS switch for CH-7 34 4-A ERR5 O Output of gm amp for CH-5 35 4-B SS5 O Current source of soft-start for CH-5 36 4-C ERR7 O Output of gm amp for CH-7 37 4-D NC 38 4-E NC 39 4-F GND_LOG G Ground for general logic circuit 40 4-G(= 3-G) FB6 IO Current sense input of CH-6 (same pin as No.29, 3-G) 41 4-H VCH3B O Output of CH-3 (2/3) 42 4-J VCC7 V Power supply of CH-7 43 4-K VOS72 O Gate drive of high side PMOS switch for CH-7 44 4-L GND_GD G Ground for gate driver of internal power MOS-FET 45 5-A GND_ANA G Ground for general analog circuit No connection (recommended to be GND) No connection (recommended to be GND) No connection (recommended to be GND) No connection (recommended to be GND) 17 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 TERMINAL FUNCTIONS (continued) TERMINAL PIN ADDRESS NAME I/O 46 5-B CBG IO Output of BG reference voltage buffer 47 5-C SS_SYNC O Current source of soft-start for CH-1, CH-4 and CH-7 48 5-D ERR4 O Output of gm amp for CH-4 49 5-E NC 50 5-H(= 7-J) TEST I Test mode selection Input of serial I/F (same pin as No.67, 7-J) 51 5-J VCH5 O Output of CH-5 52 5-K VCC5 V Power supply of CH-5 53 5-L OUT5 IO Primary side terminal of coil L5 for CH-5 54 6-A ERR1 O Output of gm amp for CH-1 55 6-B ERR2 O Output of gm amp for CH-2 56 6-C(= 6-D) ERR8 O Output of gm amp for CH-8 (same pin as No.57, 6-D) 57 6-D(= 6-C) ERR8 O Output of gm amp for CH-8 (same pin as No.56, 6-C) 58 6-H TLD I Test mode latch input of serial I/F 59 6-J VCH4 O Output of CH-4 60 6-K OUT4 IO Output side terminal of coil L4 for CH-4 61 6-L GND4 G Ground for CH-4 62 7-A READY O READY output for Sub-CPU 63 7-B XRESET O Low Active RESET output for Sub-CPU 64 7-C PWR_ON I TPS65520 device enable input 65 7-D LDO4_ON I Enable of LDO-4 66 7-H(= 8-J) ROMWR I Voltage bias to write EEPROM (same pin as No.78, 8-J) 67 7-J(= 5-H) TEST I Test mode selection input of serial I/F (same pin as No.50, 5-H) 68 7-K LD I Latch input of serial I/F 69 7-L DOUT O Data output of serial I/F 70 8-A CREF IO Capacitor of RC filter for band-gap reference 71 8-B VLDO5 O Output of LDO-5 72 8-C VLDO4 O Output of LDO-4 73 8-D NC 74 8-E NC 75 8-F SSLDO5 O Current source of soft-start for LDO-5 76 8-G BOOT11 IO Bootstrap for primary side of CH-1 Bootstrap for output side of CH-1 NO. DESCRIPTION No connection (recommended to be GND) No connection (recommended to be GND) No connection (recommended to be GND) 77 8-H BOOT12 IO 78 8-J(= 7-H) ROMWR I Voltage bias to write EEPROM (same pin as No.66, 7-H) 79 8-K CLK I Clock input of serial I/F 80 8-L DIN I Data input of serial I/F 81 9-A GND_LDOA G Ground for analog circuit of LDO-1,LDO-2,LDO-3 82 9-B VLDO2 O Output of LDO-2 83 9-C NC 84 9-D OUT8A IO Output side terminal of coil L8 for CH-8 (1/2) 85 9-E OUT8B IO Output side terminal of coil L8 for CH-8 (2/2) 86 9-F VCC2 V Power supply of CH-2 87 9-G VCC1C V Power supply of CH-1 (3/3) 88 9-H GND1A G Ground for CH-1 (1/3) 89 9-J OUT12C IO Output side terminal of coil L1 for CH-1 (3/3) 90 9-K VCH1B O Output of CH-1 (2/3) 18 No connection (recommended to be GND) TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 TERMINAL FUNCTIONS (continued) TERMINAL PIN ADDRESS NAME I/O 91 9-L VCH1C O Output of CH-1 (3/3) 92 10-A VLDO3 O Output of LDO-3 93 10-B NC 94 10-C VCH8A 95 10-D 96 10-E 97 NO. DESCRIPTION No connection (recommended to be GND) O Output of CH-8 (1/2) GND8A G Ground for CH-8 (1/2) BOOT2 IO Bootstrap for CH-2 10-F OUT2 IO Primary side terminal of coil L2 for CH-2 98 10-G VCC1B V Power supply of CH-1 (2/3) 99 10-H OUT11B IO Primary side terminal of coil L1 for CH-1 (2/3) 100 10-J GND1B G Ground for CH-1 (2/3) 101 10-K OUT12B IO Output side terminal of coil L1 for CH-1 (2/3) 102 10-L VCH1A O Output of CH-1 (1/3) 103 11-A VLDO1 O Output of LDO-1 104 11-B VCC8 V Power supply of CH-8 105 11-C VCH8B O Output of CH-8 (2/2) 106 11-D GND8B G Ground for CH-8 (2/2) 107 11-E VCH2 O Output of CH-2 108 11-F GND2 G Ground for CH-2 109 11-G VCC1A V Power supply of CH-1 (1/3) 110 11-H OUT11A IO Primary side terminal of coil L1 for CH-1 (1/3) 111 11-J OUT11C IO Primary side terminal of coil L1 for CH-1 (3/3) 112 11-K GND1C G Ground for CH-1 (3/3) 113 11-L OUT12A IO Output side terminal of coil L1 for CH-1 (1/3) 19 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 REGISTER MAP Some switching regulators allow the output voltage to be changed according to control register settings. However, changing the voltage setting while a regulator is operating may cause the output to overshoot and exceed the rating. Be careful when dynamically changing the regulator output voltage. LIST OF REGISTERS NAME POSITION parity D[47] - D[40] CH7-SW DESCRIPTION parity data D[38] VOS71, load side switch of CH-7 Dmax7 D[37] - D[36] duty setting of CH-7 Dmax5 D[35] - D[34] duty setting of CH-5 Dmax4 D[33] - D[32] duty setting of CH-4 CH3-SW D[31] - D[30] Load side switch of CH-3 Dmax3 D[29] - D[28] duty setting of CH-3, CH-1(UP,CROSS) and CH-8 Vout7 D[27] - D[24] Voltage setting of CH-7 Vout5 D[23] - D[22] Voltage setting of CH-5 Vout4 D[21] - D[20] Voltage setting of CH-4 Vout3 D[19] - D[16] Voltage setting of CH-3 Vout2 D[15] - D[12] Voltage setting of CH-2 Vout1 D[11] - D[08] Voltage setting of CH-1 LDO5Vo D[07] - D[06] Voltage setting of LDO-5 LDOSW5 D[05] LDO-5 ON/OFF switch D[04] LDO-3 ON/OFF switch LDOSW3 Dmax6 D[03] - D[02] duty setting of CH-6 Vout6B D[01] - D[00] Back-light LED current of CH-6 CH7-SW D[39] D[38] D[37] D[36] ON/OFF * 0 * * OFF * 1 * * ON default Dmax7 D[39] D[38] D[37] D[36] * * 0 * * 0 * * * * DUTY [%] MIN TYP MAX 0 82 86 91 1 77 81 86 1 0 72 76 81 1 1 67 71 76 default Dmax5 20 DUTY [%] D[35] D[34] D[33] D[32] MIN TYP MAX 0 0 * * 84 88 92 0 1 * * 79 83 87 1 0 * * 74 78 82 1 1 * * 69 73 77 default TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 Dmax4 DUTY [%] D[35] D[34] D[33] D[32] MIN TYP MAX * * 0 0 92 94 96 * * 0 1 90 92 94 * * 1 0 88 90 92 * * 1 1 86 88 90 default CH3-SW D[31] D[30] D[29] D[28] ON/OFF 0 0 * * OFF 0 1 * * OFF 1 0 * * OFF 1 1 * * ON default Dmax3 D[31] D[30] D[29] D[28] * * 0 * * * * * * DUTY [%] MIN TYP MAX 0 82 86 91 0 1 77 81 86 1 0 72 76 81 1 1 67 71 76 default recommend Vout7 D[27] D[26] D[25] D[24] 0 0 0 0 0 0 0 0 0 0 Output Voltage [V] DOWN UP 0 3.10 4.90 1 3.05 4.85 1 0 3.00 4.80 0 1 1 2.95 4.75 1 0 0 2.90 4.70 1 0 1 2.85 4.65 0 1 1 0 2.80 4.60 0 1 1 1 2.75 4.55 1 0 0 0 2.70 4.50 1 0 0 1 2.65 4.45 1 0 1 0 2.60 4.40 1 0 1 1 2.55 5.10 1 1 0 0 2.50 5.05 1 1 0 1 3.20 5.00 1 1 1 0 3.15 4.95 1 1 1 1 3.10 4.90 default Vout5 D[23] D[22] D[21] D[20] Output Voltage [V] 0 0 * * -7.5 0 1 * * -8.0 default 21 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 Vout5 (continued) D[23] D[22] D[21] D[20] Output Voltage [V] 1 0 * * -8.5 1 1 * * -9.0 Vout4 D[19] D[18] D[17] D[16] Output Voltage [V] * * 0 0 15.0 * * 0 1 15.5 * * 1 0 16.0 * * 1 1 16.5 default Vout3 D[19] D[18] D[17] D[16] Output Voltage [V] 0 0 0 0 4.90 0 0 0 1 4.85 0 0 1 0 4.80 0 0 1 1 4.75 0 1 0 0 4.70 0 1 0 1 4.65 0 1 1 0 4.60 0 1 1 1 4.55 1 0 0 0 4.50 1 0 0 1 5.20 1 0 1 0 5.15 1 0 1 1 5.10 1 1 0 0 5.05 1 1 0 1 5.00 1 1 1 0 4.95 1 1 1 1 4.90 default Vout2 22 D[15] D[14] D[13] D[12] Output Voltage [V] 0 0 0 0 1.20 0 0 0 1 1.15 0 0 1 0 1.10 0 0 1 1 1.80 0 1 0 0 1.75 0 1 0 1 1.70 0 1 1 0 1.65 0 1 1 1 1.60 1 0 0 0 1.55 1 0 0 1 1.50 1 0 1 0 1.45 1 0 1 1 1.40 1 1 0 0 1.35 1 1 0 1 1.30 1 1 1 0 1.25 1 1 1 1 1.225 default TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 Vout1 D[11] D[10] D[09] D[08] Output Voltage [V] 0 0 0 0 2.80 0 0 0 1 2.75 0 0 1 0 2.70 0 0 1 1 2.65 0 1 0 0 2.60 not recommended 0 1 0 1 2.55 not recommended 0 1 1 0 2.50 not recommended 0 1 1 1 3.20 1 0 0 0 3.15 1 0 0 1 3.10 1 0 1 0 3.05 3.05 1 0 1 1 3.00 1 1 0 0 2.95 1 1 0 1 2.90 1 1 1 0 2.85 1 1 1 1 2.825 default LDO5Vo D[07] D[06] D[05] D[04] Output Voltage [V] 0 0 * * 13.5 0 1 * * 12.5 1 0 * * 12.0 1 1 * * 8.5 default LDOSW5 D[07] D[06] D[05] D[04] ON / OFF * * 0 * OFF * * 1 * ON ON / OFF default LDOSW3 D[07] D[06] D[05] D[04] * * * 0 ON * * * 1 OFF default Dmax6 D[03] D[02] D[01] D[00] 0 0 * 0 1 * 1 0 1 1 DUTY [%] MIN TYP MAX * 87 89 91 * 89 91 93 * * 91 93 95 * * 93 95 97 default 23 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 Vout6B D[03] D[02] D[01] D[00] Output Current [mA] * * 0 0 12.0 * * 0 1 20.0 * * 1 0 8.0 * * 1 1 OFF EEPROM MAP Note: TI is shipping ICs with recommended values. DEFAULT VALUE SETUP BITS NAME Test Mode (none) POSITION D[47] - D[45] (D[44]) DESCRIPTION 001: Test1 (write), 010: Test2 (read) (not used) TRIM_DTC0 D[43] - D[42] Trimming for DTC of Tr/Tf, CH-1,CH-2 TRIM_DTCR0 D[41] - D[40] Trimming for DTC of Tr, CH-3,CH-8 TRIM_DTCR1 D[39] - D[38] Trimming for DTC of Tr, CH-7 TRIM_DTCF0 D[37] - D[36] Trimming for DTC of Tf, CH-3,CH-8 TRIM_DTCF1 D[35] - D[34] Trimming for DTC of Tf, CH-7 TRIMMING BITS NAME POSITION DESCRIPTION Test Mode D[47] - D[45] TRIM_BG (5[bit]) 100: Test1(write), 101: Test2 (read) Trimming for band-gap reference voltage TRIM_OSC (3[bit]) Trimming for oscillator frequency TRIM_GAIN0 (2[bit]) Trimming for AMP gain of CH-1 TRIM_VOFF0 (2[bit]) Trimming for AMP offset voltage of CH-1 PROTECTION STATUS READ MAP NAME Test Mode POSITION D[47] - D[45] DESCRIPTION 011: Test3 SCP7 D[12] (none) (D[11]) SCP5 D[10] SCP5 to previous system down SCP4 D[09] SCP4 to previous system down SCP3 D[08] SCP3 to previous system down SCP2 D[07] SCP2 to previous system down SCP1 D[06] SCP1 to previous system down OVP7 D[05] OVP7 to previous system down OVP6 D[04] OVP6 to previous system down OVP3 D[03] OVP3 to previous system down OVP2 D[02] OVP2 to previous system down TSD D[01] TSD to previous system down 24 SCP7 to previous system down (not assigned, always L) default TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 TPS65520 BLOCK CONFIGURATION VCC8 MODE7 ERR7 VOS73 VOS72 VCC7 VCH7 VOS71 REF6 SS6 ERR6 GND6 OUT6 FB6 ICH6 VCH6 Figure 16 shows the overall block configuration of the TPS65520. Note that the figure is simplified for clarity and does not show accurate details for the IC wiring, pin layout, and internal component layout. VCH8A, VCH8B OUT8A, OUT8B GND8A, GND8B CH-7 CH-8 CH-1 CH-6 ERR8 OCP CH-2 CH-3 REFERENCE EEPROM BG BUF OSC LDO-4 LDO-5 LDO-1 LDO-2 LDO-3 XRESET OVP TPS65520 RESET READY TSD LOGIG SERIAL I/F PWR_ON CLK DIN LD DOUT TEST TLD GND_LOG ROMWR SCP PROTECTION CSCP BOOT11 VCC1A, VCC1B, VCC1C OUT11A, OUT11B, OUT11C BOOT12 VCH1A, VCH1B, VCH1C OUT12A, OUT12B, OUT12C GND1A, GND1B, GND1C ERR1 SS_SYNC VCH2 BOOT2 VCC2 OUT2 GND2 ERR2 SS2 VCH3S VCH3A, VCH3B, VCH3C OUT3A, OUT3B, OUT3C GND3A, GND3B, GND3C ERR3 SS3 CH-4 VCH4 OUT4 GND4 ERR4 CH-5 VCH5 VCC5 OUT5 ERR5 SS5 To all of CH-x VCC_GD GND_REG GND_GD LDO4_ON VLDO4 VLDO5 SSLDO5 ROSC GND_ANA CBG CREF VLDO1 VLDO2 VLDO3 GND_LDOA Figure 16. TPS65520 Block Diagram 25 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 FUNCTIONAL DESCRIPTION COMMON SWITCHING REGULATOR FUNCTIONS The following sections describe the common features for all switching regulators. MAXIMUM DUTY CYCLE CONTROL The maximum duty cycle control is applied to each channel to prevent a 100% on condition. For CH-3, CH-4, CH-5, CH-6, and CH-7, control registers are provided to adjust the maximum duty cycle settings that affects the channel characteristics substantially. For CH-1 (step-up and step-up/down) and CH-8, which have relatively large margins for maximum duty cycle control, settings are linked to CH-3 to simplify circuits. Table 3 lists settings for each channel: Table 3. Settings for Each Channel CHANNEL CONTROL SETTINGS CH-1 (step-up, step-up/down) (Dmax3) CH-1 (step-down) Fixed at 95% CH-2 Fixed at 95% CH-3 Dmax3 CH-4 Dmax4 CH-5 Dmax5 CH-6 Dmax6 CH-7 Dmax7 CH-8 (Dmax3) DEAD TIME CONTROL The synchronous rectification channels are subjected to dead time control to prevent a flow-through current. The dead time for each channel is fixed by the EEPROM, as shown in Table 4: Table 4. Channel CH-1 CH-2 CH-3 CH-7 CH-8 Dead time 30[ns] 30[ns] 30[ns] 40[ns] 30[ns] CH-1 CH-1 is a step-up/down switching regulator for I/F 3-V power supplies, including those for the main processor, TMS320TM DSP family, and ASIC. Figure 17 shows its block diagram and the connection of external devices. CH-1 operates by automatically switching between two modes: step-up to step-up/down mode and step-down mode. In Step-up to step-up/down mode, the channel shifts between step-up and step-up/down operations within the single mode. Table 5 shows the rough relationship between the input voltage and CH-1 mode. Note that the threshold values shown in the table are merely guidelines because the actual CH-1 circuit finely adjusts the threshold voltages to maximize efficiency. Electrical Characteristics section for the voltage specifications of thresholds for switching between step-up to step-up/down mode and step-down mode (Vmod11 and Vmod12). CH-1 incorporates a voltage retention circuit that maintains the boosting power supply voltage when the channel is performing step-up only or step-down only operation. CH-1 supports the SCP and soft-start functions. The soft-start function is common to CH-1, CH-4, and CH-7. 26 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 Table 5. VCC1 [V] (1) (1) CH-1 MODE OPERATION ~ 2.3 Step-up to step-up/Down Step-up 2.3 ~ 3.78 Step-up to step-up/down Step-up/down 3.5 ~ Step-down - The voltages shown are for guideline purposes only. VCC1 SCP VCC_GD + UP-CROSS CONTROL VCH3 - L1 DTC/MODE DAC MAX DUTY BOOT12 VCH1 BOOT12 VCH3 + + - 0.85[V] GND_REG OUT11 GND_REG - + + GND_REG BOOT11 VCC_GD VCH3 BOOT11 TRIM_DTC0 VCH3 Vout1 VIN VCC_GD GND_REG OUT12 CCH1 GND_REG SS_SYNC SSSYNC GND_REG GND1 ERR1 CERR1 Figure 17. CH-1 Block Diagram CH-2 CH-2 is a step-down switching regulator for core 1.x-V power supplies, including those for the main processor, TMS360TM DSP family, and ASIC. Figure 18 shows the block diagram and the connection of external devices. CH-2 supports the OVP, SCP and soft-start functions. 27 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 VCH2 VCH3 VCH3 VCC_GD OVP SCP BOOT2 VCH3 TRIM_DTC0 VIN VCC2 VCH3 - + + BOOT2 MAX DUTY + + - DAC OUT2 DTC Vout2 L2 VCC_GD 0.85[V] GND_REG GND_REG SS2 SS2 GND_REG GND_REG GND_REG CCH2 GND2 ERR2 CERR2 Figure 18. CH-2 Block Diagram CH-3 CH-3 is a step-up switching regulator for 5-V power supplies, including those for the motor and audio IC. Figure 19 shows its block diagram and the connection of external devices. CH-3 incorporates a PMOS switch, which prevents the input voltage from appearing on the output side when the channel is turned off. Without the switch, the parasitic diode in the internal PMOS carries the input voltage from coil (L3) and causes a current to flow into the load. This switch turns the VCH3S output pin on or off according to the settings in the CH3-SW control register. The motor driver, as a load for CH-3, is a switch itself. It does not have a current path so that it can be connected to the VCH3 pin. Other current loads, which may have current paths, are intended to be connected to the VCH3S pin. When CH-3 is activated, CH-8 supplies power to CH-3. To prevent overload on CH-8 during startup, CH-3 compares VCH8 and VCH3 and performs asynchronous rectification using a body diode until VCH3 exceeds VCH8. CH-3 supports the OVP, SCP and soft-start functions. When using the TPS65520, note the following: * The following conditions must be satisfied to use a 5-V ac adaptor: - An appropriate voltage drop circuit is provided so that the input voltages for step-up CH-3 are at least 0.3 V lower than the values specified with the control register. 28 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 Internal Power Supply VCH8 OVP SCP VCC_GD VCH3S EN3S TRIM_DTCR0, GND_GD TRIM_DTCF0 Dmax3 Vout3 - + + VCC_GD MAX DUTY VIN VCH3 L3 OUT3 DTC + + - DAC VCC_GD 0.85[V] CCH3 GND_REG GND_REG GND_REG SS3 GND_REG GND_REG GND3 ERR3 SS3 CERR3 Figure 19. CH-3 Block Diagram CH-4 CH-4 is a step-up switching regulator for 15-V power supplies the LCD and CCD. Figure 20 shows its block diagram and the connection of external devices. CH-4 is controlled by asynchronous rectification because it outputs a high voltage and does not benefit much from synchronous rectification. An external SBD is connected between the OUT4 and VCH4 pins as a rectification device for CH-4. CH-4 supports the SCP and soft-start functions. The soft-start function is common to CH-1, CH-4, and CH-7. VCH3 VCH3 SCP VCH4 D4 Vout4 VCH3 OUT4 VCH3 - + + MAX DUTY VCC_GD + + - DAC GND_REG SS_SYNC SSSYNC CCH4 GND4 0.85[V] GND_REG VIN L4 Dmax4 GND_REG GND_REG GND_REG ERR4 CERR4 Figure 20. CH-4 Block Diagram 29 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 CH-5 CH-5 is an inversion switching regulator for -8-V power supplies for the LCD and CCD. Figure 21 shows its block diagram and the connection of external devices. CH-5 supports the SCP and soft-start functions. VCH3 VCH3 Dmax5 Vout5 VCH3 0.85[V] DAC VCH3 MAX DUTY + VCC_GD + + + - - GND_REG VCH3 VCC5 D5 OUT5 GND_GD SCP L5 GND_REG GND_REG CCH5 GND_REG VCH5 ERR5 SS5 CERR5 SS5 Figure 21. CH-5 Block Diagram CH-6 CH-6 is a step-up switching regulator for driving the power supply for the LCD backlight LED. CH-6 is controlled by monitoring the current flowing through the LED so that it operates as a constant-current driver. Figure 22 shows the block diagram and the connection of external devices. The output current for CH-6 can be finely adjusted using the REF6 pin. The output current becomes the value specified with the Vout6B control register when the potential of the REF6 pin equals that of the CBG pin. Note that the REF6 pin always expects a voltage to be applied. One example to ensure that an appropriate voltage is applied to the REF6 pin, is to connect it to a DAC or to the CBG pin through a resistor. The following formulas show the relationship between the voltage on the REF6 pin and that on the FB6 pin, which senses the output current: 20 mA setting V(FB6) = 0.52 x V(REF6) - 0.002 12 mA setting V(FB6) = 0.52 x V(REF6) - 0.177 8 mA setting V(FB6) = 0.52 x V(REF6) - 0.265 For example, when using 0.85 V of CBG as reference voltage and using 22 of recommended sense resistor, the caluculation is like this: IO = V(FB6) / Rsense = (0.52 x 0.85 V - 0.002) / 22 = 20 mA. CH-6 supports the OVP, SCP and soft-start functions. Without serial I/F control, CH-6 is controlled by the voltage of REF6. When the potential of REF6 is out of range between VREF6L and VREF6H, CH-6 is OFF in logical. Soft-start is reset. 30 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 CH-7 According to the state of the MODE7 pin, CH-7 operates either as a step-up switching regulator for 5-V power supplies, including those for the motor and audio IC, or as a step-down switching regulator for I/F 3-V power supplies, including those for the main processor, TMS320TM DSP family, and ASIC. Table 6 shows the relationship between the state and mode: Table 6. MODE7 MODE H Step-up L Step-down CH-7 requires different external component connections depending on the MODE7 pin state. Figure 23 shows its block diagram and the connection of external devices for step-up mode. Figure 24 shows its block diagram and the connection of external devices for step-down mode. When using the TPS65520, note the following: * The following conditions must be satisfied to use a 5-V ac adaptor: - An appropriate voltage drop circuit is provided so that the input voltages for step-up CH-7 (MODE7 = H) are at least 0.3 V lower than the values specified with the control register. For Control Using Thermistor VCH1 VCH1 + x0.26 - CBG VCH6 VCH3 LEDx VCH3 OVP 0.85[V] GND_REG VCH1 + - VCH3 Vout6B VCH1 REF6 x2 DAC D6 Dmax6 GND_REG te MAX DUTY - + + VCC_GD + + - GND_REG CCH6 OUT6 GND6 GND_REG DAC IC VIN L6 VCH3 VCC_GD ICH6 EN6 GND_REG GND_REG OCP GND_REG FB6 RSNS6 For Control Using DAC SS6 SS6 ERR6 CERR6 Figure 22. CH-6 Block Diagram 31 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 VCH7 VCH3 VCH3 PM72 VLDO1 VOS71 OVP SCP EN7S GND_GD MODE7 Dmax7 Vout7 VCH3 - + + VIN VCC7 MAX DUTY VCH3 VOS72 DTC/ MODE + + - DAC L7 PM71 VCC_GD GND_REG GND_REG NM71 VOS73 0.85[V] GND_REG SS_SYNC GND_REG GND_REG TRIM_DTCR1, TRIM_DTCF1 GND_GD CCH7 ERR7 SSSYNC CERR7 Figure 23. CH-7 Block Diagram (Step-up) VCH7 VCH3 VCH3 OVP SCP VOS71 EN7S GND_GD MODE7 Dmax7 Vout7 VCH3 - + + VCH3 VCC7 MAX DUTY VCH3 VOS72 DTC/ MODE + + - DAC PM71 L7 VCC_GD VOS73 0.85[V] GND_REG GND_REG GND_REG GND_REG SS_SYNC ERR7 SSSYNC CERR7 GND_REG TRIM_DTCR1, TRIM_DTCF1 GND_GD NM71 CCH7 Figure 24. CH-7 Block Diagram (Step-down) As shown in Figure 24, the step-down circuit configuration uses CH-3 as an input power supply that ensures a voltage higher than the output voltage. CH-7 has the VOS71 pin for controlling a separate PMOS switch, preventing the input voltage from appearing on the output side when the channel is turned off (MODE7 = H). Without the switch, the parasitic diode in the external PMOS carries the input voltage from coil (L7) which causes a current to flow into the load. This switch turns on or off according to the settings in the CH7-SW control register. When CH-7 is activated, CH-8 supplies power to CH-7. To prevent overload on CH-8 during startup, CH-7 compares VCH8 and VCH7 and performs asynchronous rectification using a body diode until VCH7 exceeds VCH8. CH-7 supports the OVP, SCP and soft-start functions. The soft-start function is common to CH-1, CH-4, and CH-7. 32 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 When CH-7 is not used, handle the pins as shown in Table 7. CH-7 enters step-down mode with its state equal to the stable output state, stopping operation. Table 7. PIN HANDLING ERR7 0.1 F - Connect a 0.1-F capacitor between the pin and ground VCH7 VCH1 - Short-circuit to VCH1 VOS71 Open MODE7 Short-circuit to the ground VCC7 Open VOS72 Open VOS73 Open CH-8 CH-8 is a step-up switching regulator for LDO-1, LDO-2, LDO-3, LDO-4, and the internal power supplies of the TPS65520. CH-8 is a 3.6-V output regulator that outputs the input voltage (VCC8) when it is higher than 3.6 V. CH-8 is turned on whenever the battery and/or ac adaptor is connected. It operates in skip mode while the PWR_ON pin is low, meaning that only the Sub-CPU real-time clock is operating. Once the PWR_ON pin is driven high, CH-8 enters synchronous rectification mode, where it can supply the maximum load current. CH-8 has a startup circuit that can start with a low input voltage because the startup of CH-8 enables the entire DSC system to start up. It outputs 3.6 V from a minimum input voltage (VCC8) of 1.6 V. See the CH-8 operating sequence for details of starting CH-8. Figure 25 shows its block diagram and the connection of external devices. CH-8 supports the soft-start function. - + WakeUp SKIP TRIM_DTCR0, TRIM_DTCF0 GND_REG - VCC_GD DTC/ MODE MAX DUTY + VIN + + - READY VCH8 OUT8 L8 VCC_GD 0.85[V] CCH8 GND_REG GND_REG GND_REG GND_REG GND_REG GND8 ERR8 CERR8 Figure 25. CH-8 Block Diagram 33 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 LDO-1 LDO-1 takes the CH-8 output voltage as an input and then outputs a voltage of 2.9 V. LDO-1 supports a current limit function, which reduces the output voltage when the current exceeds the specified value. LDO-2 LDO-2 takes the CH-8 output voltage as an input and then outputs a voltage of 2.9 V. LDO-2 supports a current limit function, which reduces the output voltage when the current exceeds the specified value. LDO-3 LDO-3 takes the CH-8 output voltage as an input and then outputs a voltage of 3.1 V. LDO-3 supports a current limit function, which reduces the output voltage when the current exceeds the specified value. LDO-3 can be turned on/off using the LDOSW3 control register. A delay is inserted before LDO-3 is turned on so that the entire system can start up and be stable. LDO-3 cannot be turned on until approximately 30 s elapse after the detection of READY. DELAY2 in Figure 29 represents this delay. LDO-4 LDO-4 takes the CH-8 output voltage as an input and then outputs a voltage of 3.1 V. LDO-4 supports a current limit function, which reduces the output voltage when the current exceeds the specified value. To prevent an inrush current during startup, LDO-4 has a delay so that it is not turned on simultaneously with LDO-3. LDO-4 cannot be turned on until 1.03 ms elapses after the detection of READY. This ensures that LDO-4 is not turned on until 1 ms elapses after the startup of LDO-3, which is turned on 30 s after READY detection. DELAY3 in Figure 29 represents this delay. LDO-4 is controlled using the LDO4_ON pin, as follows: USB ON ON/OFF H On L Off LDO-5 LDO-5 takes the CH-4 output voltage as an input and then outputs a voltage of 8.5 V to 13.5 V for the LCD panel. LDO-5 supports a current limit function, which reduces the output voltage when the current exceeds the specified value. LDO-5 can be turned on/off using the LDOSW5 control register. LDO-3 has a soft-start pin due to the power it drives. PROTECTION FUNCTIONS TSD The thermal shutdown (TSD) function protects the TPS65520 from overheat. If the TSD activates, the TPS65520 stops all channels other than CH-8. CH-8 expects that the Sub-CPU drives PWR_ON low due to the stop of CH-1 and CH-2, causing the TPS65520 to enter skip mode. SCP The short-circuit protection (SCP) function protects the output of each switching regulator from short-circuiting. If the SCP activates, the TPS65520 stops all channels other than CH-8. CH-8 expects that the Sub-CPU drives PWR_ON low due to the stop of CH-1 and CH-2, causing the TPS65520 to enter skip mode. Figure 26 shows the block diagram, the connection of external devices, and the per-channel short-circuit information from the control section for each switching regulator 34 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 + Per-Channel Short-Circuit Information From Control section For each Switching Regulator - Skip CH-8 Disable Other Channels CSCP CSCP Figure 26. SCP Block Diagram OVP The overvoltage protection (OVP) function protects the CH-2, CH-3, CH-6, and CH-7 outputs from overvoltage. If the OVP for CH-6 activates, the TPS65520 internally latches the CH-6 OVP and disables CH-6. The MOS switch between ICH6 and FB6 is designed to remain on if the OVP activates and discharges the VCH6 potential through a diode and sense resistor. To cancel the OVP for CH-6, drive PWR_ON low. The OVP for CH-6 affects the CH-6 output only. If the OVP for a channel other than CH-6 activates, the TPS65520 disables the power MOS-FET switching for that channel while still allowing the operation of the channel. The OVP for channels other than CH-6 does not have a latch function so that the TPS65520 automatically restores normal operation once it exits from the overvoltage state. OCP The overcurrent protection (OCP) function protects the CH-6 output from overcurrent. The OCP monitors the FB6 pin and, if its voltage exceeds 0.85 V, it determines that an overcurrent is flowing through CH-6. If the OCP activates, the TPS65520 disables power MOS-FET switching for CH-6 while still allowing the operation of CH-6. In the same way as with the OVP, the MOS switch between ICH6 and FB6 is designed to remain on if the OCP activates and discharges the VCH6 potential through a diode and sense resistor. The TPS65520 restarts switching once the voltage on the FB6 pin falls below 0.85 V. The OCP does not have a latch function so that the TPS65520 automatically restores normal operation once it exits from the overcurrent state. SUB-CPU CONTROL (RESET) The Sub-CPU function monitors the LDO-2 voltage to output XRESET, and it monitors VCH8 to output READY. Figure 27 shows a block diagram of this function. 35 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 VCH8 READY + - VREADYx VLDO2 LDO-2 XRESET + DELAY - VRSTx Figure 27. Sub-CPU Control Block Diagram OPERATION SEQUENCE SOFT-START The soft-start function of the TPS65520 controls the constant-current charging of the capacitors connected to the SS_SYNC, SS2, SS3, SS5, SS6, and SSLDO5 pins based on their pin voltages. When the voltage at a soft-start pin becomes approximately 0.85 V, its corresponding regulator output becomes 100%. SOFT-START OK SIGNAL FOR CH-3 The soft-start circuit for CH-3 has a logic output (internal signal) function that indicates the end of soft-start for sequence control. Figure 28 shows the entire soft-start circuit. As shown, the voltage on the SS3 pin is used as a reference for the CH-3 control section. The control section operates based on the SS3 voltage or the band gap buffer reference voltage for the CBG pin, whichever is lower. In Figure 28, the comparator that outputs the SS3OK signal implements the logic output function for sequence control. The threshold value for the comparator is set to a value (VSS3OK) that is sufficiently higher than the band gap buffer reference voltage. It can be assumed that CH-3 has been started when the comparator outputs the SS3OK signal, except when the CH-3 load is heavy or short-circuited. 36 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 VCH3 CH-3 Soft Start Circuit SS3OK_DET + SS3OK - SS3 ErrorAmp >> 0.85[V] 0.85[V] - + + Figure 28. CH-3 Soft-Start Circuit SEQUENCE CONTROL Most operations of the TPS65520 are controlled by the Sub-CPU. When a valid power supply, ac adaptor, or battery is inserted, the TPS65520 automatically activates the Sub-CPU. If a Sub-CPU does not exist, the TPS65520 automatically activates the regulators and LDOs using the default values for control registers. Figure 29 shows the connection of enable signals for the TPS65520. Figure 30 shows a timing chart. In Figure 30, ENREGs, EN3S, EN6, EN7, ENLDO3, and ENLDO5 represent the internal enable signals shown in Figure 29. The following describes the relationship among enable signals in 1. Upon power-up, the TPS65520 starts the wake-up circuit for CH-8 and activates the VCH8 potential. In the figure, only CH-8 is operating. 2. Once VCH8 rises, the READY detection circuit is activated and detects READY. 3. Upon the detection of READY, CH-8 exits from the wake-up state and enters skip mode. At this time, the blocks in the upper half of the figure can operate. They are turned on if the enable logic signal is valid. 4. In skip mode after wake-up, CH-8 enters PWM mode when PWR_ON is driven high. a. PWR_ON has a delay of approximately 60 s to ensure that the OSC starts completely before channels start operating. DELAY0 in the figure represents this delay. b. A delay of approximately 1 ms is inserted to ensure that CH-8 enters PWM mode completely before channels start operating. DELAY1 in the figure represents this delay. 5. Once CH-8 enters PWM mode, each switching regulator channel starts operating. CH-3 starts first. The SS3OK signal from CH-3 causes other channels to start. In Figure 30, the TPS65520 performs the following operation, described along the time axis in the figure: 1. In response to CH-8 starting up, the internal logic reset signal is generated at the same time as READY being canceled, thus resetting the maintained status values. 2. On the rising edge of PWR_ON, CH-8 exits from skip mode and enters PWM mode. The DELAY0 and DELAY1 blocks, shown in the upper part of Figure 29, insert delays to ensure that the mode transition is over before channels start operating, resulting in a total delay of 544 PWM pulses to complete this process. 3. Upon the mode transition of CH-8, CH-3 starts using the soft-start procedure. 4. The SS3OK signal output during the soft-start of CH-3 causes all other blocks to be enabled at one time, after which normal operation starts. 5. On the falling edge of SYDDON, all channels are disabled at one time. 37 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 The shaded portions of Figure 30 represent the on/off control applied by the Sub-CPU (if used) through the serial interface. If a Sub-CPU is used, control registers are written between the rising edges of XRESET and PWR_ON. Any channels that have been turned off do not start until the Sub-CPU turns them on again. If the Sub-CPU specifies off for a channel that has been active from the startup, the channel goes off from that instant. If a Sub-CPU is not used, the timing waveforms do not have the shaded portions. All channels are turned on with default values set in the control registers. 38 SS SS2C SS3C SSOK SSSYNC PON SS SSSC SS3OK0 SSOK SS2 PON SS3OK PON SS SSOK SS3 SS PON SS PON SS PON ENREGs0 ENREGs READY detect CH-7 CH-2 CH-3 SCP OVP SCP OVP SCP OVP IBIAS PON 32[PWM Pulse] DELAY0 SS PON CH-4 SS SSOK SS5 PON PWM VCH8 SCP SS5C D[31:30] 11 OSC PON WAKEUP_OFF 0:SKIP 1:PWM CH-8 DELAY1 SS SS 512[PWM Pulse] SCP CH-1 DELAY3 VCH3S ON SCP D[1:0] 11 CH-5 PON PON EN3S 16[PWM Pulse] DELAY2 LDO4_ON PON READY REF085 512[PWM Pulse] EN6 SSOK SS6 PON SS SS6C IN OVP6 PON XERR D[4] = 0 OCP SCP VCH8 EN7S LDO-5 PON LDO-2 PON ENLDO5 TSD PON XERR D[5]= 0 LDO-3 PON LDO-1 PON PON CH-6 SS SCP PON XERR OVP PON XERR ENLDO3 D[39:38] 11 LDO-4 PON BG PON VOS71 NOERR PWR_ON TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 Figure 29. Enable Signal Connections The shaded portions apply only when a Sub-CPU is used. 39 40 Figure 30. Operation Sequence Chart VOS71 ENLDO3 VLDO3 LDO4_ON VLDO4 ENLDO5 SSLDO5 VLDO5 PWR_ON ENREGs SS3 VCH3 SS3OK SS_SYNC VCH1 VCH4 VCH7 SS2 VCH2 SS5 VCH5 CH3-SW Vout6B CH7-SW LDOSW3 LDOSW5 EN3S VCH3S EN6 SS6 VCH6 EN7S XRESET READY LD DIN VCH8 VLDO1 Battery OFF ON OFF ON OFF td0 dataA td1 OFF ON OFF ON OFF dataB OFF ON ON ON dataC td2 90[%] ON OFF ON ON ON dataD td3 50[%] ON ON OFF ON ON dataE td3r 50[%] ON ON ON OFF ON dataF td4 90[%] ON ON ON ON OFF dataG This sequence only appears when Sub-CPU exists. td5 90[%] TPS65520 SLVS557A - MARCH 2005 - REVISED JUNE 2005 www.ti.com TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 SERIAL INTERFACE, CONTROL REGISTERS, AND EEPROMS The logic control section of the TPS65520 consists of the serial interface, control registers, and EEPROMs. See the EEPROM MAP section for details of control registers, EEPROMs, and the bit assignment for reading the protection states. The logic section operates in either of two operating modes: para mode or test mode. Each mode is described in this section. Figure 34 shows the overall block configuration. In the figure, the 48-bit Shift Register block accepts D[47] (MSB) last in the time sequence. Figure 31 shows the configuration of the parity judgment circuit. D[47:40] 0F(hex) D[31:24] D[23:16] D[15:08] D[07:00] All signal lines are 8-bit size. EX-OR gates operate bit-wise calculation. D[39:32] Figure 31. Configuration for Parity Bit Calculation NORMAL MODE Driving the TEST input signal low selects para mode. In this mode, the TPS65520 allows access to the control registers. Figure 32 shows the shift register configuration from input DIN to output DOUT. Figure 33 shows a single access cycle. As shown in Figure 33, once 48 bits have been input to the shift register, the TPS65520 determines the parity according to the output from DOUT and latches the input data using the LD input signal. In para mode, DOUT directly reflects the output from the parity check block, which is a random logic circuit. Note, therefore, that any circuit that responds to the edge of DOUT may cause malfunctioning connections. In para mode, the EEPROMs send the written data to each internal block. 47 DIN 44 43 parity 40 39 36 35 32 31 28 27 Dmax7 Dmax5 Dmax4 CH3-SWDmax3 24 23 Vout7 20 19 Vout5 Vout4 16 15 Vout3 12 11 Vout2 08 07 Vout1 CH7-SW 04 03 Dmax6 0 Vout6B DOUT LDOSW3 LDOSW5 LDO5Vo Figure 32. Shift Register Configuration in Para Mode 41 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 ts1 ts2 tcyc th2 th1 td6 LD DIN bitX bit0 bit1 bit2 bit45 bit46 CLK tw3 DOUT TEST (zero) TLD (zero) Figure 33. Serial Interface Timing Chart in Para Mode 42 bit47 bitY STAT[12:0] TLD ROMWR LD D[47:45] D[39:0] D[45:0] D[47:45] D[47:0] DATA XALL0 SCLK Decoder 111 110 101 100 011 010 001 000 T7 T6 T5 T4 T3 T2 T1 T0 D[39:0] E[39:0] LOAD CLK DIN 1 x40 0 DLOAD[45:0] LATCH 40[bit] DI[39:0] Control Data D[47:0] DATA[47:0] 48[bit] Shift Register XRESET LATCH DI[14:0] XRESET LATCH FF Q DI[47:0] D TRY D[14:0] check parity WriteProtect Latch 15[bit] TRY WriteData D[14:0] EEPROM Latch 15[bit] WriteData EEPROM E[39:0] D[47:0] DI[14:0] DO[39:0] DOUT GOOD WD1[14:0] WD2[14:0] DIN CLK 15[bit] DO[14:0] GOOD EEPROM 0 1 PROGRAM DI[(M-1):0] EEPROM V_WR DO[14:0] 15[bit] PROGRAM V_WR DI[(N-1):0] HIGH ED1[14:0] ED2[14:0] TEST x 13 x 15 x 15 x40 RD[39:0] x40 Zero padding 0 1 x 15 0 1 x 15 0 1 ETRM[14:0] EUSR[14:0] CTRL_REG[39:0] DOUT TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 Figure 34. Serial Interface Block Diagram 43 D[45:0] TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 TEST MODE Driving the TEST input signal high selects test mode. In this mode, the TPS65520 allows access to all logic functions, including EEPROMs. The following test operations are supported: * Test A: In the same way as Para mode, the TPS65520 allows access to the control registers. Unlike the para mode, no parity check is performed. The parity judgment result is internally fixed to OK and the contents of the shift register are sent to DOUT. * Test 0: The contents of the control registers are copied to the shift register in synchronization with the TLD input signal. After copying, a CLK input causes the control register value to appear at DOUT. * Test 1: Prepare (latch) the data to be written to the user setup EEPROM. When Test 6 is performed subsequently, the latched data is written to the EEPROM. After the data is latched, any internal blocks that reference values from EEPROM will see the latched data, instead of the data stored in EEPROM. * Test 2: The contents of the user setup EEPROM are copied to the shift register in synchronization with the TLD input signal. After copying, a CLK input causes the value from the user setup EEPROM to appear at DOUT. * Test 3: The states of the protection functions are copied to the shift register in synchronization with the TLD input signal. After copying, a CLK input causes the protection state value to appear at DOUT. * Test 4: Prepare (latch) the data to be written to the trimming EEPROM. When Test 7 is performed subsequently, the latched data is written to the EEPROM. After the data is latched, any internal blocks that reference values from EEPROM will see the latched data, instead of the data stored in EEPROM. * Test 5: The contents of the trimming EEPROM are copied to the shift register in synchronization with the TLD input signal. After copying, a CLK input causes the value from the trimming EEPROM to appear at DOUT. * Test 6: Data is written to the user setup EEPROM. * Test 7: Data is written to the trimming EEPROM. * Test Mode Switching: Test A does not require a transition to a special mode. Its operation is the same as in normal mode, except the difference in the DOUT output. * Tests 0 to 7 require explicit mode switching using the Decoder shown in Figure 34. The Decoder uses the three high-order bits in the shift register to change the mode. Table 8 shows the bit assignment. Table 8. Bit Assignments D[47] * D[46] D[45] MODE * * * Test A 0 0 0 Test 0 0 0 1 Test 1 0 1 0 Test 2 0 1 1 Test 3 1 0 0 Test 4 1 0 1 Test 5 1 1 0 Test 6 1 1 1 Test 7 Information Read Mode: In Test mode, Tests 0, 2, 3, and 5 have a common function: copy some TPS65520 internal logic values to the shift register and read them from DOUT. Since their operations are similar, this section describes them together. Figure 35 to Figure 38 shows the shift register configuration from input DIN and output DOUT as well as changes in the shift register caused by a TLD input pulse. 44 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 47 DIN 44 43 0 0 0 0 0 0 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 08 07 04 03 0 DOUT TLD pulse DIN DOUT Dmax7 Dmax5 Dmax4 CH3-SWDmax3 Vout7 Vout5 Vout4 Vout3 Vout2 Vout1 Dmax6 CH7-SW Vout6B LDOSW3 LDOSW5 LDO5Vo Figure 35. Shift Register Configuration and Changes for Test 0 DIN 47 0 44 43 1 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 08 07 04 03 0 0 DOUT TLD pulse DIN 0 1 0 ("0" for unused bits) DOUT TRIM_DTCF1 TRIM_DTCF0 TRIM_DTCR1 TRIM_DTCR0 TRIM_DTC0 Figure 36. Shift Register Configuration and Changes for Test 2 DIN 47 0 44 43 1 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 08 07 04 03 0 1 DOUT TLD pulse DIN 0 1 1 ("0" for unused bits) DOUT SCP7 (none) SCP5 SCP4 SCP3 SCP2 SCP1 OVP7 OVP6 OVP3 OVP2 TSD SKP Figure 37. Shift Register Configuration and Changes for Test 3 DIN 47 1 44 0 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 08 07 04 03 0 1 DOUT TLD pulse DIN 1 0 1 TRIM_BG(5bit) TRIM_OSC(3bit) TRIM_GAIN0(2bit) TRIM_VOFF0(2bit) TRIM_ICHG(1bit) ("0" for unused bits) DOUT Figure 38. Shift Register Configuration and Changes for Test 5 Figure 39 takes Test 0 as an example and shows a single access cycle. As shown in the figure, a TLD input from DIN, following the input of the data 000 (bin) to select Test 0, causes the contents of the control registers to be copied to the shift register. Subsequent 48-bit CLK inputs enables the user to read data sequentially from DOUT. The values read in Test 3 are cleared once PWR_ON is pulled high. Data should, therefore, be read while PWR_ON is low after protection activates. 45 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 LD 0 DIN 0 0 K[0] K[1] K[2] K[44] K[45] K[46] K[47] CLK (high) TEST ts3 tw1 td7 TLD ts4 X[47] DOUT Y[0] Y[1] Y[2] A[0] A[1] A[2] A[44] 0 (A[45]) 0 (A[46]) 0 (A[47]) T000 D[47] Y[47] 0 0 0 0 (A[47]) K[0] K[1] K[43] K[44] K[45] K[46] K[47] D[46] Y[46] Y[47] 0 0 0 (A[46]) 0 (A[47]) K[0] K[42] K[43] K[44] K[45] K[46] D[45] Y[45] Y[46] Y[47] 0 0 (A[45]) 0 (A[46]) 0 (A[47]) K[41] D[2] Y[2] Y[3] Y[4] Y[5] A[2] A[3] A[4] 0 (A[46]) 0 (A[47]) D[1] Y[1] Y[2] Y[3] Y[4] A[1] A[2] A[3] 0 (A[45]) 0 (A[46]) 0 (A[47]) D[0] Y[0] Y[1] Y[2] Y[3] A[0] A[1] A[2] A[44] K[42] K[43] K[44] K[45] K[0] K[1] K[2] K[0] K[1] 0 (A[45]) 0 (A[46]) 0 (A[47]) K[0] Figure 39. Serial Interface Timing Chart in Test Mode: Information Read EEPROM Data Input Mode: In test mode, Tests 1 and 4 have a common function: internally latch the data to be written to an EEPROM in the TPS65520 temporarily. Since their operations are similar, this section describes them together. Figure 40 and Figure 41 show the shift register configuration from input DIN and output DOUT. DIN 47 0 44 43 0 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 08 07 04 03 0 1 DOUT TRIM_DTCF1 TRIM_DTCF0 TRIM_DTCR1 TRIM_DTCR0 TRIM_DTC0 Figure 40. Shift Register Configuration for Test 1 47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 08 07 04 03 0 DIN 1 0 0 TRIM_BG(5bit) TRIM_OSC(3bit) TRIM_GAIN0(2bit) TRIM_VOFF0(2bit) TRIM_ICHG(1bit) Figure 41. Shift Register Configuration for Test 4 46 DOUT TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 Figure 42 takes test 1 as an example and shows a single access cycle. As shown in the figure, a TLD input from DIN, following the input of the data to be written to the EEPROM and then 001 (bin) to select Test 1, causes the TPS65520 to internally latch the data to be written temporarily. If data is latched at least once by TLD, any internal blocks that reference values from EEPROM will see the latched data, instead of the data stored in EEPROM, until TEST is driven low. LD DIN bitX bit0 bit1 bit2 bit14 1 0 0 bitY CLK TEST (high) TLD T001 WD1[14:0] X[14:0] WD_A[14:0] EUSR[14:0] X[14:0] WD_A[14:0] Figure 42. Serial Interface Timing Chart in Test Mode: EEPROM Data Input EEPROM Data Write Mode: In test mode, tests 6 and 7 have a common function: write data to an EEPROM in the TPS65520. Since their operations are similar, this section describes them together. Figure 43 takes test 6 as an example and shows a single access cycle. As shown in the figure, the EEPROM write voltage, ROMWR, is applied after the data 110 (bin) is input from DIN to select Test 6. A TLD input following the rise of ROMSW triggers a write to the EEPROM. The duration of the write depends on the TLD pulse width. Once the write is finished, stop applying ROMWR. For Test 7, write protection is applied to the write timing signal generated using TLD. 47 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 LD DIN bitX 0 1 1 bitY CLK (high) TEST tw2 TLD T110 ROMWR ts5 WD1[14:0] th3 WD_A[14:0] ED1[14:0] X'[14:0] WD_A[14:0] Figure 43. Serial Interface Timing Chart in Test Mode: EEPROM Data Write Table 9. EVM-XX LIST OF MATERIALS NAME VALUE DEVICE TYPE EXAMPLE PART NAME PM71 (CH-7 PMOS) PMOS SANYO MCH3306/CPH5802 PM72 (CH-7 Load SW) PMOS SANYO MCH3306/CPH5802 NM71 (CH-7 NMOS) NMOS SANYO MCH3406/MCH5801 D4 (CH-4) SBD SANYO SBS004M D5 (CH-5) SBD SANYO SBS004M D6 (CH-6) SBD SANYO SBS004M LED6 (CH-6) White LED NICHIA NSCW100-T38,NSCW100-T39 ROSC 150 k Resistor RSNS6 22 k Resistor CERR1 0.01 F Ceramic capacitor TDK C0603[B, 6.3V], Murata GRP03[0603, B, 6.3] CERR2 0.01 F Ceramic capacitor TDK C0603[B, 6.3V], Murata GRP03[0603, B, 6.3] CERR3 0.022 F Ceramic capacitor TDK C1005[B, 25V], Murata GRP15[1005, B, 16V] CERR4 0.01 F Ceramic capacitor TDK C0603[B, 6.3V], Murata GRP03[0603, B, 6.3] CERR5 0.022 F Ceramic capacitor TDK C1005[B, 25V], Murata GRP15[1005, B, 16V] CERR6 1 F Ceramic capacitor TDK C1005[B, 25V], Murata GRP15[1005, B, 16V] CERR7 0.1 F Ceramic capacitor TDK C1005[B, 25V], Murata GRP15[1005, B, 16V] CERR8 0.01 F Ceramic capacitor TDK C1005[B, 25V], Murata GRP15[1005, B, 16V] 48 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 Table 9. EVM-XX LIST OF MATERIALS (continued) NAME VALUE DEVICE TYPE EXAMPLE PART NAME CCH1 22 F Ceramic capacitor TDK C3225[B, 6.3V] CCH2 10 F Ceramic capacitor TDK C2012[B, 6.3V] CCH3 22 F Ceramic capacitor TDK C3225[22 F, B, 6.3V] CCH4 10 F Ceramic capacitor TDK C3225[10 F, B, 25V] CCH5 10 F Ceramic capacitor (unknown)[10 F, B, 10V] CCH6 10 F Ceramic capacitor TDK C3225[10 F, B, 25V] CCH7 22 F Ceramic capacitor TDK C3225[22 F, B, 6.3V] CCH8 10 F Ceramic capacitor TDK C2012[B, 6.3V] CLDO1 4.7 F Ceramic capacitor TDK C2012[B, 6.3V], Murata GRM21[2012, B, 6.3V] CLDO2 22 F Tantalium capacitor CLDO3 4.7 F Ceramic capacitor TDK C2012[B, 6.3V], Murata GRM21[2012, B, 6.3V] CLDO4 10 F Ceramic capacitor TDK C2012[B, 6.3V] CLDO5 22 F SS_SYNC Ceramic capacitor SS2 Ceramic capacitor SS3 Ceramic capacitor SS5 Ceramic capacitor SS6 Ceramic capacitor SSLDO5 Ceramic capacitor BOOT11 0.01 F Ceramic capacitor TDK C1005[B, 25V], Murata GRP15[1005, B, 16V] BOOT12 0.01 F Ceramic capacitor TDK C1005[B, 25V], Murata GRP15[1005, B, 16V] BOOT2 0.01 F Ceramic capacitor TDK C1005[B, 25V], Murata GRP15[1005, B, 16V] CSCP Ceramic capacitor CBG 1 F Ceramic capacitor TDK C0603[B, 6.3V], Murata GRP03[0603, B, 6.3] CREF 0.1 F Ceramic capacitor TDK C0603[B, 6.3V], Murata GRP03[0603, B, 6.3] L1 10 H TDK RLF5018 L2 10 H TDK RLF5018 L3 10 H Sumida CDRH6D28 L4 4.7 H TDK RLF5018 L5 33 H DK RLF5018 L6 4.7 H TDK RLF5018 L7 10 H Sumida CDRH6D28 L8 L8 10 H TDK RLF5018 49 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 TYPICAL CHARACTERISTICS CH-1 Efficiency vs Load Current CH-1 Efficiency vs Input Voltage (Load Current: 200 mA) 100 100 90 95 80 90 85 60 Efficiency [%] Efficiency [%] 70 50 40 30 10 0 0 0.1 0.2 75 70 VIN=1.8[V](UP) VIN=2.4[V](UP) VIN=3.6[V](CROSS) VIN=4.2[V](DOWN) 20 80 VCH1=2.5[V] VCH1=2.8[V] VCH1=3.2[V] 65 0.3 0.4 0.5 60 0.6 1 2 3 Load Current [A] Figure 44. 6 CH-3 Efficiency vs Load Current 100 90 90 80 80 70 70 Efficiency [%] Efficiency [%] CH-2 Efficiency vs Load Current 60 50 40 60 50 40 30 30 50 5 Figure 45. 100 20 VIN=1.6[V] 20 10 VIN=2.4[V] VIN=3.6[V] VIN=4.2[V] 10 0 4 Input Voltage [V] 0 0.1 VIN=1.8[V] VIN=2.4[V] VIN=3.6[V] VIN=4.2[V] 0 0.2 0.3 0.4 0.5 0.6 0 0.1 0.2 0.3 Load Current [A] Load Current [A] Figure 46. Figure 47. 0.4 0.5 0.6 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 TYPICAL CHARACTERISTICS (continued) CH-5 Efficiency vs Load Current (Input: VCH3) 100 90 90 80 80 70 70 Efficiency [%] Efficiency [%] CH-4 Efficiency vs Load Current 100 60 50 40 50 40 30 30 VIN=1.6[V] VIN=2.4[V] VIN=3.6[V] VIN=4.2[V] 20 10 0 60 0 0.02 20 VIN=4.4[V] VIN=4.9[V] VIN=5.2[V] 10 0.04 0.06 0.08 0.1 0 0 0.12 Load Current [A] 0.02 0.04 0.06 0.08 0.1 0.12 Load Current [A] Figure 48. Figure 49. CH-6 Efficiency vs REF6 (Output: 8 mA, LED2 on) 100 90 90 80 80 70 70 60 60 Efficiency [%] Efficiency [%] CH-5 Efficiency vs Load Current (Input: UNREG) 100 50 40 30 50 40 30 20 VIN=1.6[V] 10 VIN=2.4[V] VIN=3.6[V] VIN=4.2[V] 0 0 0.02 VIN=1.6[V] 20 VIN=2.4[V] VIN=3.0[V] VIN=4.2[V] 10 0.04 0.06 0.08 0.1 0.12 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Load Current [A] REF6 [V] Figure 50. Figure 51. 51 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 TYPICAL CHARACTERISTICS (continued) CH-6 Efficiency vs REF6 (Output: 12 mA, LED2 on) 100 90 90 80 80 70 70 60 60 Efficiency [%] Efficiency [%] CH-6 Efficiency vs REF6 (Output: 8 mA, LED4/5 on) 100 50 40 40 30 30 20 10 0 50 0 0.2 0.4 VIN=1.6[V](LEDx4) 20 VIN=2.4[V](LEDx4) VIN=3.0[V](LEDx5) VIN=4.2[V](LEDx5) 10 0.6 0.8 VIN=1.6[V] VIN=2.4[V] VIN=3.0[V] VIN=4.2[V] 0 1 1.2 1.4 0 0.2 0.4 0.6 Figure 52. CH-6 Efficiency vs REF6 (Output: 12 mA, LED4/5 on) 1.4 CH-6 Efficiency vs REF6 (Output: 20 mA, LED2 on) 90 90 80 80 70 70 Efficiency [%] 100 60 50 40 30 60 50 40 30 VIN=1.6[V](LEDx4) 20 VIN=2.4[V](LEDx4) VIN=3.0[V](LEDx5) 10 20 VIN=1.6[V] 10 VIN=2.4[V] VIN=3.0[V] VIN=4.2[V] VIN=4.2[V](LEDx5) 52 1.2 Figure 53. 100 0 1 REF6 [V] REF6 [V] Efficiency [%] 0.8 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0 0.2 0.4 0.6 0.8 REF6 [V] REF6 [V] Figure 54. Figure 55. 1 1.2 1.4 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 TYPICAL CHARACTERISTICS (continued) CH-7 Efficiency vs Load Current (MODE7 = H) 100 100 90 90 80 80 70 70 Efficiency [%] Efficiency [%] CH-6 Efficiency vs REF6 (Output: 20 mA, LED4/5 on) 60 50 40 60 50 40 30 30 20 10 VIN=1.6[V](LEDx4) 20 VIN=2.4[V](LEDx4) VIN=3.0[V](LEDx5) 10 0.2 0.4 0.6 0.8 VIN=2.4[V] VIN=3.6[V] VIN=4.2[V] VIN=4.2[V](LEDx5) 0 0 0 VIN=1.8[V] 1 1.2 0 1.4 0.1 0.2 0.4 0.5 Figure 56. Figure 57. CH-7 Efficiency vs Load Current (Input: VCH3, MODE7 = L) CH-7 Efficiency vs Load Current (Input: UNREG, MODE7 = L) 100 0.6 100 90 90 80 80 70 70 Efficiency [%] Efficiency [%] 0.3 Load Current [A] REF6 [V] 60 50 40 60 50 40 30 30 20 20 VIN=4.4[V] VIN=4.9[V] VIN=5.2[V] 10 0 0 0 0.02 0.04 VIN=3.6[V] VIN=4.2[V] 10 0.06 0.08 0.1 0.12 Load Current [A] Figure 58. 0.14 0.16 0.18 0.2 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 Load Current [A] Figure 59. 53 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 TYPICAL CHARACTERISTICS (continued) CH-8 Efficiency vs Load Current (Skip Mode) 100 90 90 80 80 70 70 Efficiency [%] Efficiency [%] CH-8 Efficiency vs Load Current (PWM Mode) 100 60 50 40 50 40 30 30 20 10 0 60 0 VIN=1.8[V] 20 VIN=1.6[V] VIN=2.4[V] VIN=3.6[V] VIN=4.2[V] 10 VIN=2.4[V] VIN=3.6[V] 0.05 VIN=4.2[V] 0 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0 0.02 0.04 0.06 Load Current [A] 0.08 0.1 0.12 0.14 0.16 Load Current [A] Figure 60. Figure 61. CH-1 Output Voltage vs Load Current (2% Axis) CH-2 Output Voltage vs Load Current (2% Axis) 2.86 1.22 2.84 1.21 VCH2 [V] VCH1 [V] 2.82 2.8 2.78 1.2 1.19 VIN=1.6[V] VIN=1.8[V](UP) 2.76 VIN=2.4[V](UP) VIN=3.6[V](CROSS) VIN=2.4[V] VIN=3.6[V] VIN=4.2[V] 1.18 VIN=4.2[V](DOWN) 2.74 0 0.1 0.2 0.3 Load Current [A] Figure 62. 54 0.4 0.5 0.6 0 0.1 0.2 0.3 Load Current [A] Figure 63. 0.4 0.5 0.6 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 TYPICAL CHARACTERISTICS (continued) CH-3 Output Voltage vs Load Current (2% Axis) CH-4 Output Voltage vs Load Current (2% Axis) 5 15.3 15.2 4.95 VCH4 [V] VCH3 [V] 15.1 4.9 15 14.9 4.85 VIN=1.6[V] VIN=1.8[V] 14.8 VIN=2.4[V] VIN=3.6[V] VIN=4.2[V] 14.7 4.8 0 0.1 VIN=2.4[V] VIN=3.6[V] VIN=4.2[V] 0.2 0.3 0.4 0.5 0 0.6 0.02 0.04 0.08 0.1 Figure 64. Figure 65. CH-5 Output Voltage vs Load Current (Input: VCH3, 2% Axis) CH-5 Output Voltage vs Load Current (Input: UNREG, 2% Axis) -7.35 -7.35 -7.4 -7.4 -7.45 -7.45 VCH5 [V] VCH5 [V] 0.06 0.12 Load Current [A] Load Current [A] -7.5 -7.5 -7.55 -7.55 VIN=1.6[V] -7.6 -7.6 VIN=4.4[V] VIN=4.9[V] VIN=5.2[V] -7.65 0 0.02 VIN=2.4[V] VIN=3.6[V] VIN=4.2[V] -7.65 0.04 0.06 Load Current [A] Figure 66. 0.08 0.1 0.12 0 0.02 0.04 0.06 0.08 0.1 0.12 Load Current [A] Figure 67. 55 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 TYPICAL CHARACTERISTICS (continued) CH-6 Output Current vs REF6 (Input: 3.0 V, LED5 on) CH-7 Output Voltage vs Load Current (MODE7 = H, 2% Axis) 0.04 3.16 IOUT=8[mA] IOUT=12[mA] 0.035 3.14 IOUT=20[mA] 3.12 0.025 VCH7 [V] Output Current [A] 0.03 0.02 0.015 3.1 3.08 0.01 3.06 VIN=4.4[V] VIN=4.9[V] VIN=5.2[V] 0.005 3.04 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 REF6 [V] Load Current [A] Figure 68. Figure 69. CH-7 Output Voltage vs Load Current (Input: VCH3, MODE7 = L, 2% CH-7 Output Voltage vs Load Current (Input: UNREG, MODE7 = L, 2% Axis) 5 0.18 0.2 0.18 0.2 3.16 3.14 4.95 VCH7 [V] VCH7 [V] 3.12 4.9 3.1 3.08 4.85 VIN=1.8[V] VIN=2.4[V] VIN=3.6[V] VIN=4.2[V] 4.8 3.06 VIN=3.6[V] VIN=4.2[V] 3.04 0 0.1 0.2 0.3 Load Current [A] Figure 70. 56 0.4 0.5 0.6 0 0.02 0.04 0.06 0.08 0.1 0.12 Load Current [A] Figure 71. 0.14 0.16 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 TYPICAL CHARACTERISTICS (continued) CH-8 Output Voltage vs Load Current (PWM Mode, 2% Axis) CH-8 Output Voltage vs Load Current (PWM Mode, 3.5 to 4.3 V Axis) 4.3 VIN=1.8[V] VIN=2.4[V] VIN=3.6[V] VIN=4.2[V] 3.66 4.2 3.64 4.1 VCH8 [V] VCH8 [V] 3.62 3.6 4 3.9 3.8 3.58 3.7 3.56 VIN=1.8[V] VIN=2.4[V] 3.54 3.6 VIN=3.6[V] 0 0.05 0.1 3.5 0.15 0.2 0.25 0.3 0.35 0.4 0 0.45 0.05 0.1 0.15 0.2 0.25 0.3 0.35 Load Current [A] Load Current [A] Figure 72. Figure 73. CH-8 Output Voltage vs Load Current (Skip Mode, 5% Axis) CH-1 Peak Current Waveform (Step-up, Input: 1.8 V, Output: 400 mA) 0.4 0.45 1.00 3.75 IL1 [A] 0.95 3.7 0.90 0.85 0.80 0.75 0.70 0.5 [us/div] 3.6 4.0 3.55 3.0 V OUT12[V] VCH8 [V] 3.65 VIN=1.6[V] VIN=2.4[V] VIN=3.6[V] VIN=4.2[V] 3.5 3.45 0 0.02 0.04 2.0 1.0 0.0 0.06 0.08 0.1 Load Current [A] Figure 74. 0.12 0.14 0.16 -1.0 0.5 [us/div] Figure 75. 57 TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 TYPICAL CHARACTERISTICS (continued) CH-3 Peak Current Waveform (Input: 1.8 V, Output: 400 mA) 0.60 1.70 0.55 1.60 I L3 [A] IL2 [A] CH-2 Peak Current Waveform (Input: 1.8 V, Output: 500 mA) 0.50 1.40 0.45 0.40 1.30 0.5 [us/div] 0.5 [us/div] 3.0 V OUT3 [V] VOUT2[V] 2.0 1.0 0.0 -1.0 0.5 [us/div] 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 -1.0 0.5 [us/div] Figure 76. Figure 77. CH-4 Peak Current Waveform (Input: 1.8 V, Output: 50 mA) CH-5 Peak Current Waveform (Input: VCH3, Output: 50 mA) 1.40 0.30 1.30 0.25 1.20 0.20 I L5 [A] I L4 [A] -2.0 1.50 1.10 1.00 0.90 0.15 0.10 0.05 0.80 0.00 58 18.0 16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 0.5 [us/div] V OUT5 [V] V OUT4 [V] 0.5 [us/div] 6.0 4.0 2.0 0.0 -2.0 -4.0 -6.0 -8.0 -10.0 0.5 [us/div] 0.5 [us/div] Figure 78. Figure 79. TPS65520 www.ti.com SLVS557A - MARCH 2005 - REVISED JUNE 2005 TYPICAL CHARACTERISTICS (continued) CH-6 Peak Current Waveform (Input: 1.8 V, Output: 20 mA) CH-7 Peak Current Waveform (MODE7 = H, Input: 1.8 V, Output: 500 mA) 0.60 3.80 0.50 3.60 I L7 [A] I L6 [A] 0.40 0.30 0.20 3.40 3.20 0.10 3.00 0.00 -0.10 2.80 0.5 [us/div] V OUT7 [V] V OUT6 [V] 0.5 [us/div] 18.0 16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 -2.0 0.5 [us/div] 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 -1.0 0.5 [us/div] Figure 80. Figure 81. CH-7 Peak Current Waveform (MODE7 = L, Input: VCH3, Output: 150 mA) CH-8 Peak Current Waveform (Input: 1.8 V, Output: 200 mA) 0.04 0.03 I L8 [A] I L7 [A] 0.03 0.02 0.01 0.01 0.01 0.00 0.70 0.65 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.5 [us/div] 6.0 5.0 V OUT8 [V] V OUT7 [V] 0.5 [us/div] 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 -1.0 4.0 3.0 2.0 1.0 0.0 -1.0 0.5 [us/div] 0.5 [us/div] Figure 82. Figure 83. 59 PACKAGE OPTION ADDENDUM www.ti.com 17-Aug-2012 PACKAGING INFORMATION Orderable Device TPS65520ZVDR Status (1) ACTIVE Package Type Package Drawing NFBGA ZVD Pins Package Qty Eco Plan 113 TBD (2) Lead/ Ball Finish Call TI MSL Peak Temp (3) Samples (Requires Login) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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