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FEATURES APPLICATIONS
DESCRIPTION
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
POWER MANAGEMENT IC FOR DIGITAL STILL CAMERA
•Digital Still Cameras•Highly Efficient, 8-Channel PowerManagement IC•Fully Integrated Power MOSFETs(Except CH-7)
The TPS65520 is a highly efficient, 8-channel powermanagement IC for digital still cameras (DSCs) inte-•Minimal External Components
grating power MOSFETs. The device operates from•Input Voltage Range: 1.5 to 5 V
an input voltage range of 1.5 V to 5 V.•Short-Circuit Protection (SCP)
The optimized circuit configuration maintains stable(Except for CH-6 and CH-8)
regulation characteristics while minimizing the num-•Overvoltage Protection (OVP)
ber of external components required for phase com-(CH-2, CH-3, CH-6, and CH-7)
pensation and other purposes.•Overcurrent Protection (OCP) (CH-6)
The TPS65520 controls each output channel by•Thermal Shutdown (TSD)
communicating with the Sub-CPU through a serialinterface.•High-Accuracy Output Voltage with Trimming•8 mm x 8 mm BGA Package
CIRCUIT OUTPUT ADJUSTABLE POWERNAME
(1)
RECTIFICATION PURPOSECONFIGURATION VOLTAGE [V] PARAMETER MOSFET
CH-1 H-bridge step-up/down 2.65 ~ 3.2 Output voltage Built-in Synchronous CPU, DSP I/FCH-2 Step-down 1.1 ~ 1.8 Output voltage Built-in Synchronous CPU, DSP coreOutput voltage,CH-3 Step-up 4.5 ~ 5.2 Built-in Synchronous Motor, audioduty cycle
Asynchronous, withOutput voltage,CH-4 Step-up 15.0 ~ 16,5 Built-in external rectification LCD, CCDduty cycle
diode
Asynchronous, withOutput voltage,CH-5 Inversion –9.0 ~ –7.5 Built-in external rectification LCD, CCDduty cycle
diode
Asynchronous, withStep-up with constant Output voltage,CH-6 5.6 ~ 21.0 Built-in external rectification Back light LEDcurrent control duty cycle
diodeStep-down 2.5 ~ 3.2
Output voltage,CH-7 External Synchronous Reserved/switchableduty cycleStep-up 4.4 ~ 5.1Step-up/pass-through
CH-8 3.6 ~ VCC Built-in Synchronous IC internal power supplywith skipLDO-1 2.9 Sub-CPU I/FLDO-2 2.9 Sub-CPU coreLDO-3 3.1 Charge backup batteryLDO-4 3.1 USBLDO-5 8.5 ~ 13.5 Output voltage LCD
(1) CH-N represents switching regulators. LDO-N represents series regulators.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.TMS320 is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATINGS
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
ROMWR –0.3 V to 24 VMODE7, DIN, CLK, LD, PWR_ON, LDO4_ON,
–0.3 V to 7 VTEST, TLDV
I
Input voltage range
(2)
VCH2, VCH7, VCC8 –0.3 V to 6.5 VVCC1, VCC2, VCC5, VCC7, VCC_GD –0.3 V to 6 VVCH5 –10.0 V to 0.3 VVCH4, OUT4, VLDO5, VCH6, ICH6, OUT6 –0.3 V to 24 VBOOT11, BOOT12, BOOT2 –0.3 V to 11 VVOS71, DOUT, XRESET, READY –0.3 V to 7 VV
O
Output voltage range
(2)
ROSC –0.3 V to 6.5 VOUT5 –10.0 V to 5.1 VOUT3 –0.3 V to 6 V
(3)
Others –0.3 V to 6 VVCC1 = OUT11, GND1 = OUT11,OUT12 = VCH1, OUT12 = GND1, –4.5 A to 4.5 AOUT3 = VCH3, OUT3 = GND3Peak current of Power Path OUT8 = VCH8, OUT8 = GND8 –3.0 A to 3 AVCC2 = OUT2, GND2 = OUT2, OUT4 = VCH4,OUT4 = GND4, VCC5 = OUT5, OUT6 = VCH6, –1.5 A to 1.5 AOUT6 = GND6Voltage difference between two of any GND pins (name starts with GND) –0.5 V to 0.5 VESD rating, HBM (Human Body Model) JEDEC JESD22-A114 1.5 kVESD rating, CDM (Charged Device Model) JEDEC JESD22-C101 500 VP
D
Continuous total power dissipation See Dissipation Rating TableT
J
Operating virtual junction temperature range –20°C to 150°CT
A
Operating ambient temperature range –20°C to 85°CT
stg
Storage temperature range –65°C to 150°C
(1) Stresses beyond those listed under ”absolute maximum ratings” may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under ”recommended operatingconditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltagevalues are with respect to network ground terminal.(2) All voltage values are with respect to network ground terminal.(3) For the pulse smaller than 5 ns, Maximum rating is 8.6 V.
POWER RATING DERATING FACTOR POWER RATINGPACKAGE
(1)
T
A
< 25°C ABOVE T
A
= 25°C T
A
= 70°C
nFBGA 113
(2)
2.99 W 23.9 mW/°C 1.95 W
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIWeb site at www.ti.com .(2) This data is based on using still air JEDEC environment with 2S2P JEDEC board.
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RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC_GD 4.5 5.5V
CC
(1)
Supply voltage VVCC1, VCC2, VCC5, VCC7, VCC8 1.5 5.5TLD,VCH2,VCH7 0 5.5MODE7, DIN, CLK, LD, PWR_ON, LDO4_ON,
0 3.3TESTV
I
Input voltage VVCH5 –9.5 0.0ROMWR 0 0.3V
IH1
(2)
High-level input voltage ILDO1 = 0 mA 2.4 2.9 VV
IL1
(2)
Low-level logic input voltage ILDO1 = 0 mA 0 0.5 V100V
IH2
TLD high-level logic input voltage 80%
%Ratio to VCC1A voltageV
IL2
TLD low- level logic input voltage 0% 20%Voltage difference between two of any GND pins (name starts with GND) –0.3 0.3 VT
A
Operating free-air temperature, –20 85 °CAcceptable number of EEPROM writing
(3)
20 Times
(1) These values are defined in stable state. During the start-up, supply voltage sources are OK to be lower than these values.(2) Logic input pins are PWR_ON, USB ON, DIN, CLK, LD, TEST, and MODE7, except TLD.(3) This defines the number of customer’s writing after TI’s shipment.
T
A
= 25°C, VCC1 = 3.6 V, VCC2 = 3.6 V, VCC5 = 4.9 V, VCC7 = 4.9 V, VCC8 = 3.6 V, VCH8 = 3.6 V, VCH3 = 4.9 V,VCH_GD = 4.9 V, LDO4_ON = L, and all register bits are default value (unless otherwise noted) .
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
ICC1
ICC CTRL Supply current for controller 2.2 mAPWR_ON = H, No load current at all outputs (seeTable 1 )IVCC GD Supply current for gate-drive 5 mA
ICC2A
IVCH8 Supply current for LDO, control 40 µAPWR_ON = L (see Table 2 )IVCC8 Supply current for CH-8 1 µA
SUB-CPU CONTROL
VRDY1 READY threshold, rising edge 3.322 3.4 3.478Sweep VCH8 VVRDY2 READY threshold, falling edge 3.234 3.3 3.366
VRST1 XRESET threshold, rising edge 2.115 2.184 2.253Sweep VLDO2 VVRST2 XRESET threshold, falling edge 1.844 1.884 1.924
IREADY Sink current of READY VREADY = 0.5 V 250 500 µA
I
lkg
Leakage current of READY VREADY = 5.25 V, VCH8 = 5.25 V 0.1 µA
IRST Sink current of XRESET VXRESET = 0.5 V, VLDO2 = 2 V 150 300 µA
IRSTL Leakage current of XRESET VXRESET = 5.25 V, VCH8 = 5.25 V 0.1 µA
REFERENCE AND PROTECTION
V
REF
BG reference voltage, sensed at CBG I
REF
= 0 mA 0.842 0.85 0.858 V
Load regulation of BG reference voltage∆VloBG I
REF
= 0.1 µA ~ 1 mA –5 5 mVbuffer
fosc Oscillator frequency ROSC = 150 k Ω475 500 525 kHz
Temperature threshold to shutdown
(1)
140 155 170 °C
(1) Not production tested. Assured by design.
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TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
ELECTRICAL CHARACTERISTICS (continued)T
A
= 25°C, VCC1 = 3.6 V, VCC2 = 3.6 V, VCC5 = 4.9 V, VCC7 = 4.9 V, VCC8 = 3.6 V, VCH8 = 3.6 V, VCH3 = 4.9 V,VCH_GD = 4.9 V, LDO4_ON = L, and all register bits are default value (unless otherwise noted) .
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SOFT-START
Source current of SS_SYNC VSS_SYNC = 0.5 V 0.7 1 1.3 µA
Source current of SS2 VSS2 = 0.5 V 0.7 1 1.3 µA
Source current of SS3 VSS3 = 0.5 V 0.7 1 1.3 µAI
SS
Source current of SS5 VSS5 = 0.5 V 0.7 1 1.3 µA
Source current of SS6 VSS6 = 0.5 V 0.7 1 1.3 µA
Source current of SSLDO5 VSSLDO5 = 0.5 V 0.35 0.65 µA
VSS3OK SS3OK threshold voltage 1.2 1.6 2 V
LOGIC INPUT/OUTPUT
V
OH
(2)
High-level logic output voltage 2.5ILDO1 = 0 mA, IDOUT = –0.5 mA VV
OL
(2)
Low-level logic output voltage 0.4
START-UP CIRCUIT
VWU Wake-up voltage Monitoring VCC8 1.6 V
CH-1
Vout1 = 0000(bin), T
A
= –10 ~ 65°C 2.744 2.8 2.856 V
Vout1 = 0001(bin), T
A
= –10 ~ 65°C 2.695 2.75 2.805 V
Vout1 = 0010(bin), T
A
= –10 ~ 65°C 2.646 2.7 2.754 V
Vout1 = 0001(bin), T
A
= –10 ~ 65°C 2.597 2.65 2.703 V
Vout1 = 0100(bin), T
A
= –10 ~ 65°C 2.548 2.6 2.652 V
Vout1 = 0101(bin), T
A
= –10 ~ 65°C 2.499 2.55 2.601 V
Vout1 = 0110(bin), T
A
= –10 ~ 65°C 2.450 2.5 2.550 V
Vout1 = 0111(bin), T
A
= –10 ~ 65°C 3.138 3.2 3.264 VVCH1 Error amp center voltage
Vout1 = 1000(bin), T
A
= –10 ~ 65°C 3.087 3.15 3.213 V
Vout1 = 1001(bin), T
A
= –10 ~ 65°C 3.038 3.1 3.162 V
Vout1 = 1010(bin), T
A
= –10 ~ 65°C 2.989 3.05 3.111 V
Vout1 = 1011(bin), T
A
= –10 ~ 65°C 2.940 3 3.060 V
Vout1 = 1100(bin), T
A
= –10 ~ 65°C 2.891 2.95 3.009 V
Vout1 = 1101(bin), T
A
= –10 ~ 65°C 2.842 2.9 2.958 V
Vout1 = 1110(bin), T
A
= –10 ~ 65°C 2.793 2.85 2.907 V
Vout1 = 1111(bin), T
A
= –10 ~ 65°C 2.769 2.825 2.88 V
gm1 gm value of error amp 0.8 1 1.2 mS
VOCH1
(3)
Output voltage On EVM, T
A
= –10 ~ 65°C 2.744 2.8 2.856 V
∆Vli11
(3)
Line regulation (CROSS state) On EVM –28 28 mV
∆Vli12
(3)
Line regulation (DOWN state) On EVM –28 28 mV
∆Vlo11
(3)
Load regulation (CROSS state) On EVM –28 28 mV
∆Vlo12
(3)
Load regulation (DOWN state) On EVM –28 28 mV
IOUT1
(3)
Minimum Load current On EVM, VCC1=1.8 V 400 mA
VSCP1 SCP detector threshold Ratio to VCH1 75% 80% 85%
Vmod11 Mode selector threshold, rising edge Ratio to VCH1 130% 135% 137%
Vmod12 Mode selector threshold, falling edge Ratio to VCH1 120% 125% 127%
(2) Logic output pin is DOUT.(3) Not production tested. Assured by design. Using reference EVM.
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TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
ELECTRICAL CHARACTERISTICS (continued)T
A
= 25°C, VCC1 = 3.6 V, VCC2 = 3.6 V, VCC5 = 4.9 V, VCC7 = 4.9 V, VCC8 = 3.6 V, VCH8 = 3.6 V, VCH3 = 4.9 V,VCH_GD = 4.9 V, LDO4_ON = L, and all register bits are default value (unless otherwise noted) .
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CH-2
Vout2 = 0000(bin), T
A
= –10 ~ 65°C 1.176 1.2 1.224 V
Vout2 = 0001(bin), T
A
= –10 ~ 65°C 1.127 1.15 1.173 V
Vout2 = 0010(bin), T
A
= –10 ~ 65°C 1.078 1.1 1.122 V
Vout2 = 0011(bin), T
A
= –10 ~ 65°C 1.764 1.8 1.836 V
Vout2 = 0100(bin), T
A
= –10 ~ 65°C 1.715 1.75 1.785 V
Vout2 = 0101(bin), T
A
= –10 ~ 65°C 1.666 1.7 1.734 V
Vout2 = 0110(bin), T
A
= –10 ~ 65°C 1.617 1.65 1.683 V
Vout2 = 0111(bin), T
A
= –10 ~ 65°C 1.568 1.6 1.632 VVCH2 Error amp center voltage
Vout2 = 1000(bin), T
A
= –10 ~ 65°C 1.519 1.55 1.581 V
Vout2 = 0001(bin), T
A
= –10 ~ 65°C 1.470 1.5 1.530 V
Vout2 = 1010(bin), T
A
= –10 ~ 65°C 1.421 1.45 1.479 V
Vout2 = 1011(bin), T
A
= –10 ~ 65°C 1.372 1.4 1.428 V
Vout2 = 1100(bin), T
A
= –10 ~ 65°C 1.323 1.35 1.377 V
Vout2 = 1101(bin), T
A
= –10 ~ 65°C 1.274 1.3 1.326 V
Vout2 = 1110(bin), T
A
= –10 ~ 65°C 1.225 1.25 1.275 V
Vout2 = 1111(bin), T
A
= –10 ~ 65°C 1.201 1.225 1.250 V
gm2 gm value of error amp 0.8 1 1.2 mS
VoCH2
(3)
Output voltage On EVM, T
A
= –10 ~ 65°C 1.176 1.2 1.224 V
∆Vli12
(3)
Line regulation On EVM –12 12 mV
∆Vlo2
(3)
Load regulation On EVM –12 12 mV
IOUT2
(3)
Minimum load current On EVM, VCC2=4.2 V 500 mA
VSCP2 SCP detector threshold Ratio to VCH2 75% 80% 85%
VOVP2 OVP detector threshold Ratio to VCH2 115% 120% 125%
CH-3
Vout1 = 0000(bin), T
A
= –10 ~ 65°C 4.802 4.9 4.998 V
Vout1 = 0001(bin), T
A
= –10 ~ 65°C 4.753 4.85 4.947 V
Vout1 = 0010(bin), T
A
= –10 ~ 65°C 4.704 4.8 4.896 V
Vout1 = 0001(bin), T
A
= –10 ~ 65°C 4.655 4.75 4.845 V
Vout1 = 0100(bin), T
A
= –10 ~ 65°C 4.606 4.7 4.794 V
Vout1 = 0101(bin), T
A
= –10 ~ 65°C 4.557 4.65 4.743 V
Vout1 = 0110(bin), T
A
= –10 ~ 65°C 4.508 4.6 4.692 V
Vout1 = 0111(bin), T
A
= –10 ~ 65°C 4.459 4.55 4.641 VVCH3 Error amp center voltage
Vout1 = 1000(bin), T
A
= –10 ~ 65°C 4.410 4.5 4.590 V
Vout1 = 1001(bin), T
A
= –10 ~ 65°C 5.096 5.2 5.304 V
Vout1 = 1010(bin), T
A
= –10 ~ 65°C 5.047 5.15 5.253 V
Vout1 = 1011(bin), T
A
= –10 ~ 65°C 4.998 5.10 5.202 V
Vout1 = 1100(bin), T
A
= –10 ~ 65°C 4.949 5.05 5.151 V
Vout1 = 1101(bin), T
A
= –10 ~ 65°C 4.900 5 5.100 V
Vout1 = 1110(bin), T
A
= –10 ~ 65°C 4.851 4.95 5.049 V
Vout1 = 1111(bin), T
A
= –10 ~ 65°C 4.802 4.9 4.998 V
gm3 gm value of error amp 0.8 1 1.2 mS
VoCH3
(4)
Output voltage On EVM, T
A
= –10 ~ 65°C 4.802 4.90 4.998 V
∆Vli3
(4)
Line regulation On EVM –49 49 mV
∆Vlo3
(4)
Load regulation On EVM –49 49 mV
IOUT3
(4)
Minimum Load current On EVM, [CH-3 input voltage]=1.8 V 500 mA
VSCP3 SCP detector threshold Ratio to VCH3 75% 80% 85%
VOVP3 OVP detector threshold Ratio to VCH3 5.99 V
(4) Not production tested. Assured by design. Using reference EVM.
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TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
ELECTRICAL CHARACTERISTICS (continued)T
A
= 25°C, VCC1 = 3.6 V, VCC2 = 3.6 V, VCC5 = 4.9 V, VCC7 = 4.9 V, VCC8 = 3.6 V, VCH8 = 3.6 V, VCH3 = 4.9 V,VCH_GD = 4.9 V, LDO4_ON = L, and all register bits are default value (unless otherwise noted) .
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CH-4
Vout4 = 00(bin), T
A
= –10 ~ 65°C 14.700 15 15.300 V
Vout4 = 01(bin), T
A
= –10 ~ 65°C 15.190 15.5 15.810 VVCH4 Error amp center voltage
Vout4 = 10(bin), T
A
= –10 ~ 65°C 15.680 16 16.320 V
Vout4 = 11(bin), T
A
= –10 ~ 65°C 16.170 16.5 16.830 V
gm4 gm value of error amp 0.8 1 1.2 mS
VoCH4
(4)
Output voltage On EVM, T
A
= –10 ~ 65°C 14.700 15.0 15.300 V
∆Vli4
(4)
Line regulation On EVM –150 150 mV
∆Vlo4
(4)
Load regulation On EVM –150 150 mV
IOUT4
(4)
Minimum Load current On EVM, [CH-4 input voltage] = 1.8 V 50 mA
VSCP4 SCP detector threshold Ratio to VCH4 75% 80% 85%
CH-5
Vout5=00(bin), T
A
= –10 ~ 65°C –7.650 –7.5 –7.350 V
Vout5=01(bin), T
A
= –10 ~ 65°C –8.160 –8.0 –7.840 VVCH5 Error amp center voltage
Vout5=10(bin), T
A
= –10 ~ 65°C –8..670 –8.5 –8.330 V
Vout5=11(bin), T
A
= –10 ~ 65°C –9.180 –9.0 –8.820 V
gm5 gm value of error amp 0.8 1.0 1.2 mS
VoCH5
(5)
Output voltage On EVM, T
A
= –10 ~ 65°C –7.650 –7.5 –7.350 V
∆Vli5
(5)
Line regulation On EVM –75 75 mV
∆Vlo5
(5)
Load regulation On EVM –75 75 mV
IOUT5
(5)
Minimum Load current On EVM,VCC5 = 4.9 V 50 mA
VSCP5 SCP detector threshold 75% 80% 85%
CH-6
Vout5 = 00(bin), T
A
= –10 ~ 65°C 0.2482 0.264 0.2798 V
VFB6 Error amp center voltage Vout5 = 01(bin), T
A
= –10 ~ 65°C 0.4136 0.440 0.4664 V
Vout5 = 10(bin), T
A
= –10 ~ 65°C 0.1654 0.176 0.1866 V
gm6 gm value of error amp 0.8 1 1.2 mS
ICH6
(5)
Output voltage On EVM, T
A
= –10 ~ 65°C 11.28 12 12.72 mA
∆Vli6
(5)
Line regulation of VFB6 On EVM –120 120 µA
VOCP OCP detector threshold Monitor at FB6 0.80 0.85 0.90 V
VOVP6 OVP detector threshold 21.0 22 23.0 V
VREF6L CH-6 disable threshold, low side 0.16 0.21 0.26 V
VREF6H CH-6 disable threshold, high side VCH1 = 2.8 V 1.7 2 2.3 V
VfDI6 Forward voltage of integrated diode I(OUT6 = VCH6) = 20 mA 0.9 V
(5) Not production tested. Assured by design. Using reference EVM.
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TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
ELECTRICAL CHARACTERISTICS (continued)T
A
= 25°C, VCC1 = 3.6 V, VCC2 = 3.6 V, VCC5 = 4.9 V, VCC7 = 4.9 V, VCC8 = 3.6 V, VCH8 = 3.6 V, VCH3 = 4.9 V,VCH_GD = 4.9 V, LDO4_ON = L, and all register bits are default value (unless otherwise noted) .
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CH-7
Vout7 = 0000(bin), T
A
= –10 ~ 65°C, MODE7 = H 4.802 4.9 4.998 V
Vout7 = 0001(bin), T
A
= –10 ~ 65°C, MODE7 = H 4.753 4.85 4.947 V
Vout7 = 0010(bin), T
A
= –10 ~ 65°C, MODE7 = H 4.704 4.8 4.896 V
Vout7 = 0001(bin), T
A
= –10 ~ 65°C, MODE7 = H 4.655 4.75 4.845 V
Vout7 = 0100(bin), T
A
= –10 ~ 65°C, MODE7 = H 4.606 4.7 4.794 V
Vout7 = 0101(bin), T
A
= –10 ~ 65°C, MODE7 = H 4.557 4.65 4.743 V
Vout7 = 0110(bin), T
A
= –10 ~ 65°C, MODE7 = H 4.508 4.60 4.692 V
Vout7 = 0111(bin), T
A
= –10 ~ 65°C, MODE7 = H 4.459 4.55 4.641 VVCH7U Error amp center voltage
Vout7 = 1000(bin), T
A
= –10 ~ 65°C, MODE7 = H 4.41 4.50 4.590 V
Vout7 = 1001(bin), T
A
= –10 ~ 65°C, MODE7 = H 4.361 4.45 4.539 V
Vout7 = 1010(bin), T
A
= –10 ~ 65°C, MODE7 = H 4.312 4.40 4.488 V
Vout7 = 1011(bin), T
A
= –10 ~ 65°C, MODE7 = H 4.998 5.10 5.202 V
Vout7 = 1100(bin), T
A
= –10 ~ 65°C, MODE7 = H 4.949 5.05 5.151 V
Vout7 = 1101(bin), T
A
= –10 ~ 65°C, MODE7 = H 4.9 5 5.1 V
Vout7 = 1110(bin), T
A
= –10 ~ 65°C, MODE7 = H 4.851 4.95 5.049 V
Vout7 = 1111(bin), T
A
= –10 ~ 65°C, MODE7 = L 4.802 4.90 4.998 V
Vout7 = 0000(bin), T
A
= –10 ~ 65°C, MODE7 = L 3.038 3.1 3.162 V
Vout7 = 0001(bin), T
A
= –10 ~ 65°C, MODE7 = L 2.989 3.05 3.111 V
Vout7 = 0010(bin), T
A
= –10 ~ 65°C, MODE7 = L 2.940 3.00 3.060 V
Vout7 = 0001(bin), T
A
= –10 ~ 65°C, MODE7 = L 2.891 2.95 3.009 V
Vout7 = 0100(bin), T
A
= –10 ~ 65°C, MODE7 = L 2.842 2.9 2.958 V
Vout7 = 0101(bin), T
A
= –10 ~ 65°C, MODE7 = L 2.793 2.85 2.907 V
Vout7 = 0110(bin), T
A
= –10 ~ 65°C, MODE7 = L 2.744 2.8 2.856 V
Vout7 = 0111(bin), T
A
= –10 ~ 65°C, MODE7 = L 2.695 2.75 2.805 VVCH7D Error amp center voltage
Vout7 = 1000(bin), T
A
= –10 ~ 65°C, MODE7 = L 2.646 2.7 2.754 V
Vout7 = 1001(bin), T
A
= –10 ~ 65°C, MODE7 = L 2.597 2.65 2.703 V
Vout7 = 1010(bin), T
A
= –10 ~ 65°C, MODE7 = L 2.548 2.6 2.652 V
Vout7 = 1011(bin), T
A
= –10 ~ 65°C, MODE7 = L 2.499 2.55 2.601 V
Vout7 = 1100(bin), T
A
= –10 ~ 65°C, MODE7 = L 2.450 2.5 2.550 V
Vout7 = 1101(bin), T
A
= –10 ~ 65°C, MODE7 = L 3.138 3.2 3.264 V
Vout7 = 1110(bin), T
A
= –10 ~ 65°C, MODE7 = L 3.087 3.15 3.213 V
Vout7 = 1111(bin), T
A
= –10 ~ 65°C, MODE7 = L 3.038 3.1 3.162 V
gm7 gm value of error amp 0.8 1 1.2 mS
VoC71
(6)
Output voltage Mode7 = H, On EVM, T
A
= –10 ~ 65°C 4.802 4.9 4.998 V
∆Vli71
(6)
Line regulation Mode7 = H, On EVM –49 49 mV
∆Vlo71
(6)
Load regulation Mode7 = H, On EVM –49 49 mV
IOUT71
(6)
Minimum Load current Mode7 = H, On EVM, VCC7=1.8 V 500 mA
VOCH72
(6)
Output voltage Mode7 = L, On EVM, T
A
= –10 ~ 65°C 3.038 3.1 3.162 V
∆Vli72
(6)
Line regulation Mode7 = L, On EVM –31 31 mV
∆Vlo72
(6)
Load regulation Mode7 = L, On EVM –31 31 mV
IOUT72
(6)
Minimum load current Mode7 = L, On EVM, [CH-7 input voltage] = 4.9 V 150 mA
VSCP7 SCP detector threshold Ratio to VCH7 75% 80% 85%
VOVP7 OVP detector threshold Ratio to VCH7 5.99 V
IOS71H Source current of OS71 VOS71 = 0 V, VCH3 = VCH7 = 4.9 V –6 mA
IOS71L Sink current of OS71 VOS71 = 4.9 V, VCH3 = VCH7 = 4.9 V 0.2 µA
IOS72H Source current of OS72 VOS72 = 4.4 V, VCH3 = VCH7 = 4.9 V –100 mA
IOS72L Sink current of OS72 VOS72 = 0.5 V, VCH3 = VCH7 = 4.9 V 100 mA
(6) Not production tested. Assured by design. Using reference EVM.
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TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
ELECTRICAL CHARACTERISTICS (continued)T
A
= 25°C, VCC1 = 3.6 V, VCC2 = 3.6 V, VCC5 = 4.9 V, VCC7 = 4.9 V, VCC8 = 3.6 V, VCH8 = 3.6 V, VCH3 = 4.9 V,VCH_GD = 4.9 V, LDO4_ON = L, and all register bits are default value (unless otherwise noted) .
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOS73H Source current of OS73 VOS73 = 0.0 V, VCH3 = VCH7 = 4.9 V –100 mA
IOS73L Sink current of OS73 VOS73 = 0.5 V, VCH3 = VCH7 = 4.9 V 100 mA
NMOS (OS71, GND GD), VOS71 = 0.1 V, VCH3 =ROS71n ON resistance 7.5 k ΩVCH7 = 4.9 V
NMOS(OS72, GND GD), VOS72 = 0.1 V, VCH3 =ROS72n ON resistance 5 ΩVCH7 = 4.9 V
NMOS(OS73, GND GD), VOS73 = 0.1 V, VCH3 =ROS73n ON resistance 5 ΩVCH7 = 4.9 V
PMOS(VCH7, OS71), VOS71 = 4.8 V, VCH3 = VCH7 =ROS71p ON resistance 360 Ω4.9 V
PMOS(VCC7, OS72), VOS72 = 4.8 V, VCH3 = VCH7 =ROS72p ON resistance 5 Ω4.9 V
PMOS(VCC GD, OS73), VOS73 = 4.8 V, VCH3 =ROS73p ON resistance 15 ΩVCH7 = 4.9 V
CH-8
VCH81 Error amp center voltage (normal) 3.528 3.6 3.672 VPWR_ON = H, T
A
= –10 ~ 65°CVCH82 Error detector center voltage (skip) 3.492 3.6 3.708 V
gm8 gm value of error amp 0.8 1 1.2 mS
VoCH81
(7)
Output voltage (skip) 3.492 3.6 3.708 VOn EVM, T
A
= –10 ~ 65°C, VCC8 = 1.5 ~ 3.6 VVoCH82
(7)
Output voltage (normal) 3.528 3.6 3.672 V
∆Vli81
(7)
Line regulation (skip) On EVM, VCC8 = 1.8 ~ 3.6 V (= VoCH81)
(8)
–108 180 mV
∆Vli82
(7)
Line regulation (normal) On EVM, VCC8 = 1.8 ~ 3.6 V –36 36 mV
∆Vlo81
(7)
Load regulation (skip) On EVM, VCC8 = 1.8 ~ 3.6 V, ICH8 < x[mA] –120 120 mV
∆Vlo82
(7)
Load regulation (normal) On EVM, VCC8 = 1.8 ~ 3.6 V –36 36 mV
IOUT81
(7)
Minimum Load current (skip) On EVM, VCC8 = 1.8 V 120 mA
IOUT82
(7)
Minimum Load current (normal) On EVM, VCC8 = 1.8 V 170 mA
(7) Not production tested. Assured by design. Using reference EVM.(8) This parameter ∆Vli81 is covered by VoCH81 and adjusted to VoCH81.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LDO-1
VLDO1 Output voltage VCH8 = 3.6 ~ 5.25 V, ILDO1 = 5 mA 2.842 2.9 2.958 V∆VliL1 Line regulation VCH8 = 3.6 ~ 5.25 V, ILDO1 = 5 mA 30 mV∆VloL1 Load regulation VCH8 = 3.6 V, ILOD1 = 0.1 ~ 30 mA 100 mVOutput current limit VCH8 = 3.6 ~ 5.25 V 36 mA
LDO-2
VLDO2 Output voltage VCH8 = 3.6 ~ 5.25 V, ILDO2 =6 mA 2.842 2.9 2.958 V∆VliL2 Line regulation VCH8 = 3.6 ~ 5.25 V, ILDO2 = 6 mA 30 mV∆VloL2 Load regulation VCH8 = 3.6 V, ILOD2 = 0.1 ~ 50 mA 100 mVOutput current limit VCH8 = 3.6 ~ 5.25 V 60 mA
LDO-3
VLDO3 Output voltage VCH8 = 3.6 ~ 5.25 V, ILDO3 = 10 mA 3.038 3.1 3.162 V∆VliL3 Line regulation VCH8 = 3.6 ~ 5.25 V, ILDO3 = 10 mA 30 mV∆VloL3 Load regulation VCH8 = 3.6 V, ILOD3 = 0.1 ~ 20 mA 100 mVOutput current limit VCH8 = 3.6 ~ 5.25 V 24 mA
LDO-4
VLDO4 Output voltage VCH8 = 3.6 ~ 5.25 V, ILDO4 = 5 mA 3.078 3.142 3.202 V∆VliL4 Line regulation VCH8 = 3.6 ~ 5.25 V, ILDO4 = 5 mA 30 mV∆VloL4 Load regulation VCH8 = 3.6 V, ILOD1 = 0.5 ~ 100 mA 100 mVOutput current limit VCH8 = 3.6 ~ 5.25 V 120 mA
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EQUIVALENT INPUT/OUTPUT CIRCUIT DIAGRAMS
INPUT
VCC1A
GND_REG
470 k
INPUT CIRCUIT
INPUT
VLDO1
GND_REG
470 k
INPUT CIRCUIT
MODE7
VLDO1
GND_REG
INPUT CIRCUIT
INPUT
VLDO1
GND_REG
470 k
INPUT CIRCUIT
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LDO-5
LDO5Vo = 00 (bin), T
A
= –10 ~ 65°C,
13.23 13.5 13.778ILDO5 = 15 mALDO5Vo = 01 (bin), T
A
= –10 ~ 65°C,
12.25 12.5 12.75ILDO5 = 15 mAVLDO5 Output voltage VLDO5Vo = 10 (bin), T
A
= –10 ~ 65°C,
11.76 12 12.24ILDO5 = 15 mALDO5Vo = 11 (bin), T
A
= –10 ~ 65°C,
8.33 8.5 8.67ILDO5 = 15 mA∆VliL5 Line regulation VCH4 = 15 ~ 16.5 V, ILDO5 = 5 mA 50 mV∆VloL5 Load regulation VCH4 = 15 V, ILOD5 = 0.1 ~ 15 mA 50 mVOutput current limit VCH4 = 15 ~ 16.5 V 36 mA
Figure 1. PWR_ON, LDO4_ON, DIN, TEST Figure 2. TLD
Figure 3. LD Figure 4. MODE7
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CLK
VLDO1
GND_REG
470 k
INPUT CIRCUIT
DOUT
VLDO1
GND_REG
OUTPUT CIRCUIT
OPEN DRAIN
GND_REG
OUTPUT CIRCUIT
ICC1
ICC1 4.9
4.2 1
CH3IVCC_GD ICC_CTRL
4.9 IVCC_GD
4.2 (ICC1 ICC_CTRL) CH3
(1)
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
EQUIVALENT INPUT/OUTPUT CIRCUIT DIAGRAMS (continued)
Figure 5. CLK Figure 6. DOUT
Figure 7. READY, XRESET
ICC1 represents the supply current measured when all channels are operating normally with no load. It is difficultto connect coils and other external devices to the TPS65520. Therefore, to measure characteristics in shippingtests, the desired ICC1 is specified using two testable parameters with the pins handled as shown in Table 1.
ICC_CTRL represents the supply current from the 2.9-V and 4.2-V power supplies shown in the tables. ICC_GDrepresents the supply current from the 4.2-V power supplies shown in the tables. IVCC_GD is a self-consumedgate drive current from CH-3. Therefore, it is associated with the desired ICC1 through the CH-3 efficiency.Equation 1 indicates the relationship between IVCC_GD and the supply current from the power supplies in theapplication circuit (ICC1). ICC1 is specified as the supply current when a voltage of 4.2 V is the input. ICC_CTRLis the current consumed by the TPS65520 (excluding IVCC_GD).
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TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
Table 1. Pin Handling for Measuring ICC1Pin Name Connection NotePin Name Connection Note
CH-2POWER SUPPLY
BOOT2 4.9 V supply gate driverVCC_GD 4.9 V Supply gate drive
VCH2 GND force MAX DUTYGND_GD GND
VCC2 2.9 V bias power MOSGNDANA GND
OUT2 open (not concerned)GNDLOG GND
GND2 GNDGNDREG GND
ERR2 4.2 V force MAX DUTYGNDLDOA GND
CH-3SUB-CPU CONTROL
VCH3A/B/C 4.9 V supply TAKUMIPWR_ON 2.9 V
VCH3S open (not concerned)CSCP GND avoid shutdown
OUT3A/B/C open (not concerned)ROSC 150 k Ωto GND recommended part
GND3A/B/C GNDCREF Cap recommended part
ERR3 4.2 V force MAX DUTYCBG Cap recommended part
CH-4VLDO1 Cap recommended part
VCH4 4.9 V force MAX DUTYVLDO2 Cap recommended part
OUT4 open (not concerned)VLDO3 Cap recommended part
GND4 GNDVLDO4 Cap recommended part
ERR4 open (not concerned)VLDO5 Cap recommended part
CH-5LOGIC
VCH5 GND force MAX DUTYROMWR GND
VCC5 4.9 V supply gate driverTEST open pull down internally
OUT5 open (not concerned)TLD open pull down internally
ERR5 open (not concerned)CLK open pull up internally
CH-6DIN open pull down internally
OUT6 open (not concerned)LD open pull up internally
FB6 GND force MAX DUTYDOUT open (not concerned)
VCH6 open (not concerned)SS, ETC.
ICH6 open (not concerned)READY open (not concerned)
GND6 GNDXRESET open (not concerned)
REF6 CBG biasLDO4_ON 2.9 V force LDO-4 ON
ERR6 open (not concerned)SS_SYNC open (not concerned)
CH-7SS2 open (not concerned)
VCH7 open (not concerned)SS3 open (not concerned)
VCC7 4.9 V supply gate driverSS5 open (not concerned)
ERR7 4.2 V force MAX DUTYSS6 open (not concerned)
MODE7 GND fix logic valueSSLDO5 open (not concerned)
VOS71 open (not concerned)CH-1
VOS72 open (not concerned)BOOT11 4.9 V supply gate driver
VOS73 open (not concerned)BOOT12 4.9 V supply gate driver
CH-8VCH1A/B/C 2.9 V force output
VCH8A/B 4.2 V force through modeVCC1A/B/C 2.9 V supply CH-1
VCC8 4.2 V force through modeGND1A/B/C GND
ERR8 4.2 V force MAX DUTYOUT11A/B/C open (not concerned)
OUT8A/B open (not concerned)OUT12A/B/C open (not concerned)
GND8A/B GNDERR1 4.2 V force MAX DUTY
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ICC2
ICC2 1
CH8:skip IVCH8 IVCC8
(2)
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
ICC2 represents the supply current measured when the system operation is minimized with CH-8 placed in sleepmode. It is difficult to connect coils and other external devices to the TPS65520 to measure its characteristics inshipping tests. Therefore, the desired ICC2 is specified using three testable parameters with the pins handled asshown in Table 2 .
IVCC8 and IVCH8 represent the supply currents from the VCC8 and VCH8 pins, respectively.
Equation 2 indicates the relationship between those currents and the supply current from the power supplies inthe application circuit (ICC2). ICC2 is specified as the supply current when a voltage of 3.6 V is input.
Table 2. Pin Handling for Measuring ICC2Pin Name Connection NotePin Name Connection Note
SSLDO5 open (not concerned)POWER SUPPLY
CH-1VCC_GD open (not concerned)
BOOT11 open (not concerned)GND_GD GND
BOOT12 open (not concerned)GNDANA GND
VCH1A/B/C open (not concerned)GNDLOG GND
VCC1A/B/C open (not concerned)GNDREG GND
GND1A/B/C GNDGNDLDOA GND
OUT11A/B/C open (not concerned)LOGIC
OUT12A/B/C open (not concerned)ROMWR GND
ERR1 open (not concerned)TEST open pull down internally
CH-2TLD open pull down internally
BOOT2 open (not concerned)CLK open pull up internally
VCH2 open (not concerned)DIN open pull down internally
VCC2 open (not concerned)LD open pull up internally
OUT2 open (not concerned)DOUT open (not concerned)
GND2 GNDSUB-CPU CONTROL
ERR2 open (not concerned)PWR_ON GND
CH-3CSCP GND avoid shutdown
VCH3A/B/C open (not concerned)ROSC 150 k Ωto GND recommended part
VCH3S open (not concerned)CREF Cap recommended part
OUT3A/B/C open (not concerned)CBG Cap recommended part
GND3A/B/C GNDVLDO1 Cap recommended part
ERR3 open (not concerned)VLDO2 Cap recommended part
CH-4VLDO3 Cap recommended part
VCH4 open (not concerned)VLDO4 Cap recommended part
OUT4 open (not concerned)VLDO5 Cap recommended part
GND4 GNDSS, ETC.
ERR4 open (not concerned)READY open (not concerned)
CH-5XRESET open (not concerned)
VCH5 open (not concerned)LDO4_ON GND
VCC5 open (not concerned)SS_SYNC open (not concerned)
OUT5 open (not concerned)SS2 open (not concerned)
ERR5 open (not concerned)SS3 open (not concerned)
CH-6SS5 open (not concerned)
OUT6 open (not concerned)SS6 open (not concerned)
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Time
1.6[V]
PWR_ON
SS3
td1
VCH3S
VCH3
47[k ]
4.9[V]
Time
90[%]
LD
VCH3S
0.01 [F] td2
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
Pin Name Connection Note Pin Name Connection Note
FB6 GND MODE7 GND fix logic valueVCH6 open (not concerned) VOS71 open (not concerned)ICH6 open (not concerned) VOS72 open (not concerned)GND6 GND VOS73 open (not concerned)REF6 open (not concerned) CH-8
ERR6 open (not concerned) VCH8A/B 3.7 V stop skip switching
CH-7 VCC8 3.6 V supply to CH-8 circuitVCH7 open (not concerned) ERR8 open (not concerned)VCC7 open (not concerned) OUT8A/B open (not concerned)ERR7 open (not concerned) GND8A/B GND
A. t
d1
(Measure SS3 when it is left open.)Figure 8. t
d1
Measurement Reference
Figure 9. t
d2
Measuring Circuit and Measurement Reference
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Time
50[%]
LD
VOS71 50[%]
~
~
~
~
~
~
td3f
td3fr
Time
90[%]
LD
VLDO3
td4
Time
90[%]
LDO4_ON
VLDO4
td5
DOUT
20[pF]
Time
50[%]
CLK
DOUT
50[%]
~
~
50[%]
50[%]
DOUT
or
td7
td6
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
A. t
d3r
, t
d3f
(Measure VOS71 when it is left open.)
Figure 10. t
d3r
and t
d3f
Measurement References
A. t
d4
(Connect a capacitor, 4.7 µF A. t
d5
(Connect a capacitor, 4.7 µFrecommended, to VLDO3.) recommended, to VLDO4.)Figure 11. t
d4
Measurement Reference Figure 12. t
d5
Measurement Reference
Figure 13. t
d6
and t
d7
Measuring Circuit and Measurement References
14
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XRESET
10[k ]
Time
50[%]
VLDO2
XRESET
VRST1
td8
TIMING REQUIREMENTS
SWITCHING CHARACTERISTICS
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
Figure 14. t
d8
Measuring Circuit and Measurement Reference
T
A
= 25°C, VCC1 = 3.6 V, VCC2 = 3.6 V, VCC5 = 3.6 V, VCC7 = 3.6 V, VCC8 = 3.6 V, VCH8 = 3.6 V, VCH3 = 4.9 V,VCH_GD = 4.9 V, LDO4_ON = L, and all register bits are default value (unless otherwise noted)
PARAMETER MIN MAX UNIT
t
s1
Setup time, LD ↓before CLK ↑(see Figure 33 ) 400 nst
s2
Setup time, DIN valid before CLK ↑(see Figure 33 ) 200 nst
s3
Setup time, TLD ↑after CLK ↑(see Figure 39 ) 50 nst
s4
Setup time, TLD ↑before CLK ↑(see Figure 39 ) 50 nst
s5
Setup time, ROMWR ↑before TLD ↑(see Figure 43 ) 10 µst
h1
Hold time, DIN valid after CLK ↑(see Figure 33 ) 50 nst
h2
Hold time, LD ↑after last CLK ↑(see Figure 33 ) 50 nst
h3
Hold time, ROMWR ↓after last TLD ↓(see Figure 33 ) 10 µst
w1
Pulse width of TLD = H for Test0 ~ Test5 (see Figure 39 ) 50 nst
w2
Pulse width of TLD = H for Test6,Test7 (see Figure 43 ) 20 mst
w3
Pulse width of CLK = H (see Figure 33 ) 100 nst
cyc
Period of CLK ↑(see Figure 33 ) 500 ns
PARAMETER MIN TYP MAX UNIT
t
d1
Delay time, PWR_ON ↑to start of charging SS3 (see Figure 8 and Figure 30 ) 1.1 1.15 mst
d2
Delay time, LD ↑to VCH3S ↑(see Figure 9 and Figure 30 ) 500 750 µst
d3r
Delay time, LD ↑to VOS71 ↑, VCH7 = 4.9 V (see Figure 10 and Figure 30 ) 500 1000 nst
d3f
Delay time, LD ↑to VOS71 ↓, VCH7 = 4.9 V (see Figure 10 and Figure 30 ) 60 100 µs
td4
Delay time, LD ↑to VLDO3 ↑(see Figure 11 and Figure 30 ) 300 650 µst
d5
Delay time, LDO4_ON ↑to VLDO4 ↑(see Figure 12 and Figure 30 ) 300 650 µst
d6
Delay time, last CLK ↑to DOUT valid for Normal Mode (see Figure 13 ,Figure 33 , and Figure 39 ) 100 200 nsDelay time, CLK ↓to DOUT valid for Test0, Test2, Test3, Test5 (see Figure 13 ,Figure 33 , andt
d7
100 200 nsFigure 39 )t
d8
Delay time, VLDO2 exceeds VRST1 to XRESET ↑(see Figure 14 ) 200 300 600 µs
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ABCDEFGHJKL
BOOT11
VCC1A
VCC1B
VCC1C
OUT11A
OUT11B
OUT11C
BOOT12
VCH1A
VCH1B VCH1C
OUT12A
OUT12B
OUT12CGND1A
GND1B
GND1C
ERR1
SS_SYNC
VCH2
BOOT2
VCC2
OUT2
GND2
ERR2
VCH3S
VCH3A
VCH3B
VCH3C OUT3A
OUT3B
OUT3C GND3AGND3B
GND3C
ERR3SS3
VCH4 OUT4 GND4
ERR4
VLDO5
VCH5 VCC5 OUT5
ERR5 SS5
VCH6
ICH6
FB6
OUT6
GND6
ERR6
SS6
REF6
VOS71 VCH7
VCC7 VOS72
VOS73
ERR7
MODE7
VCH8A
VCH8B
OUT8A OUT8B
GND8A
GND8B
ERR8
VCC8
NC
GND
CSCP
ROSC
NC
NC
GND
NC
GND
NC
DINCLK
LD
ROMWR
DOUTLDO4_ON
VLDO4
XRESET
VLDO3
NC
VLDO2
VLDO1
READY
TEST
TLD
CBG
VCC_GD
GND_GD
GND_REG
CREF
GND_ANA
GND_LOG
1
2
3
4
5
6
7
8
9
10
11
SS2
PWR_ON
SSLDO5NC
GND_LDOA
Power Line
Logic Line
Analog Line
Analog Line(CAP)
GND Line
Voltage Output
MOS Gate DriveERR8
GND6 FB6
ROMWR TEST
NC
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
PIN LAYOUT
(TOP VIEW)
Figure 15. Pin Layout
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TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
TERMINAL FUNCTIONS
TERMINAL
NAME I/O DESCRIPTIONPINNO.
ADDRESS
1 1-A ERR6 O Output of gm amp for CH-62 1-B REF6 IO Reference resistor of CH-63 1-C GND_REG G Ground for analog circuit of regulators4 1-D NC No connection (recommended to be GND)5 1-E CSCP IO Current source of short-circuit protection6 1-F OUT6 IO Output side terminal of coil L6 for CH-67 1-G VCH6 O Output voltage of CH-68 1-H VCC_GD V Power supply for gate driver of internal power MOS-FET9 1-J VCH3A O Output of CH-3 (1/3)10 1-K OUT3B IO Output side terminal of coil L3 for CH-3 (2/3)11 1-L GND3C G Ground for CH-3 (3/3)12 2-A SS3 O Current source of soft-start for CH-313 2-B ERR3 O Output of gm amp for CH-314 2-C SS2 I Current source of soft-start for CH-215 2-D NC No connection (recommended to be GND)16 2-E ROSC O Reference resistor for PWM oscillator17 2-F(= 3-F) GND6 G Ground for CH-6(same pin as No.28, 3-F)18 2-G ICH6 IO LEDs cathode of CH-619 2-H VCH3S O Analog switched output of CH-320 2-J OUT3C IO Output side terminal of coil L3 for CH-3 (3/3)21 2-K GND3B G Ground for CH-3 (2/3)22 2-L GND3A G Ground for CH-3 (1/3)n23 3-A VOS71 O Gate drive of external PMOS switch for CH-724 3-B MODE7 I Mode selection of CH-725 3-C SS6 O Current source of soft-start for CH-626 3-D NC No connection (recommended to be GND)27 3-E NC No connection (recommended to be GND)28 3-F(= 2-F) GND6 G Ground for CH-6 (same pin as No.17, 2-F)29 3-G(= 4-G) FB6 IO Current sense input of CH-6 (same pin as No.40, 4-G)30 3-H VCH3C O Output of CH-3 (3/3)31 3-J OUT3A IO Output side terminal of coil L3 for CH-3 (1/3)32 3-K VCH7 O Output of CH-733 3-L VOS73 O Gate drive of low side NMOS switch for CH-734 4-A ERR5 O Output of gm amp for CH-535 4-B SS5 O Current source of soft-start for CH-536 4-C ERR7 O Output of gm amp for CH-737 4-D NC No connection (recommended to be GND)38 4-E NC No connection (recommended to be GND)39 4-F GND_LOG G Ground for general logic circuit40 4-G(= 3-G) FB6 IO Current sense input of CH-6 (same pin as No.29, 3-G)41 4-H VCH3B O Output of CH-3 (2/3)42 4-J VCC7 V Power supply of CH-743 4-K VOS72 O Gate drive of high side PMOS switch for CH-744 4-L GND_GD G Ground for gate driver of internal power MOS-FET45 5-A GND_ANA G Ground for general analog circuit
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TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
TERMINAL FUNCTIONS (continued)
TERMINAL
NAME I/O DESCRIPTIONPINNO.
ADDRESS
46 5-B CBG IO Output of BG reference voltage buffer47 5-C SS_SYNC O Current source of soft-start for CH-1, CH-4 and CH-748 5-D ERR4 O Output of gm amp for CH-449 5-E NC No connection (recommended to be GND)50 5-H(= 7-J) TEST I Test mode selection Input of serial I/F (same pin as No.67, 7-J)51 5-J VCH5 O Output of CH-552 5-K VCC5 V Power supply of CH-553 5-L OUT5 IO Primary side terminal of coil L5 for CH-554 6-A ERR1 O Output of gm amp for CH-155 6-B ERR2 O Output of gm amp for CH-256 6-C(= 6-D) ERR8 O Output of gm amp for CH-8 (same pin as No.57, 6-D)57 6-D(= 6-C) ERR8 O Output of gm amp for CH-8 (same pin as No.56, 6-C)58 6-H TLD I Test mode latch input of serial I/F59 6-J VCH4 O Output of CH-460 6-K OUT4 IO Output side terminal of coil L4 for CH-461 6-L GND4 G Ground for CH-462 7-A READY O READY output for Sub-CPU63 7-B XRESET O Low Active RESET output for Sub-CPU64 7-C PWR_ON I TPS65520 device enable input65 7-D LDO4_ON I Enable of LDO-466 7-H(= 8-J) ROMWR I Voltage bias to write EEPROM (same pin as No.78, 8-J)67 7-J(= 5-H) TEST I Test mode selection input of serial I/F (same pin as No.50, 5-H)68 7-K LD I Latch input of serial I/F69 7-L DOUT O Data output of serial I/F70 8-A CREF IO Capacitor of RC filter for band-gap reference71 8-B VLDO5 O Output of LDO-572 8-C VLDO4 O Output of LDO-473 8-D NC No connection (recommended to be GND)74 8-E NC No connection (recommended to be GND)75 8-F SSLDO5 O Current source of soft-start for LDO-576 8-G BOOT11 IO Bootstrap for primary side of CH-177 8-H BOOT12 IO Bootstrap for output side of CH-178 8-J(= 7-H) ROMWR I Voltage bias to write EEPROM (same pin as No.66, 7-H)79 8-K CLK I Clock input of serial I/F80 8-L DIN I Data input of serial I/F81 9-A GND_LDOA G Ground for analog circuit of LDO-1,LDO-2,LDO-382 9-B VLDO2 O Output of LDO-283 9-C NC No connection (recommended to be GND)84 9-D OUT8A IO Output side terminal of coil L8 for CH-8 (½)85 9-E OUT8B IO Output side terminal of coil L8 for CH-8 (2/2)86 9-F VCC2 V Power supply of CH-287 9-G VCC1C V Power supply of CH-1 (3/3)88 9-H GND1A G Ground for CH-1 (1/3)89 9-J OUT12C IO Output side terminal of coil L1 for CH-1 (3/3)90 9-K VCH1B O Output of CH-1 (2/3)
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TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
TERMINAL FUNCTIONS (continued)
TERMINAL
NAME I/O DESCRIPTIONPINNO.
ADDRESS
91 9-L VCH1C O Output of CH-1 (3/3)92 10-A VLDO3 O Output of LDO-393 10-B NC No connection (recommended to be GND)94 10-C VCH8A O Output of CH-8 (½)95 10-D GND8A G Ground for CH-8 (½)96 10-E BOOT2 IO Bootstrap for CH-297 10-F OUT2 IO Primary side terminal of coil L2 for CH-298 10-G VCC1B V Power supply of CH-1 (2/3)99 10-H OUT11B IO Primary side terminal of coil L1 for CH-1 (2/3)100 10-J GND1B G Ground for CH-1 (2/3)101 10-K OUT12B IO Output side terminal of coil L1 for CH-1 (2/3)102 10-L VCH1A O Output of CH-1 (1/3)103 11-A VLDO1 O Output of LDO-1104 11-B VCC8 V Power supply of CH-8105 11-C VCH8B O Output of CH-8 (2/2)106 11-D GND8B G Ground for CH-8 (2/2)107 11-E VCH2 O Output of CH-2108 11-F GND2 G Ground for CH-2109 11-G VCC1A V Power supply of CH-1 (1/3)110 11-H OUT11A IO Primary side terminal of coil L1 for CH-1 (1/3)111 11-J OUT11C IO Primary side terminal of coil L1 for CH-1 (3/3)112 11-K GND1C G Ground for CH-1 (3/3)113 11-L OUT12A IO Output side terminal of coil L1 for CH-1 (1/3)
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REGISTER MAP
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
Some switching regulators allow the output voltage to be changed according to control register settings.However, changing the voltage setting while a regulator is operating may cause the output to overshoot andexceed the rating. Be careful when dynamically changing the regulator output voltage.
LIST OF REGISTERS
NAME POSITION DESCRIPTION
parity D[47] - D[40] parity dataCH7-SW D[38] VOS71, load side switch of CH-7Dmax7 D[37] - D[36] duty setting of CH-7Dmax5 D[35] - D[34] duty setting of CH-5Dmax4 D[33] - D[32] duty setting of CH-4CH3-SW D[31] - D[30] Load side switch of CH-3Dmax3 D[29] - D[28] duty setting of CH-3, CH-1(UP,CROSS) and CH-8Vout7 D[27] - D[24] Voltage setting of CH-7Vout5 D[23] - D[22] Voltage setting of CH-5Vout4 D[21] - D[20] Voltage setting of CH-4Vout3 D[19] - D[16] Voltage setting of CH-3Vout2 D[15] - D[12] Voltage setting of CH-2Vout1 D[11] - D[08] Voltage setting of CH-1LDO5Vo D[07] - D[06] Voltage setting of LDO-5LDOSW5 D[05] LDO-5 ON/OFF switchLDOSW3 D[04] LDO-3 ON/OFF switchDmax6 D[03] - D[02] duty setting of CH-6Vout6B D[01] - D[00] Back-light LED current of CH-6
CH7-SW
D[39] D[38] D[37] D[36] ON/OFF
* 0 * * OFF default* 1 * * ON
Dmax7
DUTY [%]D[39] D[38] D[37] D[36]
MIN TYP MAX
* * 0 0 82 86 91 default* * 0 1 77 81 86* * 1 0 72 76 81* * 1 1 67 71 76
Dmax5
DUTY [%]D[35] D[34] D[33] D[32]
MIN TYP MAX
0 0 * * 84 88 92 default0 1 * * 79 83 871 0 * * 74 78 821 1 * * 69 73 77
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TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
Dmax4
DUTY [%]D[35] D[34] D[33] D[32]
MIN TYP MAX
* * 0 0 92 94 96 default* * 0 1 90 92 94* * 1 0 88 90 92* * 1 1 86 88 90
CH3-SW
D[31] D[30] D[29] D[28] ON/OFF
0 0 * * OFF default0 1 * * OFF1 0 * * OFF1 1 * * ON
Dmax3
DUTY [%]D[31] D[30] D[29] D[28]
MIN TYP MAX
* * 0 0 82 86 91 default* * 0 1 77 81 86* * 1 0 72 76 81 recommend* * 1 1 67 71 76
Vout7
Output Voltage [V]D[27] D[26] D[25] D[24]
DOWN UP
0 0 0 0 3.10 4.90 default0 0 0 1 3.05 4.850 0 1 0 3.00 4.800 0 1 1 2.95 4.750 1 0 0 2.90 4.701 0 1 2.85 4.650 1 1 0 2.80 4.600 1 1 1 2.75 4.551 0 0 0 2.70 4.501 0 0 1 2.65 4.451 0 1 0 2.60 4.401 0 1 1 2.55 5.101 1 0 0 2.50 5.051 1 0 1 3.20 5.001 1 1 0 3.15 4.951 1 1 1 3.10 4.90
Vout5
D[23] D[22] D[21] D[20] Output Voltage [V]
0 0 * * -7.5 default0 1 * * -8.0
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TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
Vout5 (continued)
D[23] D[22] D[21] D[20] Output Voltage [V]
1 0 * * -8.51 1 * * -9.0
Vout4
D[19] D[18] D[17] D[16] Output Voltage [V]
* * 0 0 15.0 default* * 0 1 15.5* * 1 0 16.0* * 1 1 16.5
Vout3
D[19] D[18] D[17] D[16] Output Voltage [V]
0 0 0 0 4.90 default0 0 0 1 4.850 0 1 0 4.800 0 1 1 4.750 1 0 0 4.700 1 0 1 4.650 1 1 0 4.600 1 1 1 4.551 0 0 0 4.501 0 0 1 5.201 0 1 0 5.151 0 1 1 5.101 1 0 0 5.051 1 0 1 5.001 1 1 0 4.951 1 1 1 4.90
Vout2
D[15] D[14] D[13] D[12] Output Voltage [V]
0 0 0 0 1.20 default0 0 0 1 1.150 0 1 0 1.100 0 1 1 1.800 1 0 0 1.750 1 0 1 1.700 1 1 0 1.650 1 1 1 1.601 0 0 0 1.551 0 0 1 1.501 0 1 0 1.451 0 1 1 1.401 1 0 0 1.351 1 0 1 1.301 1 1 0 1.251 1 1 1 1.225
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TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
Vout1
D[11] D[10] D[09] D[08] Output Voltage [V]
0 0 0 0 2.80 default0 0 0 1 2.750 0 1 0 2.700 0 1 1 2.650 1 0 0 2.60 not recommended0 1 0 1 2.55 not recommended0 1 1 0 2.50 not recommended0 1 1 1 3.201 0 0 0 3.151 0 0 1 3.101 0 1 0 3.05 3.051 0 1 1 3.001 1 0 0 2.951 1 0 1 2.901 1 1 0 2.851 1 1 1 2.825
LDO5Vo
D[07] D[06] D[05] D[04] Output Voltage [V]
0 0 * * 13.5 default0 1 * * 12.51 0 * * 12.01 1 * * 8.5
LDOSW5
D[07] D[06] D[05] D[04] ON / OFF
* * 0 * OFF default* * 1 * ON
LDOSW3
D[07] D[06] D[05] D[04] ON / OFF
* * * 0 ON default* * * 1 OFF
Dmax6
DUTY [%]D[03] D[02] D[01] D[00]
MIN TYP MAX
0 0 * * 87 89 91 default0 1 * * 89 91 931 0 * * 91 93 951 1 * * 93 95 97
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EEPROM MAP
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
Vout6B
D[03] D[02] D[01] D[00] Output Current [mA]
* * 0 0 12.0 default* * 0 1 20.0* * 1 0 8.0* * 1 1 OFF
Note: TI is shipping ICs with recommended values.
DEFAULT VALUE SETUP BITS
NAME POSITION DESCRIPTION
Test Mode D[47] - D[45] 001: Test1 (write), 010: Test2 (read)(none) (D[44]) (not used)TRIM_DTC0 D[43] - D[42] Trimming for DTC of Tr/Tf, CH-1,CH-2TRIM_DTCR0 D[41] - D[40] Trimming for DTC of Tr, CH-3,CH-8TRIM_DTCR1 D[39] - D[38] Trimming for DTC of Tr, CH-7TRIM_DTCF0 D[37] - D[36] Trimming for DTC of Tf, CH-3,CH-8TRIM_DTCF1 D[35] - D[34] Trimming for DTC of Tf, CH-7
TRIMMING BITS
NAME POSITION DESCRIPTION
Test Mode D[47] - D[45] 100: Test1(write), 101: Test2 (read)TRIM_BG (5[bit]) Trimming for band-gap reference voltageTRIM_OSC (3[bit]) Trimming for oscillator frequencyTRIM_GAIN0 (2[bit]) Trimming for AMP gain of CH-1TRIM_VOFF0 (2[bit]) Trimming for AMP offset voltage of CH-1
PROTECTION STATUS READ MAP
NAME POSITION DESCRIPTION
Test Mode D[47] - D[45] 011: Test3SCP7 D[12] SCP7 to previous system down(none) (D[11]) (not assigned, always L)SCP5 D[10] SCP5 to previous system downSCP4 D[09] SCP4 to previous system downSCP3 D[08] SCP3 to previous system downSCP2 D[07] SCP2 to previous system downSCP1 D[06] SCP1 to previous system downOVP7 D[05] OVP7 to previous system downOVP6 D[04] OVP6 to previous system downOVP3 D[03] OVP3 to previous system downOVP2 D[02] OVP2 to previous system downTSD D[01] TSD to previous system down
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TPS65520 BLOCK CONFIGURATION
GND_ANA
BOOT11
VCC1A, VCC1B, VCC1C
OUT11A, OUT11B, OUT11C
BOOT12
VCH1A, VCH1B, VCH1C
OUT12A, OUT12B, OUT12C
GND1A, GND1B, GND1C
ERR1
SS_SYNC
VCH2
BOOT2
VCC2
OUT2
GND2
ERR2
VCH3S
VCH3A, VCH3B, VCH3C
OUT3A, OUT3B, OUT3C
GND3A, GND3B, GND3C
ERR3
SS3
VCH4
OUT4
GND4
ERR4
VLDO5
VCH5
VCC5
OUT5
ERR5
SS5
VCH6
ICH6
OUT6
ERR6
SS6
REF6
VOS71
VCH7
VCC7
VOS72
VOS73
ERR7
MODE7
VCH8A, VCH8B
OUT8A, OUT8B
GND8A, GND8B
VCC8
CSCP
ROSC
DIN
CLK
LD
ROMWR
DOUT
LDO4_ON
VLDO4
XRESET
VLDO3
VLDO2
VLDO1
READY
TLD
CBG
VCC_GD
GND_GD
GND_REG
CREF
GND_LOG
SS2
PWR_ON
SSLDO5
GND_LDOA
ERR8
GND6
FB6
TEST
TPS65520
CH-1
CH-2
CH-3
CH-4
CH-5
CH-6CH-7
CH-8
LDO-1
LDO-2
LDO-3
LDO-4
LDO-5
RESET
LOGIG
PROTECTION
SERIAL I/F
EEPROM
REFERENCE
SCP
OVP
BG BUF OSC
To all of CH-x
TSD
OCP
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
Figure 16 shows the overall block configuration of the TPS65520. Note that the figure is simplified for clarity anddoes not show accurate details for the IC wiring, pin layout, and internal component layout.
Figure 16. TPS65520 Block Diagram
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FUNCTIONAL DESCRIPTION
COMMON SWITCHING REGULATOR FUNCTIONS
MAXIMUM DUTY CYCLE CONTROL
DEAD TIME CONTROL
CH-1
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
The following sections describe the common features for all switching regulators.
The maximum duty cycle control is applied to each channel to prevent a 100% on condition.
For CH-3, CH-4, CH-5, CH-6, and CH-7, control registers are provided to adjust the maximum duty cycle settingsthat affects the channel characteristics substantially.
For CH-1 (step-up and step-up/down) and CH-8, which have relatively large margins for maximum duty cyclecontrol, settings are linked to CH-3 to simplify circuits.
Table 3 lists settings for each channel:
Table 3. Settings for Each Channel
CHANNEL CONTROL SETTINGS
CH-1 (step-up, step-up/down) (Dmax3)CH-1 (step-down) Fixed at 95%CH-2 Fixed at 95%CH-3 Dmax3CH-4 Dmax4CH-5 Dmax5CH-6 Dmax6CH-7 Dmax7CH-8 (Dmax3)
The synchronous rectification channels are subjected to dead time control to prevent a flow-through current. Thedead time for each channel is fixed by the EEPROM, as shown in Table 4 :
Table 4.
Channel CH-1 CH-2 CH-3 CH-7 CH-8
Dead time 30[ns] 30[ns] 30[ns] 40[ns] 30[ns]
CH-1 is a step-up/down switching regulator for I/F 3-V power supplies, including those for the main processor,TMS320™ DSP family, and ASIC. Figure 17 shows its block diagram and the connection of external devices.
CH-1 operates by automatically switching between two modes: step-up to step-up/down mode and step-downmode. In Step-up to step-up/down mode, the channel shifts between step-up and step-up/down operations withinthe single mode.
Table 5 shows the rough relationship between the input voltage and CH-1 mode. Note that the threshold valuesshown in the table are merely guidelines because the actual CH-1 circuit finely adjusts the threshold voltages tomaximize efficiency. Electrical Characteristics section for the voltage specifications of thresholds for switchingbetween step-up to step-up/down mode and step-down mode (Vmod11 and Vmod12).
CH-1 incorporates a voltage retention circuit that maintains the boosting power supply voltage when the channelis performing step-up only or step-down only operation.
CH-1 supports the SCP and soft-start functions. The soft-start function is common to CH-1, CH-4, and CH-7.
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+
+
−
0.85[V]
DAC
Vout1
GND_REG GND_REG
VCH3
VCH3
GND_REG
+
+
−
MAX
DUTY
TRIM_DTC0
DTC/MODE
VCC_GD
VCH1
SS_SYNC
OUT12
GND1
ERR1
BOOT12
BOOT12
CERR1
SSSYNC
L1
CCH1
VCC_GD
GND_REG
GND_REG
VCH3
VCH3
SCP
VIN
VCC1
VCC_GD OUT11
BOOT11
BOOT11
+
−
GND_REG
UP−CROSS
CONTROL
CH-2
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
Table 5.
VCC1 [V]
(1)
CH-1 MODE OPERATION
~ 2.3 Step-up to step-up/Down Step-up2.3 ~ 3.78 Step-up to step-up/down Step-up/down3.5 ~ Step-down -
(1) The voltages shown are for guideline purposes only.
Figure 17. CH-1 Block Diagram
CH-2 is a step-down switching regulator for core 1.x-V power supplies, including those for the main processor,TMS360™ DSP family, and ASIC. Figure 18 shows the block diagram and the connection of external devices.
CH-2 supports the OVP, SCP and soft-start functions.
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+
+
−
0.85[V]
DAC
Vout2
GND_REG GND_REG
VCH3 VCH3
GND_REG
+
+
−
MAX
DUTY
TRIM_DTC0
DTC
VCC_GD
VIN
VCH2
SS2
OUT2
GND2
VCC2
ERR2
BOOT2
BOOT2
CERR2SS2
L2
CCH2
VCC_GD
GND_REGGND_REG
VCH3
VCH3
OVP SCP
CH-3
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
Figure 18. CH-2 Block Diagram
CH-3 is a step-up switching regulator for 5-V power supplies, including those for the motor and audio IC.Figure 19 shows its block diagram and the connection of external devices.
CH-3 incorporates a PMOS switch, which prevents the input voltage from appearing on the output side when thechannel is turned off. Without the switch, the parasitic diode in the internal PMOS carries the input voltage fromcoil (L3) and causes a current to flow into the load. This switch turns the VCH3S output pin on or off according tothe settings in the CH3-SW control register.
The motor driver, as a load for CH-3, is a switch itself. It does not have a current path so that it can be connectedto the VCH3 pin. Other current loads, which may have current paths, are intended to be connected to the VCH3Spin.
When CH-3 is activated, CH-8 supplies power to CH-3. To prevent overload on CH-8 during startup, CH-3compares VCH8 and VCH3 and performs asynchronous rectification using a body diode until VCH3 exceedsVCH8.
CH-3 supports the OVP, SCP and soft-start functions.
When using the TPS65520, note the following:•The following conditions must be satisfied to use a 5-V ac adaptor:– An appropriate voltage drop circuit is provided so that the input voltages for step-up CH-3 are at least 0.3 Vlower than the values specified with the control register.
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+
+
−
0.85[V]
DAC
Vout3
GND_REG GND_REG GND_REG
+
+
−
MAX
DUTY
TRIM_DTCR0,
TRIM_DTCF0
DTC
VIN
VCH3
SS3
OUT3
GND3
ERR3
CERR3
SS3
L3
CCH3
VCC_GD
VCH3S
Dmax3
VCH8
Internal Power Supply
VCC_GD
GND_GD
VCC_GD
EN3S
GND_REGGND_REG
OVP SCP
CH-4
+
+
−
0.85[V]
DAC
Vout4
GND_REG GND_REG
VCH3 VCH3
GND_REG
+
+
−
MAX
DUTY
VIN
VCH4
SS_SYNC
OUT4
GND4
ERR4
CERR4
SSSYNC
L4
CCH4
VCC_GD
Dmax4
VCH3
VCH3
GND_REG GND_REG
SCP
D4
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
Figure 19. CH-3 Block Diagram
CH-4 is a step-up switching regulator for 15-V power supplies the LCD and CCD. Figure 20 shows its blockdiagram and the connection of external devices.
CH-4 is controlled by asynchronous rectification because it outputs a high voltage and does not benefit muchfrom synchronous rectification. An external SBD is connected between the OUT4 and VCH4 pins as arectification device for CH-4.
CH-4 supports the SCP and soft-start functions. The soft-start function is common to CH-1, CH-4, and CH-7.
Figure 20. CH-4 Block Diagram
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CH-5
+
−
0.85[V] DAC
Vout5
GND_REG
VCH3VCH3
GND_REG
+
+
−
MAX
DUTY
VCH3
VCH5
SS5
OUT5
ERR5
CERR5 SS5
L5 CCH5
VCC_GD
GND_GD
Dmax5
VCC5
+
VCH3 VCH3
GND_REG GND_REG
SCP
D5
CH-6
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
CH-5 is an inversion switching regulator for -8-V power supplies for the LCD and CCD. Figure 21 shows its blockdiagram and the connection of external devices.
CH-5 supports the SCP and soft-start functions.
Figure 21. CH-5 Block Diagram
CH-6 is a step-up switching regulator for driving the power supply for the LCD backlight LED. CH-6 is controlledby monitoring the current flowing through the LED so that it operates as a constant-current driver. Figure 22shows the block diagram and the connection of external devices.
The output current for CH-6 can be finely adjusted using the REF6 pin. The output current becomes the valuespecified with the Vout6B control register when the potential of the REF6 pin equals that of the CBG pin. Notethat the REF6 pin always expects a voltage to be applied. One example to ensure that an appropriate voltage isapplied to the REF6 pin, is to connect it to a DAC or to the CBG pin through a resistor. The following formulasshow the relationship between the voltage on the REF6 pin and that on the FB6 pin, which senses the outputcurrent:
20 mA setting V
(FB6)
= 0.52 × V
(REF6)
– 0.00212 mA setting V
(FB6)
= 0.52 × V
(REF6)
– 0.1778 mA setting V
(FB6)
= 0.52 × V
(REF6)
– 0.265
For example, when using 0.85 V of CBG as reference voltage and using 22 Ωof recommended sense resistor,the caluculation is like this: I
O
= V
(FB6)
/ R
sense
= (0.52 x 0.85 V - 0.002) / 22 Ω= 20 mA.
CH-6 supports the OVP, SCP and soft-start functions.
Without serial I/F control, CH-6 is controlled by the voltage of REF6. When the potential of REF6 is out of rangebetween VREF6L and VREF6H, CH-6 is OFF in logical. Soft-start is reset.
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CH-7
+
+
−
0.85[V]
DAC
Vout6B
GND_REG
VCH3 VCH3
GND_REG
+
+
−
MAX
DUTY
VIN
VCH6
SS6
OUT6
GND6
ERR6
CERR6
SS6
L6
CCH6
VCC_GD
Dmax6
VCH3VCH3
GND_REG
GND_REG ICH6
VCC_GD
EN6 FB6
OVP
OCP
+
−
REF6
t¡ë
VCH1
VCH1
CBG
DAC
IC
GND_REG
VCH1
LEDx
RSNS6
GND_REG
x2
+
−
x0.26
VCH1
GND_REG D6
For Control Using Thermistor
For Control Using DAC
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
According to the state of the MODE7 pin, CH-7 operates either as a step-up switching regulator for 5-V powersupplies, including those for the motor and audio IC, or as a step-down switching regulator for I/F 3-V powersupplies, including those for the main processor, TMS320™ DSP family, and ASIC. Table 6 shows therelationship between the state and mode:
Table 6.
MODE7 MODE
H Step-upL Step-down
CH-7 requires different external component connections depending on the MODE7 pin state. Figure 23 shows itsblock diagram and the connection of external devices for step-up mode. Figure 24 shows its block diagram andthe connection of external devices for step-down mode.
When using the TPS65520, note the following:•The following conditions must be satisfied to use a 5-V ac adaptor:– An appropriate voltage drop circuit is provided so that the input voltages for step-up CH-7 (MODE7 = H)are at least 0.3 V lower than the values specified with the control register.
Figure 22. CH-6 Block Diagram
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+
+
−
0.85[V]
DAC
Vout7
GND_REG GND_REG GND_REG
+
+
−
MAX
DUTY
TRIM_DTCR1,
TRIM_DTCF1
VIN
VCC7
SS_SYNC ERR7
CERR7SSSYNC
L7
CCH7
VCC_GD
GND_GD
Dmax7
VCH3
GND_GD
EN7S
GND_REGGND_REG
OVP SCP
VCH3
VCH3
VCH3
VOS71
VOS72
VOS73
VCH7
DTC/
MODE
MODE7
VLDO1
PM71
NM71
PM72
+
+
−
0.85[V]
DAC
Vout7
GND_REG GND_REG GND_REG
+
+
−
MAX
DUTY
TRIM_DTCR1,
TRIM_DTCF1
VCH3
VCC7
SS_SYNC ERR7
CERR7SSSYNC
L7
CCH7
VCC_GD
GND_GD
Dmax7
VCH3
GND_GD
EN7S
GND_REGGND_REG
OVP SCP
VCH3
VCH3
VCH3
VOS71
VOS72
VOS73
VCH7
DTC/
MODE
MODE7
PM71
NM71
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
Figure 23. CH-7 Block Diagram (Step-up)
Figure 24. CH-7 Block Diagram (Step-down)
As shown in Figure 24 , the step-down circuit configuration uses CH-3 as an input power supply that ensures avoltage higher than the output voltage.
CH-7 has the VOS71 pin for controlling a separate PMOS switch, preventing the input voltage from appearing onthe output side when the channel is turned off (MODE7 = H). Without the switch, the parasitic diode in theexternal PMOS carries the input voltage from coil (L7) which causes a current to flow into the load. This switchturns on or off according to the settings in the CH7-SW control register.
When CH-7 is activated, CH-8 supplies power to CH-7. To prevent overload on CH-8 during startup, CH-7compares VCH8 and VCH7 and performs asynchronous rectification using a body diode until VCH7 exceedsVCH8.
CH-7 supports the OVP, SCP and soft-start functions. The soft-start function is common to CH-1, CH-4, andCH-7.
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CH-8
+
−
0.85[V]
GND_REG GND_REG GND_REG
+
+
−
MAX
DUTY
TRIM_DTCR0,
TRIM_DTCF0 VIN
VCH8
OUT8
GND8
ERR8
CERR8
L8
CCH8
VCC_GD
GND_REGGND_REG
VCC_GD
DTC/
MODE
+
−
SKIP
GND_REG
READY
WakeUp
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
When CH-7 is not used, handle the pins as shown in Table 7 . CH-7 enters step-down mode with its state equalto the stable output state, stopping operation.
Table 7.
PIN HANDLING
ERR7 0.1 µF - Connect a 0.1-µF capacitor between the pin and groundVCH7 VCH1 - Short-circuit to VCH1VOS71 OpenMODE7 Short-circuit to the groundVCC7 OpenVOS72 OpenVOS73 Open
CH-8 is a step-up switching regulator for LDO-1, LDO-2, LDO-3, LDO-4, and the internal power supplies of theTPS65520. CH-8 is a 3.6-V output regulator that outputs the input voltage (VCC8) when it is higher than 3.6 V.
CH-8 is turned on whenever the battery and/or ac adaptor is connected. It operates in skip mode while thePWR_ON pin is low, meaning that only the Sub-CPU real-time clock is operating. Once the PWR_ON pin isdriven high, CH-8 enters synchronous rectification mode, where it can supply the maximum load current.
CH-8 has a startup circuit that can start with a low input voltage because the startup of CH-8 enables the entireDSC system to start up. It outputs 3.6 V from a minimum input voltage (VCC8) of 1.6 V.
See the CH-8 operating sequence for details of starting CH-8.
Figure 25 shows its block diagram and the connection of external devices.
CH-8 supports the soft-start function.
Figure 25. CH-8 Block Diagram
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LDO-1
LDO-2
LDO-3
LDO-4
LDO-5
PROTECTION FUNCTIONS
TSD
SCP
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
LDO-1 takes the CH-8 output voltage as an input and then outputs a voltage of 2.9 V. LDO-1 supports a currentlimit function, which reduces the output voltage when the current exceeds the specified value.
LDO-2 takes the CH-8 output voltage as an input and then outputs a voltage of 2.9 V. LDO-2 supports a currentlimit function, which reduces the output voltage when the current exceeds the specified value.
LDO-3 takes the CH-8 output voltage as an input and then outputs a voltage of 3.1 V. LDO-3 supports a currentlimit function, which reduces the output voltage when the current exceeds the specified value. LDO-3 can beturned on/off using the LDOSW3 control register.
A delay is inserted before LDO-3 is turned on so that the entire system can start up and be stable. LDO-3 cannotbe turned on until approximately 30 µs elapse after the detection of READY. DELAY2 in Figure 29 representsthis delay.
LDO-4 takes the CH-8 output voltage as an input and then outputs a voltage of 3.1 V. LDO-4 supports a currentlimit function, which reduces the output voltage when the current exceeds the specified value.
To prevent an inrush current during startup, LDO-4 has a delay so that it is not turned on simultaneously withLDO-3. LDO-4 cannot be turned on until 1.03 ms elapses after the detection of READY. This ensures that LDO-4is not turned on until 1 ms elapses after the startup of LDO-3, which is turned on 30 µs after READY detection.DELAY3 in Figure 29 represents this delay.
LDO-4 is controlled using the LDO4_ON pin, as follows:
USB ON ON/OFF
H OnL Off
LDO-5 takes the CH-4 output voltage as an input and then outputs a voltage of 8.5 V to 13.5 V for the LCDpanel. LDO-5 supports a current limit function, which reduces the output voltage when the current exceeds thespecified value. LDO-5 can be turned on/off using the LDOSW5 control register. LDO-3 has a soft-start pin dueto the power it drives.
The thermal shutdown (TSD) function protects the TPS65520 from overheat.
If the TSD activates, the TPS65520 stops all channels other than CH-8. CH-8 expects that the Sub-CPU drivesPWR_ON low due to the stop of CH-1 and CH-2, causing the TPS65520 to enter skip mode.
The short-circuit protection (SCP) function protects the output of each switching regulator from short-circuiting. Ifthe SCP activates, the TPS65520 stops all channels other than CH-8. CH-8 expects that the Sub-CPU drivesPWR_ON low due to the stop of CH-1 and CH-2, causing the TPS65520 to enter skip mode.
Figure 26 shows the block diagram, the connection of external devices, and the per-channel short-circuitinformation from the control section for each switching regulator
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CSCP
CSCP
+
−
Skip CH−8 Disable
Other Channels
Per-Channel Short-Circuit
Information From Control section
For each Switching Regulator
OVP
OCP
SUB-CPU CONTROL (RESET)
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
Figure 26. SCP Block Diagram
The overvoltage protection (OVP) function protects the CH-2, CH-3, CH-6, and CH-7 outputs from overvoltage.
If the OVP for CH-6 activates, the TPS65520 internally latches the CH-6 OVP and disables CH-6. The MOSswitch between ICH6 and FB6 is designed to remain on if the OVP activates and discharges the VCH6 potentialthrough a diode and sense resistor. To cancel the OVP for CH-6, drive PWR_ON low. The OVP for CH-6 affectsthe CH-6 output only.
If the OVP for a channel other than CH-6 activates, the TPS65520 disables the power MOS-FET switching forthat channel while still allowing the operation of the channel.
The OVP for channels other than CH-6 does not have a latch function so that the TPS65520 automaticallyrestores normal operation once it exits from the overvoltage state.
The overcurrent protection (OCP) function protects the CH-6 output from overcurrent.
The OCP monitors the FB6 pin and, if its voltage exceeds 0.85 V, it determines that an overcurrent is flowingthrough CH-6. If the OCP activates, the TPS65520 disables power MOS-FET switching for CH-6 while stillallowing the operation of CH-6. In the same way as with the OVP, the MOS switch between ICH6 and FB6 isdesigned to remain on if the OCP activates and discharges the VCH6 potential through a diode and senseresistor.
The TPS65520 restarts switching once the voltage on the FB6 pin falls below 0.85 V. The OCP does not have alatch function so that the TPS65520 automatically restores normal operation once it exits from the overcurrentstate.
The Sub-CPU function monitors the LDO-2 voltage to output XRESET, and it monitors VCH8 to output READY.
Figure 27 shows a block diagram of this function.
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+
−
VLDO2
VCH8
+
−
READY
XRESET
DELAY
VREADYx
VRSTx
LDO−2
OPERATION SEQUENCE
SOFT-START
SOFT-START OK SIGNAL FOR CH-3
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
Figure 27. Sub-CPU Control Block Diagram
The soft-start function of the TPS65520 controls the constant-current charging of the capacitors connected to theSS_SYNC, SS2, SS3, SS5, SS6, and SSLDO5 pins based on their pin voltages. When the voltage at a soft-startpin becomes approximately 0.85 V, its corresponding regulator output becomes 100%.
The soft-start circuit for CH-3 has a logic output (internal signal) function that indicates the end of soft-start forsequence control.
Figure 28 shows the entire soft-start circuit. As shown, the voltage on the SS3 pin is used as a reference for theCH-3 control section. The control section operates based on the SS3 voltage or the band gap buffer referencevoltage for the CBG pin, whichever is lower.
In Figure 28 , the comparator that outputs the SS3OK signal implements the logic output function for sequencecontrol. The threshold value for the comparator is set to a value (VSS3OK) that is sufficiently higher than theband gap buffer reference voltage. It can be assumed that CH-3 has been started when the comparator outputsthe SS3OK signal, except when the CH-3 load is heavy or short-circuited.
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SS3 +
+
−
VCH3
ErrorAmp
CH−3 Soft Start Circuit
+
−
SS3OK_DET
0.85[V]
SS3OK
>> 0.85[V]
SEQUENCE CONTROL
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
Figure 28. CH-3 Soft-Start Circuit
Most operations of the TPS65520 are controlled by the Sub-CPU. When a valid power supply, ac adaptor, orbattery is inserted, the TPS65520 automatically activates the Sub-CPU. If a Sub-CPU does not exist, theTPS65520 automatically activates the regulators and LDOs using the default values for control registers.
Figure 29 shows the connection of enable signals for the TPS65520. Figure 30 shows a timing chart. InFigure 30 , ENREGs, EN3S, EN6, EN7, ENLDO3, and ENLDO5 represent the internal enable signals shown inFigure 29 .
The following describes the relationship among enable signals in1. Upon power-up, the TPS65520 starts the wake-up circuit for CH-8 and activates the VCH8 potential. In thefigure, only CH-8 is operating.2. Once VCH8 rises, the READY detection circuit is activated and detects READY.3. Upon the detection of READY, CH-8 exits from the wake-up state and enters skip mode. At this time, theblocks in the upper half of the figure can operate. They are turned on if the enable logic signal is valid.4. In skip mode after wake-up, CH-8 enters PWM mode when PWR_ON is driven high.a. PWR_ON has a delay of approximately 60 µs to ensure that the OSC starts completely before channelsstart operating. DELAY0 in the figure represents this delay.b. A delay of approximately 1 ms is inserted to ensure that CH-8 enters PWM mode completely beforechannels start operating. DELAY1 in the figure represents this delay.5. Once CH-8 enters PWM mode, each switching regulator channel starts operating. CH-3 starts first. TheSS3OK signal from CH-3 causes other channels to start.
In Figure 30 , the TPS65520 performs the following operation, described along the time axis in the figure:1. In response to CH-8 starting up, the internal logic reset signal is generated at the same time as READYbeing canceled, thus resetting the maintained status values.2. On the rising edge of PWR_ON, CH-8 exits from skip mode and enters PWM mode. The DELAY0 andDELAY1 blocks, shown in the upper part of Figure 29 , insert delays to ensure that the mode transition is overbefore channels start operating, resulting in a total delay of 544 PWM pulses to complete this process.3. Upon the mode transition of CH-8, CH-3 starts using the soft-start procedure.4. The SS3OK signal output during the soft-start of CH-3 causes all other blocks to be enabled at one time,after which normal operation starts.5. On the falling edge of SYDDON, all channels are disabled at one time.
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TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
The shaded portions of Figure 30 represent the on/off control applied by the Sub-CPU (if used) through the serialinterface. If a Sub-CPU is used, control registers are written between the rising edges of XRESET and PWR_ON.Any channels that have been turned off do not start until the Sub-CPU turns them on again. If the Sub-CPUspecifies off for a channel that has been active from the startup, the channel goes off from that instant.
If a Sub-CPU is not used, the timing waveforms do not have the shaded portions. All channels are turned on withdefault values set in the control registers.
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CH-7 CH-4 CH-1
CH-2 CH-5
CH-6
SS2
SS
SS5
SS6
PON
SSSYNC
SSOK SS SS SS
SS SS
SS
SS
SS
SS
PON PON PON PON
PON
PON
PON
PON
PON
SSOK
D[1:0] ¹11
CH-3
SS3
SS
SSOK SS
PON
PON
IBIAS
PON
OSC
PON
REF085
PON
LDO-4
PON
OVP6
PON XERR
READY
OVP
PON XERR
SCP
PON XERR
TSD
PON XERR
READY detect
LDO4_ON
PWR_ON CH-8
DELAY0 0:SKIP
1:PWM PWM
VCH8
SSOK
SSOK
OVP
SCP
OVP
SCP
SCP SCP
OVP
SCP
SCP
SCP
VCH8
IN
LDO-3
PON
LDO-5
PON
BG
PON
LDO-1
PON
LDO-2
PON
D[4] =0D[5]=0
VOS71
D[39:38] 11
¹
VCH3S ON
D[31:30] 11¹
32[PWM Pulse] 512[PWM Pulse]
16[PWM Pulse]
ENREGs
SS3OK
EN6
ENLDO3 ENLDO5
EN7S
EN3S
NOERR
ENREGs0
SS3OK0
SS3C
SS2C
SSSC
SS5C
SS6C
512[PWM Pulse]
OCP
WAKEUP_OFF
DELAY1
DELAY3
DELAY2
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
Figure 29. Enable Signal Connections
The shaded portions apply only when a Sub-CPU is used.
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PWR_ON
ENREGs
VCH8
SS3
VCH1
td1
Battery
VLDO1
XRESET
dataA
DIN
LD
VCH3S
CH3−SW
VCH4
VOS71
VLDO5
dataD dataE dataF dataG
VCH2
ON ON
Vout6B OFF OFF
OFF OFF
LDOSW5 OFF OFF
CH7−SW
dataC
ON
OFF
ON OFF
ON
ON
ON
ON
ON
OFF
ON
ON
ON
ON
OFF
ON
ON
ON
ON
READY
VCH3
SS3OK
SS_SYNC
SS2
VCH5
SS5
VCH6
SS6
EN6
EN3S
ENLDO5
EN7S
LDOSW3 ON ON ON ON ON OFF ON
dataB
VLDO3
ENLDO3
SSLDO5
td0
td2 td3 td3r
90[%]
50[%] 50[%]
VLDO4
LDO4_ON
90[%]
td5
90[%]
td4
This sequence only appears when Sub−CPU exists.
VCH7
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
Figure 30. Operation Sequence Chart
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SERIAL INTERFACE, CONTROL REGISTERS, AND EEPROMS
D[39:32]
D[31:24]
D[23:16]
D[15:08]
D[07:00]
D[47:40] 0F(hex)
All signal lines are 8−bit size.
EX−OR gates operate bit−wise calculation.
NORMAL MODE
parity Dmax7 Dmax5 Dmax4 Dmax3 Vout7 Vout5 Vout4 Vout3 Vout2 Vout1
LDOSW5
LDOSW3
Dmax6 Vout6B
47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 08 07 04 03 0
LDO5Vo
DIN
DOUT
CH3−SW
CH7−SW
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
The logic control section of the TPS65520 consists of the serial interface, control registers, and EEPROMs. Seethe EEPROM MAP section for details of control registers, EEPROMs, and the bit assignment for reading theprotection states.
The logic section operates in either of two operating modes: para mode or test mode. Each mode is described inthis section.
Figure 34 shows the overall block configuration. In the figure, the 48-bit Shift Register block accepts D[47] (MSB)last in the time sequence. Figure 31 shows the configuration of the parity judgment circuit.
Figure 31. Configuration for Parity Bit Calculation
Driving the TEST input signal low selects para mode. In this mode, the TPS65520 allows access to the controlregisters.
Figure 32 shows the shift register configuration from input DIN to output DOUT. Figure 33 shows a single accesscycle. As shown in Figure 33 , once 48 bits have been input to the shift register, the TPS65520 determines theparity according to the output from DOUT and latches the input data using the LD input signal.
In para mode, DOUT directly reflects the output from the parity check block, which is a random logic circuit. Note,therefore, that any circuit that responds to the edge of DOUT may cause malfunctioning connections.
In para mode, the EEPROMs send the written data to each internal block.
Figure 32. Shift Register Configuration in Para Mode
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LD
DIN
CLK
bit0 bit1 bit2bitX bit47bit46
DOUT
ts1
th1
tcyc
ts2 td6
th2
TEST (zero)
bit45 bitY
TLD (zero)
tw3
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
Figure 33. Serial Interface Timing Chart in Para Mode
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DIN
DOUT
TEST
CLK
LD
CTRL_REG[39:0]
Shift Register
48[bit]
DIN
CLK
DOUT
LOAD
DLOAD[45:0]
DATA[47:0]
D[39:0]
1
0
Control Data
40[bit]
DI[39:0]
DO[39:0]
LATCH
x40 E[39:0]
parity
check
DI[47:0] GOOD
001
000
011
010
101
100
0
1
D[47:0]
E[39:0]
D[47:45]
Decoder
DATA
EEPROM
WriteData
Latch 15[bit]
D[14:0]LATCH
TLD
EEPROM
15[bit]
DI[(N−1):0]
V_WR
ROMWR
x 15
STAT[12:0]
x 15
x 15
EEPROM
WriteData
Latch 15[bit]
LATCH EEPROM
15[bit]
DI[(M−1):0]
V_WR
x 15
x 13
EUSR[14:0]
ETRM[14:0]
XALL0
x40
x40
D[45:0]
D[39:0]
1
0
1
0
D[47:45]
D[45:0]
D[47:0] D[47:0]
Zero padding
GOOD
T0
T1
T2
T3
T4
T5
WD1[14:0]WD2[14:0]
ED1[14:0]
ED2[14:0]
RD[39:0]
SCLK
XRESET
XRESET
111
110 T6
T7
PROGRAM
PROGRAM
D[14:0]
DO[14:0]
DO[14:0]
DI[14:0]
DI[14:0]
0
1
HIGH
TRY
TRY
WriteProtect
D Q
FF
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
Figure 34. Serial Interface Block Diagram
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TEST MODE
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
Driving the TEST input signal high selects test mode. In this mode, the TPS65520 allows access to all logicfunctions, including EEPROMs. The following test operations are supported:•Test A: In the same way as Para mode, the TPS65520 allows access to the control registers. Unlike the paramode, no parity check is performed. The parity judgment result is internally fixed to OK and the contents ofthe shift register are sent to DOUT.•Test 0: The contents of the control registers are copied to the shift register in synchronization with the TLDinput signal. After copying, a CLK input causes the control register value to appear at DOUT.•Test 1: Prepare (latch) the data to be written to the user setup EEPROM. When Test 6 is performedsubsequently, the latched data is written to the EEPROM. After the data is latched, any internal blocks thatreference values from EEPROM will see the latched data, instead of the data stored in EEPROM.•Test 2: The contents of the user setup EEPROM are copied to the shift register in synchronization with theTLD input signal. After copying, a CLK input causes the value from the user setup EEPROM to appear atDOUT.
•Test 3: The states of the protection functions are copied to the shift register in synchronization with the TLDinput signal. After copying, a CLK input causes the protection state value to appear at DOUT.•Test 4: Prepare (latch) the data to be written to the trimming EEPROM. When Test 7 is performedsubsequently, the latched data is written to the EEPROM. After the data is latched, any internal blocks thatreference values from EEPROM will see the latched data, instead of the data stored in EEPROM.•Test 5: The contents of the trimming EEPROM are copied to the shift register in synchronization with theTLD input signal. After copying, a CLK input causes the value from the trimming EEPROM to appear atDOUT.
•Test 6: Data is written to the user setup EEPROM.•Test 7: Data is written to the trimming EEPROM.•Test Mode Switching: Test A does not require a transition to a special mode. Its operation is the same as innormal mode, except the difference in the DOUT output.•Tests 0 to 7 require explicit mode switching using the Decoder shown in Figure 34 . The Decoder uses thethree high-order bits in the shift register to change the mode. Table 8 shows the bit assignment.
Table 8. Bit Assignments
D[47] D[46] D[45] MODE
* * * Test A0 0 0 Test 00 0 1 Test 10 1 0 Test 20 1 1 Test 31 0 0 Test 41 0 1 Test 51 1 0 Test 61 1 1 Test 7
•Information Read Mode: In Test mode, Tests 0, 2, 3, and 5 have a common function: copy some TPS65520internal logic values to the shift register and read them from DOUT. Since their operations are similar, thissection describes them together.
Figure 35 to Figure 38 shows the shift register configuration from input DIN and output DOUT as well as changesin the shift register caused by a TLD input pulse.
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Dmax7 Dmax5 Dmax4 Dmax3 Vout7 Vout5 Vout4 Vout3 Vout2 Vout1
LDOSW5
LDOSW3
Dmax6 Vout6B
LDO5Vo
0 00
0 00
TLD pulse
DIN DOUT
DIN DOUT
47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 08 07 04 03 0
CH3−SW
CH7−SW
1 00
1 00
TLD pulse
(”0” for unused bits)
DIN
DOUT
DIN
DOUT
47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 08 07 04 03 0
TRIM_DTCF1
TRIM_DTCF0
TRIM_DTCR1
TRIM_DTCR0
TRIM_DTC0
1 10
1 10
SCP7
(none)
SCP5
SCP4
SCP3
SCP2
SCP1
OVP7
OVP6
OVP3
OVP2
TSD
SKP
(”0” for unused bits)
TLD pulse
DIN
DOUT
DIN
DOUT
47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 08 07 04 03 0
0 11
TLD pulse
TRIM_OSC(3bit)
0 11 TRIM_BG(5bit) TRIM_GAIN0(2bit) TRIM_VOFF0(2bit) TRIM_ICHG(1bit) (”0” for unused bits)
DIN
DOUT
DIN
DOUT
47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 08 07 04 03 0
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
Figure 35. Shift Register Configuration and Changes for Test 0
Figure 36. Shift Register Configuration and Changes for Test 2
Figure 37. Shift Register Configuration and Changes for Test 3
Figure 38. Shift Register Configuration and Changes for Test 5
Figure 39 takes Test 0 as an example and shows a single access cycle. As shown in the figure, a TLD input fromDIN, following the input of the data 000 (bin) to select Test 0, causes the contents of the control registers to becopied to the shift register. Subsequent 48-bit CLK inputs enables the user to read data sequentially from DOUT.
The values read in Test 3 are cleared once PWR_ON is pulled high. Data should, therefore, be read whilePWR_ON is low after protection activates.
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(A[47])
LD
DIN
CLK
0 0 0
TEST
TLD
D[47]
T000
DOUT
ts3 tw1
A[0] A[1] 0A[44]
ts4
(high)
td7
A[2] 00
D[46]
D[2]
D[1]
D[0]
D[45]
0
0
0
0
0
0
A[44]A[0] A[1] A[2]
A[1]
A[2]
0
0
0
A[2]
A[3]
A[3]
A[4]
0
00
0
0
Y[1]Y[0]
Y[2]
Y[3]
Y[46]
Y[47]
0
0
0
Y[1]
Y[2]
Y[45]
Y[46]
Y[47] 0
0
0
Y[2]
Y[3]
Y[4]
Y[47]
Y[3]
Y[4]
Y[5]
Y[1]Y[0] Y[2]X[47]
K[0] K[1] K[2] K[44] K[45] K[46] K[47]
K[0] K[1] K[43] K[44] K[45] K[46] K[47]
K[0] K[42] K[43] K[44] K[45] K[46]
K[41] K[42] K[43] K[44] K[45]
K[0] K[1] K[2]
K[0] K[1]
K[0]
(A[46])
(A[45])
(A[47])
(A[46]) (A[47])
(A[47])
(A[46]) (A[47])
(A[47])
(A[46])
(A[45])
(A[46])
(A[45])
(A[46]) (A[47])(A[45])
0 10
DIN
DOUT
47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 08 07 04 03 0
TRIM_DTCF1
TRIM_DTCF0
TRIM_DTCR1
TRIM_DTCR0
TRIM_DTC0
TRIM_OSC(3bit)
0 01 TRIM_BG(5bit) TRIM_GAIN0(2bit) TRIM_VOFF0(2bit) TRIM_ICHG(1bit)
DIN
DOUT
47 44 43 40 39 36 35 32 31 28 27 24 23 20 19 16 15 12 11 08 07 04 03 0
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
Figure 39. Serial Interface Timing Chart in Test Mode: Information Read
EEPROM Data Input Mode: In test mode, Tests 1 and 4 have a common function: internally latch the data to bewritten to an EEPROM in the TPS65520 temporarily. Since their operations are similar, this section describesthem together.
Figure 40 and Figure 41 show the shift register configuration from input DIN and output DOUT.
Figure 40. Shift Register Configuration for Test 1
Figure 41. Shift Register Configuration for Test 4
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LD
DIN
CLK
bit0 bit1 bit2bitX 01
TEST
bit14 0 bitY
TLD
X[14:0] WD_A[14:0]WD1[14:0]
T001
X[14:0] WD_A[14:0]EUSR[14:0]
(high)
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
Figure 42 takes test 1 as an example and shows a single access cycle. As shown in the figure, a TLD input fromDIN, following the input of the data to be written to the EEPROM and then 001 (bin) to select Test 1, causes theTPS65520 to internally latch the data to be written temporarily. If data is latched at least once by TLD, anyinternal blocks that reference values from EEPROM will see the latched data, instead of the data stored inEEPROM, until TEST is driven low.
Figure 42. Serial Interface Timing Chart in Test Mode: EEPROM Data Input
EEPROM Data Write Mode: In test mode, tests 6 and 7 have a common function: write data to an EEPROM inthe TPS65520. Since their operations are similar, this section describes them together.
Figure 43 takes test 6 as an example and shows a single access cycle. As shown in the figure, the EEPROMwrite voltage, ROMWR, is applied after the data 110 (bin) is input from DIN to select Test 6. A TLD inputfollowing the rise of ROMSW triggers a write to the EEPROM. The duration of the write depends on the TLDpulse width. Once the write is finished, stop applying ROMWR.
For Test 7, write protection is applied to the write timing signal generated using TLD.
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LD
DIN
CLK
0 1 1bitX
TEST
bitY
TLD
T110
tw2
(high)
WD_A[14:0]WD1[14:0]
ROMWR
X’[14:0] WD_A[14:0]ED1[14:0]
ts5 th3
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
Figure 43. Serial Interface Timing Chart in Test Mode: EEPROM Data Write
Table 9. EVM-XX LIST OF MATERIALS
NAME VALUE DEVICE TYPE EXAMPLE PART NAME
PM71 (CH-7 PMOS) PMOS SANYO MCH3306/CPH5802PM72 (CH-7 Load SW) PMOS SANYO MCH3306/CPH5802NM71 (CH-7 NMOS) NMOS SANYO MCH3406/MCH5801D4 (CH-4) SBD SANYO SBS004MD5 (CH-5) SBD SANYO SBS004MD6 (CH-6) SBD SANYO SBS004MLED6 (CH-6) White LED NICHIA NSCW100-T38,NSCW100-T39ROSC 150 k ΩResistorRSNS6 22 k ΩResistorCERR1 0.01 µF Ceramic capacitor TDK C0603[B, 6.3V], Murata GRP03[0603, B, 6.3]CERR2 0.01 µF Ceramic capacitor TDK C0603[B, 6.3V], Murata GRP03[0603, B, 6.3]CERR3 0.022 µF Ceramic capacitor TDK C1005[B, 25V], Murata GRP15[1005, B, 16V]CERR4 0.01 µF Ceramic capacitor TDK C0603[B, 6.3V], Murata GRP03[0603, B, 6.3]CERR5 0.022 µF Ceramic capacitor TDK C1005[B, 25V], Murata GRP15[1005, B, 16V]CERR6 1 µF Ceramic capacitor TDK C1005[B, 25V], Murata GRP15[1005, B, 16V]CERR7 0.1 µF Ceramic capacitor TDK C1005[B, 25V], Murata GRP15[1005, B, 16V]CERR8 0.01 µF Ceramic capacitor TDK C1005[B, 25V], Murata GRP15[1005, B, 16V]
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TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
Table 9. EVM-XX LIST OF MATERIALS (continued)
NAME VALUE DEVICE TYPE EXAMPLE PART NAME
CCH1 22 µF Ceramic capacitor TDK C3225[B, 6.3V]CCH2 10 µF Ceramic capacitor TDK C2012[B, 6.3V]CCH3 22 µF Ceramic capacitor TDK C3225[22 µF, B, 6.3V]CCH4 10 µF Ceramic capacitor TDK C3225[10 µF, B, 25V]CCH5 10 µF Ceramic capacitor (unknown)[10 µF, B, 10V]CCH6 10 µF Ceramic capacitor TDK C3225[10 µF, B, 25V]CCH7 22 µF Ceramic capacitor TDK C3225[22 µF, B, 6.3V]CCH8 10 µF Ceramic capacitor TDK C2012[B, 6.3V]CLDO1 4.7 µF Ceramic capacitor TDK C2012[B, 6.3V], Murata GRM21[2012, B, 6.3V]CLDO2 22 µF Tantalium capacitorCLDO3 4.7 µF Ceramic capacitor TDK C2012[B, 6.3V], Murata GRM21[2012, B, 6.3V]CLDO4 10 µF Ceramic capacitor TDK C2012[B, 6.3V]CLDO5 22 µFSS_SYNC Ceramic capacitorSS2 Ceramic capacitorSS3 Ceramic capacitorSS5 Ceramic capacitorSS6 Ceramic capacitorSSLDO5 Ceramic capacitorBOOT11 0.01 µF Ceramic capacitor TDK C1005[B, 25V], Murata GRP15[1005, B, 16V]BOOT12 0.01 µF Ceramic capacitor TDK C1005[B, 25V], Murata GRP15[1005, B, 16V]BOOT2 0.01 µF Ceramic capacitor TDK C1005[B, 25V], Murata GRP15[1005, B, 16V]CSCP Ceramic capacitorCBG 1 µF Ceramic capacitor TDK C0603[B, 6.3V], Murata GRP03[0603, B, 6.3]CREF 0.1 µF Ceramic capacitor TDK C0603[B, 6.3V], Murata GRP03[0603, B, 6.3]L1 10 µH TDK RLF5018L2 10 µH TDK RLF5018L3 10 µH Sumida CDRH6D28L4 4.7 µH TDK RLF5018L5 33 µH DK RLF5018L6 4.7 µH TDK RLF5018L7 10 µH Sumida CDRH6D28 L8L8 10 µH TDK RLF5018
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TYPICAL CHARACTERISTICS
0
10
20
30
40
50
60
70
80
90
100
0 0.1 0.2 0.3 0.4 0.5 0.6
Efficiency [%]
Load Current [A]
VIN=1.8[V](UP)
VIN=2.4[V](UP)
VIN=3.6[V](CROSS)
VIN=4.2[V](DOWN)
60
65
70
75
80
85
90
95
100
1 2 3 4 5 6
Efficiency [%]
Input Voltage [V]
VCH1=2.5[V]
VCH1=2.8[V]
VCH1=3.2[V]
0
10
20
30
40
50
60
70
80
90
100
0 0.1 0.2 0.3 0.4 0.5 0.6
Efficiency [%]
Load Current [A]
VIN=1.8[V]
VIN=2.4[V]
VIN=3.6[V]
VIN=4.2[V]
0
10
20
30
40
50
60
70
80
90
100
0 0.1 0.2 0.3 0.4 0.5 0.6
Efficiency [%]
Load Current [A]
VIN=1.6[V]
VIN=2.4[V]
VIN=3.6[V]
VIN=4.2[V]
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
CH-1 Efficiency vs Load Current CH-1 Efficiency vs Input Voltage (Load Current: 200 mA)
Figure 44. Figure 45.
CH-2 Efficiency vs Load Current CH-3 Efficiency vs Load Current
Figure 46. Figure 47.
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0
10
20
30
40
50
60
70
80
90
100
0 0.02 0.04 0.06 0.08 0.1 0.12
Efficiency [%]
Load Current [A]
VIN=1.6[V]
VIN=2.4[V]
VIN=3.6[V]
VIN=4.2[V]
0
10
20
30
40
50
60
70
80
90
100
0 0.02 0.04 0.06 0.08 0.1 0.12
Efficiency [%]
Load Current [A]
VIN=4.4[V]
VIN=4.9[V]
VIN=5.2[V]
0
10
20
30
40
50
60
70
80
90
100
0 0.02 0.04 0.06 0.08 0.1 0.12
Efficiency [%]
Load Current [A]
VIN=1.6[V]
VIN=2.4[V]
VIN=3.6[V]
VIN=4.2[V]
0
10
20
30
40
50
60
70
80
90
100
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Efficiency [%]
REF6 [V]
VIN=1.6[V]
VIN=2.4[V]
VIN=3.0[V]
VIN=4.2[V]
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
TYPICAL CHARACTERISTICS (continued)
CH-4 Efficiency vs Load Current CH-5 Efficiency vs Load Current (Input: VCH3)
Figure 48. Figure 49.
CH-5 Efficiency vs Load Current (Input: UNREG) CH-6 Efficiency vs REF6 (Output: 8 mA, LED2 on)
Figure 50. Figure 51.
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0
10
20
30
40
50
60
70
80
90
100
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Efficiency [%]
REF6 [V]
VIN=1.6[V]
VIN=2.4[V]
VIN=3.0[V]
VIN=4.2[V]
0
10
20
30
40
50
60
70
80
90
100
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Efficiency [%]
REF6 [V]
VIN=1.6[V](LEDx4)
VIN=2.4[V](LEDx4)
VIN=3.0[V](LEDx5)
VIN=4.2[V](LEDx5)
0
10
20
30
40
50
60
70
80
90
100
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Efficiency [%]
REF6 [V]
VIN=1.6[V](LEDx4)
VIN=2.4[V](LEDx4)
VIN=3.0[V](LEDx5)
VIN=4.2[V](LEDx5)
0
10
20
30
40
50
60
70
80
90
100
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Efficiency [%]
REF6 [V]
VIN=1.6[V]
VIN=2.4[V]
VIN=3.0[V]
VIN=4.2[V]
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
TYPICAL CHARACTERISTICS (continued)
CH-6 Efficiency vs REF6 (Output: 8 mA, LED4/5 on) CH-6 Efficiency vs REF6 (Output: 12 mA, LED2 on)
Figure 52. Figure 53.
CH-6 Efficiency vs REF6 (Output: 12 mA, LED4/5 on) CH-6 Efficiency vs REF6 (Output: 20 mA, LED2 on)
Figure 54. Figure 55.
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0
10
20
30
40
50
60
70
80
90
100
0 0.1 0.2 0.3 0.4 0.5 0.6
Efficiency [%]
Load Current [A]
VIN=1.8[V]
VIN=2.4[V]
VIN=3.6[V]
VIN=4.2[V]
0
10
20
30
40
50
60
70
80
90
100
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Efficiency [%]
REF6 [V]
VIN=1.6[V](LEDx4)
VIN=2.4[V](LEDx4)
VIN=3.0[V](LEDx5)
VIN=4.2[V](LEDx5)
0
10
20
30
40
50
60
70
80
90
100
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
Efficiency [%]
Load Current [A]
VIN=4.4[V]
VIN=4.9[V]
VIN=5.2[V]
0
10
20
30
40
50
60
70
80
90
100
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
Efficiency [%]
Load Current [A]
VIN=3.6[V]
VIN=4.2[V]
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
TYPICAL CHARACTERISTICS (continued)
CH-6 Efficiency vs REF6 (Output: 20 mA, LED4/5 on) CH-7 Efficiency vs Load Current(MODE7 = H)
Figure 56. Figure 57.
CH-7 Efficiency vs Load Current CH-7 Efficiency vs Load Current(Input: VCH3, MODE7 = L) (Input: UNREG, MODE7 = L)
Figure 58. Figure 59.
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0
10
20
30
40
50
60
70
80
90
100
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45
Efficiency [%]
Load Current [A]
VIN=1.8[V]
VIN=2.4[V]
VIN=3.6[V]
VIN=4.2[V]
0
10
20
30
40
50
60
70
80
90
100
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16
Efficiency [%]
Load Current [A]
VIN=1.6[V]
VIN=2.4[V]
VIN=3.6[V]
VIN=4.2[V]
2.74
2.76
2.78
2.8
2.82
2.84
2.86
0 0.1 0.2 0.3 0.4 0.5 0.6
VCH1 [V]
Load Current [A]
VIN=1.8[V](UP)
VIN=2.4[V](UP)
VIN=3.6[V](CROSS)
VIN=4.2[V](DOWN)
1.18
1.19
1.2
1.21
1.22
0 0.1 0.2 0.3 0.4 0.5 0.6
VCH2 [V]
Load Current [A]
VIN=1.6[V]
VIN=2.4[V]
VIN=3.6[V]
VIN=4.2[V]
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
TYPICAL CHARACTERISTICS (continued)
CH-8 Efficiency vs Load Current (PWM Mode) CH-8 Efficiency vs Load Current (Skip Mode)
Figure 60. Figure 61.
CH-1 Output Voltage vs Load Current (±2% Axis) CH-2 Output Voltage vs Load Current (±2% Axis)
Figure 62. Figure 63.
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14.7
14.8
14.9
15
15.1
15.2
15.3
0 0.02 0.04 0.06 0.08 0.1 0.12
VCH4 [V]
Load Current [A]
VIN=1.6[V]
VIN=2.4[V]
VIN=3.6[V]
VIN=4.2[V]
4.8
4.85
4.9
4.95
5
0 0.1 0.2 0.3 0.4 0.5 0.6
VCH3 [V]
Load Current [A]
VIN=1.8[V]
VIN=2.4[V]
VIN=3.6[V]
VIN=4.2[V]
−7.65
−7.6
−7.55
−7.5
−7.45
−7.4
−7.35
0 0.02 0.04 0.06 0.08 0.1 0.12
VCH5 [V]
Load Current [A]
VIN=1.6[V]
VIN=2.4[V]
VIN=3.6[V]
VIN=4.2[V]
−7.65
−7.6
−7.55
−7.5
−7.45
−7.4
−7.35
0 0.02 0.04 0.06 0.08 0.1 0.12
VCH5 [V]
Load Current [A]
VIN=4.4[V]
VIN=4.9[V]
VIN=5.2[V]
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
TYPICAL CHARACTERISTICS (continued)
CH-3 Output Voltage vs Load Current (±2% Axis) CH-4 Output Voltage vs Load Current (±2% Axis)
Figure 64. Figure 65.
CH-5 Output Voltage vs Load Current CH-5 Output Voltage vs Load Current(Input: VCH3, ±2% Axis) (Input: UNREG, ±2% Axis)
Figure 66. Figure 67.
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3.04
3.06
3.08
3.1
3.12
3.14
3.16
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
VCH7 [V]
Load Current [A]
VIN=4.4[V]
VIN=4.9[V]
VIN=5.2[V]
0
0.005
0.01
0.015
0.02
0.025
0.03
0.035
0.04
0 0.2 0.4 0.6 0.8 1 1.2 1.4
Output Current [A]
REF6 [V]
IOUT=8[mA]
IOUT=12[mA]
IOUT=20[mA]
4.8
4.85
4.9
4.95
5
0 0.1 0.2 0.3 0.4 0.5 0.6
VCH7 [V]
Load Current [A]
VIN=1.8[V]
VIN=2.4[V]
VIN=3.6[V]
VIN=4.2[V]
3.04
3.06
3.08
3.1
3.12
3.14
3.16
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
VCH7 [V]
Load Current [A]
VIN=3.6[V]
VIN=4.2[V]
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
TYPICAL CHARACTERISTICS (continued)
CH-6 Output Current vs REF6 CH-7 Output Voltage vs Load Current(Input: 3.0 V, LED5 on) (MODE7 = H, ±2% Axis)
Figure 68. Figure 69.
CH-7 Output Voltage vs Load Current CH-7 Output Voltage vs Load Current(Input: VCH3, MODE7 = L, ±2% (Input: UNREG, MODE7 = L, ±2% Axis)
Figure 70. Figure 71.
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3.5
3.6
3.7
3.8
3.9
4
4.1
4.2
4.3
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45
VCH8 [V]
Load Current [A]
VIN=1.8[V]
VIN=2.4[V]
VIN=3.6[V]
VIN=4.2[V]
3.54
3.56
3.58
3.6
3.62
3.64
3.66
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45
VCH8 [V]
Load Current [A]
VIN=1.8[V]
VIN=2.4[V]
VIN=3.6[V]
0.70
0.75
0.80
0.85
0.90
0.95
1.00
IL1
[A]
0.5 [us/div]
−1.0
0.0
1.0
2.0
3.0
4.0
VOUT12
[V]
0.5 [us/div]
3.45
3.5
3.55
3.6
3.65
3.7
3.75
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16
VCH8 [V]
Load Current [A]
VIN=1.6[V]
VIN=2.4[V]
VIN=3.6[V]
VIN=4.2[V]
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
TYPICAL CHARACTERISTICS (continued)
CH-8 Output Voltage vs Load Current CH-8 Output Voltage vs Load Current(PWM Mode, ±2% Axis) (PWM Mode, 3.5 to 4.3 V Axis)
Figure 72. Figure 73.
CH-8 Output Voltage vs Load Current CH-1 Peak Current Waveform(Skip Mode, ±5% Axis) (Step-up, Input: 1.8 V, Output: 400 mA)
Figure 74. Figure 75.
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0.40
0.45
0.50
0.55
0.60
IL2
[A]
0.5 [us/div]
−2.0
−1.0
0.0
1.0
2.0
3.0
VOUT2
[V]
0.5 [us/div]
1.30
1.40
1.50
1.60
1.70
IL3 [A]
0.5 [us/div]
−1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
VOUT3 [V]
0.5 [us/div]
0.80
0.90
1.00
1.10
1.20
1.30
1.40
IL4 [A]
0.5 [us/div]
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
VOUT4 [V]
0.5 [us/div]
0.00
0.05
0.10
0.15
0.20
0.25
0.30
IL5 [A]
0.5 [us/div]
−10.0
−8.0
−6.0
−4.0
−2.0
0.0
2.0
4.0
6.0
VOUT5 [V]
0.5 [us/div]
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
TYPICAL CHARACTERISTICS (continued)
CH-2 Peak Current Waveform CH-3 Peak Current Waveform(Input: 1.8 V, Output: 500 mA) (Input: 1.8 V, Output: 400 mA)
Figure 76. Figure 77.
CH-4 Peak Current Waveform CH-5 Peak Current Waveform(Input: 1.8 V, Output: 50 mA) (Input: VCH3, Output: 50 mA)
Figure 78. Figure 79.
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−0.10
0.00
0.10
0.20
0.30
0.40
0.50
0.60
IL6 [A]
0.5 [us/div]
−2.0
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
VOUT6 [V]
0.5 [us/div]
2.80
3.00
3.20
3.40
3.60
3.80
IL7 [A]
0.5 [us/div]
−1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
VOUT7 [V]
0.5 [us/div]
0.00
0.01
0.01
0.01
0.02
0.03
0.03
0.04
IL7 [A]
0.5 [us/div]
−1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
VOUT7 [V]
0.5 [us/div]
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
IL8 [A]
0.5 [us/div]
−1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
VOUT8 [V]
0.5 [us/div]
TPS65520
SLVS557A – MARCH 2005 – REVISED JUNE 2005
TYPICAL CHARACTERISTICS (continued)
CH-6 Peak Current Waveform CH-7 Peak Current Waveform(Input: 1.8 V, Output: 20 mA) (MODE7 = H, Input: 1.8 V, Output: 500 mA)
Figure 80. Figure 81.
CH-7 Peak Current Waveform CH-8 Peak Current Waveform(MODE7 = L, Input: VCH3, Output: 150 mA) (Input: 1.8 V, Output: 200 mA)
Figure 82. Figure 83.
59
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS65520ZVDR ACTIVE NFBGA ZVD 113 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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