5555 N.E. Moore Ct. Hillsboro, Oregon 97124-6421 Phone (503) 268-8000 FAX (503) 268-8347
Internet: http://www.latticesemi.com
ispPAC®-POWR1208P1 Device Datasheet
September 2010
All Devices Discontinued!
Product Change Notification (PCN) #13-10 has been issued to discontinue all devices in
this data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
Product Line
Ordering Part Number
Product
Status
Reference PCN
ispPAC-
POWR1208P1
ispPAC-POWR1208P1-01T44I
Discontinued
PCN#13-10
ispPAC-POWR1208P1-01TN44I
www.latticesemi.com
3-1
DS1033_01.0
February 2005 Data Sheet DS1033
© 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other
brand or product names are trademarks or registered trademarks of their respective holders . The specifications and information herein are subject to change without
notice.
Features
■
Monitor and Control Multiple Power
Supplies
• Simultaneously monitors up to 12 po w er supplies
• Sequence controller for power-up conditions
• Provides eight output control signals
• Programmable digital and analog circuitry
■
Precision Analog Comparators for
Monitoring
• 12 analog comparators for monitoring
• 384 programmable threshold levels spanning
0.68V to 5.93V
• 0.5% precision
• Other user-defined voltages possible
• 80mV near-ground threshold for power-off
detect
• Each comparator independently configurable
• Eight direct comparator outputs
• Digital filter on comparator outputs
■
Embedded PLD for Sequence Control
• Implements state machine and input conditional
events
• In-System Programmable (ISP™) through JTAG
and on-chip E
2
CMOS
®
• Input synchronizers
■
Embedded Programmable Timers
• 4 Programmable 8-bit timers (32µs to 524ms)
• Programmable time delay between multiple
power supply ramp-up and wait statements
■
Embedded Oscillator
• Built-in clock generator, 1MHz
• Programmable clock frequency
• Programmable timer pre-scaler
• External clock support
■
Programmable Output Configurations
• Four digital outputs for logic and power supply
control
• Four fully programmable gate driver outputs for
FET control, or programmable as four additional
digital outputs
• Expandable with ispMACH™ 4000 CPLD
■
2.7V to 5.5V Supply Range
• In-system programmable at 3.0V to 5.5V
• Industrial temperature range: -40°C to +85°C
• 44-pin TQFP package
Application Block Diagram
Description
The Lattice ispPAC-POWR1208P1 incorporates both in-
system programmable logic and in-system programma-
ble analog circuits to perform special functions for
power supply sequencing and monitoring. The ispPAC-
POWR1208P1 device has the capability to be config-
ured through software to control up to eight outputs for
power supply sequencing and 12 comparators monitor-
ing supply voltage limits , along with four digital inputs for
interfacing to other control circuits or digital logic. Once
configured, the design is downloaded into the device
through a standard JTAG interface. The circuit configu-
ration and routing are stored in non-volatile E
2
CMOS.
PAC-Designer,
®
an easy-to-use Windows-compatible
software package gives users the ability to design and
simulate logic and sequences that control the power
supplies or FET driver circuits. The user has control
over timing functions, programmable logic functions and
comparator threshold values as well as I/O configura-
tions.
Primary +
Gnd
+
-
+5V
+3.3V
+2.5V
+1.0V +1V
ispPAC-POWR1208P1
Power Sequence
Controller
HVOUT1
0.1uF10uF
HVOUT2
HVOUT3
HVOUT4
OUT5
OUT6
OUT7
OUT8
DC/DC Supply
or Regulator
OE/EN
Digital
Logic
EN
Circuits
RESET
Comp2
Comp4
VMON12
12 Analog Inputs
IN1
IN2
VDD
IN3
IN4
VMON1
VMON2
VMON3
VMON4
VMON5
VMON6
VMON7
VMON8
VMON9
VMON10
VMON11
CLK
Comp3
Comp1
Comp6
Comp8
Comp7
Comp5
+2.5V
Circuits
+3.3V
Circuits
+5V
Circuits
OE/EN
Digital
Logic
EN
Primary +
Gnd
+
-
Primary +
Gnd
+
-
DC/DC
Supply
Primary +
Gnd
+
-
DC/DC Supply
or Regulator
POR
DC/DC
Supply
DC/DC
Supply
DC/DC
RG
Supply
VDD VDDINP
0.1uF
CREF
3.3V
3.3V
RG
RG
RG
ispPAC-POWR1208P1
In-System Programmable Power Supply
Sequencing Controller and Precision Monitor
®
ALL DEVICES
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USE ispPAC-POWR1014/A
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Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-2
Power Supply Sequence Controller and Monitor
The ispPAC-POWR1208P1 device is specifically designed as a fully-programmable power supply sequencing con-
troller and monitor for managing up to eight separate power supplies, as well as monitoring up to 12 analog inputs
or supplies. The ispPA C-POWR1208P1 device contains an internal PLD that is programmab le by the user to imple-
ment digital logic functions and control state machines. The internal PLD connects to four programmable timers,
special pur pose I/O and the programmable monitoring circuit blocks. The inter nal PLD and timers can be clocked
by either an internal programmable clock oscillator or an external clock source.
The voltage monitors are arranged as 12 independent comparators, each with 384 programmable trip-point set-
tings ranging from 0.68V to 5.392V in roughly 0.5% steps. An additional low-voltage threshold (80mV) is also pro-
vided for sensing power-off conditions.
The voltage monitors incorporate two features designed to increase their robustness. The first is a small amount of
hysteresis. In general, more hysteresis implies more noise immunity, but as trip-points decrease a fixed amount of
hysteresis would adversely affect the trip-point accuracy. For this reason the ispPAC-POWR1208P1’s voltage mon-
itors use a scheme in which hysteresis scales with trip-point voltages remaining at a nearly constant 0.5% of the
selected trip-point. Hysteresis is 30mV for a 5.932V trip-point and scales down to 4mV for a 0.68V trip-point.
The second feature that increases the voltage monitor’s robustness are a synchronizer and digital filter in each
monitor circuit. The filter may be optionally enabled to provide higher noise immunity at the cost of a somewhat
increased response time.
The programmable logic functions consist of a block of 36 inputs with 81 product terms and 16 macrocells. The
architecture supports the steering of product terms to enhance the overall usability.
Output pins are configurable in two different modes. There are eight outputs for controlling eight different power
supplies. OUT5-OUT8 are open-drain outputs for interfacing to other circuits. The HVOUT1-HVOUT4 pins can be
programmed individually as open-drain outputs or as high voltage FET gate drivers. As high voltage FET gate
driver outputs, they can be used to dr ive an exter nal N-Channel MOSFET as a switch to control the voltage ramp-
up of the target board. The four HVOUT drivers have programmable current and voltage levels.
Figure 3-1. ispPAC-POWR1208P1 Block Diagram
Sequence
Controller
CPLD
36 I/P & 16
Macrocell
GLB
Comparator
Outputs
High V oltage
Outputs
Analog
Inputs
CLKIO
Digital
Inputs
250kHz
Internal
OSC
4 Timers Logic
Outputs
12
8
4
4
5
COMP1
COMP2
COMP3
COMP4
COMP5
COMP6
COMP7
COMP8
OUT5
OUT6
OUT7
OUT8
HVOUT1
HVOUT2
HVOUT3
HVOUT4
VDD
ispPAC-POWR1208P1
VMON1
VMON2
VMON3
VMON4
VMON5
VMON6
VMON7
VMON8
VMON9
VMON10
VMON11
VMON12
IN1
RESET
IN2
IN3
IN4
ALL DEVICES
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USE ispPAC-POWR1014/A
FOR NEW DESIGNS
Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-3
Pin Descriptions
Number Name Pin Type Description
1 HVOUT4 O/D Output Open-drain Output 4
Current Source FET Gate Driver 4
2 HVOUT3 O/D Output Open-drain Output 3
Current Source FET Gate Driver 3
3 HVOUT2 O/D Output Open-drain Output 2
Current Source FET Gate Driver 2
4 HVOUT1 O/D Output Open-drain Output 1
Current Source FET Gate Driver 1
5 VDD Power Main Power Supply
6 IN1 CMOS Input Input 1, Schmitt-Trigger Input
7 IN2 CMOS Input Input 2, Schmitt-Trigger Input
8 IN3 CMOS Input Input 3, Schmitt-Trigger Input
9 IN4 CMOS Input Input 4, Schmitt-Trigger Input
10 RESET
CMOS input
1
PLD Reset Input, Active Low, Schmitt-Trigger Input
11 VDDINP Power
2
Digital Inputs Power Supply
12 OUT5 O/D Output Open-Drain Output
13 OUT6 O/D Output Open-Drain Output
14 OUT7 O/D Output Open-Drain Output
15 OUT8 O/D Output Open-Drain Output
16 COMP8 O/D Output VMON8 Comparator Output (Open-Drain)
17 COMP7 O/D Output VMON7 Comparator Output (Open-Drain)
18 COMP6 O/D Output VMON6 Comparator Output (Open-Drain)
19 COMP5 O/D Output VMON5 Comparator Output (Open-Drain)
20 COMP4 O/D Output VMON4 Comparator Output (Open-Drain)
21 COMP3 O/D Output VMON3 Comparator Output (Open-Drain)
22 COMP2 O/D Output VMON2 Comparator Output (Open-Drain)
23 COMP1 O/D Output VMON1 Comparator Output (Open-Drain)
24 TCK TTL/LVCMOS Input Test Clock (JTAG Pin)
25 POR
O/D Output Power-On-Reset Output
26 CLK Bi-directional I/O
3
Clock Output (Open-Drain) or Clock Input
27 GND Ground Ground
28 TDO TTL/LVCMOS Output Test Data Out (JTAG Pin)
29 TRST
TTL/LVCMOS Input Test Reset, Active Low, 50k Ohm Internal Pull-up (JTAG Pin, Optional
Use)
30 TDI TTL/LVCMOS Input Test Data In, 50k Ohm Internal Pull-up (JTAG Pin)
31 TMS TTL/LVCMOS Input Test Mode Select, 50k Ohm Internal pull-up (JTAG Pin)
32 VMON1 Analog Input Voltage Monitor Input 1
33 VMON2 Analog Input Voltage Monitor Input 2
34 VMON3 Analog Input Voltage Monitor Input 3
35 VMON4 Analog Input Voltage Monitor Input 4
36 VMON5 Analog Input Voltage Monitor Input 5
37 VMON6 Analog Input Voltage Monitor Input 6
38 VMON7 Analog Input Voltage Monitor Input 7
ALL DEVICES
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Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-4
Absolute Maximum Ratings
Absolute maximum ratings are shown in the table below. Stresses beyond these listed values may cause perma-
nent damage to the device. Functional operation of the device at these or any other conditions outside those indi-
cated in the operating sections of this specification is not implied.
39 CREF Reference
4
Reference for Internal Use, Decoupling Capacitor (.1uf Required,
CREF to GND)
40 VMON8 Analog Input Voltage Monitor Input 8
41 VMON9 Analog Input Voltage Monitor Input 9
42 VMON10 Analog Input Voltage Monitor Input 10
43 VMON11 Analog Input Voltage Monitor Input 11
44 VMON12 Analog Input Voltage Monitor Input 12
1. RESET is an active low INPUT pin, external pull-up resistor to V
DD
is required. When driven low it resets all internal PLD flip-flops to zero,
and may turn “ON” or “OFF” the output pins, including the HVOUT pins depending on the polarity configuration of the outputs in the PLD. If
a reset function is needed for the other devices on the board, the PLD inputs and outputs can be used to generate these signals. The
RESET should be used if multiple ispPAC-POWR1208P1 devices are cascaded together in expansion mode.
2. V
DDINP
can be chosen independent of V
DD.
It is used to set the logic threshold only to the four logic inputs IN1-IN4.
3. CLK is the PLD clock output in master mode . It is re-routed as an input in slav e mode . The cloc k mode is set in software during design time.
In output mode it is an open-drain type pin and requires an external pull-up resistor. Multiple ispPAC-POWR1208P1 devices can be tied
together with one acting as the master, the master can use the internal clock and the slave can be clocked by the master. The slave needs
to be set up using the clock as an input.
4. The CREF pin requires a 0.1µF capacitor to ground, near the device pin. This reference is used internally by the device. No additional
external circuitry should be connected to this pin.
Symbol Parameter Conditions Min. Max. Units
V
DD
Core supply voltage at pin — -0.5 6.0 V
V
DDINP
1
Digital input supply voltage for IN1-IN4 — -0.5 6.0 V
HVOUTmax HVOUT pin voltage, max = V
DD
+ 9V — -0.5 15 V
V
IN
2
Input voltage applied, digital inputs — -0.5 6.0 V
VMON Input voltage applied, V
MON
voltage monitor inputs — -0.5 7.0 V
V
TRI
Tristated or open drain output, external voltage applied (CLK
pin 26 pull-up
≤
V
DD
). — -0.5 6.0 V
T
S
Storage temperature — -65 150 °C
T
A
Ambient temperature with power applied — -55 125 °C
T
SOL
Maximum soldering temperature (10 sec. at 1/16 in.) — — 260 °C
1. V
DDINP
is the supply pin that controls logic inputs IN1-IN4 only. Place 0.1µF capacitor to ground and supply the V
DDINP
pin with appropriate
supply voltage for the given input logic range.
2. Digital inputs are tolerant up to 5.5V, independent of the V
DDINP
voltage.
Pin Descriptions (Continued)
Number Name Pin Type Description
ALL DEVICES
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Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-5
Recommended Operating Conditions
Analog Specifications
Over Recommended Operating Conditions
Reference
Voltage Monitors
Symbol Parameter Conditions Min. Max. Units
V
DD
Core supply voltage at pin 2.7 5.5 V
V
DDPROG
Core supply voltage at pin During E
2
cell programming 3.0 5.5 V
V
DDINP
1
Digital input supply voltage for IN1-IN4 2.25 5.5 V
V
IN
2
Input voltage digital inputs 0 5.5 V
V
MON
Voltage monitor inputs V
MON1
- V
MON12
0 6.0 V
Erase/Program
Cycles EEPROM, programmed at
V
DD
= 3.0V to 5.5V 1000 — Cycles
T
APROG
Ambient temperature during
programming -40 +85 °C
T
A
Ambient temperature Power applied -40 +85 °C
1. V
DDINP
is the supply pin that controls logic inputs IN1-IN4 only. Place 0.1µF capacitor to ground and supply the V
DDINP
pin with appropriate
supply voltage for the given input logic range.
2. Digital inputs are tolerant up to 5.5V, independent of the V
DDINP
voltage.
Symbol Parameter Conditions Min. Typ. Max. Units
I
DD
V
DD
Supply Current Internal Clock = 1MHz — 10 20 mA
I
DDINP
V
DDINP
Supply Current — 5 20 µA
Symbol Parameter Conditions Min. Typ. Max. Units
V
REF
1
Reference voltage at CREF pin T = 25°C — 1.16 — V
1. CREF pin requires a 0.1µF capacitor to ground.
Symbol Parameter Conditions Min. Typ. Max. Units
R
IN
Input impedance 70 100 130 k
Ω
V
MON
Range Programmable voltage monitor trip
point (384 steps) 0.680 5.932 V
V
MON
Accuracy Absolute accuracy of any trip point
2
T = 25 °C,
V
DD
= 3.3V
V
MON
≤
1.8V -0.5 +0.5 %
T = 25 °C,
V
DD
= 3.3V
V
MON
> 1.8V -0.6 +0.6 %
V
MON
Tempco
1
Temperature drift of any trip point -40°C to +85°C 30 ppm/ °C
V
HYST
Hysteresis of V
MON
input V
DD
= 3.3V 0.5% of
trip point
setting %
V
MONLO
Near-ground sense threshold T = 25 °C,
V
DD
= 3.3V 70 80 90 mV
PSR Trip point sensitivity to V
DD
V
DD
= 3.3V 0.07 %/V
1. See Performance Graphs section.
2. Guaranteed by characterization.
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Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-6
High Voltage FET Drivers
Power-On-Reset
Symbol Parameter Conditions Min. Typ. Max. Units
V
PP
Range Programmable gate driver voltage
(eight steps) (Note 1) 8 — 12 V
V
PP
Accuracy Absolute accuracy of V
PP
output
voltage 25°C -10 — 10 %
V
PP
Step Gate driver voltage step (Note 2) — 0.5 — V
I
SOURCE
Range Programmable I
SOURCE
current
(32 steps) 0.5 — 50 µA
I
SOURCE
Accuracy Absolute accuracy of I
SOURCE
current —10—%
I
STEP
Relative current value, from any
I
SOURCE
setting to the next —15—%
R
SINK
Gate driver sink/discharge resistor
when setting FET driver to a LOW
state
FET Driver in OFF state —8—k
Ω
1. Maximum voltage of V
PP
is not to exceed 7.5V over V
DD.
2. The high voltage driv er outputs are set in softw are , HVOUT voltage range is between 8V and 12V. VDD values determine the maximum VPP.
Symbol Parameter Conditions Min. Typ. Max. Units
VLPOR3VDD supply threshold above which POR out-
put is guaranteed to be driven low VDD ramping up1— — 1.15 V
VHPOR3VDD supply threshold above which POR
output is guaranteed driven high, and device
initializes VDD ramping up1— — 2.1 V
tDPOR POR delay2VDD ramping up to
3.3V in <10µs
CREF = 0.1µF —3—ms
VRESET VDD supply threshold below which will trigger
a reset cycle from the “ON’ state. VDD ramping down11.8 — 2.1 V
1. POR tests run with 10kΩ resistor pulled up to VDD.
2. 1MHz clock must be present.
3. Hysteresis = 50mV.
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Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-7
AC/Transient Characteristics
Over Recommended Operating Conditions
Digital Specifications Over Recommended Operating Conditions
DC Input Levels: IN1-IN4
Symbol Parameter Conditions Min. Typ. Max. Units.
Voltage Monitors
tPDMON Propagation Delay. Output
transitions after a step input,
from VMON to comparator
output
Glitch filter OFF.1
Input VTRIP + 100mV to VTRIP - 100mV —4 7µs
Glitch filter ON.1
Input VTRIP + 100mV to VTRIP - 100mV 28 32 35 µs
Oscillators
fCLK Internal Master Clock
frequency 0.8 1 1.2 MHz
PLDCLKext Frequency range of applied
external clock source External clock applied 0.8 — 1.2 MHz
PLDCLK
Range Programmable frequency range
of PLD clock (8 binary steps) (Note 1) 1.95 — 250 kHz
Timers
Timeout
Range Range of programmable
time-out duration (15 steps) (Note 1) 0.03 — 524 ms
1. Assumes 1MHz clock.
Symbol Parameter Conditions Min. Typ. Max. Units
IIL, IIH Input or I/O leakage current, no pull-up 0V ≤ VIN ≤ VDDINP or VDD
25 °C +/-10 µA
IPU Input pull-up current (TMS, TDI, TRST) 25 °C 70 µA
VOL Output Low Voltage
[OUT5-OUT8]
[COMP1-COMP8]
[HVOUT1-HVOUT4]
ISINKOUT = 4mA 0.4 V
ISINKHVOUT Maxim um sink current for HV OUT pins in
open-drain mode [HVOUT1-HVOUT4] (Note 1) 10 mA
ISINKOUT Maximum sink current for logic outputs
[OUT5-OUT8], [COMP1-COMP8] (Note 1) 20 mA
ISINKTOTAL Total combined sink currents from all
outputs [OUT, HVOUT, COMP] (Note 1) 80 mA
1. [OUT5-OUT8] and [COMP1-COMP8] can sink up to 20mA max. per pin for LEDs, etc. However, output voltage levels may exceed VOL.
Total combined sink currents from all outputs (OUT, HVOUT, COMP) should not exceed ISINKTOTAL.
Symbol Parameter Min. Max. Units
VIL Schmitt trigger input low voltage -0.3 0.25 x VDDINP V
VIH Schmitt trigger input high voltage 0.75 x VDDINP 5.5 V
Note: VDDINP is the input supply pin for IN1-IN4 digital logic input pins. These pins’ Schmitt-Trigger thresholds are dependent
on the voltage at VDDINP.
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Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-8
Timing CharacteristicsOver Recommended Operating Conditions
Timing for JTAG Operations
Symbol Parameter Conditions Min. Typ. Max. Units
PLD Timing
tPD Combinatorial propagation delay from INx
input to OUTx output. 150 ns
tRST RESET pulse width 25 µs
Symbol Parameter Conditions Min Typ. Max Units
tCKMIN Minimum clock period 1 µs
tCKH TCK high time 200 ns
tCKL TCK low time 200 ns
tMSS TMS setup time 15 ns
tMSH TMS hold time 50 ns
tDIS TDI setup time 15 ns
tDIH TDI hold time 50 ns
tDOZX TDO float to valid delay 200 ns
tDOV TDO valid delay 200 ns
tDOXZ TDO valid to float delay 200 ns
tRSTMIN Minimum reset pulse width 40 ns
tPWP Time for a programming operation140 100 ms
tPWE Time for an erase operation 40 100 ms
1. tPWP represents programming pulse width for a single row of E2CMOS cells.
tCK
tMSS tMSS tMSStMSH
tDIS tDIH
tCKH tCKMIN
tCKL
tMS
tCK
tMS
tDI
tDO
tDOZH tDOXZ
tDOV
tPWP, tPWE
Program and Erase cycles
executed in Run-Test/Idle
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Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-9
Performance Graphs
Lower Trip Point Error (TP’s <= 1.8V)
(VCC = 3.3V, 25C)
Upper Trip Point Error (TP’s <= 1.8V)
(VCC = 3.3V, 25C)
Upper Trip Point Error (TP’s > 1.8V)
(VCC = 3.3V, 25C)
Lower Trip Point Error (TP’s > 1.8V)
(VCC = 3.3V, 25C)
Trip Error (%)
Frequency
Frequency
0
200
1200
1000
800
600
400
200
0
-1
1
-0.9
0.9
-0.8
0.8
-0.7
0.7
-0.6
0.6
-0.5
0.5
-0.4
0.4
-0.3
0.3
-0.2
0.2
-0.1
0.1
0
Trip Error (%)
-1
1
-0.9
0.9
-0.8
0.8
-0.7
0.7
-0.6
0.6
-0.5
0.5
-0.4
0.4
-0.3
0.3
-0.2
0.2
-0.1
0.1
0
Trip Error (%)
-1
1
-0.9
0.9
-0.8
0.8
-0.7
0.7
-0.6
0.6
-0.5
0.5
-0.4
0.4
-0.3
0.3
-0.2
0.2
-0.1
0.1
0
Trip Error (%)
Temperature (°C)
-1
1
-0.9
0.9
-0.8
0.8
-0.7
0.7
-0.6
0.6
-0.5
0.5
-0.4
0.4
-0.3
0.3
-0.2
0.2
-0.1
0.1
0
400
600
800
1000
1200
1400
1600
Frequency
Frequency
Trip Point Error (%)
0
0
-0.1
-40 40 60 80 100-20 200
0.1
0.2
0.3
0.4
0.5
0
200
400
600
800
1000
1200
200
400
600
800
1000
1200
1400
1600
Typical Change in Trip Point vs. Temperature
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Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-10
Table3-1. VMON T rip Points
Table 3-1 shows all possible comparator trip point voltage settings. There are 384 available voltages, ranging from
0.680V to 5.932V, as well as a ‘near-ground’ monitor threshold of 80mV which can be used to determine if a power
supply rail has completely discharged to an OFF state . In addition to these 385 voltage monitor trip points, the user
can add external resistors to divide down the voltage and achieve vir tually any voltage trip point. This allows the
capability to monitor higher v oltages such and 12V, 15V, 24V, etc. Voltage monitor trip points are set in the graphical
user interface of PAC-Designer software by simple pull-down menus. The user simply selects the given range and
corresponding trip point value . Attenuation and reference values are set internally using E2CMOS configuration bits
internal to the device.
Theory Of Operation
The ispPAC-POWR1208P1 incor porates programmable voltage monitors along with digital inputs and outputs as
well as high voltage FET gate drivers to control MOSFETs for ramping up power supply rails. The 16 macrocell
123456789101112
00.680 0.808 0.962 1.142 1.363 1.618 1.931 2.289 2.724 3.241 4.221 5.017
10.684 0.812 0.968 1.149 1.371 1.628 1.942 2.302 2.741 3.260 4.246 5.046
20.688 0.817 0.974 1.156 1.378 1.637 1.954 2.316 2.757 3.279 4.270 5.076
30.692 0.822 0.979 1.162 1.386 1.647 1.965 2.329 2.773 3.298 4.295 5.105
40.696 0.827 0.985 1.169 1.394 1.656 1.976 2.342 2.789 3.318 4.320 5.135
50.700 0.831 0.990 1.176 1.402 1.666 1.988 2.356 2.805 3.337 4.345 5.164
60.704 0.836 0.996 1.182 1.410 1.675 1.999 2.369 2.821 3.356 4.370 5.194
70.708 0.841 1.002 1.189 1.418 1.685 2.010 2.383 2.837 3.375 4.394 5.224
80.712 0.845 1.007 1.196 1.426 1.694 2.021 2.396 2.853 3.394 4.419 5.253
90.716 0.850 1.013 1.202 1.434 1.704 2.033 2.410 2.869 3.413 4.444 5.283
10 0.720 0.855 1.019 1.209 1.442 1.713 2.044 2.423 2.885 3.432 4.469 5.312
11 0.724 0.860 1.024 1.216 1.450 1.723 2.055 2.437 2.901 3.451 4.494 5.342
12 0.728 0.864 1.030 1.222 1.458 1.732 2.067 2.450 2.917 3.470 4.518 5.371
13 0.732 0.869 1.035 1.229 1.466 1.742 2.078 2.464 2.933 3.489 4.543 5.401
14 0.736 0.874 1.041 1.236 1.474 1.751 2.089 2.477 2.949 3.508 4.568 5.430
15 0.740 0.878 1.047 1.243 1.482 1.761 2.101 2.490 2.965 3.527 4.593 5.460
16 0.744 0.883 1.052 1.249 1.490 1.770 2.112 2.504 2.981 3.547 4.618 5.489
17 0.748 0.888 1.058 1.256 1.498 1.780 2.123 2.517 2.997 3.566 4.642 5.519
18 0.752 0.893 1.064 1.263 1.506 1.789 2.135 2.531 3.013 3.585 4.667 5.548
19 0.756 0.897 1.069 1.269 1.514 1.799 2.146 2.544 3.029 3.604 4.692 5.578
20 0.760 0.902 1.075 1.276 1.522 1.808 2.157 2.558 3.045 3.623 4.717 5.607
21 0.764 0.907 1.081 1.283 1.530 1.818 2.169 2.571 3.061 3.642 4.742 5.637
22 0.768 0.911 1.086 1.289 1.538 1.827 2.180 2.585 3.077 3.661 4.766 5.666
23 0.772 0.916 1.092 1.296 1.546 1.837 2.191 2.598 3.093 3.680 4.791 5.696
24 0.776 0.921 1.097 1.303 1.554 1.846 2.203 2.612 3.109 3.699 4.816 5.726
25 0.780 0.926 1.103 1.310 1.562 1.856 2.214 2.625 3.125 3.718 4.841 5.755
26 0.784 0.930 1.109 1.316 1.570 1.865 2.225 2.638 3.141 3.737 4.866 5.785
27 0.787 0.935 1.114 1.323 1.578 1.875 2.237 2.652 3.157 3.756 4.890 5.814
28 0.791 0.940 1.120 1.330 1.586 1.884 2.248 2.665 3.173 3.776 4.915 5.844
29 0.795 0.944 1.126 1.336 1.594 1.894 2.259 2.679 3.189 3.795 4.940 5.873
30 0.799 0.949 1.131 1.343 1.602 1.903 2.271 2.692 3.205 3.814 4.965 5.903
31 0.803 0.954 1.137 1.350 1.610 1.913 2.282 2.706 3.221 3.833 4.990 5.932
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Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-11
PLD inputs are from the 12 voltage monitors and four digital inputs. There are f our embedded progr ammab le timers
that interface with the PLD, along with an internal programmable oscillator.
The 12 independently programmable voltage monitors each have 384 programmable trip points over the range of
0.680V to 5.932V. Additionally, a 80mV ‘near-ground’ sensing threshold is selectab le which allo ws the voltage mon-
itors to determine if a monitored signal has dropped to ground-level. This feature is especially useful for deter min-
ing if a power supply’s output has completely tur ned off. Figure 2 shows a simplified schematic representation of
one of these monitors.
Figure 3-2. Voltage Monitors
Each monitor consists of four major subsystems. The core of the monitor is a precision voltage comparator. This
comparator outputs a HIGH signal to the PLD array if the voltage at its positive ter minal is greater than that at its
negative terminal, otherwise it outputs a LO W signal. A small amount of h ysteresis is pro vided b y the comparator to
reduce the effects of input noise.
The second subsystem is a programmable resistive divider that attenuates the input signal before it is fed into the
comparator. This feature is used to determine the coarse range in which the comparator should trip (e.g. 1.8V, 3.3V,
5V). Twelve possible ranges are available from the input divider network.
The third subsystem is a programmab le reference, which ma y be set to one of 32 possible values scaled in appro x-
imately 0.5% increments apart from each other, allowing for fine-tuning of the voltage monitor’s trip points. One
additional setting is provided to implement the 80mV ‘near-ground’ sense setting. This combination of coarse and
fine adjustment supports 384 possible trip-point voltages for a given monitor circuit, in addition to the ‘near-ground’
sense setting. Because each monitor’s reference and input divider settings are completely independent of those of
the other monitor circuits, the user can set any input monitor to any of the 385 available settings.
A comparator will turn on at the specified tr ip-point and turn off at the specified trip-point minus the hysteresis. The
hysteresis provided by the voltage monitor is a function of the input divider setting and is derived from the differ-
ence in voltage between the current setting and the one immediately below it. The following table lists the typical
hysteresis versus voltage monitor trip-point.
To PLD
Array
Programmable
Reference
(32 selections)
Monitor Voltage
VMON1..VMON12
Input
Attenuator
(12 taps)
Comparator
with
Hysteresis
DDigital
Filter
Q
250kHz
Clock
Sampling
Flip-flop
Digital
Filter
ON/OFF
OFF
ON
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Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-12
Table 3-2. Comparator Hysteresis vs. Setpoint
The f ourth subsystem in the ispPAC-PO WR1208P1’s input voltage monitor is a synchronizer latch and optional dig-
ital filter. The synchronizer flip-flop samples the comparator’s output state synchronously with the internal system
clock. Synchronous sampling effectively eliminates the possibility of race conditions occurr ing in any state-control-
lers implemented in the ispPAC-POWR1208P1’s internal PLD logic.
An optional digital filter is also provided f or each compar ator input f or the purpose of suppressing glitches and other
short transients. This filter is implemented using a saturating counter. When the comparator output is HIGH, the fil-
ter counts up to a maximum of ‘111’, and when the comparator output is LOW the filter counts down to a minimum
of ‘000’. When a ‘111’ count is reached, the output of the filter is set HIGH, and when the ‘000’ count is reached, the
output is set LOW. Because the filter is clocked at the same rate as the synchronizer, the combination of the two
imposes a dela y of 8 sampling periods, or 32 clock cycles (32µs at 1MHz). The digital filters may be enabled or dis-
abled individually on a channel-by-channel basis by the user.
PLD Architecture
The ispPAC-POWR1208P1 digital logic is composed of an internal PLD that is programmed to perform the
sequencing functions. The PLD architecture allows flexibility in designing various state machines and control logic
used for monitoring. The macrocell shown in Figure 3-3 is the hear t of the PLD. There are 16 macrocells that can
be used to control the functional states of the sequencer state machine or other control or monitoring logic. The
PLD AND array shown in Figure 3-4 has 36 inputs, and 81 product terms (PTs). The resources from the AND arr ay
feed the 16 macrocells. The resources within the macrocells share routing and contain a product-term allocation
array. The product term allocation arra y g reatly expands the PLD’s ability to implement complex logical functions b y
allowing logic to be shared between adjacent blocks and distributing the product terms to allow for wider decode
functions.
The basic macrocell has five product terms that f eed the OR gate and the flip-flop. The flip-flop in each macrocell is
independently configured. It can be programmed to function as a D-Type or T-Type flip-flop. Combinatorial functions
are realized b y bypassing the flip-flop. By having the polarity control XOR, the logic reduction can be best fit to min-
imize the number of product terms. The flip-flop’s clock is driven from a common clock that can be generated from
a pre-scaled, on-board clock source or from an external clock. The macrocell also supports asynchronous reset
and preset functions, derived from either product terms, the global reset input or the power-on reset signal.
Setpoint Range (V) Hysteresis (mV)Low Limit High Limit
5.017 5.932 30
4.221 4.99 25
3.241 3.833 19
2.724 3.221 16
2.289 2.706 14
1.931 2.282 12
1.618 1.913 10
1.363 1.61 8
1.142 1.35 7
0.962 1.137 6
0.808 0.954 5
0.68 0.803 4
80 mV 0 (disabled)
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Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-13
Figure 3-3. ispPAC-POWR1208P1 Macrocell Block Diagram
PT0
PT1
PT2
PT3
PT4
D/T Q
RPTo ORP
CLK
Clock
Polarity
Macrocell flip-flop provides
D, T, or combinatorial
output with polarity
Product T erm Allocation
Global Reset Power On Reset
Global Polarity Fuse for
Init Product Term
Block Init Product Term
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Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-14
Figure 3-4. PLD and Timer Functional Block Diagram
MC0
MC1
MC2
MC14
MC15
PT[0..4] 4
4
4
4
4
BLK Init
PT[5..9]
PT[10..14]
PT[70..74]
PT[75..79]
AND ARRAY
36 Inputs
81 Product Terms
Output
Routing
Pool
Routing
Pool
Timer 1
Synchronizer
+ Digital
Filters (12)
Timer 2
Timer 3
16 16
HVOUT1
HVOUT2
HVOUT3
HVOUT4
OUT5
OUT6
OUT7
OUT8
Timer 4
4
Clock Generation
POR/RESET
VMON[1..12]
IN[1..4]
4
12
16 Logic
Macrocells
12
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Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-15
Clock and Timer Systems
Figure 3-5 shows a block diagram of the ispPAC-POWR1208P1’s internal clock and timer systems. The PLD clock
can be programmed with eight different frequencies based on the internal oscillator frequency of 1MHz.
Figure 3-5. Clock and Timer Block
The internal oscillator r uns at a fixed frequency of 1 MHz. This signal is used as a source for the PLD clock pres-
caler, the timer clock prescaler, and also for synchronizing the comparator outputs and clocking the digital filters in
the voltage monitor circuits. Figure 5 shows a functional block diagram of the ispPAC-POWR1208P1’s internal
clock system. The ispPAC-POWR1208P1 can operate from either its own internal or an external supplied clock
source. When the device is configured to use the inter nal clock source (Schematically, INT/EXT select switch is in
upper position), the CLK pin operates as an output. The user may select either the 1MHz inter nal clock, or the out-
put of the PLD clock prescaler to be driven out of this pin (1MHz/Prescaler select switch). When the device is con-
figured to use the e xternal clock source (INT/EXT select s witch is in low er position), the CLK pin is configured as an
input, and the e xternally applied clock signal is routed to all prescalers, synchroniz ers , and other internal functions.
The ispPAC-POWR1208P1 provides prescalers to provide for flexibility in selecting the PLD clock and wide
dynamic range for the timers. The frequencies available for the PLD clock will be the external clock frequency
divided by the chosen prescaler value (listed in Table 3-3).
Internal
OSC
1MHz
Timer Prescaler
(Time Out Range)
PLD Clock
Prescaler
CLK
Timer1
Timer2
Timer3
Timer4
INT/EXT
Select 1MHz/Prescaler
Select
To
VMON
Samplers
and
Digital Filters
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Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-16
Table 3-3. PLD Clock Frequency (kHz) PLD Prescaler Divider1
Because the ispPAC-POWR1208P1’ s PLD arr ay is clock ed from a divided-do wn version of the device’s 1MHz main
clock, special considerations must be observed for asserting input data if it is to be reliably recognized by state
machines implemented using the device. Data presented to the IN1 through IN4 digital inputs must be asserted for
a minimum of at least one PLD clock period (4µs – 512µs depending on the PLD prescaler setting) to be recog-
nized. For data presented to the VMON inputs, this minimum assertion time may need to be increased to account
for the behavior of the VMON samplers and digital filters (when enabled).
The Timer Clock Pre-Scaler divides the internal 1MHz oscillator (or external clock, if selected) down before it gen-
erates the clock for the four programmable timers. The pre-scaler has eight different divider ratios, shown in
Table 3-4. Each divider ratio provides a range of intervals to which each of the four timers may be independently
programmed. Please note that since there is only one prescaler, all of the timer inter vals must lie within the range
associated with the selected prescaler value.
Table 3-4. Timer Values1
PLD Prescaler Divider PLD Clock Frequency (kHz)
4 250
8 125
16 62.5
32 31.3
64 15.6
128 7.8
256 3.9
512 2.0
1. Frequency values based on 1MHz clock
÷÷
÷÷ 16
62.5 kHz ÷÷
÷÷ 32
31.2 kHz ÷÷
÷÷ 64
15.6 kHz ÷÷
÷÷ 128
7.8 kHz ÷÷
÷÷ 256
3.9 kHz ÷÷
÷÷ 512
2.0 kHz ÷÷
÷÷ 1024
1.0 kHz ÷÷
÷÷ 2048
0.5 kHz
0.032 ms
0.064 ms 0.064 ms
0.128 ms 0.128 ms 0.128 ms
0.256 ms 0.256 ms 0.256 ms 0.256 ms
0.512 ms 0.512 ms 0.512 ms 0.512 ms 0.512 ms
1.024 ms 1.024 ms 1.024 ms 1.024 ms 1.024 ms 1.024 ms
2.048 ms 2.048ms 2.048ms 2.048ms 2.048ms 2.048ms 2.048ms
4.096 ms 4.096 ms 4.096 ms 4.096 ms 4.096 ms 4.096 ms 4.096 ms 4.096 ms
8.192 ms 8.192 ms 8.192 ms 8.192 ms 8.192 ms 8.192 ms 8.192 ms
16.384 ms 16.384 ms 16.384 ms 16.384 ms 16.384 ms 16.384 ms
32.768 ms 32.768 ms 32.768 ms 32.768 ms 32.768 ms
65.536 ms 65.536 ms 65.536 ms 65.536 ms
131.072 ms 131.072 ms 131.072 ms
262.144 ms 262.144 ms
524.288 ms
1. Timer values based on 1MHz clock.
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Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-17
For design entry, the user can select the source for the clock and the PAC-Designer software will calculate the
appropriate delays in an easy-to-select menu format.
The control inputs f or Timer1-Timer4 can be driven b y any of the 16 PLD macrocell outputs . The reset f or the timers
is a function of the Global Reset pin (RESET), a pow er-on reset or when the timer gate goes lo w. The wav eforms in
Figure 3-6 show the basic timer star t and reset functions. Timer and clock divider values are entered in dur ing the
design phase using PAC-Designer software, simple pull-down menus allow the user to select the clocking mode
and the values for the timers and the PLD clock.
Figure 3-6. Timer Waveforms
Note that if the clock module is configured as “slave” (i.e. the CLK is an input), the actual time-out of the f our timers
is determined by the external clock frequency.
Timer Period
Timer Gate
Timer Output
Timer Period
(From PLD)
(To PLD)
Start
Timer Timer
Expired Reset
Timer
ProgrammableTimer
Delay
Start
Timer Timer
Expired
ProgrammableTimer
Delay
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Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-18
Master-Slave and PLD Expansion Modes
To suppor t designs requiring more I/O or logic resources than those provided by the ispPAC-POWR1208P1, it is
possible to gang a number of devices together, or to add a CPLD to provide additional logic. Figure 3-7 shows an
example of slaving a CPLD and two ispPAC-POWR1208P1’s to a single master device
Figure 3-7. Example of ispPAC-POWR1208P1’s and CPLD in Expansion Mode
In this circuit a 1 MHz CLK output is broadcast from the master device to all of the slave devices. The PLD pres-
caler should be set identically f or both the master and sla ve ispPAC device to ensure synchronous operation. In the
case of the CPLD, some internal logic will need to be used to essentially replicate the function of the ispPAC
devices’ PLD prescaler to ensure that it also operates synchronously.
The POR (power-on reset) signal from the master device is broadcast to all of the slave devices, holding them in a
reset state until the master device’s power-on-reset sequence completes. Because each of the ispPAC slave
devices have their own power-on-reset circuitry, their signals are wire-OR’ed together and fed back into the master
device’s RESET. This causes all of the devices to remain in a reset state until all power-on-reset sequences have
been successfully completed.
While it is possible to also slave ispPAC-POWR1208 and ispPAC-POWR604 devices to an ispPAC-POWR1208P1,
the converse is not tr ue. This is because the ispPAC-POWR1208 and 604 devices operate from a 250kHz internal
clock, while the ispPA C-PO WR1208P1 requires a 1MHz clock to maintain proper internal operation. Table 3-5 sum-
marizes the requirements for slaving a device to the ispPAC-POWR1208P1.
ispPAC-
POWR1208P1
Master
ispPAC-
POWR1208P1
Slave
ispPAC-
POWR1208P1
Slave
V+ V+
POR
POR
POR
CLK
CLK
CLK CLOCK Clock
Divider
RESET
RESET
RESET
RESET
Expansion
PLD
Wired
‘OR’
Connection
RPU RPU
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Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-19
Table 3-5. ispPAC-POWR1208P1 Expansion Requirements
Note that because different slave devices impose different requirements for master clock output frequency, there
are limitations on what types of slave devices may be operated synchronously from a single master. For example, it
is not generally possib le to slav e both ispPA C-PO WR1208P1’s and ispPAC-PO WR1208’s (or PO WR604’s) together
to a single ispPAC-POWR1208P1.
Output Configuration Modes
The output pins for the ispPAC-POWR1208P1 device are programmable for different functional modes. The four
outputs HVOUT1-HVOUT4, can be used as FET gate drivers or be programmed as open-drain digital outputs.
Figure 3-8 explains the details of the gate driver mode.
Figure 3-8. Basic Function Diagram for an Output in High-Voltage MOSFET Gate Driver Mode
Figure 3-8 shows an output programmed for gate driver mode. In this mode the output is a current source that is
programmable between 0.5µA to 50µA. The maximum voltage that the output level at the pin will rise is also pro-
grammable. The levels required depend on the gate-to-source threshold of the FET and the supply voltage. The
maximum level needs to be sufficient to bias the gate-to-source threshold on and also accommodate the load volt-
age at the FET’s source, since the source pin of the FET is tied to the supply of the target board. When the HVOUT
pin is sourcing current, charging a FET gate, the current is programmable between 0.5µA and 50µA. When the
driver is turned to the off state, the driver will sink current to ground through the 8kΩ resistor.
Slave Device Slave Configuration Master Configuration
ispPAC-POWR1208P1 External Clock Mode Select 1MHz Clock Output
ispPAC-POWR1208
ispPAC-POWR604 External Clock Mode Select PLD Prescaler Output
CPLD or FPGA Clock Prescaler implemented in logic Select 1MHz Clock Output
No Clock Prescaler Select PLD Prescaler output
ISource
(0.5-50uA)
≈ 8kΩ
VPP
(8-12V)
Digital In
From Sequence
Controller
Output to
IC Pin
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Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-20
Predicting MOSFET T urn-on Time
Because the ispPAC-POWR1208P1’s MOSFET output drivers source a precise and well-defined output current, it
becomes possible to predict MOSFET gate rise times if one knows the value of the load capacitance presented by
the MOSFET being driven. The other method is by relating the total gate charge to the gate-to-source voltage.
Figure 3-9. MOSFET Gate Charge vs. Gate-Source Voltage
Using this method, it becomes straightforward to estimate the gate rise time for a given charging current. As an
example a MOSFET’s source voltage (VS) will be 3.3V when the device is fully switched on, while the gate voltage
(VG) will be 10V in this condition. The device’s gate-to-source voltage (VGS) will therefore be 6.7V. Reading across
and down the plot of Figure 3-9, a VGS of 6.7V corresponds to ~40 nC of gate charge (QG). Because charge is
equal to the product of current (I) and time (tCHARGE-TIME) when current is constant, gate charging time can be
expressed as:
(1)
(2)
For this example, let us assume a charging current of 10.9µA. Gate charging time is given by:
(3)
Validation of this result can be seen in the scope plot shown in Figure 3-10. The top set of traces shows gate rise
times for various (5.5µA to 50.3µA) gate drive currents. The trace labeled 10.9µA shows gate voltage VG rising
from 0V to 10V in slightly ov er 3 milliseconds , which agrees to within 25% of our predicted v alue , well within the lim-
its of device-to-device variation.
VGS, Gate-to-source Voltage (V)
QG, Total Gate Charge (nC)
0204060
0
3
6
6.7
9
=
idQ
dt
=
tCHARGE-TIME QG
I
= = 3.7 x 10-3s
tCHARGE-TIME 40 x 10-9C
10.9 x 10-6A
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Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-21
Figure 3-10. Gate and Source Voltage Responses for a 3.3V Supply
MOSFET gate capacitance ranges from hundreds to thousands of picoFarads. Refer to the MOSFET manufac-
turer’s data sheet for values of Cgs (Capacitance gate-to-source). If slower ramps are required, an additional exter-
nal low leakage capacitor (e .g. a polycarbonate or other poly type capacitor) can be added from the gate to ground.
As a good design practice, it is recommended that a series resistor of 10-100Ω be placed in the gate drive signal
near the FET gate pin to reduce the possibility that the FET may self-oscillate.
Charge Pump
F our internal charge pumps are provided to fully support e xternal N-channel FET devices . No external components
are required f or the charge pumps. The output voltage is prog r ammable from 8 to 12V in 0.5V steps. The user must
select a high voltage limit no greater than 7.5V above VDD (the software assists this process). This voltage is con-
trolled with an on-chip feedback loop, and is independent of the actual supply voltage.
Programmable Output Voltage Levels for HVOUT1- HVOUT4
There are eight selectable steps for the output voltage of the FET drivers when in FET driv er mode . The output pins
HVOUT1-4 are current source outputs, each with a programmable current. The current is programmable in 32 dif-
ferent steps ranging from 0.5µA to 50µA. The voltage that the pin is capable of dr iving to is listed in Table 3-6. For
each supply range, the charge-pump range will be set by the software.
Table 3-6. HVOUT Gate Driver Voltage Range
VDD = 3.3V VDD = 5V
88
8.5 8.5
99
9.5 9.5
10 10
10.5
11
12
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Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-22
IEEE Standard 1149.1 Interface
Communication with the ispPAC-POWR1208P1 is facilitated via an IEEE 1149.1 test access port (TAP). It is used
by the ispPAC-POWR1208P1 as a serial programming interface, and not for boundar y scan test purposes. There
are no boundar y scan logic registers in the ispPAC-POWR1208P1 architecture. This does not prevent the ispPAC-
PO WR1208P1 from functioning correctly, how e v er, when placed in a v alid serial chain with other IEEE 1149.1 com-
pliant devices. Since the ispPAC-POWR1208P1 is used to powerup other devices, it should be programmed in a
separate chain from PLDs, FPGAs or other JTAG devices.
A brief description of the ispPAC-POWR1208P1 serial interf ace follows. For complete details of the ref erence spec-
ification, refer to the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std 1149.1-
1990 (which now includes IEEE Std 1149.1a-1993).
Overview
An IEEE 1149.1 test access port (TAP) pro vides the control interface for serially accessing the digital I/O of the isp-
PAC-POWR1208P1. The TAP controller is a state machine driven with mode and clock inputs. Under the correct
protocol, instructions are shifted into an instruction register, which then determines subsequent data input, data
output, and related operations. Device programming is perfor med by addressing various registers, shifting data in,
and then executing the respective program instruction. The programming instructions transfer the data into inter nal
E2CMOS memory. It is these non-volatile memory cells that determine the configuration of the ispPAC-
POWR1208P1. By cycling the TAP controller through the necessary states, data can also be shifted out of the var-
ious registers to verify the current ispPAC-POWR1208P1 configuration. Instructions exist to access all data regis-
ters and perform internal control operations.
For compatibility between compliant devices, two data registers are mandated by the IEEE 1149.1 specification.
Other registers are functionally specified, but inclusion is strictly optional. Finally, there are provisions for optional
user data registers that are defined by the manufacturer. The two required registers are the bypass and boundary-
scan registers. For ispPAC-POWR1208P1, the bypass register is a 1-bit shift register that provides a short path
through the device when boundary testing or other operations are not being performed. The ispPAC-
POWR1208P1, as mentioned earlier has no boundary-scan logic and therefore no boundary scan register. All
instructions relating to boundar y scan operations place the ispPAC-POWR1208P1 in the BYPASS mode to main-
tain compliance with the specification.
The optional identification (IDCODE) register described in IEEE 1149.1 is also included in the ispPAC-
PO WR1208P1. Six additional user data registers are included in the TAP of the ispPAC-POWR1208P1 as sho wn in
Figure 3-11. Most of these additional registers are used to program and verify the analog configuration (CFG) and
PLD bits. A status register is also provided to read the status of the twelve analog comparators.
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Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-23
Figure 3-11. TAP Registers
TAP Controller Specifics
The TAP is controlled b y the Test Clock (TCK) and Test Mode Select (TMS) inputs. These inputs determine whether
an Instruction Register or Data Register operation is performed. Driven by the TCK input, the TAP consists of a
small 16-state controller. In a given state , the controller responds according to the level on the TMS input as shown
in Figure 3-12. Test Data In (TDI) and TMS are latched on the rising edge of TCK, with Test Data Out (TDO) becom-
ing valid on the falling edge of TCK. There are six steady states within the controller : Test-Logic-Reset, Run-Test/
Idle, Shift-Data-Register, Pause-Data-Register, Shift-Instruction-Register, and Pause-Instruction-Register. But
there is only one steady state for the condition when TMS is set high: the Test-Logic-Reset state. This allows a
reset of the test logic within five TCKs or less by keeping the TMS input high. Test-Logic-Reset is the power-on
default state.
When the correct logic sequence is applied to the TMS and TCK inputs, the TAP will exit the Test-Logic-Reset state
and move to the desired state. The next state after Test-Logic-Reset is Run-Test/Idle. Until a data or instruction
scan is performed, no action will occur in Run-Test/Idle (steady state = idle). After Run-Test/Idle, either a data or
instruction scan is performed. The states of the Data and Instruction Register blocks are identical to each other dif-
fering only in their entr y points. When either block is entered, the first action is a capture operation. For the Data
Registers, the Capture-DR state is ver y simple; it captures (parallel loads) data onto the selected ser ial data path
(previously chosen with the appropriate instruction). For the Instruction Register, the Capture-IR state will always
load the IDCODE instruction. It will always enable the ID Register for readout if no other instr uction is loaded prior
to a Shift-DR operation. This, in conjunction with mandated bit codes, allows a “blind” interrogation of any device in
a compliant IEEE 1149.1 serial chain.
STATUS REGISTER (12 bits)
IDCODE REGISTER (32 bits)
UES REGISTER (16 bits)
CFG REGISTER (41 bits)
CFG ADDRESS REGISTER (4 bits)
PLD DATA REGISTER (81 bits)
PLD ADDRESS REGISTER (75 bits)
BYPASS REGISTER (1 bit)
TEST ACCESS PORT
(TAP) LOGIC OUTPUT
LATCH
MULTIPLEXER
ANALOG
CONFIGURATION
E2 NON-VOLATILE
MEMORY
(164 bits)
PLD
AND / ARCH
E2 NON-VOLATILE
MEMORY
(6075 bits)
INSTRUCTION REGISTER (6 bits)
ANALOG COMPARATOR ARRAY (12 bits)
TDI TCK TMS TDO
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Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-24
Figure 3-12. TAP States
From the Capture state, the TAP transitions to either the Shift or Exit1 state. Normally the Shift state follows the
Capture state so that test data or status information can be shifted out or new data shifted in. Following the Shift
state, the TAP either returns to the Run-Test/Idle state via the Exit1 and Update states or enters the Pause state via
Exit1. The Pause state is used to temporarily suspend the shifting of data through either the Data or Instruction
Register while an external operation is performed. From the Pause state, shifting can resume by re-entering the
Shift state via the Exit2 state or be terminated by entering the Run-Test/Idle state via the Exit2 and Update states.
If the proper instruction is shifted in during a Shift-IR operation, the next entr y into Run-Test/Idle initiates the test
mode (steady state = test). This is when the device is actually prog rammed, er ased or v erified. All other instructions
are executed in the Update state.
Test Instructions
Like data registers, the IEEE 1149.1 standard also mandates the inclusion of certain instructions. It outlines the
function of three required and six optional instructions. Any additional instructions are left exclusively for the manu-
f acturer to determine. The instruction word length is not mandated other than to be a minimum of two bits, with only
the BYPASS and EXTEST instruction code patterns being specifically called out (all ones and all zeroes respec-
tively). The ispPAC-POWR1208P1 contains the required minimum instruction set as well as one from the optional
instruction set. In addition, there are several proprietary instructions that allow the device to be configured, verified,
and monitored. For ispPAC-POWR1208P1, the instr uction word length is 6-bits. All ispPAC-POWR1208P1 instruc-
tions available to users are shown in Table 3-7.
1
0
0
1
1
0
0
1
0
0
0
0
1
0
1
1
0101
1
1
0
1
0
0
111
0
0
1
Update-IR
Exit2-IR
Pause-IR
Exit1-IR
Shift-IR
Capture-IR
Select-IR-Scan
Update-DR
Exit2-DR
Pause-DR
Exit1-DR
Shift-DR
Capture-DR
Select-DR-Scan
Run-Test/Idle
Test-Logic-Reset
Note: The value shown adjacent to each state transition represents the signal present
at TMS at the time of a rising edge at TCK.
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Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-25
Table 3-7. ispPAC-POWR1208P1 TAP Instruction Table
BYPASS is one of the three required instructions. It selects the Bypass Register to be connected between TDI and
TDO and allows serial data to be transferred through the device without affecting the operation of the ispPAC-
POWR1208P1. The IEEE 1149.1 standard defines the bit code of this instruction to be all ones (111111).
The required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI
and TDO. The ispPAC-POWR1208P1 has no boundary scan register, so for compatibility it defaults to the BYPASS
mode whenever this instruction is received. The bit code for this instruction is defined by Lattice as shown in
Table 3-7.
The EXTEST (external test) instr uction is required and would normally place the device into an external boundary
test mode while also enabling the boundary scan register to be connected between TDI and TDO. Again, since the
ispPAC-POWR1208P1 has no boundary scan logic, the device is put in the BYPASS mode to ensure specification
compatibility. The bit code of this instruction is defined by the 1149.1 standard to be all zeros (000000).
The optional IDCODE (identification code) instruction is incorporated in the ispPAC-POWR1208P1 and leaves it in
its functional mode when executed. It selects the Device Identification Register to be connected between TDI and
TDO. The Identification Register is a 32-bit shift register containing information regarding the IC manufacturer,
Instruction Code Description
EXTEST 000000 External Test. Defaults to BYPASS.
ADDPLD1000001 Address PLD address register (75 bits).
DATAPLD1000010 Address PLD column data register (81 bits).
ERASEAND1, 2 000011 Bulk Erase AND array.
ERASEARCH1, 2 000100 Bulk Erase Architect array.
PROGPLD1, 2 000101 Program PLD column data register into E2.
PROGESF1, 2 000110 Program the Electronic Security Fuse bit.
BYPASS 000111 Bypass (connect TDI to TDO).
READPLD1001000 Reads PLD column data from E2 to the register (81 bits).
DISCHARGE1001001 F ast VPP discharge.
ADDCFG1001010 Address CFG array address (4 bits).
DATACFG1001011 Address CFG data (41 bits).
ERASECFG1, 2 001100 Bulk Erase CFG data.
PROGCFG1, 2 001101 Program CFG data register into E2.
READCFG1001110 Read CFG column data from E2 to the register (41 bits).
CFGBE1, 2 010110 Bulk Erase all E2 memory (CFG, PLD, USE, and ESF).
SAFESTATE1010111 Digital outputs hiZ (FET pulled L)
PROGRAMEN1011000 Enable program mode (SAFESTATE IO)
IDCODE 011001 Address Identification Code data register (32 bits).
PROGRAMDIS 011010 Disable Program mode (normal IO)
ADDSTATUS 011011 Address STATUS register (12 bits).
SAMPLE 011100 Sample/Preload. Default to Bypass.
ERASEUES1, 2 011101 Bulk Erase UES.
SHIFTUES 011110 Reads UES data from E2 and selects the UES register (16 bits).
PROGUES1, 2 011111 Program UES data register into E2.
BYPASS 1xxxxx Bypass (connect TDI to TDO).
1. When these instructions are executed, the outputs are placed in the same mode as the instruction SAFESTATE (as
described later) to prevent invalid and potentially destructive power supply sequencing.
2. Instructions that erase or program the E2CMOS memory must be executed only when the supply to the device is
maintained at 3.0V to 5.5V.
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Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-26
device type and version code (Figure 3-13). Access to the Identification Register is immediately available, via a
TAP data scan operation, after power-up of the device, or by issuing a Test-Logic-Reset instruction. The bit code for
this instruction is defined by Lattice as shown in Table 3-7.
Figure 3-13. ID Code
ispPAC-POWR1208P1 Specific Instructions
There are 21 unique instructions specified by Lattice for the ispPAC-POWR1208P1. These instructions are pr ima-
rily used to interface to the various user registers and the E2CMOS non-v olatile memory. Additional instructions are
used to control or monitor other features of the device. A br ief descr iption of each unique instr uction is provided in
detail below, and the bit codes are found in Table 3-7.
ADDPLD – This instruction is used to set the address of the PLD AND/ARCH arrays for subsequent program or
read operations. This instruction also forces the outputs into the SAFESTATE.
DATAPLD – This instruction is used to shift PLD data into the register prior to programming or reading. This
instruction also forces the outputs into the SAFESTATE.
ERASEAND – This instr uction will bulk erase the PLD AND array. The action occurs at the second rising edge of
TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAMEN instruction).
This instruction also forces the outputs into the SAFESTATE.
ERASEARCH – This instruction will bulk erase the PLD ARCH array. The action occurs at the second r ising edge
of TCK in Run-Test-Idle JTAG state . The de vice m ust already be in progr amming mode (PR OGRAMEN instruction).
This instruction also forces the outputs into the SAFESTATE.
PROGPLD – This instr uction programs the selected PLD AND/ARCH array column. The specific column is prese-
lected by using ADDPLD instruction. The programming occurs at the second rising edge of the TCK in Run-Test-
Idle JTAG state. The device must already be in programming mode (PROGRAMEN instruction). This instruction
also forces the outputs into the SAFESTATE.
PROGESF – This instruction is used to program the electronic security fuse (ESF) bit. Programming the ESF bit
protects proprietary designs from being read out. The programming occurs at the second rising edge of the TCK in
Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAMEN instruction). This
instruction also forces the outputs into the SAFESTATE.
READPLD – This instruction is used to read the content of the selected PLD AND/ARCH array column. This spe-
cific column is preselected by using ADDPLD instruction. This instruction also forces the outputs into the SAF-
ESTATE.
DISCHARGE – This instruction is used to discharge the internal programming supply v oltage after an erase or pro-
gramming cycle and prepares ispPAC-POWR1208P1 for a read cycle. This instruction also forces the outputs into
the SAFESTATE.
XXXX / 0000 0001 0100 0010 / 0000 0100 001 / 1
MSB LSB
Version
(4 bits)
E2 Configured
Part Number
(16 bits)
0142h = ispPAC-POWR1208P1 JEDEC Manufacturer
Identity Code for
Lattice Semiconductor
(11 bits) Constant 1
(1 bit)
per 1149.1-1990
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Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-27
ADDCFG – This instruction is used to set the address of the CFG arra y for subsequent program or read operations .
This instruction also forces the outputs into the SAFESTATE.
DATACFG – This instruction is used to shift data into the CFG register prior to programming or reading. This
instruction also forces the outputs into the SAFESTATE.
ERASECFG – This instruction will bulk erase the CFG array. The action occurs at the second rising edge of TCK in
Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAMEN instruction). This
instruction also forces the outputs into the SAFESTATE.
PROGCFG – This instruction programs the selected CFG array column. This specific column is preselected by
using ADDCFG instruction. The programming occurs at the second rising edge of the TCK in Run-Test-Idle JTAG
state. The device must already be in programming mode (PROGRAMEN instruction). This instruction also forces
the outputs into the SAFESTATE.
READCFG – This instruction is used to read the content of the selected CFG array column. This specific column is
preselected by using ADDCFG instruction. This instruction also forces the outputs into the SAFESTATE.
CFGBE – This instruction will bulk erase all E2CMOS bits (CFG, PLD, UES, and ESF) in the ispPAC-
POWR1208P1. The device must already be in programming mode (PROGRAMEN instruction). This instruction
also forces the outputs into the SAFESTATE.
SAFESTATE – This instr uction tur ns off all of the open-drain output transistors. Pins that are programmed as FET
drivers will be placed in the active low state. This instruction is effective after Update-Instruction-Register JTAG
state.
PROGRAMEN – This instruction enables the programming mode of the ispPAC-POWR1208P1. This instruction
also forces the outputs into the SAFESTATE.
IDCODE – This instruction connects the output of the Identification Code Data Shift (IDCODE) Register to TDO
(Figure 3-14), to support reading out the identification code.
Figure 3-14. IDCODE Register
PROGRAMDIS – This instruction disables the programming mode of the ispPAC-POWR1208P1. The Test-Logic-
Reset JTAG state can also be used to cancel the programming mode of the ispPAC-POWR1208P1.
ADDSTATUS – This instr uction is used to both connect the status register to TDO (Figure 3-15) and latch the 12
voltage monitor (comparator outputs) into the status register. Latching of the 12 comparator outputs into the status
register occurs during Capture-Data-Register JTAG state.
Figure 3-15. Status Register
ERASEUES – This instr uction will bulk erase the content of the UES E2CMOS memor y. The device must already
be in programming mode (PR OGRAMEN instruction). This instruction also forces the outputs into the SAFESTATE.
SHIFTUES – This instruction both reads the E2CMOS bits into the UES register and places the UES register
between the TDI and TDO pins (as shown in Figure U), to suppor t programming or reading of the user electronic
signature bits.
TDO
Bit
0
Bit
1
Bit
2
Bit
3
Bit
4
Bit
27
Bit
28
Bit
29
Bit
30
Bit
31
TDO
VMON
12
VMON
11
VMON
10
VMON
9
VMON
8
VMON
7
VMON
6
VMON
5
VMON
4
VMON
3
VMON
2
VMON
1
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Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-28
Figure 3-16. UES Register
PROGUES – This instruction will program the content of the UES Register into the UES E2CMOS memory. The
device must already be in programming mode (PROGRAMEN instruction). This instruction also forces the outputs
into the SAFESTATE.
Notes:
In all of the descriptions above, SAFESTATE refers both to the instruction and the state of the digital output pins, in
which the open-drains are tri-stated and the FET drivers are pulled low.
Before any of the above programming instructions are executed, the respective E2CMOS bits need to be erased
using the corresponding erase instruction.
Application Example
The ispPAC-POWR1208P1 device has 12 comparators to monitor various power supply levels. The comparators
each have a programmable trip point that is progr ammed by the user at design time. The output of the comparators
are latched and optionally filtered bef ore being fed into the PLD logic array to drive the state machine logic or mon-
itor logic. The comparator’s filtered outputs COMP1...COMP8 are also routed to external pins to be monitored
directly or can be used to drive additional control logic if expansion is required. The comparator outputs are open-
drain type output buffers and require a pull up resistor to drive a logic high. All 12 comparators have hysteresis, the
hysteresis is dependent on the voltage trip point scale that is set, it ranges from 4mV for a 0.680V trip point to
30mV f or a 5.93V trip point. The comparators can be set with a trip point from 0.68V to 5.93V, with 384 diff erent val-
ues. The application diagram shows a set-up that can monitor and control multiple power supplies. The ispPAC-
POWR1208P1 device controls FET switches to ramp the supplies at different slew rates and time delays. The digi-
tal outputs and inputs are also used to interface with the board that is being powered up.
To reduce the possibility of RF oscillation, a gate resistor (RG) is often inserted in series with the gate of the MOS-
FET power switch. This resistor should be placed physically close to the MOSFET gate terminal, and connected by
as shor t a PCB trace as is feasible. An appropr iate value for these gate resistors is highly dependent on both the
characteristics of the MOSFET being used and the circumstances of the application, but will often be in the range
of 10Ω to 100Ω.
TDO
Bit
0
Bit
1
Bit
2
Bit
3
Bit
4
Bit
5
Bit
6
Bit
7
Bit
8
Bit
9
Bit
10
Bit
11
Bit
12
Bit
13
Bit
14
Bit
15
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Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-29
Figure 3-17. Typical Application Example: ispPAC-POWR1208P1 Driving [4] FET Switches [4] Digital OE/EN
Lines
Primary +
Gnd
+
-
+5V
+3.3V
+2.5V
+1.0V +1V
ispPAC-POWR1208P1
Power Sequence
Controller
HVOUT1
0.1uF10uF
HVOUT2
HVOUT3
HVOUT4
OUT5
OUT6
OUT7
OUT8
DC/DC Supply
or Regulator
OE/EN
Digital
Logic
EN
Circuits
RESET
Comp2
Comp4
VMON12
12 Analog Inputs
IN1
IN2
VDD
IN3
IN4
VMON1
VMON2
VMON3
VMON4
VMON5
VMON6
VMON7
VMON8
VMON9
VMON10
VMON11
CLK
Comp3
Comp1
Comp6
Comp8
Comp7
Comp5
+2.5V
Circuits
+3.3V
Circuits
+5V
Circuits
OE/EN
Digital
Logic
EN
Primary +
Gnd
+
-
Primary +
Gnd
+
-
DC/DC
Supply
Primary +
Gnd
+
-
DC/DC Supply
or Regulator
POR
DC/DC
Supply
DC/DC
Supply
DC/DC
RG
Supply
VDD VDDINP
0.1uF
CREF
3.3V
3.3V
RG
RG
RG
ALL DEVICES
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Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-30
Software-Based Design Environment
Design Entry Software
All functions within the ispPAC-POWR1208P1 are controlled through a Windows-based software development tool
called PAC-Designer. PAC-Designer is an easy-to-use graphical user interface (Figure 3-18) that allows the user to
set up the ispPAC-POWR1208P1 to perform given functions, such as timed sequences for power supply and mon-
itor trip points for the voltage monitor inputs. The software tool gives the user control over how the device driv es the
outputs and the functional configurations for all I/O pins. User-friendly dialog boxes are provided to set and edit all
of the analog features of the ispPAC-POWR1208P1. An extension to the schematic screen is the LogiBuilder
design environment (Figure 3-19) that is used to enter and edit control sequences. Again, user-friendly dialog
boxes are provided in this window to help the designer to quickly implement sequences that take advantage of the
powerful built-in PLD. Once the configurations are chosen and the sequence has been described by the utilities,
the de vice is ready to program. A standard JTA G interface is used to program the E2CMOS memory. PAC-Designer
software supports downloading the device through the PC’s parallel port. The ispPAC-POWR1208P1 can be repro-
grammed using the software and ispDOWNLOAD® Cable assembly, to adjust for variations in supply timing,
sequencing or scaling of voltage monitor inputs.
Figure 3-18. PAC-Designer Schematic Screen
The user interface (Figure 3-18) provides access to various internal function blocks within the ispPAC-
POWR1208P1 device.
Analog Inputs: Accesses the programmable threshold trip-points for the comparators and pin naming conven-
tions.
Digital Inputs: Digital input naming configurations and digital inputs feed into the internal PLD for the sequence
controller.
Sequence Controller: Incorporates a PLD architecture for designing the state machine to control the order and
functions associated with the user-defined power-up sequence/monitor and control.
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Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-31
FET Drivers: Allows the user to define r amp rates by controlling the current driven to the gate of the external FETs.
Maximum voltage levels and pin names are also set using this functional block. The four FET driver outputs
HVOUT1-4 can also be configured as open-drain digital logic outputs.
Logic Outputs: These pins are configured and assigned in the Logic Output Functional Block. The four digital out-
puts are open-drain and require a pull-up resistor.
Internal Clock: The inter nal clock configuration and clock prescaler values are user-programmable, as well as the
four internal programmable timers used for sequence delay.
User Electronic Signature (UES): Stores 16 bits of ID or board information in non-volatile E2CMOS.
Figure 3-19. PAC-Designer LogiBuilder Screen
Programming of the ispPAC-POWR1208P1 is accomplished using the Lattice ispDOWNLOAD Cable. This cable
connects to the parallel port of a PC and is driven through the PAC-Designer software. The software controls the
JTAG TAP interface and shifts in the JEDEC data bits that set the configuration of all the analog and digital circuitry
that the user has defined during the design process.
Power to the de vice m ust be set at 3.0V to 5.5V during programming, once the progr amming steps ha v e been com-
pleted, the power supply to the ispPAC-POWR1208P1 can be set from 2.7V to 5.5V. Once programmed, the on-
chip non-volatile E2CMOS bits hold the entire design configuration for the digital circuits, analog circuits and trip
points for comparators etc. Upon powering the device up, the non-volatile E2CMOS bits control the device configu-
ration. If design changes need to be made such as adjusting comparator trip points or changes to the digital logic
functions, the device is simply re-programmed using the ispDOWNLOAD Cable.
Design Simulation Capability
Support for functional simulation of the control sequence is provided using the software tools Waveform Editor and
Wavefor m Viewer. Both applications are spawned from the LogiBuilder environment of PAC-Designer. The simula-
tion engine combines the design file with a stimulus file (edited by the user with Waveform Editor) to produce an
output file that can be observed with the Waveform Viewer (Figure 3-20).
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Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-32
Figure 3-20. PAC-Designer Functional Simulation Screen
In-System Programming
The ispPAC-POWR1208P1 is an in-system programmable device. This is accomplished by integrating all E2CMOS
configuration memory and control logic on-chip. Programming is perfor med through a 4-wire, IEEE 1149.1 compli-
ant serial JTAG interface. Once a device is programmed, all configuration infor mation is stored on-chip, in non-vol-
atile E2CMOS memory cells. The specifics of the IEEE 1149.1 serial interface and all ispPAC-POWR1208P1
instructions are described in the JTAG interface section of this data sheet.
User Electronic Signature
The User Electronic Signature (UES), allows the designer to include identification bits or serial numbers inside the
de vice, stored in E2CMOS memory. The ispPAC-POWR1208P1 contains 16 UES bits that can be configured by the
user to store unique data such as ID codes, revision numbers or inventory control codes.
Electronic Security
An Electronic Security Fuse (ESF) bit is provided to pre v ent unauthorized readout of the E 2CMOS bit pattern. Once
programmed, this cell prevents fur ther access to the functional user bits in the device. This cell can only be erased
by reprogramming the device; this way the original configuration cannot be examined or copied once programmed.
Usage of this feature is optional.
Production Programming Support
Once a final configuration is determined, an ASCII format JEDEC file can be created using the PAC-Designer soft-
ware . Devices can then be ordered through the usual supply channels with the user’s specific configuration already
preloaded into the devices. By vir tue of its standard interface, compatibility is maintained with existing production
programming equipment, giving customers a wide degree of freedom and flexibility in production planning.
Evaluation Fixture
The ispPAC-PO WR1208P1 Design Kit includes an engineering prototype board that can be connected to the paral-
lel port of a PC using a Lattice ispDOWNLOAD cable. It demonstrates proper layout techniques for the ispPAC-
PO WR1208P1 and can be used in real time to chec k circuit oper ation as part of the design process. LEDs are sup-
plied to debug designs without involving test equipment. Input and output connections as well as a “breadboard”
circuit area are provided to speed deb ugging of the circuit. The board includes an area for prototyping other circuits
and interconnect areas with pads for pins or cables. The user can check out designs on the hardware and make
necessary changes to the design for the function required.
Part Number Description
PAC-SYSPOWR1208P1 Complete system kit, evaluation board, ispDOWNLOAD Cable and software
PACPOWR1208P1-EV Evaluation board only, with components, fully assembled
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Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-33
Package Diagrams
44-Pin TQFP (Dimensions in Millimeters)
0.10 C
BASE METAL
5. THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOTTOM
4. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION.
DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H.
ALLOWABLE MOLD PROTRUSION IS 0.254 MM ON D1 AND E1
2. ALL DIMENSIONS ARE IN MILLIMETERS.
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982.
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.10 AND 0.25 MM FROM THE LEAD TIP.
7. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE
TO THE LOWEST POINT ON THE PACKAGE BODY.
EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8.
DIMENSIONS.
OF THE PACKAGE BY 0.15 MM.
6. SECTION B-B:
3.
SECTION B-B
b1
c 1
c
0.45
0.40
0.16
0.20
c1 0.09 0.13
c
b1
0.09
0.30
b
e
0.30
0.35
0.15
0.37
0.80 BSC
MAX.
1.60
0.15
1.45
0.75
E 12.00 BSC
0.45L
N
E1
0.60
44
10.00 BSC
D
D1
A2 1.35
12.00 BSC
10.00 BSC
1.40
DETAIL 'A'
A1
A1
A
0.05
-
SYMBOL MIN.
-
-
NOM.
1.00 REF.
0.20 MIN.
B
L
0-7∞
SEATING PLANE
LEAD FINISH
0.20
b
b
A-BC
MD
SIDE VIEW
e
TOP VIEW
8D3
A
3
D
GAUGE PLANE
DH A-B4X 0.20 BOTTOM VIEW
A2
C
A
SEE DETAIL 'A'
H
B
3
E
B
E1
D1
0.25
A-B0.20 C44XD
NOTES:
PIN 1 INDICATOR
ALL DEVICES
DISCONTINUED
USE ispPAC-POWR1014/A
FOR NEW DESIGNS
Lattice Semiconductor ispPAC-POWR1208P1 Data Sheet
3-34
Part Number Description
ispPAC-POWR1208P1 Ordering Information
Industrial
Lead-Free Industrial
Package Options
Revision History
Part Number Package Pins
ispPAC-POWR1208P1-01T44I TQFP 44
Part Number Package Pins
ispPA C-POWR1208P1-01TN44I Lead-free TQFP 44
Date Version Change Summary
February 2005 01.0 Initial release.
Device Number
ispPAC-POWR1208P1 - 01XX44X
Operating Temperature Range
I = Industrial (-40°C to +85°C)
Package
T = 44-pin TQFP
TN = Lead-Free 44-pin TQFP*
*Contact factory for package availability.
Performance Grade
01 = Standard
Device Family
OUT5
OUT6
OUT7
OUT8
VMON1
VMON2
VMON3
VMON4
VMON5
VMON6
VMON7
VMON8
VMON9
COMP1
COMP2
COMP4
COMP5
COMP6
COMP7
COMP8
ispPAC-POWR1208P1
44-pin TQFP
1
44
43
42
41
40
39
38
37
35
34
33
2
3
4
5
6
7
8
9
10
11 12 13 14 15 16 17 18 19 20 21 22
23
24
25
26
27
28
29
30
31
32
36
COMP3
POR
VMON10
VMON11
VMON12
TDI
TDO
TCK
TMS
TRST
CLK
CREF
GND
HVOUT1
HVOUT2
HVOUT3
VDD
IN1
IN2
IN3
IN4
VDDINP
HVOUT4
RESET
ALL DEVICES
DISCONTINUED
USE ispPAC-POWR1014/A
FOR NEW DESIGNS
