PTN3361BBS - NXP Semiconductors

1. General description

The PTN3361B is a high-speed level shifter device which converts four lanes of low-swing

AC-coupled differential input signals to DVI v1.0 and HDMI v1.3a compliant open-drain

current-steering differential output signals, up to 1.65 Gbit/s per lane. Each of these lanes

provides a level-shifting differential buffer to translate from low-swing AC-coupled

differential signaling on the source side, to TMDS-type DC-coupled differential

current-mode signaling terminated into 50 Ω to 3.3 V on the sink side. Additionally, the

PTN3361B provides a single-ended active buffer for voltage translation of the HPD signal

from 5 V on the sink side to 3.3 V on the source side and provides a channel with active

buffering and level shifting of the DDC channel (consisting of a clock and a data line)

between 3.3 V source-side and 5 V sink-side. The DDC channel is implemented using

active I2C-bus buffer technology providing capacitive isolation, redriving and level shifting

as well as disablement (isolation between source and sink) of the clock and data lines.

The low-swing AC-coupled differential input signals to the PTN3361B typically come from

a display source with multi-mode I/O, which supports multiple display standards, e.g.,

DisplayPort, HDMI and DVI. While the input differential signals are conﬁgured to carry DVI

or HDMI coded data, they do not comply with the electrical requirements of the DVI v1.0 or

HDMI v1.3a speciﬁcation. By using PTN3361B, chip set vendors are able to implement

such reconﬁgurable I/Os on multi-mode display source devices, allowing the support of

multiple display standards while keeping the number of chip set I/O pins low. See

Figure 1.

The PTN3361B main high-speed differential lanes feature low-swing self-biasing

differential inputs which are compliant to the electrical speciﬁcations of

DisplayPort

Standard v1.1

and/or

PCI Express Standard v1.1

, and open-drain current-steering

differential outputs compliant to DVI v1.0 and HDMI v1.3a electrical speciﬁcations. The

I2C-bus channel actively buffers as well as level-translates the DDC signals for optimal

capacitive isolation. Its I2C-bus control block also provides for optional software HDMI

dongle detect by issuing a predetermined code sequence upon a read command to an

I2C-bus speciﬁed address. The PTN3361B also supports power-saving modes in order to

minimize current consumption when no display is active or connected.

The PTN3361B is a fully featured HDMI as well as DVI level shifter. It is functionally

comparable to PTN3360B but provides additional features supporting HDMI dongle

detection and active DDC buffering. For HDMI dongles, support of HDMI dongle detection

via the DDC channel is mandatory, hence HDMI dongle applications should enable this

feature for correct operation in accordance with DisplayPort interoperability guidelines.

PTN3361B is powered from a single 3.3 V power supply consuming a small amount of

power (90 mW typ.) and is offered in a 48-terminal HVQFN48 package.

PTN3361B

HDMI/DVI level shifter with dongle detect support and active

DDC buffer

Rev. 02 — 7 October 2009 Product data sheet

Product data sheet Rev. 02 — 7 October 2009 2 of 29

NXP Semiconductors PTN3361B

HDMI/DVI level shifter with dongle detect and DDC buffer

Remark: TMDS clock and data lanes can be assigned arbitrarily and interchangeably to D[4:1].

Fig 1. Typical application system diagram

002aae053

OUT_D1−

OUT_D1+

IN_D1−

IN_D1+

HPD_SOURCE HPD_SINK

SCL_SINK

SDA_SINK

DDC_EN

(0 V to 3.3 V)

SCL_SOURCE

SDA_SOURCE

OUT_D2−

OUT_D2+

IN_D2−

IN_D2+

OUT_D3−

OUT_D3+

IN_D3−

IN_D3+

OUT_D4−

OUT_D4+

IN_D4−

IN_D4+

PTN3361B

OE_N

DVI/HDMI CONNECTOR

5 V

0 V to 5 V0 V to 3.3 V

3.3 V

AC-coupled

differential pair

clock

CLOCK LANE

DATA LANE

AC-coupled

differential pair

TMDS data

AC-coupled

differential pair

TMDS data

AC-coupled

differential pair

TMDS data

TMDS

clock

pattern

MULTI-MODE DISPLAY SOURCE

TMDS

coded

data

TMDS

coded

data

TMDS

coded

data

PCIe PHY ELECTRICAL

CONFIGURATION

DDC I/O

(I2C-bus)

PCIe

output buffer

reconfigurable I/Os

PCIe

output buffer

PCIe

output buffer

PCIe

output buffer

Product data sheet Rev. 02 — 7 October 2009 3 of 29

NXP Semiconductors PTN3361B

HDMI/DVI level shifter with dongle detect and DDC buffer

2. Features

2.1 High-speed TMDS level shifting

nConverts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and

HDMI v1.3a compliant open-drain current-steering differential output signals

nPin-programmable pre-emphasis feature

nTMDS level shifting operation up to 1.65 Gbit/s per lane (165 MHz character clock)

nTMDS level shifting operation up to 2.25 Gbit/s per lane (225 MHz character clock)

using pre-emphasis feature

nIntegrated 50 Ω termination resistors for self-biasing differential inputs

nBack-current safe outputs to disallow current when device power is off and monitor is

nDisable feature to turn off TMDS inputs and outputs and to enter low-power state

2.2 DDC level shifting

nIntegrated active DDC buffering and level shifting (3.3 V source to 5 V sink side)

nRise time accelerator on sink-side DDC ports

n0 Hz to 400 kHz I2C-bus clock frequency

nBack-power safe sink-side terminals to disallow backdrive current when power is off or

when DDC is not enabled

2.3 HDMI dongle detect support

nIncorporates I2C slave ROM

nResponds to DDC read to address 81h with predetermined byte sequence

nFeature enabled by pin DDET (must be enabled for correct operation in accordance

with DisplayPort interoperability guideline

2.4 HPD level shifting

nHPD non-inverting level shift from 0 V on the sink side to 0 V on the source side, or

from 5 V on the sink side to 3.3 V on the source side

nIntegrated 200 kΩ pull-down resistor on HPD sink input guarantees ‘input LOW’ when

no display is plugged in

nBack-power safe design on HPD_SINK to disallow backdrive current when power is off

2.5 General

nPower supply 3.3 V ±10 %

nESD resilience to 7 kV HBM, 1 kV CDM

nSupport for optional HDMI dongle detection via DDC/I2C-bus channel

nPower-saving modes (using output enable)

nBack-current-safe design on all sink-side main link, DDC and HPD terminals

nTransparent operation: no re-timing or software conﬁguration required

Product data sheet Rev. 02 — 7 October 2009 4 of 29

NXP Semiconductors PTN3361B

HDMI/DVI level shifter with dongle detect and DDC buffer

3. Applications

nDisplayPort to HDMI adapters (must enable DDET)

nDisplayPort to DVI adapters required to drive long cables

4. Ordering information

Table 1. Ordering information

Type number Package

Name Description Version

PTN3361BBS HVQFN48 plastic thermal enhanced very thin quad ﬂat package; no leads; 48 terminals;

body 7 ×7×0.85 mm SOT619-1

Product data sheet Rev. 02 — 7 October 2009 5 of 29

NXP Semiconductors PTN3361B

HDMI/DVI level shifter with dongle detect and DDC buffer

5. Functional diagram

Fig 2. Functional diagram of PTN3361B

002aae054

OUT_D1−

OUT_D1+

input bias

50 Ω50 Ω

IN_D1−

IN_D1+

HPD level shifter

HPD_SOURCE

(0 V to 3.3 V) HPD_SINK

(0 V to 5 V)

200 kΩ

SCL_SINK

SDA_SINK

DDC_EN (0 V to 3.3 V)

SCL_SOURCE

SDA_SOURCE

OUT_D2−

OUT_D2+

IN_D2−

IN_D2+

OUT_D3−

OUT_D3+

IN_D3−

IN_D3+

OUT_D4−

OUT_D4+

IN_D4−

IN_D4+

PTN3361B

OE_N

enable

input bias

50 Ω50 Ω

input bias

50 Ω50 Ω

input bias

50 Ω50 Ω

enable

DDC BUFFER

AND

LEVEL SHIFTER

I2C-BUS

SLAVE

ROM

DDET

Product data sheet Rev. 02 — 7 October 2009 6 of 29

NXP Semiconductors PTN3361B

HDMI/DVI level shifter with dongle detect and DDC buffer

6. Pinning information

6.1 Pinning

HVQFN48 package supply ground is connected to both GND pins and exposed center pad. GND

pins must be connected to supply ground for proper device operation. For enhanced thermal,

electrical, and board level performance, the exposed pad needs to be soldered to the board using

a corresponding thermal pad on the board and for proper heat conduction through the board,

thermal vias need to be incorporated in the PCB in the thermal pad region.

Fig 3. Pin conﬁguration for HVQFN48

OUT_D4+

OUT_D4−

VDD

OUT_D3+

OUT_D3−

GND

OUT_D2+

OUT_D2−

VDD

OUT_D1+

OUT_D1−

GND

OE_N

VDD

GND

SCL_SINK

SDA_SINK

HPD_SINK

GND

DDC_EN

VDD

n.c.

GND

VDD

GND

PES1

SCL_SOURCE

SDA_SOURCE

HPD_SOURCE

REXT

GND

DDET

PES0

VDD

GND

IN_D4+

IN_D4−

VDD

IN_D3+

IN_D3−

GND

IN_D2+

IN_D2−

VDD

IN_D1+

IN_D1−

GND

002aae055

PTN3361BBS

12 25

11 26

10 27

9 28

8 29

7 30

6 31

5 32

4 33

3 34

2 35

1 36

terminal 1

index area

Transparent top view

Product data sheet Rev. 02 — 7 October 2009 7 of 29

NXP Semiconductors PTN3361B

HDMI/DVI level shifter with dongle detect and DDC buffer

6.2 Pin description

Table 2. Pin description

Symbol Pin Type Description

OE_N, IN_Dx and OUT_Dx signals

OE_N 25 3.3 V low-voltage

CMOS single-ended

input

Output Enable and power saving function for

high-speed differential level shifter path.

When OE_N = HIGH:

IN_Dx termination = high-impedance

OUT_Dx outputs = high-impedance; zero

output current

When OE_N = LOW:

IN_Dx termination = 50 Ω

OUT_Dx outputs = active

IN_D4+ 48 Self-biasing

differential input Low-swing differential input from display source

with PCI Express electrical signalling.

IN_D4+ makes a differential pair with IN_D4−.

The input to this pin must be AC coupled

externally.

IN_D4−47 Self-biasing

differential input Low-swing differential input from display source

with PCI Express electrical signalling.

IN_D4−makes a differential pair with IN_D4+.

The input to this pin must be AC coupled

externally.

IN_D3+ 45 Self-biasing

differential input Low-swing differential input from display source

with PCI Express electrical signalling.

IN_D3+ makes a differential pair with IN_D3−.

The input to this pin must be AC coupled

externally.

IN_D3−44 Self-biasing

differential input Low-swing differential input from display source

with PCI Express electrical signalling.

IN_D3−makes a differential pair with IN_D3+.

The input to this pin must be AC coupled

externally.

IN_D2+ 42 Self-biasing

differential input Low-swing differential input from display source

with PCI Express electrical signalling.

IN_D2+ makes a differential pair with IN_D2−.

The input to this pin must be AC coupled

externally.

IN_D2−41 Self-biasing

differential input Low-swing differential input from display source

with PCI Express electrical signalling.

IN_D2−makes a differential pair with IN_D2+.

The input to this pin must be AC coupled

externally.

IN_D1+ 39 Self-biasing

differential input Low-swing differential input from display source

with PCI Express electrical signalling.

IN_D1+ makes a differential pair with IN_D1−.

The input to this pin must be AC coupled

externally.

Product data sheet Rev. 02 — 7 October 2009 8 of 29

NXP Semiconductors PTN3361B

HDMI/DVI level shifter with dongle detect and DDC buffer

IN_D1−38 Self-biasing

differential input Low-swing differential input from display source

with PCI Express electrical signalling.

IN_D1−makes a differential pair with IN_D1+.

The input to this pin must be AC coupled

externally.

OUT_D4+ 13 TMDS differential

output HDMIcompliantTMDSoutput.OUT_D4+makes

a differential pair with OUT_D4−. OUT_D4+ is in

phase with IN_D4+.

OUT_D4−14 TMDS differential

output HDMI compliant TMDS output. OUT_D4−makes

a differential pair with OUT_D4+. OUT_D4−is in

phase with IN_D4−.

OUT_D3+ 16 TMDS differential

output HDMIcompliantTMDSoutput.OUT_D3+makes

a differential pair with OUT_D3−. OUT_D3+ is in

phase with IN_D3+.

OUT_D3−17 TMDS differential

output HDMI compliant TMDS output. OUT_D3−makes

a differential pair with OUT_D3+. OUT_D3−is in

phase with IN_D3−.

OUT_D2+ 19 TMDS differential

output HDMIcompliantTMDSoutput.OUT_D2+makes

a differential pair with OUT_D2−. OUT_D2+ is in

phase with IN_D2+.

OUT_D2−20 TMDS differential

output HDMI compliant TMDS output. OUT_D2−makes

a differential pair with OUT_D2+. OUT_D2−is in

phase with IN_D2−.

OUT_D1+ 22 TMDS differential

output HDMIcompliantTMDSoutput.OUT_D1+makes

a differential pair with OUT_D1−. OUT_D1+ is in

phase with IN_D1+.

OUT_D1−23 TMDS differential

output HDMI compliant TMDS output. OUT_D1−makes

a differential pair with OUT_D1+. OUT_D1−is in

phase with IN_D1−.

HPD and DDC signals

HPD_SINK 30 5 V CMOS

single-ended input 0 V to 5 V (nominal) input signal. This signal

comes from the DVI or HDMI sink. A HIGH value

indicates that the sink is connected; a LOW

value indicates that the sink is disconnected.

HPD_SINK is pulled down by an integrated

200 kΩ pull-down resistor.

HPD_SOURCE 7 3.3 V CMOS

single-ended output 0 V to 3.3 V (nominal) output signal. This is

level-shifted version of the HPD_SINK signal.

SCL_SOURCE 9 single-ended 3.3 V

open-drain DDC I/O 3.3 V source-side DDC clock I/O. Pulled up by

external termination to 3.3 V.

SDA_SOURCE 8 single-ended 3.3 V

open-drain DDC I/O 3.3 V source-side DDC data I/O. Pulled up by

external termination to 3.3 V.

SCL_SINK 28 single-ended 5 V

open-drain DDC I/O 5 V sink-side DDC clock I/O. Pulled up by

external termination to 5 V. Provides rise time

acceleration for LOW-to-HIGH transitions.

SDA_SINK 29 single-ended 5 V

open-drain DDC I/O 5 V sink-side DDC data I/O. Pulled up by

external termination to 5 V. Provides rise time

acceleration for LOW-to-HIGH transitions.

Table 2. Pin description

…continued

Symbol Pin Type Description

Product data sheet Rev. 02 — 7 October 2009 9 of 29

NXP Semiconductors PTN3361B

HDMI/DVI level shifter with dongle detect and DDC buffer

[1] HVQFN48 package supply ground is connected to both GND pins and exposed center pad. GND pins must

be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board

level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad

on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the

PCB in the thermal pad region.

DDC_EN 32 3.3 V CMOS input Enables the DDC buffer and level shifter.

When DDC_EN = LOW, buffer/level shifter is

disabled.

When DDC_EN = HIGH, buffer and level shifter

are enabled.

Supply and ground

VDD 2, 11,

15, 21,

26, 33,

40, 46

3.3 V DC supply Supply voltage; 3.3 V ±10 %.

VCC -

GND[1] 1, 5,

12, 18,

24, 27,

31, 36,

37, 43

ground Supply ground. All GND pins must be connected

to ground for proper operation.

Feature control signals

REXT 6 analog I/O Current sense port used to provide an accurate

current reference for the differential outputs

OUT_Dx. For best output voltage swing

accuracy, use of a 10 kΩresistor (1 % tolerance)

from this terminal to GND is recommended. May

also be left open-circuit or tied to either VDD or

GND. See Section 7.2 for details.

DDET 4 3.3 V input Dongle detect enable input. When HIGH, the

dongle detect function via I2C is active. When

used in an HDMI dongle, this pin must be tied

HIGH for correct operation in accordance with

DisplayPort interoperability guidelines. When

used in a DVI dongle, this pin must be tied LOW.

When LOW, the dongle detect function will not

respond to an I2C-bus command. Must be tied to

GND or VDD either directly or via a resistor. Note

that this pin may not be left open-circuit.

PES1 10 3.3 V CMOS input Programming pins to activate the pre-emphasis

feature of the TMDS differential outputs. See

Section 7.3 for details. Must be tied either to

GND or VDD either directly or via a resistor. To

disable pre-emphasis, connect both to GND

(PES[1:0] = 00b). PES[1:0] = 11b is reserved for

testing purposes and should not be used in

normal application. Note that these pins may not

be left open-circuit.

PES0 3 3.3 V CMOS input

Miscellaneous

n.c. 34, 35 no connection

to the die Not connected. May be left open-circuit or tied to

GND or VDD either directly or via a resistor.

Table 2. Pin description

…continued

Symbol Pin Type Description

Product data sheet Rev. 02 — 7 October 2009 10 of 29

NXP Semiconductors PTN3361B

HDMI/DVI level shifter with dongle detect and DDC buffer

7. Functional description

Refer to Figure 2 “Functional diagram of PTN3361B”.

The PTN3361B level shifts four lanes of low-swing AC-coupled differential input signals to

DVI and HDMI compliant open-drain current-steering differential output signals, up to

1.65 Gbit/s per lane. Speed of operation and cable length drive may be extended (by

using the programmable pre-emphasis feature) to up to 2.25 Gbit/s per lane. It has

integrated 50 Ω termination resistors for AC-coupled differential input signals. An enable

signal OE_N can be used to turn off the TMDS inputs and outputs, thereby minimizing

power consumption. The TMDS outputs are back-power safe to disallow current ﬂow from

a powered sink while the PTN3361B is unpowered.

The PTN3361B's DDC channel provides active level shifting and buffering, allowing 3.3 V

source-side termination and 5 V sink-side termination. The sink-side DDC ports are

equipped with a rise time accelerator enabling drive of long cables or high bus

capacitance. This enables the system designer to isolate bus capacitance to meet HDMI

DDC version 1.3a distance speciﬁcation. Furthermore, the DDC channel is augmented

with an I2C-bus slave ROM device that provides optional HDMI dongle detect response,

which can be enabled by dongle detect signal DDET. The PTN3361B offers back-power

safe sink-side I/Os to disallow backdrive current from the DDC clock and data lines when

power is off or when DDC is not enabled. An enable signal DCC_EN enables the DDC

level shifter block.

Remark: When used in an HDMI dongle, the DDET function must be enabled for correct

operation in accordance with DisplayPort interoperability guidelines. When used in a DVI

dongle, the DDET function must be disabled.

The PTN3361B also provides voltage translation for the Hot Plug Detect (HPD) signal

from 0 V to 5 V on the sink side to 0 V to 3.3 V on the source side.

The PTN3361B does not re-time any data. It contains no state machines except for the

DDC/I2C-bus block. No inputs or outputs of the device are latched or clocked. Because

the PTN3361B acts as a transparent level shifter, no reset is required.

7.1 Enable and disable features

PTN3361B offers different ways to enable or disable functionality, using the Output Enable

(OE_N) and DDC Enable (DDC_EN) inputs. Whenever the PTN3361B is disabled, the

device will be in Standby mode and power consumption will be minimal; otherwise the

PTN3361B will be in Active mode and power consumption will be nominal. These two

inputs each affect the operation of PTN3361B differently: OE_N affects only the TMDS

channels, and DDC_EN affects only the DDC channel. HPD_SINK does not affect either

of the channels. The following sections and truth table describe their detailed operation.

7.1.1 Hot plug detect

The HPD channel of PTN3361B functions as a level-shifting buffer to pass the HPD logic

signal from the display sink device (via input HPD_SINK) on to the display source device

(via output HPD_SOURCE).

The output logic state of HPD_SOURCE output always follows the logic state of input

HPD_SINK, regardless of whether the device is in Active or Standby mode.

Product data sheet Rev. 02 — 7 October 2009 11 of 29

NXP Semiconductors PTN3361B

HDMI/DVI level shifter with dongle detect and DDC buffer

7.1.2 Output Enable function (OE_N)

When input OE_N is asserted (active LOW), the IN_Dx and OUT_Dx signals are fully

functional. Input termination resistors are enabled and the internal bias circuits are turned

on.

When OE_N is de-asserted (inactive HIGH), the OUT_Dx outputs are in a

high-impedance state and drive zero output current. The IN_Dx input buffers are disabled

and IN_Dx termination is disabled. Power consumption is minimized.

Remark: Note that OE_N has no inﬂuence on the HPD_SINK input, HPD_SOURCE

output, or the SCL and SDA level shifters. OE_N only affects the high-speed TMDS

channel.

7.1.3 DDC channel enable function (DDC_EN)

The DDC_EN pin is active HIGH and can be used to isolate a badly behaved slave. When

DDC_EN is LOW, the DDC channel is turned off. The DDC_EN input should never change

state during an I2C-bus operation. Note that disabling DDC_EN during a bus operation will

hang the bus, while enabling DDC_EN during bus trafﬁc would corrupt the I2C-bus

operation. Hence, DDC_EN should only be toggled while the bus is idle. (See I2C-bus

speciﬁcation).

Product data sheet Rev. 02 — 7 October 2009 12 of 29

NXP Semiconductors PTN3361B

HDMI/DVI level shifter with dongle detect and DDC buffer

7.1.4 Enable/disable truth table

[1] A HIGH level on input OE_N disables only the TMDS channels.

[2] A LOW level on input DDC_EN disables only the DDC channel.

[3] OUT_Dx channels ‘enabled’ means outputs OUT_Dx toggling in accordance with IN_Dx differential input voltage switching.

[4] DDC channel ‘enabled’ means SDA_SINK is connected to SDA_SOURCE and SCL_SINK is connected to SCL_SOURCE.

[5] The HPD_SOURCE output logic state always follows the HPD_SINK input logic state.

Table 3. HPD_SINK, OE_N and DDC_EN enabling truth table

Inputs Channels Mode

HPD_SINK OE_N

[1] DDC_EN

[2] IN_Dx OUT_Dx[3] DDC[4] HPD_SOURCE[5]

LOW LOW LOW 50 Ωtermination

to VRX(bias)

enabled high-impedance LOW Active;DDC

disabled

LOW LOW HIGH 50 Ωtermination

to VRX(bias)

enabled SDA_SINK

connected to

SDA_SOURCE

and SCL_SINK

connected to

SCL_SOURCE

LOW Active;DDC

enabled

LOW HIGH LOW high-impedance high-impedance;

zero output current high-impedance LOW Standby

LOW HIGH HIGH high-impedance high-impedance;

zero output current SDA_SINK

connected to

SDA_SOURCE

and SCL_SINK

connected to

SCL_SOURCE

LOW Standby;

DDC

enabled

HIGH LOW LOW 50 Ωtermination

to VRX(bias)

enabled high-impedance HIGH Active;DDC

disabled

HIGH LOW HIGH 50 Ωtermination

to VRX(bias)

enabled SDA_SINK

connected to

SDA_SOURCE

and SCL_SINK

connected to

SCL_SOURCE

HIGH Active;DDC

enabled

HIGH HIGH LOW high-impedance high-impedance;

zero output current high-impedance HIGH Standby

HIGH HIGH HIGH high-impedance high-impedance;

zero output current SDA_SINK

connected to

SDA_SOURCE

and SCL_SINK

connected to

SCL_SOURCE

HIGH Standby;

DDC

enabled

Product data sheet Rev. 02 — 7 October 2009 13 of 29

NXP Semiconductors PTN3361B

HDMI/DVI level shifter with dongle detect and DDC buffer

7.2 Analog current reference

The REXT pin (pin 6) is an analog current sense port used to provide an accurate current

reference for the differential outputs OUT_Dx. For best output voltage swing accuracy, use

of a 10 kΩ resistor (1 % tolerance) connected between this terminal and GND is

recommended.

If an external 10 kΩ±1 % resistor is not used, this pin can be left open-circuit, or

connected to GND or VDD, either directly (0 Ω) or using pull-up or pull-down resistors of

value less than 10 kΩ. In any of these cases, the output will function normally but at

reduced accuracy over voltage and temperature of the following parameters: output levels

(VOL), differential output voltage swing, and rise and fall time accuracy.

7.3 Programmable pre-emphasis

PTN3361B includes an optional programmable pre-emphasis feature, allowing adaptor or

motherboard PCB designers to extend speed performance or support longer cable drive.

The pre-emphasis feature, when enabled, adds a selectable amount of pre-emphasis to

each bit transition by injecting a momentary current pulse (typically 200 ps to 400 ps long)

to help overcome cable or trace losses.

Pre-emphasis is not needed for normal HDMI operation at speeds below 1.65 Gbit/s and

is not required to meet eye diagram compliance. At the user's discretion, it can be enabled

in order to provide additional signal boost in difﬁcult or lossy signaling environments such

as long cables or lossy media.

It should be noted that by enabling pre-emphasis, in addition to the AC effect of the

pre-emphasis pulse on the signal transition, also a constant DC current is added in order

to provide the necessary headroom, which will affect VOH and VOL static levels. This

should be taken into account when designing for HDMI or DVI single-ended (DC) voltage

compliance. For full HDMI or DVI compliance in normal applications, the default mode

(pre-emphasis off) is recommended.

The pre-emphasis feature is programmed by means of two CMOS input pins, PES1 and

PES0, according to Table 4:

[1] Should not be used in normal application.

7.4 Backdrive current protection

The PTN3361B is designed for backdrive prevention on all sink-side TMDS outputs,

sink-side DDC I/Os and the HPD_SINK input. This supports user scenarios where the

display is connected and powered, but the PTN3361B is unpowered. In these cases, the

PTN3361B will sink no more than a negligible amount of leakage current, and will block

the display (sink) termination network from driving the power supply of the PTN3361B or

that of the inactive DVI or HDMI source.

Table 4. PTN3361B pre-emphasis logic table

PES1 (pin 10) PES0 (pin 3) Level

0 0 0 dB (default

0 1 3.5 dB (150 %)

1 0 6 dB (200 %)

1 1 Test mode[1]

Product data sheet Rev. 02 — 7 October 2009 14 of 29

NXP Semiconductors PTN3361B

HDMI/DVI level shifter with dongle detect and DDC buffer

7.5 Active DDC buffer with rise time accelerator

The PTN3361B DDC channel, besides providing 3.3 V to 5 V level shifting, includes active

buffering and rise time acceleration which allows up to 18 meters bus extension for

reliable DDC applications. While retaining all the operating modes and features of the

I2C-bus system during the level shifts, it permits extension of the I2C-bus by providing

bidirectional buffering for both the data (SDA) and the clock (SCL) line as well as the

rise time accelerator on the sink-side port (SCL_SINK and SDA_SINK) enabling the bus

to drive a load up to 1400 pF or distance of 18 m on port A, and 400 pF on the

source-side port (SCL_SOURCE and SCA_SOURCE). Using the PTN3361B for DVI or

HDMI level shifting enables the system designer to isolate bus capacitance to meet HDMI

DDC version 1.3 distance speciﬁcation. The SDA and SCL pins are overvoltage tolerant

and are high-impedance when the PTN3361B is unpowered or when DDC_EN is LOW.

PTN3361B has rise time accelerators on the sink-side port (SCL_SINK and SDA_SINK)

only. During positive bus transitions on the sink-side port, a current source is switched on

to quickly slew the SCL_SINK and SDA_SINK lines HIGH once the 5 V DDC bus VIL

threshold level of around 1.5 V is exceeded, and turns off as the 5 V DDC bus VIH

threshold voltage of approximately 3.5 V is approached.

7.6 I2C-bus based HDMI dongle detection

The PTN3361B includes an on-board I2C-bus slave ROM which provides a means to

detect the presence of an HDMI dongle by the system through the DDC channel,

accessible via ports SDA_SOURCE and SCL_SOURCE. This allows system vendors to

detect HDMI dongle presence through the already available DDC/I2C-bus port using a

predetermined bus sequence. Please see Section 8 for more information.

For the I2C-bus HDMI Dongle Detect function to be active, input pin DDET (dongle detect)

should be tied HIGH. When DDET is LOW, the PTN3361B will not respond to an I2C-bus

command. When used in an HDMI dongle, the DDET function must be enabled for correct

operation in accordance with DisplayPort interoperability guidelines. When used in a DVI

dongle, the DDET function must be disabled.

The HDMI dongle detection is accomplished by accessing the PTN3361B on-board

I2C-bus slave ROM using a simple sequential I2C-bus Read operation as described below.

7.6.1 Slave address

R = 1; W = 0

Fig 4. PTN3361B slave address

002aad340

1 0 0 0 0 0 0 R/W

slave address

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Product data sheet Rev. 02 — 7 October 2009 15 of 29

NXP Semiconductors PTN3361B

HDMI/DVI level shifter with dongle detect and DDC buffer

7.6.2 Read operation

The slave device address of PTN3361B is 80h. PTN3361B will respond to a Read

command to slave address 81h (PTN3361B will respond with an ACK to a Write

command to address 80h). Following the Read command, the PTN3361B will respond

with the contents of its internal ROM, as a sequence of 16 bytes, for as long as the master

continues to issue clock edges with an acknowledge after each byte. The 16-byte

sequence represents the ‘DP-HDMI ADAPTOR<EOT>’ symbol converted to ASCII and is

documented in Table 5.

The PTN3361B auto-increments its internal ROM address pointer (0h through Fh) as long

as it continues to receive clock edges from the master with an acknowledge after each

byte. If the master continues to issue clock edges past the 16th byte, the PTN3361B will

respond with a data byte of FFh. If the master does not acknowledge a received byte, the

PTN3361B internal address pointer will be reset to 0 and a new Read sequence should be

started by the master. Access to the 16-byte is by sequential read only as described

above; there is no random-access possible to any speciﬁc byte in the ROM.

Remark: If the slave does not acknowledge the above transaction sequence, the entire

sequence should be retried by the source.

Table 5. DisplayPort - HDMI Adaptor Detection ROM content

Internal pointer

offset (hex) 0123456789ABCDEF

Data (hex) 44 50 2D 48 44 4D 49 20 41 44 41 50 54 4F 52 04

Table 6. HDMI dongle detect transaction sequence outline

Phase I2C transaction Transmitting Bit Status

7 6 5 4 3 2 1 R/W Master Slave

1 START master optional -

2 Write command master 1000000 0 optional -

3 Acknowledge slave - mandatory

4 Word address offset master word address offset data byte optional -

5 Acknowledge slave - mandatory

6 STOP master optional -

7 START master mandatory -

8 Read command master 1000000 1mandatory -

9 Acknowledge slave - mandatory

10 Read data slave data byte at offset 0 - mandatory

11 Acknowledge master mandatory -

12 Read data slave data byte at offset 1 - mandatory

13 : : - -

:: : - -

40 Read data slave data byte at offset 15 - mandatory

41 Not Acknowledge master mandatory -

42 STOP master mandatory -

Product data sheet Rev. 02 — 7 October 2009 16 of 29

NXP Semiconductors PTN3361B

HDMI/DVI level shifter with dongle detect and DDC buffer

7.7 Characteristics of the I2C-bus

The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

7.7.1 Bit transfer

One data bit is transferred during each clock phase. The data on the SDA line must

remain stable during the HIGH period of the clock pulse as changes in the data line at this

time will be interpreted as control signals (see Figure 5).

7.7.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line, while the clock is HIGH is deﬁned as the START condition (S). A

LOW-to-HIGH transition of the data line while the clock is HIGH is deﬁned as the STOP

condition (P). See Figure 6.

7.7.3 System conﬁguration

An I2C-bus device generating a message is a ‘transmitter’, a device receiving is the

‘receiver’. The device that controls the message is the ‘master’ and the devices which are

controlled by the master are the ‘slaves’. See Figure 7.

Fig 5. Bit transfer

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 6. Deﬁnition of START and STOP conditions.

mba608

SDA

SCL P

STOP condition

START condition

Product data sheet Rev. 02 — 7 October 2009 17 of 29

NXP Semiconductors PTN3361B

HDMI/DVI level shifter with dongle detect and DDC buffer

7.7.4 Acknowledge

The number of data bytes transferred between the START and the STOP conditions from

transmitter to receiver is not limited. Each byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,

whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of

each byte. Also, a master must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter. The device that acknowledges has to

pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable

LOW during the HIGH period of the acknowledge related clock pulse, set-up and hold

times must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating as

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Fig 7. System conﬁguration

002aaa381

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER/

RECEIVER

SDA

SCL

Fig 8. Acknowledgement on the I2C-bus

002aaa987

START

condition

9821

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from master

Product data sheet Rev. 02 — 7 October 2009 18 of 29

NXP Semiconductors PTN3361B

HDMI/DVI level shifter with dongle detect and DDC buffer

8. Application design-in information

8.1 Dongle or cable adaptor detect discovery mechanism

The PTN3361B supports the source-side dongle detect discovery mechanism described

VESA DisplayPort Interoperability Guideline Version 1.1

When a source-side cable adaptor is plugged into a multi-mode source device that

supports multiple standards such as DisplayPort, DVI and HDMI, a discovery mechanism

is needed for the multi-mode source to conﬁgure itself for outputting DisplayPort, DVI or

HDMI compliant signals through the dongle or cable adaptor. The discovery mechanism

ensures that a multi-mode source device only sends either DVI or HDMI signals when a

valid DVI or HDMI cable adaptor is present.

The V

ESA Interoperability Guideline

recommends that a multi-mode source to power up

with both DDC and AUX CH disabled. After initialization, the source device can use a

variety of mechanisms to decide whether a dongle or cable adaptor is present by

detecting pin 13 on the DisplayPort connector. Depending on the voltage level detected at

pin 13, the source conﬁgures itself either:

•as a DVI or HDMI source (see below paragraph for detection between DVI and HDMI),

and enables DDC, while keeping AUX CH disabled, or

•as a DisplayPort source and enables AUX CH, while keeping DDC disabled.

The monitoring of the voltage level on pin 13 by a multi-mode source device is optional. A

multi-mode source may also e.g. attempt an AUX CH read transaction and, if the

transaction fails, a DDC transaction to discover the presence/absence of a cable adaptor.

Furthermore, a source that supports both DVI and HDMI can discover whether a DVI or

HDMI dongle or cable adaptor is present by using a variety of discovery procedures. One

possible method is to check the voltage level of pin 14 of the DisplayPort connector.

Pin 14 also carries CEC signal used for HDMI. Please note that other HDMI devices on

the CEC line may be momentarily pulling down pin 14 as a part of CEC protocol.

The

VESA Interoperability Guideline

recommends that a multi-mode source should

distinguish a source-side HDMI cable adaptor from a DVI cable adaptor by checking the

DDC buffer ID as described in Section 7.6 “I2C-bus based HDMI dongle detection”. While

it is optional for a multi-mode source to use the I2C-bus based HDMI dongle detection

mechanism, it is mandatory for HDMI dongle or cable adaptor to respond to the I2C-bus

read command described in Section 7.7. The PTN3361B provides an integrated I2C-bus

slave ROM to support this mandatory HDMI dongle detect mechanism for HDMI dongles.

For a DisplayPort-to-HDMI source-side dongle or cable adaptor, DDET must be tied HIGH

to enable the I2C-bus based HDMI dongle detection response function of PTN3361B. For

a DisplayPort-to-DVI sink-side dongle or cable adaptor, DDET must be tied LOW to

disable the function.

Product data sheet Rev. 02 — 7 October 2009 19 of 29

NXP Semiconductors PTN3361B

HDMI/DVI level shifter with dongle detect and DDC buffer

9. Limiting values

[1] Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model -

Component level; Electrostatic Discharge Association, Rome, NY, USA.

[2] Charged-Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing,

Charged-Device Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.

10. Recommended operating conditions

[1] Input signals to these pins must be AC-coupled.

[2] Operation without external reference resistor is possible but will result in reduced output voltage swing

accuracy. For details, see Section 7.2.

10.1 Current consumption

Table 7. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage −0.3 +4.6 V

VIinput voltage 3.3 V CMOS inputs −0.3 VDD + 0.5 V

5.0 V CMOS inputs −0.3 6.0 V

Tstg storage temperature −65 +150 °C

VESD electrostatic discharge

voltage HBM [1] - 7000 V

CDM [2] - 1000 V

Table 8. Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

VDD supply voltage 3.0 3.3 3.6 V

VIinput voltage 3.3 V CMOS inputs 0 - 3.6 V

5.0 V CMOS inputs 0 - 5.5 V

VI(AV) average input voltage IN_Dn+, IN_Dn− inputs [1] -0 -V

Rref(ext) external reference

resistance connected between pin

REXT (pin 6) and GND [2] -10± 1% - kΩ

Tamb ambient temperature operating in free air −40 - +85 °C

Table 9. Current consumption

Symbol Parameter Conditions Min Typ Max Unit

IDD supply current OE_N = 1 and DDC_EN = 0;

Standby mode --2mA

OE_N = 0; Active mode - 27 50 mA

Product data sheet Rev. 02 — 7 October 2009 20 of 29

NXP Semiconductors PTN3361B

HDMI/DVI level shifter with dongle detect and DDC buffer

11. Characteristics

11.1 Differential inputs

[1] UI (unit interval) = tbit (bit time).

[2] UI is determined by the display mode. Nominal bit rate ranges from 250 Mbit/s to 1.65 Gbit/s per lane. Nominal UI at

1.65 Gbit/s = 606 ps.

[3] VRX_DIFFp-p = 2 ×|VRX_D+ −VRX_D−|. Applies to IN_Dx signals.

[4] Vi(cm)M(AC) = |VRX_D+ +V

RX_D−|/2−VRX(cm).

VRX(cm) = DC (avg) of |VRX_D+ +V

RX_D−|/2.

[5] Intended to limit power-up stress on chip set’s PCIe output buffers.

[6] Differential inputs will switch to a high-impedance state when OE_N is HIGH.

Table 10. Differential input characteristics for IN_Dx signals

Symbol Parameter Conditions Min Typ Max Unit

UI unit interval[1] [2] 600 - 4000 ps

VRX_DIFFp-p differential input peak-to-peak voltage [3] 0.175 - 1.200 V

TRX_EYE receiver eye time minimum eye width at

IN_Dx input pair 0.8 - - UI

Vi(cm)M(AC) peak common-mode input voltage (AC) includes all frequencies

above 30 kHz [4] - - 100 mV

ZRX_DC DC input impedance 40 50 60 Ω

VRX(bias) bias receiver voltage [5] 1.0 1.2 1.4 V

ZI(se) single-ended input impedance inputs in

high-impedance state [6] 100 - - kΩ

Product data sheet Rev. 02 — 7 October 2009 21 of 29

NXP Semiconductors PTN3361B

HDMI/DVI level shifter with dongle detect and DDC buffer

11.2 Differential outputs

The level shifter’s differential outputs are designed to meet HDMI version 1.3 and

DVI version 1.0 speciﬁcations.

[1] VTT is the DC termination voltage in the HDMI or DVI sink. VTT is nominally 3.3 V.

[2] The open-drain output pulls down from VTT.

[3] Swing down from TMDS termination voltage (3.3 V ±10 %).

[4] This differential skew budget is in addition to the skew presented between IN_D+ and IN_D− paired input pins.

[5] This lane-to-lane skew budget is in addition to skew between differential input pairs.

[6] Jitter budget for differential signals as they pass through the level shifter.

11.3 HPD_SINK input, HPD_SOURCE output

[1] Low-speed input changes state on cable plug/unplug.

[2] Time from HPD_SINK changing state to HPD_SOURCE changing state. Includes HPD_SOURCE rise/fall time.

[3] Time required to transition from VOH to VOL or from VOL to VOH.

[4] Guarantees HPD_SINK is LOW when no display is plugged in.

Table 11. Differential output characteristics for OUT_Dx signals

Symbol Parameter Conditions Min Typ Max Unit

VOH(se) single-ended HIGH-level

output voltage PES[1:0] = 00b [1] VTT −0.01 VTT VTT + 0.01 V

VOL(se) single-ended LOW-level

output voltage PES[1:0] = 00b [2] VTT −0.60 VTT −0.50 VTT −0.40 V

∆VO(se) single-ended output

voltage variation logic 1 and logic 0 state applied

respectively to differential inputs

IN_Dn; Rref(ext) connected;

see Table 8

[3] 450 500 600 mV

IOZ OFF-state output current single-ended - - 10 µA

trrise time 20 % to 80 % 75 - 240 ps

tffall time 80 % to 20 % 75 - 240 ps

tsk skew time intra-pair [4] - - 10 ps

inter-pair [5] - - 250 ps

tjit jitter time jitter contribution [6] - - 7.4 ps

Table 12. HPD characteristics

Symbol Parameter Conditions Min Typ Max Unit

VIH HIGH-level input voltage HPD_SINK [1] 2.0 5.0 5.3 V

VIL LOW-level input voltage HPD_SINK 0 - 0.8 V

ILI input leakage current HPD_SINK - - 15 µA

VOH HIGH-level output voltage HPD_SOURCE 2.5 - VDD V

VOL LOW-level output voltage HPD_SOURCE 0 - 0.2 V

tPD propagation delay from HPD_SINK to HPD_SOURCE;

50 % to 50 % [2] - - 200 ns

tttransition time HPD_SOURCE rise/fall; 10 % to 90 % [3] 1 - 20 ns

Rpd pull-down resistance HPD_SINK input pull-down resistor [4] 100 200 300 kΩ

Product data sheet Rev. 02 — 7 October 2009 22 of 29

NXP Semiconductors PTN3361B

HDMI/DVI level shifter with dongle detect and DDC buffer

11.4 OE_N, DDC_EN and DDET inputs

[1] Measured with input at VIH maximum and VIL minimum.

11.5 DDC characteristics

Table 13. OE_N, DDC_EN and DDET input characteristics

Symbol Parameter Conditions Min Typ Max Unit

VIH HIGH-level input voltage 2.0 - V

VIL LOW-level input voltage - 0.8 V

ILI input leakage current OE_N pin [1] --10µA

Table 14. DDC characteristics

= 3.0 V to 3.3 V

Symbol Parameter Conditions Min Typ Max Unit

Input and output SCL_SOURCE and SDA_SOURCE

VIH HIGH-level input voltage 0.7VDD -- V

VIL LOW-level input voltage −0.5 - +0.3VDD V

VILc contention LOW-level input voltage −0.5 0.4 - V

ILI input leakage current VI= 3.6 V - - ±1µA

IIL LOW-level input current VI= 0.2 V - - 10 µA

VOL LOW-level output voltage IOL = 100 µA or 6 mA 0.47 0.52 0.6 V

VOL−VILc difference between LOW-level output

and LOW-level input voltage

contention

guaranteed by design - - 70 mV

Cio input/output capacitance VI= 3 V or 0 V;

VDD = 3.3 V -67pF

VI= 3 V or 0 V; VDD =0V - 6 7 pF

Input and output SDA_SINK and SCL_SINK

VIH HIGH-level input voltage 1.5 - 5.5 V

VIL LOW-level input voltage −0.5 - +1.5 V

ILI input leakage current VDD =V

I= 5.5 V - - ±1µA

IIL LOW-level input current VI= 0.2 V - - 10 µA

VOL LOW-level output voltage IOL = 6 mA - 0.1 0.2 V

Cio input/output capacitance VI= 3 V or 0 V;

VDD = 3.3 V --7pF

VI= 3 V or 0 V; VDD =0V - 6 7 pF

Itrt(pu) transient boosted pull-up current VDD = 4.5 V;

slew rate = 1.25 V/µs-6-mA

Product data sheet Rev. 02 — 7 October 2009 23 of 29

NXP Semiconductors PTN3361B

HDMI/DVI level shifter with dongle detect and DDC buffer

12. Package outline

Fig 9. Package outline SOT619-1 (HVQFN48)

0.51

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 7.1

6.9

5.25

4.95

7.1

6.9 5.25

4.95

5.5

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT619-1 MO-220 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT619-1

HVQFN48: plastic thermal enhanced very thin quad flat package; no leads;

48 terminals; body 7 x 7 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

13 24

48 37

01-08-08

02-10-18

terminal 1

index area

terminal 1

index area

1/2 e

1/2 e AC

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 02 — 7 October 2009 24 of 29

NXP Semiconductors PTN3361B

HDMI/DVI level shifter with dongle detect and DDC buffer

13. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note

AN10365 “Surface mount reﬂow

soldering description”

13.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

13.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

•Board speciﬁcations, including the board ﬁnish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

13.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath speciﬁcations, including temperature and impurities

Product data sheet Rev. 02 — 7 October 2009 25 of 29

NXP Semiconductors PTN3361B

HDMI/DVI level shifter with dongle detect and DDC buffer

13.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

•Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 10) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 15 and 16

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 10.

Table 15. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 16. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 02 — 7 October 2009 26 of 29

NXP Semiconductors PTN3361B

HDMI/DVI level shifter with dongle detect and DDC buffer

For further information on temperature proﬁles, refer to Application Note

AN10365

“Surface mount reﬂow soldering description”

14. Abbreviations

MSL: Moisture Sensitivity Level

Fig 10. Temperature proﬁles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Table 17. Abbreviations

Acronym Description

CDM Charged-Device Model

CEC Consumer Electronics Control

DDC Data Display Channel

DVI Digital Visual Interface

EMI ElectroMagnetic Interference

ESD ElectroStatic Discharge

HBM Human Body Model

HDMI High-Deﬁnition Multimedia Interface

HPD Hot Plug Detect

I2C-bus Inter-IC bus

I/O Input/Output

NMOS Negative-channel Metal-Oxide Semiconductor

ROM Read-Only Memory

TMDS Transition Minimized Differential Signaling

VESA Video Electronic Standards Association

Product data sheet Rev. 02 — 7 October 2009 27 of 29

NXP Semiconductors PTN3361B

HDMI/DVI level shifter with dongle detect and DDC buffer

15. Revision history

Table 18. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PTN3361B_2 20091007 Product data sheet - PTN3361B_1

Modiﬁcations: •Table 11 “Differential output characteristics for OUT_Dx signals”,Table note [6]: deleted second

sentence

PTN3361B_1 20090929 Product data sheet - -

Product data sheet Rev. 02 — 7 October 2009 28 of 29

NXP Semiconductors PTN3361B

HDMI/DVI level shifter with dongle detect and DDC buffer

16. Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

16.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

16.4 Licenses

16.5 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

Purchase of NXP ICs with HDMI technology

Use of an NXP IC with HDMI technology in equipment that complies with

the HDMI standard requires a license from HDMI Licensing LLC, 1060 E.

Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail:

admin@hdmi.org.

NXP Semiconductors PTN3361B

HDMI/DVI level shifter with dongle detect and DDC buffer

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 7 October 2009

Document identifier: PTN3361B_2

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.1 High-speed TMDS level shifting . . . . . . . . . . . . 3

2.2 DDC level shifting . . . . . . . . . . . . . . . . . . . . . . . 3

2.3 HDMI dongle detect support. . . . . . . . . . . . . . . 3

2.4 HPD level shifting . . . . . . . . . . . . . . . . . . . . . . . 3

2.5 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 4

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 6

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7

7 Functional description . . . . . . . . . . . . . . . . . . 10

7.1 Enable and disable features . . . . . . . . . . . . . . 10

7.1.1 Hot plug detect . . . . . . . . . . . . . . . . . . . . . . . . 10

7.1.2 Output Enable function (OE_N) . . . . . . . . . . . 11

7.1.3 DDC channel enable function (DDC_EN). . . . 11

7.1.4 Enable/disable truth table. . . . . . . . . . . . . . . . 12

7.2 Analog current reference . . . . . . . . . . . . . . . . 13

7.3 Programmable pre-emphasis . . . . . . . . . . . . . 13

7.4 Backdrive current protection. . . . . . . . . . . . . . 13

7.5 Active DDC buffer with rise time accelerator . 14

7.6 I2C-bus based HDMI dongle detection. . . . . . 14

7.6.1 Slave address. . . . . . . . . . . . . . . . . . . . . . . . . 14

7.6.2 Read operation. . . . . . . . . . . . . . . . . . . . . . . . 15

7.7 Characteristics of the I2C-bus. . . . . . . . . . . . . 16

7.7.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.7.2 START and STOP conditions . . . . . . . . . . . . . 16

7.7.3 System conﬁguration . . . . . . . . . . . . . . . . . . . 16

7.7.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 17

8 Application design-in information . . . . . . . . . 18

8.1 Dongle or cable adaptor detect discovery

mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 19

10 Recommended operating conditions. . . . . . . 19

10.1 Current consumption . . . . . . . . . . . . . . . . . . . 19

11 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 20

11.1 Differential inputs . . . . . . . . . . . . . . . . . . . . . . 20

11.2 Differential outputs . . . . . . . . . . . . . . . . . . . . . 21

11.3 HPD_SINK input, HPD_SOURCE output. . . . 21

11.4 OE_N, DDC_EN and DDET inputs. . . . . . . . . 22

11.5 DDC characteristics . . . . . . . . . . . . . . . . . . . . 22

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23

13 Soldering of SMD packages . . . . . . . . . . . . . . 24

13.1 Introduction to soldering. . . . . . . . . . . . . . . . . 24

13.2 Wave and reﬂow soldering. . . . . . . . . . . . . . . 24

13.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 24

13.4 Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 25

14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 26

15 Revision history . . . . . . . . . . . . . . . . . . . . . . . 27

16 Legal information . . . . . . . . . . . . . . . . . . . . . . 28

16.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 28

16.2 Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 28

16.4 Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

16.5 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 28

17 Contact information . . . . . . . . . . . . . . . . . . . . 28

18 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29