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• Organization: 1,048,576 words × 18 bits
•NTD
™ architecture for efficient bus operation
• Fast clock speeds to 200 MHz in LVTTL/LVCMOS
• Fast clock to data access: 3/3.4/4 ns
•Fast OE
access time: 3/3.4/4 ns
• Fully synchronous operatio n
• “Flow-th rough” or “pip el ined” mod e
• Asynchronous output enable control
• Economical 100-pin TQFP package
• 119 BGA (7 x 17 Ball Grid Array package)
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 2.5V core power supply
• 2.5V I/O operation
• S elf-tim ed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
Write Buffer
Address
DQ
CLK
register
Output
Register
DATA [a:d]
20
20
CLK
CE0
CE1
CE2
A[19:0]
OE
CLK
CEN
Control
CLK
logic
Data
DQ
CLK
Input
Register
18 18
OE
1M x 18
SRAM
Array
R/W
DATA [a:d]
BWa
BWc
BWb
BWd
CLK
Q
D
FT
ADV / LD
LBO
Burst logic
addr . registers
Write delay 20
/RJLFEORFNGLDJUDP
ZZ
CLK
18 18
18
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
LBO
A
A
A
A
A1
A0
NC
NC
V
SS
VDD
NC
NC
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE0
CE1
BWd
BWc
BWb
BWa
CE2
VDD
VSS
CLK
R/W
CEN
OE
ADV/LD
A
A
A
A
TQFP 14 x 20mm
A
NC
NC
NC
VDDQ
VSSQ
NC
NC
DQc
DQc
VSSQ
VDDQ
DQc
DQc
FT
VDD
VDD
VSS
DQd
DQd
VDDQ
VSSQ
DQd
DQd
DQd
NC
VSSQ
VDDQ
NC
NC
NC
A
NC
NC
VDDQ
VSSQ
DQb
DQb
DQb
DQb
VSSQ
VDDQ
DQb
DQb
VSS
ZZ
DQa
DQa
VDDQ
VSSQ
DQa
DQa
NC
NC
VSSQ
VDDQ
NC
NC
NC
VDD
VDD
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NTD™ is a trademark of Alliance Semiconductor Corporation.
-200 -166 -100 Units
Minimum cycle time 5 6 10 ns
Maximum pipel ined clock frequenc y 200 166 100 MHz
Maximum pipelined clock acce ss time 3.0 3.4 4.0 ns
Maximum operating cur rent 280 230 150 mA
Maximum standby current 100 70 50 mA
Maximum C MOS stand by current (DC) 30 30 30 mA
$6&017'$
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