PL133-27
Low-Power, 1.62V to 3.63V, 1MHz To 150MHz, 1:2 Fanout Buffer IC
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 09/13/13 Page 1
FEATURES
2 LVCMOS Outputs
Input/Output Frequency: 1MHz to 150MHz
Supports LVCMOS or Sine Wave Input Clock
Extremely low additive Jitter
8 mA Output Drive Strength
Low Current Consumption
Single 1.8V, 2.5V, or 3.3V, ±10% Power Supply
Operating Temperature Range
o 0°C to 70°C (Commercial)
o -40C to 85C (Industrial)
Available in DFN-6L GREEN/RoHS Compliant
Packages
DESCRIPTION
The PL133-27 is an advanced fanout buffer design for
high performance, low-power, small form-factor
applications. The PL133-27 accepts a reference
clock input of 1MHz to 150MHz and produces two
outputs of the same frequency. Reference clock
inputs may be LVCMOS or sine-wave signals (the
inputs are internally AC-coupled). PL133-27 is
designed to fit in a small 2 x 1.3 x 0.6mm DFN
package, and offers the best phase noise and jitter
performance and lowest power consumption of any
comparable IC.
PACKAGE PIN CONFIGURATION
BLOCK DIAGRAM
FIN CLK0
CLK1
OE
DFN-6L
(2.0 x 1.3 x 0.6mm)
FIN
GND
OE
VDD
CLK0
CLK1 1
4
5
6
3
2
PL133-27
Low-Power, 1.62V to 3.63V, 1MHz To 150MHz, 1:2 Fanout Buffer IC
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 09/13/13 Page 2
PACKAGE PIN ASSIGNMENT
Name
Package Pin #
Type
Description
DFN-6L
FIN
1
I
Reference clock input
CLK1
2
O
Clock output
GND
3
P
GND connection
CLK0
4
O
Clock output
VDD
5
P
VDD connection
OE
6
I
Output enable input
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination Considerations
- Keep traces short!
- Trace = Inductor. With a capacitive load this equals
ringing!
- Long trace = Transmission Line. Without proper
termination this will cause reflections (looks like ringing).
- Design long traces as “striplines” or “microstrips” with
defined impedance.
- Match trace at one side to avoid reflections bouncing
back and forth.
Decoupling and Power Supply Considerations
- Place decoupling capacitors as close as possible to
the VDD pin(s) to limit noise from the power supply
- Multiple VDD pins should be decoupled separately
for best performance.
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency
dependant. Typical values to use are 0.1F for
designs using crystals < 50MHz and 0.01F for
designs using crystals > 50MHz.
Typical CMOS termination
Place Series Resistor as close as possible to CMOS output
CMOS Output Buffer
(Typical buffer impedance 20Ω)To CMOS Input
Series Resistor
Use value to match output buffer impedance to
50Ω trace. Typical value 30Ω
50Ω line
PL133-27
Low-Power, 1.62V to 3.63V, 1MHz To 150MHz, 1:2 Fanout Buffer IC
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 09/13/13 Page 3
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
SYMBOL
MIN.
MAX.
UNITS
VDD
-0.5
4.6
V
VI
-0.5
VDD+0.5
V
VO
-0.5
VDD+0.5
V
TS
-65
150
C
-40
85
C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Input (FIN) Frequency
@ VDD = 2.5V and 3.3V
1MHz
150
MHz
@ VDD = 1.8V
65
Input (FIN) Signal Amplitude
Internally AC coupled
0.8
VDD
VPP
Output Rise Time
15pF Load, 10/90%VDD, 3.3V
2
3
ns
Output Fall Time
15pF Load, 90/10%VDD, 3.3V
2
3
ns
Output to Output Skew
500
ps
Duty Cycle
Input Duty Cycle is 50%
45
50
55
%
DC SPECIFICATIONS
PARAMETERS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Current, Dynamic
IDD
VDD = 3.3V, 25MHz, No Load
1.8
mA
VDD = 2.5V, 25MHz, No Load
1.3
mA
VDD = 1.8V, 25MHz, No Load
0.8
mA
Operating Voltage
VDD
1.62
3.63
V
Output Low Voltage
VOL
IOL = +4mA, VDD = 3.3V
0.4
V
Output High Voltage
VOH
IOH = -4mA, VDD = 3.3V
2.4
V
Output Current
IOSD
VOL = 0.4V, VOH = 2.4V,
VDD = 3.3V
8
mA
PL133-27
Low-Power, 1.62V to 3.63V, 1MHz To 150MHz, 1:2 Fanout Buffer IC
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 09/13/13 Page 4
NOISE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
Additive Phase Jitter
V DD=3.3V, Frequency=26MHz
Offset=12KHz ~ 5MHz
130
fs
V DD=3.3V, Frequency=100MHz
Offset=12KHz ~ 20MHz
150
fs
PL133-27 Additive Phase Jitter:
VDD=3.3V, CLK=26MHz, Integration Range 12KHz to 5MHz: 0.127ps typical.
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
10 100 1000 10000 100000 1000000 10000000
Offset Frequency (Hz)
Phase Noise (dBc/Hz)
REF Input PL133-27 Output
When a buffer is used to pass a signal then the buffer will add a little bit of its own noise. The phase noise on the
output of the buffer will be a little bit more than the phase noise in the input signal. To quantify the noise addition in
the buffer we compare the Phase Jitter numbers from the input and the output. The difference is called "Additive
Phase Jitter". The formula for the Additive Phase Jitter is as follows:
Additive Phase Jitter = (Output Phase Jitter) - (Input Phase Jitter)22
PL133-27
Low-Power, 1.62V to 3.63V, 1MHz To 150MHz, 1:2 Fanout Buffer IC
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 09/13/13 Page 5
D
E
Pin1 Dot
D1
be
E1
L
A3
AA1
Pin 6 ID
Chamfer
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
DFN-6L
ORDERING INFORMATION (GREEN PACKAGE)
For part ordering, please contact our Sales Department:
2180 Fortune Drive, San Jose, CA 95131, USA
Tel: (408) 944-0800 Fax: (408) 474-1000
PART NUMBER
The order number for this device is a combination of the following:
Part number, Package type and Operating temperature range
PL133-27 X X - R
Part Number
Package Type
G=DFN-6L
Temperature Range
C=Commercial (0°C to 70°C)
I=Industrial (-40°C to 85°C)
R=Tape and Reel
Part/Order Number
Marking
Package Option
PL133-27GC-R
H27
LLL
6-Pin DFN (Tape and Reel)
PL133-27GI-R
*Note: LLL designates lot number
Micrel Inc., reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Micrel is believed to be accurate
and reliable. However, Micrel makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever
nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: Micrel’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the
President of Micrel Inc.
Symbol
Dimension in MM
Min.
Max.
A
0.45
0.60
A1
0.00
0.05
A3
0.152
0.152
b
0.15
0.25
e
0.40BSC
D
1.25
1.35
E
1.95
2.05
D1
0.75
0.85
E1
0.95
1.05
L
0.20
0.30