ASM802MCPAF-T - ON Semiconductor L.L.C.

August, 2011 − Rev. 3

1Publication Order Number:

ASM690A/D

ASM690A/692A,

ASM802L/802M, ASM805L

mP Power Supply Supervisor

with Battery Backup Switch

Description

The ASM690A / ASM692A / ASM802L / ASM802M / ASM805L

offers complete single chip solutions for power supply monitoring and

control battery functions in microprocessor systems. Each device

implements four functions: Reset control, watchdog monitoring,

battery−backup switching and power failure monitoring. In addition to

microprocessor reset under power−up and power−down conditions,

these devices provide battery−backup switching to maintain control in

power loss and brown−out situations. Additional monitoring

capabilities can provide an early warning of unregulated power supply

loss before the voltage regulator drops out. The important features of

these four functions are:

•1.6 second watchdog timer to keep microprocessor responsive

•4.40 V or 4.65 V VCC threshold for microprocessor reset at

power−up and power−down

•SPDT (Single−pole, Double−throw) PMOS switch connects backup

power to RAM if VCC fails

•1.25 V threshold detector for power loss or general purpose voltage

monitoring

These features are pin−compatible with the industry standard

power−supply supervisors. Short−circuit and thermal protection have

also been added. The ASM690A / ASM802L / ASM805L generate a

reset pulse when the supply voltage drops below 4.65 V and the

ASM692A / ASM802M generate a reset below 4.40 V. The ASM802L

/ ASM802M have power−fail accuracy to ±2%. The ASM805L is the

same as the ASM690A except that RESET is provided instead of

RESET.

Features

•Two Precision Supply−voltage Monitor Options

4.65 V (ASM690A / ASM802L / ASM805L)

4.40 V (ASM692A / ASM802M)

•Battery−backup Power Switch On−chip

•Watchdog Timer: 1.6 Second Timeout

•Power Failure / Low Battery Detection

•Short Circuit Protection and Thermal Limiting

•Small 8−pin SO and 8−pin PDIP Packages

•No External Components

•Specified Over Full Temperature Range

Applications

•Embedded Control Systems

•Portable/Battery Operated Systems

•Intelligent Instruments

•Wireless Instruments

•Wireless Communication Systems

•PDAs and Hand−held Equipments

•mP / mC Power Supply Monitoring

•Safety System

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PIN CONFIGURATIONS

See detailed ordering and shipping information in the package

dimensions section on page 11 of this data sheet.

ORDERING INFORMATION

PDIP−8

P SUFFIX

CASE 646AA

SOIC−8

S SUFFIX

CASE 751BD

VOUT

VCC

GND

PFI

VBATT

RESET

WDI

PFO

ASM690A,

ASM692A,

ASM802L,

ASM802M

VOUT

VCC

GND

PFI

VBATT

RESET

WDI

PFO

ASM805L

(Top Views)

ASM690A/692A, ASM802L/802M, ASM805L

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Figure 1. Typical Operating Circuit Figure 2. Block Diagram

Table 1. PIN DESCRIPTION

Pin Number

Name Function

ASM690A/ASM692A

ASM802L/ASM802M ASM805L

1 1 VOUT Voltage supply for RAM. When VCC is above the reset threshold, VOUT connects

to VCC through a P−Channel MOS device. If VCC falls below the reset threshold,

this output will be connected to the backup supply at VBATT (or VCC, whichever is

higher) through the MOS switch to provide continuous power to the CMOS RAM.

2 2 VCC +5 V power supply input.

3 3 GND Ground.

4 4 PFI Power failure monitor input. PFI is connected to the internal power fail comparat-

or which is referenced to 1.25 V. The power fail output (PFO) is active LOW but

remains HIGH if PFI is above 1.25 V. If this feature is unused, the PFI pin should

be connected to GND or VOUT

5 5 PFO Power−fail output. PFO is active LOW whenever the PFI pin is less than 1.25 V.

6 6 WDI Watchdog input. The WDI input monitors microprocessor activity. An internal

timer is reset with each transition of the WDI input. If the WDI is held HIGH or

LOW for longer than the watchdog timeout period, typically 1.6 seconds, RESET

(or RESET) is asserted for the reset pulse width time, tRS, of 140 ms, minimum.

7−RESET Active−LOW reset output. When triggered by VCC falling below the reset

threshold or by watchdog timer timeout, RESET pulses low for the reset pulse

width tRS, typically 200 ms. It will remain low if VCC is below the reset threshold

(4.65 V in ASM690A / ASM802L and 4.4 V in the ASM692A / ASM802L) and

remains low for 200 ms after VCC rises above the reset threshold.

−7 RESET Active−HIGH reset output. The inverse of RESET.

8 8 VBATT Auxiliary power or backup−battery input. VBATT should be connected to GND if

the function is not used. The input has about 40 mV of hysteresis to prevent rapid

toggling between VCC and VBATT

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Table 2. ABSOLUTE MAXIMUM RATINGS

Parameter Min Max Unit

Pin Terminal Voltage with Respect to Ground

VCC

VBATT

All other inputs (Note 1)

−0.3

6.0

VCC + 0.3

Input Current at VCC 200 mA

Input Current at VBATT 50 mA

Input Current at GND 20 mA

Output Current

VOUT Short circuit protected

All other inputs 20 mA

Rate of Rise: VBATT and VCC 100 V/ms

Continuous Power Dissipation

Plastic DIP (derate 9 mW/°C above 70°C)

SO (derate 5.9 mW/°C above 70°C)

800

500

Operating Temperature Range (C Devices) 0 70 °C

Operating Temperature Range (E Devices) −40 85 °C

Storage Temperature Range −65 160 °C

Lead Temperature (Soldering, 10 sec) 300 °C

ESD rating

HBM

100

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. The input voltage limits on PFI and WDI may be exceeded if the current is limited to less than 10 mA.

Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted, VCC = 4.75 V to 5.5 V for the ASM690A / ASM802L /

ASM805L and VCC = 4.5 V to 5.5 V for the ASM692A / ASM802M; VBATT = 2.8 V; and TA = TMIN to TMAX.)

Parameter Symbol Conditions Min Typ Max Unit

VCC, VBATT Voltage

Range (Note 2)

1.1 5.5 V

Supply Current

Excluding IOUT

IS35 100 mA

ISUPPLY in Battery

Backup Mode

(Excluding IOUT)

VCC = 0 V, VBATT = 2.8 V TA = 25°C 1.5 mA

TA = TMIN to TMAX 5.0

VBATT Standby

Current (Note 3)

5.5 V > VCC > VBATT + 0.2 V TA = 25°C

TA = TMIN to TMAX

−0.1

−1.0

0.02

VOUT Output IOUT = 5 mA VCC−0.025 VCC−

0.010

IOUT = 50 mA VCC−0.25 VCC−

0.10

VOUT in Battery

Backup Mode

IOUT = 250 mA, VCC < VBATT − 0.2 V VBATT− 0.1 VBATT

−

0.001

2. If VCC or VBATT is 0 V, the other must be greater than 2.0 V.

3. Battery charging−current is “−”. Battery discharge current is “+”.

4. WDI is guaranteed to be in an intermediate level state if WDI is floating and VCC is within the operating voltage range.

NOTE: WDI input impedance is 50 kW. WDI is biased to 0.3 VCC.

ASM690A/692A, ASM802L/802M, ASM805L

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Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted, VCC = 4.75 V to 5.5 V for the ASM690A / ASM802L /

ASM805L and VCC = 4.5 V to 5.5 V for the ASM692A / ASM802M; VBATT = 2.8 V; and TA = TMIN to TMAX.) (continued)

Parameter UnitMaxTypMinConditionsSymbol

Battery Switch

Threshold,

VCC to VBATT

VCC < VRT Power Up

Power Down

−20

Battery Switch over

Hysteresis

40 mV

Reset Threshold VRT ASM690A/802L/805L 4.50 4.65 4.75 V

ASM692A, ASM802M 4.25 4.40 4.50

ASM802L, TA = 25°C, VCC falling 4.55 4.70

ASM802M, TA = 25°C, VCC falling 4.30 4.45

Reset Threshold

Hysteresis

40 mV

Reset Pulse Width tRS 140 200 280 ms

Reset Output

Voltage

ISOURCE = 800 mAVCC − 1.5 V

ISINK = 3.2 mA 0.4

ASM69_AC, ASM802_C, VCC = 1.0 V, ISINK = 50 mA0.3

ASM69_AE, ASM802_E, VCC = 1.2 V, ISINK = 100 mA0.3

ASM805LC, ISOURCE = 4 mA, VCC = 1.1 V 0.8

ASM805LE, ISOURCE = 4 mA, VCC = 1.2 V 0.9

ASM805L, ISOURCE = 800 mAVCC − 1.5

ASM805L, ISINK = 3.2 mA 0.4

Watchdog Timeout tWD 1.00 1.60 2.25 sec

WDI Pulse Width tWP VIL = 0.4 V, VIH = 0.8 VCC 50 ns

WDI Input Current WDI = VCC 50 150 mA

WDI = 0 V −150 −50

WDI Input Threshold

(Note 4)

VCC = 5 V, Logic LOW 0.8 V

VCC = 5 V, Logic HIGH 3.5

PFI Input Threshold ASM69_A, ASM805L, VCC = 5 V 1.20 1.25 1.30 V

ASM802_C/E, VCC = 5 V 1.225 1.250 1.275

PFI Input Current −25 0.01 25 nA

PFO Output Voltage ISOURCE = 800 mAVCC − 1.5 V

ISINK = 3.2 mA 0.4

2. If VCC or VBATT is 0 V, the other must be greater than 2.0 V.

3. Battery charging−current is “−”. Battery discharge current is “+”.

4. WDI is guaranteed to be in an intermediate level state if WDI is floating and VCC is within the operating voltage range.

NOTE: WDI input impedance is 50 kW. WDI is biased to 0.3 VCC.

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Detailed Description

It is important to initialize a microprocessor to a known

state in response to specific events that could create code

execution errors and “lock−up”. The reset output of these

supervisory circuits send a reset pulse to the microprocessor

in response to power−up, power−down/power−loss or a

watchdog time−out.

RESET/RESET Timing

Power−up reset occurs when a rising VCC reaches the

reset threshold, VRT, forcing a reset condition in which the

reset output is asserted in the appropriate logic state for the

duration of tRS. The reset pulse width, tRS, is typically

around 200 ms and is LOW for the ASM690A, ASM692A,

ASM802 and HIGH for the ASM805L. Figure 3 shows the

reset pin timing.

Power−loss or “brown−out” reset occurs when VCC dips

below the reset threshold resulting in a reset assertion for the

duration of tRS. The reset signal remains asserted as long as

VCC is between VRT and 1.1 V, the lowest VCC for which

these devices can provide a guaranteed logic−low output. To

ensure logic inputs connected to the ASM690A /

ASM692A/ASM802 RESET pin are in a known state when

VCC is under 1.1 V, a 100 kW pull−down resistor at RESET

is needed: the logic−high ASM805L will need a pull−up

resistor to VCC.

Watchdog Timer

A Watchdog time−out reset occurs when a logic “1” or

logic “0” is continuously applied to the WDI pin for more

than 1.6 seconds. After the duration of the reset interval, the

watchdog timer starts a new 1.6 second timing interval; the

microprocessor must service the watchdog input by

changing states or by floating the WDI pin before this

interval is finished. If the WDI pin is held either HIGH or

LOW, a reset pulse will be triggered every 1.8 seconds (the

1.6 second timing interval plus the reset pulse width tRS).

Application Information

Microprocessor Interface

The ASM690 has logic−LOW RESET output while the

ASM805 has an inverted logic−HIGH RESET output.

Microprocessors with bidirectional reset pins can pose a

problem when the supervisory circuit and the

microprocessor output pins attempt to go to opposite logic

states. The problem can be resolved by placing a 4.7 kW

resistor between the RESET output and the microprocessor

reset pin. This is shown in Figure 4. Since the series resistor

limits drive capabilities, the reset signal to other devices

should be buffered.

Figure 3. RESET/RESET Timing

Figure 4. Interfacing with Bi−directional

Microprocessor Reset Inputs

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Watchdog Input

As discussed in the Reset section, the Watchdog input is

used to monitor microprocessor activity. It can be used to

insure that the microprocessor is in a continually responsive

state by requiring that the WDI pin be toggled every second.

If the WDI pin is not toggled within the 1.6 second window

(minimum tWD + tRS), a reset pulse will be asserted to return

the microprocessor to the initial start−up state. Pulses as

short as 50 ns can be applied to the WDI pin. If this feature

is not used, the WDI pin should be open circuited or the logic

placed into a high−impedance state to allow the pin to float.

Backup−Battery Switchover

A power loss can be made less severe if the system RAM

contents are preserved. This is achieved in the ASM690/

692/802/805 by switching from the failed VCC to an

alternate power source connected at VBATT when VCC is less

than the reset threshold voltage (VCC < VRT), and VCC is less

than VBATT. The VOUT pin is normally connected to VCC

through a 2 W PMOS switch but a brown−out or loss of VCC

will cause a switchover to VBATT by means of a 20 W PMOS

switch. Although both conditions (VCC < VRT and VCC <

VBATT) must occur for the switchover to VBATT to occur,

VOUT will be switched back to VCC when VCC exceeds VRT

irrespective of the voltage at VBATT. It should be noted that

an internal device diode (D1 in Figure 5) will be forward

biased if VBATT exceeds VCC by more than a diode drop

when VCC is switched to VOUT. Because of this it is

recommended that VBATT be no greater than VRT + 0.6 V.

Table 4.

Condition SW1/SW2 SW3/SW4

VCC > Reset Threshold Open Closed

VCC < Reset Threshold

VCC > VBATT

Open Closed

VCC < Reset Threshold

VCC < VBATT

Closed Open

ASM690A/802A/805L Reset Threshold = 4.65 V

ASM692A/ASM802M Reset Threshold = 4.4 V

Figure 5. Internal Device Configuration of Battery

Switch−over Function

Table 5. PIN CONNECTIONS

IN BATTERY BACKUP MODE

Pin Connection

VOUT Connected to VBATT through internal

PMOS switch

VBATT Connected to VOUT

PFI Disabled

PFO Logic−LOW

RESET Logic−LOW (except on ASM805 where it

is HIGH)

WDI Watchdog timer disabled

During the backup power mode, the internal circuitry of

the supervisory circuit draws power from the battery supply.

While VCC is still alive, the comparator circuits remain alive

and the current drawn by the device is typically 35 mA.

When VCC drops more than 1.1 V below VBATT, the internal

switchover comparator, the PFI comparator and WDI

comparator will shut off, reducing the quiescent current

drawn by the IC to less than 1 mA.

Backup Power Sources − Batteries

Battery voltage selection is important to insure that the

battery does not discharge through the parasitic device diode

D1 (see Figure 5) when VCC is less than VBATT and VCC >

VRT.

Table 6. MAXIMUM BATTERY VOLTAGES

Part Number Maximum Battery Voltage (V)

ASM690A 4.80

ASM802L 4.80

ASM805L 4.80

ASM692A 4.55

ASM802M 4.55

Although most batteries that meet the requirements of

Table 6 are acceptable, lithium batteries are very effective

backup source due to their high−energy density and very low

self−discharge rates.

Battery Replacement while Powered

Batteries can be replaced even when the device is in a

powered state as long as VCC remains above the reset

threshold voltage VRT. In the ASM devices, a floating

VBATT pin will not cause a power supply switchover as can

occur in some other supervisory circuits. If VBATT is not

used, the pin should be grounded.

Backup Power Sources − SuperCapt

Capacitor storage, with very high values of capacitance,

can be used as a back−up power source instead of batteries.

SuperCap are capacitors with capacities in the fractional

farad range. A 0.1 farad SuperCap would provide a useful

backup power source. Like the battery supply, it is important

ASM690A/692A, ASM802L/802M, ASM805L

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that the capacitor voltage remain below the maximum

voltages shown in Table 6. Although the circuit of Figure 6

shows the most simple way to connect the SuperCap, this

circuit cannot insure that an over voltage condition will not

occur since the capacitor will ultimately charge up to VCC.

To insure that an over voltage condition does not occur, the

circuit of Figure 7 is preferred. In this circuit configuration,

the diode−resistor pair clamps the capacitor voltage at one

diode drop below VCC. VCC itself should be regulated

within ±5% of 5 V for the ASM692A/802M or within ±10%

of 5 V for the ASM690A/802L/805L to insure that the

storage capacitor does not achieve an over voltage state.

Figure 6. Capacitor as a Backup Power Source

Figure 7. Capacitor as a Backup Power Source

Voltage Clamped to 0.5 V below VCC

Operation without a Backup Power Source

When operating without a back−up power source, the

VBATT pin should be connected to GND and VOUT should

be connected to VCC, since power source switchover will not

occur. Connecting VOUT to VCC eliminates the voltage drop

due to the ON−resistance of the PMOS switch.

Power−Fail Comparator

The Power Fail feature is an independent voltage

monitoring function that can be used for any number of

monitoring activities. The PFI function can provide an early

sensing of power supply failure by sensing the voltage of the

unregulated DC ahead of the regulated supply sensing seen

by the backup−battery switchover circuitry. The PFI pin is

compared to a 1.25 V internal reference. If the voltage at the

PFI pin is less than this reference voltage, the PFO pin goes

low. By sensing the voltage of the raw DC power supply, the

microprocessor system can prepare for imminent

power−loss, especially if the battery backup supply is not

enabled. The input voltage at the PFI pin results from a

simple resistor voltage divider as shown in Figure 8.

Figure 8. Simple Voltage Divider Sets PFI Trip Point

Power Fail Hysteresis

A noise margin can be added to the simple monitoring

circuit of Figure 8 by adding positive feedback from the

PFO pin. The circuit of Figure 9 adds this positive “latching”

effect by means of an additional resistor R3 connected

between PFO and PFI which helps in pulling PFI in the

direction of PFO and eliminating an indecision at the trip

point. Resistor R3 is normally about 10 times higher in

resistance than R2 to keep the hysteresis band reasonable

and should be larger than 10 kW to avoid excessive loading

on the PFO pin. The calculations for the correct values of

resistors to set the hysteresis thresholds are given in

Figure 9. A capacitor can be added to offer additional noise

rejection by low−pass filtering.

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Figure 9. Hysteresis Added to PFI Pin

Monitoring Capabilities of the Power−fail Input:

Although designed for power supply failure monitoring,

the PFI pin can be used for monitoring any voltage condition

that can be scaled by means of a resistive divider. An

example is the negative power supply monitor configured in

Figure 10. In this case a good negative supply will hold the

PFI pin below 1.25 V and the PFO pin will be at logic “0”.

As the negative voltage declines, the voltage at the PFI pin

will rise until it exceeds 1.25 V and the PFO pin will go to

logic “1”.

Figure 10. Using PFI to Monitor Negative Supply

Voltage

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PACKAGE DIMENSIONS

PDIP−8, 300 mils

CASE 646AA−01

ISSUE A

TOP VIEW

SIDE VIEW END VIEW

PIN # 1

IDENTIFICATION

Notes:

(1) All dimensions are in millimeters.

(2) Complies with JEDEC MS-001.

SYMBOL MIN NOM MAX

0.38

2.92

0.36

6.10

1.14

0.20

9.02

2.54 BSC

3.30

5.33

4.95

0.56

7.11

1.78

0.36

10.16

eB 7.87 10.92

E 7.62 8.25

2.92 3.80

3.30

0.46

6.35

1.52

0.25

9.27

7.87

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PACKAGE DIMENSIONS

SOIC 8, 150 mils

CASE 751BD−01

ISSUE O

E1 E

PIN # 1

IDENTIFICATION

TOP VIEW

SIDE VIEW END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MS-012.

SYMBOL MIN NOM MAX

0º 8º

0.10

0.33

0.19

0.25

4.80

5.80

3.80

1.27 BSC

1.75

0.25

0.51

0.25

0.50

5.00

6.20

4.00

L0.40 1.27

1.35

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Table 7. ORDERING INFORMATION − Tin − Lead Devices

Part Number (Note 5) Reset Threshold (V) Temperature (5C) Pins−Package Package Marking

ASM690A

ASM690ACPA 4.5 to 4.75 0 to +70 8−Plastic DIP ASM690ACPA

ASM690ACSA 4.5 to 4.75 0 to +70 8−SO ASM690ACSA

ASM690AEPA 4.5 to 4.75 −40 to +85 8−Plastic DIP ASM690AEPA

ASM690AESA 4.5 to 4.75 −40 to +85 8−SO ASM690AESA

ASM692A

ASM692ACPA 4.25 to 4.50 0 to +70 8−Plastic DIP ASM692ACPA

ASM692ACSA 4.25 to 4.50 0 to +70 8−SO ASM692ACSA

ASM692AEPA 4.25 to 4.50 −40 to +85 8−Plastic DIP ASM692AEPA

ASM692AESA 4.25 to 4.50 −40 to +85 8−SO ASM692AESA

ASM802L

ASM802LCPA 4.5 to 4.75 0 to +70 8−Plastic DIP ASM802LCPA

ASM802LCSA 4.5 to 4.75 0 to +70 8−SO ASM802LCSA

ASM802LEPA 4.5 to 4.75 −40 to +85 8−Plastic DIP ASM802LEPA

ASM802LESA 4.5 to 4.75 −40 to +85 8−SO ASM802LESA

ASM802M

ASM802MCPA 4.25 to 4.50 0 to +70 8−Plastic DIP ASM802MCPA

ASM802MCSA 4.25 to 4.50 0 to +70 8−SO ASM802MCSA

ASM802MEPA 4.25 to 4.50 −40 to +85 8−Plastic DIP ASM802MEPA

ASM802MESA 4.25 to 4.50 −40 to +85 8−SO ASM802MESA

ASM805L

ASM805LCPA 4.5 to 4.75 0 to +70 8−Plastic DIP ASM805LCPA

ASM805LCSA 4.5 to 4.75 0 to +70 8−SO ASM805LCSA

ASM805LEPA 4.5 to 4.75 −40 to +85 8−Plastic DIP ASM805LEPA

ASM805LESA 4.5 to 4.75 −40 to +85 8−SO ASM805LESA

5. For parts to be packed in Tape and Reel, add “−T” at the end of the part number. ON Semiconductor lead free parts are RoHS compliant.

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Table 8. ORDERING INFORMATION − Lead Free Devices

Part Number (Note 6) Reset Threshold (V) Temperature (5C) Pins−Package Package Marking

ASM690A

ASM690ACPAF 4.5 to 4.75 0 to +70 8−Plastic DIP ASM690ACPAF

ASM690ACSAF 4.5 to 4.75 0 to +70 8−SO ASM690ACSAF

ASM690AEPAF 4.5 to 4.75 −40 to +85 8−Plastic DIP ASM690AEPAF

ASM690AESAF 4.5 to 4.75 −40 to +85 8−SO ASM690AESAF

ASM692A

ASM692ACPAF 4.25 to 4.50 0 to +70 8−Plastic DIP ASM692ACPAF

ASM692ACSAF 4.25 to 4.50 0 to +70 8−SO ASM692ACSAF

ASM692AEPAF 4.25 to 4.50 −40 to +85 8−Plastic DIP ASM692AEPAF

ASM692AESAF 4.25 to 4.50 −40 to +85 8−SO ASM692AESAF

ASM802L

ASM802LCPAF 4.5 to 4.75 0 to +70 8−Plastic DIP ASM802LCPAF

ASM802LCSAF 4.5 to 4.75 0 to +70 8−SO ASM802LCSAF

ASM802LEPAF 4.5 to 4.75 −40 to +85 8−Plastic DIP ASM802LEPAF

ASM802LESAF 4.5 to 4.75 −40 to +85 8−SO ASM802LESAF

ASM802M

ASM802MCPAF 4.25 to 4.50 0 to +70 8−Plastic DIP ASM802MCPAF

ASM802MCSAF 4.25 to 4.50 0 to +70 8−SO ASM802MCSAF

ASM802MEPAF 4.25 to 4.50 −40 to +85 8−Plastic DIP ASM802MEPAF

ASM802MESAF 4.25 to 4.50 −40 to +85 8−SO ASM802MESAF

ASM805L

ASM805LCPAF 4.5 to 4.75 0 to +70 8−Plastic DIP ASM805LCPAF

ASM805LCSAF 4.5 to 4.75 0 to +70 8−SO ASM805LCSAF

ASM805LEPAF 4.5 to 4.75 −40 to +85 8−Plastic DIP ASM805LEPAF

ASM805LESAF 4.5 to 4.75 −40 to +85 8−SO ASM805LESAF

6. For parts to be packed in Tape and Reel, add “−T” at the end of the part number. ON Semiconductor lead free parts are RoHS compliant.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

ASM690A/D

SuperCap is a trademark of Baknor Industries.

PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

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Phone: 81−3−5773−3850

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