CB-C8VX/VM 3-Volt, 0.5-Micron Cell-Based CMOS ASIC NEC Electronics Inc. Preliminary April 1996 Figure 1. BGA Package Examples Description NEC's CB-C8VX/VM CMOS cell-based ASIC family facilitates the design of complete cell-based silicon systems composed of user-defined logic, complex macrofunctions such as microprocessors, intelligent peripherals, analog functions, and compiled memory blocks. The CB-C8VX cell-based ASIC series employs a 0.5-micron (0.35-micron effective) silicon gate CMOS process with silicidation. This advanced process greatly reduces the number of contacts per cell, leading to areaefficient library elements optimized on speed with a 3.3volt power supply. CB-C8VM, a derivative of CB-C8VX, features a unique I/O structure that provides a full 5-volt CMOS interface. For both technologies, the TitaniumSilicide process results in overall reduced power consumption per cell. Combining very high integration, high speed, and low power consumption, this technology meets today's rigorous application demands. (R) Fully supported by NEC's sophisticated OpenCAD design framework, CB-C8VX/VM maximizes design quality and flexibility while minimizing ASIC design time. NEC's OpenCAD system combines popular third-party design tools with proprietary NEC tools, including advanced floorplanner and clock tree synthesis tools. Full 5-Volt CMOS Interface CB-C8VM offers a full voltage swing interface to a 5-volt CMOS signal environment. This option is realized by implementing a section of thicker gate oxide into the I/O buffer to guarantee the necessary breakdown voltages. The 5-volt I/O buffers can be placed at any location of the I/O area and are freely mixable with 3.3-volt buffers. The internal core is identical to CB-C8VX. Table 1. CB-C8VX/VM Series Features and Benefits CB-C8VX/VM Series Features CB-C8VX/VM Series Benefits * 0.5-micron (drawn), Ti-Silicide CMOS technology * High-density cell structure * True 3.3 V process * High speed at low power supply * 36 base sizes, each with 2- and 3-metal layer options * Flexible base sizes to best fit design needs * Usable gates from 14K to 703K gates * High integration capabilities * True 5 V CMOS interface by multi-oxide I/O structure * Supports flexible interfacing to different signal voltages * Staggered pad ring for high gate-to-pad ratio * Minimizes device cost for high I/O requirement * 5 V and 3.3 V PCI buffer, including 66-MHz PCI * Full PCI support compliant with latest PCI specification * GTL and HSTL buffer in development * High-speed I/F to memory and processor buses * Low power dissipation: 1.04 mW/MHz/gate (3.3 V) * Ideally-suited for hand-held applications * Extensive macro range (CPUs, peripherals, analog) * Advanced system-on-silicon capabilities * Memory compiler for various types of memory blocks * Area-effective memory integration on chip * Extensive package support: PQFP, TQFP, BGA, TBGA * Delivers the latest package requirements * Automatic clock skew control by clock tree synthesis * Minimizes on-chip clock skew * OpenCAD: popular, third-party CAE tools supported * Smooth design flow from customer design to silicon A10985EU1V0DS00 OpenCAD is a registered trademark of NEC Electronics Inc. CB-C8VX/VM 5-Volt-Tolerant Interface CB-C8VX supports both 3.3-volt and 5-volt-tolerant signaling. The 5-volt-tolerant buffers enable CB-C8VX devices to communicate with 5-volt TTL signals while protecting the ASIC. CB-C8VX requires only a 3.3-volt power supply. Integration and Performance Gate complexities up to 703K usable gates can be integrated on the largest of 36 die sizes, each routable with 2- or 3-metal layers. This gives enough flexibility to optimally fit design needs. Twenty-two die sizes offer a single I/O pad ring and 14 are equipped with a staggered dual pad ring in order to achieve a high padto-gate ratio. For details, please refer to Table 2 and Table 3. Each of these blocks has several different drive strengths, allowing the synthesis tool to select the most suitable block for the required internal load. This generally reduces the design overhead without influencing design performance. The internal gate delay for a two-input NAND gate is 110 picoseconds (ps), (F/O=1, L=0mm) and 220 ps under loaded conditions (F/O=2, L=2mm). The family offers an extensive library of primitive macrofunctions characterized for 3.3-volt operation. To meet today's high-speed demands, high-performance I/O macros are mandatory. CB-C8VX/VM supports macros such as GTL and HSTL for fast, lowpower data transfer, PLLs to synchronize on-chip system clocks, and PCI signaling standards. Also, CB-C8VX/VM offers a variety of macrofunctions to be incorporated on a single chip. These macrofunctions include CPU cores, peripheral devices, RAM/ROM and analog functions, enabling designers to create systems on silicon. Table 2. CB-C8VX/VM Die Steps (124 pad pitch) Low Power Consumption Max. Usable Gates(1) 2 Layer 3 Layer Step I/O B18 88 13078 19617 B57 104 18797 28195 B97 120 25438 38156 C37 136 33219 49828 C76 152 42016 63023 D16 168 51703 77555 D55 184 62547 93820 D75 192 67969 101953 E15 208 80484 E54 224 E94 240 F34 256 F74 Table 3. CB-C8VX/VM Die Steps (80 staggered pad pitch) Max. Usable Gates(1) 2 Layer 3 Layer Step I/O 120727 B73T 148 18844 28266 93875 140813 C37T 188 30250 45375 106000 159000 C50T 196 32703 49055 120969 181453 D01T 228 44000 66000 272 136641 204961 D52T 260 57047 85570 G14 288 153500 230250 D90T 284 67797 101695 G53 304 171234 256852 E54T 324 88281 132422 G93 320 183078 274617 F18T 364 109125 163688 H33 336 202328 303492 F70T 396 128875 193313 H72 352 222219 333328 G34T 436 155297 232945 J32 376 254094 381141 H49T 508 202766 304148 J71 392 275813 413719 J51T 572 256047 384070 K11 408 298797 448195 K92T 660 337531 506297 K90 440 347031 520547 M97T 788 468984 703477 Single pad ring die steps. (1) Glue logic only, with average utilization. 2 NEC's CB-C8VX/VM Ti-Silicide process features exceptionally low power dissipation to facilitate highspeed operation without the need of costly package options, and drastically increases battery life for handheld applications. At 3.3-volts, power dissipation for internal cells is 1.04 W/gate/MHz. Dual pad ring die steps. (1) Glue logic only, with average utilization. CB-C8VX/VM Multi-Voltage I/O Interface System on Silicon For those systems not yet ready to migrate completely to 3.3-volts, CB-C8 has a full 5-volt CMOS interface available. Applying two additional process steps that realize a "multi-oxide" section in the I/O area, 5-volt speed and drive capabilities are available with the help of a separate 5-volt supply rail. The 5-volt I/O buffers include level shifters to convert the 5-volt signal levels to the internal core supply voltage of 3.3-volts. This CB-C8 derivative is called CB-C8VM and is, except for the different I/O structure, identical to CB-C8VX. NEC offers a wide selection of CPU/MCU cores, industrystandard intelligent peripheral macros, and compilable RAM/ROM blocks as well as analog functions in hard macro form that can be integrated onto a single CBC8VX/VM chip. Including such macrofunctions in an ASIC design makes it possible to achieve a high level of integration, performance, and system security. For moderate speed and driveable 5-volt I/O cell requirements, CB-C8VM's flexibility provides tolerant I/Os that safely interface to 5V devices using a single 3.3volt power supply. In both cases, the 3.3-volt and 5-volt interfaces can be mixed without restriction along the entire I/O ring. Device Names Interface options CB-C8VX CB-C8VM PD97xxx PD99xxx * true 3.3 V * 5 V tolerant * true 3.3 V * 5 V tolerant * true 5 V CMOS Core voltage 3.3 V 3.3 V I/O voltage 3.3 V 3.3 V and 5 V The range of NEC's on-chip macrofunctions includes NEC's proprietary 32-bit V810TM RISC CPU, and an upgraded high-speed version of the popular 16-bit CPU V30HLTM, called V30MXTM, which operates at clock speeds of 33 MHz at 3.3-volts, and offers an improved 286-compatible address pipelining and uses a 24-bit address bus. Other specific cores can be implemented on request. For details about the full range of on-chip macrofunctions, refer to Table 4. Embedded macrofunctions are easy to place, route, and simulate. Because these macros are derived from NEC's standard parts, they have fully characterized parameters and can be tested with standard test vectors to ensure full functionality and reliability. NEC's test bus architecture allows complete system simulation, production testing of the internal circuits of the macrofunctions, and seamless embedded CPU core emulation. The CPU may be connected externally and can be replaced by an in-circuit emulator (ICE). All this is performed with only two dedicated test control pins. Table 4. Macrofunction Range Macro Comparable Device NZ 70008H PD70008A Z80TM: 8-bit microprocessor (16 MHz) NZ V30MX PD70108H V30MX: 16-bit microprocessor (16-bit data bus, 33 MHz) Description NZ V810 PD70732 V810TM: 32-bit RISC microprocessor (25 MHz) NZ 71037H PD71037 Programmable DMA controller (4 channels, 20 MHz) NZ 71051H PD71051 USART: serial data control (full-duplex Tx/Rx, 300kbit/s, 20 MHz) NZ 71054H PD71054 Programmable timer/counter (16-bit, 3 counter, 6 modes, 20 MHz) NZ 71055H PD71055 Programmable parallel interface (8-bit, 3 I/O ports, 3 modes) NZ 71059H PD71059 Programmable interrupt control (64 interrupt request inputs) NA 4993 PD4993 8-bit parallel I/O real-time clock NA 72065BL NZ 72103 2 M I CTM PD72065B PD72103 -- Single-double density floppy disk controller HDLC Controller: Full duplex, Baud rate 4 Mbps, built-in DMA I2 C Bus interface: receive, transmit, master and slave NA 16450L NS16C450 UART: for PC-compatible serial ports NA 16550L NS16550A UART with FIFO: for PC-compatible serial ports Z80 is a trademark of Zilog, Inc. V30HL, V30MX and v810 are trademarks of NEC Corporation I2 C is a trademark of Philips 3 CB-C8VX/VM Memory Macros All memory blocks in NEC's CB-C8VX/VM technology are realized as embedded hard macros and are generated by a memory compiler. To ease the task of RAM testing for the designer, NEC supplies standard test pattern sets, which help to save valuable development time. NEC offers seven different types of memory blocks, as shown in Table 5. Packaging NEC offers a wide variety of over 60 package types. The CB-C8VX/VM family can be packaged in NEC's most popular surface-mount and through-hole packages. These include plastic quad-flat packs (PQFPs) with up to 376 pins. The QFP range includes thin packages (TQFP, LQFP), QFPs with integrated heatspreader, and tape-automated-bonding QFPs (TAB-QFP) with up to 304 pins. Pin grid arrays (PGAs) with up to 528 pins, BGA packages with up to 672 pins, and TBGA packages with up to 696 pins can be used. mainframes, multimedia platforms, graphic accelerators, personal digital assistants (PDAs), notebook and pen-based devices, hand-held data terminals, and hard disk controllers. Consumer applications include games, video cameras, portable printers, and sophisticated calculators. Each of these applications demands the benefits of increased integration and low power consumption that only a cell-based family using an optimized 3.3volt process technology can deliver. CB-C8VX/VM provides the flexibility needed when a 3.3-volt process is required. Design Tool Support CB-C8VX/VM Applications The CB-C8VX/VM family is fully supported by NEC's OpenCAD Design System, a unified front-to-back-end design package that allows designers to mix and match tools from the industry's most popular third-party vendors and from NEC's offering of powerful proprietary software tools. These tools perform schematic capture, logic synthesis, floorplanning, logic and timing simulation, layout, design and circuit rule check, and memory compilations. CB-C8VX/VM devices are targeted for 3.3-volt products in telecommunications, electronic data processing (EDP), and consumer applications. Typical telecommunications applications include cellular telephones, high-end pagers, and PCMCIA devices, as well as broad-band communication systems up to 156 Mbit/s. In the EDP segment, applications range from personal computers to high-end workstations and The company's proprietary clock tree synthesis tool automatically buffers clock lines as needed to minimize clock skew, which is essential for half-micron designs. The nonlinear delay calculator ensures timing accuracy throughout the simulation, synthesis, and silicon stages. Finally, NEC's memory compiler software enables memory block generation based on size and performance requirements. Table 5. Memory Blocks Macro Type 4 Word Range Bit Range Step (Word / Bit) ROM 128 - 8192 256 - 16384 512 - 32768 4 - 64 2 - 32 1 - 16 128 / 2 256 / 1 512 / 1 Low-power RAM, single-port (asynchronous, bi-directional I/O) 64 - 512 128 - 1024 256 - 2048 1 - 32 1 - 16 1-8 16 / 1 32 / 1 64 / 1 Low-power RAM, single-port (synchronous, separate I/O) 64 - 512 128 - 1024 256 - 2048 1 - 32 1 - 16 1-8 16 / 1 32 / 1 64 / 1 High-density RAM, single-port (synchronous, separate I/O) 128 - 2048 1 - 64 16 / 1 High-speed RAM, single-port (synchronous, separate I/O) 32 - 2048 1- 32 32 / 1 Register files, dual-port 8 - 256 4 - 32 4/1 Register files, triple-port 8 - 256 4 - 32 4/1 CB-C8VX/VM Absolute Maximum Ratings Input/Output Capacitance Terminal Power supply voltage, V DD (VDD = VI = 0 V; f = 1 MHz) Symbol Typ Max Unit CIN 10 20 pF 3.3 V supply -0.5 to +4.6 V Input 5 V supply -0.5 to +6.0 V Output COUT 10 20 pF I/O CI/O 10 20 pF I/O voltage, VI/VO (1) 3.3 V interface block -0.5 to +4.6 V and (VI/VO < VDD +0.5 V) 5 V-tolerant block -0.5 to +6.6 V and (VI/VO < VDD +3.0 V) 5 V swing block -0.5 to +6.0 V and (VI/VO < VDD +0.5 V) Latch-up current, I LATCH Power Consumption Description >1 A (typ) Operating temperature, TOPT Internal gate(1) -40 to +85C Storage temperature, TSTG Values include package pin capacitance -65 to +150C (1) Caution: Exposure to absolute maximum ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The device should not be operated outside the recommended operating conditions. Parameter Unit 1.04 W/MHz Input block -- W/MHz Output block -- W/MHz Assumes 30% internal gate switching at one time Caution: Exposure to absolute maximum ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The device should not be operated outside the recommended operating conditions. Recommended Operating Conditions (VDD = 3.3 V 0.165 V; VCC = 5.0 V 0.5 V; 3.3 V Interface Block Limits 5 V Tolerant Block (CB-C8VX/VM) TJ = -40 to +125C) 5 V Swing CMOS Level (CB-C8VM) 5 V Swing TTL Level (CB-C8 VM) Symbol Min Max Min Max Min Max Min Max Unit VDD 3.0 3.6 3.0 3.6 4.5 5.5 4.75 5.25 V Junction temperature TJ -40 +125 -40 +125 -40 +125 -40 +125 C High-level input voltage VIH 2.0 VDD 2.0 5.5 0.7 VDD VDD 2.0 VDD V Low-level input voltage VIL 0 0.8 0 0.8 0 0.3 VDD 0 0.8 V Positive trigger voltage VP 1.2 2.4 1.2 2.4 1.8 4.0 1.2 2.4 V Negative trigger voltage VN 0.6 1.8 0.6 1.8 0.6 3.1 0.6 1.8 V Hysteresis voltage VH 0.3 1.5 0.3 1.5 0.3 1.5 0.3 1.5 V Input rise/fall time tR, tF 0 200 0 200 0 200 0 200 ns Input rise/fall time, Schmitt t R, tF 0 10 0 10 0 10 0 10 ms I/O power supply voltage AC Characteristics (VDD = 3.3 V 0.3 V; TJ = -40 to +125C) Parameter Symbol Unit Conditions Toggle frequency fTOG 480 MHz D-F/F; F/O = 2 mm 2-input NAND (F322) tPD tPD 236 272 ps ps F/O = 1; L = 0 mm F/O = 2; L = typ Flip-flop (F661) tPD tPD tSETUP tHOLD 777 865 420 580 ps ps ps ps F/O = 1; L = 0 mm F/O = 2; L = typ -- -- Input buffer (FI01) tPD tPD 126 228 ps ps F/O = 1; L = 0 mm F/O = 2; L = typ Min Typ Max Delay time Output buffer (9 mA) 3.3 V tPD 1.24 ns CL = 15 pF Output buffer (9 mA) 5 V-tolerant t PD 4.262 ns CL = 15 pF Output buffer (6 mA) 5 V-swing tPD 2.698 ns CL = 15 pF Output rise time (9 mA) tR 1.88 ns CL = 15 pF Output fall time (9 mA) tF 1.32 ns CL = 15 pF 5 CB-C8VX/VM DC Characteristics (VDD = 3.3 V 0.3 V, 5 V 0.5 V; TA = -40 to +125C) Parameters Static current consumption Symbol IL Conditions TYP. MAX. Unit VI = VDD B18 to H33 200 A or GND H72 to K90 300 A Off-state output current IOZ VO = VDD or GND Output short-circuit current IOS VO = 0V Input leakage current MIN. 10 A -250 mA 10 A II Normal input 10-5 VI = VDD or GND With pull-up resistor (50 ky) VI = GND -10 -40 -80 A With pull-up resistor (5 ky) VI = GND -130 -350 -640 A With pull-down resistor (50 ky) VI = VDD 10 65 130 A Low-level output current IOL 3 V interface buffer VOL = 0.4V mA 3 mA IOL 3 mA 6 mA IOL 6 mA 9 mA IOL 9 mA 12 mA IOL 12 mA 18 mA IOL 18 mA 24 mA IOL 5 V-tolerant buffer 24 VOL = 0.4V mA mA 1 mA IOL 1 mA 2 mA IOL 2 mA 3 mA IOL 3 mA 6 mA IOL 6 mA 9 mA IOL 9 mA 5 V swing buffer VOL = 0.4V mA 1 mA IOL 1 mA 2 mA IOL 2 mA 3 mA IOL 3 mA 6 mA IOL 6 mA 9 mA IOL 9 mA 12 mA IOL 12 mA 18 mA IOL 18 mA High-level output current IOH 3 V interface buffer 6 VOH = 2.4V 3 mA IOH -3 mA 6 mA IOH -6 mA 9 mA IOH -9 mA 12 mA IOH -12 mA 18 mA IOH -18 mA 24 mA IOH -24 mA CB-C8VX/VM DC Characteristics (continued) (VDD = 3.3 V 0.3 V, 5 V 0.5 V; TA = -40 to +125C) Parameters High-level output current Symbol Conditions MIN. TYP. MAX. Unit IOH 5 V-tolerant buffer VOH = 2.4 V 1 mA IOH -1 mA 2 mA IOH -2 mA 3 mA IOH -3 mA 6 mA IOH -6 mA 9 mA IOH -9 mA 5 V swing buffer VOH = -0.4 V 1 mA IOH -1 mA 2 mA IOH -2 mA 3 mA IOH -3 mA 6 mA IOH -6 mA 9 mA IOH -9 mA 12 mA IOH -12 mA 18 mA IOH -18 mA Low-level output voltage VOL IOL = 0 mA 0.1 V 3 V interface buffer VOL 0.1 V 5 V interface buffer VOL 0.1 V 5 V swing buffer VOL 0.1 V High-level output voltage VOH 3 V interface buffer IOH = 0 mA V VOH VDD-0.1 V 5 V interface buffer VOH VDD-0.2 V 5 V swing buffer VOH VDD-0.1 V 7 CB-C8VX/VM NEC ASIC DESIGN CENTERS WEST SOUTH CENTRAL/SOUTHEAST NORTH CENTRAL/NORTHEAST * 3033 Scott Boulevard Santa Clara, CA 95054 * 16475 Dallas Parkway, Suite 380 Dallas, TX 75248 * The Meadows, 2nd Floor 161 Worcester Road Framingham, MA 01701 TEL 408-588-5008 FAX 408-588-5017 TEL 972-735-7444 FAX 972-931-8680 * One Embassy Centre 9020 S.W. Washington Square Road, Suite 400 Tigard, OR 97223 * Research Triangle Park 2000 Regency Parkway, Suite 455 Cary, NC 27511 TEL 919-460-1890 FAX 919-469-5926 TEL 503-671-0177 FAX 503-643-5911 TEL 508-935-2200 FAX 508-935-2234 * Greenspoint Tower 2800 W. Higgins Road, Suite 765 Hoffman Estates, IL 60195 TEL 708-519-3945 FAX 708-882-7564 * Two Chasewood Park 20405 SH 249, Suite 580 Houston, TX 77070 TEL 713-320-0524 FAX 713-320-0574 THIRD-PARTY DESIGN CENTERS SOUTH CENTRAL/SOUTHEAST * Koos Technical Services, Inc. 385 Commerce Way, Suite 101 Longwood, FL 32750 TEL 407-260-8727 FAX 407-260-6227 * Integrated Silicon Systems Inc. 2222 Chapel Hill Nelson Highway Durham, NC 27713 TEL 919-361-5814 FAX 919-361-2019 * Applied Systems, Inc. 1761 W. Hillsboro Blvd., Suite 328 Deerfield Beach, FL 33442 TEL 305-428-0534 FAX 305-428-5906 For literature, call toll-free 7 a.m. to 6 p.m. Pacific time: 1-800-366-9782 or FAX your request to: 1-800-729-9288 NEC Electronics Inc. CORPORATE HEADQUARTERS 2880 Scott Boulevard P.O. Box 58062 Santa Clara, CA 95052 TEL 408-588-6000 8(c)1996 NEC Electronics Inc./Printed in U.S.A. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics Inc. (NECEL). The information in this document is subject to change without notice. ALL DEVICES SOLD BY NECEL ARE COVERED BY THE PROVISIONS APPEARING IN NECEL TERMS AND CONDITIONS OF SALES ONLY. INCLUDING THE LIMITATION OF LIABILITY, WARRANTY, AND PATENT PROVISIONS. NECEL makes no warranty, express, statutory, implied or by description, regarding information set forth herein or regarding the freedom of the described devices from patent infringement. NECEL assumes no responsibility for any errors that may appear in this document. NECEL makes no commitments to update or to keep current information contained in this document. The devices listed in this document are not suitable for use in applications such as, but not limited to, aircraft control systems, aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. "Standard" quality grade devices are recommended for computers, office equipment, communication equipment, test and measurement equipment, machine tools, industrial robots, audio and visual equipment, and other consumer products. For automotive and transportation equipment, traffic control systems, antidisaster and anti-crime systems, it is recommended that the customer contact the responsible NECEL salesperson to determine the reliabilty requirements for any such application and any cost adder. NECEL does not recommend or approve use of any of its products in life support devices or systems or in any application where failure could result in injury or death. If customers wish to use NECEL devices in applications not intended by NECEL, customer must contact the responsible NECEL sales people to determine NECEL's willingness to support a given application. Document No. A10985EU1V0DS00