A3PE600-2FG256I - MICROCHIP TECHNOLOGY

April 2007 i

ProASIC®3E Flash Family FPGAs

with Optional Soft ARM® Support

Features and Benefits

High Capacity

• 600 k to 3 Million System Gates

• 108 to 504 kbits of True Dual-Port SRAM

• Up to 616 User I/Os

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS

Process

• Live at Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• Retains Programmed Design when Powered Off

On-Chip User Nonvolatile Memory

• 1 kbit of FlashROM with Synchronous Interfacing

High Performance

• 350 MHz System Performance

• 3.3 V, 66 MHz 64-Bit PCI

In-System Programming (ISP) and Security

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

Standard (AES) Decryption via JTAG (IEEE 1532–

compliant)

•FlashLock

® to Secure FPGA Contents

Low Power

• Core Voltage for Low Power

• Support for 1.5-V-Only Systems

• Low-Impedance Flash Switches

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

• Ultra-Fast Local and Long-Line Network

• Enhanced High-Speed, Very-Long-Line Network

• High-Performance, Low-Skew Global Network

• Architecture Supports Ultra-High Utilization

Pro (Professional) I/O

• 700 Mbps DDR, LVDS-Capable I/Os

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—Up to 8 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and

LVCMOS 2.5 V / 5.0 V Input

• Differential I/O Standards: LVPECL, LVDS, BLVDS, and

M-LVDS

• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V,

GTL 2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II,

SSTL3 Class I and II

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold Sparing I/Os

• Programmable Output Slew Rate and Drive Strength

• Programmable Input Delay

• Schmitt Trigger Option on Single-Ended Inputs

• Weak Pull-Up/Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages Across the ProASIC3E Family

Clock Conditioning Circuit (CCC) and PLL

• Six CCC Blocks, Each with an Integrated PLL

• Configurable Phase-Shift, Multiply/Divide, Delay

Capabilities and External Feedback, Multiply/Divide,

Delay Capabilities, and External Feedback

• Wide Input Frequency Range (1.5 MHz to 200 MHz)

• CoreMP7Sd (with debug) and CoreMP7S (without debug

SRAMs and FIFOs

• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2,

×4, ×9, and ×18 Organizations Available)

• True Dual-Port SRAM (except ×18)

• 24 SRAM and FIFO Configurations with Synchronous

Operation up to 350 MHz

Soft ARM7™ Core Support in M7 ProASIC3E Devices

• CoreMP7Sd (with debug) and CoreMP7S (without

debug)

Table 1 • ProASIC3E Product Family

ProASIC3E Devices A3PE600 A3PE1500 A3PE3000

ARM-Enabled ProASIC3E Devices1M7A3PE600 M7A3PE1500 M7A3PE3000

System Gates 600 k 1.5 M 3 M

VersaTiles (D-flip-flops) 13,824 38,400 75,264

RAM kbits (1,024 bits) 108 270 504

4,608-Bit Blocks 24 60 112

FlashROM Bits 1 k 1 k 1 k

Secure (AES) ISP Yes Yes Yes

CCCs with Integrated PLLs266 6

VersaNet Globals318 18 18

I/O Banks 88 8

Maximum User I/Os 270 444 616

Package Pins

PQFP

FBGA

PQ208

FG256, FG484

PQ208

FG484, FG676

PQ208

FG484, FG896

Notes:

1. Refer to the CoreMP7 datasheet for more information.

2. The PQ208 package has six CCCs and two PLLs.

3. Six chip (main) and three quadrant global networks are available.

4. For devices supporting lower densities, refer to the ProASIC3 Flash FPGAs datasheet.

v2.0

ProASIC3E Flash Family FPGAs

ii v2.0

I/Os Per Package1

Packaging Tables

Pinout tables not published in this document will be added in future revisions of the datasheet. For updates, contact

our local sales office.

ProASIC3E Devices A3PE600 A3PE1500 3A3PE3000 3

ARM-Enabled

ProASIC3E Devices M7A3PE600 M7A3PE1500 M7A3PE3000

Package

I/O Types

Single-Ended

I/O1Differential

I/O Pairs

Single-Ended

I/O1Differential

I/O Pairs

Single-Ended

I/O1Differential

I/O Pairs

PQ208 147 65 147 65 147 65

FG256 165 79 – – – –

FG484 270 135 280 139 280 136

FG676 – – 444 222 – –

FG896 – – – – 616 300

Notes:

1. When considering migrating your design to a lower- or higher-density device, refer to "Package Pin Assignments" starting on page

4-1 to ensure compliance with design and board migration requirements.

2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.

3. For A3PE1500 and A3PE3000 devices, the usage of certain I/O standards is limited as follows:

– SSTL3(I) and (II): up to 40 I/Os per north or south bank

– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank

– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank

4. FG256 and FG484 are footprint-compatible packages.

5. When using voltage-referenced I/O standards, one I/O pin should be assigned as a voltage-referenced pin (VREF) per minibank

(group of I/Os).Refer to the "I/O Banks and I/O Standards Compatibility" section on page 2-28 for more information about VREF and

the use of minibanks

6. "G" indicates RoHS-compliant packages. Refer to the "ProASIC3E Ordering Information" on page iii for the location of the "G" in

the part number.

ProASIC3E Flash Family FPGAs

v2.0 iii

ProASIC3E Ordering Information

Note: *The DC and switching characteristics for the –F speed grade targets are based only on simulation.

The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some restrictions

might be added and will be reflected in future revisions of this document. The –F speed grade is only supported in the commercial

temperature range.

A3PE3000 FG

Part Number

Speed Grade

Blank = Standard

1 = 15% Faster than Standard

2 = 25% Faster than Standard

F = 20% Slower than Standard*

Package Type

PQ =Plastic Quad Flat Pack (0.5 mm pitch)

FG =Fine Pitch Ball Grid Array (1.0 mm pitch)

896 I

Package Lead Count

Application (Temperature Range)

Blank = Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

PP = Pre-Production

ES = Engineering Sample (Room Temperature Only)

600,000 System Gates

A3PE600 =

1,500,000 System Gates

A3PE1500 =

3,000,000 System Gates

A3PE3000 =

600,000 System Gates

M7A3PE600 =

1,500,000 System Gates

M7A3PE1500 =

3,000,000 System Gates

M7A3PE3000 =

Lead-Free Packaging

Blank = Standard Packaging

G = RoHS-Compliant (Green) Packaging

ProASIC3E Devices

ARM-Enabled ProASIC3E Devices

ProASIC3E Flash Family FPGAs

iv v2.0

Temperature Grade Offerings

Speed Grade and Temperature Grade Matrix

Datasheet references made to ProASIC3E devices also apply to ARM-enabled ProASIC3E devices. The ARM-enabled

part numbers start with M7.

Contact your local Actel representative for device availability (http://www.actel.com/contact/default.aspx).

Package

A3PE600 A3PE1500 A3PE3000

M7A3PE600 M7A3PE1500 M7A3PE3000

PQ208 C, IC, IC, I

FG256 C, I – –

FG484 C, I C, I C, I

FG676 – C, I –

FG896 – – C, I

Note: C = Commercial temperature range: 0°C to 70°C

I = Industrial temperature range: –40°C to 85°C

Temperature Grade –F 1Std. –1 –2

C2✓✓✓✓

I3–✓✓✓

Notes:

1. The DC and switching characteristics for the –F speed grade targets are based only on simulation.

The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some restrictions

might be added and will be reflected in future revisions of this document. The –F speed grade is only supported in the commercial

temperature range.

2. C = Commercial temperature range: 0°C to 70°C

3. I = Industrial temperature range: –40°C to 85°C

v2.0 1

Table of Contents

ProASIC3E Flash Family FPGAs

Introduction and Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Device Architecture

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51

Software Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53

Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53

Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53

ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54

DC and Switching Characteristics

General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60

Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-64

Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67

Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-79

JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-80

Package Pin Assignments

208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

676-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23

896-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

ProASIC3E Flash Family FPGAs

v2.0 1-1

Introduction and Overview

General Description

ProASIC3E, the third-generation family of Actel Flash

FPGAs, offers performance, density, and features beyond

those of the ProASICPLUS® family. Nonvolatile Flash

technology gives ProASIC3E devices the advantage of

being a secure, low-power, single-chip solution that is

live at power-up (LAPU). ProASIC3E is reprogrammable

and offers time-to-market benefits at an ASIC-level unit

cost. These features enable designers to create high-

density systems using existing ASIC or FPGA design flows

and tools.

ProASIC3E devices offer 1 kbit of on-chip,

programmable, nonvolatile FlashROM storage as well as

clock conditioning circuitry based on six integrated

phase-locked loops (PLLs). ProASIC3E devices have up to

three million system gates, supported with up to

504 kbits of true dual-port SRAM and up to 616 user I/Os.

All ProASIC3E devices support the ARM7 soft IP core, and

the ARM-enabled devices have Actel ordering numbers

that begin with M7A3PE.

Flash Advantages

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost,

performance, and ease of use. Unlike SRAM-based

FPGAs, Flash-based ProASIC3E devices allow all

functionality to be live at power-up; no external boot

PROM is required. On-board security mechanisms

prevent access to all the programming information and

enable secure remote updates of the FPGA logic.

Designers can perform secure remote in-system

reprogramming to support future design iterations and

field upgrades with confidence that valuable intellectual

property (IP) cannot be compromised or copied. Secure

ISP can be performed using the industry-standard AES

algorithm. The ProASIC3E family device architecture

mitigates the need for ASIC migration at higher user

volumes. This makes the ProASIC3E family a cost-

effective ASIC replacement solution, especially for

applications in the consumer, networking/

communications, computing, and avionics markets.

Security

The nonvolatile, Flash-based ProASIC3E devices do not

require a boot PROM, so there is no vulnerable external

bitstream that can be easily copied. ProASIC3E devices

incorporate FlashLock, which provides a unique

combination of reprogrammability and design security

without external overhead, advantages that only an

FPGA with nonvolatile Flash programming can offer.

ProASIC3E devices utilize a 128-bit Flash-based lock and a

separate AES key to secure programmed intellectual

property and configuration data. In addition, all

FlashROM data in ProASIC3E devices can be encrypted

prior to loading, using the industry-leading AES-128

(FIPS192) bit block cipher encryption standard. The AES

standard was adopted by the National Institute of

Standards and Technology (NIST) in 2000 and replaces

the 1977 DES standard. ProASIC3E devices have a built-in

AES decryption engine and a Flash-based AES key that

make them the most comprehensive programmable logic

device security solution available today. ProASIC3E

devices with AES-based security allow for secure, remote

field updates over public networks such as the Internet,

and ensure that valuable IP remains out of the hands of

system overbuilders, system cloners, and IP thieves. The

contents of a programmed ProASIC3E device cannot be

read back, although secure design verification is possible.

Security, built into the FPGA fabric, is an inherent

component of the ProASIC3E family. The Flash cells are

located beneath seven metal layers, and many device

design and layout techniques have been used to make

invasive attacks extremely difficult. The ProASIC3E

family, with FlashLock and AES security, is unique in

being highly resistant to both invasive and noninvasive

attacks. Your valuable IP is protected and secure, making

remote ISP possible. An ProASIC3E device provides the

most impenetrable security for programmable logic

designs.

Single Chip

Flash-based FPGAs store their configuration information

in on-chip Flash cells. Once programmed, the

configuration data is an inherent part of the FPGA

structure, and no external configuration data needs to

be loaded at system power-up (unlike SRAM-based

FPGAs). Therefore, Flash-based ProASIC3E FPGAs do not

require system configuration components such as

EEPROMs or microcontrollers to load device

configuration data. This reduces bill-of-materials costs

and PCB area, and increases security and system

reliability.

ProASIC3E Flash Family FPGAs

1-2 v2.0

Live at Power-Up

The Actel Flash-based ProASIC3E devices support Level 0

of the LAPU classification standard. This feature helps in

system component initialization, execution of critical

tasks before the processor wakes up, setup and

configuration of memory blocks, clock generation, and

bus activity management. The LAPU feature of Flash-

based ProASIC3E devices greatly simplifies total system

design and reduces total system cost, often eliminating

the need for CPLDs and clock generation PLLs that are

used for these purposes in a system. In addition, glitches

and brownouts in system power will not corrupt the

ProASIC3E device's Flash configuration, and unlike

SRAM-based FPGAs, the device will not have to be

reloaded when system power is restored. This enables

the reduction or complete removal of the configuration

PROM, expensive voltage monitor, brownout detection,

and clock generator devices from the PCB design. Flash-

based ProASIC3E devices simplify total system design and

reduce cost and design risk while increasing system

reliability and improving system initialization time.

"I/O Power-Up and Supply Voltage Thresholds for Power-

On Reset (Commercial and Industrial)" section on page 3-

Firm Errors

Firm errors occur most commonly when high-energy

neutrons, generated in the upper atmosphere, strike a

configuration cell of an SRAM FPGA. The energy of the

collision can change the state of the configuration cell

and thus change the logic, routing, or I/O behavior in an

unpredictable way. These errors are impossible to

prevent in SRAM FPGAs. The consequence of this type of

error can be a complete system failure. Firm errors do

not exist in the configuration memory of ProASIC3E

Flash-based FPGAs. Once it is programmed, the Flash cell

configuration element of ProASIC3E FPGAs cannot be

altered by high-energy neutrons and is therefore

immune to them. Recoverable (or soft) errors occur in

the user data SRAM of all FPGA devices. These can easily

be mitigated by using error detection and correction

(EDAC) circuitry built into the FPGA fabric.

Low Power

Flash-based ProASIC3E devices exhibit power

characteristics similar to an ASIC, making them an ideal

choice for power-sensitive applications. ProASIC3E

devices have only a very limited power-on current surge

and no high-current transition period, both of which

occur on many FPGAs.

ProASIC3E devices also have low dynamic power

consumption to further maximize power savings.

Advanced Flash Technology

The ProASIC3E family offers many benefits, including

nonvolatility and reprogrammability through an

advanced Flash-based, 130-nm LVCMOS process with

seven layers of metal. Standard CMOS design techniques

are used to implement logic and control functions. The

combination of fine granularity, enhanced flexible

routing resources, and abundant Flash switches allows

for very high logic utilization without compromising

device routability or performance. Logic functions within

the device are interconnected through a four-level

routing hierarchy.

Advanced Architecture

The proprietary ProASIC3E architecture provides

granularity comparable to standard-cell ASICs. The

ProASIC3E device consists of five distinct and

programmable architectural features (Figure 1-1):

• FPGA VersaTiles

• Dedicated FlashROM

• Dedicated SRAM/FIFO memory

• Extensive CCCs and PLLs

• Pro I/O structure

The FPGA core consists of a sea of VersaTiles. Each

VersaTile can be configured as a three-input logic

function, a D-flip-flop (with or without enable), or a

latch by programming the appropriate Flash switch

interconnections. The versatility of the ProASIC3E core

tile as either a three-input lookup table (LUT) equivalent

or as a D-flip-flop/latch with enable allows for efficient

use of the FPGA fabric. The VersaTile capability is unique

to the Actel ProASIC family of third-generation

architecture Flash FPGAs. VersaTiles are connected with

any of the four levels of routing hierarchy. Flash switches

are distributed throughout the device to provide

nonvolatile, reconfigurable interconnect programming.

Maximum core utilization is possible for virtually any

design.

In addition, extensive on-chip programming circuitry

allows for rapid, single-voltage (3.3 V) programming of

ProASIC3E devices via an IEEE 1532 JTAG interface.

ProASIC3E Flash Family FPGAs

v2.0 1-3

VersaTiles

The ProASIC3E core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS® core tiles. The

ProASIC3E VersaTile supports the following:

• All 3-input logic functions—LUT-3 equivalent

• Latch with clear or set

• D-flip-flop with clear or set

• Enable D-flip-flop with clear or set

Refer to Figure 1-2 for VersaTile configurations.

For more information about VersaTiles, refer to the "VersaTile" section on page 2-2.

Figure 1-1 • ProASIC3E Device Architecture Overview

4,608-Bit Dual-Port SRAM

or FIFO Block

VersaTile

RAM Block

CCC

Pro I/Os

ISP AES Decryption User Nonvolatile

FlashROM Charge Pumps

4,608-Bit Dual-Port SRAM

or FIFO Block

RAM Block

Figure 1-2 • VersaTile Configurations

LUT-3

Data Y

CLK

Enable

CLR

D-FF

Data Y

CLK

CLR

D-FF

LUT-3 Equivalent D-Flip-Flop with Clear or Set Enable D-Flip-Flop with Clear or Set

ProASIC3E Flash Family FPGAs

1-4 v2.0

User Nonvolatile FlashROM

Actel ProASIC3E devices have 1 kbit of on-chip, user-

accessible, nonvolatile FlashROM. The FlashROM can be

used in diverse system applications:

• Internet protocol addressing (wireless or fixed)

• System calibration settings

• Device serialization and/or inventory control

• Subscription-based business models (for example,

set-top boxes)

• Secure key storage for secure communications

algorithms

• Asset management/tracking

• Date stamping

• Version management

The FlashROM is written using the standard ProASIC3E

IEEE 1532 JTAG programming interface. The core can be

individually programmed (erased and written), and on-

chip AES decryption can be used selectively to securely

load data over public networks, as in security keys stored

in the FlashROM for a user design.

The FlashROM can be programmed via the JTAG

programming interface, and its contents can be read

back either through the JTAG programming interface or

via direct FPGA core addressing. Note that the FlashROM

can only be programmed from the JTAG interface and

cannot be programmed from the internal logic array.

The FlashROM is programmed as 8 banks of 128 bits;

however, reading is performed on a byte-by-byte basis

using a synchronous interface. A 7-bit address from the

FPGA core defines which of the 8 banks and which of the

16 bytes within that bank are being read. The three most

significant bits (MSBs) of the FlashROM address

determine the bank, and the four least significant bits

(LSBs) of the FlashROM address define the byte.

The Actel ProASIC3E development software solutions,

Libero® Integrated Design Environment (IDE) and

Designer, have extensive support for the FlashROM. One

such feature is auto-generation of sequential

programming files for applications requiring a unique

serial number in each part. Another feature allows the

inclusion of static data for system version control. Data

for the FlashROM can be generated quickly and easily

using Actel Libero IDE and Designer software tools.

Comprehensive programming file support is also

included to allow for easy programming of large

numbers of parts with differing FlashROM contents.

SRAM and FIFO

ProASIC3E devices have embedded SRAM blocks along

their north and south sides. Each variable-aspect-ratio

SRAM block is 4,608 bits in size. Available memory

configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1

bits. The individual blocks have independent read and

write ports that can be configured with different bit

widths on each port. For example, data can be sent

through a 4-bit port and read as a single bitstream. The

embedded SRAM blocks can be initialized via the device

JTAG port (ROM emulation mode) using the UJTAG

macro.

In addition, every SRAM block has an embedded FIFO

control unit. The control unit allows the SRAM block to

be configured as a synchronous FIFO without using

additional core VersaTiles. The FIFO width and depth are

programmable. The FIFO also features programmable

Almost Empty (AEMPTY) and Almost Full (AFULL) flags in

addition to the normal Empty and Full flags. The

embedded FIFO control unit contains the counters

necessary for generation of the read and write address

pointers. The embedded SRAM/FIFO blocks can be

cascaded to create larger configurations.

PLL and CCC

ProASIC3E devices provide designers with very flexible

clock conditioning capabilities. Each member of the

ProASIC3E family contains six CCCs, each with an

integrated PLL.

The six CCC blocks are located at the four corners and the

centers of the east and west sides.

To maximize user I/Os, only the center east and west PLLs

are available in devices using the PQ208 package.

However, all six CCC blocks are still usable; the four

corner CCCs allow simple clock delay operations as well

as clock spine access (refer to the "Clock Conditioning

Circuits" section on page 2-13 for more information).

The inputs of the six CCC blocks are accessible from the

FPGA core or from one of several inputs located near the

CCC that have dedicated connections to the CCC block.

The CCC block has these key features:

• Wide input frequency range (fIN_CCC) = 1.5 MHz to

350 MHz

• Output frequency range (fOUT_CCC) = 0.75 MHz to

350 MHz

• Clock delay adjustment via programmable and

fixed delays from –7.56 ns to +11.12 ns

ProASIC3E Flash Family FPGAs

v2.0 1-5

• 2 programmable delay types for clock skew

minimization; refer to Figure 2-16 on page 2-17,

Table 2-4 on page 2-18, and the"Features

Supported on Every I/O" section on page 2-31 for

more information.

• Clock frequency synthesis

Additional CCC specifications:

• Internal phase shift = 0°, 90°, 180°, and 270°.

Output phase shift depends on the output divider

configuration.

• Output duty cycle = 50% ± 1.5% or better

• Low output jitter: worst case < 2.5% × clock period

peak-to-peak period jitter when single global

network used

• Maximum acquisition time = 300 µs

• Low power consumption of 5 mW

• Exceptional tolerance to input period jitter—

allowable input jitter is up to 1.5 ns

• Four precise phases; maximum misalignment

between adjacent phases of 40 ps × (350 MHz /

fOUT_CCC)

Global Clocking

ProASIC3E devices have extensive support for multiple

clocking domains. In addition to the CCC and PLL support

described above, there is a comprehensive global clock

distribution network.

Each VersaTile input and output port has access to nine

VersaNets: six chip (main) and three quadrant global

networks (Figure 2-9 on page 2-9). The VersaNets can be

driven by the CCC or directly accessed from the core via

multiplexers (MUXes). The VersaNets can be used to

distribute low-skew clock signals or for rapid distribution

of high fanout nets.

Pro I/Os with Advanced I/O Standards

The ProASIC3E family of FPGAs features a flexible I/O

structure, supporting a range of voltages (1.5 V, 1.8 V,

2.5 V, and 3.3 V). ProASIC3E FPGAs support 19 different

I/O standards, including single-ended, differential, and

voltage-referenced. For more information, see Table 2-23

on page 2-49.

The I/Os are organized into banks, with eight banks per

device (two per side). The configuration of these banks

determines the I/O standards supported (see Table 2-14

on page 2-30 for more information). Each I/O bank is

subdivided into VREF minibanks, which are used by

voltage-referenced I/Os. VREF minibanks contain 8 to 18

I/Os. All the I/Os in a given minibank share a common

VREF line. Therefore, if any I/O in a given VREF minibank is

configured as a VREF pin, the remaining I/Os in that

minibank will be able to use that reference voltage.

Each I/O module contains several input, output, and

enable registers (Figure 2-24 on page 2-33). These

registers allow the implementation of the following:

• Single-Data-Rate applications (e.g., PCI 66 MHz,

bidirectional SSTL 2 and 3, Class I and II)

• Double-Data-Rate applications (e.g., DDR LVDS,

BLVDS, and M-LVDS I/Os for point-to-point

communications, and DDR 200 MHz SRAM using

bidirectional HSTL Class II). See the "DDR Module

Specifications" section on page 3-56.

ProASIC3E banks support M-LVDS with 20 multi-drop

points.

ProASIC3E Flash Family FPGAs

1-6 v2.0

Related Documents

Application Notes

ProASIC3/E I/O Usage Guide

http://www.actel.com/documents/PA3_E_IO_AN.pdf

In-System Programming (ISP) in ProASIC3/E Using FlashPro3

http://www.actel.com/documents/PA3_E_ISP_AN.pdf

ProASIC3/E FlashROM

http://www.actel.com/documents/PA3_E_FROM_AN.pdf

ProASIC3/E Security

http://www.actel.com/documents/PA3_E_Security_AN.pdf

ProASIC3/E SRAM/FIFO Blocks

http://www.actel.com/documents/PA3_E_SRAMFIFO_AN.pdf

Programming a ProASIC3/E Using a Microprocessor

http://www.actel.com/documents/PA3_E_Microprocessor_AN.pdf

UJTAG Applications in ProASIC3/E Devices

http://www.actel.com/documents/PA3_E_UJTAG_AN.pdf

Using DDR for ProASIC3/E Devices

http://www.actel.com/documents/PA3_E_DDR_AN.pdf

Using Global Resources in Actel ProASIC3/E Devices

http://www.actel.com/documents/PA3_E_Global_AN.pdf

Power-Up/Down Behavior of ProASIC3/E Devices

http://www.actel.com/documents/ProASIC3_E_PowerUp_AN.pdf

For additional ProASIC3E application notes, go to http://www.actel.com/techdocs/an.aspx.

User’s Guides

SmartGen Cores Reference Guide

http://www.actel.com/documents/genguide_ug.pdf

Designer User’s Guide

http://www.actel.com/documents/designer_ug.pdf

ProASIC3/E Macro Library Guide

http://www.actel.com/documents/pa3_libguide_ug.pdf

ProASIC3E Flash Family FPGAs

v2.0 2-1

Device Architecture

Introduction

Flash Technology

Advanced Flash Switch

Unlike SRAM FPGAs, the ProASIC3E family uses a live at

power-up ISP Flash switch as its programming element.

Flash cells are distributed throughout the device to

provide nonvolatile, reconfigurable programming to

connect signal lines to the appropriate VersaTile inputs

and outputs. In the Flash switch, two transistors share

the floating gate, which stores the programming

information (Figure 2-1). One is the sensing transistor,

which is only used for writing and verification of the

floating gate voltage. The other is the switching

transistor. The latter is used to connect or separate

routing nets, or to configure VersaTile logic. It is also

used to erase the floating gate. Dedicated high-

performance lines are connected as required using the

Flash switch for fast, low-skew, global signal distribution

throughout the device core. Maximum core utilization is

possible for virtually any design. The use of the Flash

switch technology also removes the possibility of firm

errors, which are increasingly common in SRAM-based

FPGAs.

Figure 2-1 • ProASIC3E Flash-Based Switch

Sensing Switching

Switch In

Switch Out

Word

Floating Gate

ProASIC3E Flash Family FPGAs

2-2 v2.0

Device Overview

The ProASIC3E device family consists of five distinct

programmable architectural features (Figure 2-2):

• FPGA fabric/core (VersaTiles)

• Routing and clock resources (VersaNets)

• FlashROM

• Dedicated SRAM/FIFO memory

• Pro I/O structure

Core Architecture

VersaTile

The proprietary ProASIC3E family architecture provides

granularity comparable to gate arrays. The ProASIC3E

device core consists of a sea-of-VersaTiles architecture.

As illustrated in Figure 2-3 on page 2-3, there are four

inputs in a logic VersaTile cell, and each VersaTile can be

configured using the appropriate Flash switch

connections:

• Any 3-input logic function

• Latch with clear or set

• D-flip-flop with clear or set

• Enable D-flip-flop with clear or set (on a fourth

input)

VersaTiles can flexibly map the logic and sequential gates

of a design. The inputs of the VersaTile can be inverted

(allowing bubble pushing), and the output of the tile can

connect to high-speed, very-long-line routing resources.

VersaTiles and larger functions can be connected with

any of the four levels of routing hierarchy.

When the VersaTile is used as an enable D-flip-flop,

SET/CLR is supported by a fourth input. The SET/CLR

signal can only be routed to this fourth input over the

VersaNet (global) network. However, if in the user’s

design the SET/CLR signal is not routed over the VersaNet

network, a compile warning message will be given and

the intended logic function will be implemented by two

VersaTiles instead of one.

The output of the VersaTile is F2 (Figure 2-3 on page 2-3)

when the connection is to the ultra-fast local lines, or YL

when the connection is to the efficient long-line or very-

long-line resources.

Figure 2-2 • ProASIC3E Device Architecture Overview

4,608-Bit Dual-Port SRAM

or FIFO Block

VersaTile

RAM Block

CCC

Pro I/Os

ISP AES Decryption User Nonvolatile

FlashROM Charge Pumps

4,608-Bit Dual-Port SRAM

or FIFO Block

RAM Block

ProASIC3E Flash Family FPGAs

v2.0 2-3

Note: *This input can only be connected to the global clock distribution network.

Figure 2-3 • ProASIC3E Core VersaTile

Switch (Flash connection) Ground

Via (hard connection)

Legend:

Pin 1

Data

CLK

CLR/

Enable

CLR

XC*

ProASIC3E Flash Family FPGAs

2-4 v2.0

Array Coordinates

During many place-and-route operations in the Actel

Designer software tool, it is possible to set constraints

that require array coordinates. Table 2-1 provides array

coordinates of core cells and memory blocks. The array

coordinates are measured from the lower left (0, 0). They

can be used in region constraints for specific logic

groups/blocks, designated by a wildcard, and can contain

core cells, memories, and I/Os.

I/O and cell coordinates are used for placement

constraints. Two coordinate systems are needed because

there is not a one-to-one correspondence between I/O

cells and core cells. In addition, the I/O coordinate system

changes depending on the die/package combination. It is

not listed in Table 2-1. The Designer ChipPlanner tool

provides array coordinates of all I/O locations. I/O and

cell coordinates are used for placement constraints.

However, I/O placement is easier by package pin

assignment.

Figure 2-4 illustrates the array coordinates of an A3PE600

device. For more information on how to use array

coordinates for region/placement constraints, see the

Designer User's Guide or online help (available in the

software) for ProASIC3E software tools.

Table 2-1 • ProASIC3E Array Coordinates

Device

VersaTiles Memory Rows All

Min. Max. Bottom Top Min. Max.

x y x y (x, y) (x, y) (x, y) (x, y)

A3PE600 3 4 194 75 (3, 2) (3, 76) (0, 0) (197, 79)

A3PE1500 3 4 322 123 (3, 2) (3, 124) (0, 0) (325, 127)

A3PE3000 3 6 450 173 (3, 2) or (3, 4) (3, 174) or (3, 176) (0, 0) (453, 179)

Note: The vertical I/O tile coordinates are not shown. West side coordinates are {(0, 2) to (2, 2)} to {(0, 77) to (2, 77)}; east side coordinates

are {(195, 2) to (197, 2)} to {(195, 77) to (197, 77)}.

Figure 2-4 • Array Coordinates for A3PE600

Top Row (5, 1) to (168, 1)

Bottom Row (7, 0) to (165, 0)

Top Row (169, 1) to (192, 1)

I/O Tile

Memory

Blocks

Memory

Blocks

Memory

Blocks

UJTAG FlashROM

Top Row (7, 79) to (189, 79)

Bottom Row (5, 78) to (192, 78)

I/O Tile

(3, 77)

(3, 76)

Memory

Blocks

(3, 3)

(3, 2)

VersaTile (Core)

(3, 75)

VersaTile (Core)

(3, 4)

(0, 0) (197, 0)

(194, 2)

(194, 3)

(194, 4)

VersaTile (Core)

(194, 75)

VersaTile (Core)

(197, 79)

(194, 77)

(194, 76)

(0, 79)

(197, 1)

ProASIC3E Flash Family FPGAs

v2.0 2-5

Routing Architecture

Routing Resources

The routing structure of ProASIC3E devices is designed to

provide high performance through a flexible four-level

hierarchy of routing resources: ultra-fast local resources,

efficient long-line resources, high-speed, very-long-line

resources, and the high-performance VersaNet networks.

The ultra-fast local resources are dedicated lines that allow

the output of each VersaTile to connect directly to every

input of the eight surrounding VersaTiles (Figure 2-5). The

exception to this is that the SET/CLR input of a VersaTile

configured as a D-flip-flop is driven only by the VersaTile

global network.

The efficient long-line resources provide routing for longer

distances and higher-fanout connections. These resources

vary in length (spanning one, two, or four VersaTiles), run

both vertically and horizontally, and cover the entire

ProASIC3E device (Figure 2-6 on page 2-6). Each VersaTile

can drive signals onto the efficient long-line resources,

which can access every input of every VersaTile. Active

buffers are inserted automatically by routing software to

limit loading effects.

The high-speed, very-long-line resources, which span the

entire device with minimal delay, are used to route very

long or high-fanout nets: length +/–12 VersaTiles in the

vertical direction and length +/–16 in the horizontal

direction from a given core VersaTile (Figure 2-7 on page

2-7). Very long lines in ProASIC3E devices have been

enhanced over those in previous ProASIC families. This

provides a significant performance boost for long-reach

signals.

The high-performance VersaNet global networks are

low-skew, high-fanout nets that are accessible from

external pins or from internal logic (Figure 2-8 on page

2-8). These nets are typically used to distribute clocks,

resets, and other high-fanout nets requiring minimum

skew. The VersaNet networks are implemented as clock

trees, and signals can be introduced at any junction.

These can be employed hierarchically, with signals

accessing every input on all VersaTiles.

Note: Input to the core cell for the D-flip-flop set and reset is only available via the VersaNet global network connection.

Figure 2-5 • Ultra-Fast Local Lines Connected to the Eight Nearest Neighbors

LInputs

Output

Ultra-Fast Local Lines

(connects a VersaTile to the

adjacent VersaTile, I/O buffer,

or memory block)

LLL

Long Lines

ProASIC3E Flash Family FPGAs

2-6 v2.0

Figure 2-6 • Efficient Long-Line Resources

LL LLLL

LLLLLL

LL LLLL

Spans 1 VersaTile

Spans 2 VersaTiles

Spans 4 VersaTiles

Spans 1 VersaTile

Spans 2 VersaTiles

Spans 4 VersaTiles

VersaTile

ProASIC3E Flash Family FPGAs

v2.0 2-7

Figure 2-7 • Very-Long-Line Resources

High-Speed, Very-Long-Line Resources

Pad Ring

I/O Ring

Pad Ring

16×12 Block of VersaTiles

SRAM

ProASIC3E Flash Family FPGAs

2-8 v2.0

Clock Resources (VersaNets)

ProASIC3E devices offer powerful and flexible control of

circuit timing through the use of analog circuitry. Each

chip has six CCCs containing a phase-locked loop (PLL)

core, delay lines, a phase shifter (0°, 90°, 180°, 270°),

clock multipliers/dividers, and all the circuitry needed for

the selection and interconnection of inputs to the

VersaNet global network. The east and west CCCs each

have access to three VersaNet global lines on each side of

the chip (six total lines). The CCCs at the four corners

each have access to three quadrant global lines in each

quadrant of the chip.

Advantages of the VersaNet Approach

One of the architectural benefits of ProASIC3E is the set of

powerful and low-delay VersaNet global networks.

ProASIC3E offers six chip (main) global networks that are

distributed from the center of the FPGA array (Figure 2-8).

In addition, ProASIC3E devices have three regional globals

in each of the four chip quadrants. Each core VersaTile has

access to nine global network resources: three quadrant

and six chip (main) global networks, and a total of 18

globals on the device. Each of these networks contains

spines and ribs that reach all the VersaTiles in the quadrants

(Figure 2-9 on page 2-9). This flexible VersaNet global

network architecture allows users to map up to 252

different internal/external clocks in a ProASIC3E device.

Details on the VersaNet networks are given in Table 2-2 on

page 2-9. The flexible use of the ProASIC3E VersaNet global

network allows the designer to address several design

requirements. User applications that are clock-resource-

intensive can easily route external or gated internal clocks

using VersaNet global routing networks. Designers can also

drastically reduce delay penalties and minimize resource

usage by mapping critical, high-fanout nets to the VersaNet

global network.

Figure 2-8 • Overview of ProASIC3E VersaNet Global Network

Quadrant Global Pads

Top Spine

Bottom Spine

Pad Ring

I/O Ring

Chip (main)

Global Pads

Spine-Selection

Tree MUX

Global

Pads

High-Performance

VersaNet Global Network

Main (chip)

Global Network

Global Spine

Global Ribs

ProASIC3E Flash Family FPGAs

v2.0 2-9

Figure 2-9 • Global Network Architecture

Table 2-2 • ProASIC3E Globals/Spines/Rows by Device

A3PE600 A3PE1500 A3PE3000

Global Clock Networks (Trees)* 9 9 9

Clock Spines/Trees 12 20 28

Total Spines 108 180 252

VersaTiles in Each Top or Bottom Spine 1,120 1,888 2,656

Total VersaTiles 13,824 38,400 75,264

Rows in Each Top or Bottom Spine 36 60 84

Note: *There are six chip (main) globals and three globals per quadrant.

Northwest Quadrant Global Network

Southeast Quadrant Global Network

Chip (main)

Global

Network

333

3333

Global Spine Quadrant Global Spine

CCC

CCC CCC

CCC

ProASIC3E Flash Family FPGAs

2-10 v2.0

VersaNet Global Networks and Spine Access

The ProASIC3E architecture contains a total of 18

segmented global networks that can access the

VersaTiles, SRAM, and I/O tiles of the ProASIC3E device.

There are nine global network resources in each device

quadrant: three quadrant globals and six chip (main)

global networks. Each device has a total of 18 globals.

These VersaNet global networks offer fast, low-skew

routing resources for high-fanout nets, including clock

signals. In addition, these highly segmented global

networks offer users the flexibility to create low-skew

local networks using spines for up to 252

internal/external clocks (in an A3PE3000 device) or other

high-fanout nets in ProASIC3E devices. Optimal usage of

these low-skew networks can result in significant

improvement in design performance on ProASIC3E

devices.

The nine spines available in a vertical column reside in

global networks with two separate regions of scope: the

quadrant global network, which has three spines, and

the chip (main) global network, which has six spines.

Note that there are three quadrant spines in each

quadrant of the device. There are four quadrant global

network regions per device (Figure 2-9 on page 2-9).

The spines are the vertical branches of the global

network tree, shown in Figure 2-10 on page 2-11. Each

spine in a vertical column of a chip (main) global

network is further divided into two equal-length spine

segments: one in the top and one in the bottom half of

the die.

Each spine and its associated ribs cover a certain area of

the ProASIC3E device (the "scope" of the spine; see

Figure 2-8 on page 2-8). Each spine is accessed by the

dedicated global network MUX tree architecture, which

defines how a particular spine is driven—either by the

signal on the global network from a CCC, for example, or

by another net defined by the user (Figure 2-11 on page

2-12). Quadrant spines can be driven from user I/Os on

the north and south sides of the die. The ability to drive

spines in the quadrant global networks can have a

significant effect on system performance for high-fanout

inputs to a design.

Details of the chip (main) global network spine-selection

MUX are presented in Figure 2-11 on page 2-12. The

spine drivers for each spine are located in the middle of

the die.

Quadrant spines are driven from a north or south rib.

Access to the top and bottom ribs is from the corner CCC

or from the I/Os on the north and south sides of the

device.

For details on using spines in ProASIC3E devices, see the

Actel application note Using Global Resources in Actel

ProASIC3/E Devices.

ProASIC3E Flash Family FPGAs

v2.0 2-11

Figure 2-10 • ProASIC3E Spines in a Global Clock Tree Network

Pad Ring

I/O Ring

I/ORing

Chip (main)

Global Pads

Global

Pads

High-Performance

Global Network

Global Spine

Global Ribs

Scope of Spine

(shaded area

plus local RAMs

and I/Os)

Spine-Selection

MUX

Embedded

RAM Blocks

Logic Tiles

Top Spine

Bottom Spine

Quadrant Global Pads

ProASIC3E Flash Family FPGAs

2-12 v2.0

Clock Aggregation

Clock aggregation allows for multi-spine clock domains.

A MUX tree provides the necessary flexibility to allow

long lines or I/Os to access domains of one, two, or four

global spines. Signal access to the clock aggregation

system is achieved through long-line resources in the

central rib, and also through local resources in the north

and south ribs, allowing I/Os to feed directly into the

clock system. As Figure 2-12 indicates, this access system

is contiguous.

There is no break in the middle of the chip for the north

and south I/O VersaNet access. This is different from the

quadrant clocks located in these ribs, which only reach

the middle of the rib. Refer to the Using Global

Resources in Actel ProASIC3/E Devices application note.

Figure 2-11 • Spine Selection MUX of Global Tree

Figure 2-12 • Clock Aggregation Tree Architecture

Internal/External

Signal

Internal/External

Signal

Internal/External

Signals

Spine

Global Rib

Global Driver MUX

Tree Node MUX

Internal/External

Signals

Tree Node MUX

Global Spine

Global Rib

Global Driver and MUX

I/O Access

Internal Signal Access

I/O Tiles

Global Signal Access

Tree Node MUX

ProASIC3E Flash Family FPGAs

v2.0 2-13

Clock Conditioning Circuits

Overview of Clock Conditioning Circuitry

In ProASIC3E devices, the CCCs are used to implement

frequency division, frequency multiplication, phase

shifting, and delay operations.

The CCCs are available in six chip locations—each of the

four chip corners and the middle of the east and west

chip sides.

Each CCC can implement up to three independent global

buffers (with or without programmable delay), or a PLL

function (programmable frequency division/multiplication,

phase shift, and delays) with up to three global outputs.

Unused global outputs of a PLL can be used to

implement independent global buffers, up to a

maximum of three global outputs for a given CCC.

A global buffer can be placed in any of the three global

locations (CLKA-GLA, CLKB-GLB, or CLKC-GLC) of a given

CCC.

A PLL macro uses the CLKA CCC input to drive its reference

clock. It uses the GLA and optionally the GLB and GLC

global outputs to drive the global networks. A PLL macro

can also drive the YB and YC regular core outputs. The GLB

(or GLC) global output cannot be reused if the YB (or YC)

output is used (Figure 2-13 on page 2-14). Refer to the

"PLL Macro" section on page 2-15 for more information.

Each global buffer, as well as the PLL reference clock, can

be driven from one of the following:

• 3 dedicated single-ended I/Os using a hardwired

connection

• 2 dedicated differential I/Os using a hardwired

connection

•The FPGA core

The CCC block is fully configurable, either via Flash

configuration bits set in the programming bitstream or

through an asynchronous interface. This asynchronous

interface is dynamically accessible from inside the

ProASIC3E device to permit parameter changes (such as

divide ratios) during device operation. To increase the

versatility and flexibility of the clock conditioning

system, the CCC configuration is determined either by

the user during the design process, with configuration

data being stored in Flash memory as part of the device

programming procedure, or by writing data into a

dedicated shift register during normal device operation.

This latter mode allows the user to dynamically

reconfigure the CCC without the need for core

programming. The shift register is accessed through a

simple serial interface. Refer to the UJTAG Applications

in ProASIC3/E Devices application note and the "CCC

Electrical Specifications" section on page 2-18 for more

information.

Global Buffers with No Programmable Delays

The CLKBUF and CLKBUF_LVPECL/LVDS/BLVDS/M-LVDS

macros are composite macros that include an I/O macro

driving a global buffer, which uses a hardwired

connection.

The CLKBUF, CLKBUF_LVPECL/LVDS/BLVDS/M-LVDS, and

CLKINT macros are pass-through clock sources and do

not use the PLL or provide any programmable delay

functionality.

The CLKINT macro provides a global buffer function

driven by the FPGA core.

Many specific CLKBUF macros support the wide variety of

single-ended and differential I/O standards supported by

ProASIC3E devices. The available CLKBUF macros are

described in the ProASIC3/E Macro Library Guide.

Global Buffer with Programmable Delay

The CLKDLY macro is a pass-through clock source that

does not use the PLL, but provides the ability to delay the

clock input using a programmable delay. The CLKDLY

macro takes the selected clock input and adds a user-

defined delay element. This macro generates an output

clock phase shift from the input clock.

The CLKDLY macro can be driven by an INBUF* macro to

create a composite macro, where the I/O macro drives

the global buffer (with programmable delay) using a

hardwired connection. In this case, the I/O must be

placed in one of the dedicated global I/O locations.

Many specific INBUF macros support the wide variety of

single-ended and differential I/O standards supported by

the ProASIC3E family. The available INBUF macros are

described in the ProASIC3/E Macro Library Guide.

The CLKDLY macro can be driven directly from the FPGA

core.

The CLKDLY macro can also be driven from an I/O that is

routed through the FPGA regular routing fabric. In this

case, users must instantiate a special macro, PLLINT, to

differentiate from the hardwired I/O connection

described earlier.

The visual CLKDLY configuration in the SmartGen part of

the Libero IDE and Designer tools allows the user to

select the desired amount of delay and configures the

delay elements appropriately. SmartGen also allows the

user to select the input clock source. SmartGen will

automatically instantiate the special macro, PLLINT,

when needed.

ProASIC3E Flash Family FPGAs

2-14 v2.0

Notes:

1. Visit the Actel website for future application notes concerning dynamic PLL reconfiguration. Refer to the "PLL Macro" section on

page 2-15 for signal descriptions.

2. Refer to the ProASIC3/E Macro Library Guide for more information.

3. Many standard-specific INBUF macros (for example, INBUF_LVDS) support the wide variety of single-ended and differential I/O

standards supported by the ProASIC3E family. The available INBUF macros are described in the ProASIC3/E Macro Library Guide.

Figure 2-13 • ProASIC3E CCC Options

CLKBUF_LVDS/LVPECL Macro

PADN

PADP

PAD Y

CLKINT MacroCLKBUF Macro

Input LVDS/LVPECL Macro PLL Macro

INBUF* Macro

GLA

GLA and (GLB or YB)

GLA and (GLC or YC)

GLA and (GLB or YB) and

(GLC or YC)

GLA

GLB

GLC

Clock Source Clock Conditioning Output

OADIV[4:0]

OAMUX[2:0]

DLYGLA[4:0]

OBDIV[4:0]

OBMUX[2:0]

DLYYB[4:0]

DLYGLB[4:0]

OCDIV[4:0]

OCMUX[2:0]

DLYYC[4:0]

DLYGLC[4:0]

FINDIV[6:0]

FBDIV[6:0]

FBDLY[4:0]

FBSEL[1:0]

XDLYSEL

VCOSEL[2:0]

CLKA GLA

LOCK

GLB

GLC

POWERDOWN

CLKDLY Macro

CLK GL

DLYGL[4:0]

PADN

PADP Y

ProASIC3E Flash Family FPGAs

v2.0 2-15

PLL Macro

The PLL functionality of the clock conditioning block is

supported by the PLL macro. Note that the PLL macro

reference clock uses the CLKA input of the CCC block,

which is only accessible from the global A[0:2] package

pins. Refer to Figure 2-14 on page 2-16 for more

information.

The PLL macro provides five derived clocks (three

independent) from a single reference clock. The PLL

macro also provides power-down input and lock output

signals. See Figure 2-16 on page 2-17 for more

information.

Inputs:

• CLKA: selected clock input

• POWERDOWN (active low): disables PLLs. The

default state is Powerdown On (active low).

Outputs:

• LOCK: indicates that PLL output has locked on the

input reference signal

• GLA, GLB, GLC: outputs to respective global

networks

• YB, YC: allows output from the CCC to be routed

back to the FPGA core

As previously described, the PLL allows up to five flexible

and independently configurable clock outputs. Figure 2-19

on page 2-19 illustrates the various clock output options

and delay elements.

As illustrated, the PLL supports three distinct output

frequencies from a given input clock. Two of these (GLB

and GLC) can be routed to the B and C global network

access, respectively, and/or routed to the device core (YB

and YC).

There are five delay elements to support phase control

on all five outputs (GLA, GLB, GLC, YB, and YC).

There is also a delay element in the feedback loop that

can be used to advance the clock relative to the

reference clock.

The PLL macro reference clock can be driven by an INBUF*

macro to create a composite macro, where the I/O macro

drives the global buffer (with programmable delay) using a

hardwired connection. In this case, the I/O must be placed

in one of the dedicated global I/O locations.

The PLL macro reference clock can be driven directly

from the FPGA core.

The PLL macro reference clock can also be driven from an

I/O that is routed through the FPGA regular routing

fabric. In this case, users must instantiate a special macro,

PLLINT, to differentiate from the hardwired I/O

connection described earlier.

During power-up, the PLL outputs will toggle around the

maximum frequency of the VCO gear selected. Toggle

frequencies can range from 40 Mhz to 350 Mhz. This will

continue as long as the clock input (CLKA) is constant

(high or low). This can be prevented by LOW assertion of

the POWERDOWN signal.

The visual PLL configuration in SmartGen, part of the

Libero IDE and Designer tools, will derive the necessary

internal divider ratios based on the input frequency and

desired output frequencies selected by the user.

SmartGen also allows the user to select the various delays

and phase shift values necessary to adjust the phases

between the reference clock (CLKA) and the derived

clocks (GLA, GLB, GLC, YB, and YC). SmartGen also allows

the user to select the input clock source. SmartGen

automatically instantiates the special macro, PLLINT,

when needed.

ProASIC3E Flash Family FPGAs

2-16 v2.0

Notes:

1. Represents the global input pins. Globals have direct access to the clock conditioning block and are not routed via the FPGA fabric.

Refer to the "User I/O Naming Convention" section on page 2-50 for more information.

2. Instantiate the routed clock source input as follows:

a) Connect the output of a logic element to the clock input of a PLL, CLKDLY, or CLKINT macro.

b) Do not place a clock source I/O (INBUF or INBUF_LVPECL/LVDS/BLVDS/M-LVDS/DDR) in a relevant global pin location.

Figure 2-14 • Clock Input Sources Including CLKBUF, CLKBUF_LVDS/LVPECL, and CLKINT

Figure 2-15 • CLKBUF and CLKINT

Source for CCC

(CLKA or CLKB or CLKC)

Each shaded box represents an

INBUF or INBUF_LVDS/LVPECL

macro, as appropriate. To Core

Routed Clock

(from FPGA core)

Sample Pin Names

GAA0/IO0NDB0V01

GAA1/IO00PDB0V01

GAA2/IO13PDB7V11

GAA[0:2]: GA represents global in the northwest corner

of the device. A[0:2]: designates specific A clock source.

CLKBUF CLKINT

CLKBUF_LVDS/LVPECL

PADN

PADP Y

PAD Y YA

ProASIC3E Flash Family FPGAs

v2.0 2-17

Table 2-3 • Available ProASIC3E I/O Standards within

CLKBUF and CLKBUF_LVDS/LVPECL Macros

CLKBUF Macros

CLKBUF_LVCMOS5

CLKBUF_LVCMOS331

CLKBUF_LVCMOS25

CLKBUF_LVCMOS18

CLKBUF_LVCMOS15

CLKBUF_PCI

CLKBUF_PCIX

CLKBUF_GTL25

CLKBUF_GTL33

CLKBUF_GTLP25

CLKBUF_GTLP33

CLKBUF_HSTL_I

CLKBUF_HSTL_II

CLKBUF_SSTL3_I

CLKBUF_SSTL3_II

CLKBUF_SSTL2_I

CLKBUF_SSTL2_II

CLKBUF_LVDS2

CLKBUF_LVPECL

Notes:

1. By default, the CLKBUF macro uses the 3.3 V LVTTL I/O

technology. For more details, refer to the ProASIC3/E Macro

Library Guide.

2. BLVDS and M-LVDS standards are supported by

CLKBUF_LVDS.

Note: *Visit the Actel website for future application notes

concerning the dynamic PLL.

Figure 2-16 • CCC/PLL Macro

Note: The CLKDLY macro uses programmable delay element type 2.

Figure 2-17 • CLKDLY

CLKA GLA

GLB

GLC

LOCK

POWERDOWN

OADIV[4:0]*

OAMUX[2:0]*

DLYGLA[4:0]*

OBDIV[4:0]*

OBMUX[2:0]*

DLYYB[4:0]*

DLYGLB[4:0]*

OCDIV[4:0]*

OCMUX[2:0]*

DLYYC[4:0]*

DLYGLC[4:0]*

FINDIV[6:0]*

FBDIV[6:0]*

FBDLY[4:0]*

FBSEL[1:0]*

XDLYSEL*

VCOSEL[2:0]*

CLKDLY

CLK GL

DLYGL[4:0]

ProASIC3E Flash Family FPGAs

2-18 v2.0

CCC Electrical Specifications

Timing Characteristics

Table 2-4 • ProASIC3E CCC/PLL Specification

Parameter Minimum Typical Maximum Units

Clock Conditioning Circuitry Input Frequency fIN_CCC 1.5 350 MHz

Clock Conditioning Circuitry Output Frequency fOUT_CCC 0.75 350 MHz

Delay Increments in Programmable Delay Blocks1, 2 160 ps

Number of Programmable Values in Each Programmable Delay Block 32

Input Period Jitter 1.5 ns

CCC Output Peak-to-Peak Period Jitter FCCC_OUT Max Peak-to-Peak Period Jitter

1 Global

Network Used

3 Global

Networks Used

0.75 MHz to 24 MHz 0.50% 0.70%

24 MHz to 100 MHz 1.00% 1.20%

100 MHz to 250 MHz 1.75% 2.00%

250 MHz to 350 MHz 2.50% 5.60%

Acquisition Time LockControl = 0 300 µs

LockControl = 1 6.0 ms

Tracking Jitter3 LockControl = 0 1.6 ns

LockControl = 1 0.8 ns

Output Duty Cycle 48.5 51.5 %

Delay Range in Block: Programmable Delay 11, 2 0.6 5.56 ns

Delay Range in Block: Programmable Delay 21, 2 0.025 5.56 ns

Delay Range in Block: Fixed Delay1, 2 2.2 ns

Notes:

1. This delay is a function of voltage and temperature. See Table 3-6 on page 3-4 for deratings.

2. TJ = 25°C, VCC = 1.5 V.

3. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock edge. Tracking

jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter.

Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max - Tperiod_min

Figure 2-18 • Peak-to-Peak Jitter Definition

period_max

period_min

Output Signal

ProASIC3E Flash Family FPGAs

v2.0 2-19

CCC Physical Implementation

The CCC is composed of the following (Figure 2-19):

• PLL core

• 3 phase selectors

• 6 programmable delays and 1 fixed delay that

advances/delays phase

• 5 programmable frequency dividers that provide

frequency multiplication/division (not shown in

Figure 2-19 because they are automatically

configured based on the user's required

frequencies)

• 1 dynamic shift register that provides CCC dynamic

reconfiguration capability

CCC Programming

The CCC block is fully configurable, either via static Flash

configuration bits in the array, set by the user in the

programming bitstream, or through an asynchronous

dedicated shift register dynamically accessible from

inside the ProASIC3E device. The dedicated shift register

permits changes in parameters such as PLL divide ratios

and delays during device operation. This latter mode

allows the user to dynamically reconfigure the PLL

without the need for core programming. The register file

is accessed through a simple serial interface. Refer to the

UJTAG Applications in ProASIC3/E Devices application

note for more information.

Notes:

1. Refer to the "Clock Conditioning Circuits" section on page 2-13 and Table 2-4 on page 2-18 for signal descriptions.

2. Clock divider and clock multiplier blocks are not shown in this figure or in SmartGen. They are automatically configured based on the

user's required frequencies.

Figure 2-19 • PLL Block

PLL Core Phase

Select

Phase

Select

Phase

Select

GLA

CLKA

GLB

GLC

Fixed Delay Programmable

Delay Type 1

Programmable

Delay Type 2

Programmable

Delay Type 2

Programmable

Delay Type 1

Programmable

Delay Type 2

Programmable

Delay Type 1

Four-Phase Output

ProASIC3E Flash Family FPGAs

2-20 v2.0

Nonvolatile Memory (NVM)

Overview of User Nonvolatile FlashROM

ProASIC3E devices have 1 kbit of on-chip nonvolatile

Flash memory that can be read from the FPGA core

fabric. The FlashROM is arranged in 8 banks of 128 bits

during programming. The 128 bits in each bank are

addressable as 16 bytes during the read back of the

FlashROM from the FPGA core (Figure 2-20).

The FlashROM can only be programmed via the IEEE1532

JTAG port. It cannot be programmed directly from the

FPGA core. When programming, each of the eight

128-bit banks can be selectively reprogrammed. The

FlashROM can only be reprogrammed on a bank

boundary. Programming involves an automatic, on-chip

bank erase prior to reprogramming the bank. The

FlashROM supports synchronous read. The address is

latched on the rising edge of the clock and the new

output data is stable after the falling edge of the same

clock cycle. Please refer to Figure 3-53 on page 3-79 for

the timing diagram. The FlashROM can be read on byte

boundaries. The upper three bits of the FlashROM

address from the FPGA core define the bank that is being

accessed. The lower four bits of the FlashROM address

from the FPGA core define which of the 16 bytes in the

bank is being accessed.

Figure 2-20 • FlashROM Architecture

Bank Number 3 MSB of

ADDR (READ)

Byte Number in Bank 4 LSB of ADDR (READ)

012345

789101112131415

ProASIC3E Flash Family FPGAs

v2.0 2-21

SRAM and FIFO

ProASIC3E devices have embedded SRAM blocks along

the north and south sides of the device. To meet the

needs of high-performance designs, the memory blocks

operate strictly in synchronous mode for both read and

write operations. The read and write clocks are

completely independent, and each may operate at any

desired frequency less than or equal to 350 MHz.

• 4k×1, 2k×2, 1k×4, 512×9 (dual-port RAM—2 read,

2 write or 1 read, 1 write)

• 512×9, 256×18 (2-port RAM—1 read and 1 write)

• Sync write, sync pipelined / nonpipelined read

The ProASIC3E memory block includes dedicated FIFO

control logic to generate internal addresses and external

flag logic (FULL, EMPTY, AFULL, AEMPTY). Block

diagrams of the memory modules are illustrated in

Figure 2-21 on page 2-22.

Simultaneous dual-port read/write and write/write

operations at the same address are allowed when certain

timing requirements are met.

During RAM operation, addresses are sourced by the

user logic and the FIFO controller is ignored. In FIFO

mode, the internal addresses are generated by the FIFO

controller and routed to the RAM array by internal

MUXes. Refer to Figure 2-22 on page 2-23 for more

information about the implementation of the embedded

FIFO controller.

The ProASIC3E architecture enables the read and write

sizes of RAMs to be organized independently, allowing

for bus conversion. For example, the write side size can

be set to 256×18 and the read size to 512×9.

Both the write width and read width for the RAM blocks

can be specified independently with the WW (write

width) and RW (read width) pins. The different D×W

configurations are: 256×18, 512×9, 1k×4, 2k×2, and 4k×1.

Refer to the allowable RW and WW values supported for

each of the RAM macro types in Table 2-5 on page 2-24.

When widths of one, two, or four are selected, the ninth

bit is unused. For example, when writing nine-bit values

and reading four-bit values, only the first four bits and

the second four bits of each nine-bit value are

addressable for read operations. The ninth bit is not

accessible.

Conversely, when writing four-bit values and reading

nine-bit values, the ninth bit of a read operation will be

undefined. The RAM blocks employ little-endian byte

order for read and write operations.

ProASIC3E Flash Family FPGAs

2-22 v2.0

Figure 2-21 • Supported Basic RAM Macros

FIFO4K18

RW2

RD17

RW1

RD16

RW0

WW2

WW1

WW0 RD0

ESTOP

FSTOP

FULL

AFULL

EMPTY

AFVAL11

AEMPTY

AFVAL10

AFVAL0

AEVAL11

AEVAL10

AEVAL0

REN

RBLK

RCLK

WEN

WBLK

WCLK

RPIPE

WD17

WD16

WD0

RESET

ADDRA11 DOUTA8

DOUTA7

DOUTA0

DOUTB8

DOUTB7

DOUTB0

ADDRA10

ADDRA0

DINA8

DINA7

DINA0

WIDTHA1

WIDTHA0

PIPEA

WMODEA

BLKA

WENA

CLKA

ADDRB11

ADDRB10

ADDRB0

DINB8

DINB7

DINB0

WIDTHB1

WIDTHB0

PIPEB

WMODEB

BLKB

WENB

CLKB

RAM4K9

RADDR8 RD17

RADDR7 RD16

RADDR0 RD0

WD17

WD16

WD0

WW1

WW0

RW1

RW0

PIPE

REN

RCLK

RAM512x18

WADDR8

WADDR7

WADDR0

WEN

WCLK

RESET

ProASIC3E Flash Family FPGAs

v2.0 2-23

Figure 2-22 • ProASIC3E RAM Block with Embedded FIFO Controller

CNT 12

AFVAL

AEVAL

SUB 12

RCLK

WCLK

Reset

RBLK

REN

ESTOP

WBLK

WEN

FSTOP

RD[17:0]

WD[17:0]

RCLK

WCLK

RADD[J:0]

WADD[J:0]

REN

FREN FWEN WEN

FULL

AEMPTY

AFULL

EMPTY

RPIPE

RW[2:0]

WW[2:0]

RAM

ProASIC3E Flash Family FPGAs

2-24 v2.0

Signal Descriptions for RAM4K9

The following signals are used to configure the RAM4K9

memory element:

WIDTHA and WIDTHB

These signals enable the RAM to be configured in one of

four allowable aspect ratios (Table 2-5).

BLKA and BLKB

These signals are active low and will enable the

respective ports when asserted. When a BLKx signal is

deasserted, that port’s outputs hold the previous value.

WENA and WENB

These signals switch the RAM between read and write

modes for the respective ports. A LOW on these signals

indicates a write operation, and a HIGH indicates a read.

CLKA and CLKB

These are the clock signals for the synchronous read and

write operations. These can be driven independently or

with the same driver.

PIPEA and PIPEB

These signals are used to specify pipelined read on the

output. A low on PIPEA or PIPEB indicates a nonpipelined

read, and the data appears on the corresponding output

in the same clock cycle. A HIGH indicates a pipelined

read, and data appears on the corresponding output in

the next clock cycle.

WMODEA and WMODEB

These signals are used to configure the behavior of the

output when the RAM is in write mode. A LOW on these

signals makes the output retain data from the previous

read. A HIGH indicates pass-through behavior, wherein

the data being written will appear immediately on the

output. This signal is overridden when the RAM is being

read.

RESET

This active low signal resets the control logic and forces

the output hold state registers to zero and disables reads

and/or writes from the SRAM block as well as clears the

data hold registers when asserted. It does not reset the

contents of the memory array.

While the RESET signal is active, read and write

operations are disabled. As with any asynchronous reset

signal, care must be taken not to assert it too close to the

edges of active read and write clocks. Refer to the tables

beginning with Table 3-94 on page 3-73 for the

specifications.

ADDRA and ADDRB

These are used as read or write addresses, and they are 12

bits wide. When a depth of less than 4 k is specified, the

unused high-order bits must be grounded (Table 2-6).

DINA and DINB

These are the input data signals, and they are nine bits

wide. Not all nine bits are valid in all configurations.

When a data width less than nine is specified, unused

high-order signals must be grounded (Table 2-7).

DOUTA and DOUTB

These are the nine-bit output data signals. Not all nine

bits are valid in all configurations. As with DINA and

DINB, high-order bits may not be used (Table 2-7). The

output data on unused pins is undefined.

Table 2-5 • Allowable Aspect Ratio Settings for

WIDTHA[1:0]

WIDTHA[1:0] WIDTHB[1:0] D×W

00 00 4k×1

01 01 2k×2

10 10 1k×4

11 11 512×9

Note: The aspect ratio settings are constant and cannot be

changed on-the-fly. Table 2-6 • Address Pins Unused/Used for Various

Supported Bus Widths

D×W

ADDRx

Unused Used

4k×1 None [11:0]

2k×2 [11] [10:0]

1k×4 [11:10] [9:0]

512×9 [11:9] [8:0]

Note: The "x" in ADDRx implies A or B.

Table 2-7 • Unused/Used Input and Output Data Pins for

Various Supported Bus Widths

D×W

DINx/DOUTx

Unused Used

4k×1 [8:1] [0]

2k×2 [8:2] [1:0]

1k×4 [8:4] [3:0]

512×9 None [8:0]

Note: The "x" in DINx or DOUTx implies A or B.

ProASIC3E Flash Family FPGAs

v2.0 2-25

Signal Descriptions for RAM512X18

RAM512X18 has slightly different behavior than

RAM4K9, as it has dedicated read and write ports.

WW and RW

These signals enable the RAM to be configured in one of

the two allowable aspect ratios (Table 2-8).

WD and RD

These are the input and output data signals, and they

are 18 bits wide. When a 512×9 aspect ratio is used for

write, WD[17:9] are unused and must be grounded. If

this aspect ratio is used for read, RD[17:9] are undefined.

WADDR and RADDR

These are read and write addresses, and they are nine

bits wide. When the 256×18 aspect ratio is used for write

or read, WADDR[8] or RADDR[8] are unused and must be

grounded.

WCLK and RCLK

These signals are the write and read clocks, respectively.

They can be clocked on the rising or falling edge of

WCLK and RCLK.

WEN and REN

These signals are the write and read enables,

respectively. They are both active low by default. These

signals can be configured as active high.

RESET

This active low signal resets the control logic and forces

the output hold state registers to zero and disables reads

and/or writes from the SRAM block as well as clears the

data hold registers when asserted. It does not reset the

contents of the memory array.

While the RESET signal is active, read and write

operations are disabled. As with any asynchronous reset

signal, care must be taken not to assert it too close to the

edges of active read and write clocks. Refer to the tables

beginning with Table 3-95 on page 3-74 for the

specifications.

PIPE

This signal is used to specify pipelined read on the

output. A LOW on PIPE indicates a nonpipelined read,

and the data appears on the output in the same clock

cycle. A HIGH indicates a pipelined read, and data

appears on the output in the next clock cycle.

Clocking

The dual-port SRAM blocks are only clocked on the rising

edge. SmartGen allows falling-edge-triggered clocks by

adding inverters to the netlist, hence achieving dual-port

SRAM blocks that are clocked on either edge (rising or

falling). For dual-port SRAM, each port can be clocked on

either edge and/or by separate clocks by port.

ProASIC3E devices support inversion (bubble pushing)

throughout the FPGA architecture, including the clock

input to the SRAM modules. Inversions added to the

SRAM clock pin on the design schematic or in the HDL

code will be automatically accounted for during design

compile without incurring additional delay in the clock

path.

The two-port SRAM can be clocked on the rising or

falling edge of WCLK and RCLK.

If negative-edge RAM and FIFO clocking is selected for

memory macros, clock edge inversion management

(bubble pushing) is automatically used within the

ProASIC3E development tools, without performance

penalty.

Modes of Operation

There are two read modes and one write mode:

• Read Nonpipelined (synchronous—1 clock edge):

In the standard read mode, new data is driven

onto the RD bus in the same clock cycle following

RA and REN valid. The read address is registered

on the read port clock active edge, and data

appears at RD after the RAM access time. Setting

PIPE to OFF enables this mode.

• Read Pipelined (synchronous—2 clock edges): The

pipelined mode incurs an additional clock delay

from address to data but enables operation at a

much higher frequency. The read address is

registered on the read port active clock edge, and

the read data is registered and appears at RD after

the second read clock edge. Setting PIPE to ON

enables this mode.

• Write (synchronous—1 clock edge): On the write

clock active edge, the write data is written into

the SRAM at the write address when WEN is high.

The setup times of the write address, write

enables, and write data are minimal with respect

to the write clock. Write and read transfers are

described with timing requirements in the "DDR

Module Specifications" section on page 3-56.

RAM Initialization

Each SRAM block can be individually initialized on power-

up by means of the JTAG port using the UJTAG mechanism

(refer to the "JTAG 1532" section on page 2-54 and the

ProASIC3/E SRAM/FIFO Blocks application note). The shift

with the proper bit configuration to enable serial

loading. The 4,608 bits of data can be loaded in a single

operation.

Table 2-8 • Aspect Ratio Settings for WW[1:0]

WW[1:0] RW[1:0] D×W

01 01 512×9

10 10 256×18

00, 11 00, 11 Reserved

ProASIC3E Flash Family FPGAs

2-26 v2.0

Signal Descriptions for FIFO4K18

The following signals are used to configure the FIFO4K18

memory element:

WW and RW

These signals enable the FIFO to be configured in one of

the five allowable aspect ratios (Table 2-9).

WBLK and RBLK

These signals are active low and will enable the

respective ports when LOW. When the RBLK signal is

HIGH, that port’s outputs hold the previous value.

WEN and REN

Read and write enables. WEN is active low and REN is

active high by default. These signals can be configured as

active high or low.

WCLK and RCLK

These are the clock signals for the synchronous read and

write operations. These can be driven independently or

with the same driver.

RPIPE

This signal is used to specify pipelined read on the

output. A LOW on RPIPE indicates a nonpipelined read,

and the data appears on the output in the same clock

cycle. A HIGH indicates a pipelined read, and data

appears on the output in the next clock cycle.

RESET

This active low signal resets the control logic and forces

the output hold state registers to zero when asserted. It

does not reset the contents of the memory array

(Table 2-10).

While the RESET signal is active, read and write

operations are disabled. As with any asynchronous RESET

signal, care must be taken not to assert it too close to the

edges of active read and write clocks. Refer to the tables

beginning with Table 3-96 on page 3-78 for the

specifications.

This is the input data bus and is 18 bits wide. Not all 18

bits are valid in all configurations. When a data width

less than 18 is specified, unused higher-order signals

must be grounded (Table 2-10).

This is the output data bus and is 18 bits wide. Not all 18

bits are valid in all configurations. Like the WD bus, high-

order bits become unusable if the data width is less than

18. The output data on unused pins is undefined

(Table 2-10).

ESTOP, FSTOP

ESTOP is used to stop the FIFO read counter from further

counting once the FIFO is empty (i.e., the EMPTY flag

goes HIGH). A HIGH on this signal inhibits the counting.

FSTOP is used to stop the FIFO write counter from further

counting once the FIFO is full (i.e., the FULL flag goes

HIGH). A HIGH on this signal inhibits the counting.

For more information on these signals, refer to the

"ESTOP and FSTOP Usage" section on page 2-27.

FULL, EMPTY

When the FIFO is full and no more data can be written,

the FULL flag asserts HIGH. The FULL flag is synchronous

to WCLK to inhibit writing immediately upon detection

of a full condition and to prevent overflows. Since the

write address is compared to a resynchronized (and thus

time-delayed) version of the read address, the FULL flag

will remain asserted until two WCLK active edges after a

read operation eliminates the full condition.

When the FIFO is empty and no more data can be read,

the EMPTY flag asserts HIGH. The EMPTY flag is

synchronous to RCLK to inhibit reading immediately

upon detection of an empty condition and to prevent

underflows. Since the read address is compared to a

resynchronized (and thus time-delayed) version of the

write address, the EMPTY flag will remain asserted until

two RCLK active edges after a write operation removes

the empty condition.

For more information on these signals, refer to the "FIFO

Flag Usage Considerations" section on page 2-27.

AFULL, AEMPTY

These are programmable flags and will be asserted on

the threshold specified by AFVAL and AEVAL,

respectively.

When the number of words stored in the FIFO reaches

the amount specified by AEVAL while reading, the

Table 2-9 • Aspect Ratio Settings for WW[2:0]

WW[2:0] RW[2:0] D×W

000 000 4k×1

001 001 2k×2

010 010 1k×4

011 011 512×9

100 100 256×18

101, 110, 111 101, 110, 111 Reserved

Table 2-10 • Input Data Signal Usage for Different Aspect

Ratios

D×W WD/RD Unused

4k×1 WD[17:1], RD[17:1]

2k×2 WD[17:2], RD[17:2]

1k×4 WD[17:4], RD[17:4]

512×9 WD[17:9], RD[17:9]

256×18 –

ProASIC3E Flash Family FPGAs

v2.0 2-27

AEMPTY output will go HIGH. Likewise, when the

number of words stored in the FIFO reaches the amount

specified by AFVAL while writing, the AFULL output will

go HIGH.

AFVAL, AEVAL

The AEVAL and AFVAL pins are used to specify the

almost-empty and almost-full threshold values. They are

12-bit signals. For more information on these signals,

refer to the "FIFO Flag Usage Considerations" section on

page 2-27.

ESTOP and FSTOP Usage

The ESTOP pin is used to stop the read counter from

counting any further once the FIFO is empty (i.e., the

EMPTY flag goes HIGH). Likewise, the FSTOP pin is used

to stop the write counter from counting any further once

the FIFO is full (i.e., the FULL flag goes HIGH).

The FIFO counters in the ProASIC3E device start the count

at zero, reach the maximum depth for the configuration

(e.g., 511 for a 512×9 configuration), and then restart at

zero. An example application for ESTOP, where the read

counter keeps counting, would be writing to the FIFO

once and reading the same content over and over

without doing another write.

FIFO Flag Usage Considerations

The AEVAL and AFVAL pins are used to specify the 12-bit

AEMPTY and AFULL threshold values. The FIFO contains

separate 12-bit write address (WADDR) and read address

(RADDR) counters. WADDR is incremented every time a

write operation is performed, and RADDR is incremented

every time a read operation is performed. Whenever the

difference between WADDR and RADDR is greater than

or equal to AFVAL, the AFULL output is asserted.

Likewise, whenever the difference between WADDR and

RADDR is less than or equal to AEVAL, the AEMPTY

output is asserted. To handle different read and write

aspect ratios, AFVAL and AEVAL are expressed in terms

of total data bits instead of total data words. When users

specify AFVAL and AEVAL in terms of read or write

words, the SmartGen tool translates them into bit

addresses and configures these signals automatically.

SmartGen configures the AFULL flag to assert when the

write address exceeds the read address by at least a

predefined value. In a 2k×8 FIFO, for example, a value of

1,500 for AFVAL means that the AFULL flag will be

asserted after a write when the difference between the

write address and the read address reaches 1,500 (there

have been at least 1,500 more writes than reads). It will

stay asserted until the difference between the write and

read addresses drops below 1,500.

The AEMPTY flag is asserted when the difference

between the write address and the read address is less

than a predefined value. In the example above, a value

of 200 for AEVAL means that the AEMPTY flag will be

asserted when a read causes the difference between the

write address and the read address to drop to 200. It will

stay asserted until that difference rises above 200. Note

that the FIFO can be configured with different read and

write widths; in this case the AFVAL setting is based on

the number of write data entries, and the AEVAL setting

is based on the number of read data entries. For aspect

ratios of 512×9 and 256×18, only 4,096 bits can be

addressed by the 12 bits of AFVAL and AEVAL. The

number of words must be multiplied by 8 and 16 instead

of 9 and 18. The SmartGen tool automatically uses the

proper values. To avoid halfwords being written or read,

which could happen if different read and write aspect

ratios are specified, the FIFO will assert FULL or EMPTY as

soon as at least a minimum of one word cannot be

written or read. For example, if a two-bit word is written

and a four-bit word is being read, the FIFO will remain in

the empty state when the first word is written. This

occurs even if the FIFO is not completely empty, because

in this case a complete word cannot be read. The same is

applicable in the full state. If a four-bit word is written

and a two-bit word is read, the FIFO is full and one word

is read. The FULL flag will remain asserted because a

complete word cannot be written at this point.

Refer to the ProASIC3/E SRAM/FIFO Blocks application

note for more information.

Pro I/Os

Introduction

ProASIC3E devices feature a flexible I/O structure,

supporting a range of mixed voltages (1.5 V, 1.8 V, 2.5 V,

and 3.3 V) through a bank-selectable voltage. Table 2-11,

Table 2-12, Table 2-13, and Table 2-14 on page 2-30 show

the voltages and the compatible I/O standards. I/Os

provide programmable slew rates, drive strengths, and

weak pull-up and pull-down circuits. All I/O standards,

except 3.3 V PCI and 3.3 V PCI-X, are capable of hot

insertion. 3.3 V PCI and 3.3 V PCI-X are 5 V–tolerant. See

the "5 V Input Tolerance" section on page 2-38 for

possible implementations of 5 V tolerance.

Single-ended input buffers support both the Schmitt

trigger and programmable delay options on a per-I/O

basis.

All I/Os are in a known state during power-up and any

power-up sequence is allowed without current impact.

Refer to the "I/O Power-Up and Supply Voltage

Thresholds for Power-On Reset (Commercial and

Industrial)" section on page 3-3 for more information.

During power-up, before reaching activation levels, the

I/O input and output buffers are disabled, while the

weak pull-up is enabled. Activation levels are described

in Table 3-2 on page 3-2.

ProASIC3E Flash Family FPGAs

2-28 v2.0

I/O Tile

The ProASIC3E I/O tile provides a flexible, programmable

structure for implementing a large number of I/O

standards. In addition, the registers available in the I/O

tile can be used to support high-performance register

inputs and outputs, with register enable if desired

(Figure 2-24 on page 2-33). The registers can also be used

to support the JESD-79C Double Data Rate (DDR)

standard within the I/O structure (see the "Double Data

Rate (DDR) Support" section on page 2-34 for more

information).

As depicted in Figure 2-24 on page 2-33, all I/O registers

share one CLR port. The output register and output

enable register share one CLK port. Refer to the "I/O

Registers" section on page 2-33 for more information.

I/O Banks and I/O Standards Compatibility

I/Os are grouped into I/O voltage banks. There are eight I/O

banks (two per side). Each I/O voltage bank has dedicated

I/O supply and ground voltages (VMV/GNDQ for input

buffers and VCCI/GND for output buffers). Because of

these dedicated supplies, only I/Os with compatible

standards can be assigned to the same I/O voltage bank.

Table 2-12 on page 2-29 shows the required voltage

compatibility values for each of these voltages.

For more information about I/O and global assignments

to I/O banks, refer to the specific pin table of the device

in the "Package Pin Assignments" section on page 4-1

and the "User I/O Naming Convention" section on

page 2-50.

Every I/O bank is divided into minibanks. Any user I/O in a

VREF minibank (a minibank is the region of scope of a

VREF pin) can be configured as a VREF pin (Figure 2-23).

Only one VREF pin is needed to control the entire VREF

minibank. The location and scope of the VREF minibanks

can be determined by the I/O name. For details, see the

"User I/O Naming Convention" section on page 2-50.

Table 2-11 on page 2-29 shows the I/O standards

supported by ProASIC3E devices and the corresponding

voltage levels.

I/O standards are compatible if they answer the

following:

• Their VCCI and VMV values are identical

• Both of the standards need a VREF and their VREF

values are identical

Figure 2-23 • Typical ProASIC3E I/O Bank Detail Showing VREF Minibanks

Bank 3 Bank 2

Any I/O in a VREF

minibank can be used to

provide the reference

voltage to the common

VREF signal for the VREF

minibank.

Common VREF

signal for all I/Os

in VREF minibanks

Up to five VREF

minibanks within

an I/O bankF

VREF signal scope is

between 8 and 18 I/Os.

I/O Pad

VCCI

VCC

GND

I/O

VCCI

VCC

GND

JTAG

CCC/PLL

“C”

CCC/PLL

“B”

CCC/PLL

“D”

ProASIC3E Flash Family FPGAs

v2.0 2-29

Table 2-11 • ProASIC3E Supported I/O Standards

A3PE600 A3PE1500 A3PE3000

Single-Ended

LVTTL/LVCMOS 3.3 V, LVCMOS 2.5 V / 1.8 V / 1.5 V,

LVCMOS 2.5/5.0 V, 3.3 V PCI/PCI-X

✓✓✓

Differential

LVPECL, LVDS, BLVDS, M-LVDS ✓✓✓

Voltage-Referenced

GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V, HSTL Class I and II, SSTL2

Class I and II, SSTL3 Class I and II

✓✓✓

Table 2-12 • VCCI Voltages and Compatible ProASIC3E Standards

VCCI and VMV (typical) Compatible Standards

3.3 V LVTTL/LVCMOS 3.3, PCI 3.3, SSTL3 (Class I and II), GTL+ 3.3, GTL 3.3, LVPECL

2.5 V LVCMOS 2.5, LVCMOS 2.5/5.0, SSTL2 (Class I and II), GTL+ 2.5, GTL 2.5, LVDS, DDR LVDS,

BLVDS, and M-LVDS

1.8 V LVCMOS 1.8

1.5 V LVCMOS 1.5, HSTL (Class I), HSTL (Class II)

Table 2-13 • VREF Voltages and Compatible ProASIC3E Standards

VREF (typical) Compatible Standards

1.5 V SSTL3 (Class I and II)

1.25 V SSTL2 (Class I and II)

1.0 V GTL+ 2.5, GTL+ 3.3

0.8 V GTL 2.5, GTL 3.3

0.75 V HSTL (Class I), HSTL (Class II)

ProASIC3E Flash Family FPGAs

2-30 v2.0

Table 2-14 • Legal ProASIC3E I/O Usage Matrix within the Same Bank

I/O Bank Voltage (typical)

Minibank Voltage (typical)

LVTTL / LVCMOS 3.3 V

LVCMOS 2.5 V

LVCMOS 1.8 V

LVCMOS 1.5 V

3.3 V PCI/PCI-X

GTL+ (3.3 V)

GTL+ (2.5 V)

GTL (3.3 V)

GTL (2.5 V)

HSTL Class I and II (1.5 V)

SSTL2 Class I and II (2.5 V)

SSTL3 Class I and II (3.3 V)

LVDS, BLVDS, and M-LVDS,

DDR (2.5 V ± 5%)

LVPECL (3.3 V)

3.3 V –

0.80 V

1.00 V

1.50 V

2.5 V –

0.80 V

1.00 V

1.25 V

1.8 V –

1.5 V –

0.75 V

Note: White box: Allowable I/O standard combination

Gray box: Illegal I/O standard combination

ProASIC3E Flash Family FPGAs

v2.0 2-31

Features Supported on Every I/O

Table 2-15 lists all features supported by transmitter/receiver for single-ended and differential I/Os.

Table 2-15 • ProASIC3E I/O Features

Feature Description

Single-Ended and Voltage-Referenced Transmitter Features • Hot insertion in every mode except PCI or 5 V input tolerant

(these modes use clamp diodes and do not allow hot insertion)

• Activation of hot insertion (disabling the clamp diode) is

selectable by I/Os

• Weak pull-up and pull-down

• 2 slew rates

• Skew between output buffer enable/disable time: 2 ns delay

on the rising edge and 0 ns delay on the falling edge (see the

"Selectable Skew between Output Buffer Enable/Disable

Time" on page 2-43 for more information).

• 5 drive strengths

• 5 V–tolerant receiver ("5 V Output Tolerance" section on

page 2-41)

• LVTTL/LVCMOS 3.3 V outputs compatible with 5 V TTL inputs

("5 V Output Tolerance" section on page 2-41)

• High performance (Table 2-16 on page 2-32)

Single-Ended Receiver Features • ESD protection

• Schmitt trigger option

• Programmable Delay: 0 ns if bypassed, 0.625 ns with '000'

setting, 6.575 ns with '111' setting, 0.85-ns intermediate delay

increments (at 25°C, 1.5 V)

• High performance (Table 2-16 on page 2-32)

• Separate ground plane for GNDQ pin and power plane for VMV

pin are used for input buffer to reduce output induced noise.

Voltage-Referenced Differential Receiver Features • Programmable delay: 0 ns if bypassed, 0.46 ns with '000'

setting, 4.66 ns with '111' setting, 0.6-ns intermediate delay

increments (at 25°C, 1.5 V)

• High performance (Table 2-16 on page 2-32)

• Separate ground plane for GNDQ pin and power plane for VMV

pin are used for input buffer to reduce output induced noise.

CMOS-Style LVDS, BLVDS, M-LVDS, or LVPECL Transmitter • 2 I/Os and external resistors are used to provide a CMOS-style

LVDS, DDR LVDS, BLVDS, and M-LVDS/LVPECL transmitter

solution.

• Activation of hot insertion (disabling the clamp diode) is

selectable by I/Os.

• Weak pull-up and pull-down

• High slew rate

LVDS, DDR LVDS, BLVDS, and M-LVDS/LVPECL Differential Receiver

Features

• ESD protection

• High performance (Table 2-16 on page 2-32)

• Programmable Delay: 0 ns if bypassed, 0.46 ns with '000'

setting, 4.66 ns with '111' setting, 0.6-ns intermediate delay

increments (at 25°C, 1.5 V)

• Separate input buffer ground and power planes to avoid

output-induced noise in the input circuitry

ProASIC3E Flash Family FPGAs

2-32 v2.0

Table 2-16 • Maximum I/O Frequency for Single-Ended and Differential I/Os in All Banks in ProASIC3E Devices (maximum

drive strength and high slew selected)

Specification Performance Up To

LVTTL/LVCMOS 3.3 V 200 MHz

LVCMOS 2.5 V 250 MHz

LVCMOS 1.8 V 200 MHz

LVCMOS 1.5 V 130 MHz

PCI 200 MHz

PCI-X 200 MHz

HSTL-I 300 MHz

HSTL-II 300 MHz

SSTL2-I 300 MHz

SSTL2-II 300 MHz

SSTL3-I 300 MHz

SSTL3-II 300 MHz

GTL+ 3.3 V 300 MHz

GTL+ 2.5 V 300 MHz

GTL 3.3 V 300 MHz

GTL 2.5 V 300 MHz

LVDS 350 MHz

M-LVDS 200 MHz

B LVDS 200 MHz

LVPECL 350 MHz

ProASIC3E Flash Family FPGAs

v2.0 2-33

I/O Registers

Each I/O module contains several input, output, and enable registers. Refer to Figure 2-24 for a simplified

representation of the I/O block.

The number of input registers is selected by a set of switches (not shown in Figure 2-24) between registers to

implement single or differential data transmission to and from the FPGA core. The Designer software sets these

switches for the user.

A common CLR/PRE signal is employed by all I/O registers when I/O register combining is used. Input Register 2 does

not have a CLR/PRE pin, as this register is used for DDR implementation. The I/O register combining must satisfy certain

rules. For more information, refer to the ProASIC3/E I/O Usage Guide.

Note: ProASIC3E I/Os have registers to support DDR functionality (see the "Double Data Rate (DDR) Support" section on page 2-34 for

more information).

Figure 2-24 • I/O Block Logical Representation

Input

E = Enable Pin

PAD

OCE

ICE

Input

CLR/PRE

Pull-Up/Down

Resistor Control

Signal Drive Strength

and Slew-Rate Control

Output

To FPGA Core

From FPGA Core

Output

Enable

OCE

I/O / CLR or I/O / PRE / OCE

I/O / Q0

I/O / Q1

I/O / ICLK

I/O / D0

I/O / D1 / ICE

I/O / OCLK

I/O / OE

ProASIC3E Flash Family FPGAs

2-34 v2.0

Double Data Rate (DDR) Support

ProASIC3E devices support 350 MHz DDR inputs and

outputs. In DDR mode, new data is present on every

transition of the clock signal. Clock and data lines have

identical bandwidths and signal integrity requirements,

making them very efficient for implementing very high-

speed systems.

DDR interfaces can be implemented using HSTL, SSTL,

LVDS, and LVPECL I/O standards. The DDR feature is

primarily implemented in the FPGA core periphery and is

not tied to a specific I/O technology or limited to any I/O

standards.

Input Support for DDR

The basic structure to support a DDR input is shown in

Figure 2-25. Three input registers are used to capture

incoming data, which is presented to the core on each

rising edge of the I/O register clock.

Each I/O tile on ProASIC3E devices supports DDR inputs.

Output Support for DDR

The basic DDR output structure is shown in Figure 2-26

on page 2-35. New data is presented to the output every

half clock cycle. Note: DDR macros and I/O registers do

not require additional routing. The combiner

automatically recognizes the DDR macro and pushes its

registers to the I/O register area at the edge of the chip.

The routing delay from the I/O registers to the I/O buffers

is already taken into account in the DDR macro.

Refer to the Actel application note Using DDR for

ProASIC3/E Devices for more information.

Figure 2-25 • DDR Input Register Support in ProASIC3E Devices

Input DDR

Data

CLK

CLKBUF

INBUF

Out_QF

(to core)

FF2

FF1

INBUF

CLR

DDR_IN

Out_QR

(to core)

ProASIC3E Flash Family FPGAs

v2.0 2-35

Figure 2-26 • DDR Output Support in ProASIC3E Devices

Data_F

(from core)

CLK

CLKBUF

Out

FF2

INBUF

CLR

DDR_OUT

Output DDR

FF1

OUTBUF

Data_R

(from core)

ProASIC3E Flash Family FPGAs

2-36 v2.0

Hot-Swap Support

Hot-swapping (also called hot plugging) is the operation of hot insertion or hot removal of a card in or from a

powered-up system. The levels of hot-swap support and examples of related applications are described in Table 2-17.

The I/Os also need to be configured in hot insertion mode if hot plugging compliance is required.

For ProASIC3E devices requiring Level 3 and/or Level 4

compliance, the board drivers connected to ProASIC3E I/Os

must have 10 kΩ (or lower) output drive resistance at hot

insertion, and 1 kΩ (or lower) output drive resistance at

hot removal. This resistance is the transmitter resistance

sending signal towards the ProASIC3E I/O, and no

additional resistance is needed on the board. If that

cannot be assured, three levels of staging can be used to

achieve Level 3 and/or Level 4 compliance. Cards with two

levels of staging should have the following sequence:

• Grounds

• Powers, I/Os, and other pins

For boards and cards with three levels of staging, card

power supplies must have time to reach their final value

before the I/Os are connected. Pay attention to the sizing

of power supply decoupling capacitors on the card to

ensure that the power supplies are not overloaded with

capacitance.

Cards with three levels of staging should have the

following sequence:

• Grounds

•Powers

• I/Os and other pins

Table 2-17 • Levels of Hot-Swap Support

Hot-

Swapping

Level Description

Power

Applied

to Device Bus State

Card

Ground

Connection

Device

Circuitry

Connected

to Bus Pins

Example of

Application with

Cards that Contain

ProASIC3E Devices

Compliance of

ProASIC3E Devices

1 Cold-swap No – – – System and card with

Actel FPGA chip are

powered down and the

card is plugged into the

system. Then the power

supplies are turned on for

the system but not for the

FPGA on the card.

Compliant I/Os can but

do not have to be set to

hot insertion mode.

2 Hot-swap while

reset

Yes Held in reset

state

Must be made

and

maintained

for 1 ms

before,

during, and

after

insertion/

removal

– In PCI hot-plug

specification, reset control

circuitry isolates the card

busses until the card

supplies are at their

nominal operating levels

and stable.

Compliant I/Os can but

do not have to be set to

hot insertion mode.

3 Hot-swap while

bus idle

Yes Held idle (no

ongoing I/O

processes

during

insertion/

removal)

Same as Level

Must remain

glitch-free

during

power-up or

power-down

Board bus shared with

card bus is "frozen," and

there is no toggling

activity on the bus. It is

critical that the logic states

set on the bus signal are

not disturbed during card

insertion/removal.

Compliant with 2 levels

of staging (first-GND,

second-all other pins)

4 Hot-swap on

an active bus

Yes Bus may have

active I/O

processes

ongoing, but

device being

inserted or

removed

must be idle.

Same as Level

Same as

Level 3

There is activity on the

system bus, and it is

critical that the logic states

set on the bus signal are

not disturbed during card

insertion/removal.

Compliant with 2 levels

of staging (first-GND,

second-all other pins)

ProASIC3E Flash Family FPGAs

v2.0 2-37

Cold-Sparing Support

Cold-sparing means that a subsystem with no power

applied (usually a circuit board) is electrically connected

to the system that is in operation. This means that all

input buffers of the subsystem must present very high

input impedance with no power applied so as not to

disturb the operating portion of the system.

ProASIC3E devices support cold-sparing for all I/O

configurations. Standards such as PCI that require I/O

clamp diodes can also achieve cold-sparing compliance,

since clamp diodes get disconnected internally when the

supplies are at 0 V.

Electrostatic Discharge (ESD) Protection

ProASIC3E devices are tested per JEDEC Standard

JESD22-A114-B.

ProASIC3E devices contain clamp diodes at every I/O,

global, and power pad. Clamp diodes protect all device

pads against damage from ESD as well as from excessive

voltage transients.

ProASIC3E devices are tested to the following models:

the Human Body Model (HBM) with a tolerance of

2,000 V, the Machine Model (MM) with a tolerance of

250 V, and the Charged Device Model (CDM) with a

tolerance of 200 V.

Each I/O has two clamp diodes. One diode has its

positive (P) side connected to the pad and its negative

(N) side connected to VCCI. The second diode has its P

side connected to GND and its N side connected to the

pad. During operation, these diodes are normally

biased in the off state, except when transient voltage is

significantly above VCCI or below GND levels.

By selecting the appropriate I/O configuration, the diode

is turned on or off. Refer to Table 2-18 for more

information about the I/O standards and the clamp

diode.

The second diode is always connected to the pad,

regardless of the I/O configuration selected.

Table 2-18 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3E Devices

I/O Assignment

Clamp

Diode

Hot

Insertion

5 V Input

Tolerance Input Buffer

Output

Buffer

3.3 V LVTTL/LVCMOS No Yes Yes1Enabled/Disabled

3.3 V PCI, 3.3 V PCI-X Yes No Yes1Enabled/Disabled

LVCMOS 2.5 V 3No Yes No Enabled/Disabled

LVCMOS 2.5 V / 5.0 V 3Yes No Yes2Enabled/Disabled

LVCMOS 1.8 V No Yes No Enabled/Disabled

LVCMOS 1.5 V No Yes No Enabled/Disabled

Voltage-Referenced Input Buffer No Yes No Enabled/Disabled

Differential, LVDS/BLVDS/M-LVDS/LVPECL No Yes No Enabled/Disabled

Notes:

1. Can be implemented with an external IDT bus switch, resistor divider, or Zener with resistor.

2. Can be implemented with an external resistor and an internal clamp diode.

3. In the SmartGen Core Reference Guide, select the LVCMOS5 macro for the LVCMOS 2.5 V / 5.0 V I/O standard or the LVCMOS25

macro for the LVCMOS 2.5 V I/O standard.

ProASIC3E Flash Family FPGAs

2-38 v2.0

5 V Input Tolerance

I/Os can support 5-V input tolerance when LVTTL 3.3 V,

LVCMOS 3.3 V, LVCMOS 2.5 V and LVCMOS 2.5 V / 5.0 V

configurations are used (see Table 2-18 on page 2-37 for

more details). There are four recommended solutions for

achieving 5 V receiver tolerance (see Figure 2-27 to

Figure 2-30 on page 2-40 for details of board and macro

setups). All the solutions meet a common requirement of

limiting the voltage at the input to 3.6 V or less. In fact,

the I/O absolute maximum voltage rating is 3.6 V, and

any voltage above 3.6 V may cause long-term gate oxide

failures.

Solution 1

The board-level design must ensure that the reflected

waveform at the pad does not exceed the limits provided

in Table 3-4 on page 3-2. This is a requirement to ensure

long-term reliability.

This scheme will also work for a 3.3 V PCI/ PCI-X

configuration, but the internal diode should not be used for

clamping, and the voltage must be limited by the two

external resistors as explained below. Relying on the

diode clamping would create an excessive pad DC

voltage of 3.3 V + 0.7 V = 4 V.

Here are some examples of possible resistor values

(based on a simplified simulation model with no line

effects and 10 Ω transmitter output resistance, where

Rtx_out_high = (VCCI – VOH) / IOH, Rtx_out_low = VOL / IOL).

Example 1 (high speed, high current):

Rtx_out_high = Rtx_out_low = 10 Ω

R1 = 36 Ω (±5%), P(r1)min = 0.069 Ω

R2 = 82 Ω (±5%), P(r2)min = 0.158 Ω

Imax_tx = 5.5 V / (82 × 0.95 + 36 × 0.95 + 10) = 45.04 mA

tRISE = tFALL = 0.85 ns at C_pad_load = 10 pF (includes up

to 25% safety margin)

tRISE = tFALL = 4 ns at C_pad_load = 50 pF (includes up to

25% safety margin)

Example 2 (low–medium speed, medium current):

Rtx_out_high = Rtx_out_low = 10 Ω

R1 = 220 Ω (±5%), P(r1)min = 0.018 Ω

R2 = 390 Ω (±5%), P(r2)min = 0.032 Ω

Imax_tx = 5.5 V / (220 × 0.95 + 390 × 0.95 + 10) = 9.17 mA

tRISE = tFALL = 4 ns at C_pad_load = 10 pF (includes up to

25% safety margin)

tRISE = tFALL = 20 ns at C_pad_load = 50 pF (includes up to

25% safety margin)

Other values of resistors are also allowed as long as the

resistors are sized appropriately to limit the voltage at

the receiving end to 2.5 V < Vin (rx) < 3.6 V* when the

transmitter sends a logic 1. This range of Vin_dc (rx) must

be assured for any combination of transmitter supply

(5 V ± 0.5 V), transmitter output resistance, and board

resistor tolerances.

Temporary overshoots are allowed according to Table 3-4

on page 3-2.

Figure 2-27 • ProASIC3E Solution 1

Solution 1

5.5 V 3.3 V

Requires two board resistors,

LVCMOS 3.3 V I/Os

ProASIC3E I/O Input

Rext1

Rext2

ProASIC3E Flash Family FPGAs

v2.0 2-39

Solution 2

The board-level design must ensure that the reflected waveform at the pad does not exceed limits provided in Table 3-4

on page 3-2. This is a requirement to ensure long-term reliability.

This scheme will also work for a 3.3 V PCI/PCIX configuration, but the internal diode should not be used for clamping,

and the voltage must be limited by the external resistors and Zener, as shown in Figure 2-28. Relying on the diode

clamping would create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V.

Figure 2-28 • ProASIC3E Solution 2

Solution 2

5.5 V 3.3 V

Requires one board resistor, one

Zener 3.3 V diode, LVCMOS 3.3 V I/Os

ProASIC3E I/O Input

Rext1

Zener

3.3V

ProASIC3E Flash Family FPGAs

2-40 v2.0

Solution 3

The board-level design must ensure that the reflected waveform at the pad does not exceed limits provided in Table 3-4

on page 3-2. This is a requirement to ensure long-term reliability.

This scheme will also work for a 3.3 V PCI/PCI-X configuration, but the internal diode should not be used for clamping,

and the voltage must be limited by the bus switch, as shown in Figure 2-29. Relying on the diode clamping would

create an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V.

Solution 4

Figure 2-29 • ProASIC3E Solution 3

Solution 3

Requires a bus switch on the board,

LVTTL 3.3 V I/Os.

ProASIC3E I/O Input

3.3 V

5.5 V

Bus

Switch

IDTQS32x23

Figure 2-30 • ProASIC3E Solution 4

Solution 4

2.5 V

5.5 V 2.5 V

Requires one board resistor.

Available for LVCMOS 2.5 V / 5.0 V.

ProASIC3E I/O Input

Rext

On-Chip

Clamp

Diode

ProASIC3E Flash Family FPGAs

v2.0 2-41

5 V Output Tolerance

ProASIC3E I/Os must be set to 3.3 V LVTTL or 3.3 V

LVCMOS mode to reliably drive 5 V TTL receivers. It is also

critical that there be NO external I/O pull-up resistor to

5 V, since this resistor would pull the I/O pad voltage

beyond the 3.6 V absolute maximum value, and

consequently cause damage to the I/O.

When set to 3.3 V LVTTL or 3.3 V LVCMOS mode,

ProASIC3E I/Os can directly drive signals into 5 V TTL

receivers. In fact, VOL = 0.4 V and VOH = 2.4 V in both

3.3 V LVTTL and 3.3 V LVCMOS modes exceeds the

VIL = 0.8 V and VIH = 2 V level requirements of 5 V TTL

receivers. Therefore, level '1' and level '0' will be

recognized correctly by 5 V TTL receivers.

Table 2-19 • Comparison Table for 5 V–Compliant Receiver Scheme

Scheme Board Components Speed Current Limitations

1 Two resistors Low to High1Limited by transmitter's drive strength

2 Resistor and Zener 3.3 V Medium Limited by transmitter's drive strength

3 Bus switch High N/A

4 Minimum resistor value2, 3, 4, 5

• R = 47 Ω at TJ = 70°C

• R = 150 Ω at TJ = 85°C

• R = 420 Ω at TJ = 100°C

Medium Maximum diode current at 100% duty cycle, signal constantly at '1'

• 52.7 mA at TJ = 70°C / 10-year lifetime

• 16.5 mA at TJ = 85°C / 10-year lifetime

• 5.9 mA at TJ = 100°C / 10-year lifetime

For duty cycles other than 100%, the currents can be increased by

a factor of 1 / duty cycle.

Example: 20% duty cycle at 70°C

Maximum current = (1 / 0.2) × 52.7 mA = 5 × 52.7 mA = 263.5 mA

Notes:

1. Speed and current consumption increase as the board resistance values decrease.

2. Resistor values ensure I/O diode long-term reliability.

3. At 70°C, customers could still use 420

on every I/O.

4. At 85°C, a 5 V solution on every other I/O is permitted, since the resistance is lower (150

) and the current is higher. Also, the

designer can still use 420

and use the solution on every I/O.

5. At 100°C, the 5 V solution on every I/O is permitted, since 420

are used to limit the current to 5.9 mA.

ProASIC3E Flash Family FPGAs

2-42 v2.0

Simultaneous Switching Outputs (SSOs)

and Printed Circuit Board Layout

SSOs can cause signal integrity problems on adjacent

signals that are not part of the SSO bus. Both inductive

and capacitive coupling parasitics of bond wires inside

packages and of traces on PCBs will transfer noise from

SSO busses onto signals adjacent to those busses.

Additionally, SSOs can produce ground bounce noise and

VCCI dip noise. These two noise types are caused by

rapidly changing currents through GND and VCCI

package pin inductances during switching activities

(EQ 2-1 and EQ 2-2).

Ground bounce noise voltage = L(GND) × di/dt

EQ 2-1

VCCI dip noise voltage = L(VCCI) × di/dt

EQ 2-2

Any group of four or more input pins switching on the

same clock edge is considered an SSO bus. The shielding

should be done both on the board and inside the

package unless otherwise described.

In-package shielding can be achieved in several ways; the

required shielding will vary depending on whether pins

next to the SSO bus are LVTTL/LVCMOS inputs,

LVTTL/LVCMOS outputs, or GTL/SSTL/HSTL/LVDS/LVPECL

inputs and outputs. Board traces in the vicinity of the

SSO bus have to be adequately shielded from mutual

coupling and inductive noise that can be generated by

the SSO bus. Also, noise generated by the SSO bus needs

to be reduced inside the package.

PCBs perform an important function in feeding stable

supply voltages to the IC and, at the same time,

maintaining signal integrity between devices.

Key issues that need to considered are as follows:

• Power and ground plane design and decoupling

network design

• Transmission line reflections and terminations

ProASIC3E Flash Family FPGAs

v2.0 2-43

Selectable Skew between Output Buffer Enable/Disable Time

The configurable skew block is used to delay the output buffer assertion (enable) without affecting deassertion

(disable) time.

Figure 2-31 • Block Diagram of Output Enable Path

Figure 2-32 • Timing Diagram (option 1: bypasses skew circuit)

Figure 2-33 • Timing Diagram (option 2: enables skew circuit)

ENABLE (OUT)

Skew Circuit

Output Enable

(from FPGA core)

I/O Output

Buffers

ENABLE (IN)

MUX

Skew Select

ENABLE (IN)

ENABLE (OUT)

Less than

0.1 ns

Less than

0.1 ns

ENABLE (IN)

ENABLE (OUT)

1.2 ns

(typical)

Less than

0.1 ns

ProASIC3E Flash Family FPGAs

2-44 v2.0

At the system level, the skew circuit can be used in applications where transmission activities on bidirectional data

lines need to be coordinated. This circuit, when selected, provides a timing margin that can prevent bus contention

and subsequent data loss and/or transmitter over-stress due to transmitter-to-transmitter current shorts. Figure 2-34

presents an example of the skew circuit implementation in a bidirectional communication system. Figure 2-35 shows

how bus contention is created, and Figure 2-36 on page 2-45 shows how it can be avoided with the skew circuit.

Figure 2-34 • Example of Implementation of Skew Circuits in Bidirectional Transmission Systems Using ProASIC3E Devices

Figure 2-35 • Timing Diagram (bypasses skew circuit)

Transmitter 1: ProASIC3E I/O Transmitter 2: Generic I/O

ENABLE (t2)

EN (b1) EN (b2)

Routing

Delay (t1)

Routing

Delay (t2)

EN (r1)

ENABLE (t1)

Skew or

Bypass

Skew

Bidirectional Data Bus

Transmitter

ENABLE/

DISABLE

EN (b1)

EN (b2)

ENABLE (r1)

Transmitter 1: ON

ENABLE (t2)

Transmitter 2: ON

ENABLE (t1)

Bus

Contention

Transmitter 1: OFF Transmitter 1: OFF

Transmitter 2: OFF

ProASIC3E Flash Family FPGAs

v2.0 2-45

Figure 2-36 • Timing Diagram (with skew circuit selected)

EN (b1)

EN (b2)

Transmitter 1: ON

ENABLE (t2)

Transmitter 2: ON Transmitter 2: OFF

ENABLE (t1)

Result: No Bus Contention

Transmitter 1: OFF Transmitter 1: OFF

ProASIC3E Flash Family FPGAs

2-46 v2.0

I/O Software Support

In the ProASIC3E development software, default settings

have been defined for the various I/O standards

supported. Changes can be made to the default settings

via the use of attributes; however, not all I/O attributes

are applicable for all I/O standards. Table 2-20 lists the

valid I/O attributes that can be manipulated by the user

for each I/O standard.

Single-ended I/O standards in ProASIC3E support up to

five different drive strengths.

Table 2-20 • ProASIC3E I/O Attributes vs. I/O Standard Applications

I/O Standards

SLEW (output only)

OUT_DRIVE (output only)

SKEW (all macros with OE)

RES_PULL

OUT_LOAD (output only)

COMBINE_REGISTER

IN_DELAY (input only)

IN_DELAY_VAL (input only)

SCHMITT_TRIGGER (input only)

HOT_SWAPPABLE

LVTTL/LVCMOS 3.3 V ✓✓✓✓✓✓✓✓✓✓

LVCMOS 2.5 V ✓✓✓✓✓✓✓✓✓✓

LVCMOS 2.5/5.0 V ✓✓✓✓✓✓✓✓✓✓

LVCMOS 1.8 V ✓✓✓✓✓✓✓✓✓✓

LVCMOS 1.5 V ✓✓✓✓✓✓✓✓✓✓

PCI (3.3 V) ✓ ✓✓✓✓

PCI-X (3.3 V) ✓ ✓ ✓✓✓✓

GTL+ (3.3 V) ✓ ✓✓✓✓ ✓

GTL+ (2.5 V) ✓ ✓✓✓✓ ✓

GTL (3.3 V) ✓ ✓✓✓✓ ✓

GTL (2.5 V) ✓ ✓✓✓✓ ✓

HSTL Class I ✓ ✓✓✓✓ ✓

HSTL Class II ✓ ✓✓✓✓ ✓

SSTL2 Class I & II ✓ ✓✓✓✓ ✓

SSTL3 Class I & II ✓ ✓✓✓✓ ✓

LVDS, BLVDS, M-LVDS ✓ ✓✓✓ ✓

LVPECL ✓✓✓ ✓

ProASIC3E Flash Family FPGAs

v2.0 2-47

Weak Pull-Up and Weak Pull-Down Resistors

ProASIC3E devices support optional weak pull-up and

pull-down resistors per I/O pin. When the I/O is pulled up,

it is connected to the VCCI of its corresponding I/O bank.

When it is pulled down, it is connected to GND. Refer to

Table 3-20 on page 3-20 for more information.

Slew Rate Control and Drive Strength

ProASIC3E devices support output slew rate control: high

and low.Actel recommends the high slew rate option to

minimize the propagation delay. This high-speed option

may introduce noise into the system if appropriate signal

integrity measures are not adopted. Selecting a low slew

rate reduces this kind of noise but adds some delays in

the system. Low slew rate is recommended when bus

transients are expected. Drive strength should also be

selected according to the design requirements and noise

immunity of the system.

The output slew rate and multiple drive strength

controls are available in LVTTL/LVCMOS 3.3 V, LVCMOS

2.5 V, LVCMOS 2.5 V / 5.0 V input, LVCMOS 1.8 V, and

LVCMOS 1.5 V. All other I/O standards have a high output

slew rate by default.

Refer to Table 2-21 for more information about the slew

rate and drive strength specification.

Table 2-21 • ProASIC3E I/O Standards—SLEW and Output Drive (OUT_DRIVE) Settings

I/O Standards

OUT_DRIVE (mA)

Slew2468121624

LVTTL/LVCMOS 3.3 V ✓✓✓✓✓✓✓High Low

LVCMOS 2.5 V ✓✓✓✓✓✓✓High Low

LVCMOS 2.5 V/5.0 V ✓✓✓✓✓✓✓High Low

LVCMOS 1.8 V ✓✓✓✓✓✓ –HighLow

LVCMOS 1.5 V ✓✓✓✓✓ ––HighLow

ProASIC3E Flash Family FPGAs

2-48 v2.0

Table 2-23 on page 2-49 lists the default values for the

above selectable I/O attributes as well as those that are

preset for that I/O standard.

Refer to Table 2-21 for SLEW and OUT_DRIVE settings.

Table 2-22 on page 2-48 lists the I/O default attributes.

Table 2-23 on page 2-49 lists the voltages for the

supported I/O standards.

Table 2-22 • ProASIC3E I/O Default Attributes

I/O Standards

SLEW (output only)

OUT_DRIVE (output only)

SKEW (tribuf and bibuf only)

RES_PULL

OUT_LOAD (output only)

COMBINE_REGISTER

IN_DELAY (input only)

IN_DELAY_VAL (input only)

SCHMITT_TRIGGER (input only)

LVTTL/LVCMOS 3.3 V See Table 2-21

on page 2-47

See Table 2-21

on page 2-47

Off None 35 pF – Off 0 Off

LVCMOS 2.5 V Off None 35 pF – Off 0 Off

LVCMOS 2.5/5.0 V Off None 35 pF – Off 0 Off

LVCMOS 1.8 V Off None 35 pF – Off 0 Off

LVCMOS 1.5 V Off None 35 pF – Off 0 Off

PCI (3.3 V) Off None 10 pF – Off 0 Off

PCI-X (3.3 V) Off None 10 pF – Off 0 Off

GTL+ (3.3 V) Off None 10 pF – Off 0 Off

GTL+ (2.5 V) Off None 10 pF – Off 0 Off

GTL (3.3 V) Off None 10 pF – Off 0 Off

GTL (2.5 V) Off None 10 pF – Off 0 Off

HSTL Class I Off None 20 pF – Off 0 Off

HSTL Class II Off None 20 pF – Off 0 Off

SSTL2 Class I & II Off None 30 pF – Off 0 Off

SSTL3 Class I & II Off None 30 pF – Off 0 Off

LVDS, BLVDS, M-LVDS Off None 0 pF – Off 0 Off

LVPECL Off None 0 pF – Off 0 Off

ProASIC3E Flash Family FPGAs

v2.0 2-49

Table 2-23 • Supported ProASIC3E I/O Standards and the Corresponding VREF and VTT Voltages

I/O Standard

Input/Output Supply

Voltage (VMVtyp/VCCI_TYP)

Input Reference Voltage

(VREF_TYP)

Board Termination

Voltage (VTT_TYP)

LVTTL/LVCMOS 3.3 V 3.30 V – –

LVCMOS 2.5 V 2.50 V – –

LVCMOS 2.5/5.0 V Input 2.50 V – –

LVCMOS 1.8 V 1.80 V – –

LVCMOS 1.5 V 1.50 V – –

PCI 3.3 V 3.30 V – –

PCI-X 3.3 V 3.30 V – –

GTL+ 3.3 V 3.30 V 1.00 V 1.50 V

GTL+ 2.5 V 2.50 V 1.00 V 1.50 V

GTL 3.3 V 3.30 V 0.80 V 1.20 V

GTL 2.5 V 2.50 V 0.80 V 1.20 V

HSTL Class I 1.50 V 0.75 V 0.75 V

HSTL Class II 1.50 V 0.75 V 0.75 V

SSTL3 Class I 3.30 V 1.50 V 1.50 V

SSTL3 Class II 3.30 V 1.50 V 1.50 V

SSTL2 Class I 2.50 V 1.25 V 1.25 V

SSTL2 Class II 2.50 V 1.25 V 1.25 V

LVDS, DDR LVDS, BLVDS, M-LVDS 2.50 V – –

LVPECL 3.30 V – –

ProASIC3E Flash Family FPGAs

2-50 v2.0

User I/O Naming Convention

Due to the comprehensive and flexible nature of ProASIC3E device user I/Os, a naming scheme is used to show the

details of the I/O (Figure 2-37). The name identifies to which I/O bank it belongs, as well as the pairing and pin polarity

for differential I/Os.

I/O Nomenclature = Gmn/IOuxwByVz

Gmn is only used for I/Os that also have CCC access—i.e., global pins.

G = Global

m = Global pin location associated with each CCC on the device: A (northwest corner), B (northeast corner), C (east

middle), D (southeast corner), E (southwest corner), and F (west middle)

n = Global input MUX and pin number of the associated Global location m, either A0, A1, A2, B0, B1, B2, C0, C1, or

C2. Figure 2-14 on page 2-16 shows the three input pins per clock source MUX at CCC location m.

u = I/O pair number in the bank, starting at 00 from the northwest I/O bank and proceeding in a clockwise direction

x = P (Positive) or N (Negative) for differential pairs, or R (Regular—single-ended) for the I/Os that support single-

ended and voltage-referenced I/O standards only

w = D (Differential Pair), P (Pair), or S (Single-Ended). D (Differential Pair) if both members of the pair are bonded

out to adjacent pins or are separated only by one GND or NC pin; P (Pair) if both members of the pair are

bonded out but do not meet the adjacency requirement; or S (Single-Ended) if the I/O pair is not bonded out.

For Differential (D) pairs, adjacency for ball grid packages means only vertical or horizontal. Diagonal

adjacency does not meet the requirements for a true differential pair.

B = Bank

y = Bank number (0–7). The bank number starts at 0 from northwest I/O bank and proceeds in a clockwise direction.

V = VREF

z = VREF minibank number (0–4). A given voltage-referenced signal spans 16 pins (typically) in an I/O bank. Voltage

banks may have multiple VREF minibanks.

Figure 2-37 • User I/O Naming Conventions of ProASIC3E Devices – Top View

GNDQ

VMV7

VMV6

GNDQ

VMV0

GNDQ

GND

GNDQ

VMV1

VMV4

TMS

TDI

TCK

GNDQ

GND

GNDQ

VMV5

COMPLF

CCPLF

COMPLE

CCPLE

COMPLA

CCPLA

GND

IB7

CCI

GND

CCI

GNDQ

VMV2

GND

TRST

TDO

VMV3

GNDQ

COMPLB

COMPLC

CCPLB

CCPLC

JTAG

COMPLD

PUMP

CCPLD

CCI

GND

CCIB3

CCC/PLL

“D”

Bank 5 Bank 4

JTAG

Bank 3 Bank 2

JTAG

Bank 6 Bank 7

A3PE600

A3PE1500

A3PE3000

Bank 0 Bank 1

CCC/PLL

“C”

CCC/PLL

“B”

CCC/PLL

“E”

CCC/PLL

“F”

CCC/PLL

“A”

ProASIC3E Flash Family FPGAs

v2.0 2-51

Pin Descriptions

Supply Pins

GND Ground

Ground supply voltage to the core, I/O outputs, and I/O

logic.

GNDQ Ground (quiet)

Quiet ground supply voltage to input buffers of I/O

banks. Within the package, the GNDQ plane is

decoupled from the simultaneous switching noise

originated from the output buffer ground domain. This

minimizes the noise transfer within the package, and

improves input signal integrity. GNDQ must always be

connected to GND on the board.

VCC Core Supply Voltage

Supply voltage to the FPGA core, nominally 1.5 V. VCC is

required for powering the JTAG state machine in

addition to VJTAG. Even when a ProASIC3 device is in

bypass mode in a JTAG chain of interconnected devices,

both VCC and VJTAG must remain powered to allow JTAG

signals to pass through the ProASIC3 device.

VCCIBx I/O Supply Voltage

Supply voltage to the bank's I/O output buffers and I/O

logic. Bx is the I/O bank number. There are eight I/O

banks on ProASIC3E devices plus a dedicated VJTAG bank.

Each bank can have a separate VCCI connection. All I/Os

in a bank will run off the same VCCIBx supply. VCCI can be

1.5 V, 1.8 V, 2.5 V, or 3.3 V nominal voltage. Unused I/O

banks should have their corresponding VCCI pins tied to

GND.

VMVx I/O Supply Voltage (quiet)

Quiet supply voltage to the input buffers of each I/O

bank. x is the bank number. Within the package, the

VMV plane is decoupled from the simultaneous

switching noise originated from the output buffer VCCI

domain. This minimizes the noise transfer within the

package and improves input signal integrity. Each bank

must have at least one VMV connection and no VMV

should be left unconnected. All I/Os in a bank run off the

same VMVx supply. VMV is used to provide a quiet supply

voltage to the input buffers of each I/O bank. VMVx can

be 1.5 V, 1.8 V, 2.5 V, or 3.3 V nominal voltage. Unused I/O

banks should have their corresponding VMV pins tied to

GND. VMV and VCCI should be at the same voltage within

a given I/O bank. Used VMV pins must be connected to

the corresponding VCCI pins of the same bank (i.e., VMV0

to VCCIB0, VMV1 to VCCIB1, etc.).

VCCPLA/B/C/D/E/F PLL Supply Voltage

Supply voltage to analog PLL, nominally 1.5 V. There are

six VCCPL pins (PLL power) on ProASIC3E devices. Unused

VCCPL pins should be connected to GND.

VCOMPLA/B/C/D/E/F PLL Ground

Ground to analog PLL power supplies. There are six

VCOMPL pins (PLL ground) on ProASIC3E devices. Unused

VCOMPL pins should be connected to GND.

VJTAG JTAG Supply Voltage

ProASIC3E devices have a separate bank for the

dedicated JTAG pins. The JTAG pins can be run at any

voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG

power supply in a separate I/O bank gives greater

flexibility in supply selection and simplifies power supply

and PCB design. If the JTAG interface is neither used nor

planned for use, the VJTAG pin together with the TRST

pin could be tied to GND. It should be noted that VCC is

required to be powered for JTAG operation; VJTAG alone

is insufficient. If a ProASIC3E device is in a JTAG chain of

interconnected boards, the board containing the

ProASIC3E device can be powered down, provided both

VJTAG and VCC to the ProASIC3E part remain powered;

otherwise, JTAG signals will not be able to transition the

ProASIC3E device, even in bypass mode.

VPUMP Programming Supply Voltage

ProASIC3E devices support single-voltage ISP

programming of the configuration Flash and FlashROM.

For programming, VPUMP should be 3.3 V nominal.

During normal device operation, VPUMP can be left

floating or can be tied (pulled up) to any voltage

between 0 V and 3.6 V. Programming power supply

voltage (VPP) range is 3.3 V +/- 5%.

When the VPUMP pin is tied to ground, it will shut off the

charge pump circuitry, resulting in no sources of

oscillation from the charge pump circuitry.

For proper programming, 0.01 µF and 0.33 µF capacitors

(both rated at 16 V) are to be connected in parallel across

VPUMP and GND, and positioned as close to the FPGA pins

as possible.

User-Defined Supply Pins

VREF I/O Voltage Reference

Reference voltage for I/O minibanks. VREF pins are

configured by the user from regular I/Os, and any I/O in a

bank, except JTAG I/Os, can be designated as the voltage

reference I/O. Only certain I/O standards require a

voltage reference—HSTL (I) and (II), SSTL2 (I) and (II),

SSTL3 (I) and (II), and GTL/GTL+. One VREF pin can support

the number of I/Os available in its minibank.

ProASIC3E Flash Family FPGAs

2-52 v2.0

User Pins

I/O User Input/Output

The I/O pin functions as an input, output, tristate, or

bidirectional buffer. Input and output signal levels are

compatible with the I/O standard selected.

During programming, I/Os become tristated and weakly

pulled up to VCCI. With VCCI, VMV, and VCC supplies

continuously powered up, when the device transitions

from programming to operating mode, the I/Os are

instantly configured to the desired user configuration.

Unused I/Os are configured as follows:

• Output buffer is disabled (with tristate value of high

impedance)

• Input buffer is disabled (with tristate value of high

impedance)

• Weak pull-up is programmed

GL Globals

GL I/Os have access to certain clock conditioning circuitry

(and the PLL) and/or have direct access to the global

network (spines). Additionally, the global I/Os can be

used as Pro I/Os, since they have identical capabilities.

Unused GL pins are configured as inputs with pull-up

resistors.All inputs labeled GC/GF are direct inputs into

the quadrant clocks. For example, if GAA0 is used for an

input, GAA1 and GAA2 are no longer available for input

to the quadrant globals. All inputs labeled GC/GF are

direct input into the chip level globals and the rest are

connected to the quadrant globals. The inputs to the

global network are multiplexed and only one input can

be used as a global input.

Refer to the "User I/O Naming Convention" section on

page 2-50 for a explanation of the naming of global

pins.

JTAG Pins

ProASIC3E devices have a separate bank for the

dedicated JTAG pins. The JTAG pins can be run at any

voltage from 1.5 V to 3.3 V (nominal). VCC must also be

powered for the JTAG state machine to operate, even if

the device is in bypass mode; VJTAG alone is insufficient.

Both VJTAG and VCC to the ProASIC3E part must be

supplied to allow JTAG signals to transition the

ProASIC3E device. Isolating the JTAG power supply in a

separate I/O bank gives greater flexibility in supply

selection and simplifies power supply and PCB design. If

the JTAG interface is neither used nor planned for use,

the VJTAG pin together with the TRST pin could be tied to

GND.

TCK Test Clock

Test clock input for JTAG boundary scan, ISP, and UJTAG.

The TCK pin does not have an internal pull-up/down

resistor. If JTAG is not used, Actel recommends tying off

TCK to GND through a resistor placed close to the FPGA

pin. This prevents JTAG operation in case TMS enters an

undesired state.

Note that to operate at all VJTAG voltages, 500 Ω to 1 kΩ

will satisfy the requirements. Refer to Table 2-24 for

more information.

TDI Test Data Input

Serial input for JTAG boundary scan, ISP, and UJTAG

usage. There is an internal weak pull-up resistor on the

TDI pin.

TDO Test Data Output

Serial output for JTAG boundary scan, ISP, and UJTAG

usage.

TMS Test Mode Select

The TMS pin controls the use of the IEEE1532 boundary

scan pins (TCK, TDI, TDO, TRST). There is an internal weak

pull-up resistor on the TMS pin.

TRST Boundary Scan Reset Pin

The TRST pin functions as an active low input to

asynchronously initialize (or reset) the boundary scan

circuitry. There is an internal weak pull-up resistor on the

TRST pin. If JTAG is not used, an external pull-down

resistor could be included to ensure the test access port

(TAP) is held in reset mode. The resistor values must be

chosen from Table 2-24 and must satisfy the parallel

resistance value requirement. The values in Table 2-24

correspond to the resistor recommended when a single

device is used and the equivalent parallel resistor when

multiple devices are connected via a JTAG chain.

In critical applications, an upset in the JTAG circuit could

allow entering an undesired JTAG state. In such cases,

Table 2-24 • Recommended Tie-Off Values for the TCK and

TRST Pins

VJTAG Tie-Off Resistance

VJTAG at 3.3 V 200 Ω to 1 kΩ

VJTAG at 2.5 V 200 Ω to 1 kΩ

VJTAG at 1.8 V 500 Ω to 1 kΩ

VJTAG at 1.5 V 500 Ω to 1 kΩ

Notes:

1. Equivalent parallel resistance if more than one device is on

the JTAG chain.

2. The TCK pin can be pulled up/down.

3. The TRST pin be pulled down.

ProASIC3E Flash Family FPGAs

v2.0 2-53

Actel recommends tying off TRST to GND through a

resistor placed close to the FPGA pin.

Note that to operate at all VJTAG voltages, 500 Ω to 1 kΩ

will satisfy the requirements.

Special Function Pins

NC No Connect

This pin is not connected to circuitry within the device.

These pins can be driven to any voltage or can be left

floating with no effect on the operation of the device.

DC Do Not Connect

This pin should not be connected to any signals on the

PCB. These pins should be left unconnected.

Software Tools

Overview of Tools Flow

The ProASIC3E family of FPGAs is fully supported by both

Actel Libero IDE and Designer FPGA development

software. Actel Libero IDE is an integrated design

manager that seamlessly integrates design tools while

guiding the user through the design flow, managing all

design and log files and passing necessary design data

among tools. Additionally, Libero IDE allows users to

integrate both schematic and HDL synthesis into a single

flow and verify the entire design in a single environment

(see the Libero IDE flow diagram located on the Actel

website). Libero IDE includes Synplify® AE from

Synplicity,® ViewDraw® AE from Mentor Graphics,®

ModelSim® HDL Simulator from Mentor Graphics,

WaveFormer LiteTM AE from SynaptiCAD,® PALACETM AE

Physical Synthesis from Magma Design Automation,TM

and Designer software from Actel.

Actel Designer software is a place-and-route tool and

provides a comprehensive suite of backend support tools

for FPGA development. The Designer software includes

the following:

• Timer—a world-class integrated static timing

analyzer and constraints editor that supports

timing-driven place-and-route

• NetlistViewer—a design netlist schematic viewer

• ChipPlanner—a graphical floorplanner viewer and

editor

• SmartPower—a tool that enables the designer to

quickly estimate the power consumption of a

design

• PinEditor—a graphical application for editing pin

assignments and I/O attributes

• I/O Attribute Editor—a tool that displays all

assigned and unassigned I/O macros and their

attributes in a spreadsheet format

With the Designer software, a user can lock the design

pins before layout while minimally impacting the results

of place-and-route. Additionally, Actel back-annotation

flow is compatible with all the major simulators. Another

tool included in the Designer software is the SmartGen

core generator, which easily creates popular and

commonly used logic functions for implementation into

your schematic or HDL design.

Actel Designer software is compatible with the most

popular FPGA design entry and verification tools from

EDA vendors such as Mentor Graphics, Synplicity,

Synopsys, and Cadence.® The Designer software is

available for both the Windows® and UNIX operating

systems.

Programming

Programming can be performed using tools such as

Silicon Sculptor II (BP Micro Systems) or FlashPro3 (Actel).

The user can generate STP programming files from the

Designer software and use these files to program a

device.

ProASIC3E devices can be programmed in system. For

more information on ISP of ProASIC3E devices, refer to

the In-System Programming (ISP) in ProASIC3/E Using

FlashPro3 and Programming a ProASIC3/E Using a

Microprocessor application notes.

The ProASIC3E device can be serialized with a unique

identifier stored in the FlashROM of each device.

Serialization is an automatic assignment of serial

numbers that are stored within the STAPL file used for

programming. The area of the FlashROM used for

holding such identifiers is defined using SmartGen, and

the range of serial numbers to be used is defined at the

time of STAPL file generation with FlashPoint. Serial

number values for STAPL file generation can even be

read from a file of predefined values. Serialized

programming using a serialized STAPL file can be done

through Actel In-House Programming (IHP), an external

vendor using Silicon Sculptor software, or the ISP

capabilities of the FlashPro software.

Security

ProASIC3E devices have a built-in 128-bit AES decryption

core. The decryption core facilitates secure in-system

programming of the FPGA core array fabric and the

FlashROM. The FlashROM and the FPGA core fabric can

be programmed independently from each other,

allowing the FlashROM to be updated without the need

for change to the FPGA core fabric. The AES master key is

ProASIC3E Flash Family FPGAs

2-54 v2.0

stored in on-chip nonvolatile memory (Flash). The AES

master key can be preloaded into parts in a secure

programming environment (such as the Actel in-house

programming center), and then "blank" parts can be

shipped to an untrusted programming or manufacturing

center for final personalization with an AES-encrypted

bitstream. Late-stage product changes or personalization

can be implemented easily and securely by simply

sending a STAPL file with AES encrypted data. Secure

remote field updates over public networks (such as the

Internet) are possible by sending and programming a

STAPL file with AES-encrypted data.

128-Bit AES Decryption

The 128-bit AES standard (FIPS-192) block cipher is the

NIST (National Institute of Standards and Technology)

replacement for DES (Data Encryption Standard

FIPS46-2). AES has been designed to protect sensitive

government information well into the 21st century. It

replaces the aging DES, which NIST adopted in 1977 as a

Federal Information Processing Standard used by federal

agencies to protect sensitive, unclassified information.

The 128-bit AES standard has 3.4 × 1038 possible 128-bit

key variants, and it has been estimated that it would

take 1,000 trillion years to crack 128-bit AES cipher text

using exhaustive techniques. Keys are stored (securely) in

ProASIC3E devices in nonvolatile Flash memory. All

programming files sent to the device can be

authenticated by the part prior to programming to

ensure that bad programming data is not loaded into

the part that may possibly damage it. All programming

verification is performed on-chip, ensuring that the

contents of ProASIC3E devices remain secure.

AES decryption can also be used on the 1,024-bit

FlashROM to allow for secure remote updates of the

FlashROM contents. This allows for easy, secure support

for subscription model products. See the application

note ProASIC3/E Security for more details.

ISP

ProASIC3E devices support IEEE 1532 ISP via JTAG and

require a single VPUMP voltage of 3.3 V during

programming. In addition, programming via a

microcontroller in a target system can be achieved. See

the application note In-System Programming (ISP) in

ProASIC3/E Using FlashPro3 for more details.

JTAG 1532

ProASIC3E devices support the JTAG-based IEEE 1532

standard for ISP. As part of this support, when a

ProASIC3E device is in an unprogrammed state, all user

I/O pins are disabled. This is achieved by keeping the

global IO_EN signal deactivated, which also has the

effect of disabling the input buffers. The

SAMPLE/PRELOAD instruction captures the status of pads

in parallel and shifts them out as new data is shifted in

for loading into the Boundary Scan Register. When the

ProASIC3E device is in an unprogrammed state, the

SAMPLE/PRELOAD instruction has no effect on I/O status;

however, it will continue to shift in new data to be

loaded into the BSR. Therefore, when SAMPLE/PRELOAD

is used on an unprogrammed device, the BSR will be

loaded with undefined data. Refer to the In-System

Programming (ISP) in ProASIC3/E Using FlashPro3

application note for more details.

For JTAG timing information on setup, hold, and fall

times, refer to the FlashPro User’s Guide.

Boundary Scan

ProASIC3E devices are compatible with IEEE Standard

1149.1, which defines a hardware architecture and the

set of mechanisms for boundary scan testing. The basic

ProASIC3E boundary scan logic circuit is composed of the

TAP controller, test data registers, and instruction

all mandatory IEEE 1149.1 instructions (EXTEST,

SAMPLE/PRELOAD, and BYPASS) and the optional

IDCODE instruction (Table 2-25).

Each test section is accessed through the TAP, which has

five associated pins: TCK (test clock input), TDI, TDO (test

data input and output), TMS (test mode selector), and

TRST (test reset input). TMS, TDI, and TRST are equipped

with pull-up resistors to ensure proper operation when

no input data is supplied to them. These pins are

dedicated for boundary scan test usage. Refer to the

"JTAG Pins" section on page 2-52 for pull-up/down

recommendations for TDO and TCK pins. Table 2-26 gives

Table 2-25 • Boundary Scan Opcodes

Hex Opcode

EXTEST 00

HIGHZ 07

USERCODE 0E

SAMPLE/PRELOAD 01

IDCODE 0F

CLAMP 05

BYPASS FF

ProASIC3E Flash Family FPGAs

v2.0 2-55

pull-down recommendations for the TRST and TCK

pins.

The TAP controller is a 4-bit state machine (16 states)

that operates as shown in Figure 2-39. The 1s and 0s

represent the values that must be present on TMS at a

rising edge of TCK for the given state transition to occur.

IR and DR indicate that the instruction register or the

data register is operating in that state.

The TAP controller receives two control inputs (TMS and

TCK) and generates control and clock signals for the rest

of the test logic architecture. On power-up, the TAP

controller enters the Test-Logic-Reset state. To guarantee

a reset of the controller from any of the possible states,

TMS must remain HIGH for five TCK cycles. The TRST pin

may also be used to asynchronously place the TAP

controller in the Test-Logic-Reset state.

ProASIC3E devices support three types of test data

registers: bypass, device identification, and boundary

scan. The bypass register is selected when no other

test data transfer to other devices in a test data path.

The 32-bit device identification register is a shift register

with four fields (LSB, ID number, part number, and

version). The boundary scan register observes and

controls the state of each I/O pin. Each I/O cell has three

boundary scan register cells, each with serial-in, serial-

out, parallel-in, and parallel-out pins.

Table 2-26 • TRST and TCK Pull-Down Recommendations

VJTAG Tie-Off Resistance*

VJTAG at 3.3 V 200 Ω to 1 kΩ

VJTAG at 2.5 V 200 Ω to 1 kΩ

VJTAG at 1.8 V 500 Ω to 1 kΩ

VJTAG at 1.5 V 500 Ω to 1 kΩ

Note: *Equivalent parallel resistance if more than one device

is on JTAG chain (Figure 2-38 on page 2-55).

Note: TCK is correctly wired with an equivalent tie-off resistance

of 500

, which satisfies the table for VJTAG of 1.5 V. The

resistor values for TRST are not appropriate in this case, as

the tie-off resistance of 375

is below the recommended

minimum for VJTAG = 1.5 V, but would be appropriate for

a VJTAG setting of 2.5 V or 3.3 V.

Figure 2-38 • Parallel Resistance on JTAG Chain of Devices

TDI

TDO

JTAG

Header

Actel

FPGA 1

Actel

FPGA 2

Actel

FPGA 3

Actel

FPGA 4

2 k Ω

1.5 V

TCK

TRST

VJTAG

GND

1.5 k Ω

Figure 2-39 • TAP State Machine

TEST_LOGIC_RESET

RUN_TEST_IDLE SELECT_DR

CAPTURE_DR

SHIFT_DR

EXIT1_DR

PAUSE_DR

EXIT2_DR

UPDATE_DR

SELECT_IR

CAPTURE_IR

SHIFT_IR

EXIT1_IR

PAUSE_IR

EXIT2_IR

UPDATE_IR

ProASIC3E Flash Family FPGAs

2-56 v2.0

The serial pins are used to serially connect all the

boundary scan register cells in a device into a boundary

scan register chain, which starts at the TDI pin and ends

at the TDO pin. The parallel ports are connected to the

internal core logic I/O tile and the input, output, and

control ports of an I/O buffer to capture and load data

into the register to control or observe the logic state of

each I/O.

Figure 2-40 • Boundary Scan Chain in ProASIC3E

Device

Logic

TDI

TCK

TMS

TRST

TDO

I/OI/OI/O I/OI/O

I/O

Bypass Register

Instruction

TAP

Controller

Test Data

Registers

ProASIC3E Flash Family FPGAs

v2.0 3-1

DC and Switching Characteristics

General Specifications

DC and switching characteristics for –F speed grade targets are based only on simulation.

The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some

restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only

supported in the commercial temperature range.

Operating Conditions

Stresses beyond those listed in Table 3-1 may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute

Maximum Ratings are stress ratings only; functional operation of the device at these or any other conditions beyond

those listed under the Recommended Operating Conditions specified in Table 3-2 on page 3-2 is not implied.

Table 3-1 • Absolute Maximum Ratings

Symbol Parameter Limits Units

VCC DC core supply voltage –0.3 to 1.65 V

VJTAG JTAG DC voltage –0.3 to 3.75 V

VPUMP Programming voltage –0.3 to 3.75 V

VCCPLL Analog power supply (PLL) –0.3 to 1.65 V

VCCI DC I/O output buffer supply voltage –0.3 to 3.75 V

VMV DC I/O input buffer supply voltage –0.3 to 3.75 V

VI I/O input voltage –0.3 V to 3.6 V (when I/O hot insertion mode is enabled)

–0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower (when

I/O hot-insertion mode is disabled)

TSTG 2Storage temperature –65 to +150 °C

TJ2Junction temperature +125 °C

Notes:

1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or

overshoot according to the limits shown in Table 3-3 on page 3-2.

2. For Flash programming and retention maximum limits refer to Table 3-3 on page 3-2 and for recommended operating limits refer to

Table 3-2 on page 3-2.

ProASIC3E Flash Family FPGAs

3-2 v2.0

Table 3-2 • Recommended Operating Conditions

Symbol Parameter Commercial Industrial Units

TJJunction temperature 0 to +70 –40 to +85 °C

VCC 1.5 V DC core supply voltage 1.425 to 1.575 1.425 to 1.575 V

VJTAG JTAG DC voltage 1.4 to 3.6 1.4 to 3.6 V

VPUMP Programming voltage Programming Mode 3.15 to 3.45 3.15 to 3.45 V

Operation30 to 3.6 0 to 3.6 V

VCCPLL Analog power supply (PLL) 1.4 to 1.6 1.4 to 1.6 V

VCCI and VMV 1.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575 V

1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V

2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V

3.3 V DC supply voltage 3.0 to 3.6 3.0 to 3.6 V

LVDS/BLVDS/M-LVDS differential I/O 2.375 to 2.625 2.375 to 2.625 V

LVPECL differential I/O 3.0 to 3.6 3.0 to 3.6 V

Notes:

1. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given

in Table 3-13 on page 3-15. VMV and VCCI should be at the same voltage within a given I/O bank.

2. All parameters representing voltages are measured with respect to GND unless otherwise specified.

3. VPUMP can be left floating during normal operation (not programming mode).

Table 3-3 • Flash Programming Limits – Retention, Storage and Operating Temperature1

Product Grade

Programming

Cycles

Program Retention

(biased/unbiased)

Maximum Storage

Temperature TSTG (°C) 2

Maximum Operating Junction

Temperature TJ (°C) 2

Commercial 500 20 years 110 110

Industrial 500 20 years 110 110

Notes:

1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.

2. These limits apply for program/data retention only. Refer to Table 3-1 and Table 3-2 for device operating conditions and absolute

limits.

Table 3-4 • Overshoot and Undershoot Limits (as measured on quiet I/Os)1

VCCI and VMV

Average VCCI–GND Overshoot or Undershoot Duration as a

Percentage of Clock Cycle2Maximum Overshoot/

Undershoot2

2.7 V or less 10% 1.4 V

5% 1.49 V

3 V 10% 1.1 V

5% 1.19 V

3.3 V

10% 0.79 V

5% 0.88 V

3.6 V

10% 0.45 V

5% 0.54 V

Notes:

1. Based on reliability requirements at 85°C.

2. The duration is allowed at one out of six clock cycles (estimated SSO density over cycles). If the overshoot/undershoot occurs at one

out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V.

3. This table refers only to overshoot/undershoot limits for simultaneous switching I/Os.

4. The device meets overshoot/undershoot specification requirements for PCI inputs with VCCI 3.45 V at 85 °C maximum, whereas the

average toggling of inputs at one-sixth of PCI frequency is considered.

ProASIC3E Flash Family FPGAs

v2.0 3-3

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and

Industrial)

Sophisticated power-up management circuitry is

designed into every ProASIC3E device. These circuits

ensure easy transition from the powered-off state to the

powered-up state of the device. The many different

supplies can power up in any sequence with minimized

current spikes or surges. In addition, the I/O will be in a

known state through the power-up sequence. The basic

principle is shown in Figure 3-1.

There are five regions to consider during power-up.

ProASIC3E I/Os are activated only if ALL of the following

three conditions are met:

1. VCC and VCCI are above the minimum specified trip

points (Figure 3-1).

2. VCCI > VCC – 0.75 V (typical)

3. Chip is in the operating mode.

VCCI Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.2 V

Ramping down: 0.5 V < trip_point_down < 1.1 V

VCC Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.1 V

Ramping down: 0.5 V < trip_point_down < 1 V

VCC and VCCI ramp-up trip points are about 100 mV

higher than ramp-down trip points. This specifically

built-in hysteresis prevents undesirable power-up

oscillations and current surges. Note the following:

• During programming, I/Os become tristated and

weakly pulled up to VCCI.

• JTAG supply, PLL power supplies, and charge pump

VPUMP supply have no influence on I/O behavior.

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

3. Output buffers, after 200 ns delay from input

buffer activation

Figure 3-1 • I/O State as a Function of VCCI and VCC Voltage Levels

Region 1: I/O buffers are OFF

Region 2: I/O buffers are ON.

I/Os are functional (except differential inputs)

but slower because VCCI/VCC are below

specification. For the same reason, input

buffers do not meet VIH/VIL levels, and

output buffers do not meet VOH/VOL levels.

Min VCCI datasheet specification

voltage at a selected I/O

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

VCC

VCC = 1.425 V

Region 1: I/O Buffers are OFF

Activation trip point:

Va = 0.85 V ± 0.25 V

Deactivation trip point:

Vd = 0.75 V ± 0.25 V

Activation trip point:

Va = 0.9 V ± 0.3 V

Deactivation trip point:

Vd = 0.8 V ± 0.3 V

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

I/Os meet the entire datasheet

and timer specifications for

speed, VIH/VIL , VOH/VOL , etc.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential

but slower because VCCI is

below specification. For the

same reason, input buffers do not

meet VIH/VIL levels, and output

buffers do not meet VOH/VOL levels.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential inputs)

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCCI

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the VCC is below specification.

VCC = VCCI + VT

ProASIC3E Flash Family FPGAs

3-4 v2.0

Thermal Characteristics

Introduction

The temperature variable in Actel Designer software

refers to the junction temperature, not the ambient

temperature. This is an important distinction because

dynamic and static power consumption cause the chip

junction to be higher than the ambient temperature.

EQ 3-1 can be used to calculate junction temperature.

TJ = Junction Temperature = ΔT + TA

EQ 3-1

where:

TA = Ambient Temperature

ΔT = Temperature gradient between junction (silicon)

and ambient ΔT = θja * P

θja = Junction-to-ambient of the package. θja numbers

are located in Table 3-5.

P = Power dissipation

Package Thermal Characteristics

The device junction-to-case thermal resistivity is θjc and

the junction-to-ambient air thermal resistivity is θja. The

thermal characteristics for θja are shown for two air flow

rates. The absolute maximum junction temperature is

110°C. EQ 3-2 shows a sample calculation of the absolute

maximum power dissipation allowed for an 896-pin

FBGA package at commercial temperature and in still air.

EQ 3-2

Temperature and Voltage Derating Factors

Table 3-5 • Package Thermal Resistivities

Package Type Pin Count θjc

θja

UnitsStill Air 200 ft./min. 500 ft./min.

Plastic Quad Flat Package (PQFP) 208 8.0 26.1 22.5 20.8 C/W

Plastic Quad Flat Package (PQFP) with

embedded heat spreader

208 3.8 16.2 13.3 11.9 C/W

Fine Pitch Ball Grid Array (FBGA) 256 3.8 26.9 22.8 21.5 C/W

484 3.2 20.5 17.0 15.9 C/W

676 3.2 16.4 13.0 12.0 C/W

896 2.4 13.6 10.4 9.4 C/W

Table 3-6 • Temperature and Voltage Derating Factors for Timing Delays

(normalized to TJ = 70°C, VCC = 1.425 V)

Array Voltage

VCC (V)

Junction Temperature (°C)

–40°C 0°C 25°C 70°C 85°C 100°C

1.425 0.87 0.92 0.95 1.00 1.02 1.05

1.500 0.83 0.88 0.90 0.95 0.97 1.00

1.575 0.80 0.85 0.87 0.92 0.94 0.96

Maximum Power Allowed Max. junction temp. (°C) Max. ambient temp. (°C)–

θja(°C/W)

--------------------------------------------------------------------------------------------------------------------------------------- 110°C70°C–

13.6°C/W

------------------------------------ 5 . 8 8 W===

ProASIC3E Flash Family FPGAs

v2.0 3-5

Calculating Power Dissipation

Quiescent Supply Current

Power per I/O Pin

Table 3-7 • Quiescent Supply Current Characteristics

A3PE600 A3PE1500 A3PE3000

Typical (25°C) 5 mA 12 mA 25 mA

Maximum (Commercial) 30 mA 70 mA 150 mA

Maximum (Industrial) 45 mA 105 mA 225 mA

Notes:

1. IDD Includes VCC, VPUMP, VCCI, and VMV currents. Values do not include I/O static contribution, which is shown in Table 3-8 and

Table 3-9 on page 3-6.

2. –F speed grade devices may experience higher standby IDD of up to five times the standard IDD and higher I/O leakage.

Table 3-8 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings

VMV

(V)

Static Power

PDC2 (mW)1Dynamic Power

PAC9 (μW/MHz)2

Single-Ended

3.3 V LVTTL/LVCMOS 3.3 – 17.39

3.3 V LVTTL/LVCMOS – Schmitt trigger 3.3 – 25.51

2.5 V LVCMOS 2.5 – 5.76

2.5 V LVCMOS – Schmitt trigger 2.5 – 7.16

1.8 V LVCMOS 1.8 – 2.72

1.8 V LVCMOS – Schmitt trigger 1.8 – 2.80

1.5 V LVCMOS (JESD8-11) 1.5 – 2.08

1.5 V LVCMOS (JESD8-11) – Schmitt trigger 1.5 – 2.00

3.3 V PCI 3.3 – 18.82

3.3 V PCI – Schmitt trigger 3.3 – 20.12

3.3 V PCI-X 3.3 – 18.82

3.3 V PCI-X – Schmitt trigger 3.3 – 20.12

Voltage-Referenced

3.3 V GTL 3.3 2.90 8.23

2.5 V GTL 2.5 2.13 4.78

3.3 V GTL+ 3.3 2.81 4.14

2.5 V GTL+ 2.5 2.57 3.71

HSTL (I) 1.5 0.17 2.03

HSTL (II) 1.5 0.17 2.03

SSTL2 (I) 2.5 1.38 4.48

SSTL2 (II) 2.5 1.38 4.48

SSTL3 (I) 3.3 3.21 9.26

SSTL3 (II) 3.3 3.21 9.26

Differential

LVDS/BLVDS/M-LVDS 2.5 2.26 1.50

LVPECL 3.3 5.71 2.17

Notes:

1. PDC2 is the static power (where applicable) measured on VMV.

2. PAC9 is the total dynamic power measured on VCC and VMV.

ProASIC3E Flash Family FPGAs

3-6 v2.0

Table 3-9 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1

CLOAD

(pF)

VCCI

(V)

Static Power

PDC3 (mW)2Dynamic Power

PAC10 (μW/MHz)3

Single-Ended

3.3 V LVTTL/LVCMOS 35 3.3 – 474.70

2.5 V LVCMOS 35 2.5 – 270.73

1.8 V LVCMOS 35 1.8 – 151.78

1.5 V LVCMOS (JESD8-11) 35 1.5 – 104.55

3.3 V PCI 10 3.3 – 204.61

3.3 V PCI-X 10 3.3 – 204.61

Voltage-Referenced

3.3 V GTL 10 3.3 – 24.08

2.5 V GTL 10 2.5 – 13.52

3.3 V GTL+ 10 3.3 – 24.10

2.5 V GTL+ 10 2.5 – 13.54

HSTL (I) 20 1.5 7.08 26.22

HSTL (II) 20 1.5 13.88 27.22

SSTL2 (I) 30 2.5 16.69 105.56

SSTL2 (II) 30 2.5 25.91 116.60

SSTL3 (I) 30 3.3 26.02 114.87

SSTL3 (II) 30 3.3 42.21 131.76

Differential

LVDS/BLVDS/M-LVDS – 2.5 7.70 89.62

LVPECL – 3.3 19.42 168.02

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output slew.

2. PDC3 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCC and VCCI.

ProASIC3E Flash Family FPGAs

v2.0 3-7

Power Consumption of Various Internal Resources

Table 3-10 • Different Components Contributing to the Dynamic Power Consumption in ProASIC3E Devices

Parameter Definition

Device-Specific Dynamic Contributions

(μW/MHz)

A3PE600 A3PE1500 A3PE3000

PAC1 Clock contribution of a Global Rib 12.77 16.21 19.7

PAC2 Clock contribution of a Global Spine 1.85 3.06 4.16

PAC3 Clock contribution of a VersaTile row 0.88

PAC4 Clock contribution of a VersaTile used as a sequential module 0.12

PAC5 First contribution of a VersaTile used as a sequential module 0.07

PAC6 Second contribution of a VersaTile used as a sequential module 0.29

PAC7 Contribution of a VersaTile used as a combinatorial module 0.29

PAC8 Average contribution of a routing net 0.70

PAC9 Contribution of an I/O input pin (standard-dependent) See Table 3-8 on page 3-5.

PAC10 Contribution of an I/O output pin (standard-dependent) See Table 3-9 on page 3-6

PAC11 Average contribution of a RAM block during a read operation 25.00

PAC12 Average contribution of a RAM block during a write operation 30.00

PAC13 Static PLL contribution 2.55 mW

PAC14 Dynamic contribution for PLL 2.60

Note: *For a different output load, drive strength, or slew rate, Actel recommends using the Actel power calculator or SmartPower in

Actel Libero IDE software.

ProASIC3E Flash Family FPGAs

3-8 v2.0

Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For more accurate and

detailed power estimations, use the SmartPower tool in the Libero IDE software.

The power calculation methodology described below uses the following variables:

• The number of PLLs as well as the number and the frequency of each output clock generated

• The number of combinatorial and sequential cells used in the design

• The internal clock frequencies

• The number and the standard of I/O pins used in the design

• The number of RAM blocks used in the design

• Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 3-11 on page 3-10.

• Enable rates of output buffers—guidelines are provided for typical applications in Table 3-12 on page 3-10.

• Read rate and write rate to the memory—guidelines are provided for typical applications in Table 3-12 on

page 3-10. The calculation should be repeated for each clock domain defined in the design.

Methodology

Total Power Consumption—PTOTAL

PTOTAL = PSTAT + PDYN

PSTAT is the total static power consumption.

PDYN is the total dynamic power consumption.

Total Static Power Consumption—PSTAT

PSTAT = PDC1 + NINPUTS * PDC2 + NOUTPUTS * PDC3

NINPUTS is the number of I/O input buffers used in the design.

NOUTPUTS is the number of I/O output buffers used in the design.

Total Dynamic Power Consumption—PDYN

PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL

Global Clock Contribution—PCLOCK

PCLOCK = (PAC1 + NSPINE * PAC2 + NROW * PAC3 + NS-CELL * PAC4) * FCLK

NSPINE is the number of global spines used in the user design—guidelines are provided in Table 3-11 on page 3-10.

NROW is the number of VersaTile rows used in the design—guidelines are provided in Table 3-11 on page 3-10.

FCLK is the global clock signal frequency.

NS-CELL is the number of VersaTiles used as sequential modules in the design.

PAC1, PAC2, PAC3, and PAC4 are device-dependent.

Sequential Cells Contribution—PS-CELL

PS-CELL = NS-CELL * (PAC5 + α1 / 2 * PAC6) * FCLK

NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile sequential cell

is used, it should be accounted for as 1.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-11 on page 3-10.

FCLK is the global clock signal frequency.

ProASIC3E Flash Family FPGAs

v2.0 3-9

Combinatorial Cells Contribution—PC-CELL

PC-CELL = NC-CELL* α1 / 2 * PAC7 * FCLK

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-11 on page 3-10.

FCLK is the global clock signal frequency.

Routing Net Contribution—PNET

PNET = (NS-CELL + NC-CELL) * α1 / 2 * PAC8 * FCLK

NS-CELL is the number VersaTiles used as sequential modules in the design.

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-11 on page 3-10.

FCLK is the global clock signal frequency.

I/O Input Buffer Contribution—PINPUTS

PINPUTS = NINPUTS * α2 / 2 * PAC9 * FCLK

NINPUTS is the number of I/O input buffers used in the design.

α2 is the I/O buffer toggle rate—guidelines are provided in Table 3-11 on page 3-10.

FCLK is the global clock signal frequency.

I/O Output Buffer Contribution—POUTPUTS

POUTPUTS = NOUTPUTS * α2 / 2 * β1 * PAC10 * FCLK

NOUTPUTS is the number of I/O output buffers used in the design.

α2 is the I/O buffer toggle rate—guidelines are provided in Table 3-11 on page 3-10.

β1 is the I/O buffer enable rate—guidelines are provided in Table 3-12 on page 3-10.

FCLK is the global clock signal frequency.

RAM Contribution—PMEMORY

PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * β2 + PAC12 * NBLOCK * FWRITE-CLOCK * β3

NBLOCKS is the number RAM blocks used in the design.

FREAD-CLOCK is the memory read clock frequency.

β2 is the RAM enable rate for read operations—guidelines are provided in Table 3-12 on page 3-10.

FWRITE-CLOCK is the memory write clock frequency.

β3 is the RAM enable rate for write operations—guidelines are provided in Table 3-12 on page 3-10.

PLL Contribution—PPLL

PPLL = PAC13 + PAC14 * FCLKOUT

FCLKIN is the input clock frequency.

FCLKOUT is the output clock frequency.1

1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the

PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output

clock in the formula by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL contribution.

ProASIC3E Flash Family FPGAs

3-10 v2.0

Guidelines

Toggle Rate Definition

A toggle rate defines the frequency of a net or logic

element relative to a clock. It is a percentage. If the

toggle rate of a net is 100%, this means that this net

switches at half the clock frequency. Below are some

examples:

• The average toggle rate of a shift register is 100%

as all flip-flop outputs toggle at half of the clock

frequency.

• The average toggle rate of an 8-bit counter is

25%:

– Bit 0 (LSB) = 100%

– Bit 1 = 50%

– Bit 2 = 25%

–…

– Bit 7 (MSB) = 0.78125%

– Average toggle rate = (100% + 50% + 25% +

12.5% + . . . + 0.78125%) / 8.

Enable Rate Definition

Output enable rate is the average percentage of time

during which tristate outputs are enabled. When

nontristate output buffers are used, the enable rate

should be 100%.

Table 3-11 • Toggle Rate Guidelines Recommended for Power Calculation

Component Definition Guideline

α1Toggle rate of VersaTile outputs 10%

α2I/O buffer toggle rate 10%

Table 3-12 • Enable Rate Guidelines Recommended for Power Calculation

Component Definition Guideline

β1I/O output buffer enable rate 100%

β2RAM enable rate for read operations 12.5%

β3RAM enable rate for write operations 12.5%

ProASIC3E Flash Family FPGAs

v2.0 3-11

User I/O Characteristics

Timing Model

Figure 3-2 • Timing Model

Operating Conditions: –2 Speed, Commercial Temperature Range (TJ= 70°C), Worst-Case VCC = 1.425 V

DQ DQ

Combinational Cell

I/O Module

(Registered)

I/O Module

(Non-Registered)

I/O Module

(Registered)

I/O Module

(Non-Registered)

LVPECL

LVDS,

BLVDS,

M-LVDS

GTL+ 3.3V

Combinational Cell

I/O Module

(Non-Registered)

LVTTL/LVCMOS

Output drive strength = 24 mA

High slew rate

I/O Module

(Non-Registered)

LVCMOS 1.5V

Output drive strength = 12 mA

High slew

LVTTL/LVCMOS

Output drive strength = 12 mA

High slew rate

I/O Module

(Non-Registered)

Input LVTTL/LVCMOS

Clock

Input LVTTL/LVCMOS

Clock

Input LVTTL/LVCMOS

Clock

tPD = 0.56 ns tPD = 0.49 ns

tDP = 1.36 ns

tPD = 0.87 ns tDP = 2.74 ns

tPD = 0.51 ns

tPD = 0.47 ns

tDP = 2.39 ns

tDP = 3.30 ns

tCLKQ = 0.59 ns

tDP = 1.53 ns

tSUD = 0.31 ns

tPY = 0.90 ns

tCLKQ = 0.55 ns

tSUD = 0.43 ns

tPY = 0.90 ns

tPD = 0.47 ns

tCLKQ = 0.55 ns

tSUD = 0.43 ns

tPY = 1.36 ns

tPY = 0.90 ns

tICLKQ = 0.24 ns

tISUD = 0.26 ns

tPY = 1.22 ns

ProASIC3E Flash Family FPGAs

3-12 v2.0

Figure 3-3 • Input Buffer Timing Model and Delays (example)

(R)

PAD

GND

(F)

50%

(R) (F)

(R)

DIN

GND

(F)

50%50%

PAD Y

CLK

I/O Interface

DIN

To Array

tDOUT tDOUT

VCC

tPYS

tPY

tPYS

tPY

VCC

Vtrip Vtrip

VIH

VIL

tPY = MAX(tPY(R), tPY(F))

tDIN = MAX(tDIN(R), tDIN(F))

tPY tDIN

ProASIC3E Flash Family FPGAs

v2.0 3-13

Figure 3-4 • Output Buffer Model and Delays (example)

tDP

(R)

PAD VOL

tDP

(F)

Vtrip

VOH

VCC

D50% 50%

VCC

0 V

DOUT 50% 50% 0 V

tDOUT

(R)

tDOUT

(F)

From Array

PAD

tDP

Std

Load

CLK

I/O Interface

DOUT

tDOUT

tDp = MAX(tDP(R), tDP(F))

tDOUT = MAX(tDOUT(R), tDOUT(F))

ProASIC3E Flash Family FPGAs

3-14 v2.0

Figure 3-5 • Tristate Output Buffer Timing Model and Delays (example)

CLK

10% V

CCI

trip

50%

90% V

CCI

trip

50% 50% t

50%

EOUT

PAD

E50%

EOUT (R)

50%

EOUT (F)

PAD

DOUT

EOUT

I/O interface

EOUT

ZLS

trip

50%

ZHS

trip

50%

EOUT

PAD

E50% 50%

EOUT (R)

EOUT (F)

50%

CCI

, t

ZLS

, t

ZHS

EOUT

= MAX(t

EOUT

(r), t

EOUT

(f))

ProASIC3E Flash Family FPGAs

v2.0 3-15

Overview of I/O Performance

Summary of I/O DC Input and Output Levels – Default I/O Software Settings

Table 3-13 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial

Conditions

I/O Standard

Drive

Strength

Slew

Rate

VIL VIH VOL VOH IOL IOH

Min, V Max, V Min, V Max, V Max, V Min, V mA mA

3.3 V LVTTL /

3.3 V LVCMOS

12 mA High –0.3 0.8 2 3.6 0.4 2.4 12 12

2.5 V LVCMOS 12 mA High –0.3 0.7 1.7 3.6 0.7 1.7 12 12

1.8 V LVCMOS 12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 12 12

1.5 V LVCMOS 12 mA High –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 12 12

3.3 V PCI Per PCI Specification

3.3 V PCI-X Per PCI-X Specification

3.3 V GTL 25 mA2High –0.3 VREF – 0.05 VREF + 0.05 3.6 0.4 – 25 25

2.5 V GTL 25 mA2High –0.3 VREF – 0.05 VREF + 0.05 3.6 0.4 – 25 25

3.3 V GTL+ 35 mA High –0.3 VREF – 0.1 VREF + 0.1 3.6 0.6 – 51 51

2.5 V GTL+ 33 mA High –0.3 VREF – 0.1 VREF + 0.1 3.6 0.6 – 40 40

HSTL (I) 8 mA High –0.3 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCI – 0.4 8 8

HSTL (II) 15 mA2High –0.3 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCI – 0.4 15 15

SSTL2 (I) 15 mA High –0.3 VREF – 0.2 VREF + 0.2 3.6 0.54 VCCI – 0.62 15 15

SSTL2 (II) 18 mA High –0.3 VREF – 0.2 VREF + 0.2 3.6 0.35 VCCI – 0.43 18 18

SSTL3 (I) 14 mA High –0.3 VREF – 0.2 VREF + 0.2 3.6 0.7 VCCI – 1.1 14 14

SSTL3 (II) 21 mA High –0.3 VREF – 0.2 VREF + 0.2 3.6 0.5 VCCI – 0.9 21 21

Notes:

1. Currents are measured at 85°C junction temperature.

2. Output drive strength is below JEDEC specification.

3. Output Slew Rates can be extracted from IBIS Models, located at http://www.actel.com/download/ibis/default.aspx.

ProASIC3E Flash Family FPGAs

3-16 v2.0

Table 3-14 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions

DC I/O Standards

Commercial1Industrial2

IIL IIH IIL IIH

µA µA µA µA

3.3 V LVTTL / 3.3 V LVCMOS 10 10 15 15

2.5 V LVCMOS 10 10 15 15

1.8 V LVCMOS 10 10 15 15

1.5 V LVCMOS 10 10 15 15

3.3 V PCI 10 10 15 15

3.3 V PCI-X 10 10 15 15

3.3 V GTL 10 10 15 15

2.5 V GTL 10 10 15 15

3.3 V GTL+ 10 10 15 15

2.5 V GTL+ 10 10 15 15

HSTL (I) 10101515

HSTL (II) 10 10 15 15

SSTL2 (I) 10101515

SSTL2 (II) 10 10 15 15

SSTL3 (I) 10101515

SSTL3 (II) 10 10 15 15

Notes:

1. Commercial range (0°C < TJ < 70°C)

2. Industrial range (–40°C < TJ < 85°C)

ProASIC3E Flash Family FPGAs

v2.0 3-17

Summary of I/O Timing Characteristics – Default I/O Software Settings

Table 3-15 • Summary of AC Measuring Points

Standard

Input Reference Voltage

(VREF_TYP)

Board Termination

Voltage (VTT_REF) Measuring Trip Point (Vtrip)

3.3 V LVTTL/3.3 V LVCMOS – – 1.4 V

2.5 V LVCMOS – – 1.2 V

1.8 V LVCMOS – – 0.90 V

1.5 V LVCMOS – – 0.75 V

3.3 V PCI – – 0.285 * VCCI (RR)

0.615 * VCCI (FF))

3.3 V PCI-X – – 0.285 * VCCI (RR)

0.615 * VCCI (FF)

3.3 V GTL 0.8 V 1.2 V VREF

2.5 V GTL 0.8 V 1.2 V VREF

3.3 V GTL+ 1.0 V 1.5 V VREF

2.5 V GTL+ 1.0 V 1.5 V VREF

HSTL (I) 0.75 V 0.75 V VREF

HSTL (II) 0.75 V 0.75 V VREF

SSTL2 (I) 1.25 V 1.25 V VREF

SSTL2 (II) 1.25 V 1.25 V VREF

SSTL3 (I) 1.5 V 1.485 V VREF

SSTL3 (II) 1.5 V 1.485 V VREF

LVDS – – Cross point

LVPECL – – Cross point

Table 3-16 • I/O AC Parameter Definitions

Parameter Definition

tDP Data to Pad delay through the Output Buffer

tPY Pad to Data delay through the Input Buffer with Schmitt trigger disabled

tDOUT Data to Output Buffer delay through the I/O interface

tEOUT Enable to Output Buffer Tristate Control delay through the I/O interface

tDIN Input Buffer to Data delay through the I/O interface

tPYS Pad to Data delay through the Input Buffer with Schmitt trigger enabled

tHZ Enable to Pad delay through the Output Buffer—HIGH to Z

tZH Enable to Pad delay through the Output Buffer—Z to HIGH

tLZ Enable to Pad delay through the Output Buffer—LOW to Z

tZL Enable to Pad delay through the Output Buffer—Z to LOW

tZHS Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH

tZLS Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW

ProASIC3E Flash Family FPGAs

3-18 v2.0

Table 3-17 • Summary of I/O Timing Characteristics—Software Default Settings

–2 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

I/O Standard

Drive Strength (mA)

Slew Rate

Capacitive Load (pF)

External Resistor (Ω)

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tPYS (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

tZLS (ns)

tZHS (ns)

3.3 V LVTTL /

3.3 V LVCMOS

12 High 35 – 0.49 2.74 0.03 0.90 1.17 0.32 2.79 2.14 2.45 2.70 4.46 3.81

2.5 V LVCMOS 12 High 35 – 0.49 2.80 0.03 1.13 1.24 0.32 2.85 2.61 2.51 2.61 4.52 4.28

1.8 V LVCMOS 12 High 35 – 0.49 2.83 0.03 1.08 1.42 0.32 2.89 2.31 2.79 3.16 4.56 3.98

1.5 V LVCMOS 12 High 35 – 0.49 3.30 0.03 1.27 1.60 0.32 3.36 2.70 2.96 3.27 5.03 4.37

3.3 V PCI Per PCI spec High 10 25 2 0.49 2.09 0.03 0.78 1.17 0.32 2.13 1.49 2.45 2.70 3.80 3.16

3.3 V PCI-X Per PCI-X

spec

High 10 25 2 0.49 2.09 0.03 0.78 1.17 0.32 2.13 1.49 2.45 2.70 3.80 3.16

3.3 V GTL 25 High 10 25 0.45 1.55 0.03 2.19 – 0.32 1.52 1.55 – – 3.19 3.22

2.5 V GTL 25 High 10 25 0.45 1.59 0.03 1.83 – 0.32 1.61 1.59 – – 3.28 3.26

3.3 V GTL+ 35 High 10 25 0.45 1.53 0.03 1.19 – 0.32 1.56 1.53 – – 3.23 3.20

2.5 V GTL+ 33 High 10 25 0.45 1.65 0.03 1.13 – 0.32 1.68 1.57 – – 3.35 3.24

HSTL (I) 8 High 20 50 0.49 2.37 0.03 1.59 – 0.32 2.42 2.35 – – 4.09 4.02

HSTL (II) 15 High 20 25 0.49 2.26 0.03 1.59 – 0.32 2.30 2.03 – – 3.97 3.70

SSTL2 (I) 15 High 30 50 0.49 1.59 0.03 1.00 – 0.32 1.62 1.38 – – 3.29 3.05

SSTL2 (II) 18 High 30 25 0.49 1.62 0.03 1.00 – 0.32 1.65 1.32 – – 3.32 2.99

SSTL3 (I) 14 High 30 50 0.49 1.72 0.03 0.93 – 0.32 1.75 1.37 – – 3.42 3.04

SSTL3 (II) 21 High 30 25 0.49 1.54 0.03 0.93 – 0.32 1.57 1.25 – – 3.24 2.92

LVDS/BLVDS/

M-LVDS

24 High – – 0.49 1.40 0.03 1.36 – – – – – – – –

LVPECL 24 High – – 0.49 1.36 0.03 1.22 – – – – – – – –

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 3-10 on page 3-35 for connectivity.

This resistor is not required during normal operation.

ProASIC3E Flash Family FPGAs

v2.0 3-19

Detailed I/O DC Characteristics

Table 3-18 • Input Capacitance

Symbol Definition Conditions Min. Max. Units

CIN Input capacitance VIN = 0, f = 1.0 MHz 8 pF

CINCLK Input capacitance on the clock pin VIN = 0, f = 1.0 MHz 8 pF

Table 3-19 • I/O Output Buffer Maximum Resistances1

Standard Drive Strength RPULL-DOWN (Ω)2RPULL-UP (Ω)3

3.3 V LVTTL / 3.3 V LVCMOS 4 mA 100 300

8 mA 50 150

12 mA 25 75

16 mA 17 50

24 mA 11 33

2.5 V LVCMOS 4 mA 100 200

8 mA 50 100

12 mA 25 50

16 mA 20 40

24 mA 11 22

1.8 V LVCMOS 2 mA 200 225

4 mA 100 112

6 mA 50 56

8 mA 50 56

12 mA 20 22

16 mA 20 22

1.5 V LVCMOS 2 mA 200 224

4 mA 100 112

6 mA 67 75

8 mA 33 37

12 mA 33 37

3.3 V PCI/PCI-X Per PCI/PCI-X specification 25 75

3.3 V GTL 25 mA 11 –

2.5 V GTL 25 mA 14 –

3.3 V GTL+ 35 mA 12 –

2.5 V GTL+ 33 mA 15 –

HSTL (I) 8 mA 50 50

HSTL (II) 15 mA 25 25

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive

strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the

corresponding IBIS models located on the Actel website at http://www.actel.com/techdocs/models/ibis.html.

2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec

3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

ProASIC3E Flash Family FPGAs

3-20 v2.0

SSTL2 (I) 15 mA 27 31

SSTL2 (II) 18 mA 13 15

SSTL3 (I) 14 mA 44 69

SSTL3 (II) 21 mA 18 32

Table 3-20 • I/O Weak Pull-Up/Pull-Down Resistances

Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values

VCCI

R((WEAK PULL-UP)1

(Ω)

R(WEAK PULL-DOWN)2

(Ω)

Min. Max. Min. Max.

3.3 V 10 k 45 k 10 k 45 k

2.5 V 11 k 55 k 12 k 74 k

1.8 V 18 k 70 k 17 k 110 k

1.5 V 19 k 90 k 19 k 140 k

Notes:

1. R(WEAK PULL-DOWN-MAX) = (VOLspec) / IWEAK PULL-DOWN-MIN

2. R(WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / IWEAK PULL-UP-MIN

Table 3-19 • I/O Output Buffer Maximum Resistances1 (Continued)

Standard Drive Strength RPULL-DOWN (Ω)2RPULL-UP (Ω)3

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive

strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the

corresponding IBIS models located on the Actel website at http://www.actel.com/techdocs/models/ibis.html.

2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec

3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

ProASIC3E Flash Family FPGAs

v2.0 3-21

Table 3-21 • I/O Short Currents IOSH/IOSL

Drive Strength IOSH (mA)* IOSL (mA)*

3.3 V LVTTL / 3.3 V LVCMOS 4 mA 25 27

8 mA 51 54

12 mA 103 109

16 mA 132 127

24 mA 268 181

2.5 V LVCMOS 4 mA 16 18

8 mA 32 37

12 mA 65 74

16 mA 83 87

24 mA 169 124

1.8 V LVCMOS 2 mA 9 11

4 mA 17 22

6 mA 35 44

8 mA 45 51

12 mA 91 74

16 mA 91 74

1.5 V LVCMOS 2 mA 13 16

4 mA 25 33

6 mA 32 39

8 mA 66 55

12 mA 66 55

Note: *TJ = 100°C

ProASIC3E Flash Family FPGAs

3-22 v2.0

The length of time an I/O can withstand IOSH/IOSL events

depends on the junction temperature. The reliability

data below is based on a 3.3 V, 36 mA I/O setting, which

is the worst case for this type of analysis.

For example, at 110°C, the short current condition would

have to be sustained for more than three months to

cause a reliability concern. The I/O design does not

contain any short circuit protection, but such protection

would only be needed in extremely prolonged stress

conditions.

Table 3-22 • Short Current Event Duration before Failure

Temperature Time before Failure

–40°C > 20 years

0°C > 20 years

25°C > 20 years

70°C 5 years

85°C 2 years

100°C 6 months

110°C 3 months

Table 3-23 • Schmitt Trigger Input Hysteresis

Hysteresis Voltage Value (Typ) for Schmitt Mode Input Buffers

Input Buffer Configuration Hysteresis Value (typ.)

3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode) 240 mV

2.5 V LVCMOS (Schmitt trigger mode) 140 mV

1.8 V LVCMOS (Schmitt trigger mode) 80 mV

1.5 V LVCMOS (Schmitt trigger mode) 60 mV

Table 3-24 • I/O Input Rise Time, Fall Time, and Related I/O Reliability1

Input Buffer Input Rise/Fall Time (min.) Input Rise/Fall Time (max.) Reliability

LVTTL/LVCMOS (Schmitt trigger disabled) No requirement 10 ns * 20 years (110°C)

LVTTL/LVCMOS (Schmitt trigger enabled) No requirement No requirement, but input noise voltage

cannot exceed Schmitt hysteresis.

20 years (110°C)

HSTL/SSTL/GTL No requirement 10 ns * 10 years (100°C)

LVDS/BLVDS/M-LVDS/LVPECL No requirement 10 ns * 10 years (100°C)

Note: *The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the rise time

and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the

input signal is to the board noise. Actel recommends signal integrity evaluation/characterization of the system to ensure that there is

no excessive noise coupling into input signals.

ProASIC3E Flash Family FPGAs

v2.0 3-23

Single-Ended I/O Characteristics

3.3 V LVTTL / 3.3 V LVCMOS

Low-Voltage Transistor–Transistor Logic is a general purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL

input buffer and push-pull output buffer. The 3.3 V LVCMOS standard is supported as part of the 3.3 V LVTTL

support.

Table 3-25 • Minimum and Maximum DC Input and Output Levels

3.3 V LVTTL /

3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1μA2μA2

4 mA –0.3 0.8 2 3.6 0.4 2.4 4 4 27 25 10 10

8 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 10 10

12 mA –0.3 0.8 23.6 0.4 2.4 12 12 109 103 10 10

16 mA –0.3 0.8 2 3.6 0.4 2.4 16 16 127 132 10 10

24 mA –0.3 0.8 2 3.6 0.4 2.4 24 24 181 268 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Figure 3-6 • AC Loading

Table 3-26 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) VREF (typ.) (V) CLOAD (pF)

03.31.4–35

Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

ProASIC3E Flash Family FPGAs

3-24 v2.0

Timing Characteristics

Table 3-27 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA –F 0.79 9.47 0.05 1.44 1.88 0.51 9.64 8.05 3.23 3.11 12.33 10.74 ns

Std. 0.66 7.88 0.04 1.20 1.57 0.43 8.03 6.70 2.69 2.59 10.26 8.94 ns

–1 0.56 6.71 0.04 1.02 1.33 0.36 6.83 5.70 2.29 2.20 8.73 7.60 ns

–2 0.49 5.89 0.03 0.90 1.17 0.32 6.00 5.01 2.01 1.93 7.67 6.67 ns

8 mA –F 0.79 6.10 0.05 1.44 1.88 0.51 6.21 4.98 3.66 3.86 8.90 7.66 ns

Std. 0.66 5.08 0.04 1.20 1.57 0.43 5.17 4.14 3.05 3.21 7.41 6.38 ns

–1 0.56 4.32 0.04 1.02 1.33 0.36 4.40 3.52 2.59 2.73 6.30 5.43 ns

–2 0.49 3.79 0.03 0.90 1.17 0.32 3.86 3.09 2.28 2.40 5.53 4.76 ns

12 mA –F 0.79 4.41 0.05 1.44 1.88 0.51 4.49 3.45 3.93 4.34 7.17 6.13 ns

Std. 0.66 3.67 0.04 1.20 1.57 0.43 3.74 2.87 3.28 3.61 5.97 5.11 ns

–1 0.56 3.12 0.04 1.02 1.33 0.36 3.18 2.44 2.79 3.07 5.08 4.34 ns

–2 0.49 2.74 0.03 0.90 1.17 0.32 2.79 2.14 2.45 2.70 4.46 3.81 ns

16 mA –F 0.79 4.16 0.05 1.44 1.88 0.51 4.24 3.13 4.00 4.47 6.92 5.82 ns

Std. 0.66 3.46 0.04 1.20 1.57 0.43 3.53 2.61 3.33 3.72 5.76 4.84 ns

–1 0.56 2.95 0.04 1.02 1.33 0.36 3.00 2.22 2.83 3.17 4.90 4.12 ns

–2 0.49 2.59 0.03 0.90 1.17 0.32 2.63 1.95 2.49 2.78 4.30 3.62 ns

24 mA –F 0.79 3.85 0.05 1.44 1.88 0.51 3.92 2.59 4.07 4.96 6.61 5.28 ns

Std. 0.66 3.21 0.04 1.20 1.57 0.43 3.27 2.16 3.39 4.13 5.50 4.39 ns

–1 0.56 2.73 0.04 1.02 1.33 0.36 2.78 1.83 2.88 3.51 4.68 3.74 ns

–2 0.49 2.39 0.03 0.90 1.17 0.32 2.44 1.61 2.53 3.08 4.11 3.28 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

ProASIC3E Flash Family FPGAs

v2.0 3-25

Table 3-28 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA –F 0.79 13.22 0.05 1.44 1.88 0.51 13.47 10.87 3.23 2.93 16.16 13.56 ns

Std. 0.66 11.01 0.04 1.20 1.57 0.43 11.21 9.05 2.69 2.44 13.45 11.29 ns

–1 0.56 9.36 0.04 1.02 1.33 0.36 9.54 7.70 2.29 2.08 11.44 9.60 ns

–2 0.49 8.22 0.03 0.90 1.17 0.32 8.37 6.76 2.01 1.82 10.04 8.43 ns

8 mA –F 0.79 9.45 0.05 1.44 1.88 0.51 9.62 7.74 3.65 3.68 12.31 10.42 ns

Std. 0.66 7.86 0.04 1.20 1.57 0.43 8.01 6.44 3.04 3.06 10.24 8.68 ns

–1 0.56 6.69 0.04 1.02 1.33 0.36 6.81 5.48 2.58 2.61 8.71 7.38 ns

–2 0.49 5.87 0.03 0.90 1.17 0.32 5.98 4.81 2.27 2.29 7.65 6.48 ns

12 mA –F 0.79 7.24 0.05 1.44 1.88 0.51 7.37 6.03 3.93 4.17 10.06 8.72 ns

Std. 0.66 6.03 0.04 1.20 1.57 0.43 6.14 5.02 3.28 3.47 8.37 7.26 ns

–1 0.56 5.13 0.04 1.02 1.33 0.36 5.22 4.27 2.79 2.95 7.12 6.17 ns

–2 0.49 4.50 0.03 0.90 1.17 0.32 4.58 3.75 2.45 2.59 6.25 5.42 ns

16 mA –F 0.79 6.75 0.05 1.44 1.88 0.51 6.87 5.68 3.99 4.30 9.56 8.36 ns

Std. 0.66 5.62 0.04 1.20 1.57 0.43 5.72 4.72 3.32 3.58 7.96 6.96 ns

–1 0.56 4.78 0.04 1.02 1.33 0.36 4.87 4.02 2.83 3.04 6.77 5.92 ns

–2 0.49 4.20 0.03 0.90 1.17 0.32 4.27 3.53 2.48 2.67 5.94 5.20 ns

24 mA –F 0.79 6.30 0.05 1.44 1.88 0.51 6.42 5.64 4.07 4.76 9.10 8.32 ns

Std. 0.66 5.24 0.04 1.20 1.57 0.43 5.34 4.69 3.39 3.96 7.58 6.93 ns

–1 0.56 4.46 0.04 1.02 1.33 0.36 4.54 3.99 2.88 3.37 6.44 5.89 ns

–2 0.49 3.92 0.03 0.90 1.17 0.32 3.99 3.50 2.53 2.96 5.66 5.17 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

ProASIC3E Flash Family FPGAs

3-26 v2.0

2.5 V LVCMOS

Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-purpose 2.5 V

applications. It uses a 5 V–tolerant input buffer and push-pull output buffer.

Table 3-29 • Minimum and Maximum DC Input and Output Levels

2.5 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA

Max.,

mA1Max.,

mA1μA2μA2

4 mA –0.3 0.7 1.7 3.6 0.7 1.7 4 4 18 16 10 10

8 mA –0.3 0.7 1.7 3.6 0.7 1.7 8 8 37 32 10 10

12 mA –0.3 0.7 1.7 3.6 0.7 1.7 12 12 74 65 10 10

16 mA –0.3 0.7 1.7 3.6 0.7 1.7 16 16 87 83 10 10

24 mA –0.3 0.7 1.7 3.6 0.7 1.7 24 24 124 169 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Figure 3-7 • AC Loading

Table 3-30 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) VREF (typ.) (V) CLOAD (pF)

02.51.2–35

Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

ProASIC3E Flash Family FPGAs

v2.0 3-27

Timing Characteristics

Table 3-31 • 2.5 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA –F 0.79 10.59 0.05 1.82 1.99 0.51 9.77 10.59 3.26 2.75 12.45 13.28 ns

Std. 0.66 8.82 0.04 1.51 1.66 0.43 8.13 8.82 2.72 2.29 10.37 11.05 ns

–1 0.56 7.50 0.04 1.29 1.41 0.36 6.92 7.50 2.31 1.95 8.82 9.40 ns

–2 0.49 6.58 0.03 1.13 1.24 0.32 6.07 6.58 2.03 1.71 7.74 8.25 ns

8 mA –F 0.79 6.33 0.05 1.82 1.99 0.51 6.33 6.33 3.73 3.64 9.02 9.02 ns

Std. 0.66 5.27 0.04 1.51 1.66 0.43 5.27 5.27 3.10 3.03 7.50 7.51 ns

–1 0.56 4.48 0.04 1.29 1.41 0.36 4.48 4.48 2.64 2.58 6.38 6.38 ns

–2 0.49 3.94 0.03 1.13 1.24 0.32 3.93 3.94 2.32 2.26 5.60 5.61 ns

12 mA –F 0.79 4.50 0.05 1.82 1.99 0.51 4.58 4.19 4.04 4.20 7.27 6.88 ns

Std. 0.66 3.74 0.04 1.51 1.66 0.43 3.81 3.49 3.37 3.49 6.05 5.73 ns

–1 0.56 3.18 0.04 1.29 1.41 0.36 3.24 2.97 2.86 2.97 5.15 4.87 ns

–2 0.49 2.80 0.03 1.13 1.24 0.32 2.85 2.61 2.51 2.61 4.52 4.28 ns

16 mA –F 0.79 4.24 0.05 1.82 1.99 0.51 4.32 3.75 4.11 4.35 7.00 6.43 ns

Std. 0.66 3.53 0.04 1.51 1.66 0.43 3.59 3.12 3.42 3.62 5.83 5.35 ns

–1 0.56 3.00 0.04 1.29 1.41 0.36 3.06 2.65 2.91 3.08 4.96 4.55 ns

–2 0.49 2.63 0.03 1.13 1.24 0.32 2.68 2.33 2.56 2.71 4.35 4.00 ns

24 mA –F 0.79 3.92 0.05 1.82 1.99 0.51 3.99 2.98 4.20 4.93 6.68 5.67 ns

Std. 0.66 3.26 0.04 1.51 1.66 0.43 3.32 2.48 3.49 4.11 5.56 4.72 ns

–1 0.56 2.77 0.04 1.29 1.41 0.36 2.83 2.11 2.97 3.49 4.73 4.01 ns

–2 0.49 2.44 0.03 1.13 1.24 0.32 2.48 1.85 2.61 3.07 4.15 3.52 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

ProASIC3E Flash Family FPGAs

3-28 v2.0

Table 3-32 • 2.5 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA –F 0.79 14.42 0.05 1.82 1.99 0.51 14.69 13.95 3.26 2.64 17.37 16.63 ns

Std. 0.66 12.00 0.04 1.51 1.66 0.43 12.23 11.61 2.72 2.20 14.46 13.85 ns

–1 0.56 10.21 0.04 1.29 1.41 0.36 10.40 9.88 2.31 1.87 12.30 11.78 ns

–2 0.49 8.96 0.03 1.13 1.24 0.32 9.13 8.67 2.03 1.64 10.80 10.34 ns

8 mA –F 0.79 10.49 0.05 1.82 1.99 0.51 10.68 9.62 3.73 3.52 13.37 12.31 ns

Std. 0.66 8.73 0.04 1.51 1.66 0.43 8.89 8.01 3.10 2.93 11.13 10.25 ns

–1 0.56 7.43 0.04 1.29 1.41 0.36 7.57 6.82 2.64 2.49 9.47 8.72 ns

–2 0.49 6.52 0.03 1.13 1.24 0.32 6.64 5.98 2.32 2.19 8.31 7.65 ns

12 mA –F 0.79 8.14 0.05 1.82 1.99 0.51 8.29 7.34 4.04 4.08 10.97 10.02 ns

Std. 0.66 6.77 0.04 1.51 1.66 0.43 6.90 6.11 3.37 3.39 9.14 8.34 ns

–1 0.56 5.76 0.04 1.29 1.41 0.36 5.87 5.20 2.86 2.89 7.77 7.10 ns

–2 0.49 5.06 0.03 1.13 1.24 0.32 5.15 4.56 2.51 2.53 6.82 6.23 ns

16 mA –F 0.79 7.58 0.05 1.82 1.99 0.51 7.72 6.88 4.11 4.23 10.40 9.57 ns

Std. 0.66 6.31 0.04 1.51 1.66 0.43 6.42 5.73 3.42 3.52 8.66 7.96 ns

–1 0.56 5.37 0.04 1.29 1.41 0.36 5.46 4.87 2.91 3.00 7.37 6.77 ns

–2 0.49 4.71 0.03 1.13 1.24 0.32 4.80 4.28 2.56 2.63 6.47 5.95 ns

24 mA –F 0.79 7.13 0.05 1.82 1.99 0.51 7.26 6.85 4.20 4.80 9.94 9.54 ns

Std. 0.66 5.93 0.04 1.51 1.66 0.43 6.04 5.70 3.49 4.00 8.28 7.94 ns

–1 0.56 5.05 0.04 1.29 1.41 0.36 5.14 4.85 2.97 3.40 7.04 6.75 ns

–2 0.49 4.43 0.03 1.13 1.24 0.32 4.51 4.26 2.61 2.99 6.18 5.93 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

ProASIC3E Flash Family FPGAs

v2.0 3-29

1.8 V LVCMOS

Low-Voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-purpose 1.8 V

applications. It uses a 1.8 V input buffer and a push-pull output buffer.

Table 3-33 • Minimum and Maximum DC Input and Output Levels

1.8 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA

Max.,

mA1Max.,

mA1μA2μA2

2 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 2 2 11 9 10 10

4 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 4 4 22 17 10 10

6 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 6 6 44 35 10 10

8 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 8 8 51 45 10 10

12 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 12 12 74 91 10 10

16 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 16 16 74 91 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Figure 3-8 • AC Loading

Table 3-34 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) VREF (typ.) (V) CLOAD (pF)

0 1.8 0.9 – 35

Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

ProASIC3E Flash Family FPGAs

3-30 v2.0

Timing Characteristics

Table 3-35 • 1.8 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA –F 0.79 14.54 0.05 1.74 2.29 0.51 11.52 14.54 3.34 1.97 14.21 17.23 ns

Std. 0.66 12.10 0.04 1.45 1.91 0.43 9.59 12.10 2.78 1.64 11.83 14.34 ns

–1 0.56 10.30 0.04 1.23 1.62 0.36 8.16 10.30 2.37 1.39 10.06 12.20 ns

–2 0.49 9.04 0.03 1.08 1.42 0.32 7.16 9.04 2.08 1.22 8.83 10.71 ns

4 mA –F 0.79 8.47 0.05 1.74 2.29 0.51 7.45 8.47 3.90 3.44 10.14 11.16 ns

Std. 0.66 7.05 0.04 1.45 1.91 0.43 6.20 7.05 3.25 2.86 8.44 9.29 ns

–1 0.56 6.00 0.04 1.23 1.62 0.36 5.28 6.00 2.76 2.44 7.18 7.90 ns

–2 0.49 5.27 0.03 1.08 1.42 0.32 4.63 5.27 2.43 2.14 6.30 6.94 ns

6 mA –F 0.79 5.43 0.05 1.74 2.29 0.51 5.36 5.43 4.29 4.17 8.05 8.12 ns

Std. 0.66 4.52 0.04 1.45 1.91 0.43 4.47 4.52 3.57 3.47 6.70 6.76 ns

–1 0.56 3.85 0.04 1.23 1.62 0.36 3.80 3.85 3.04 2.95 5.70 5.75 ns

–2 0.49 3.38 0.03 1.08 1.42 0.32 3.33 3.38 2.66 2.59 5.00 5.05 ns

8 mA –F 0.79 4.95 0.05 1.74 2.29 0.51 5.04 4.80 4.36 4.35 7.73 7.48 ns

Std. 0.66 4.12 0.04 1.45 1.91 0.43 4.20 3.99 3.63 3.62 6.43 6.23 ns

–1 0.56 3.51 0.04 1.23 1.62 0.36 3.57 3.40 3.09 3.08 5.47 5.30 ns

–2 0.49 3.08 0.03 1.08 1.42 0.32 3.14 2.98 2.71 2.71 4.81 4.65 ns

12 mA –F 0.79 4.56 0.05 1.74 2.29 0.51 4.64 3.71 4.48 5.09 7.33 6.40 ns

Std. 0.66 3.80 0.04 1.45 1.91 0.43 3.87 3.09 3.73 4.24 6.10 5.32 ns

–1 0.56 3.23 0.04 1.23 1.62 0.36 3.29 2.63 3.18 3.60 5.19 4.53 ns

–2 0.49 2.83 0.03 1.08 1.42 0.32 2.89 2.31 2.79 3.16 4.56 3.98 ns

16 mA –F 0.79 4.56 0.05 1.74 2.29 0.51 4.64 3.71 4.48 5.09 7.33 6.40 ns

Std. 0.66 3.80 0.04 1.45 1.91 0.43 3.87 3.09 3.73 4.24 6.10 5.32 ns

–1 0.56 3.23 0.04 1.23 1.62 0.36 3.29 2.63 3.18 3.60 5.19 4.53 ns

–2 0.49 2.83 0.03 1.08 1.42 0.32 2.89 2.31 2.79 3.16 4.56 3.98 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

ProASIC3E Flash Family FPGAs

v2.0 3-31

Table 3-36 • 1.8 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA –F 0.79 19.03 0.05 1.74 2.29 0.51 18.80 19.03 3.34 1.90 21.49 21.71 ns

Std. 0.66 15.84 0.04 1.45 1.91 0.43 15.65 15.84 2.78 1.58 17.89 18.07 ns

–1 0.56 13.47 0.04 1.23 1.62 0.36 13.31 13.47 2.37 1.35 15.22 15.37 ns

–2 0.49 11.83 0.03 1.08 1.42 0.32 11.69 11.83 2.08 1.18 13.36 13.50 ns

4 mA –F 0.79 13.68 0.05 1.74 2.29 0.51 13.94 12.92 3.91 3.33 16.62 15.61 ns

Std. 0.66 11.39 0.04 1.45 1.91 0.43 11.60 10.76 3.26 2.77 13.84 12.99 ns

–1 0.56 9.69 0.04 1.23 1.62 0.36 9.87 9.15 2.77 2.36 11.77 11.05 ns

–2 0.49 8.51 0.03 1.08 1.42 0.32 8.66 8.03 2.43 2.07 10.33 9.70 ns

6 mA –F 0.79 10.78 0.05 1.74 2.29 0.51 10.98 9.73 4.29 4.03 13.66 12.41 ns

Std. 0.66 8.97 0.04 1.45 1.91 0.43 9.14 8.10 3.57 3.36 11.37 10.33 ns

–1 0.56 7.63 0.04 1.23 1.62 0.36 7.77 6.89 3.04 2.86 9.67 8.79 ns

–2 0.49 6.70 0.03 1.08 1.42 0.32 6.82 6.05 2.66 2.51 8.49 7.72 ns

8 mA –F 0.79 10.03 0.05 1.74 2.29 0.51 10.22 9.11 4.37 4.23 12.90 11.80 ns

Std. 0.66 8.35 0.04 1.45 1.91 0.43 8.50 7.59 3.64 3.52 10.74 9.82 ns

–1 0.56 7.10 0.04 1.23 1.62 0.36 7.23 6.45 3.10 3.00 9.14 8.35 ns

–2 0.49 6.24 0.03 1.08 1.42 0.32 6.35 5.66 2.72 2.63 8.02 7.33 ns

12 mA –F 0.79 9.54 0.05 1.74 2.29 0.51 9.72 9.08 4.50 4.93 12.40 11.77 ns

Std. 0.66 7.94 0.04 1.45 1.91 0.43 8.09 7.56 3.74 4.11 10.32 9.80 ns

–1 0.56 6.75 0.04 1.23 1.62 0.36 6.88 6.43 3.18 3.49 8.78 8.33 ns

–2 0.49 5.93 0.03 1.08 1.42 0.32 6.04 5.65 2.79 3.07 7.71 7.32 ns

16 mA –F 0.79 9.54 0.05 1.74 2.29 0.51 9.72 9.08 4.50 4.93 12.40 11.77 ns

Std. 0.66 7.94 0.04 1.45 1.91 0.43 8.09 7.56 3.74 4.11 10.32 9.80 ns

–1 0.56 6.75 0.04 1.23 1.62 0.36 6.88 6.43 3.18 3.49 8.78 8.33 ns

–2 0.49 5.93 0.03 1.08 1.42 0.32 6.04 5.65 2.79 3.07 7.71 7.32 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

ProASIC3E Flash Family FPGAs

3-32 v2.0

1.5 V LVCMOS (JESD8-11)

Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-purpose 1.5 V

applications. It uses a 1.5 V input buffer and a push-pull output buffer.

Table 3-37 • Minimum and Maximum DC Input and Output Levels

1.5 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA

Max.,

mA1Max.,

mA1μA2μA2

2 mA –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 2 2 16 13 10 10

4 mA –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 4 4 33 25 10 10

6 mA –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 6 6 39 32 10 10

8 mA –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 8 8 55 66 10 10

12 mA –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 12 12 55 66 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Figure 3-9 • AC Loading

Table 3-38 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) VREF (typ.) (V) CLOAD (pF)

0 1.5 0.75 – 35

Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

ProASIC3E Flash Family FPGAs

v2.0 3-33

Timing Characteristics

Table 3-39 • 1.5 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA –F 0.79 10.25 0.05 2.04 2.58 0.51 8.72 10.25 4.08 3.35 11.41 12.94 ns

Std. 0.66 8.53 0.04 1.70 2.14 0.43 7.26 8.53 3.39 2.79 9.50 10.77 ns

–1 0.56 7.26 0.04 1.44 1.82 0.36 6.18 7.26 2.89 2.37 8.08 9.16 ns

–2 0.49 6.37 0.03 1.27 1.60 0.32 5.42 6.37 2.53 2.08 7.09 8.04 ns

4 mA –F 0.79 6.50 0.05 2.04 2.58 0.51 6.27 6.50 4.51 4.18 8.95 9.19 ns

Std. 0.66 5.41 0.04 1.70 2.14 0.43 5.22 5.41 3.75 3.48 7.45 7.65 ns

–1 0.56 4.60 0.04 1.44 1.82 0.36 4.44 4.60 3.19 2.96 6.34 6.50 ns

–2 0.49 4.04 0.03 1.27 1.60 0.32 3.89 4.04 2.80 2.60 5.56 5.71 ns

6 mA –F 0.79 5.77 0.05 2.04 2.58 0.51 5.88 5.70 4.60 4.41 8.56 8.39 ns

Std. 0.66 4.80 0.04 1.70 2.14 0.43 4.89 4.75 3.83 3.67 7.13 6.98 ns

–1 0.56 4.09 0.04 1.44 1.82 0.36 4.16 4.04 3.26 3.12 6.06 5.94 ns

–2 0.49 3.59 0.03 1.27 1.60 0.32 3.65 3.54 2.86 2.74 5.32 5.21 ns

8 mA –F 0.79 5.31 0.05 2.04 2.58 0.51 5.41 4.35 4.76 5.25 8.09 7.04 ns

Std. 0.66 4.42 0.04 1.70 2.14 0.43 4.50 3.62 3.96 4.37 6.74 5.86 ns

–1 0.56 3.76 0.04 1.44 1.82 0.36 3.83 3.08 3.37 3.72 5.73 4.98 ns

–2 0.49 3.30 0.03 1.27 1.60 0.32 3.36 2.70 2.96 3.27 5.03 4.37 ns

12 mA –F 0.79 5.31 0.05 2.04 2.58 0.51 5.41 4.35 4.76 5.25 8.09 7.04 ns

Std. 0.66 4.42 0.04 1.70 2.14 0.43 4.50 3.62 3.96 4.37 6.74 5.86 ns

–1 0.56 3.76 0.04 1.44 1.82 0.36 3.83 3.08 3.37 3.72 5.73 4.98 ns

–2 0.49 3.30 0.03 1.27 1.60 0.32 3.36 2.70 2.96 3.27 5.03 4.37 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

ProASIC3E Flash Family FPGAs

3-34 v2.0

Table 3-40 • 1.5 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Drive Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA –F 0.79 16.95 0.05 2.04 2.58 0.51 17.26 15.78 4.09 3.22 19.95 18.47 ns

Std. 0.66 14.11 0.04 1.70 2.14 0.43 14.37 13.14 3.40 2.68 16.61 15.37 ns

–1 0.56 12.00 0.04 1.44 1.82 0.36 12.22 11.17 2.90 2.28 14.13 13.08 ns

–2 0.49 10.54 0.03 1.27 1.60 0.32 10.73 9.81 2.54 2.00 12.40 11.48 ns

4 mA –F 0.79 13.49 0.05 2.04 2.58 0.51 13.74 11.85 4.53 4.03 16.43 14.54 ns

Std. 0.66 11.23 0.04 1.70 2.14 0.43 11.44 9.87 3.77 3.36 13.68 12.10 ns

–1 0.56 9.55 0.04 1.44 1.82 0.36 9.73 8.39 3.21 2.86 11.63 10.29 ns

–2 0.49 8.39 0.03 1.27 1.60 0.32 8.54 7.37 2.81 2.51 10.21 9.04 ns

6 mA –F 0.79 12.56 0.05 2.04 2.58 0.51 12.79 11.10 4.62 4.26 15.48 13.79 ns

Std. 0.66 10.45 0.04 1.70 2.14 0.43 10.65 9.24 3.84 3.55 12.88 11.48 ns

–1 0.56 8.89 0.04 1.44 1.82 0.36 9.06 7.86 3.27 3.02 10.96 9.76 ns

–2 0.49 7.81 0.03 1.27 1.60 0.32 7.95 6.90 2.87 2.65 9.62 8.57 ns

8 mA –F 0.79 12.04 0.05 2.04 2.58 0.51 12.26 11.09 4.77 5.07 14.94 13.77 ns

Std. 0.66 10.02 0.04 1.70 2.14 0.43 10.20 9.23 3.97 4.22 12.44 11.47 ns

–1 0.56 8.52 0.04 1.44 1.82 0.36 8.68 7.85 3.38 3.59 10.58 9.75 ns

–2 0.49 7.48 0.03 1.27 1.60 0.32 7.62 6.89 2.97 3.15 9.29 8.56 ns

12 mA –F 0.79 12.04 0.05 2.04 2.58 0.51 12.26 11.09 4.77 5.07 14.94 13.77 ns

Std. 0.66 10.02 0.04 1.70 2.14 0.43 10.20 9.23 3.97 4.22 12.44 11.47 ns

–1 0.56 8.52 0.04 1.44 1.82 0.36 8.68 7.85 3.38 3.59 10.58 9.75 ns

–2 0.49 7.48 0.03 1.27 1.60 0.32 7.62 6.89 2.97 3.15 9.29 8.56 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

ProASIC3E Flash Family FPGAs

v2.0 3-35

3.3 V PCI, 3.3 V PCI-X

Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus applications.

AC loadings are defined per the PCI/PCI-X specifications for the datapath; Actel loadings for enable path

characterization are described in Figure 3-10.

AC loadings are defined per PCI/PCI-X specifications for the datapath; Actel loading for tristate is described in Table 3-42.

Timing Characteristics

Table 3-41 • Minimum and Maximum DC Input and Output Levels

3.3 V PCI/PCI-X VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

Per PCI specification Per PCI curves 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

Figure 3-10 • AC Loading

Table 3-42 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) VREF (typ.) (V) CLOAD (pF)

0 3.3 0.285 * VCCI for tDP(R)

0.615 * VCCI for tDP(F)

–10

Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.

Table 3-43 • 3.3 V PCI/PCI-X

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

–F 0.79 3.37 0.05 1.26 2.01 0.51 3.43 2.40 3.93 4.34 6.12 5.08 ns

Std. 0.66 2.81 0.04 1.05 1.67 0.43 2.86 2.00 3.28 3.61 5.09 4.23 ns

–1 0.56 2.39 0.04 0.89 1.42 0.36 2.43 1.70 2.79 3.07 4.33 3.60 ns

–2 0.49 2.09 0.03 0.78 1.25 0.32 2.13 1.49 2.45 2.70 3.80 3.16 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

Test Point

Enable Path

R to V for t /t /t

CCI LZ ZL ZLS

10 pF for t /t /t /t

ZH ZHS ZLSZL

5 pF for tHZ /tLZ

R to GND for t /t /t

HZ ZH ZH

R = 1 k

Test Point

Datapath

R = 25 R to VCCI for tDP (F)

R to GND for tDP (R)

ProASIC3E Flash Family FPGAs

3-36 v2.0

Voltage-Referenced I/O Characteristics

3.3 V GTL

Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and

an open-drain output buffer. The VCCI pin should be connected to 3.3 V.

Timing Characteristics

Table 3-44 • Minimum and Maximum DC Input and Output Levels

3.3 V GTL VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA

Max.,

mA1Max.,

mA1µA2µA2

25 mA3–0.3 VREF – 0.05 VREF + 0.05 3.6 0.4 – 25 25 181 268 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Output drive strength is below JEDEC specification.

Figure 3-11 • AC Loading

Table 3-45 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)

VREF – 0.05 VREF + 0.05 0.8 0.8 1.2 10

Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.

Table 3-46 • 3.3 V GTL

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V VREF = 0.8 V

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

–F 0.72 2.49 0.05 3.52 0.51 2.45 2.49 5.13 5.18 ns

Std. 0.60 2.08 0.04 2.93 0.43 2.04 2.08 4.27 4.31 ns

–1 0.51 1.77 0.04 2.50 0.36 1.73 1.77 3.63 3.67 ns

–2 0.45 1.55 0.03 2.19 0.32 1.52 1.55 3.19 3.22 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

Test Point

10 pF

GTL

VTT

ProASIC3E Flash Family FPGAs

v2.0 3-37

2.5 V GTL

Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and

an open-drain output buffer. The VCCI pin should be connected to 2.5 V

Timing Characteristics

Table 3-47 • Minimum and Maximum DC Input and Output Levels

2.5 GTL VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA

Max.,

mA1Max.,

mA1μA2μA2

25 mA3–0.3 VREF – 0.05 VREF + 0.05 3.6 0.4 – 25 25 124 169 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Output drive strength is below JEDEC specification.

Figure 3-12 • AC Loading

Table 3-48 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)

VREF – 0.05 VREF + 0.05 0.8 0.8 1.2 10

Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.

Table 3-49 • 2.5 V GTL

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V VREF = 0.8 V

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

–F 0.72 2.56 0.05 2.95 0.51 2.60 2.56 5.28 5.24 ns

Std. 0.60 2.13 0.04 2.46 0.43 2.16 2.13 4.40 4.36 ns

–1 0.51 1.81 0.04 2.09 0.36 1.84 1.81 3.74 3.71 ns

–2 0.45 1.59 0.03 1.83 0.32 1.61 1.59 3.28 3.26 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

Test Point

10 pF

GTL

VTT

ProASIC3E Flash Family FPGAs

3-38 v2.0

3.3 V GTL+

Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer

and an open-drain output buffer. The VCCI pin should be connected to 3.3 V

Timing Characteristics

Table 3-50 • Minimum and Maximum DC Input and Output Levels

3.3 V GTL+ VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

35 mA –0.3 VREF – 0.1 VREF + 0.1 3.6 0.6 – 35 35 181 268 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

Figure 3-13 • AC Loading

Table 3-51 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)

VREF – 0.1 VREF + 0.1 1.0 1.0 1.5 10

Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.

Table 3-52 • 3.3 V GTL+

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 1.0 V

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

–F 0.72 2.47 0.05 1.91 0.51 2.51 2.47 5.20 5.15 ns

Std. 0.60 2.06 0.04 1.59 0.43 2.09 2.06 4.33 4.29 ns

–1 0.51 1.75 0.04 1.35 0.36 1.78 1.75 3.68 3.65 ns

–2 0.45 1.53 0.03 1.19 0.32 1.56 1.53 3.23 3.20 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

Test Point

10 pF

GTL+

VTT

ProASIC3E Flash Family FPGAs

v2.0 3-39

2.5 V GTL+

Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer

and an open-drain output buffer. The VCCI pin should be connected to 2.5 V.

Timing Characteristics

Table 3-53 • Minimum and Maximum DC Input and Output Levels

2.5 V GTL+ VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1μA2μA2

33 mA –0.3 VREF – 0.1 VREF + 0.1 3.6 0.6 – 33 33 124 169 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

Figure 3-14 • AC Loading

Table 3-54 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)

VREF – 0.1 VREF + 0.1 1.0 1.0 1.5 10

Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.

Test Point

10 pF

GTL+

VTT

Table 3-55 • 2.5 V GTL+

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V, VREF = 1.0 V

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

–F 0.72 2.65 0.05 1.82 0.51 2.70 2.52 5.38 5.21 ns

Std. 0.60 2.21 0.04 1.51 0.43 2.25 2.10 4.48 4.34 ns

–1 0.51 1.88 0.04 1.29 0.36 1.91 1.79 3.81 3.69 ns

–2 0.45 1.65 0.03 1.13 0.32 1.68 1.57 3.35 3.24 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

ProASIC3E Flash Family FPGAs

3-40 v2.0

HSTL Class I

High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). ProASIC3E devices

support Class I. This provides a differential amplifier input buffer and a push-pull output buffer.

Timing Characteristics

Table 3-56 • Minimum and Maximum DC Input and Output Levels

HSTL Class I VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

8 mA –0.3 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCI-0.4 8 8 39 32 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

Figure 3-15 • AC Loading

Table 3-57 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)

VREF – 0.1 VREF + 0.1 0.75 0.75 0.75 20

Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.

Table 3-58 • HSTL Class I

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V, VREF = 0.75 V

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

–F 0.79 3.82 0.05 2.55 0.51 3.89 3.78 6.58 6.46 ns

Std. 0.66 3.18 0.04 2.12 0.43 3.24 3.14 5.47 5.38 ns

–1 0.56 2.70 0.04 1.81 0.36 2.75 2.67 4.66 4.58 ns

–2 0.49 2.37 0.03 1.59 0.32 2.42 2.35 4.09 4.02 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

Test Point

20 pF

HSTL

Class I

VTT

ProASIC3E Flash Family FPGAs

v2.0 3-41

HSTL Class II

High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). ProASIC3E devices

support Class II. This provides a differential amplifier input buffer and a push-pull output buffer.

Timing Characteristics

Table 3-59 • Minimum and Maximum DC Input and Output Levels

HSTL Class II VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1μA2μA2

15 mA3–0.3 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCI-0.4 15 15 55 66 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Output drive strength is below JEDEC specification.

Figure 3-16 • AC Loading

Table 3-60 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)

VREF – 0.1 VREF + 0.1 0.75 0.75 0.75 20

Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.

Table 3-61 • HSTL Class II

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V, VREF = 0.75 V

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

–F 0.79 3.63 0.05 2.55 0.51 3.70 3.26 6.39 5.95 ns

Std. 0.66 3.02 0.04 2.12 0.43 3.08 2.71 5.32 4.95 ns

–1 0.56 2.57 0.04 1.81 0.36 2.62 2.31 4.52 4.21 ns

–2 0.49 2.26 0.03 1.59 0.32 2.30 2.03 3.97 3.70 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

Test Point

20 pF

HSTL

Class II

VTT

ProASIC3E Flash Family FPGAs

3-42 v2.0

SSTL2 Class I

Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support Class I. This provides

a differential amplifier input buffer and a push-pull output buffer.

Timing Characteristics

Table 3-62 • Minimum and Maximum DC Input and Output Levels

SSTL2 Class I VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1μA2μA2

15 mA –0.3 VREF – 0.2 VREF + 0.2 3.6 0.54 VCCI - 0.62 15 15 87 83 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

Figure 3-17 • AC Loading

Table 3-63 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)

VREF – 0.2 VREF + 0.2 1.25 1.25 1.25 30

Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.

Table 3-64 • SSTL 2 Class I

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V, VREF = 1.25 V

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

–F 0.79 2.56 0.05 1.60 0.51 2.60 2.22 5.29 4.90 ns

Std. 0.66 2.13 0.04 1.33 0.43 2.17 1.85 4.40 4.08 ns

–1 0.56 1.81 0.04 1.14 0.36 1.84 1.57 3.74 3.47 ns

–2 0.49 1.59 0.03 1.00 0.32 1.62 1.38 3.29 3.05 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

Test Point

30 pF

SSTL2

Class I

VTT

ProASIC3E Flash Family FPGAs

v2.0 3-43

SSTL2 Class II

Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support Class II. This

provides a differential amplifier input buffer and a push-pull output buffer.

Timing Characteristics

Table 3-65 • Minimum and Maximum DC Input and Output Levels

SSTL2 Class II VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

18 mA –0.3 VREF – 0.2 VREF + 0.2 3.6 0.35 VCCI – 0.43 18 18 124 169 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

Figure 3-18 • AC Loading

Table 3-66 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)

VREF – 0.2 VREF + 0.2 1.25 1.25 1.25 30

Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.

Table 3-67 • SSTL 2 Class II

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V, VREF = 1.25 V

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

–F 0.79 0.79 2.60 0.05 1.60 0.51 2.65 2.13 5.34 ns

Std. 0.66 0.66 2.17 0.04 1.33 0.43 2.21 1.77 4.44 ns

–1 0.56 0.56 1.84 0.04 1.14 0.36 1.88 1.51 3.78 ns

–2 0.49 0.49 1.62 0.03 1.00 0.32 1.65 1.32 3.32 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

Test Point

30 pF

SSTL2

Class II

VTT

ProASIC3E Flash Family FPGAs

3-44 v2.0

SSTL3 Class I

Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support Class I. This provides

a differential amplifier input buffer and a push-pull output buffer.

Timing Characteristics

Table 3-68 • Minimum and Maximum DC Input and Output Levels

SSTL3 Class I VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

14 mA –0.3 VREF – 0.2 VREF + 0.2 3.6 0.7 VCCI – 1.1 14 14 54 51 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

Figure 3-19 • AC Loading

Table 3-69 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)

VREF – 0.2 VREF + 0.2 1.5 1.5 1.485 30

Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.

Table 3-70 • SSTL3 Class I

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 1.5 V

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

–F 0.79 2.77 0.05 1.50 0.51 2.82 2.21 5.51 4.89 ns

Std. 0.66 2.31 0.04 1.25 0.43 2.35 1.84 4.59 4.07 ns

–1 0.56 1.96 0.04 1.06 0.36 2.00 1.56 3.90 3.46 ns

–2 0.49 1.72 0.03 0.93 0.32 1.75 1.37 3.42 3.04 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

Test Point

30 pF

SSTL3

Class I

VTT

ProASIC3E Flash Family FPGAs

v2.0 3-45

SSTL3 Class II

Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support Class II. This

provides a differential amplifier input buffer and a push-pull output buffer.

Timing Characteristics

Table 3-71 • Minimum and Maximum DC Input and Output Levels

SSTL3 Class II VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

21 mA –0.3 VREF – 0.2 VREF + 0.2 3.6 0.5 VCCI – 0.9 21 21 109 103 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

Figure 3-20 • AC Loading

Table 3-72 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)

VREF – 0.2 VREF + 0.2 1.5 1.5 1.485 30

Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.

Table 3-73 • SSTL3 Class II

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 1.5 V

Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

–F 0.79 2.48 0.05 1.50 0.51 2.53 2.01 5.21 4.69 ns

Std. 0.66 2.07 0.04 1.25 0.43 2.10 1.67 4.34 3.91 ns

–1 0.56 1.76 0.04 1.06 0.36 1.79 1.42 3.69 3.32 ns

–2 0.49 1.54 0.03 0.93 0.32 1.57 1.25 3.24 2.92 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

Test Point

30 pF

SSTL3

Class II

VTT

ProASIC3E Flash Family FPGAs

3-46 v2.0

Differential I/O Characteristics

Physical Implementation

Configuration of the I/O modules as a differential pair is

handled by the Actel Designer software when the user

instantiates a differential I/O macro in the design.

Differential I/Os can also be used in conjunction with the

embedded Input Register (InReg), Output Register

(OutReg), Enable Register (EnReg), and DDR. However,

there is no support for bidirectional I/Os or tristates with

the LVPECL standards.

LVDS

Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is

a high-speed, differential I/O standard. It requires that

one data bit be carried through two signal lines, so two

pins are needed. It also requires external resistor

termination.

The full implementation of the LVDS transmitter and

receiver is shown in an example in Figure 3-21. The

building blocks of the LVDS transmitter-receiver are one

transmitter macro, one receiver macro, three board

resistors at the transmitter end, and one resistor at the

receiver end. The values for the three driver resistors are

different from those used in the LVPECL implementation

because the output standard specifications are different.

Along with LVDS I/O, ProASIC3E also supports Bus LVDS

structure and Multipoint LVDS (M-LVDS) configuration

(up to 40 nodes).

Figure 3-21 • LVDS Circuit Diagram and Board-Level Implementation

Table 3-74 • Minimum and Maximum DC Input and Output Levels

DC Parameter Description Min. Typ. Max. Units

VCCI Supply Voltage 2.375 2.5 2.625 V

VOL Output LOW Voltage 0.9 1.075 1.25 V

VOH Output HIGH Voltage 1.25 1.425 1.6 V

VIInput Voltage 0 – 2.925 V

VODIFF Differential Output Voltage 250 350 450 mV

VOCM Output Common-Mode Voltage 1.125 1.25 1.375 V

VICM Input Common-Mode Voltage 0.05 1.25 2.35 V

VIDIFF Input Differential Voltage 100 350 – mV

Notes:

1. ± 5%

2. Differential input voltage = ±350 mV

Table 3-75 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) VREF (typ.) (V)

1.075 1.325 Cross point –

Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.

140 Ω100 Ω

ZO = 50 Ω

165 Ω

–

INBUF_LVDS

OUTBUF_LVDS

FPGA FPGA

Bourns Part Number: CAT16-LV4F12

ProASIC3E Flash Family FPGAs

v2.0 3-47

Timing Characteristics

BLVDS/M-LVDS

Bus LVDS (BLVDS) and Multipoint LVDS (M-LVDS)

specifications extend the existing LVDS standard to high-

performance multipoint bus applications. Multidrop and

multipoint bus configurations may contain any

combination of drivers, receivers, and transceivers. Actel

LVDS drivers provide the higher drive current required by

BLVDS and M-LVDS to accommodate the loading. The

drivers require series terminations for better signal quality

and to control voltage swing. Termination is also required

at both ends of the bus since the driver can be located

anywhere on the bus. These configurations can be

implemented using the TRIBUF_LVDS and BIBUF_LVDS

macros along with appropriate terminations. Multipoint

designs using Actel LVDS macros can achieve up to

200 MHz with a maximum of 20 loads. A sample

application is given in Figure 3-22. The input and output

buffer delays are available in the LVDS section in Table 3-

76.

Example: For a bus consisting of 20 equidistant loads, the

following terminations provide the required differential

voltage, in worst-case Industrial operating conditions, at

the farthest receiver: RS=60Ω and RT=70Ω, given

Z0=50Ω (2") and Zstub =50Ω (~1.5").

Table 3-76 • LVDS

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Speed Grade tDOUT tDP tDIN tPY Units

–F 0.79 2.25 0.05 2.18 ns

Std. 0.66 1.87 0.04 1.82 ns

–1 0.56 1.59 0.04 1.55 ns

–2 0.49 1.40 0.03 1.36 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

Figure 3-22 • BLVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers

...

BIBUF_LVDS

-T

-R

-T

EN EN EN EN EN

Receiver Transceiver Receiver TransceiverDriver

RSRSRSRSRSRSRSRS

RSRS

Zstub Zstub Zstub Zstub Zstub Zstub Zstub Zstub

ProASIC3E Flash Family FPGAs

3-48 v2.0

LVPECL

Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is

another differential I/O standard. It requires that one

data bit be carried through two signal lines. Like LVDS,

two pins are needed. It also requires external resistor

termination.

The full implementation of the LVDS transmitter and

receiver is shown in an example in Figure 3-23. The

building blocks of the LVPECL transmitter-receiver are

one transmitter macro, one receiver macro, three board

resistors at the transmitter end, and one resistor at the

receiver end. The values for the three driver resistors are

different from those used in the LVDS implementation

because the output standard specifications are different.

Timing Characteristics

Figure 3-23 • LVPECL Circuit Diagram and Board-Level Implementation

Table 3-77 • Minimum and Maximum DC Input and Output Levels

DC Parameter Description Min. Max. Min. Max. Min. Max. Units

VCCI Supply Voltage 3.0 3.3 3.6 V

VOL Output LOW Voltage 0.96 1.27 1.06 1.43 1.30 1.57 V

VOH Output HIGH Voltage 1.8 2.11 1.92 2.28 2.13 2.41 V

VIL, VIH Input LOW, Input HIGH Voltages 0 3.3 0 3.6 0 3.9 V

VODIFF Differential Output Voltage 0.625 0.97 0.625 0.97 0.625 0.97 V

VOCM Output Common-Mode Voltage 1.762 1.98 1.762 1.98 1.762 1.98 V

VICM Input Common-Mode Voltage 1.01 2.57 1.01 2.57 1.01 2.57 V

VIDIFF Input Differential Voltage 300 300 300 mV

Table 3-78 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) VREF (typ.) (V)

1.64 1.94 Cross point –

Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.

Table 3-79 • LVPECL

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Speed Grade tDOUT tDP tDIN tPY Units

–F 0.79 2.19 0.05 1.96 ns

Std. 0.66 1.83 0.04 1.63 ns

–1 0.56 1.55 0.04 1.39 ns

–2 0.49 1.36 0.03 1.22 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

187 W 100 Ω

ZO = 50 Ω

100 Ω

–

INBUF_LVPECL

OUTBUF_LVPECL

FPGA FPGA

Bourns Part Number: CAT16-PC4F12

ProASIC3E Flash Family FPGAs

v2.0 3-49

I/O Register Specifications

Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset

Figure 3-24 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset

INBUF

INBUF INBUF

TRIBUF

CLKBUF

INBUF

CLKBUF

Data Input I/O Register with:

Active High Enable

Active High Preset

Positive Edge Triggered

Data Output Register and

Enable Output Register with:

Active High Enable

Active High Preset

Postive Edge Triggered

Pad Out

CLK

Enable

Preset

Data_out

Data

EOUT

DOUT

Enable

CLK

DFN1E1P1

PRE

DFN1E1P1

PRE

DFN1E1P1

PRE

D_Enable

Core

Array

ProASIC3E Flash Family FPGAs

3-50 v2.0

Table 3-80 • Parameter Definition and Measuring Nodes

Parameter Name Parameter Definition Measuring Nodes (from, to)*

tOCLKQ Clock-to-Q of the Output Data Register H, DOUT

tOSUD Data Setup Time for the Output Data Register F, H

tOHD Data Hold Time for the Output Data Register F, H

tOSUE Enable Setup Time for the Output Data Register G, H

tOHE Enable Hold Time for the Output Data Register G, H

tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register L, DOUT

tOREMPRE Asynchronous Preset Removal Time for the Output Data Register L, H

tORECPRE Asynchronous Preset Recovery Time for the Output Data Register L, H

tOECLKQ Clock-to-Q of the Output Enable Register H, EOUT

tOESUD Data Setup Time for the Output Enable Register J, H

tOEHD Data Hold Time for the Output Enable Register J, H

tOESUE Enable Setup Time for the Output Enable Register K, H

tOEHE Enable Hold Time for the Output Enable Register K, H

tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register I, EOUT

tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register I, H

tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register I, H

tICLKQ Clock-to-Q of the Input Data Register A, E

tISUD Data Setup Time for the Input Data Register C, A

tIHD Data Hold Time for the Input Data Register C, A

tISUE Enable Setup Time for the Input Data Register B, A

tIHE Enable Hold Time for the Input Data Register B, A

tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register D, E

tIREMPRE Asynchronous Preset Removal Time for the Input Data Register D, A

tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register D, A

Note: *See Figure 3-24 on page 3-49 for more information.

ProASIC3E Flash Family FPGAs

v2.0 3-51

Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear

Figure 3-25 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear

Enable

CLK

Pad Out

CLK

Enable

CLR

Data_out

Data

EOUT

DOUT

Core

Array

DFN1E1C1

CLR

DFN1E1C1

CLR

DFN1E1C1

CLR

D_Enable

CLKBUF

INBUF

TRIBUF

INBUF INBUF CLKBUF

INBUF

Data Input I/O Register with

Active High Enable

Active High Clear

Positive Edge Triggered Data Output Register and

Enable Output Register with

Active High Enable

Active High Clear

Positive Edge Triggered

ProASIC3E Flash Family FPGAs

3-52 v2.0

Table 3-81 • Parameter Definition and Measuring Nodes

Parameter Name Parameter Definition Measuring Nodes (from, to)*

tOCLKQ Clock-to-Q of the Output Data Register HH, DOUT

tOSUD Data Setup Time for the Output Data Register FF, HH

tOHD Data Hold Time for the Output Data Register FF, HH

tOSUE Enable Setup Time for the Output Data Register GG, HH

tOHE Enable Hold Time for the Output Data Register GG, HH

tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register LL, DOUT

tOREMCLR Asynchronous Clear Removal Time for the Output Data Register LL, HH

tORECCLR Asynchronous Clear Recovery Time for the Output Data Register LL, HH

tOECLKQ Clock-to-Q of the Output Enable Register HH, EOUT

tOESUD Data Setup Time for the Output Enable Register JJ, HH

tOEHD Data Hold Time for the Output Enable Register JJ, HH

tOESUE Enable Setup Time for the Output Enable Register KK, HH

tOEHE Enable Hold Time for the Output Enable Register KK, HH

tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register II, EOUT

tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register II, HH

tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register II, HH

tICLKQ Clock-to-Q of the Input Data Register AA, EE

tISUD Data Setup Time for the Input Data Register CC, AA

tIHD Data Hold Time for the Input Data Register CC, AA

tISUE Enable Setup Time for the Input Data Register BB, AA

tIHE Enable Hold Time for the Input Data Register BB, AA

tICLR2Q Asynchronous Clear-to-Q of the Input Data Register DD, EE

tIREMCLR Asynchronous Clear Removal Time for the Input Data Register DD, AA

tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register DD, AA

Note: *See Figure 3-25 on page 3-51 for more information.

ProASIC3E Flash Family FPGAs

v2.0 3-53

Input Register

Timing Characteristics

Figure 3-26 • Input Register Timing Diagram

50%

Preset

Clear

Out_1

CLK

Data

Enable

tISUE

50%

tISUD

tIHD

50% 50%

tICLKQ

tIHE

tIRECPRE tIREMPRE

tIRECCLR tIREMCLR

tIWCLR

tIWPRE

tIPRE2Q

tICLR2Q

tICKMPWH tICKMPWL

50% 50%

50% 50% 50%

50% 50%

50% 50% 50% 50% 50% 50%

50%

Table 3-82 • Input Data Register Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tICLKQ Clock-to-Q of the Input Data Register 0.24 0.27 0.32 0.38 ns

tISUD Data Setup Time for the Input Data Register 0.26 0.30 0.35 0.42 ns

tIHD Data Hold Time for the Input Data Register 0.00 0.00 0.00 0.00 ns

tISUE Enable Setup Time for the Input Data Register 0.37 0.42 0.50 0.60 ns

tIHE Enable Hold Time for the Input Data Register 0.00 0.00 0.00 0.00 ns

tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.45 0.52 0.61 0.73 ns

tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.45 0.52 0.61 0.73 ns

tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 0.00 0.00 0.00 ns

tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.22 0.25 0.30 0.36 ns

tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 0.00 0.00 0.00 ns

tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.22 0.25 0.30 0.36 ns

tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.22 0.25 0.30 0.36 ns

tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.22 0.25 0.30 0.36 ns

tICKMPWH Clock Minimum Pulse Width HIGH for the Input Data Register 0.36 0.41 0.48 0.57 ns

tICKMPWL Clock Minimum Pulse Width LOW for the Input Data Register 0.32 0.37 0.43 0.52 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

ProASIC3E Flash Family FPGAs

3-54 v2.0

Output Register

Timing Characteristics

Figure 3-27 • Output Register Timing Diagram

Preset

Clear

DOUT

CLK

Data_out

Enable

tOSUE

50%

tOSUD tOHD

50% 50%

tOCLKQ

tOHE

tORECPRE

tOREMPRE

tORECCLR tOREMCLR

tOWCLR

tOWPRE

tOPRE2Q

tOCLR2Q

tOCKMPWH tOCKMPWL

50% 50%

50% 50% 50%

50% 50%

50% 50% 50% 50% 50% 50%

50%

Table 3-83 • Output Data Register Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tOCLKQ Clock-to-Q of the Output Data Register 0.59 0.67 0.79 0.95 ns

tOSUD Data Setup Time for the Output Data Register 0.31 0.36 0.42 0.50 ns

tOHD Data Hold Time for the Output Data Register 0.00 0.00 0.00 0.00 ns

tOSUE Enable Setup Time for the Output Data Register 0.44 0.50 0.59 0.70 ns

tOHE Enable Hold Time for the Output Data Register 0.00 0.00 0.00 0.00 ns

tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 0.80 0.91 1.07 1.29 ns

tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 0.80 0.91 1.07 1.29 ns

tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 0.00 0.00 0.00 ns

tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.22 0.25 0.30 0.36 ns

tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 0.00 0.00 0.00 ns

tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.22 0.25 0.30 0.36 ns

tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.22 0.25 0.30 0.36 ns

tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.22 0.25 0.30 0.36 ns

tOCKMPWH Clock Minimum Pulse Width HIGH for the Output Data Register 0.36 0.41 0.48 0.57 ns

tOCKMPWL Clock Minimum Pulse Width LOW for the Output Data Register 0.32 0.37 0.43 0.52 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

ProASIC3E Flash Family FPGAs

v2.0 3-55

Output Enable Register

Timing Characteristics

Figure 3-28 • Output Enable Register Timing Diagram

50%

Preset

Clear

EOUT

CLK

D_Enable

Enable

tOESUE

50%

tOESUD tOEHD

50% 50%

tOECLKQ

tOEHE

tOERECPRE

tOEREMPRE

tOERECCLR tOEREMCLR

tOEWCLR

tOEWPRE

tOEPRE2Q tOECLR2Q

tOECKMPWH tOECKMPWL

50% 50%

50% 50% 50%

50% 50%

50% 50% 50% 50% 50% 50%

50%

Table 3-84 • Output Enable Register Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tOECLKQ Clock-to-Q of the Output Enable Register 0.59 0.67 0.79 0.95 ns

tOESUD Data Setup Time for the Output Enable Register 0.31 0.36 0.42 0.50 ns

tOEHD Data Hold Time for the Output Enable Register 0.00 0.00 0.00 0.00 ns

tOESUE Enable Setup Time for the Output Enable Register 0.44 0.50 0.58 0.70 ns

tOEHE Enable Hold Time for the Output Enable Register 0.00 0.00 0.00 0.00 ns

tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 0.67 0.76 0.89 1.07 ns

tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 0.67 0.76 0.89 1.07 ns

tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 0.00 0.00 0.00 ns

tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.22 0.25 0.30 0.36 ns

tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 0.00 0.00 0.00 ns

tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.22 0.25 0.30 0.36 ns

tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.22 0.25 0.30 0.36 ns

tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.22 0.25 0.30 0.36 ns

tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register 0.36 0.41 0.48 0.57 ns

tOECKMPWL Clock Minimum Pulse Width LOW for the Output Enable Register 0.32 0.37 0.43 0.52 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

ProASIC3E Flash Family FPGAs

3-56 v2.0

DDR Module Specifications

Input DDR Module

Figure 3-29 • Input DDR Timing Model

Table 3-85 • Parameter Definitions

Parameter Name Parameter Definition Measuring Nodes (from, to)

tDDRICLKQ1 Clock-to-Out Out_QR B, D

tDDRICLKQ2 Clock-to-Out Out_QF B, E

tDDRISUD Data Setup Time of DDR input A, B

tDDRIHD Data Hold Time of DDR input A, B

tDDRICLR2Q1 Clear-to-Out Out_QR C, D

tDDRICLR2Q2 Clear-to-Out Out_QF C, E

tDDRIREMCLR Clear Removal C, B

tDDRIRECCLR Clear Recovery C, B

Input DDR

Data

CLK

CLKBUF

INBUF

Out_QF

(to core)

FF2

FF1

INBUF

CLR

DDR_IN

Out_QR

(to core)

ProASIC3E Flash Family FPGAs

v2.0 3-57

Timing Characteristics

Figure 3-30 • Input DDR Timing Diagram

tDDRICLR2Q2

tDDRIREMCLR

tDDRIRECCLR

tDDRICLR2Q1

12 3 4 5 6 7 8 9

CLK

Data

CLR

Out_QR

Out_QF

tDDRICLKQ1

246

357

tDDRIHD

tDDRISUD

tDDRICLKQ2

Table 3-86 • Input DDR Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tDDRICLKQ1 Clock-to-Out Out_QR for Input DDR 0.39 0.44 0.52 0.62 ns

tDDRICLKQ2 Clock-to-Out Out_QF for Input DDR 0.27 0.31 0.37 0.44 ns

tDDRISUD Data Setup for Input DDR 0.28 0.32 0.38 0.45 ns

tDDRIHD Data Hold for Input DDR 0.00 0.00 0.00 0.00 ns

tDDRICLR2Q1 Asynchronous Clear to Out Out_QR for Input DDR 0.57 0.65 0.76 0.92 ns

tDDRICLR2Q2 Asynchronous Clear-to-Out Out_QF for Input DDR 0.46 0.53 0.62 0.74 ns

tDDRIREMCLR Asynchronous Clear Removal Time for Input DDR 0.00 0.00 0.00 0.00 ns

tDDRIRECCLR Asynchronous Clear Recovery Time for Input DDR 0.22 0.25 0.30 0.36 ns

tDDRIWCLR Asynchronous Clear Minimum Pulse Width for Input DDR 0.22 0.25 0.30 0.36 ns

tDDRICKMPWH Clock Minimum Pulse Width HIGH for Input DDR 0.36 0.41 0.48 0.57 ns

tDDRICKMPWL Clock Minimum Pulse Width LOW for Input DDR 0.32 0.37 0.43 0.52 ns

FDDRIMAX Maximum Frequency for Input DDR 1404 1232 1048 871 MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

ProASIC3E Flash Family FPGAs

3-58 v2.0

Output DDR Module

Figure 3-31 • Output DDR Timing Model

Table 3-87 • Parameter Definitions

Parameter Name Parameter Definition Measuring Nodes (from, to)

tDDROCLKQ Clock-to-Out B, E

tDDROCLR2Q Asynchronous Clear-to-Out C, E

tDDROREMCLR Clear Removal C, B

tDDRORECCLR Clear Recovery C, B

tDDROSUD1 Data Setup Data_F A, B

tDDROSUD2 Data Setup Data_R D, B

tDDROHD1 Data Hold Data_F A, B

tDDROHD2 Data Hold Data_R D, B

Data_F

(from core)

CLK

CLKBUF

Out

FF2

INBUF

CLR

DDR_OUT

Output DDR

FF1

OUTBUF

Data_R

(from core)

ProASIC3E Flash Family FPGAs

v2.0 3-59

Timing Characteristics

Figure 3-32 • Output DDR Timing Diagram

116

910

28 3 9

tDDROREMCLR

tDDROHD1

tDDROREMCLR

tDDROHD2

tDDROSUD2

tDDROCLKQ

tDDRORECCLR

CLK

Data_R

Data_F

CLR

Out

tDDROCLR2Q

7104

Table 3-88 • Output DDR Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tDDROCLKQ Clock-to-Out of DDR for Output DDR 0.70 0.80 0.94 1.13 ns

tDDROSUD1 Data_F Data Setup for Output DDR 0.38 0.43 0.51 0.61 ns

tDDROSUD2 Data_R Data Setup for Output DDR 0.38 0.43 0.51 0.61 ns

tDDROHD1 Data_F Data Hold for Output DDR 0.00 0.00 0.00 0.00 ns

tDDROHD2 Data_R Data Hold for Output DDR 0.00 0.00 0.00 0.00 ns

tDDROCLR2Q Asynchronous Clear-to-Out for Output DDR 0.80 0.91 1.07 1.29 ns

tDDROREMCLR Asynchronous Clear Removal Time for Output DDR 0.00 0.00 0.00 0.00 ns

tDDRORECCLR Asynchronous Clear Recovery Time for Output DDR 0.22 0.25 0.30 0.36 ns

tDDROWCLR1 Asynchronous Clear Minimum Pulse Width for Output DDR 0.22 0.25 0.30 0.36 ns

tDDROCKMPWH Clock Minimum Pulse Width HIGH for the Output DDR 0.36 0.41 0.48 0.57 ns

tDDROCKMPWL Clock Minimum Pulse Width LOW for the Output DDR 0.32 0.37 0.43 0.52 ns

FDDOMAX Maximum Frequency for the Output DDR 1404 1232 1048 871 MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

ProASIC3E Flash Family FPGAs

3-60 v2.0

VersaTile Characteristics

VersaTile Specifications as a Combinatorial Module

The ProASIC3E library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics

are presented for a sample of the library. For more details, refer to the ProASIC3/E Macro Library Guide.

Figure 3-33 • Sample of Combinatorial Cells

MAJ3

MUX2

XOR2 Y

NOR2

YOR2

INV

AND2

NAND3

XOR3

NAND2

ProASIC3E Flash Family FPGAs

v2.0 3-61

Figure 3-34 • Timing Model and Waveforms

tPD

tPD = MAX(tPD(RR), tPD(RF),

tPD(FF), tPD(FR)) where edges are

applicable for the particular

combinatorial cell

NAND2 or

Any Combinatorial

Logic

tPD

50%

VCC

50%

GND

A, B, C

50% 50%

50%

(RR)

(RF) GND

OUT

GND

50%

(FF)

(FR)

tPD

ProASIC3E Flash Family FPGAs

3-62 v2.0

Timing Characteristics

VersaTile Specifications as a Sequential Module

The ProASIC3E library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input

and optional enable, clear, or preset. In this section, timing characteristics are presented for a representative sample

from the library. For more details, refer to the ProASIC3/E Macro Library Guide.

Table 3-89 • Combinatorial Cell Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Combinatorial Cell Equation Parameter –2 –1 Std. –F Units

INV Y = !A tPD 0.40 0.46 0.54 0.65 ns

AND2 Y = A · B tPD 0.47 0.54 0.63 0.76 ns

NAND2 Y = !(A · B) tPD 0.47 0.54 0.63 0.76 ns

OR2 Y = A + B tPD 0.49 0.55 0.65 0.78 ns

NOR2 Y = !(A + B) tPD 0.49 0.55 0.65 0.78 ns

XOR2 Y = A ⊕ Bt

PD 0.74 0.84 0.99 1.19 ns

MAJ3 Y = MAJ(A , B, C) tPD 0.70 0.79 0.93 1.12 ns

XOR3 Y = A ⊕ B ⊕ Ct

PD 0.87 1.00 1.17 1.41 ns

MUX2 Y = A !S + B S tPD 0.51 0.58 0.68 0.81 ns

AND3 Y = A · B · C tPD 0.56 0.64 0.75 0.90 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

Figure 3-35 • Sample of Sequential Cells

DFN1

Data

CLK

Out

DFN1C1

Data

CLK

Out

CLR

DFI1E1P1

Data

CLK

Out

PRE

DFN1E1

Data

CLK

Out

ProASIC3E Flash Family FPGAs

v2.0 3-63

Timing Characteristics

Figure 3-36 • Timing Model and Waveforms

PRE

CLR

Out

CLK

Data

tSUE

50%

tSUD

tHD

50% 50%

tCLKQ

tHE

tRECPRE tREMPRE

tRECCLR tREMCLRtWCLR

tWPRE

tPRE2Q tCLR2Q

tCKMPWH tCKMPWL

50% 50%

50% 50% 50%

50% 50%

50% 50% 50% 50% 50% 50%

50%

Table 3-90 • Register Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tCLKQ Clock-to-Q of the Core Register 0.55 0.63 0.74 0.89 ns

tSUD Data Setup Time for the Core Register 0.43 0.49 0.57 0.69 ns

tHD Data Hold Time for the Core Register 0.00 0.00 0.00 0.00 ns

tSUE Enable Setup Time for the Core Register 0.45 0.52 0.61 0.73 ns

tHE Enable Hold Time for the Core Register 0.00 0.00 0.00 0.00 ns

tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.40 0.45 0.53 0.64 ns

tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.40 0.45 0.53 0.64 ns

tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 0.00 0.00 0.00 ns

tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.22 0.25 0.30 0.36 ns

tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 0.00 0.00 0.00 ns

tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.22 0.25 0.30 0.36 ns

tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.22 0.25 0.30 0.36 ns

tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.22 0.25 0.30 0.36 ns

tCKMPWH Clock Minimum Pulse Width HIGH for the Core Register 0.32 0.37 0.43 0.52 ns

tCKMPWL Clock Minimum Pulse Width LOW for the Core Register 0.36 0.41 0.48 0.57 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

ProASIC3E Flash Family FPGAs

3-64 v2.0

Global Resource Characteristics

A3PE600 Clock Tree Topology

Clock delays are device-specific. Figure 3-37 is an example of a global tree used for clock routing. The global tree

presented in Figure 3-37 is driven by a CCC located on the west side of the A3PE600 device. It is used to drive all D-flip-

flops in the device.

Figure 3-37 • Example of Global Tree Use in an A3PE600 Device for Clock Routing

Central

Global Rib

VersaTile

Rows

Global Spine

CCC

ProASIC3E Flash Family FPGAs

v2.0 3-65

Global Tree Timing Characteristics

Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input

buffer clock delays, as these are I/O standard–dependent, and the clock may be driven and conditioned internally by

the CCC module. For more details on clock conditioning capabilities, refer to the "Clock Conditioning Circuits" section

on page 2-13. Table 3-91, Table 3-92, and Table 3-93 on page 3-66 present minimum and maximum global clock delays

within the device. Minimum and maximum delays are measured with minimum and maximum loading.

Timing Characteristics

Table 3-91 • A3PE600 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std. –F

UnitsMin.1Max.2Min.1Max.2Min.1Max.2Min.1Max.2

tRCKL Input LOW Delay for Global Clock 0.83 1.04 0.94 1.18 1.11 1.39 1.33 1.67 ns

tRCKH Input HIGH Delay for Global Clock 0.81 1.06 0.93 1.21 1.09 1.42 1.31 1.71 ns

tRCKMPWH Minimum Pulse Width HIGH for Global

Clock

tRCKMPWL Minimum Pulse Width LOW for Global

Clock

tRCKSW Maximum Skew for Global Clock 0.25 0.28 0.33 0.40 ns

FRMAX Maximum Frequency for Global Clock MHz

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a

lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row

(all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

Table 3-92 • A3PE1500 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std. –F

UnitsMin.1Max.2Min.1Max.2Min.1Max.2Min.1Max.2

tRCKL Input LOW Delay for Global Clock 1.07 1.29 1.22 1.47 1.43 1.72 1.72 2.07 ns

tRCKH Input HIGH Delay for Global Clock 1.06 1.32 1.21 1.50 1.42 1.76 1.71 2.12 ns

tRCKMPWH Minimum Pulse Width HIGH for Global

Clock

tRCKMPWL Minimum Pulse Width LOW for Global

Clock

tRCKSW Maximum Skew for Global Clock 0.26 0.29 0.34 0.41 ns

FRMAX Maximum Frequency for Global Clock MHz

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a

lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row

(all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

ProASIC3E Flash Family FPGAs

3-66 v2.0

Table 3-93 • A3PE3000 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std. –F

UnitsMin.1Max.2Min.1Max.2Min.1Max.2Min.1Max.2

tRCKL Input LOW Delay for Global Clock 1.41 1.62 1.60 1.85 1.88 2.17 2.26 2.61 ns

tRCKH Input HIGH Delay for Global Clock 1.40 1.66 1.59 1.89 1.87 2.22 2.25 2.66 ns

tRCKMPWH Minimum Pulse Width HIGH for Global

Clock

tRCKMPWL Minimum Pulse Width LOW for Global

Clock

tRCKSW Maximum Skew for Global Clock 0.26 0.29 0.35 0.41 ns

FRMAX Maximum Frequency for Global Clock MHz

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly

loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row

(all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

ProASIC3E Flash Family FPGAs

v2.0 3-67

Embedded SRAM and FIFO Characteristics

SRAM

Figure 3-38 • RAM Models

ADDRA11 DOUTA8

DOUTA7

DOUTA0

DOUTB8

DOUTB7

DOUTB0

ADDRA10

ADDRA0

DINA8

DINA7

DINA0

WIDTHA1

WIDTHA0

PIPEA

WMODEA

BLKA

WENA

CLKA

ADDRB11

ADDRB10

ADDRB0

DINB8

DINB7

DINB0

WIDTHB1

WIDTHB0

PIPEB

WMODEB

BLKB

WENB

CLKB

RAM4K9

RADDR8 RD17

RADDR7 RD16

RADDR0 RD0

WD17

WD16

WD0

WW1

WW0

RW1

RW0

PIPE

REN

RCLK

RAM512X18

WADDR8

WADDR7

WADDR0

WEN

WCLK

RESET

ProASIC3E Flash Family FPGAs

3-68 v2.0

Timing Waveforms

Figure 3-39 • RAM Read for Pass-Through Output

Figure 3-40 • RAM Read for Pipelined Output

CLK

ADD

BLK_B

WEN_B

A0A1A2

D0D1D2

tCYC

tCKH tCKL

tAS tAH

tBKS

tENS tENH

tDOH1

tBKH

tCKQ1

CLK

ADD

BLK_B

WEN_B

A0A1A2

D0D1

tCYC

tCKH tCKL

tAS tAH

tBKS

tENS tENH

tDOH2

tCKQ2

tBKH

ProASIC3E Flash Family FPGAs

v2.0 3-69

Figure 3-41 • RAM Write, Output Retained (WMODE = 0)

Figure 3-42 • RAM Write, Output as Write Data (WMODE = 1)

tCYC

tCKH tCKL

A0A1A2

DI0DI1

tAS tAH

tBKS

tENS tENH

tDS tDH

CLK

BLK_B

WEN_B

ADD

tBKH

CYC

CKH

CKL

BKS

ENS

CLK

BLK_B

WEN_B

ADD

BKH

(pass-through) DI

(Pipelined) DI

ProASIC3E Flash Family FPGAs

3-70 v2.0

Figure 3-43 • Write Access After Write onto Same Address

CLK1

CLK2

WEN_B1

WEN_B2

ADD1

ADD2

DI1

DI2

DO2

(pass-through)

DO2

(pipelined)

tAH

tAS

tAH

tAS

tDH

tCCKH

tDS

tCKQ1

tCKQ2

DnD0

A0A4

ProASIC3E Flash Family FPGAs

v2.0 3-71

Figure 3-44 • Read Access After Write onto Same Address

CLK1

CLK2

WEN_B1

WEN_B2

ADD1

ADD2

DI1

DO2

(pass-through)

DO2

(pipelined)

tAH

tAS

tAH

tAS

tDH

tDS

tWRO

tCKQ1

tCKQ2

A0A1A4

DnD0

D0D1

ProASIC3E Flash Family FPGAs

3-72 v2.0

Figure 3-45 • Write Access After Read onto Same Address

Figure 3-46 • RAM Reset

A0A1A0

A0A1A3

D1D2D3

tAH

tAS

tAH

tAS

tCKQ1 tCKQ1

tCKQ2

tCCKH

CLK1

ADD1

WEN_B1

DO1

(pass-through)

DO1

(pipelined)

CLK2

ADD2

DI2

WEN_B2

D0D1

CLK

RESET_B

DO Dn

tCYC

tCKH tCKL

tRSTBQ

ProASIC3E Flash Family FPGAs

v2.0 3-73

Timing Characteristics

Table 3-94 • RAM4K9

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tAS Address Setup Time 0.25 0.28 0.33 0.40 ns

tAH Address Hold Time 0.00 0.00 0.00 0.00 ns

tENS REN_B, WEN_B Setup Time 0.14 0.16 0.19 0.23 ns

tENH REN_B, WEN_B Hold Time 0.10 0.11 0.13 0.16 ns

tBKS BLK_B Setup Time 0.23 0.27 0.31 0.37 ns

tBKH BLK_B Hold Time 0.02 0.02 0.02 0.03 ns

tDS Input Data (DI) Setup Time 0.18 0.21 0.25 0.29 ns

tDH Input Data (DI) Hold Time 0.00 0.00 0.00 0.00 ns

tCKQ1 Clock HIGH to New Data Valid on DO (output retained, WMODE = 0) 1.79 2.03 2.39 2.87 ns

Clock HIGH to New Data Valid on DO (pass-through, WMODE = 1) 2.36 2.68 3.15 3.79 ns

tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 0.89 1.02 1.20 1.44 ns

tWRO Address collision clk-to-clk delay for reliable read access after write on

same address

TBD TBD TBD TBD ns

tCCKH Address collision clk-to-clk delay for reliable write access after

write/read on same address

TBD TBD TBD TBD ns

tRSTBQ RESET_B LOW to Data Out LOW on DO (pass-through) 0.92 1.05 1.23 1.48 ns

RESET_B LOW to Data Out LOW on DO (pipelined) 0.92 1.05 1.23 1.48 ns

tREMRSTB RESET_B Removal 0.29 0.33 0.38 0.46 ns

tRECRSTB RESET_B Recovery 1.50 1.71 2.01 2.41 ns

tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 0.34 ns

tCYC Clock Cycle Time 3.23 3.68 4.32 5.19 ns

FMAX Maximum Frequency 310 272 231 193 MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

ProASIC3E Flash Family FPGAs

3-74 v2.0

Table 3-95 • RAM512X18

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tAS Address Setup Time 0.25 0.28 0.33 0.40 ns

tAH Address Hold Time 0.00 0.00 0.00 0.00 ns

tENS REN_B, WEN_B Setup Time 0.18 0.20 0.24 0.28 ns

tENH REB_B, WEN_B Hold Time 0.06 0.07 0.08 0.09 ns

tDS Input Data (DI) Setup Time 0.18 0.21 0.25 0.29 ns

tDH Input Data (DI) Hold Time 0.00 0.00 0.00 0.00 ns

tCKQ1 Clock HIGH to New Data Valid on DO (output retained, WMODE = 0) 2.16 2.46 2.89 3.47 ns

tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 0.90 1.02 1.20 1.44 ns

tWRO Address collision clk-to-clk delay for reliable read access after write on

same address

TBD TBD TBD TBD ns

tCCKH Address collision clk-to-clk delay for reliable write access after

write/read on same address

TBD TBD TBD TBD ns

tRSTBQ RESET_B LOW to Data Out LOW on DO (pass-through) 0.92 1.05 1.23 1.48 ns

RESET_B LOW to Data Out LOW on DO (pipelined) 0.92 1.05 1.23 1.48 ns

tREMRSTB RESET_B Removal 0.29 0.33 0.38 0.46 ns

tRECRSTB RESET_B Recovery 1.50 1.71 2.01 2.41 ns

tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 0.34 ns

tCYC Clock Cycle Time 3.23 3.68 4.32 5.19 ns

FMAX Maximum Frequency 310 272 231 193 MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

ProASIC3E Flash Family FPGAs

v2.0 3-75

FIFO

Timing Waveforms

Figure 3-47 • FIFO Model

FIFO4K18

RW2

RD17

RW1

RD16

RW0

WW2

WW1

WW0 RD0

ESTOP

FSTOP

FULL

AFULL

EMPTY

AFVAL11

AEMPTY

AFVAL10

AFVAL0

AEVAL11

AEVAL10

AEVAL0

REN

RBLK

RCLK

WEN

WBLK

WCLK

RPIPE

WD17

WD16

WD0

RESET

ProASIC3E Flash Family FPGAs

3-76 v2.0

Figure 3-48 • FIFO Reset

Figure 3-49 • FIFO EMPTY Flag and AEMPTY Flag Assertion

MATCH (A0)

tMPWRSTB

tRSTFG

tRSTCK

tRSTAF

RCLK/

WCLK

RESET_B

EMPTY

AEMPTY

WA/RA

(Address Counter)

tRSTFG

tRSTAF

FULL

AFULL

RCLK

NO MATCH NO MATCH Dist = AEF_TH MATCH (EMPTY)

tCKAF

tRCKEF

EMPTY

AEMPTY

tCYC

WA/RA

(Address Counter)

ProASIC3E Flash Family FPGAs

v2.0 3-77

Figure 3-50 • FIFO FULL Flag and AFULL Flag Assertion

Figure 3-51 • FIFO EMPTY Flag and AEMPTY Flag Deassertion

Figure 3-52 • FIFO FULL Flag and AFULL Flag Deassertion

NO MATCH NO MATCH Dist = AFF_TH MATCH (FULL)

tCKAF

tWCKFF

tCYC

WCLK

FULL

AFULL

WA/RA

(Address Counter)

WCLK

WA/RA

(Address Counter) MATCH

(EMPTY) NO MATCH NO MATCH NO MATCH Dist = AEF_TH + 1

NO MATCH

RCLK

EMPTY

1st Rising

Edge

After 1st

Write

2nd Rising

Edge

After 1st

Write

tRCKEF

tCKAF

AEMPTY

Dist = AFF_TH – 1

MATCH (FULL) NO MATCH NO MATCH NO MATCH NO MATCH

tWCKF

tCKAF

1st Rising

Edge

After 1st

Read

1st Rising

Edge

After 2nd

Read

RCLK

WA/RA

(Address Counter)

WCLK

FULL

AFULL

ProASIC3E Flash Family FPGAs

3-78 v2.0

Timing Characteristics

Table 3-96 • FIFO

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tENS REN_B, WEN_B Setup Time 1.38 1.57 1.84 2.21 ns

tENH REN_B, WEN_B Hold Time 0.02 0.02 0.02 0.03 ns

tBKS BLK_B Setup Time 0.19 0.22 0.26 0.31 ns

tBKH BLK_B Hold Time 0.00 0.00 0.00 0.00 ns

tDS Input Data (DI) Setup Time 0.18 0.21 0.25 0.29 ns

tDH Input Data (DI) Hold Time 0.00 0.00 0.00 0.00 ns

tCKQ1 Clock HIGH to New Data Valid on DO (pass-through) 2.36 2.68 3.15 3.79 ns

tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 0.89 1.02 1.20 1.44 ns

tRCKEF RCLK HIGH to Empty Flag Valid 1.72 1.96 2.30 2.76 ns

tWCKFF WCLK HIGH to Full Flag Valid 1.63 1.86 2.18 2.62 ns

tCKAF Clock HIGH to Almost Empty/Full Flag Valid 6.19 7.05 8.29 9.96 ns

tRSTFG RESET_B LOW to Empty/Full Flag Valid 1.69 1.93 2.27 2.72 ns

tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 6.13 6.98 8.20 9.85 ns

tRSTBQ RESET_B LOW to Data Out LOW on DO (pass-through) 0.92 1.05 1.23 1.48 ns

RESET_B LOW to Data Out LOW on DO (pipelined) 0.92 1.05 1.23 1.48 ns

tREMRSTB RESET_B Removal 0.29 0.33 0.38 0.46 ns

tRECRSTB RESET_B Recovery 1.50 1.71 2.01 2.41 ns

tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 0.34 ns

tCYC Clock Cycle Time 3.23 3.68 4.32 5.19 ns

FMAX Maximum Frequency 310 272 231 193 HMz

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

ProASIC3E Flash Family FPGAs

v2.0 3-79

Embedded FlashROM Characteristics

Timing Characteristics

Figure 3-53 • Timing Diagram

A0A1

tSU

tHOLD

tSU

tHOLD

tSU

tHOLD

tCKQ2 tCKQ2 tCKQ2

CLK

Address

Data D0D0D1

Table 3-97 • Embedded FlashROM Access Time

Parameter Description –2 –1 Std. Units

tSU Address Setup Time 0.53 0.61 0.71 ns

tHOLD Address Hold Time 0.00 0.00 0.00 ns

tCK2Q Clock to Out 16.23 18.48 21.73 ns

FMAX Maximum Clock Frequency 15 15 15 MHz

ProASIC3E Flash Family FPGAs

3-80 v2.0

JTAG 1532 Characteristics

JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the

corresponding standard selected; refer to the I/O timing characteristics in the "User I/O Characteristics" section on

page 3-11 for more details.

Timing Characteristics

Table 3-98 • JTAG 1532

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description –2 –1 Std. Units

tDISU Test Data Input Setup Time ns

tDIHD Test Data Input Hold Time ns

tTMSSU Test Mode Select Setup Time ns

tTMDHD Test Mode Select Hold Time ns

tTCK2Q Clock to Q (data out) ns

tRSTB2Q Reset to Q (data out) ns

FTCKMAX TCK Maximum Frequency 20 20 20 MHz

tTRSTREM ResetB Removal Time ns

tTRSTREC ResetB Recovery Time ns

tTRSTMPW ResetB Minimum Pulse ns

Note: For specific junction temperature and voltage supply levels, refer to Table 3-6 on page 3-4 for derating values.

ProASIC3E Flash Family FPGAs

v2.0 4-1

Package Pin Assignments

208-Pin PQFP

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.actel.com/products/solutions/package/docs.aspx.

Note: This is the top view of the package.

208-Pin PQFP

1208

ProASIC3E Flash Family FPGAs

4-2 v2.0

208-Pin PQFP*

Pin Number A3PE600 Function

1GND

2 GNDQ

3VMV7

4 GAB2/IO133PSB7V1

5 GAA2/IO134PDB7V1

6 IO134NDB7V1

7 GAC2/IO132PDB7V1

8 IO132NDB7V1

9 IO130PDB7V1

10 IO130NDB7V1

11 IO127PDB7V1

12 IO127NDB7V1

13 IO126PDB7V0

14 IO126NDB7V0

15 IO124PSB7V0

16 VCC

17 GND

18 VCCIB7

19 IO122PPB7V0

20 IO121PSB7V0

21 IO122NPB7V0

22 GFC1/IO120PSB7V0

23 GFB1/IO119PDB7V0

24 GFB0/IO119NDB7V0

25 VCOMPLF

26 GFA0/IO118NPB6V1

27 VCCPLF

28 GFA1/IO118PPB6V1

29 GND

30 GFA2/IO117PDB6V1

31 IO117NDB6V1

32 GFB2/IO116PPB6V1

33 GFC2/IO115PPB6V1

34 IO116NPB6V1

35 IO115NPB6V1

36 VCC

37 IO112PDB6V1

38 IO112NDB6V1

39 IO108PSB6V0

40 VCCIB6

41 GND

42 IO106PDB6V0

43 IO106NDB6V0

44 GEC1/IO104PDB6V0

45 GEC0/IO104NDB6V0

46 GEB1/IO103PPB6V0

47 GEA1/IO102PPB6V0

48 GEB0/IO103NPB6V0

49 GEA0/IO102NPB6V0

50 VMV6

51 GNDQ

52 GND

53 VMV5

54 GNDQ

55 IO101NDB5V2

56 GEA2/IO101PDB5V2

57 IO100NDB5V2

58 GEB2/IO100PDB5V2

59 IO99NDB5V2

60 GEC2/IO99PDB5V2

61 IO98PSB5V2

62 VCCIB5

63 IO96PSB5V2

64 IO94NDB5V1

65 GND

66 IO94PDB5V1

67 IO92NDB5V1

68 IO92PDB5V1

69 IO88NDB5V0

70 IO88PDB5V0

71 VCC

72 VCCIB5

73 IO85NPB5V0

74 IO84NPB5V0

75 IO85PPB5V0

76 IO84PPB5V0

208-Pin PQFP*

Pin Number A3PE600 Function

77 IO83NPB5V0

78 IO82NPB5V0

79 IO83PPB5V0

80 IO82PPB5V0

81 GND

82 IO80NDB4V1

83 IO80PDB4V1

84 IO79NPB4V1

85 IO78NPB4V1

86 IO79PPB4V1

87 IO78PPB4V1

88 VCC

89 VCCIB4

90 IO76NDB4V1

91 IO76PDB4V1

92 IO72NDB4V0

93 IO72PDB4V0

94 IO70NDB4V0

95 GDC2/IO70PDB4V0

96 IO68NDB4V0

97 GND

98 GDA2/IO68PDB4V0

99 GDB2/IO69PSB4V0

100 GNDQ

101 TCK

102 TDI

103 TMS

104 VMV4

105 GND

106 VPUMP

107 GNDQ

108 TDO

109 TRST

110 VJTAG

111 VMV3

112 GDA0/IO67NPB3V1

113 GDB0/IO66NPB3V1

114 GDA1/IO67PPB3V1

208-Pin PQFP*

Pin Number A3PE600 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3E Flash Family FPGAs

v2.0 4-3

115 GDB1/IO66PPB3V1

116 GDC0/IO65NDB3V1

117 GDC1/IO65PDB3V1

118 IO62NDB3V1

119 IO62PDB3V1

120 IO58NDB3V0

121 IO58PDB3V0

122 GND

123 VCCIB3

124 GCC2/IO55PSB3V0

125 GCB2/IO54PSB3V0

126 NC

127 IO53NDB3V0

128 GCA2/IO53PDB3V0

129 GCA1/IO52PPB3V0

130 GND

131 VCCPLC

132 GCA0/IO52NPB3V0

133 VCOMPLC

134 GCB0/IO51NDB2V1

135 GCB1/IO51PDB2V1

136 GCC1/IO50PSB2V1

137 IO49NDB2V1

138 IO49PDB2V1

139 IO48PSB2V1

140 VCCIB2

141 GND

142 VCC

143 IO47NDB2V1

144 IO47PDB2V1

145 IO44NDB2V1

146 IO44PDB2V1

208-Pin PQFP*

Pin Number A3PE600 Function

147 IO43NDB2V0

148 IO43PDB2V0

149 IO40NDB2V0

150 IO40PDB2V0

151 GBC2/IO38PSB2V0

152 GBA2/IO36PSB2V0

153 GBB2/IO37PSB2V0

154 VMV2

155 GNDQ

156 GND

157 VMV1

158 GNDQ

159 GBA1/IO35PDB1V1

160 GBA0/IO35NDB1V1

161 GBB1/IO34PDB1V1

162 GND

163 GBB0/IO34NDB1V1

164 GBC1/IO33PDB1V1

165 GBC0/IO33NDB1V1

166 IO31PDB1V1

167 IO31NDB1V1

168 IO27PDB1V0

169 IO27NDB1V0

170 VCCIB1

171 VCC

172 IO23PPB1V0

173 IO22PSB1V0

174 IO23NPB1V0

175 IO21PDB1V0

176 IO21NDB1V0

177 IO19PPB0V2

178 GND

208-Pin PQFP*

Pin Number A3PE600 Function

179 IO18PPB0V2

180 IO19NPB0V2

181 IO18NPB0V2

182 IO17PPB0V2

183 IO16PPB0V2

184 IO17NPB0V2

185 IO16NPB0V2

186 VCCIB0

187 VCC

188 IO15PDB0V2

189 IO15NDB0V2

190 IO13PDB0V2

191 IO13NDB0V2

192 IO11PSB0V1

193 IO09PDB0V1

194 IO09NDB0V1

195 GND

196 IO07PDB0V1

197 IO07NDB0V1

198 IO05PDB0V0

199 IO05NDB0V0

200 VCCIB0

201 GAC1/IO02PDB0V0

202 GAC0/IO02NDB0V0

203 GAB1/IO01PDB0V0

204 GAB0/IO01NDB0V0

205 GAA1/IO00PDB0V0

206 GAA0/IO00NDB0V0

207 GNDQ

208 VMV0

208-Pin PQFP*

Pin Number A3PE600 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3E Flash Family FPGAs

4-4 v2.0

208-Pin PQFP*

Pin Number A3PE1500 Function

1GND

2 GNDQ

3VMV7

4 GAB2/IO220PSB7V3

5 GAA2/IO221PDB7V3

6 IO221NDB7V3

7 GAC2/IO219PDB7V3

8 IO219NDB7V3

9 IO215PDB7V3

10 IO215NDB7V3

11 IO212PDB7V2

12 IO212NDB7V2

13 IO208PDB7V2

14 IO208NDB7V2

15 IO204PSB7V1

16 VCC

17 GND

18 VCCIB7

19 IO200PDB7V1

20 IO200NDB7V1

21 IO196PSB7V0

22 GFC1/IO192PSB7V0

23 GFB1/IO191PDB7V0

24 GFB0/IO191NDB7V0

25 VCOMPLF

26 GFA0/IO190NPB6V2

27 VCCPLF

28 GFA1/IO190PPB6V2

29 GND

30 GFA2/IO189PDB6V2

31 IO189NDB6V2

32 GFB2/IO188PPB6V2

33 GFC2/IO187PPB6V2

34 IO188NPB6V2

35 IO187NPB6V2

36 VCC

37 IO184PDB6V2

38 IO184NDB6V2

39 IO180PSB6V1

40 VCCIB6

41 GND

42 IO176PDB6V1

43 IO176NDB6V1

44 GEC1/IO169PDB6V0

45 GEC0/IO169NDB6V0

46 GEB1/IO168PPB6V0

47 GEA1/IO167PPB6V0

48 GEB0/IO168NPB6V0

49 GEA0/IO167NPB6V0

50 VMV6

51 GNDQ

52 GND

53 VMV5

54 GNDQ

55 IO166NDB5V3

56 GEA2/IO166PDB5V3

57 IO165NDB5V3

58 GEB2/IO165PDB5V3

59 IO164NDB5V3

60 GEC2/IO164PDB5V3

61 IO163PSB5V3

62 VCCIB5

63 IO161PSB5V3

64 IO157NDB5V2

65 GND

66 IO157PDB5V2

67 IO153NDB5V2

68 IO153PDB5V2

69 IO149NDB5V1

70 IO149PDB5V1

71 VCC

72 VCCIB5

208-Pin PQFP*

Pin Number A3PE1500 Function

73 IO145NDB5V1

74 IO145PDB5V1

75 IO143NDB5V1

76 IO143PDB5V1

77 IO137NDB5V0

78 IO137PDB5V0

79 IO135NDB5V0

80 IO135PDB5V0

81 GND

82 IO131NDB4V2

83 IO131PDB4V2

84 IO129NDB4V2

85 IO129PDB4V2

86 IO127NDB4V2

87 IO127PDB4V2

88 VCC

89 VCCIB4

90 IO121NDB4V1

91 IO121PDB4V1

92 IO119NDB4V1

93 IO119PDB4V1

94 IO113NDB4V0

95 GDC2/IO113PDB4V0

96 IO112NDB4V0

97 GND

98 GDB2/IO112PDB4V0

99 GDA2/IO111PSB4V0

100 GNDQ

101 TCK

102 TDI

103 TMS

104 VMV4

105 GND

106 VPUMP

107 GNDQ

108 TDO

208-Pin PQFP*

Pin Number A3PE1500 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3E Flash Family FPGAs

v2.0 4-5

109 TRST

110 VJTAG

111 VMV3

112 GDA0/IO110NPB3V2

113 GDB0/IO109NPB3V2

114 GDA1/IO110PPB3V2

115 GDB1/IO109PPB3V2

116 GDC0/IO108NDB3V2

117 GDC1/IO108PDB3V2

118 IO105NDB3V2

119 IO105PDB3V2

120 IO101NDB3V1

121 IO101PDB3V1

122 GND

123 VCCIB3

124 GCC2/IO90PSB3V0

125 GCB2/IO89PSB3V0

126 NC

127 IO88NDB3V0

128 GCA2/IO88PDB3V0

129 GCA1/IO87PPB3V0

130 GND

131 VCCPLC

132 GCA0/IO87NPB3V0

133 VCOMPLC

134 GCB0/IO86NDB2V3

135 GCB1/IO86PDB2V3

136 GCC1/IO85PSB2V3

137 IO83NDB2V3

138 IO83PDB2V3

139 IO81PSB2V3

140 VCCIB2

141 GND

142 VCC

208-Pin PQFP*

Pin Number A3PE1500 Function

143 IO73NDB2V2

144 IO73PDB2V2

145 IO71NDB2V2

146 IO71PDB2V2

147 IO67NDB2V1

148 IO67PDB2V1

149 IO65NDB2V1

150 IO65PDB2V1

151 GBC2/IO60PSB2V0

152 GBA2/IO58PSB2V0

153 GBB2/IO59PSB2V0

154 VMV2

155 GNDQ

156 GND

157 VMV1

158 GNDQ

159 GBA1/IO57PDB1V3

160 GBA0/IO57NDB1V3

161 GBB1/IO56PDB1V3

162 GND

163 GBB0/IO56NDB1V3

164 GBC1/IO55PDB1V3

165 GBC0/IO55NDB1V3

166 IO51PDB1V2

167 IO51NDB1V2

168 IO47PDB1V1

169 IO47NDB1V1

170 VCCIB1

171 VCC

172 IO43PSB1V1

173 IO41PDB1V1

174 IO41NDB1V1

175 IO35PDB1V0

176 IO35NDB1V0

208-Pin PQFP*

Pin Number A3PE1500 Function

177 IO31PDB0V3

178 GND

179 IO31NDB0V3

180 IO29PDB0V3

181 IO29NDB0V3

182 IO27PDB0V3

183 IO27NDB0V3

184 IO23PDB0V2

185 IO23NDB0V2

186 VCCIB0

187 VCC

188 IO18PDB0V2

189 IO18NDB0V2

190 IO15PDB0V1

191 IO15NDB0V1

192 IO12PSB0V1

193 IO11PDB0V1

194 IO11NDB0V1

195 GND

196 IO08PDB0V1

197 IO08NDB0V1

198 IO05PDB0V0

199 IO05NDB0V0

200 VCCIB0

201 GAC1/IO02PDB0V0

202 GAC0/IO02NDB0V0

203 GAB1/IO01PDB0V0

204 GAB0/IO01NDB0V0

205 GAA1/IO00PDB0V0

206 GAA0/IO00NDB0V0

207 GNDQ

208 VMV0

208-Pin PQFP*

Pin Number A3PE1500 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3E Flash Family FPGAs

4-6 v2.0

208-Pin PQFP*

Pin Number A3PE3000 Function

1GND

2 GNDQ

3VMV7

4 GAB2/IO303PSB7V3

5 GAA2/IO304PDB7V3

6 IO304NDB7V3

7 GAC2/IO302PDB7V3

8 IO302NDB7V3

9 IO298PDB7V3

10 IO298NDB7V3

11 IO294PDB7V2

12 IO294NDB7V2

13 IO290PDB7V2

14 IO290NDB7V2

15 IO286PSB7V1

16 VCC

17 GND

18 VCCIB7

19 IO282PDB7V1

20 IO282NDB7V1

21 IO278PSB7V0

22 GFC1/IO274PSB7V0

23 GFB1/IO273PDB7V0

24 GFB0/IO273NDB7V0

25 VCOMPLF

26 GFA0/IO272NPB6V4

27 VCCPLF

28 GFA1/IO272PPB6V4

29 GND

30 GFA2/IO271PDB6V4

31 IO271NDB6V4

32 GFB2/IO270PPB6V4

33 GFC2/IO269PPB6V4

34 IO270NPB6V4

35 IO269NPB6V4

36 VCC

37 IO250PDB6V2

38 IO250NDB6V2

39 IO246PSB6V1

40 VCCIB6

41 GND

42 IO242PDB6V1

43 IO242NDB6V1

44 GEC1/IO234PPB6V0

45 GEB1/IO233PPB6V0

46 GEC0/IO234NPB6V0

47 GEB0/IO233NPB6V0

48 GEA1/IO232PDB6V0

49 GEA0/IO232NDB6V0

50 VMV6

51 GNDQ

52 GND

53 VMV5

54 GNDQ

55 IO231NDB5V4

56 GEA2/IO231PDB5V4

57 IO230NDB5V4

58 GEB2/IO230PDB5V4

59 IO229NDB5V4

60 GEC2/IO229PDB5V4

61 IO228PSB5V4

62 VCCIB5

63 IO216NDB5V3

64 IO216PDB5V3

65 GND

66 IO212PSB5V2

67 IO210NDB5V2

68 IO210PDB5V2

69 IO206NDB5V1

70 IO206PDB5V1

71 VCC

72 VCCIB5

208-Pin PQFP*

Pin Number A3PE3000 Function

73 IO200NDB5V1

74 IO200PDB5V1

75 IO196NDB5V0

76 IO196PDB5V0

77 IO195NDB5V0

78 IO195PDB5V0

79 IO192NDB5V0

80 IO192PDB5V0

81 GND

82 IO182NDB4V3

83 IO182PDB4V3

84 IO178NDB4V3

85 IO178PDB4V3

86 IO174NDB4V2

87 IO174PDB4V2

88 VCC

89 VCCIB4

90 IO168NDB4V2

91 IO168PDB4V2

92 IO164NDB4V1

93 IO164PDB4V1

94 IO154NDB4V0

95 GDC2/IO154PDB4V0

96 IO153NDB4V0

97 GND

98 GDB2/IO153PDB4V0

99 GDA2/IO152PSB4V0

100 GNDQ

101 TCK

102 TDI

103 TMS

104 VMV4

105 GND

106 VPUMP

107 GNDQ

108 TDO

208-Pin PQFP*

Pin Number A3PE3000 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3E Flash Family FPGAs

v2.0 4-7

109 TRST

110 VJTAG

111 VMV3

112 GDA0/IO151NPB3V4

113 GDB0/IO150NPB3V4

114 GDA1/IO151PPB3V4

115 GDB1/IO150PPB3V4

116 GDC0/IO149NDB3V4

117 GDC1/IO149PDB3V4

118 IO146NDB3V4

119 IO146PDB3V4

120 IO142NDB3V3

121 IO142PDB3V3

122 GND

123 VCCIB3

124 GCC2/IO117PSB3V0

125 GCB2/IO116PSB3V0

126 NC

127 IO115NDB3V0

128 GCA2/IO115PDB3V0

129 GCA1/IO114PPB3V0

130 GND

131 VCCPLC

132 GCA0/IO114NPB3V0

133 VCOMPLC

134 GCB0/IO113NDB2V3

135 GCB1/IO113PDB2V3

136 GCC1/IO112PSB2V3

137 IO110NDB2V3

138 IO110PDB2V3

139 IO106PSB2V3

140 VCCIB2

141 GND

142 VCC

208-Pin PQFP*

Pin Number A3PE3000 Function

143 IO99NDB2V2

144 IO99PDB2V2

145 IO96NDB2V1

146 IO96PDB2V1

147 IO91NDB2V1

148 IO91PDB2V1

149 IO88NDB2V0

150 IO88PDB2V0

151 GBC2/IO84PSB2V0

152 GBA2/IO82PSB2V0

153 GBB2/IO83PSB2V0

154 VMV2

155 GNDQ

156 GND

157 VMV1

158 GNDQ

159 GBA1/IO81PDB1V4

160 GBA0/IO81NDB1V4

161 GBB1/IO80PDB1V4

162 GND

163 GBB0/IO80NDB1V4

164 GBC1/IO79PDB1V4

165 GBC0/IO79NDB1V4

166 IO74PDB1V4

167 IO74NDB1V4

168 IO70PDB1V3

169 IO70NDB1V3

170 VCCIB1

171 VCC

172 IO67PSB1V3

173 IO66PDB1V3

174 IO66NDB1V3

175 IO63PDB1V2

176 IO63NDB1V2

208-Pin PQFP*

Pin Number A3PE3000 Function

177 IO40PDB0V4

178 GND

179 IO40NDB0V4

180 IO37PDB0V4

181 IO37NDB0V4

182 IO35PDB0V4

183 IO35NDB0V4

184 IO32PDB0V3

185 IO32NDB0V3

186 VCCIB0

187 VCC

188 IO28PDB0V3

189 IO28NDB0V3

190 IO24PDB0V2

191 IO24NDB0V2

192 IO21PSB0V2

193 IO16PDB0V1

194 IO16NDB0V1

195 GND

196 IO11PDB0V1

197 IO11NDB0V1

198 IO08PDB0V0

199 IO08NDB0V0

200 VCCIB0

201 GAC1/IO02PDB0V0

202 GAC0/IO02NDB0V0

203 GAB1/IO01PDB0V0

204 GAB0/IO01NDB0V0

205 GAA1/IO00PDB0V0

206 GAA0/IO00NDB0V0

207 GNDQ

208 VMV0

208-Pin PQFP*

Pin Number A3PE3000 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3E Flash Family FPGAs

4-8 v2.0

256-Pin FBGA

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.actel.com/products/solutions/package/docs.aspx.

Note: This is the bottom view of the package.

791113

15 246

101214

A1 Ball Pad Corner

ProASIC3E Flash Family FPGAs

v2.0 4-9

256-Pin FBGA*

Pin Number A3PE600 Function

A1 GND

A2 GAA0/IO00NDB0V0

A3 GAA1/IO00PDB0V0

A4 GAB0/IO01NDB0V0

A5 IO05PDB0V0

A6 IO10PDB0V1

A7 IO12PDB0V2

A8 IO16NDB0V2

A9 IO23NDB1V0

A10 IO23PDB1V0

A11 IO28NDB1V1

A12 IO28PDB1V1

A13 GBB1/IO34PDB1V1

A14 GBA0/IO35NDB1V1

A15 GBA1/IO35PDB1V1

A16 GND

B1 GAB2/IO133PDB7V1

B2 GAA2/IO134PDB7V1

B3 GNDQ

B4 GAB1/IO01PDB0V0

B5 IO05NDB0V0

B6 IO10NDB0V1

B7 IO12NDB0V2

B8 IO16PDB0V2

B9 IO20NDB1V0

B10 IO24NDB1V0

B11 IO24PDB1V0

B12 GBC1/IO33PDB1V1

B13 GBB0/IO34NDB1V1

B14 GNDQ

B15 GBA2/IO36PDB2V0

B16 IO42NDB2V0

C1 IO133NDB7V1

C2 IO134NDB7V1

C3 VMV7

C4 VCCPLA

C5 GAC0/IO02NDB0V0

C6 GAC1/IO02PDB0V0

C7 IO15NDB0V2

C8 IO15PDB0V2

C9 IO20PDB1V0

C10 IO25NDB1V0

C11 IO27PDB1V0

C12 GBC0/IO33NDB1V1

C13 VCCPLB

C14 VMV2

C15 IO36NDB2V0

C16 IO42PDB2V0

D1 IO128PDB7V1

D2 IO129PDB7V1

D3 GAC2/IO132PDB7V1

D4 VCOMPLA

D5 GNDQ

D6 IO09NDB0V1

D7 IO09PDB0V1

D8 IO13PDB0V2

D9 IO21PDB1V0

D10 IO25PDB1V0

D11 IO27NDB1V0

D12 GNDQ

D13 VCOMPLB

D14 GBB2/IO37PDB2V0

D15 IO39PDB2V0

D16 IO39NDB2V0

E1 IO128NDB7V1

E2 IO129NDB7V1

E3 IO132NDB7V1

E4 IO130PDB7V1

E5 VMV0

E6 VCCIB0

E7 VCCIB0

E8 IO13NDB0V2

E9 IO21NDB1V0

E10 VCCIB1

256-Pin FBGA*

Pin Number A3PE600 Function

E11 VCCIB1

E12 VMV1

E13 GBC2/IO38PDB2V0

E14 IO37NDB2V0

E15 IO41NDB2V0

E16 IO41PDB2V0

F1 IO124PDB7V0

F2 IO125PDB7V0

F3 IO126PDB7V0

F4 IO130NDB7V1

F5 VCCIB7

F6 GND

F7 VCC

F8 VCC

F9 VCC

F10 VCC

F11 GND

F12 VCCIB2

F13 IO38NDB2V0

F14 IO40NDB2V0

F15 IO40PDB2V0

F16 IO45PSB2V1

G1 IO124NDB7V0

G2 IO125NDB7V0

G3 IO126NDB7V0

G4 GFC1/IO120PPB7V0

G5 VCCIB7

G6 VCC

G7 GND

G8 GND

G9 GND

G10 GND

G11 VCC

G12 VCCIB2

G13 GCC1/IO50PPB2V1

G14 IO44NDB2V1

G15 IO44PDB2V1

256-Pin FBGA*

Pin Number A3PE600 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3E Flash Family FPGAs

4-10 v2.0

G16 IO49NSB2V1

H1 GFB0/IO119NPB7V0

H2 GFA0/IO118NDB6V1

H3 GFB1/IO119PPB7V0

H4 VCOMPLF

H5 GFC0/IO120NPB7V0

H6 VCC

H7 GND

H8 GND

H9 GND

H10 GND

H11 VCC

H12 GCC0/IO50NPB2V1

H13 GCB1/IO51PPB2V1

H14 GCA0/IO52NPB3V0

H15 VCOMPLC

H16 GCB0/IO51NPB2V1

J1 GFA2/IO117PSB6V1

J2 GFA1/IO118PDB6V1

J3 VCCPLF

J4 IO116NDB6V1

J5 GFB2/IO116PDB6V1

J6 VCC

J7 GND

J8 GND

J9 GND

J10 GND

J11 VCC

J12 GCB2/IO54PPB3V0

J13 GCA1/IO52PPB3V0

J14 GCC2/IO55PPB3V0

J15 VCCPLC

J16 GCA2/IO53PSB3V0

K1 GFC2/IO115PSB6V1

K2 IO113PPB6V1

K3 IO112PDB6V1

K4 IO112NDB6V1

256-Pin FBGA*

Pin Number A3PE600 Function

K5 VCCIB6

K6 VCC

K7 GND

K8 GND

K9 GND

K10 GND

K11 VCC

K12 VCCIB3

K13 IO54NPB3V0

K14 IO57NPB3V0

K15 IO55NPB3V0

K16 IO57PPB3V0

L1 IO113NPB6V1

L2 IO109PPB6V0

L3 IO108PDB6V0

L4 IO108NDB6V0

L5 VCCIB6

L6 GND

L7 VCC

L8 VCC

L9 VCC

L10 VCC

L11 GND

L12 VCCIB3

L13 GDB0/IO66NPB3V1

L14 IO60NDB3V1

L15 IO60PDB3V1

L16 IO61PDB3V1

M1 IO109NPB6V0

M2 IO106NDB6V0

M3 IO106PDB6V0

M4 GEC0/IO104NPB6V0

M5 VMV5

M6 VCCIB5

M7 VCCIB5

M8 IO84NDB5V0

M9 IO84PDB5V0

256-Pin FBGA*

Pin Number A3PE600 Function

M10 VCCIB4

M11 VCCIB4

M12 VMV3

M13 VCCPLD

M14 GDB1/IO66PPB3V1

M15 GDC1/IO65PDB3V1

M16 IO61NDB3V1

N1 IO105PDB6V0

N2 IO105NDB6V0

N3 GEC1/IO104PPB6V0

N4 VCOMPLE

N5 GNDQ

N6 GEA2/IO101PPB5V2

N7 IO92NDB5V1

N8 IO90NDB5V1

N9 IO82NDB5V0

N10 IO74NDB4V1

N11 IO74PDB4V1

N12 GNDQ

N13 VCOMPLD

N14 VJTAG

N15 GDC0/IO65NDB3V1

N16 GDA1/IO67PDB3V1

P1 GEB1/IO103PDB6V0

P2 GEB0/IO103NDB6V0

P3 VMV6

P4 VCCPLE

P5 IO101NPB5V2

P6 IO95PPB5V1

P7 IO92PDB5V1

P8 IO90PDB5V1

P9 IO82PDB5V0

P10 IO76NDB4V1

P11 IO76PDB4V1

P12 VMV4

P13 TCK

P14 VPUMP

256-Pin FBGA*

Pin Number A3PE600 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3E Flash Family FPGAs

v2.0 4-11

P15 TRST

P16 GDA0/IO67NDB3V1

R1 GEA1/IO102PDB6V0

R2 GEA0/IO102NDB6V0

R3 GNDQ

R4 GEC2/IO99PDB5V2

R5 IO95NPB5V1

R6 IO91NDB5V1

R7 IO91PDB5V1

R8 IO83NDB5V0

R9 IO83PDB5V0

R10 IO77NDB4V1

256-Pin FBGA*

Pin Number A3PE600 Function

R11 IO77PDB4V1

R12 IO69NDB4V0

R13 GDB2/IO69PDB4V0

R14 TDI

R15 GNDQ

R16 TDO

T1 GND

T2 IO100NDB5V2

T3 GEB2/IO100PDB5V2

T4 IO99NDB5V2

T5 IO88NDB5V0

T6 IO88PDB5V0

256-Pin FBGA*

Pin Number A3PE600 Function

T7 IO89NSB5V0

T8 IO80NSB4V1

T9 IO81NDB4V1

T10 IO81PDB4V1

T11 IO70NDB4V0

T12 GDC2/IO70PDB4V0

T13 IO68NDB4V0

T14 GDA2/IO68PDB4V0

T15 TMS

T16 GND

256-Pin FBGA*

Pin Number A3PE600 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3E Flash Family FPGAs

4-12 v2.0

484-Pin FBGA

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.actel.com/products/solutions/package/docs.aspx.

This is the bottom view of the package.

12345678910111213141516171819202122

A1 Ball Pad Corner

ProASIC3E Flash Family FPGAs

v2.0 4-13

484-Pin FBGA*

Pin Number A3PE600 Function

A1 GND

A2 GND

A3 VCCIB0

A4 IO06NDB0V1

A5 IO06PDB0V1

A6 IO08NDB0V1

A7 IO08PDB0V1

A8 IO11PDB0V1

A9 IO17PDB0V2

A10 IO18NDB0V2

A11 IO18PDB0V2

A12 IO22PDB1V0

A13 IO26PDB1V0

A14 IO29NDB1V1

A15 IO29PDB1V1

A16 IO31NDB1V1

A17 IO31PDB1V1

A18 IO32NDB1V1

A19 NC

A20 VCCIB1

A21 GND

A22 GND

B1 GND

B2 VCCIB7

B3 NC

B4 IO03NDB0V0

B5 IO03PDB0V0

B6 IO07NDB0V1

B7 IO07PDB0V1

B8 IO11NDB0V1

B9 IO17NDB0V2

B10 IO14PDB0V2

B11 IO19PDB0V2

B12 IO22NDB1V0

B13 IO26NDB1V0

B14 NC

B15 NC

B16 IO30NDB1V1

B17 IO30PDB1V1

B18 IO32PDB1V1

B19 NC

B20 NC

B21 VCCIB2

B22 GND

C1 VCCIB7

C2 NC

C3 NC

C4 NC

C5 GND

C6 IO04NDB0V0

C7 IO04PDB0V0

C8 VCC

C9 VCC

C10 IO14NDB0V2

C11 IO19NDB0V2

C12 NC

C13 NC

C14 VCC

C15 VCC

C16 NC

C17 NC

C18 GND

C19 NC

C20 NC

C21 NC

C22 VCCIB2

D1 NC

D2 NC

D3 NC

D4 GND

D5 GAA0/IO00NDB0V0

D6 GAA1/IO00PDB0V0

484-Pin FBGA*

Pin Number A3PE600 Function

D7 GAB0/IO01NDB0V0

D8 IO05PDB0V0

D9 IO10PDB0V1

D10 IO12PDB0V2

D11 IO16NDB0V2

D12 IO23NDB1V0

D13 IO23PDB1V0

D14 IO28NDB1V1

D15 IO28PDB1V1

D16 GBB1/IO34PDB1V1

D17 GBA0/IO35NDB1V1

D18 GBA1/IO35PDB1V1

D19 GND

D20 NC

D21 NC

D22 NC

E1 NC

E2 NC

E3 GND

E4 GAB2/IO133PDB7V1

E5 GAA2/IO134PDB7V1

E6 GNDQ

E7 GAB1/IO01PDB0V0

E8 IO05NDB0V0

E9 IO10NDB0V1

E10 IO12NDB0V2

E11 IO16PDB0V2

E12 IO20NDB1V0

E13 IO24NDB1V0

E14 IO24PDB1V0

E15 GBC1/IO33PDB1V1

E16 GBB0/IO34NDB1V1

E17 GNDQ

E18 GBA2/IO36PDB2V0

E19 IO42NDB2V0

E20 GND

484-Pin FBGA*

Pin Number A3PE600 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3E Flash Family FPGAs

4-14 v2.0

E21 NC

E22 NC

F1 NC

F2 IO131NDB7V1

F3 IO131PDB7V1

F4 IO133NDB7V1

F5 IO134NDB7V1

F6 VMV7

F7 VCCPLA

F8 GAC0/IO02NDB0V0

F9 GAC1/IO02PDB0V0

F10 IO15NDB0V2

F11 IO15PDB0V2

F12 IO20PDB1V0

F13 IO25NDB1V0

F14 IO27PDB1V0

F15 GBC0/IO33NDB1V1

F16 VCCPLB

F17 VMV2

F18 IO36NDB2V0

F19 IO42PDB2V0

F20 NC

F21 NC

F22 NC

G1 IO127NDB7V1

G2 IO127PDB7V1

G3 NC

G4 IO128PDB7V1

G5 IO129PDB7V1

G6 GAC2/IO132PDB7V1

G7 VCOMPLA

G8 GNDQ

G9 IO09NDB0V1

G10 IO09PDB0V1

G11 IO13PDB0V2

G12 IO21PDB1V0

484-Pin FBGA*

Pin Number A3PE600 Function

G13 IO25PDB1V0

G14 IO27NDB1V0

G15 GNDQ

G16 VCOMPLB

G17 GBB2/IO37PDB2V0

G18 IO39PDB2V0

G19 IO39NDB2V0

G20 IO43PDB2V0

G21 IO43NDB2V0

G22 NC

H1 NC

H2 NC

H3 VCC

H4 IO128NDB7V1

H5 IO129NDB7V1

H6 IO132NDB7V1

H7 IO130PDB7V1

H8 VMV0

H9 VCCIB0

H10 VCCIB0

H11 IO13NDB0V2

H12 IO21NDB1V0

H13 VCCIB1

H14 VCCIB1

H15 VMV1

H16 GBC2/IO38PDB2V0

H17 IO37NDB2V0

H18 IO41NDB2V0

H19 IO41PDB2V0

H20 VCC

H21 NC

H22 NC

J1 IO123NDB7V0

J2 IO123PDB7V0

J3 NC

J4 IO124PDB7V0

484-Pin FBGA*

Pin Number A3PE600 Function

J5 IO125PDB7V0

J6 IO126PDB7V0

J7 IO130NDB7V1

J8 VCCIB7

J9 GND

J10 VCC

J11 VCC

J12 VCC

J13 VCC

J14 GND

J15 VCCIB2

J16 IO38NDB2V0

J17 IO40NDB2V0

J18 IO40PDB2V0

J19 IO45PDB2V1

J20 NC

J21 IO48PDB2V1

J22 IO46PDB2V1

K1 IO121NDB7V0

K2 IO121PDB7V0

K3 NC

K4 IO124NDB7V0

K5 IO125NDB7V0

K6 IO126NDB7V0

K7 GFC1/IO120PPB7V0

K8 VCCIB7

K9 VCC

K10 GND

K11 GND

K12 GND

K13 GND

K14 VCC

K15 VCCIB2

K16 GCC1/IO50PPB2V1

K17 IO44NDB2V1

K18 IO44PDB2V1

484-Pin FBGA*

Pin Number A3PE600 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3E Flash Family FPGAs

v2.0 4-15

K19 IO49NPB2V1

K20 IO45NDB2V1

K21 IO48NDB2V1

K22 IO46NDB2V1

L1 NC

L2 IO122PDB7V0

L3 IO122NDB7V0

L4 GFB0/IO119NPB7V0

L5 GFA0/IO118NDB6V1

L6 GFB1/IO119PPB7V0

L7 VCOMPLF

L8 GFC0/IO120NPB7V0

L9 VCC

L10 GND

L11 GND

L12 GND

L13 GND

L14 VCC

L15 GCC0/IO50NPB2V1

L16 GCB1/IO51PPB2V1

L17 GCA0/IO52NPB3V0

L18 VCOMPLC

L19 GCB0/IO51NPB2V1

L20 IO49PPB2V1

L21 IO47NDB2V1

L22 IO47PDB2V1

M1 NC

M2 IO114NDB6V1

M3 IO117NDB6V1

M4 GFA2/IO117PDB6V1

M5 GFA1/IO118PDB6V1

M6 VCCPLF

M7 IO116NDB6V1

M8 GFB2/IO116PDB6V1

M9 VCC

M10 GND

484-Pin FBGA*

Pin Number A3PE600 Function

M11 GND

M12 GND

M13 GND

M14 VCC

M15 GCB2/IO54PPB3V0

M16 GCA1/IO52PPB3V0

M17 GCC2/IO55PPB3V0

M18 VCCPLC

M19 GCA2/IO53PDB3V0

M20 IO53NDB3V0

M21 IO56PDB3V0

M22 NC

N1 IO114PDB6V1

N2 IO111NDB6V1

N3 NC

N4 GFC2/IO115PDB6V1

N5 IO113PPB6V1

N6 IO112PDB6V1

N7 IO112NDB6V1

N8 VCCIB6

N9 VCC

N10 GND

N11 GND

N12 GND

N13 GND

N14 VCC

N15 VCCIB3

N16 IO54NPB3V0

N17 IO57NPB3V0

N18 IO55NPB3V0

N19 IO57PPB3V0

N20 NC

N21 IO56NDB3V0

N22 IO58PDB3V0

P1 NC

P2 IO111PDB6V1

484-Pin FBGA*

Pin Number A3PE600 Function

P3 IO115NDB6V1

P4 IO113NPB6V1

P5 IO109PPB6V0

P6 IO108PDB6V0

P7 IO108NDB6V0

P8 VCCIB6

P9 GND

P10 VCC

P11 VCC

P12 VCC

P13 VCC

P14 GND

P15 VCCIB3

P16 GDB0/IO66NPB3V1

P17 IO60NDB3V1

P18 IO60PDB3V1

P19 IO61PDB3V1

P20 NC

P21 IO59PDB3V0

P22 IO58NDB3V0

R1 NC

R2 IO110PDB6V0

R3 VCC

R4 IO109NPB6V0

R5 IO106NDB6V0

R6 IO106PDB6V0

R7 GEC0/IO104NPB6V0

R8 VMV5

R9 VCCIB5

R10 VCCIB5

R11 IO84NDB5V0

R12 IO84PDB5V0

R13 VCCIB4

R14 VCCIB4

R15 VMV3

R16 VCCPLD

484-Pin FBGA*

Pin Number A3PE600 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3E Flash Family FPGAs

4-16 v2.0

R17 GDB1/IO66PPB3V1

R18 GDC1/IO65PDB3V1

R19 IO61NDB3V1

R20 VCC

R21 IO59NDB3V0

R22 IO62PDB3V1

T1 NC

T2 IO110NDB6V0

T3 NC

T4 IO105PDB6V0

T5 IO105NDB6V0

T6 GEC1/IO104PPB6V0

T7 VCOMPLE

T8 GNDQ

T9 GEA2/IO101PPB5V2

T10 IO92NDB5V1

T11 IO90NDB5V1

T12 IO82NDB5V0

T13 IO74NDB4V1

T14 IO74PDB4V1

T15 GNDQ

T16 VCOMPLD

T17 VJTAG

T18 GDC0/IO65NDB3V1

T19 GDA1/IO67PDB3V1

T20 NC

T21 IO64PDB3V1

T22 IO62NDB3V1

U1 NC

U2 IO107PDB6V0

U3 IO107NDB6V0

U4 GEB1/IO103PDB6V0

U5 GEB0/IO103NDB6V0

U6 VMV6

U7 VCCPLE

U8 IO101NPB5V2

484-Pin FBGA*

Pin Number A3PE600 Function

U9 IO95PPB5V1

U10 IO92PDB5V1

U11 IO90PDB5V1

U12 IO82PDB5V0

U13 IO76NDB4V1

U14 IO76PDB4V1

U15 VMV4

U16 TCK

U17 VPUMP

U18 TRST

U19 GDA0/IO67NDB3V1

U20 NC

U21 IO64NDB3V1

U22 IO63PDB3V1

V1 NC

V2 NC

V3 GND

V4 GEA1/IO102PDB6V0

V5 GEA0/IO102NDB6V0

V6 GNDQ

V7 GEC2/IO99PDB5V2

V8 IO95NPB5V1

V9 IO91NDB5V1

V10 IO91PDB5V1

V11 IO83NDB5V0

V12 IO83PDB5V0

V13 IO77NDB4V1

V14 IO77PDB4V1

V15 IO69NDB4V0

V16 GDB2/IO69PDB4V0

V17 TDI

V18 GNDQ

V19 TDO

V20 GND

V21 NC

V22 IO63NDB3V1

484-Pin FBGA*

Pin Number A3PE600 Function

W1 NC

W2 NC

W3 NC

W4 GND

W5 IO100NDB5V2

W6 GEB2/IO100PDB5V2

W7 IO99NDB5V2

W8 IO88NDB5V0

W9 IO88PDB5V0

W10 IO89NDB5V0

W11 IO80NDB4V1

W12 IO81NDB4V1

W13 IO81PDB4V1

W14 IO70NDB4V0

W15 GDC2/IO70PDB4V0

W16 IO68NDB4V0

W17 GDA2/IO68PDB4V0

W18 TMS

W19 GND

W20 NC

W21 NC

W22 NC

Y1 VCCIB6

Y2 NC

Y3 NC

Y4 IO98NDB5V2

Y5 GND

Y6 IO94NDB5V1

Y7 IO94PDB5V1

Y8 VCC

Y9 VCC

Y10 IO89PDB5V0

Y11 IO80PDB4V1

Y12 IO78NPB4V1

Y13 NC

Y14 VCC

484-Pin FBGA*

Pin Number A3PE600 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3E Flash Family FPGAs

v2.0 4-17

Y15 VCC

Y16 NC

Y17 NC

Y18 GND

Y19 NC

Y20 NC

Y21 NC

Y22 VCCIB3

AA1 GND

AA2 VCCIB6

AA3 NC

AA4 IO98PDB5V2

AA5 IO96NDB5V2

AA6 IO96PDB5V2

AA7 IO86NDB5V0

AA8 IO86PDB5V0

AA9 IO85PDB5V0

AA10 IO85NDB5V0

484-Pin FBGA*

Pin Number A3PE600 Function

AA11 IO78PPB4V1

AA12 IO79NDB4V1

AA13 IO79PDB4V1

AA14 NC

AA15 NC

AA16 IO71NDB4V0

AA17 IO71PDB4V0

AA18 NC

AA19 NC

AA20 NC

AA21 VCCIB3

AA22 GND

AB1 GND

AB2 GND

AB3 VCCIB5

AB4 IO97NDB5V2

AB5 IO97PDB5V2

AB6 IO93NDB5V1

484-Pin FBGA*

Pin Number A3PE600 Function

AB7 IO93PDB5V1

AB8 IO87NDB5V0

AB9 IO87PDB5V0

AB10 NC

AB11 NC

AB12 IO75NDB4V1

AB13 IO75PDB4V1

AB14 IO72NDB4V0

AB15 IO72PDB4V0

AB16 IO73NDB4V0

AB17 IO73PDB4V0

AB18 NC

AB19 NC

AB20 VCCIB4

AB21 GND

AB22 GND

484-Pin FBGA*

Pin Number A3PE600 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3E Flash Family FPGAs

4-18 v2.0

484-Pin FBGA*

Pin Number A3PE1500 Function

A1 GND

A2 GND

A3 VCCIB0

A4 IO05NDB0V0

A5 IO05PDB0V0

A6 IO11NDB0V1

A7 IO11PDB0V1

A8 IO15PDB0V1

A9 IO17PDB0V2

A10 IO27NDB0V3

A11 IO27PDB0V3

A12 IO32PDB1V0

A13 IO43PDB1V1

A14 IO47NDB1V1

A15 IO47PDB1V1

A16 IO51NDB1V2

A17 IO51PDB1V2

A18 IO54NDB1V3

A19 NC

A20 VCCIB1

A21 GND

A22 GND

AA1 GND

AA2 VCCIB6

AA3 NC

AA4 IO161PDB5V3

AA5 IO155NDB5V2

AA6 IO155PDB5V2

AA7 IO154NDB5V2

AA8 IO154PDB5V2

AA9 IO143PDB5V1

AA10 IO143NDB5V1

AA11 IO131PPB4V2

AA12 IO129NDB4V2

AA13 IO129PDB4V2

AA14 NC

AA15 NC

AA16 IO117NDB4V0

AA17 IO117PDB4V0

AA18 IO115NDB4V0

AA19 IO115PDB4V0

AA20 NC

AA21 VCCIB3

AA22 GND

AB1 GND

AB2 GND

AB3 VCCIB5

AB4 IO159NDB5V3

AB5 IO159PDB5V3

AB6 IO149NDB5V1

AB7 IO149PDB5V1

AB8 IO138NDB5V0

AB9 IO138PDB5V0

AB10 NC

AB11 NC

AB12 IO127NDB4V2

AB13 IO127PDB4V2

AB14 IO125NDB4V1

AB15 IO125PDB4V1

AB16 IO122NDB4V1

AB17 IO122PDB4V1

AB18 NC

AB19 NC

AB20 VCCIB4

AB21 GND

AB22 GND

B1 GND

B2 VCCIB7

B3 NC

B4 IO03NDB0V0

B5 IO03PDB0V0

B6 IO10NDB0V1

484-Pin FBGA*

Pin Number A3PE1500 Function

B7 IO10PDB0V1

B8 IO15NDB0V1

B9 IO17NDB0V2

B10 IO20PDB0V2

B11 IO29PDB0V3

B12 IO32NDB1V0

B13 IO43NDB1V1

B14 NC

B15 NC

B16 IO53NDB1V2

B17 IO53PDB1V2

B18 IO54PDB1V3

B19 NC

B20 NC

B21 VCCIB2

B22 GND

C1 VCCIB7

C2 NC

C3 NC

C4 NC

C5 GND

C6 IO07NDB0V0

C7 IO07PDB0V0

C8 VCC

C9 VCC

C10 IO20NDB0V2

C11 IO29NDB0V3

C12 NC

C13 NC

C14 VCC

C15 VCC

C16 NC

C17 NC

C18 GND

C19 NC

C20 NC

484-Pin FBGA*

Pin Number A3PE1500 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3E Flash Family FPGAs

v2.0 4-19

C21 NC

C22 VCCIB2

D1 NC

D2 NC

D3 NC

D4 GND

D5 GAA0/IO00NDB0V0

D6 GAA1/IO00PDB0V0

D7 GAB0/IO01NDB0V0

D8 IO09PDB0V1

D9 IO13PDB0V1

D10 IO21PDB0V2

D11 IO31NDB0V3

D12 IO37NDB1V0

D13 IO37PDB1V0

D14 IO49NDB1V2

D15 IO49PDB1V2

D16 GBB1/IO56PDB1V3

D17 GBA0/IO57NDB1V3

D18 GBA1/IO57PDB1V3

D19 GND

D20 NC

D21 IO69PDB2V1

D22 NC

E1 NC

E2 IO218PPB7V3

E3 GND

E4 GAB2/IO220PDB7V3

E5 GAA2/IO221PDB7V3

E6 GNDQ

E7 GAB1/IO01PDB0V0

E8 IO09NDB0V1

E9 IO13NDB0V1

E10 IO21NDB0V2

E11 IO31PDB0V3

E12 IO35NDB1V0

484-Pin FBGA*

Pin Number A3PE1500 Function

E13 IO41NDB1V1

E14 IO41PDB1V1

E15 GBC1/IO55PDB1V3

E16 GBB0/IO56NDB1V3

E17 GNDQ

E18 GBA2/IO58PDB2V0

E19 IO63NDB2V0

E20 GND

E21 IO69NDB2V1

E22 NC

F1 IO218NPB7V3

F2 IO216NDB7V3

F3 IO216PDB7V3

F4 IO220NDB7V3

F5 IO221NDB7V3

F6 VMV7

F7 VCCPLA

F8 GAC0/IO02NDB0V0

F9 GAC1/IO02PDB0V0

F10 IO23NDB0V2

F11 IO23PDB0V2

F12 IO35PDB1V0

F13 IO39NDB1V0

F14 IO45PDB1V1

F15 GBC0/IO55NDB1V3

F16 VCCPLB

F17 VMV2

F18 IO58NDB2V0

F19 IO63PDB2V0

F20 NC

F21 NC

F22 NC

G1 IO211NDB7V2

G2 IO211PDB7V2

G3 NC

G4 IO214PDB7V3

484-Pin FBGA*

Pin Number A3PE1500 Function

G5 IO217PDB7V3

G6 GAC2/IO219PDB7V3

G7 VCOMPLA

G8 GNDQ

G9 IO19NDB0V2

G10 IO19PDB0V2

G11 IO25PDB0V3

G12 IO33PDB1V0

G13 IO39PDB1V0

G14 IO45NDB1V1

G15 GNDQ

G16 VCOMPLB

G17 GBB2/IO59PDB2V0

G18 IO62PDB2V0

G19 IO62NDB2V0

G20 IO71PDB2V2

G21 IO71NDB2V2

G22 NC

H1 IO209PSB7V2

H2 NC

H3 VCC

H4 IO214NDB7V3

H5 IO217NDB7V3

H6 IO219NDB7V3

H7 IO215PDB7V3

H8 VMV0

H9 VCCIB0

H10 VCCIB0

H11 IO25NDB0V3

H12 IO33NDB1V0

H13 VCCIB1

H14 VCCIB1

H15 VMV1

H16 GBC2/IO60PDB2V0

H17 IO59NDB2V0

H18 IO67NDB2V1

484-Pin FBGA*

Pin Number A3PE1500 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3E Flash Family FPGAs

4-20 v2.0

H19 IO67PDB2V1

H20 VCC

H21 VMV2

H22 IO74PSB2V2

J1 IO212NDB7V2

J2 IO212PDB7V2

J3 VMV7

J4 IO206PDB7V1

J5 IO204PDB7V1

J6 IO210PDB7V2

J7 IO215NDB7V3

J8 VCCIB7

J9 GND

J10 VCC

J11 VCC

J12 VCC

J13 VCC

J14 GND

J15 VCCIB2

J16 IO60NDB2V0

J17 IO65NDB2V1

J18 IO65PDB2V1

J19 IO75PPB2V2

J20 GNDQ

J21 IO77PDB2V2

J22 IO79PDB2V3

K1 IO200NDB7V1

K2 IO200PDB7V1

K3 GNDQ

K4 IO206NDB7V1

K5 IO204NDB7V1

K6 IO210NDB7V2

K7 GFC1/IO192PPB7V0

K8 VCCIB7

K9 VCC

K10 GND

484-Pin FBGA*

Pin Number A3PE1500 Function

K11 GND

K12 GND

K13 GND

K14 VCC

K15 VCCIB2

K16 GCC1/IO85PPB2V3

K17 IO73NDB2V2

K18 IO73PDB2V2

K19 IO81NPB2V3

K20 IO75NPB2V2

K21 IO77NDB2V2

K22 IO79NDB2V3

L1 NC

L2 IO196PDB7V0

L3 IO196NDB7V0

L4 GFB0/IO191NPB7V0

L5 GFA0/IO190NDB6V2

L6 GFB1/IO191PPB7V0

L7 VCOMPLF

L8 GFC0/IO192NPB7V0

L9 VCC

L10 GND

L11 GND

L12 GND

L13 GND

L14 VCC

L15 GCC0/IO85NPB2V3

L16 GCB1/IO86PPB2V3

L17 GCA0/IO87NPB3V0

L18 VCOMPLC

L19 GCB0/IO86NPB2V3

L20 IO81PPB2V3

L21 IO83NDB2V3

L22 IO83PDB2V3

M1 GNDQ

M2 IO185NPB6V2

484-Pin FBGA*

Pin Number A3PE1500 Function

M3 IO189NDB6V2

M4 GFA2/IO189PDB6V2

M5 GFA1/IO190PDB6V2

M6 VCCPLF

M7 IO188NDB6V2

M8 GFB2/IO188PDB6V2

M9 VCC

M10 GND

M11 GND

M12 GND

M13 GND

M14 VCC

M15 GCB2/IO89PPB3V0

M16 GCA1/IO87PPB3V0

M17 GCC2/IO90PPB3V0

M18 VCCPLC

M19 GCA2/IO88PDB3V0

M20 IO88NDB3V0

M21 IO93PDB3V0

M22 NC

N1 IO185PPB6V2

N2 IO183NDB6V2

N3 VMV6

N4 GFC2/IO187PPB6V2

N5 IO184PPB6V2

N6 IO186PDB6V2

N7 IO186NDB6V2

N8 VCCIB6

N9 VCC

N10 GND

N11 GND

N12 GND

N13 GND

N14 VCC

N15 VCCIB3

N16 IO89NPB3V0

484-Pin FBGA*

Pin Number A3PE1500 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3E Flash Family FPGAs

v2.0 4-21

N17 IO91NPB3V0

N18 IO90NPB3V0

N19 IO91PPB3V0

N20 GNDQ

N21 IO93NDB3V0

N22 IO95PDB3V1

P1 NC

P2 IO183PDB6V2

P3 IO187NPB6V2

P4 IO184NPB6V2

P5 IO176PPB6V1

P6 IO182PDB6V1

P7 IO182NDB6V1

P8 VCCIB6

P9 GND

P10 VCC

P11 VCC

P12 VCC

P13 VCC

P14 GND

P15 VCCIB3

P16 GDB0/IO109NPB3V2

P17 IO97NDB3V1

P18 IO97PDB3V1

P19 IO99PDB3V1

P20 VMV3

P21 IO98PDB3V1

P22 IO95NDB3V1

R1 NC

R2 IO177PDB6V1

R3 VCC

R4 IO176NPB6V1

R5 IO174NDB6V0

R6 IO174PDB6V0

R7 GEC0/IO169NPB6V0

R8 VMV5

484-Pin FBGA*

Pin Number A3PE1500 Function

R9 VCCIB5

R10 VCCIB5

R11 IO135NDB5V0

R12 IO135PDB5V0

R13 VCCIB4

R14 VCCIB4

R15 VMV3

R16 VCCPLD

R17 GDB1/IO109PPB3V2

R18 GDC1/IO108PDB3V2

R19 IO99NDB3V1

R20 VCC

R21 IO98NDB3V1

R22 IO101PDB3V1

T1 NC

T2 IO177NDB6V1

T3 NC

T4 IO171PDB6V0

T5 IO171NDB6V0

T6 GEC1/IO169PPB6V0

T7 VCOMPLE

T8 GNDQ

T9 GEA2/IO166PPB5V3

T10 IO145NDB5V1

T11 IO141NDB5V0

T12 IO139NDB5V0

T13 IO119NDB4V1

T14 IO119PDB4V1

T15 GNDQ

T16 VCOMPLD

T17 VJTAG

T18 GDC0/IO108NDB3V2

T19 GDA1/IO110PDB3V2

T20 NC

T21 IO103PDB3V2

T22 IO101NDB3V1

484-Pin FBGA*

Pin Number A3PE1500 Function

U1 IO175PPB6V1

U2 IO173PDB6V0

U3 IO173NDB6V0

U4 GEB1/IO168PDB6V0

U5 GEB0/IO168NDB6V0

U6 VMV6

U7 VCCPLE

U8 IO166NPB5V3

U9 IO157PPB5V2

U10 IO145PDB5V1

U11 IO141PDB5V0

U12 IO139PDB5V0

U13 IO121NDB4V1

U14 IO121PDB4V1

U15 VMV4

U16 TCK

U17 VPUMP

U18 TRST

U19 GDA0/IO110NDB3V2

U20 NC

U21 IO103NDB3V2

U22 IO105PDB3V2

V1 NC

V2 IO175NPB6V1

V3 GND

V4 GEA1/IO167PDB6V0

V5 GEA0/IO167NDB6V0

V6 GNDQ

V7 GEC2/IO164PDB5V3

V8 IO157NPB5V2

V9 IO151NDB5V2

V10 IO151PDB5V2

V11 IO137NDB5V0

V12 IO137PDB5V0

V13 IO123NDB4V1

V14 IO123PDB4V1

484-Pin FBGA*

Pin Number A3PE1500 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3E Flash Family FPGAs

4-22 v2.0

V15 IO112NDB4V0

V16 GDB2/IO112PDB4V0

V17 TDI

V18 GNDQ

V19 TDO

V20 GND

V21 NC

V22 IO105NDB3V2

W1 NC

W2 NC

W3 NC

W4 GND

W5 IO165NDB5V3

W6 GEB2/IO165PDB5V3

W7 IO164NDB5V3

W8 IO153NDB5V2

W9 IO153PDB5V2

W10 IO147NDB5V1

484-Pin FBGA*

Pin Number A3PE1500 Function

W11 IO133NDB4V2

W12 IO130NDB4V2

W13 IO130PDB4V2

W14 IO113NDB4V0

W15 GDC2/IO113PDB4V0

W16 IO111NDB4V0

W17 GDA2/IO111PDB4V0

W18 TMS

W19 GND

W20 NC

W21 NC

W22 NC

Y1 VCCIB6

Y2 NC

Y3 NC

Y4 IO161NDB5V3

Y5 GND

Y6 IO163NDB5V3

484-Pin FBGA*

Pin Number A3PE1500 Function

Y7 IO163PDB5V3

Y8 VCC

Y9 VCC

Y10 IO147PDB5V1

Y11 IO133PDB4V2

Y12 IO131NPB4V2

Y13 NC

Y14 VCC

Y15 VCC

Y16 NC

Y17 NC

Y18 GND

Y19 NC

Y20 NC

Y21 NC

Y22 VCCIB3

484-Pin FBGA*

Pin Number A3PE1500 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3E Flash Family FPGAs

v2.0 4-23

676-Pin FBGA

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.actel.com/products/solutions/package/docs.aspx.

Note: This is the bottom view of the package.

A1 Ball Pad Corner

1234567891011121314151617181920212223242526

ProASIC3E Flash Family FPGAs

4-24 v2.0

676-Pin FBGA*

Pin Number A3PE1500 Function

A1 GND

A2 GND

A3 GAA0/IO00NDB0V0

A4 GAA1/IO00PDB0V0

A5 IO06NDB0V0

A6 IO09NDB0V1

A7 IO09PDB0V1

A8 IO14NDB0V1

A9 IO14PDB0V1

A10 IO22NDB0V2

A11 IO22PDB0V2

A12 IO26NDB0V3

A13 IO26PDB0V3

A14 IO30NDB0V3

A15 IO30PDB0V3

A16 IO34NDB1V0

A17 IO34PDB1V0

A18 IO38NDB1V0

A19 IO38PDB1V0

A20 IO41PDB1V1

A21 IO44PDB1V1

A22 IO49PDB1V2

A23 IO50PDB1V2

A24 GBC1/IO55PDB1V3

A25 GND

A26 GND

AA1 IO174PDB6V0

AA2 IO171PDB6V0

AA3 GEA1/IO167PPB6V0

AA4 GEC0/IO169NPB6V0

AA5 VCOMPLE

AA6 GND

AA7 IO165NDB5V3

AA8 GEB2/IO165PDB5V3

AA9 IO163PDB5V3

AA10 IO159NDB5V3

AA11 IO153NDB5V2

AA12 IO147NDB5V1

AA13 IO139NDB5V0

AA14 IO137NDB5V0

AA15 IO123NDB4V1

AA16 IO123PDB4V1

AA17 IO117NDB4V0

AA18 IO117PDB4V0

AA19 GDB2/IO112PDB4V0

AA20 GNDQ

AA21 TDO

AA22 GND

AA23 GND

AA24 IO102NDB3V1

AA25 IO102PDB3V1

AA26 IO98NDB3V1

AB1 IO174NDB6V0

AB2 IO171NDB6V0

AB3 GEB1/IO168PPB6V0

AB4 GEA0/IO167NPB6V0

AB5 VCCPLE

AB6 GND

AB7 GND

AB8 IO156NDB5V2

AB9 IO156PDB5V2

AB10 IO150PDB5V1

AB11 IO155PDB5V2

AB12 IO142PDB5V0

AB13 IO135NDB5V0

AB14 IO135PDB5V0

AB15 IO132PDB4V2

AB16 IO129PDB4V2

AB17 IO121PDB4V1

AB18 IO119NDB4V1

AB19 IO112NDB4V0

AB20 VMV4

676-Pin FBGA*

Pin Number A3PE1500 Function

AB21 TCK

AB22 TRST

AB23 GDC0/IO108NDB3V2

AB24 GDC1/IO108PDB3V2

AB25 IO104NDB3V2

AB26 IO104PDB3V2

AC1 IO170PDB6V0

AC2 GEB0/IO168NPB6V0

AC3 IO166NPB5V3

AC4 GNDQ

AC5 GND

AC6 IO160PDB5V3

AC7 IO161PDB5V3

AC8 IO154PDB5V2

AC9 GND

AC10 IO150NDB5V1

AC11 IO155NDB5V2

AC12 IO142NDB5V0

AC13 IO138NDB5V0

AC14 IO138PDB5V0

AC15 IO132NDB4V2

AC16 IO129NDB4V2

AC17 IO121NDB4V1

AC18 IO119PDB4V1

AC19 IO118NDB4V0

AC20 IO118PDB4V0

AC21 IO114PPB4V0

AC22 TMS

AC23 VJTAG

AC24 VMV3

AC25 IO106NDB3V2

AC26 IO106PDB3V2

AD1 IO170NDB6V0

AD2 GEA2/IO166PPB5V3

AD3 VMV5

AD4 GEC2/IO164PDB5V3

676-Pin FBGA*

Pin Number A3PE1500 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3E Flash Family FPGAs

v2.0 4-25

AD5 IO162PDB5V3

AD6 IO160NDB5V3

AD7 IO161NDB5V3

AD8 IO154NDB5V2

AD9 IO148PDB5V1

AD10 IO151PDB5V2

AD11 IO144PDB5V1

AD12 IO140PDB5V0

AD13 IO143PDB5V1

AD14 IO141PDB5V0

AD15 IO134PDB4V2

AD16 IO133PDB4V2

AD17 IO127PDB4V2

AD18 IO130PDB4V2

AD19 IO126PDB4V1

AD20 IO124PDB4V1

AD21 IO120PDB4V1

AD22 IO114NPB4V0

AD23 TDI

AD24 GNDQ

AD25 GDA0/IO110NDB3V2

AD26 GDA1/IO110PDB3V2

AE1 GND

AE2 GND

AE3 GND

AE4 IO164NDB5V3

AE5 IO162NDB5V3

AE6 IO158PPB5V2

AE7 IO157PPB5V2

AE8 IO152PPB5V2

AE9 IO148NDB5V1

AE10 IO151NDB5V2

AE11 IO144NDB5V1

AE12 IO140NDB5V0

AE13 IO143NDB5V1

AE14 IO141NDB5V0

676-Pin FBGA*

Pin Number A3PE1500 Function

AE15 IO134NDB4V2

AE16 IO133NDB4V2

AE17 IO127NDB4V2

AE18 IO130NDB4V2

AE19 IO126NDB4V1

AE20 IO124NDB4V1

AE21 IO120NDB4V1

AE22 IO116PDB4V0

AE23 GDC2/IO113PDB4V0

AE24 GDA2/IO111PDB4V0

AE25 GND

AE26 GND

AF1 GND

AF2 GND

AF3 GND

AF4 GND

AF5 IO158NPB5V2

AF6 IO157NPB5V2

AF7 IO152NPB5V2

AF8 IO146NDB5V1

AF9 IO146PDB5V1

AF10 IO149NDB5V1

AF11 IO149PDB5V1

AF12 IO145NDB5V1

AF13 IO145PDB5V1

AF14 IO136NDB5V0

AF15 IO136PDB5V0

AF16 IO131NDB4V2

AF17 IO131PDB4V2

AF18 IO128NDB4V2

AF19 IO128PDB4V2

AF20 IO122NDB4V1

AF21 IO122PDB4V1

AF22 IO116NDB4V0

AF23 IO113NDB4V0

AF24 IO111NDB4V0

676-Pin FBGA*

Pin Number A3PE1500 Function

AF25 GND

AF26 GND

B1 GND

B2 GND

B3 GND

B4 GND

B5 IO06PDB0V0

B6 IO04NDB0V0

B7 IO07NDB0V0

B8 IO11NDB0V1

B9 IO10NDB0V1

B10 IO16NDB0V2

B11 IO20NDB0V2

B12 IO24NDB0V3

B13 IO23NDB0V2

B14 IO28NDB0V3

B15 IO31NDB0V3

B16 IO32PDB1V0

B17 IO36PDB1V0

B18 IO37PDB1V0

B19 IO42NPB1V1

B20 IO41NDB1V1

B21 IO44NDB1V1

B22 IO49NDB1V2

B23 IO50NDB1V2

B24 GBC0/IO55NDB1V3

B25 GND

B26 GND

C1 GND

C2 GND

C3 GND

C4 GND

C5 GAA2/IO221PDB7V3

C6 IO04PDB0V0

C7 IO07PDB0V0

C8 IO11PDB0V1

676-Pin FBGA*

Pin Number A3PE1500 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3E Flash Family FPGAs

4-26 v2.0

C9 IO10PDB0V1

C10 IO16PDB0V2

C11 IO20PDB0V2

C12 IO24PDB0V3

C13 IO23PDB0V2

C14 IO28PDB0V3

C15 IO31PDB0V3

C16 IO32NDB1V0

C17 IO36NDB1V0

C18 IO37NDB1V0

C19 IO45NDB1V1

C20 IO42PPB1V1

C21 IO46NPB1V1

C22 IO48NPB1V2

C23 GBB0/IO56NPB1V3

C24 VMV1

C25 GBC2/IO60PDB2V0

C26 IO60NDB2V0

D1 IO218NDB7V3

D2 IO218PDB7V3

D3 GND

D4 VMV7

D5 IO221NDB7V3

D6 GAC0/IO02NDB0V0

D7 GAC1/IO02PDB0V0

D8 IO05NDB0V0

D9 IO08PDB0V1

D10 IO12NDB0V1

D11 IO18NDB0V2

D12 IO17NDB0V2

D13 IO25NDB0V3

D14 IO29NDB0V3

D15 IO33NDB1V0

D16 IO40PDB1V1

D17 IO43NDB1V1

D18 IO47PDB1V1

676-Pin FBGA*

Pin Number A3PE1500 Function

D19 IO45PDB1V1

D20 IO46PPB1V1

D21 IO48PPB1V2

D22 GBA0/IO57NPB1V3

D23 GNDQ

D24 GBB1/IO56PPB1V3

D25 GBB2/IO59PDB2V0

D26 IO59NDB2V0

E1 IO212PDB7V2

E2 IO211NDB7V2

E3 IO211PDB7V2

E4 IO220NPB7V3

E5 GNDQ

E6 GAB2/IO220PPB7V3

E7 GAB1/IO01PDB0V0

E8 IO05PDB0V0

E9 IO08NDB0V1

E10 IO12PDB0V1

E11 IO18PDB0V2

E12 IO17PDB0V2

E13 IO25PDB0V3

E14 IO29PDB0V3

E15 IO33PDB1V0

E16 IO40NDB1V1

E17 IO43PDB1V1

E18 IO47NDB1V1

E19 IO54NDB1V3

E20 IO52NDB1V2

E21 IO52PDB1V2

E22 VCCPLB

E23 GBA1/IO57PPB1V3

E24 IO63PDB2V0

E25 IO63NDB2V0

E26 IO68PDB2V1

F1 IO212NDB7V2

F2 IO203PPB7V1

676-Pin FBGA*

Pin Number A3PE1500 Function

F3 IO213NDB7V2

F4 IO213PDB7V2

F5 GND

F6 VCCPLA

F7 GAB0/IO01NDB0V0

F8 GNDQ

F9 IO03PDB0V0

F10 IO13PDB0V1

F11 IO15PDB0V1

F12 IO19PDB0V2

F13 IO21PDB0V2

F14 IO27NDB0V3

F15 IO35PDB1V0

F16 IO39NDB1V0

F17 IO51PDB1V2

F18 IO53PDB1V2

F19 IO54PDB1V3

F20 VMV2

F21 VCOMPLB

F22 IO61PDB2V0

F23 IO61NDB2V0

F24 IO66PDB2V1

F25 IO66NDB2V1

F26 IO68NDB2V1

G1 IO203NPB7V1

G2 IO207NDB7V2

G3 IO207PDB7V2

G4 IO216NDB7V3

G5 IO216PDB7V3

G6 VCOMPLA

G7 VMV0

G8 VCC

G9 IO03NDB0V0

G10 IO13NDB0V1

G11 IO15NDB0V1

G12 IO19NDB0V2

676-Pin FBGA*

Pin Number A3PE1500 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3E Flash Family FPGAs

v2.0 4-27

G13 IO21NDB0V2

G14 IO27PDB0V3

G15 IO35NDB1V0

G16 IO39PDB1V0

G17 IO51NDB1V2

G18 IO53NDB1V2

G19 VCCIB1

G20 GBA2/IO58PPB2V0

G21 GNDQ

G22 IO64NDB2V1

G23 IO64PDB2V1

G24 IO72PDB2V2

G25 IO72NDB2V2

G26 IO78PDB2V2

H1 IO208NDB7V2

H2 IO208PDB7V2

H3 IO209NDB7V2

H4 IO209PDB7V2

H5 IO219NDB7V3

H6 GAC2/IO219PDB7V3

H7 VCCIB7

H8 VCC

H9 VCCIB0

H10 VCCIB0

H11 VCCIB0

H12 VCCIB0

H13 VCCIB0

H14 VCCIB1

H15 VCCIB1

H16 VCCIB1

H17 VCCIB1

H18 VCCIB1

H19 VCC

H20 VCC

H21 IO58NPB2V0

H22 IO70PDB2V1

676-Pin FBGA*

Pin Number A3PE1500 Function

H23 IO69PDB2V1

H24 IO76PDB2V2

H25 IO76NDB2V2

H26 IO78NDB2V2

J1 IO197NDB7V0

J2 IO197PDB7V0

J3 VMV7

J4 IO215NDB7V3

J5 IO215PDB7V3

J6 IO214PDB7V3

J7 IO214NDB7V3

J8 VCCIB7

J9 VCC

J10 VCC

J11 VCC

J12 VCC

J13 VCC

J14 VCC

J15 VCC

J16 VCC

J17 VCC

J18 VCC

J19 VCCIB2

J20 IO62PDB2V0

J21 IO62NDB2V0

J22 IO70NDB2V1

J23 IO69NDB2V1

J24 VMV2

J25 IO80PDB2V3

J26 IO80NDB2V3

K1 IO195PDB7V0

K2 IO199NDB7V1

K3 IO199PDB7V1

K4 IO205NDB7V1

K5 IO205PDB7V1

K6 IO217PDB7V3

676-Pin FBGA*

Pin Number A3PE1500 Function

K7 IO217NDB7V3

K8 VCCIB7

K9 VCC

K10 GND

K11 GND

K12 GND

K13 GND

K14 GND

K15 GND

K16 GND

K17 GND

K18 VCC

K19 VCCIB2

K20 IO65PDB2V1

K21 IO65NDB2V1

K22 IO74PDB2V2

K23 IO74NDB2V2

K24 IO75PDB2V2

K25 IO75NDB2V2

K26 IO84PDB2V3

L1 IO195NDB7V0

L2 IO198PPB7V0

L3 GNDQ

L4 IO201PDB7V1

L5 IO201NDB7V1

L6 IO210NDB7V2

L7 IO210PDB7V2

L8 VCCIB7

L9 VCC

L10 GND

L11 GND

L12 GND

L13 GND

L14 GND

L15 GND

L16 GND

676-Pin FBGA*

Pin Number A3PE1500 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3E Flash Family FPGAs

4-28 v2.0

L17 GND

L18 VCC

L19 VCCIB2

L20 IO67PDB2V1

L21 IO67NDB2V1

L22 IO71PDB2V2

L23 IO71NDB2V2

L24 GNDQ

L25 IO82PDB2V3

L26 IO84NDB2V3

M1 IO198NPB7V0

M2 IO202PDB7V1

M3 IO202NDB7V1

M4 IO206NDB7V1

M5 IO206PDB7V1

M6 IO204NDB7V1

M7 IO204PDB7V1

M8 VCCIB7

M9 VCC

M10 GND

M11 GND

M12 GND

M13 GND

M14 GND

M15 GND

M16 GND

M17 GND

M18 VCC

M19 VCCIB2

M20 IO73NDB2V2

M21 IO73PDB2V2

M22 IO81PPB2V3

M23 IO77PDB2V2

M24 IO77NDB2V2

M25 IO82NDB2V3

M26 IO83PDB2V3

676-Pin FBGA*

Pin Number A3PE1500 Function

N1 GFB0/IO191NPB7V0

N2 VCOMPLF

N3 GFB1/IO191PPB7V0

N4 IO196PDB7V0

N5 GFA0/IO190NDB6V2

N6 IO200PDB7V1

N7 IO200NDB7V1

N8 VCCIB7

N9 VCC

N10 GND

N11 GND

N12 GND

N13 GND

N14 GND

N15 GND

N16 GND

N17 GND

N18 VCC

N19 VCCIB2

N20 IO79PDB2V3

N21 IO79NDB2V3

N22 GCA2/IO88PPB3V0

N23 IO81NPB2V3

N24 GCA0/IO87NDB3V0

N25 GCB0/IO86NPB2V3

N26 IO83NDB2V3

P1 GFA2/IO189PDB6V2

P2 VCCPLF

P3 IO193PPB7V0

P4 IO196NDB7V0

P5 GFA1/IO190PDB6V2

P6 IO194PDB7V0

P7 IO194NDB7V0

P8 VCCIB6

P9 VCC

P10 GND

676-Pin FBGA*

Pin Number A3PE1500 Function

P11 GND

P12 GND

P13 GND

P14 GND

P15 GND

P16 GND

P17 GND

P18 VCC

P19 VCCIB3

P20 GCC0/IO85NDB2V3

P21 GCC1/IO85PDB2V3

P22 GCB1/IO86PPB2V3

P23 IO88NPB3V0

P24 GCA1/IO87PDB3V0

P25 VCCPLC

P26 VCOMPLC

R1 IO189NDB6V2

R2 IO185PDB6V2

R3 IO187NPB6V2

R4 IO193NPB7V0

R5 GFC2/IO187PPB6V2

R6 GFC1/IO192PDB7V0

R7 GFC0/IO192NDB7V0

R8 VCCIB6

R9 VCC

R10 GND

R11 GND

R12 GND

R13 GND

R14 GND

R15 GND

R16 GND

R17 GND

R18 VCC

R19 VCCIB3

R20 NC

676-Pin FBGA*

Pin Number A3PE1500 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3E Flash Family FPGAs

v2.0 4-29

R21 IO89NDB3V0

R22 GCB2/IO89PDB3V0

R23 IO90NDB3V0

R24 GCC2/IO90PDB3V0

R25 IO91PDB3V0

R26 IO91NDB3V0

T1 IO186PDB6V2

T2 IO185NDB6V2

T3 GNDQ

T4 IO180PDB6V1

T5 IO180NDB6V1

T6 IO188NDB6V2

T7 GFB2/IO188PDB6V2

T8 VCCIB6

T9 VCC

T10 GND

T11 GND

T12 GND

T13 GND

T14 GND

T15 GND

T16 GND

T17 GND

T18 VCC

T19 VCCIB3

T20 IO99PDB3V1

T21 IO99NDB3V1

T22 IO97PDB3V1

T23 IO97NDB3V1

T24 GNDQ

T25 IO93PPB3V0

T26 NC

U1 IO186NDB6V2

U2 IO184NDB6V2

U3 IO184PDB6V2

U4 IO182NDB6V1

676-Pin FBGA*

Pin Number A3PE1500 Function

U5 IO182PDB6V1

U6 IO178PDB6V1

U7 IO178NDB6V1

U8 VCCIB6

U9 VCC

U10 GND

U11 GND

U12 GND

U13 GND

U14 GND

U15 GND

U16 GND

U17 GND

U18 VCC

U19 VCCIB3

U20 NC

U21 IO101NDB3V1

U22 IO101PDB3V1

U23 IO92NDB3V0

U24 IO92PDB3V0

U25 IO95PDB3V1

U26 IO93NPB3V0

V1 IO183PDB6V2

V2 IO183NDB6V2

V3 VMV6

V4 IO181PDB6V1

V5 IO181NDB6V1

V6 IO176PDB6V1

V7 IO176NDB6V1

V8 VCCIB6

V9 VCC

V10 VCC

V11 VCC

V12 VCC

V13 VCC

V14 VCC

676-Pin FBGA*

Pin Number A3PE1500 Function

V15 VCC

V16 VCC

V17 VCC

V18 VCC

V19 VCCIB3

V20 IO107PDB3V2

V21 IO107NDB3V2

V22 IO103NDB3V2

V23 IO103PDB3V2

V24 VMV3

V25 IO95NDB3V1

V26 IO94PDB3V0

W1 IO179NDB6V1

W2 IO179PDB6V1

W3 IO177NDB6V1

W4 IO177PDB6V1

W5 IO172PDB6V0

W6 IO172NDB6V0

W7 VCC

W8 VCC

W9 VCCIB5

W10 VCCIB5

W11 VCCIB5

W12 VCCIB5

W13 VCCIB5

W14 VCCIB4

W15 VCCIB4

W16 VCCIB4

W17 VCCIB4

W18 VCCIB4

W19 VCC

W20 VCCIB3

W21 GDB0/IO109NDB3V2

W22 GDB1/IO109PDB3V2

W23 IO105NDB3V2

W24 IO105PDB3V2

676-Pin FBGA*

Pin Number A3PE1500 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3E Flash Family FPGAs

4-30 v2.0

W25 IO96PDB3V1

W26 IO94NDB3V0

Y1 IO175NDB6V1

Y2 IO175PDB6V1

Y3 IO173NDB6V0

Y4 IO173PDB6V0

Y5 GEC1/IO169PPB6V0

Y6 GNDQ

Y7 VMV6

Y8 VCCIB5

676-Pin FBGA*

Pin Number A3PE1500 Function

Y9 IO163NDB5V3

Y10 IO159PDB5V3

Y11 IO153PDB5V2

Y12 IO147PDB5V1

Y13 IO139PDB5V0

Y14 IO137PDB5V0

Y15 IO125NDB4V1

Y16 IO125PDB4V1

Y17 IO115NDB4V0

Y18 IO115PDB4V0

676-Pin FBGA*

Pin Number A3PE1500 Function

Y19 VCC

Y20 VPUMP

Y21 VCOMPLD

Y22 VCCPLD

Y23 IO100NDB3V1

Y24 IO100PDB3V1

Y25 IO96NDB3V1

Y26 IO98PDB3V1

676-Pin FBGA*

Pin Number A3PE1500 Function

Note: *Refer to the "User I/O Naming Convention" section on page 2-50.

ProASIC3E Flash Family FPGAs

v2.0 4-31

896-Pin FBGA

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.actel.com/products/solutions/package/docs.aspx.

This is the bottom view of the package.

A1 Ball Pad Corner

123456789101112131415161718192021222324252627282930

ProASIC3E Flash Family FPGAs

v2.0 5-1

Datasheet Information

List of Changes

The following table lists critical changes that were made in the current version of the document.

Previous Version Changes in Current Version (v2.0) Page

Advanced v0.6

(January 2007)

The "Clock Conditioning Circuit (CCC) and PLL" section was updated. i

The "PLL Macro" section was updated to add information on the VCO and PLL outputs during

power-up.

2-15

In the "ProASIC3E Ordering Information", Ambient was deleted. iii

Ambient was deleted from "Temperature Grade Offerings".iv

Ambient was deleted from the"Speed Grade and Temperature Grade Matrix".iv

The "PLL Macro" section was updated to include power-up information. 2-15

Table 2-4 • ProASIC3E CCC/PLL Specification was updated. 2-18

The "SRAM and FIFO" section was updated with operation and timing requirement

information.

2-21

Figure 2-18 • Peak-to-Peak Jitter Definition is new. 2-18

The "RESET" section was updated with read and write information. 2-24

The "RESET" section was updated with read and write information. 2-25

The"Introduction" in the "Pro I/Os" section was updated to include information on input and

output buffers being disabled.

2-27

PCI-X 3.3 V was added to Table 2-12 • VCCI Voltages and Compatible ProASIC3E Standards.2-29

In the Table 2-17 • Levels of Hot-Swap Support, the ProASIC3 compliance descriptions were

updated for levels 3 and 4.

2-36

Table 2-18 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3E Devices was

updated.

2-37

Notes 3, 4, and 5 were added to Table 2-19 • Comparison Table for 5 V–Compliant Receiver

Scheme. 5 x 52.72 was changed to 52.7 and the Maximum current was updated from 4 x 52.7

to 5 x 52.7.

2-41

The "VCCPLA/B/C/D/E/F PLL Supply Voltage" section was updated. 2-51

The "VPUMP Programming Supply Voltage" section was updated. 2-51

The "GL Globals" section was updated to include information about direct input into quadrant

clocks.

2-52

VJTAG was deleted from the "TCK Test Clock" section.2-52

In Table 2-24 • Recommended Tie-Off Values for the TCK and TRST Pins, TSK was changed to

TCK in note 2. Note 3 was also updated.

2-52

Ambient was deleted from Table 3-2 • Recommended Operating Conditions. VPUMP

programming mode was changed from "3.0 to 3.6" to "3.15 to 3.45".

3-2

ProASIC3E Flash Family FPGAs

5-2 v2.0

Advanced v0.6

(continued)

Note 3 is new in Table 3-4 • Overshoot and Undershoot Limits (as measured on quiet I/Os)1.3-2

In EQ 3-2, 150 was changed to 110 and the result changed from 5.88 to 3-4

Table 3-6 • Temperature and Voltage Derating Factors for Timing Delays was updated. 3-4

Table 3-5 • Package Thermal Resistivities was updated. 3-4

Table 3-10 • Different Components Contributing to the Dynamic Power Consumption in

ProASIC3E Devices was updated.

3-7

tWRO and tCCKH were added to Table 3-94 • RAM4K9 and Table 3-95 • RAM512X18.3-73 to 3-74

The note in Table 3-24 • I/O Input Rise Time, Fall Time, and Related I/O Reliability1 was

updated.

3-22

Figure 3-43 • Write Access After Write onto Same Address, Figure 3-44 • Read Access After

Write onto Same Address, and Figure 3-45 • Write Access After Read onto Same Address are

new.

3-70 to 3-72

Figure 3-53 • Timing Diagram was updated. 3-79

Notes were added to the package diagrams identifying if they were top or bottom view. N/A

The A3PE1500 "208-Pin PQFP*" table is new. 4-4

The A3PE1500 "484-Pin FBGA*" table is new. 4-18

The A3PE1500 "A3PE1500 Function" table is new. 4-24

Advanced v0.5

(April 2006)

In the "I/Os Per Package1" table, the number of I/Os for the A3PE1500 was changed for the

FG484 and FG676 packages.

iii

Advanced v0.4

(October 2005)

BLVDS and M-LDVS are new I/O standards added to the datasheet. N/A

The term flow-through was changed to pass-through. N/A

The "Pro I/Os with Advanced I/O Standards" section was updated to include I/O bank

information.

1-5

Figure 2-7 • Very-Long-Line Resources was updated. 2-7

The footnotes in Figure 2-16 • CCC/PLL Macro were updated. 2-17

The Delay Increments in the Programmable Delay Blocks specification in Figure 2-

13 • ProASIC3E CCC Options were updated.

2-14

The "SRAM and FIFO" section was updated. 2-21

The "RESET" section was updated. 2-24

The "WCLK and RCLK" section was updated. 2-25

The "RESET" section was updated. 2-25

The "RESET" section was updated. 2-26

The "Introduction" of the "Pro I/Os" section was updated. 2-27

Previous Version Changes in Current Version (v2.0) Page

ProASIC3E Flash Family FPGAs

v2.0 5-3

Advanced v0.4

(continued)

PCI-X 3.3 V was added to the Compatible Standards for 3.3 V in Table 2-12 • VCCI Voltages

and Compatible ProASIC3E Standards

2-29

Table 2-15 • ProASIC3E I/O Features was updated. 2-31

The "Double Data Rate (DDR) Support" section was updated to include information concerning

implementation of the feature.

2-34

The "Electrostatic Discharge (ESD) Protection" section was updated to include testing

information.

2-37

The notes in Table 2-18 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3E

Devices were updated.

2-37

The "Simultaneous Switching Outputs (SSOs) and Printed Circuit Board Layout" section is new. 2-42

A footnote was added to Table 2-16 • Maximum I/O Frequency for Single-Ended and

Differential I/Os in All Banks in ProASIC3E Devices (maximum drive strength and high slew

selected).

2-32

Table 2-20 • ProASIC3E I/O Attributes vs. I/O Standard Applications 2-46

Table 2-21 • ProASIC3E I/O Standards—SLEW and Output Drive (OUT_DRIVE) Settings 2-47

The "x" was updated in the "User I/O Naming Convention" section.2-50

The "VCC Core Supply Voltage" pin description was updated. 2-51

The "VMVx I/O Supply Voltage (quiet)" pin description was updated to include information

concerning leaving the pin unconnected.

2-51

EXTFB was removed from Figure 2-13 • ProASIC3E CCC Options.2-14

The CCC Output Peak-to-Peak Period Jitter FCCC_OUT was updated in Table 2-4 • ProASIC3E

CCC/PLL Specification.

2-18

The LVPECL specification in Table 2-18 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in

ProASIC3E Devices was updated.

2-37

Table 2-17 • Levels of Hot-Swap Support was updated. 2-36

The "Cold-Sparing Support" section was updated. 2-37

"Electrostatic Discharge (ESD) Protection" section was updated. 2-37

The VJTAG and I/O pin descriptions were updated in the "Pin Descriptions" section.2-51

Previous Version Changes in Current Version (v2.0) Page

ProASIC3E Flash Family FPGAs

5-4 v2.0

Advanced v0.3 The "VJTAG JTAG Supply Voltage" pin description was updated. 2-51

The "VPUMP Programming Supply Voltage" pin description was updated to include information

on what happens when the pin is tied to ground.

2-51

The "I/O User Input/Output" pin description was updated to include information on what

happens when the pin is unused.

2-52

The "JTAG Pins" section was updated to include information on what happens when the pin is

unused.

2-52

The "Programming" section was updated to include information concerning serialization. 2-53

The "JTAG 1532" section was updated to include SAMPLE/PRELOAD information. 2-54

The "DC and Switching Characteristics" chapter was updated with new information. Starting on

page 3-1

Tabl e 3-6 was updated. 3-4

In Tabl e 3- 10 PAC4 was updated. 3-7

Tabl e 3-19 was updated. 3-19

The note in Tab le 3-24 was updated. 3-22

All Timing Characteristics tables were updated from LVTTL to Register Delays 3-25 to 3-63

The Timing Characteristics for RAM4K9, RAM512X18, and FIFO were updated. 3-73 to 3-78

FTCKMAX was updated in Tab le 3 -9 8.3-80

Advanced v0.2 The "ProASIC3E Ordering Information" table was updated. iii

The "Live at Power-Up" section is new. 1-2

Figure 2-4 was updated. 2-4

The "Clock Resources (VersaNets)" section was updated. 2-8

The "VersaNet Global Networks and Spine Access" section was updated. 2-10

The "PLL Macro" section was updated. 2-15

Figure 2-16 was updated. 2-17

Figure 2-19 was updated. 2-19

Tabl e 2-6 was updated. 2-24

Tabl e 2-7 was updated. 2-24

The "FIFO Flag Usage Considerations" section was updated. 2-27

Tabl e 2-14 was updated. 2-30

Figure 2-24 was updated. 2-33

The "Cold-Sparing Support" section is new. 2-37

Tabl e 2-18 was updated. 2-37

Tabl e 2-20 was updated. 2-46

Pin descriptions in the "JTAG Pins" section were updated. 2-52

The "User I/O Naming Convention" section was updated. 2-50

Tabl e 3-7 was updated. 3-5

The "Methodology" section was updated. 3-8

The A3PE3000 "208-Pin PQFP*" pin table was updated. 4-6

Previous Version Changes in Current Version (v2.0) Page

ProASIC3E Flash Family FPGAs

v2.0 5-5

Datasheet Categories

In order to provide the latest information to designers, some datasheets are published before data has been fully

characterized. Datasheets are designated as “Product Brief,” “Advanced,” “Production,” and “Web-only.” The

definition of these categories are as follows:

Product Brief

The product brief is a summarized version of a advanced datasheet (advanced or production) containing general

product information. This brief gives an overview of specific device and family information.

Advanced

This datasheet version contains initial estimated information based on simulation, other products, devices, or speed

grades. This information can be used as estimates, but not for production.

Datasheet Supplement

The datasheet supplement gives specific device information for a derivative family that differs from the general family

datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and

for specifications that do not differ between the two families.

Unmarked (production)

This datasheet version contains information that is considered to be final.

Export Administration Regulations (EAR)

The products described in this datasheet are subject to the Export Administration Regulations (EAR). They could

require an approved export license prior to export from the United States. An export includes release of product or

disclosure of technology to a foreign national inside or outside the United States.

51700018-6/4.07

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