Rev.1.0, Apr.05.2004, page 1 of 19
HD49330AF/AHF
CDS/PGA & 12-bit A/D Converter REJ03F0102-0100Z
(Previous : AD E- 207-3 44)
Rev.1.0
Apr.05.2004
Description
The HD49330AF/AHF is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera
digital signal processing systems together with a 12 -bit A/D converter in a single chip.
Functions
• Correlated double sampling
• PGA
• Offset compensation
• Serial interface control
• 12-bit ADC
• Operates using only the 3 V voltage
• Corresponds to switching mode of power dissipation and operating frequency
Power dissipation: 150 mW (Typ), maximum frequency: 36 MHz
Power dissipation: 80 mW (Typ), maximum frequenc y: 20 MHz
• ADC direct input mode
• Y-IN direct input mode
• QFP 48-pin package
Features
• Suppresses low-frequency noise output from CCD by the S/H type correlated double sampling.
• The S/H response frequency characteristics for the reference level can be adjusted using values of external parts and
registers.
• High sensitivity is achieved due to the high S/N ratio and a wide coverage provided by a PG amplifier.
• Feedback is used to compensate and reduce the DC offsets including the output DC offset due to PGA gain change
and the CCD offset in the CDS (correlated double sampling) amplifier input.
• PGA, standby mode, etc., is achieved via a serial interface.
• High precision is provided by a 12-bit-resolution A/D converter.
HD49330AF/AHF
Rev.1.0, Apr.05.2004, page 2 of 19
Pin Arrangement
ADCIN
AV
SS
Y IN
AV
DD
BIAS
BLKC
CDSIN
BLKFB
BLKSH
AV
DD
AV
SS
AV
SS
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
36 35 2734 33 32 31 30 29 28 26 25
12 103456789 1112
24
23
22
21
20
19
18
17
16
15
14
13
37
38
39
40
41
42
43
44
45
46
47
48
(Top view)
DV
DD
(NC)
SPSIG
SPBLK
OBP
PBLK
DV
DD
DV
DD
ADCLK
DV
SS
DV
SS
DRDV
DD
VRM
VRT
VRB
DV
DD
DV
SS
OEB
DV
DD
DV
DD
DV
SS
CS
SDATA
SCK
Pin Description
Pin No.
Symbol
Description
I/O Analog(A) or
Digital(D)
1 D0 Digital output (LSB) O D
2 to 11 D1 to D10 Digital output O D
12 D11 Digital output (MSB) O D
13 DRDVDD Output buffer power supply (3 V) — D
14 DVSS Digital ground (0 V) — D
15 DVSS Digital ground (0 V) — D
16 ADCLK ADC conversion clock input pin I D
17 DVDD Digital power supply (3 V) — D
18 DVDD Digital power supply (3 V) — D
19 PBLK Preblanking input pin I D
20 OBP Optical black pulse input pin I D
21 SPBLK Black level sampling clock input pin I D
22 SPSIG Signal level sampling clock input pin I D
23 NC No connection pin — —
24 DVDD Output power supply (3 V) — D
25 AVSS Analog ground (0 V) — A
26 AVSS Analog ground (0 V) — A
27 AVDD Analog power supply (3 V) — A
28 BLKSH Black level S/H pin — A
29 BLKFB Black level FB pin — A
30 CDSIN CDS input pin I A
31 BLKC Black level C pin — A
HD49330AF/AHF
Rev.1.0, Apr.05.2004, page 3 of 19
Pin Description (cont.)
Pin No.
Symbol
Description
I/O Analog(A) or
Digital(D)
32 BIAS Internal bias pin
Connect a 33 kΩ resistor between BIAS and AVSS. — A
33 AVDD Analog power supply (3 V) — A
34 Y IN Y input pin — A
35 AVSS Analog ground (0 V) — A
36 ADCIN ADC input pin — A
37 VRM Reference voltage pin 1
Connect a 0.1 µF ceramic capacitor between VRM and AVSS. — A
38 VRT Reference voltage pin 3
Connect a 0.1 µF ceramic capacitor between VRT and AVSS. — A
39 VRB Reference voltage pin 2
Connect a 0.1 µF ceramic capacitor between VRB and AVSS. — A
40 DVDD Digital power supply (3 V) — D
41 DVSS Digital ground (0 V) — D
42 OEB *1 Digital output ena ble pin — D
43 DVDD Digital power supply (3 V) — D
44 DVDD Digital power supply (3 V) — D
45 DVSS Digital ground (0 V) — D
46 CS Serial interface control input pin I D
47 SDATA Serial data input pin I D
48 SCK Serial clock input pin I D
Note: 1. With pull-down resistor.
HD49330AF/AHF
Rev.1.0, Apr.05.2004, page 4 of 19
Input/Output Equivalent Circuit
Pin Name Equivalent Circuit
Digital output D0 to D11
DIN DV
DD
STBY
Digital
output
Digital input ADCLK, OBP,
SPBLK, SPSIG,
CS, SCK, SDATA,
PBLK, OEB
*1
Digital
input
DVDD
Note: Only OEB is pulled down to about 70 kΩ.
CDSIN
CDSIN
Internally
connected
to VRT
AVDD
ADCIN
ADCIN
Internally
connected
to VRM
AVDD
Y IN
Y IN
AVDD
−
+
BLKSH, BLKFB
BLKFB
AVDD
BLKSH
−
+
VRT, VRM, VRB
−
+
−
+
VRT VRM VRB AVDD
Analog
BIAS
BIAS
AV
DD
HD49330AF/AHF
Rev.1.0, Apr.05.2004, page 5 of 19
Block Diagram
Bias
generator
33343243454417
26
28
29
35
2
3
4
5
6
7
8
11
42
9
10
19181631
12 bit
ADC
D11
OEB
VRB
VRM
VRT
OBP
CDSIN
BLKSH
28BLKC
26PBLK
27ADCIN 26Y IN
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BLKFB
CS
SDATA
SCK
BIAS
Timing
generator
191816
ADCLK
SPBLK
SPSIG
DV
DD
DRDV
DD
AV
SS
AV
DD
19
DV
SS
CDS PGA
Output latch circuit
Serial
interface
DC offset
compensation
circuit
HD49330AF/AHF
Rev.1.0, Apr.05.2004, page 6 of 19
Internal Functions
Functional Description
• CDS input
CCD low-frequency noise is suppressed by CDS (correlated double sampling).
The signal level is clamped at 56 LSB to 304 LSB by resister during the OB period.
Gain can be adjusted using 10 bits of register (0.033 dB steps) within the range from –2.36 dB to 31.40 dB. *1
• ADC input
The center level of the input signal is clamped at 2048 LSB (Typ).
Gain can be adjusted using 10 bits of register (0.00446 times steps) within the range from 0.57 times (–4.86 dB)
to 5.14 times (14.22 dB). *1
• Y-IN input
The input signal is clamped at 280 LSB (Typ) by SYNC Tip clamp.
• Automatic offset calibration of PGA and ADC
• DC offset compensation feedback for CCD and CDS
• Pre-blanking
CDS input operation is protected by separating it from the large input signal.
Digital output is fixed at 32 LSB .
• Digital output enable function
Note: 1. Full-scale digital output is defi ned as 0 dB (one time) when 1 V is input.
Operating Description
Figure 1 shows CDS/PGA + ADC function block.
Offset
calibration
logic
DC offset
feedback
logic
DAC
C3
CDS
AMP PG
AMP
ADCIN
CDSIN
BLKFB BLKSH
Gain setting
(register) Clamp data
(register)
OBP
SH
AMP
BLKC
C4
C2
C1
VRT Current
DAC
12-bit
ADC D0 to D11
Figure 1 HD49330AF/AHF Functional Block Diagram
1. CDS (Correlated Double Sa mpling) Circuit
The CDS circuit extracts the voltage differential between the black level and a signal including the black level. The
black level is directly sampled at C1 by using the SPB LK pulse, buffered by the SHAMP, then provided to the
CDSAMP.
The signal level is directly sampled at C2 by using the SPSIG pulse, and provided to CDSAMP (see figure 1). The
difference between these two signal levels is extracted by the CDSAMP, which also operates as a programmable
gain amplifier at the previous stage. The CDS input is biased with VRT (2 V) during the SPBLK pulse validation
period. During the PBLK period, the above sampling and bias operation are paused.
HD49330AF/AHF
Rev.1.0, Apr.05.2004, page 7 of 19
2. PGA Circuit
The PGAMP is the programmable gain ampli fier for the latter stage. The PGAMP and the CDSAMP set the gain
using 10 bits of register.
The equation below shows how the gain changes when register value N is from 0 to 1023.
In CDSIN mode: Gain = (–2.36 dB + 0.033 dB) × N (LOG linear).
In ADCIN mode: Gain = (0.57 times + 0.00446 times) × N (linear).
Full-scale digital output is defi ned as 0 dB (one time) when 1 V is input.
3. Automatic Offset Ca libration Function a nd Black-Level Clamp Data Setting
The DAC DC voltage added to the output of the PGAMP is adjusted by automatic offset calibration.
The data, which cancels the output offset of the PGAMP and the input offset of the ADC, and the clamp data (56
LSB to 304 LSB) set by register are added and input to the DAC.
The automatic offset calibration starts automatically after the RESET mode set by register 1 is cancelled and
terminates after 40000 clock cycles (when fclk = 20 MHz, 2 ms).
4. DC Offset Compe nsation Feedb ack Functio n
Feedback is done to set the blac k si gnal level input during the OB period to the DC standard, and all offsets
(including the CCD offset and the CDSAMP offset) are compensated for.
The offset from the ADC output is calculated during the OB period, and SHAMP feedback capacitor C3 is charged
by the current DAC (see figure 1).
The open-loop differential gain (∆Gain/∆H) per 1 H of the feedback loop is given by the following equation. 1H is
the one cycle of the OBP.
∆Gain/∆H = 0.078/(fclk × C3) (fclk: ADCLK frequency, C3: SHAMP external feedback capacitor)
Example: When fclk = 20 MHz and C3 = 1.0 µF, ∆Gain/∆H = 0.0039
When the PGAMP gain setting is changed, the high-speed lead-in operation state is entered, and the feedback loop
gain is increased by a multiple of N. Loop gain multiplication factor N can be selected from 2 times, 4 times, 8
times, or 16 times by changing the register settings (see table 1). Note that the open-loop differential gain
(∆Gain/∆H) must be one or lower. If it is two or more, oscillation occurs.
The time from the termination of high-speed lead-in operation to the return of normal loop gain operation can be
selected from 1 H, 2 H, 4 H, or 8 H. If the offset error is over 64 LSB, the high-speed lead-in operation continues,
and when the offset error is 64 LSB or less, the operation returns to the normal loop-gain operation after 1 H, 2 H, 4
H, or 8 H depending on the register settings. See table 2.
Table 1 Loop Gain Multiplication Factor during
High-Speed Lead-In Operation Table 2 High-Speed Lead-In Operation
Cancellation Time
HGain-Nsel
(register settings) Multiplication
Factor N
HGstop-Hsel
(register settings) Cancellation
Time
[0]
L
H
L
H
[1]
L
H
H
L4
32
16
8
[0]
L
H
L
H
[1]
L
H
H
L1 H
8 H
4 H
2 H
5. Pre-Blanking Function
During the PBLK input period, the CSD input operation is separated and protected from the large input signal. The
ADC digital output is fixed to clamp data (56 to 304 LSB).
HD49330AF/AHF
Rev.1.0, Apr.05.2004, page 8 of 19
6. ADC Digital Output Control Functio n
The ADC digital output includes the functions output enable, code conversion, and test mode. Tables 3, 4 and 5
show the output funct i ons a nd the codes.
Table 3 ADC Digital Output Functions
Operating Mode
ADC Digital Output
Low-power wait state
Output Hi-Z
Normal operation
Pre-blanking
Normal operation
Pre-blanking
Test mode
Hi-Z
Hi-Z
Same as in table 4.
D11 is inverted in table 4.
D10 to D0 are inverted in table 4.
D11 to D0 are inverted in table 4.
Output code is set up to Clamp Level.
Same as in table 5.
D11 is inverted in table 5.
D10 to D0 are inverted in table 5.
D11 to D0 are inverted in table 5.
Output code is set up to Clamp Level.
Notes: 1. STBY, TEST, LINV, and MINV are set by register.
2. Mode setting for the OEB and the PBLK are done by external input pins.
3. The polarity of the PBLK pin when the register setting is SPinv is low.
X
X
H
H
H
H
L
H
H
H
H
L
X
X
X
X
H
H
L
L
L
L
H
H
H
L
H
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
X
X
L
H
L
H
X
L
H
L
H
X
L
H
L
H
X
X
L
L
H
H
X
L
L
H
H
X
L
L
H
H
X
X
L
H
X
X
X
L
H
X
H
L
H
L
STBY
D9
OEB
D0D1D2D3D4D5D6D7D8D11 D10
PBLK
MINV
LINV
TEST0
TEST1
Table 4 ADC Output Code
Output Pin
Output
codes Steps 0
1
2
3
4
5
6
2047
2048
4092
4093
4094
4095
D1
L
L
H
H
L
L
H
H
L
L
L
H
H
D0
L
H
L
H
L
H
L
H
L
L
H
L
H
D2
L
L
L
L
H
H
H
H
L
H
H
H
H
D7
L
L
L
L
L
L
L
H
L
H
H
H
H
D5
L
L
L
L
L
L
L
H
L
H
H
H
H
D4
L
L
L
L
L
L
L
H
L
H
H
H
H
D3
L
L
L
L
L
L
L
H
L
H
H
H
H
D6
L
L
L
L
L
L
L
H
L
H
H
H
H
D8
L
L
L
L
L
L
L
H
L
H
H
H
H
D9
L
L
L
L
L
L
L
H
L
H
H
H
H
D10
L
L
L
L
L
L
L
H
L
H
H
H
H
D11
L
L
L
L
L
L
L
L
H
H
H
H
H
Table 5 ADC Output Code (TEST1)
Output Pin
Output
codes Steps 0
1
2
3
4
5
6
2047
2048
4092
4093
4094
4095
D1
L
L
H
H
H
H
L
L
L
H
H
L
L
D0
L
H
H
L
L
H
H
L
L
L
H
H
L
D2
L
L
L
L
H
H
H
L
L
L
L
L
L
D7
L
L
L
L
L
L
L
L
L
L
L
L
L
D5
L
L
L
L
L
L
L
L
L
L
L
L
L
D4
L
L
L
L
L
L
L
L
L
L
L
L
L
D3
L
L
L
L
L
L
L
L
L
L
L
L
L
D6
L
L
L
L
L
L
L
L
L
L
L
L
L
D8
L
L
L
L
L
L
L
L
L
L
L
L
L
D9
L
L
L
L
L
L
L
L
L
L
L
L
L
D10
L
L
L
L
L
L
L
H
H
L
L
L
L
D11
L
L
L
L
L
L
L
L
H
H
H
H
H
HD49330AF/AHF
Rev.1.0, Apr.05.2004, page 9 of 19
7. Adjustment of Black-Level S/H Response Frequency Characteristics
The CR time constant that is used for sampling/hold (S/H) at the black level can be adjusted by changing the
register settings, as shown in table 6.
Table 6 SHSW CR Ti me Const ant Setting
L
[0]
2.20 nsec
(72 MHz) 2.30 nsec
(69 MHz)
L
[1]
L
[2]
L2.51 nsec
(63 MHz) 2.64 nsec
(60 MHz) 2.93 nsec
(54 MHz) 3.11 nsec
(51 MHz) 3.52 nsec
(45 MHz) 3.77 nsec
(42 MHz)
[3]
H
[0]
L
[1]
L
[2]
L
[3]
L
[0]
H
[1]
L
[2]
L
[3]
H
[0]
H
[1]
L
[2]
L
[3]
L
[0]
L
[1]
H
[2]
L
[3]
H
[0]
L
[1]
H
[2]
L
[3]
L
[0]
H
[1]
H
[2]
L
[3]
H
[0]
H
[1]
H
[2]
L
[3]
L
[0]
SHSW-fsel (Register setting)
4.40 nsec
(36 MHz) 4.80 nsec
(33 MHz)
L
[1]
L
[2]
H
CR Time Constant (Typ)
(cutoff frequency conversion)
5.87 nsec
(27 MHz) 6.60 nsec
(24 MHz) 8.80 nsec
(18 MHz) 10.6 nsec
(15 MHz) 17.6 nsec
(9 MHz) 26.4 nsec
(6 MHz)
[3]
H
[0]
L
[1]
L
[2]
H
[3]
L
[0]
H
[1]
L
[2]
H
[3]
H
[0]
H
[1]
L
[2]
H
[3]
L
[0]
L
[1]
H
[2]
H
[3]
H
[0]
L
[1]
H
[2]
H
[3]
L
[0]
H
[1]
H
[2]
H
[3]
H
[0]
H
[1]
H
[2]
H
[3]
BLKC
C4
31
The SHAMP frequency characteristics can be adjusted by changing the register settings
and the C4 value of the external 31st pin.
The settings are shown in table 7.
Values other than those shown in the table 7 cannot be used.
8.
SHSW-fsel (Register setting)
CR Time Constant (Typ)
(cutoff frequency conversion)
Table 7 SHAMP Frequency Characteristics Setting
49 MHz
15000 pF
(620 pF)
24 MHz
27000 pF
(820 pF)
32 MHz
22000 pF
(750 pF)
SHA-fsel (Register setting)
LoPwr
(Register setting)
Note: Upper line
Middle line
Lower line
: SHAMP cutoff frequency (Typ)
: Standard value of C4 (maximum value is not defined)
: Minimum value of C4 (do not set below this value)
56 MHz
18000 pF
(360 pF)
116 MHz
10000 pF
(270 pF)
"Lo"
"Hi"
75 MHz
13000 pF
(300 pF)
H
[0] L
[1] L
[0] H
[1] H
[0] H
[1]
HD49330AF/AHF
Rev.1.0, Apr.05.2004, page 10 of 19
Timing Chart
Figure 2 shows the timing chart when CDSIN and ADCIN input modes are used.
~
D0 to D11
D0 to D11
Note: The phases of SPBLK and SPSIG are those when the serial data SPinv bit is set to low.
0 1 2 111213
N+1 N+2 N+11 N+12 N+13N
N−11 N−10 N−1N
CDSIN
SPBLK
SPSIG
ADCLK
N+2 N+10 N+11 N+12 N+13
N−10N−11 N−1
ADCIN
ADCLK
N N+1
NN+1
N−12
• When CDSIN input mode is used
• When ADCIN input mode is used
Figure 2 Output Timing Chart when CDSIN and ADC IN Input Modes are Used
• The ADC output (D0 to D11) is output at the rising edge of the ADCLK in both modes.
• Pipe-line delay is twelve clock cycles when CDSIN is used and eleven when ADCIN is used.
• In ADCIN input mode, the input sig nal is sampled at the rising edge of the ADC LK.
HD49330AF/AHF
Rev.1.0, Apr.05.2004, page 11 of 19
Detailed Timing Specifications
Detailed Timing Specifications when CDSIN Inp ut Mode is Used
Figure 3 shows the detailed timing specifications when the CDSIN input mode is used, and table 8 shows each timing
specification.
CDSIN
Note:
SPBLK Vth
(2) (3)
SPSIG
ADCLK (7)
Vth
Vth
(8)
(9)
(10)
Black
level Signal
level
(4)
(1)
(5)
(6)
D0 to D11
1. When serial data Spinv bit is set to low. (When the Spinv bit is set to high, the polarities
of the SPBLK and the SPSIG are inverted.)
Figure 3 Detailed Timing Chart when CDSIN Input Mode is Used
Table 8 Timing Specifications when t he CDSIN Input M ode is Used
No. Timing Symbol Min Typ Max Unit
(1) Black-level signal fetch time tCDS1 — (1.5) — ns
(2) SPBLK low period *1 t
CDS2 Typ × 0.8 1/4fCLK Typ × 1.2 ns
(3) Signal-level fetch time tCDS3 — (1.5) — ns
(4) SPSIG low period *1 t
CDS4 Typ × 0.8 1/4fCLK Typ × 1.2 ns
(5) SPBLK rising to SPSIG rising time *1 t
CDS5 Typ × 0.85 1/2fCLK Typ × 1.15 ns
(6) SPSIG rising to ADCLK rising inhibition time *1 t
CDS6 1 5 9 ns
(7), (8) ADCLK tWH min./t WL min. tCDS7, 8 11 — — ns
(9) ADCLK rising to digital output hold time tCHLD9 3 7 — ns
(10) ADCLK rising to digital output delay time tCOD10 — 16 24 ns
Note: 1. SPBLK and SPSIG polarities when serial data Spinv bit is set to low.
OBP Detailed Timing Specifications
Figure 4 shows the OBP detailed timing specifications.
The OB period is from the fifth to the twelfth clock cycle after the OB pulse is input. The average of the black signal
level is taken for eight input cycles during the OB period and becomes the clamp level (DC standard).
CDSIN
OBP
Note:
OB pulse > 2 clock cycles
When serial data OBPinv bit is set to low
(When the OBPinv is set to high, the polarity of the OBP is inverted.)
OB period *
1
1. Shifts ±1 clock cycle depending on the OBP input timing.
N N+1 N+5 N+12 N+13
This edge is used, when OBP pulse-width period is clamp-on.
Figure 4 OBP Detailed Timing Specifications
HD49330AF/AHF
Rev.1.0, Apr.05.2004, page 12 of 19
Detailed Timing Specifications at Pre-Blanking
Figure 5 shows the pre-blanking detailed timing specifications.
Digital output
(D0 to D11) ADC
data Clamp level ADC
data
PBLK
t
PBLK
ADCLK × 2 clocks ADCLK × 12 clocks
(shifts one clock cycle depending
on the PBLK input timing)
When serial data SPinv bit is set to low
(When the SPinv is set to high, the PBLK polarity is inverted.)
Vth
V
OL
V
OH
Figure 5 Detailed Timing Specifications at Pre-Blanking
Detailed Timing Specifica tions when ADCIN Input Mo de is Used
Figure 6 shows the detailed timing chart when ADCIN input mode is used, and table 9 shows each timing specification.
ADCIN (1)
ADCLK
D0 to D11
(2) Vth
VDD/2
(3)
(5)
(4)
Figure 6 Detailed Timing C ha rt when ADCIN Input Mode is Used
Table 9 Timing Specifications when ADCIN Input Mode is Used
No. Timing Symbol Min Typ Max Unit
(1) Signal fetch time tADC1 — (6) — ns
(2), (3) ADCLK tWH min./t WL min. tADC2, 3 Typ × 0.85 1/2fADCLK Typ × 1.15 ns
(4) ADCLK rising to digital output hold time tAHLD4 10 14.5 — ns
(5) ADCLK rising to digital output delay time tAOD5 — 23.5 31.5 ns
Detailed Timing Specifications for Dig ital Output-Enable Control
Figure 7 shows the detailed timing specifications for digital output enable control. When the OEB pin is set to high,
output disable mode is entered, and the output state becomes High-Z.
Digital output
(D0 to D11)
OEB
t
LZ
t
ZL
t
HZ
t
ZH
DV
DD
/2
DV
DD
/2
DV
DD
2 kΩ
10 pF
DV
DD
DV
SS
DV
SS
V
OL
t
LZ
, t
ZL
measurement load
t
HZ
, t
ZH
measurement load
V
OH
Vth
DV
SS
10 pF 2 kΩ
DV
SS
Figure 7 Detailed Timing Specifications for Digital Output Enable Control
HD49330AF/AHF
Rev.1.0, Apr.05.2004, page 13 of 19
Serial Interface Specifications
Resister 2Resister 0 Resister 4 to 7
Test Mode (can not be used)
Resister 3Resister 1
Low Low to High
Low to High
SHA-fsel [0] (LSB)
SHA-fsel [1] (MSB)
SHSW-fsel [0] (LSB)
Low: Normal operation mode
High: Sleep mode
SLP
Low: Normal operation mode
High: Standby mode
STBY
Low: CDSIN input mode
High: YIN input mode
CSEL
Low: CDSIN input mode
High: YIN input mode
YSEL
Timing Specifications
Table 10 Serial Data Function List
SCK
CS
SDATA DI
00
DI
01
DI
02
DI
03
DI
04
DI
05
DI
06
DI
07
DI
08
DI
09
DI
10
DI
11
DI
12
DI
13
DI
14
DI
15
Latches SDATA
at SCK rising edge
Data is determined
at CS rising edge
t
INT
1
t
ho
t
su
t
INT
2f
SCK
Figure 8 Serial Interface Timing Specifications
DI 00 (LSB)
DI 01
Low
Low
High
Low
Low Low
Low
High
High
Low High
High
DI 02
X
DI 03
DI 04
DI 05
DI 06
DI 07
DI 08
DI 09
DI 10
DI 11
DI 12
DI 13
DI 14
DI 15 (MSB)
PGA gain setting *5
PGA gain setting (LSB) *5
PGA gain setting *5
PGA gain setting *5
PGA gain setting *5
PGA gain setting *5
PGA gain setting *5
PGA gain setting *5
PGA gain setting *5
PGA gain setting (MSB) *5
Cannot be used. *8
Cannot be used. *8
Cannot be used. *8
Cannot be used. *8
Cannot be used. *8
Cannot be used. *8
Low
Low
Low
High
High
Low
tsu
tho
tINT1, 2
fSCK
50 ns
50 ns
50 ns
Min
5 MHz
Max
Notes: 1.
2.
3.
4.
5.
6.
7.
8.
2 byte continuous communications.
SDATA is latched at SCK rising edge.
Insert 16 clocks of SCK while CS is low.
Data is invalid if data transmission is aborted during transmission.
The gain conversion table differs in the CDSIN input mode and the ADCIN input mode.
STBY: Reference voltage generator circuit is in the operating state.
SLP: All circuits are in the sleep state.
This bit is used for the IC testing, and cannot be used by the user.
Please do not set up in addition to "ALL Low".
This bit is used for the IC testing, and cannot be used by the user.
It is set to the state on the right of a column when RESET bit is set to low. The register
3 should transmit by setup on the right of a column.
Output mode setting (LINV)
Output mode setting (MINV)
Output mode setting (TEST0)
SHAMP
frequency
character-
istics
switching
SHSW-fsel [1]
SHSW-fsel [2]
SHSW-fsel [3] (MSB)
SHSW
frequency
character-
istics
switching
HGstop-Hsel [1]
HGain-Nsel [0]
Clamp-level [3]
Clamp-level [2]
Clamp-level [1]
Clamp-level [0] (LSB)
Clamp-level [4] (MSB)
HGstop-Hsel [0]
HGain-Nsel [1]
Low: Normal mode
High: Low power mode
LoPwr
SPinv,
SPSIG/SPBLK/PBLK inversion
OBPinv, OBP inversion
Low: Reset mode
High: Normal operation mode
RESET
High-speed
lead-in
cancellation
time
High-speed
lead-in
gain
multiplication
YC-Bias off
Output mode setting (TEST1)
Cannot be used. *7
All low
Cannot be used. *7
All low
Cannot be used. *7
All low
Cannot be used. *7
All low
Average4, 4 lines average
HD49330AF/AHF
Rev.1.0, Apr.05.2004, page 14 of 19
Absolute Maximum Ratings
(Ta = 25°C)
Item Symbol Ratings Unit
Power supply voltage VDD(max) 4.1 V
Analog input voltage VIN(max) –0.3 to AVDD +0.3 V
Digital input voltage VI(max) –0.3 to DVDD +0.3 V
Operating temperature Topr –10 to +75 °C
Power dissipation Pt(max) 400 mW
Storage temperature Tstg –55 to +125 °C
Power supply voltage range Vopr 2.85 to 3.3 V
Notes: 1. VDD indicates AVDD and DVDD.
2. AVDD and DVDD must be commonly connected outside the IC. When they are separated by a noise filter, the
potential difference must be 0.3 V or less at power on, and 0.1 V or less during operation.
Electrical Characteristics
(Unless othewide specified, Ta = 25°C, AVDD = 3.0 V, DVDD = 3.0 V, and RBIAS = 33 kΩ)
• Items Common to CDSIN and ADCIN Input Modes
Item Symbol Min Typ Max Unit Test Conditions Remarks
Power supply volt age
range VDD 2.85 3.0 3.3 V
fCLK low 5.5 — 20 MHz LoPwr = high Conversion frequency fCLK hi 20 — 36 MHz LoPwr = low
VIH
DV
DD
3.0
2.0 ×
— DVDD V
VIL 0 —
DV
DD
3.0
0.8 ×
V
Digital i nput pins
other than CS,
SCK and SDATA
VIH2
DV
DD
3.0
2.25 ×
— DVDD V
Digital i nput vol t age
VIL2 0 —
DV
DD
3.0
0.6 ×
V
CS, SCK , SD ATA
VOH DVDD –0.5 — — V IOH = –1 m A Digital output voltage VOL — — 0.5 V IOL = +1 m A
IIH — — 50 µA VIH = 3.0 V
IIH2 — — 250 µA VIH = 3.0 V
Digital i nput current
IIL –50 — — µA VIL = 0 V
IOZH — — 50 µA VOH = VDD Digital output current IOZL –50 — — µA VOL = 0 V
ADC resolution RES 12 12 12 bit
ADC integral linearity INL — (8) — LSBp-p fCLK = 20 MHz
ADC differenti al lineari ty+ DNL+ — 0.6 0.95 LSB fCLK = 20 MHz *1
ADC differenti al lineari ty– DNL– –0.95 –0.6 — LSB fCLK = 20 MHz *1
Sleep current ISLP –100 0 100 µA Di gital input pin is
set to 0 V, output
pin is open
Standby current ISTBY — 3 5 mA Digital I/O pin is set
to 0 V
tHZ — — 100 ns
tLZ — — 100 ns
tZH — — 100 ns
Digital output Hi-Z
delay time
tZL — — 100 ns
RL = 2 kΩ,
CL = 10 pF See figure 7
Notes: 1. Differential linearity is the calculated difference in linearity errors between adjacent codes.
2. Values within parentheses ( ) are for reference.
HD49330AF/AHF
Rev.1.0, Apr.05.2004, page 15 of 19
Electrical Characteristics (cont.)
(Unless othewide specified, Ta = 25°C, AVDD = 3.0 V, DVDD = 3.0 V, and RBIAS = 33 kΩ)
• Items for CDSIN Input Mode
Item Symbol Min Typ Max Unit Test Conditions Remarks
Consumpti on current (1) I DD1 — 54 65 mA LoPwr = low
fCLK = 36 MHz
Consumpti on current (2) I DD2 — 28 35 mA LoPwr = high
fCLK = 20 MHz
CCD offset tolerance range VCCD (–100) — (100) mV
Timing specifications (1) tCDS1 — (1.5) — ns
Timing specifications (2) tCDS2 Typ × 0.8 1/4fCLK Typ × 1.2 ns
Timing specifications (3) tCDS3 — (1.5) — ns
Timing specifications (4) tCDS4 Typ × 0.8 1/4fCLK Typ × 1.2 ns
Timing specifications (5) tCDS5 Typ × 0.85 1/2fCLK Typ × 1.15 ns
Timing specifications (6) tCDS6 1 5 9 ns
Timing specifications (7) tCDS7 11 — — ns
Timing specifications (8) tCDS8 11 — — ns
Timing specifications (9) tCHLD9 3 7 — ns
Timing specifications (10) tCOD10 — 16 24 ns
CL = 10 pF
See table 8
CLP(00) — (56) — LSB
CLP(09) — (128) — LSB
Clamp level
CLP(31) — (304) — LSB
AGC(0) –4.4 –2.4 –0.4 dB
AGC(256) 4.1 6.1 8.1 dB
AGC(512) 12.5 14.5 16.5 dB
AGC(768) 21.0 23.0 25.0 dB
PGA gain at CDS input
AGC(1023) 29.4 31.4 33.4 dB
Note : Values within parentheses ( ) are for reference.
• Items for ADCIN Input Mode
Item Symbol Min Typ Max Unit Test Conditions Remarks
Consumpti on current (3) I DD3 — 39 49 mA LoPwr = low
fCLK = 36 MHz
Consumpti on current (4) I DD4 — 21 26 mA LoPwr = high
fCLK = 20 MHz
Timing specifications (11) tADC1 — (6) — ns
Timing specifications (12) tADC2 Typ × 0.85 1/ 2fADCLK Typ × 1.15 ns
Timing specifications (13) tADC3 Typ × 0.85 1/ 2fADCLK Typ × 1.15 ns
Timing specifications (14) tAHLD4 — 14.5 — ns
Timing specifications (15) tAOD5 — 23.5 31.5 ns
CL = 10 pF
See table 9
Input current at ADC input IINCIN –110 — 110 µA VIN = 1.0 V to 2.0 V
Clamp level at ADC input OF2 — (2048) — LS B
Clamp level at YIN input OF1 — (280) — LSB
GSL(0) 0.45 0.57 0.72 Times
GSL(256) 1.36 1.71 2.16 Times
GSL(512) 2.27 2.86 3.60 Times
GSL(768) 3.18 4.00 5.04 Times
PGA gain at ADC input
GSL(1023) 4.08 5.14 6.47 Times
Note : Values within parentheses ( ) are for reference.
HD49330AF/AHF
Rev.1.0, Apr.05.2004, page 16 of 19
Operation Sequence at Power On
V
DD
HD49330AF/AHF
serial data transfer
RESET bit
RESET = "Low"
(RESET mode) RESET = "High"
(RESET cancellation)
Must be stable within the operating
power supply voltage range
SPBLK
SPSIG
ADCLK
OBP
etc.
Start control
of TG and
camera DSP
0 ms
or more
(1) Register 2 setting
(2) Register 2 setting
(3) Register 0, 1 and 3 settings
: Set all bits in register 2 to the usage condition, and set the RESET bit to low.
: Cancel the RESET mode by setting the register 2 RESET bit to high.
Do not change other register 2 settings. Offset calibration starts automatically.
: After the offset calibration is terminated, set registers 0, 1 and 3.
(1) Register 2 setting (2) Register 2 setting
(3) Registers 0, 1
and 3 settings
0 ms
or more
0 ms
or more
2 ms or more
2 ms or more
Ends after 40000 clock cycles
Automatic offset
calibration
The following describes the above serial data transfer. For details on registers 0, 1, 2, and 3, refer to table 10.
Offset calibration
(automatically starts
after RESET cancellation)
HD49330AF/AHF
Rev.1.0, Apr.05.2004, page 17 of 19
Notice for Use
1. Careful handling is necessary to prevent damage due to static electricity.
2. T his product has been developed for consumer applications, and should not be used in non-consumer applications.
3. As this IC is sensitive to power line noise, the ground impedance should be kept as small as possible. Also, to
prevent latchup, a ceramic capacitor of 0.1 µF or more and an electrolytic capacitor of 10 µF or more should be
inserted between the ground and power supply.
4. Common connection of AVDD and DVDD should be made off-chip. If AVDD and DVDD are isolated by a noise filter,
the phase difference should be 0.3 V or less at power-on and 0.1 V or less during operation.
5. If a noise filter is necessary, make a common connection after passage through the filter, as shown in the figure
below.
HD49330AF/AHF
AV
SS
DV
SS
AV
DD
DV
DD
Noise filter
Analog
+3.0V
HD49330AF/AHF
DV
SS
AV
SS
DV
DD
AV
DD
100 µH
0.01 µF
Noise filter Example of noise filter
Digital
+3.0V
0.01 µF
6. Connect AVSS and DVSS off-chip using a common ground. If there are separate analog system and digital system
set grounds, connect to the analog system.
7. When VDD is specified in the data sheet, this indicates AVDD and DVDD.
8. No Connection (NC) pins are not connected inside the IC, but it is recommended that they be connected to power
supply or ground pins or left open to prevent crosstalk in adjacent analog pins.
9. To ensure low thermal resistance of the package, a Cu-type lead material is used. As this material is less tolerant of
bending than Fe-type lead material, careful handling is necessary.
10. The infrared reflow soldering method should be used to mount the chip. Note that general heating methods such as
solder dipping cannot be used.
11. Serial communication should not be performed during the effective video period, since this will result in degraded
picture quality. Also, use of dedicated ports is recommend ed for the SCK and SDATA signals used in the
HD49330AF. If ports are to be shared with another IC, picture quality should first be thoroughly checked.
12. At power-on, automatic adjustment of the offset voltage generated from PGA, ADC, etc., must be implemented in
accordance with the power-on operating sequence (see page 16).
HD49330AF/AHF
Rev.1.0, Apr.05.2004, page 18 of 19
Example of Recommended External Circuit
R11 100
R12 100
R13 100
R10 100
C20
0.1
C18
0.1 C19
0.1
C17
0.1
L1
47 µ
• At CDS Input
Notes: 1. For C4, see table 5.
2. For C3, see page 8 "DC Offset Compensation Feedback Function".
Unit: R: Ω
C: F
23
26
27
28
29
30
31
32
33
34
C4*
1
C14 0.1
R15 33 k
C15 0.1
35
36
25 11
10
9
8
7
6
5
4
3
2
1
12
16 15 14 1317181920212224
38 45 46 47 4844434241403937
Serial data input
GND
from
Timing generator
from CCD out
Note: External circuit is same as above except for ADC/Y input.
3.0 V
3.0 V
to
Camera
signal
processor
to
Camera
signal
processor
C21
0.1 C22
0.1
C20
0.1
C18
0.1 C19
0.1
C17
0.1 C21
0.1 C22
0.1
C13
0.1
C1
1 µC3
*2
1 µ
C10
0.1
C11
0.1
C12
0.1
C11
0.1
C12
0.1
R15 33 k
C16
47/6 C21
47/6
L2
47 µ
R14 100
HD49330AF/AHF
(CDS/PGA+ADC)
L1
47 µ
• At ADC/Yin Input
VRM
VRT
VRB
DVDD
DVSS
OEB
DVDD
DVDD
DVSS
CS
SDATA
SCK
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DVDD
(NC)
SPSIG
SPBLK
OBP
PBLK
DVDD
DVDD
ADCLK
DVSS
DVSS
DRDVDD
AV
SS
AV
SS
AV
DD
BLKSH
BLKFB
CDSIN
BLKC
BIAS
AV
DD
Y IN
AV
SS
ADCIN
23
26
27
28
29
30
31
32
33
34
C15 0.1
35
36
25 11
10
9
8
7
6
5
4
3
2
1
12
16 15 14 1317181920212224
38 45 46 47 4844434241403937
Serial data input
GND
from
Timing generator
C14 0.1
C13
0.1
C2 2.2/16
C16
47/6 C21
47/6
L2
47 µ
HD49330AF/AHF
(CDS/PGA+ADC)
+
−
C23 0.47
with Y input
AV
SS
AV
SS
AV
DD
BLKSH
BLKFB
CDSIN
BLKC
BIAS
AV
DD
Y IN
AV
SS
ADCIN
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DVDD
(NC)
SPSIG
SPBLK
OBP
PBLK
DVDD
DVDD
ADCLK
DVSS
DVSS
DRDVDD
VRM
VRT
VRB
DVDD
DVSS
OEB
DVDD
DVDD
DVSS
CS
SDATA
SCK
with ADC input
HD49330AF/AHF
Rev.1.0, Apr.05.2004, page 19 of 19
Package Dimensions
Package Code
JEDEC
JEITA
Mass
(reference value)
FP-48C
—
Conforms
0.2 g
*Dimension including the plating thickness
Base material dimension
9.0 ± 0.2
7.0
*0.21 ± 0.05 0.08
36 25
112
37
48
24
13
0.5
9.0 ± 0.2
0.10
1.00
0˚ – 8˚
0.50 ± 0.10
*0.17 ± 0.05
1.70 Max
M
0.75 0.75
0.19 ± 0.04
1.40
0.15 ± 0.04
0.13
+0.09
–0.05
As of January, 2003
Unit: mm
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