PI6C49004 Networking Clock Generator Description Features The PI6C49004 is a clock generator device intended for PCIe(R)/ networking applications. The device includes twelve 100MHz differential Host Clock Signal Level (HCSL) outputs for PCIe, two single-ended 50MHz outputs, one single-ended 32.256MHz output, and one selectable single-ended 33/66/133MHz output. * 3.3V +/-10% Supply Voltage * Uses 25MHz xtal such as Saronix-eCeraTM SRX7278 * Twelve PCIe(R) 100MHz outputs with optional -0.5% spread spectrum support * Two LVCMOS 50MHz outputs that support +/- 10% frequency margining * One frequency selectable 33/66/133MHz LVCMOS output * One 32.256MHz LVCMOS output * Industrial temperature -40C to 85C * Package: 56-pin TSSOP package Using a serially programmable SMBUS interface, the PI6C49004 incorporates spread spectrum modulation on the twelve 100MHz HCSL PCIe outputs, and independent frequency margining on the 50MHz output, 33.3333MHz and 66.6666MHz clock outputs. Pin Configuration Block Diagram VDD 12 25 MHz crystal or clock input Clock Buffer/ Crystal Oscillator 12 2 PLL, Dividers, Buffers, and Logic 100M_OUT(0-11) 50M_OUT(1-2) 33/66/133M_OUT1 SCLK 32.256M_OUT1 SDATA PD_RESET 8 GND 11-0080 09-0098 ISET 475 Ohms 1% 1 VDD 1 56 GND IREF 2 55 VDD NC 3 54 100M_Q0- 100M_Q11- 4 53 100M_Q0+ 100M_Q11+ 5 52 100M_Q1+ 100M_Q10- 6 51 100M_Q1- 100M_Q10+ 7 50 VDD VDD 8 49 GND VDD 9 48 VDD GND 10 47 100M_Q2+ 100M_Q9- 11 46 100M_Q2- 100M_Q9+ 12 45 100M_Q3+ 100M_Q8- 13 44 100M_Q3- 100M_Q8+ 14 43 100M_Q4+ 100M_Q7- 15 42 100M_Q4- 100M_Q7+ 16 41 100M_Q5+ SCLK 17 40 100M_Q5- SDATA 18 39 VDD GND 19 38 GND 50M_OUT1 20 37 VDD 50M_OUT2 21 36 100M_Q6+ VDD 22 35 100M_Q6- GND 23 34 33/66/133M_OUT1 VDD 24 33 VDD 32.256M_OUT1 25 32 GND GND 26 31 VDD NC 27 30 X2 PD_RESET 28 29 X1 PS9047A 04/11/11 PI6C49004 Networking Clock Generator Pin Description Pin # 1 2 3 4 5 6 7 8 9 Pin Name VDD IREF NC 100M_Q11100M_Q11+ 100M_Q10100M_Q10+ VDD VDD Pin Type Power Output Output Output Output Output Power Power Pin Description 3.3V Supply Pin Connect to 475-Ohm resistor to set HCSL output drive current No connect. Leave open 100MHz HCSL output 100MHz HCSL output 100MHz HCSL output 100MHz HCSL output 3.3V Supply Pin 3.3V Supply Pin 10 GND Power Ground 11 12 100M_Q9100M_Q9+ Output Output 100MHz HCSL output 100MHz HCSL output 13 100M_Q8- Output 100MHz HCSL output 14 15 16 17 100M_Q8+ 100M_Q7100M_Q7+ SCLK Output Output Output Input 100MHz HCSL output 100MHz HCSL output 100MHz HCSL output SMBus compatible input clock. Supports fast mode 400kHz input clock. 18 SDATA I/O SMBus compatible data line 19 GND Power 20 50M_Out1 Output 21 50M_Out2 Output 22 23 24 VDD GND VDD Power Power Power 25 32.256M_Out1 Output Ground 50MHz LVCMOS output. When disabled, output is trisated and has a nominal 110kOhm pull-down. 50MHz LVCMOS output. When disabled, output is trisated and has a nominal 110kOhm pull-down. 3.3V Supply Pin Ground 3.3V Supply Pin 32.256MHz LVCMOS output. When disabled, output is trisated and has a nominal 110k-Ohm pull-down. 26 GND Power GND 27 NC 28 PD_RESET Input 29 X1 Input No connect. Leave open Power down reset - when low all PLL's are powered down and outputs tristated. SMBus registers are reset to default values. Crystal input. Integrated 6pF capacitance 30 X2 Output Crystal output. Integrated 6pF capacitance 31 32 33 VDD GND VDD Power Power Power 34 33/66/133M_Out1 Output 3.3V Supply Pin GND Connect to 3.3V 33/66/133MHz selectable LVCMOS output. When disabled, output is trisated and has a nominal 110k-Ohm pull-down. 100MHz HCSL output 35 100M_Q6(Continued) 11-0080 Output 09-0098 2 PS9047A 04/11/11 PI6C49004 Networking Clock Generator Pin # 36 37 38 39 40 41 42 43 44 45 46 47 Pin Name 100M_Q6+ VDD GND VDD 100M_Q5100M_Q5+ 100M_Q4100M_Q4+ 100M_Q3100M_Q3+ 100M_Q2100M_Q2+ Pin Type Output Power Power Power Output Output Output Output Output Output Output Output Pin Description 100MHz HCSL output 3.3V Supply Pin Ground 3.3V Supply Pin 100MHz HCSL output 100MHz HCSL output 100MHz HCSL output 100MHz HCSL output 100MHz HCSL output 100MHz HCSL output 100MHz HCSL output 100MHz HCSL output 48 VDD Power 3.3V Supply Pin 49 GND Power Ground 50 VDD Power 3.3V Supply Pin 51 100M_Q1- Output 100MHz HCSL output 52 100M_Q1+ Output 100MHz HCSL output 53 100M_Q0- Output 100MHz HCSL output 54 100M_Q0+ Output 100MHz HCSL output 55 VDD Power 3.3V Supply Pin 56 GND Power Ground 50MHz Frequency Margining Table FS3 FS2 FS1 FS0 50M_OUT1, 50M_OUT2 0 0 0 0 nominal 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 11-0080 33/66/133 MHz Frequency Margining Table nominal + 1% nominal + 2% FS6 0 0 0 FS5 0 0 1 FS4 0 1 0 33M/66M/133M_OUT1 33.3333MHz 66.6666MHz +2% 66.6666MHz +1% 1 nominal + 3% 0 1 1 66.6666MHz +0% 0 0 1 0 1 0 nominal + 4% nominal + 5% nominal + 6% 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 nominal + 8% nominal + 10% nominal - 1% nominal - 2% nominal - 3% nominal - 4% nominal - 6% nominal - 8% nominal - 10% 1 1 1 1 0 0 1 1 0 1 0 1 66.6666MHz -2% 66.6666MHz -4% 66.6666MHz -6% 133.3333MHz 09-0098 3 PS9047A 04/11/11 PI6C49004 Networking Clock Generator Serial Data Interface (SMBus) PI6C49004 is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit address and read/write bit as shown below. Address Assignment A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 1 0 0 1 0/1 How to Write 1 bit 8 bits 1 8 bits 1 8 bits 1 8 bits 1 Start bit D2H Ack Register offset Ack Byte Count = N Ack Data Byte 0 Ack ... 8 bits 1 1 bit Data Byte N-1 Ack Stop bit Note: 1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0. How to Read (M: abbreviation for Master or Controller; S: abbreviation for slave/clock) 1 bit M: Start bit 8 bits M: Send "D2h" 1 bit S: sends Ack 8 bits M: send starting databyte location: N 1 bit S: sends Ack 1 bit M: Start bit 8 bits M: Send "D3h" 1 bit 8 bits S: sends Ack S: sends # of data bytes that will be sent: X 1 bit 8 bits M: sends Ack S: sends starting data byte N 1 bit M: sends Ack ... 8 bits 1 bit 1 bit ... S: sends data byte N+X1 M: Not Acknowledge M: Stop bit Byte 0: Spread Spectrum Control Register Bit Description Type Power Up Condition Output(s) Affected 7 Spread Spectrum Selection for 100MHz HCSL PCI-Express clocks RW 0 All 100MHz HCSL PCI Express outputs RW 0 PD_RESET pin, bit 5 RW 1 All outputs 0 = disabled 1 = enabled 50M_Out1 and 50M_Out2 See 50MHz Frequency Margining Table on Page 3 Single-ended 50MHz output 50M_Out2 0 = disabled 1 = enabled 6 5 Enables hardware or software control of OE bits (see Byte 0-Bit 6 and Bit 5 Functionality table) Software PD_RESET bit. Enables or disables all outputs (see Byte 0-Bit 6 and Bit 5 Functionality table) 4 Frequency margining select bit FS3 RW 1 3 2 Frequency margining select bit FS2 Frequency margining select bit FS1 RW RW 0 1 1 Frequency margining select bit FS0 RW 0 0 OE for single-ended 50MHz output 50M_Out2 RW 1 11-0080 09-0098 4 Notes 0=spread off 1 = -0.5% down spread 0 = hardware cntl 1 = software ctrl PS9047A 04/11/11 PI6C49004 Networking Clock Generator Byte 0 - Bit 6 and Bit 5 Functionality Bit 6 0 1 1 Bit 5 X 0 1 Description PD_RESET HW pin/signal = enabled Disables all outputs and tri-states the outputs, PD_RESET HW pin/signal = DO NOT CARE Enable all outputs, PD_RESET HW pin/signal = DON'T CARE Byte 1: Control Register Bit Description Type Power Up CondiOutput(s) Affected tion 7 OE for 32.256M_Out1 RW 1 32.256M_Out1 6 OE for 50M_Out1 RW 1 50M_Out1 5 OE for 33/66/133M_Out1 RW 1 33/66/133M_Out1 4 OE for 100M_Q11 HCSL output RW 1 100M_Q11 3 OE for 100M_Q10 HCSL output RW 0 100M_Q10 2 OE for 100M_Q09 HCSL output RW 0 100M_Q9 1 OE for 100M_Q08 HCSL output RW 0 100M_Q8 0 OE for 100M_Q07 HCSL output RW 0 100M_Q7 Notes 0 = disabled 1 = enabled 0 = disabled 1 = enabled 0 = disabled 1 = enabled 0 = disabled 1 = enabled 0 = disabled 1 = enabled 0 = disabled 1 = enabled 0 = disabled 1 = enabled 0 = disabled 1 = enabled Byte 2: Control Register Bit Description Type Power Up CondiOutput(s) Affected tion 7 Frequency margining select bit FS6 RW 1 6 Frequency margining select bit FS5 RW 0 33/66/133M_Out1 5 4 to 0 Frequency margining select bit FS4 Reserved RW R 0 Undefined Not Applicable 11-0080 09-0098 5 Notes See 33/66/133MHz Frequency Margining Table on Page 3 PS9047A 04/11/11 PI6C49004 Networking Clock Generator Byte 3: Control Register Bit Description Type Power Up Condition Output(s) Affected 7 OE for 100M_Q6 HCSL Output RW 0 100M_Q6 6 OE for 100M_Q5 HCSL Output RW 0 100M_Q5 5 OE for 100M_Q4 HCSL Output RW 0 100M_Q4 4 OE for 100M_Q3 HCSL Output RW 0 100M_Q3 3 OE for 100M_Q2 HCSL Output RW 0 100M_Q2 2 OE for 100M_Q1 HCSL Output RW 1 100M_Q1 1 OE for 100M_Q0 HCSL Output RW 1 100M_Q0 0 Reserved R Undefined Not Applicable Notes 0 = disabled 1 = enabled 0 = disabled 1 = enabled 0 = disabled 1 = enabled 0 = disabled 1 = enabled 0 = disabled 1 = enabled 0 = disabled 1 = enabled 0 = disabled 1 = enabled Byte 4 & 5: Control Register Bit Description Type Power Up CondiOutput(s) Affected tion 7 to 0 Reserved R Undefined Notes Not Applicable Byte 6: Control Register Bit Description Type Power Up CondiOutput(s) Affected tion 7 Revivsion ID bit 3 R 0 Not Applicable 6 Revivsion ID bit 2 R 0 Not Applicable 5 4 3 2 1 0 Revivsion ID bit 1 Revivsion ID bit 0 Vendor ID bit 3 Vendor ID bit 2 Vendor ID bit 1 Vendor ID bit 0 R R R R R R 0 0 0 0 1 1 Not Applicable Not Applicable Not Applicable Not Applicable Not Applicable Not Applicable 11-0080 09-0098 6 Notes PS9047A 04/11/11 PI6C49004 Networking Clock Generator Absolute Maximum Ratings1 (Over operating free-air temperature range) Symbol Parameters Min. Max. -0.5 4.6 VDD 3.3V I/O Supply Voltage VIH Input High Voltage VIL Input Low Voltage -0.5 Ts Storage Temperature -65 VESD ESD Protection 2000 Units 4.6 V 150 C V Note: 1. Stress beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Maximum Supply Voltage, VDD............................................................. 7V All Inputs and Outputs................................................-0.5V to VDD +0.5V Ambient Operating Temperature........................................ -40C to +85C Storage Temperature......................................................... -65C to +150C Junction Temperature.........................................................................125C Peak Soldering Temperature..............................................................260C Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC Electrical Characteristics Unless otherwise specified, VDD=3.3V10%, Ambient Temperature -40C to +85C Parameter Operating Supply Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Operating Supply Current IDD at Output Disable Condition Symbol Min Typ Max VDD 3.0 3.6 VIH VIL VIH SDATA, SCLK 2 -0.3 0.7VDD VDD 0.8 VDD VIL SDATA, SCLK Input Capacitance CIN 09-0098 V 320 mA PD_RESET = 0 RPU/RPD Units 0.3VDD IDD Internal Pull-Up/PullDown Resistor 11-0080 Conditions 3.3 PD_RESET 216 All single-ended outputs 75 All input pins 6 7 k-Ohm pF PS9047A 04/11/11 PI6C49004 Networking Clock Generator Electrical Characteristics - Single-Ended Unless otherwise specified, VDD=3.3V10%, Ambient Temperature -40C to +85C Parameter Symbol Input Clock Frequency FIN Conditions Min 100 Units MHz 400 kHz 100 FS0, FS6 = 0 ns 0 ppm 32.256MHz tr, tf 7 VDD=3.3V, 0.8V to 2.4V Measured at VDD/2 45 VOH IOH = -4mA VDD-0.4 VOH IOH = -8mA 2.4 VOL IOL = 8mA Peak-to-Peak Jitter Cycle-to-Cycle Jitter 1 ns 50 55 % V 50MHz clock output 140 200 33/66/133MHz clock output 125 175 32.256MHz clock output 115 150 50MHz clock output 33/66/133 MHz clock output 120 175 120 160 3 09-0098 0.5 0.4 Clock Stabilization Time from Power Up 11-0080 Max 25 SCLK Frequency Minimum Pulse Width of PD_RESET Input Output Frequency Error Output Frequency Error Output Rise/Fall Time Output Clock Duty Cycle High-Level Output Voltage High-Level Output Voltage Low-Level Output Voltage Typ 8 ps 10 ms PS9047A 04/11/11 PI6C49004 Networking Clock Generator Electrical Characteristics - 100MHz Differential HCSL Outputs Unless otherwise specified, VDD=3.3V10%, Ambient Temperature -40C to +85C Parameter Symbol Conditions Min Typ Output Frequency Cycle-to-Cycle Jitter Peak-to-Peak Phase Jitter Spread Modulation Percentage TCC/Jitter Clock Source DC Impedance, single ended High-Level Output Voltage 100 MHz ps 86 -0.5 0 % 32 TDC Rising/Falling Edge Rate Output Skew Units 150 Using PCIe jitter measurement method Spread Modulation Frequency Duty Cycle Max 45 Note 3, 4 TOSKEW 0.6 VT = 50%(measurement threshold) ZC-DC VOH 50 kHz 55 % 4.0 V/ns 200 ps 50 Note 2, (RS=33-Ohm, RT=50-Ohm) Ohm 0.65 0.71 0.85 V Low-Level Output Voltage VOL -0.20 0 0.05 IOH @ 6*IREF IOH -13 -14.2 -17 mA 0.55 V 140 mV Absolute Crossing Point Voltage Variation of VCROSS over all rising clock edges Average Clock Period Accuracy Absolute Period (including jitter and spread spectrum) (Continued) 11-0080 VCROSS Note 2, 5, 6 0.25 VCROSS Delta Note 2, 5, 8 TPERIOD AVG Note 3, 9, 10 -300 2800 ppm TPERIOD ABS Note 3, 7 9.847 10.203 ns 09-0098 9 PS9047A 04/11/11 PI6C49004 Networking Clock Generator Notes: 1. Measured at the end of an 8-inch trace with a 5pF load. 2. Measurement taken from a single-ended waveform. 3. Measurement taken from a differential waveform. 4. Measured from -150 mV to +150 mV on the differential waveform. The signal is monotonic through the measurement region for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing. 5. Measured at crossing point where the instantaneous voltage value of the rising edge of 100M+ equals the falling edge 100M-. 6. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. 7. Defines as the absolute minimum or maximum instantaneous period. This includes cycle-to-cycle jitter, relative PPM tolerance, and spread spectrum modulation. 8. Defined as the total variation of all crossing voltages of rising 100M+ and falling 100M-. 9. Refer to section 4.3.2.1 of the PCI Express Base Specification, Revision 1.1 for information regarding PPM considerations. 10. 10) PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is 1/1,000,000th of 100 MHz exactly or 100 Hz. For 300 PPM there is an error budget of 100Hz/PPM * 300 PPM = 30 kHz. The period is measured with a frequency counter with measurement window set at 100 ms or greater. With spread spectrum turned off the error is less than 300 ppm. With spread spectrum turned on there is an additional +2500 PPM nominal shift in maximum period resulting from the -0.5% down spread. 11-0080 09-0098 10 PS9047A 04/11/11 PI6C49004 Networking Clock Generator Configuration test load board termination for HCSL Outputs Rs 33 5% PI6C49004 Clock TLA Rs 33 5% Clock# TLB 475 1% Rp 49.9 1% Rp 49.9 1% 2pF 5% 2pF 5% Figure 4. Configuration Test Load Board Termination 11-0080 09-0098 11 PS9047A 04/11/11 PI6C49004 Networking Clock Generator 1 DATE: 09/11/06 Notes: 1. Controlling dimensions in millimeters. 2. Ref: JEDEC MO-153F/EE 3. Package Outline Exclusive of Mold Flash and Metal Burr DESCRIPTION: 56-pin, 240-mil wide TSSOP PACKAGE CODE: A56 DOCUMENT CONTROL #: PD-1502 REVISION: M 06-0736 Note: * For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php Ordering Information(1-3) Ordering Code Package Code PI6C49004AE A Package Description 56-pin, Pb-free & Green, TSSOP, (A56) Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. E = Pb-free and Green 3. Adding an X suffix = Tape/Reel Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com 11-0080 09-0098 All trademarks are property of their respective owners. 12 PS9047A 04/11/11