This is information on a product in full production.
May 2013 DocID13866 Rev 6 1/18
ST2S06
Dual synchronous rectification with reset or inhibit, 0.5 A, 1.5 MHz
adjustable step-down switching regulator
Datasheet - production data
Features
Step-down current mode PWM (1.5 MHz) DC-
DC converter
Fixed or adjustable output voltage from 0.8 V
2% DC output voltage tolerance
Synchronous rectification
Reset function for A version
Inhibit function for B version
Internal soft start for startup current limitation
and power ON delay of 50-100 µs
Typical efficiency: > 90%
0.5 A output current capability
Non-switching quiescent current: max 1.2 mA
over temperature range
RDS(ON) 150 m (typ.)
Uses tiny capacitors and inductors
Available in QFN12L (4x4 mm)
Description
The ST2S06A33 and ST2S06B are dual step-
down DC-DC converters optimized for powering
low-voltage digit al cores in ODD applications and,
generally, to replace high current linear solutions
when the power dissipation may cause high
heating of the a pplication environment. It provides
up to 0.5 A over an input voltage range of 2.5 V to
5.5 V.
A high switching frequency of 1.5 MHz allows the
use of tiny surface-mount components as well as
a resistor divider to set the output voltage value.
Only an inductor and two ca p acitors ar e re quired.
A low output ripple is guaranteed by the current
mode PWM topology and the utilization of low
ESR SMD ceramic capacitors. The devices are
thermally protected and current-limited to prevent
damage due to accidental short-circuit. The
ST2S06A33 and ST2S06B are available in the
QFN12L (4x4 mm) p ackage.
QFN12L (4 x 4 mm)
Table 1. Device summary
Order codes Package Packaging
ST2S06A33PQR QFN12L (4 x 4 mm) Tape and reel
ST2S06BPQR
www.st.com
Contents ST2S06
2/18 DocID13866 Rev 6
Contents
1 Schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6 Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DocID13866 Rev 6 3/18
ST2S06 Schematic diagram
18
1 Schematic diagram
Figure 1. Schematic diagram
* ST2S06A33
** ST2S06B
Ref
CONTROL
LOGIC
Soft Start
GND
SW2
SW
RESET_OUT *
FB1
GND
VI_SW
VI_A
FB2
HV
Ref
Delay
Trimming
VI_SW
INH**
Ref
CONTROL
LOGIC
Soft Start
GND
SW2
SW
RESET_OUT *
FB1
GND
VI_SW
VI_A
FB2
HV
Ref
Delay
Trimming
VI_SW
INH**
Pin configuration ST2S06
4/18 DocID13866 Rev 6
2 Pin configuration
Figure 2. Pin connections (top view)
Table 2. Pin description
Pin n° ST2S06A33 ST2S06B Name and function
1 HV HV Programing pin. It must be floating or connected to GND.
2 FB2 FB2 Feedback voltage
3 GND2 GND2 Power ground
4 SW2 SW2 Switching pin
5 VIN_SW VIN_SW Power input voltage pin
6 SW1 SW1 Switching pin
7 GND1 GND1 Power ground
8 FB1/OUT1 FB1 Feedback voltage / output voltage
9 Reset_out NC Reset out pin
10 NC INH Inhibit pin
11 VIN_A VIN_A Supply for analog circuit
12 GND_A GND_A System ground
DocID13866 Rev 6 5/18
ST2S06 Maximum ratings
18
3 Maximum ratings
Note: Absolute maxim um ratings are those values beyond which damage to the device may occur .
Functional operation under these conditions is not implied.
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
VIN_SW Positive power supply voltage -0.3 to 7 V
VIN_A Positive power supply voltage -0.3 to 7 V
VINH Inhibit voltage -0.3 to 7 V
SWITCH voltage Max. voltage of output pin -0.3 to 7 V
VFB1,2/VO1 Feedback voltage/output voltage -0.3 to 2.5 V
VO1 Output voltage (for VO > 1.6 V) -0.3 to 5 V
Current into VFB
pin Common mode input voltage +1 to -1 mA
TJMax junction temperature 150 °C
TSTG Storage temperature range -65 to +150 °C
TLEAD Lead temperature (soldering) 10 sec. 300 °C
Table 4. Thermal data
Symbol Parameter Value Unit
RthJC Thermal resistance junction-case 10 °C/W
RthJA Thermal resistance junction-ambient 60 °C/W
Table 5. ESD performance
Symbol Parameter Test conditions V a lu e Unit
ESD ESD protection voltage HBM-DH11C 4 kV
Electrical charact eristics ST2S06
6/18 DocID13866 Rev 6
4 Electrical characteristics
VIN_SW = VIN_A = 5 V, V01 = 3.3 V, VO2 = 1.2 V, C1 = 4.7 µF, C2 = C3 = 22 µF, L1 = L2 = 3.3
µH, TJ = - 30 to 125 °C unless otherwise specified. Typical values are referred to 25 °C.
Table 6. Electrical characteristics for the ST2S06A33
Symbol Parameter Test conditions Min. Ty p. Max. Unit
OUT1Output feedback pin 3.23 3.3 3.37 V
FB2Feedback voltage 784 800 816 mV
IO1 IO1 pin bias current VO = 3.5 V 15 20 µA
IFB2 VFB pin bias current VFB = 1 V 600 nA
IQQuiescent current VFB = 1 V 1.2 mA
IO1,2 Output current VIN = 4 to 5.5 V (1) 0.8 A
IMIN Minimum output current 1 mA
%VO1,2/VI
NReferenc e li n e regulation 4V < VIN < 5.5 V 0.032 %VO/
VIN
VO1,2 Reference load regulation 10mA < IO < 0.5 A 5.5 15 mV
PWM fSPWM switching
frequency(1) VFB = 0.7 V, TA = 25°C 1.2 1.5 1.8 MHz
DMAX Maximum duty cycle VFB = 0.7 V, TA = 25°C 85 94 %
ISWL Switching current limitation 1 1.2 A
ILKN NMOS leakage current VFB = 0.9 V, TA = 25°C 0.1 µA
ILKP PMOS leakage current VFB = 0.9 V, TA = 25°C 0.1 µA
RDSon-N NMOS switch on resistance ISW = 250 mA 0.15 0.3 W
RDSon-P PMOS switch on resistance ISW = 250 mA 0.2 0.4 W
Efficiency IO = 20 mA to 100 mA 75 %
IO = 100 mA to 0.5 A 90 %
TSHDN Thermal shut down (2) 130 150 °C
THYS Thermal shut down
hysteresis (2) 15 °C
VO1,2/IOLoad transient response (2) 100 mA < IO < 500 mA
tR = tF => 100 ns, TA = 25°C -5 +5 %VO
Reset section
tDEL Delay time TA = 25°C 80 85 ms
VRES Reset in threshold
measured on input pin VIN_A Rising 4.5 4.6 4.75 V
VIN_A Falling 4.12 4.2 4.28
1. VO = 90% of nominal value.
2. Guaranteed by design, but not tested in production.
DocID13866 Rev 6 7/18
ST2S06 Electrical characteristics
18
VIN_SW = VIN_A = 5 V, VO1,2 =1.2 V, C1= 4.7 µF, C2 = C3 = 22 µF, L1 = L2 = 3.3 µH,
TJ = -30 to 125 °C unless otherwise specified. Typical values are referred to 25 °C.
Table 7. Electrical characteristics for the ST2S06B
Symbol Parameter Test conditions Min. Ty p. Max. Unit
FB1,2 Feedback voltage 784 800 816 mV
IFB1,2 VFB pin bias current VFB = 1 V 600 nA
IQQuiescent current VINH > 1.2 V, VFB = 1 V 1 mA
VINH < 0.4 V 1 µA
IO1,2 Output current VIN = 2.5 to 5.5 V (1) 0.8 A
IMIN Minimum output current 1 mA
VINH Inhibit threshold
2.5V < VIN < 5 V 1.2
2.5V < VIN < 5.5 V 1.3 V
Device OFF 0.4
IINH1,2 Inhibit pin current 2 µA
%VO1,2/
VIN Reference line regul ation 2.5V < VIN < 5.5 V 0.032 %VO/
VIN
VO1,2 Reference load regulation 10 mA < IO < 0.5 A 5.5 15 mV
PWM fSPWM switching
frequency(1) VFB = 0.7 V, TA = 25°C 1.2 1.5 1.8 MHz
DMAX Maximum duty cycle VFB = 0.7 V, TA = 25°C 85 94 %
ISWL Switching current limitation 1 1.2 A
ILKN NMOS leakage current VFB = 0.9 V, TA = 25°C 0.1 µA
ILKP PMOS leakage current VFB = 0.9 V, TA = 25°C 0.1 µA
RDSon-N NMOS switch on resistance ISW = 250 mA 0.15 0.3 W
RDSon-P PMOS switch on resistance ISW = 250 mA 0.2 0.4 W
Efficiency IO = 20 mA to 100 mA 75 %
IO = 100 mA to 0.5 A 90 %
TSHDN Thermal shut down (2) 130 150 °C
THYS Thermal shut down
hysteresis (1) 15 °C
VO1,2/IOLoad transient response (1) 100 mA < IO < 500 mA,
tR = tF1 => 100 ns, TA = 25°C -5 +5 %VO
1. VO= 90% of nominal value.
2. Guaranteed by design, but not tested in production.
Typical performance character istics ST2S06
8/18 DocID13866 Rev 6
5 Typical performance characteristics
Figure 3. Fee d b ac k vo ltage 1 vs. tempe r at u re
(ST2S06B) Figure 4. Feedback voltage 2 vs. tempera ture
(ST2S06B)
Figure 5. Efficiency vs. output current 1 Figure 6. Efficiency vs. output current 2
Figure 7. Switching fre quency vs. temperature
(ST2S06A33) Figure 8. Duty cyc le vs . te mp era tur e
(ST2S06A33)
0.78
0.79
0.8
0.81
0.82
-50 -25 0 25 50 75 100 125
TEMPERATURE [°C]
V
FB1
[V]
V
I
=5V, V
FB1
connected to V
O1
I
O1
=I
O2
=NO LOAD
0.78
0.79
0.8
0.81
0.82
-50 -25 0 25 50 75 100 125
TEMPERATURE [°C]
V
FB1
[V]
V
I
=5V, V
FB1
connected to V
O1
I
O1
=I
O2
=NO LOAD
0.78
0.79
0.8
0.81
0.82
-50 -25 0 25 50 75 100 125
TEMPERATURE [°C]
V
FB2
[V]
V
I
=5V, V
FB2
connected to V
O2
I
O1
=I
O2
=NO LOAD
0.78
0.79
0.8
0.81
0.82
-50 -25 0 25 50 75 100 125
TEMPERATURE [°C]
V
FB2
[V]
0.78
0.79
0.8
0.81
0.82
-50 -25 0 25 50 75 100 125
TEMPERATURE [°C]
V
FB2
[V]
V
I
=5V, V
FB2
connected to V
O2
I
O1
=I
O2
=NO LOAD
V
I
=5V, V
O1
=3.3V, I
O2
NO LOAD
60
65
70
75
80
85
90
95
100
0 0.1 0.2 0.3 0.4 0.5 0.6
Output Current 1 [A]
EFFICIENCY [%]
V
I
=5V, V
O1
=3.3V, I
O2
NO LOAD
60
65
70
75
80
85
90
95
100
0 0.1 0.2 0.3 0.4 0.5 0.6
Output Current 1 [A]
EFFICIENCY [%]
40
45
50
55
60
65
70
75
80
85
90
95
100
0 0.1 0.2 0.3 0.4 0.5 0.6
Output Current 2 [A]
EFFICIENCY [%]
V
I
=5V, V
O2
=1.2V, I
O1
NO LOAD
40
45
50
55
60
65
70
75
80
85
90
95
100
0 0.1 0.2 0.3 0.4 0.5 0.6
Output Current 2 [A]
EFFICIENCY [%]
V
I
=5V, V
O2
=1.2V, I
O1
NO LOAD
V
I
=5V, V
FB1
=3.2V, V
FB2
=0.7V
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
-50 -25 0 25 50 75 100 125
Temperature [°C]
Frequency [MHz]
V
I
=5V, V
FB1
=3.2V, V
FB2
=0.7V
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
-50 -25 0 25 50 75 100 125
Temperature [°C]
Frequency [MHz]
DocID13866 Rev 6 9/18
ST2S06 Typical performanc e characteristics
18
Figure 9. Switching fre quency vs. temperature
(ST2S06B) Figure 10. Inhibit threshold vs. temperature
(ST2S06B)
Figure 11. Switching current limit ation vs. inp ut
voltage (ST2S06A33) Figure 12. PMOS switch on resistance vs.
temperature
Figure 13. NMOS switch on resistance vs.
temperature Figure 14. Delay time vs. temperature
(ST2S06A33)
VI Rising from 0V to 5V, Delay from VRES threshold and
reset pin below 0V.
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
-50 -25 0 25 50 75 100 125
Temperatu re [ °C]
Frequency [MHz]
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
-50 -25 0 25 50 75 100 125
Temperatu re [ °C]
Frequency [MHz]
VI=5V, IO1=IO2=100mA
0
0.2
0.4
0.6
0.8
1
1.2
1.4
-50 -25 0 25 50 75 100 125
T [C°]
V
INH
(V)
ON
OFF
VI=5V, IO1=IO2=100mA
0
0.2
0.4
0.6
0.8
1
1.2
1.4
-50 -25 0 25 50 75 100 125
T [C°]
V
INH
(V)
ON
OFF
VIfrom 2.5V to 5.5V, Output2 Maximum load Current
1
1.2
1.4
1.6
1.8
2
2.5 3 3.5 4 4.5 5 5.5
VI[V]
ISW2 [A]
VIfrom 2.5V to 5.5V, Output2 Maximum load Current
1
1.2
1.4
1.6
1.8
2
2.5 3 3.5 4 4.5 5 5.5
VI[V]
ISW2 [A]
V
CC
=5V, I
SW
=250mA
100
120
140
160
180
200
220
240
-50 -25 0 25 50 75 100 125
T [°C]
R
DSON
-P[mOhm]
V
CC
=5V, I
SW
=250mA
100
120
140
160
180
200
220
240
-50 -25 0 25 50 75 100 125
T [°C]
R
DSON
-P[mOhm]
VCC=5V, ISW=250mA
50
70
90
110
130
150
170
-50 -25 0 25 50 75 100 125
T [°C]
RDSON-N[mOhm]
VCC=5V, ISW=250mA
50
70
90
110
130
150
170
-50 -25 0 25 50 75 100 125
T [°C]
RDSON-N[mOhm]
V
I
V
RES
Typical performance character istics ST2S06
10/18 DocID13866 Rev 6
Figure 15. Delay time vs. temperature
(ST2S06A33) Figure 16. Reset in threshold vs. temperature
(ST2S06A33)
Figure 17. Load transient response
(ST2S06A33) Figure 18 . Startup transient (ST2S06 A33 )
VI= 5V, IO1 from 100mA to 500mA
VI= from 0V to 5V, IO1=500mA, Output Voltage=3.3V
V
I
Rising from 0V to 5V
50
55
60
65
70
75
80
85
90
95
100
-50 -25 0 25 50 75 100 125
T [C°]
T
DEL
(ms)
V
I
Rising from 0V to 5V
50
55
60
65
70
75
80
85
90
95
100
-50 -25 0 25 50 75 100 125
T [C°]
T
DEL
(ms)
Rising
Falling
4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5
-50 -25 0 25 50 75 100 125
T [C°]
V
RES
(V)
Rising
Falling
4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5
-50 -25 0 25 50 75 100 125
T [C°]
V
RES
(V)
IO1
VO1
VI
VO1
Figure 19. Startup transient (ST2S06B) Figure 20. Inhibit transient (ST2S06B)
VI= from 0V to 5V, IO1 =1A, Output Voltage=1.2V
VINH= from 0V to 2V, VI=5V, IO1=IO2=1A
V
I
V
O1
I
O1
VINH
VO1
VO2
DocID13866 Rev 6 11/18
ST2S06 Typical application
18
6 Typical application
Figure 21. Application circuit for the ST2S06A33
22µF
C2
V
O1
L1
V
IN
VIN_A
VIN_SW
C1
4.7 µF
SW2
R3
R4
C3
22µF
V
O2
3.3 µH
3.3 µHL2
GND2
R1
R2
Reset_Out
GND_A
VFB2
VFB1
SW1
GND1
NC
ST2S06A33
HV
Figure 22. Application circuit for ST2S06B
22µF
C2
V
O1
L1
V
IN
VIN_A
VIN_SW
C1
4.7µF
SW2 R3
R4 C3
22µF
V
O2
3.3µH
3.3µHL2
GND2
R1
R2
NC GND_A
VFB2
VFB1
SW1
GND1
INH
ST2S06B
HV
22µF
C2
V
O1
L1
V
IN
VIN_A
VIN_SW
C1
4.7µF
SW2 R3
R4 C3
22µF
V
O2
3.3µH
3.3µHL2
GND2
R1
R2
NC GND_A
VFB2
VFB1
SW1
GND1
INH
ST2S06B
HV
Application information ST2S06
12/18 DocID13866 Rev 6
7 Application information
The ST2S06A33 and ST2S06B represent a series of dual adjustable current mode PWM
step-down DC-DC converters with an internal 0.5 A power switch, packaged in a QFN12L
(4x4 mm).
It is a complete 0.5 A switching regulator with internal compensation that eliminates the
need for additional components.
The const ant frequency, current mode , PWM archite cture and st able ope ration with ceramic
capacitors results in low, predictable output ripple.
To clamp the error amplifier referen ce vo ltage a sof t start control block gen er ating a vo ltage
ramp has been implemented. Other circuits fitted to the device protection are the thermal
shut-down block, which turns off the regulator when the junction temperature exceeds 150
°C (typ.), and the cycle-by- cycle curr ent limiting that provides protection against shorted
outputs.
The output voltage is determined by an external resistor divide r, as the ST2S06A33 and
ST2S06B are adjustable regulators. The desired value is given by the following equation:
VO = VFB [1+R1/R2]
Operation of the device requires few components: 2 inductors, 3 capacitors and a resistor
divider. T he cho se n in d uc to r mu st be capable of no t sa tur a ting at th e pe ak curr en t level. Its
value should be selected keeping in mind that a large inductor value increases the efficiency
at low output current and reduces output voltage ripple, while a smaller inductor can be
chosen when it is important to reduce package size and total application cost. Finally, the
ST2S06A33 and ST2S06B have been designed to work properly with X5R or X7R SMD
ceramic capacitors both at the input and at the output. These types of capacitors, due to
their very low series resistance (ESR), minimize the output voltage ripple. Other low ESR
capacitors can be used according to the need of the application without compromising the
correct functionality of the d evice. Due to the high switching frequency and peak current, it is
important to optimize the application environment by reducing the length of the PCB traces
and placing all the external components near the device.
Figure 23. Reset function
V
TL
V
TH
VIN
Reset
t
DEL
V
TL
V
TH
VIN
Reset
t
DEL
DocID13866 Rev 6 13/18
ST2S06 Package mechanical data
18
8 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Package mechanical data ST2S06
14/18 DocID13866 Rev 6
Dim.
mm. inch.
Min. Typ. Max. Min. Typ. Max.
A 0.80 0.90 1.00 0.031 0.035 0.039
A1 0.02 0.05 0.001 0.002
A3 0.20 0.008
b 0.25 0.30 0.35 0.010 0.012 0.014
D 3.90 4.00 4.10 0.154 0.157 0.161
D2 2.00 2.15 2.25 0.079 0.085 0.089
E 3.90 4.00 4.10 0.154 0.157 0.161
E2 2.00 2.15 2.25 0.079 0.085 0.089
e 0.80 0.031
L 0.45 0.55 0.65 0.018 0.022 0.026
QFN12L (4x4) mechanical data
7936361B
DocID13866 Rev 6 15/18
ST2S06 Package mechanical data
18
Dim.
mm. inch.
Min. Typ. Max. Min. Typ. Max.
A 330 12.992
C 12.8 13.2 0.504 0.519
D 20.2 0.795
N 99 101 3.898 3.976
T 14.4 0.567
Ao 4.35 0.171
Bo 4.35 0.171
Ko 1.1 0.043
Po 4 0.157
P 8 0.315
Tape & reel QFNxx/DFNxx (4x4) mechanical data
Package mechanical data ST2S06
16/18 DocID13866 Rev 6
Figure 24. QFN12L (4x4 mm) footprint recommended data
DocID13866 Rev 6 17/18
ST2S06 Revision history
18
9 Revision history
Table 8. Document revision history
Date Revision Changes
3-Sep-2007 1 Initial release.
21-Jan-2008 2 Added root part number ST2S06D33.
18-Mar-2008 3 Modified: Table 2 on page 4.
28-Jul-2009 4 Modified: Table 1 on page 1.
24-May-2012 5
– Changed max value for Non-switching quiescent current to 1.2 mA in
Features on page 1.
– Updated part number in Figure 21 on page 11
– Minor text changes throughout the document
22-May-2013 6 – Changed title in cover page
ST2S06
18/18 DocID13866 Rev 6
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