CMOS Low Cost,
10-Bit Multiplying DAC
AD7533
Rev. C
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Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
FEATURES
Low cost 10-bit DAC
Low cost AD7520 replacement
Linearity: ½ LSB, 1 LSB, or 2 LSB
Low power dissipation
Full 4-quadrant multiplying DAC
CMOS/TTL direct interface
Latch free (protection Schottky not required)
Endpoint linearity
APPLICATIONS
Digitally controlled attenuators
Programmable gain amplifiers
Function generation
Linear automatic gain controls
GENERAL DESCRIPTION
The AD7533 is a low cost, 10-bit, 4-quadrant multiplying DAC
manufactured using an advanced thin-film-on-monolithic-
CMOS wafer fabrication process.
Pin and function equivalent to the AD7520 industry standard,
the AD7533 is recommended as a lower cost alternative for old
AD7520 sockets or new 10-bit DAC designs.
AD7533 application flexibility is demonstrated by its ability to
interface to TTL or CMOS, operate on 5 V to 15 V power, and
provide proper binary scaling for reference inputs of either
positive or negative polarity.
FUNCTIONAL BLOCK DIAGRAM
20kΩ
S1 S2 S3 SN
I
OUT
2
V
REF
I
OUT
1
R
FB
20kΩ20kΩ20kΩ
10kΩ
BIT 1 (MSB) BIT 10 (LSB)
DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE)
BIT 2 BIT 3
10kΩ10kΩ
10kΩ
20kΩ
01134-001
Figure 1.
AD7533* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
DOCUMENTATION
Application Notes
•AN-137: A Digitally Programmable Gain and Attenuation
Amplifier Design
•AN-320A: CMOS Multiplying DACs and Op Amps Combine
to Build Programmable Gain Amplifier, Part 1
•AN-912: Driving a Center-Tapped Transformer with a
Balanced Current-Output DAC
Data Sheet
•AD7533: CMOS Low Cost, 10-Bit Multiplying DAC Data
Sheet
REFERENCE MATERIALS
Solutions Bulletins & Brochures
•Digital to Analog Converters ICs Solutions Bulletin
DESIGN RESOURCES
•AD7533 Material Declaration
•PCN-PDN Information
•Quality And Reliability
•Symbols and Footprints
DISCUSSIONS
View all AD7533 EngineerZone Discussions.
SAMPLE AND BUY
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TECHNICAL SUPPORT
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AD7533
Rev. C | Page 2 of 12
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Ter mi no log y ...................................................................................... 5
Pin Configurations and Function Descriptions ........................... 6
Circuit Description............................................................................7
General Circuit Information........................................................7
Equivalent Circuit Analysis .........................................................7
Operation............................................................................................8
Unipolar Binary Code ..................................................................8
Bipolar (Offset Binary) Code.......................................................8
Applications........................................................................................9
Outline Dimensions ....................................................................... 10
Ordering Guide .......................................................................... 12
REVISION HISTORY
3/07—Rev. B to Rev. C
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Figure 13, Figure 14, and Figure 17 ........................... 9
Updated Outline Dimensions....................................................... 10
Changes to Ordering Guide .......................................................... 12
1/06—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Absolute Maximum Ratings ....................................... 4
Added Pin Configurations
and Function Descriptions Section................................................ 6
Updated Outline Dimensions....................................................... 10
Changes to Ordering Guide .......................................................... 12
3/04—Rev. 0 to Rev. A
Changes to Specifications.................................................................2
Changes to Absolute Maximum Ratings........................................3
Changes to Ordering Guide.............................................................3
Updated Outline Dimensions..........................................................7
AD7533
Rev. C | Page 3 of 12
SPECIFICATIONS
VDD = 15 V, VOUT1 = VOUT2 = 0 V, VREF = 10 V, unless otherwise noted.
Table 1.
Parameter TA = 25°C TA = Operating Range Test Conditions
STATIC ACCURACY
Resolution 10 Bits 10 Bits
Relative Accuracy1
AD7533JN, AD7533AQ,
AD7533SQ, AD7533JP
±0.2% FSR maximum ±0.2% FSR maximum
AD7533KN, AD7533BQ,
AD7533KP, AD7533TE
±0.1% FSR maximum ±0.1% FSR maximum
AD7533LN, AD7533CQ, AD7533UQ ±0.05% FSR maximum ±0.05% FSR maximum
DNL ±1 LSB maximum ±1 LSB maximum
Gain Error2, 3±1% FS maximum ±1% FS maximum Digital input = VINH
Supply Rejection4
∆Gain/∆VDD 0.001%/% maximum 0.001%/% maximum Digital inputs = VINH, VDD = 14 V to 17 V
Output Leakage Current
IOUT1 ±5 nA maximum ±200 nA maximum Digital inputs = VINL, VREF = ±10 V
IOUT2 ±5 nA maximum ±200 nA maximum Digital inputs = VINH, VREF = ±10 V
DYNAMIC ACCURACY
Output Current Settling Time 600 ns maximum4800 ns5 To 0.05% FSR; RLOAD = 100 Ω, digital
inputs = VINH to VINL or VINL to VINH
Feedthrough Error ±0.05% FSR maximum5±0.1% FSR maximum5Digital inputs = VINL, VREF = ±10 V,
100 kHz sine wave
Propagation Delay 100 ns typical 100 ns typical
Glitch Impulse 100 nV-s typical 100 nV-s typical
REFERENCE INPUT
Input Resistance (VREF) 5 kΩ min, 20 kΩ maximum 5 kΩ min, 20 kΩ maximum611 kΩ nominal
ANALOG OUTPUTS
Output Capacitance
CIOUT1 50 pF maximum5100 pF maximum5Digital inputs = VINH
CIOUT2 20 pF maximum535 pF maximum5
CIOUT1 30 pF maximum535 pF maximum5
CIOUT2 50 pF maximum5100 pF maximum5Digital inputs = VINL
DIGITAL INPUTS
Input High Voltage (VINH) 2.4 V minimum 2.4 V minimum
Input Low Voltage (VINL) 0.8 V maximum 0.8 V maximum
Input Leakage Current (IIN) ±1 μA maximum ±1 μA maximum VIN = 0 V and VDD
Input Capacitance (CIN) 8 pF maximum58 pF maximum5
POWER REQUIREMENTS
VDD 15 V ± 10% 15 V ± 10% Rated accuracy
VDD Ranges55 V to 16 V 5 V to 16 V Functionality with degraded performance
IDD 2 mA maximum 2 mA maximum Digital inputs = VINL or VINH D
25 μA maximum 50 μA maximum Digital inputs over VIN
1 FSR = full-scale range.
2 Full scale (FS) = VREF.
3 Maximum gain change from TA = 25°C to TMIN or TMAX is ±0.1% FSR.
4 AC parameter, sample tested to ensure specification compliance.
5 Guaranteed, not tested.
6 Absolute temperature coefficient is approximately −300 ppm/°C.
AD7533
Rev. C | Page 4 of 12
ABSOLUTE MAXIMUM RATINGS
TA = 25 °C unless otherwise noted.
Table 2.
Parameter Rating
VDD to GND −0.3 V, +17 V
RFB to GND ±25 V
VREF to GND ±25 V
Digital Input Voltage Range −0.3 V to VDD + 0.3 V
IOUT1, IOUT2 to GND −0.3 V to VDD
Power Dissipation (Any Package)
To 75°C 450 mW
Derates above 75°C by 6 mW/°C
Operating Temperature Range
Plastic (JN, JP, KN, KP, LN Versions) −40°C to +85°C
Hermetic (AQ, BQ, CQ Versions) −40°C to +85°C
Hermetic (SQ, TE, UQ Versions) −55°C to +125°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD7533
Rev. C | Page 5 of 12
TERMINOLOGY
Relative Accuracy
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for ideal zero and full scale and is expressed in % of
full-scale range or (sub) multiples of 1 LSB.
Resolution
Value of the LSB. For example, a unipolar converter with n bits
has a resolution of (2–n) (VREF). A bipolar converter of n bits has
a resolution of [2–(n–1)] (VREF). Resolution in no way implies
linearity.
Settling Time
Time required for the output function of the DAC to settle to
within ½ LSB for a given digital input stimulus, that is, 0 to
full scale.
Gain Error
Gain error is a measure of the output error between an ideal
DAC and the actual device output. It is measured with all 1s in
the DAC after offset error is adjusted out and is expressed in LSBs.
Gain error is adjustable to zero with an external potentiometer.
Feedthrough Error
Error caused by capacitive coupling from VREF to output with all
switches off.
Output Capacitance
Capacity from IOUT1 and IOUT2 terminals to ground.
Output Leakage Current
Current that appears on IOUT1 terminal with all digital inputs
low or on IOUT2 terminal when all inputs are high.
AD7533
Rev. C | Page 6 of 12
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
I
OUT
1
1
I
OUT
2
2
GND
3
BIT 1 (MSB)
4
R
FB
16
V
REF
15
V
DD
14
BIT 10 (LSB)
13
BIT 2
5
BIT 3
6
BIT 4
7
BIT 9
12
BIT 8
11
BIT 7
10
BIT 5
8
BIT 6
9
AD7533
TOP VIEW
(Not to Scale)
01134-002
Figure 2. 16-Lead PDIP Pin Configuration
01134-003
I
OUT
1
1
I
OUT
2
2
GND
3
BIT 1 (MSB)
4
R
FB
16
V
REF
15
V
DD
14
BIT 10 (LSB)
13
BIT 2
5
BIT 9
12
BIT 3
6
BIT 8
11
BIT 4
7
BIT 7
10
BIT 5
8
BIT 6
9
AD7533
TOP VIEW
(Not to Scale)
Figure 3. 16-Lead SOIC Pin Configuration
IOUT11
IOUT22
GND 3
BIT 1 (MSB) 4
RFB
16
VREF
15
VDD
14
BIT 10 (LSB)13
BIT 2 5BIT 9
12
BIT 3 6BIT 811
BIT 4 7BIT 710
BIT 5 8BIT 69
AD7533
TOP VIEW
(Not to Scale)
01134-004
Figure 4. 16-Lead CERDIP Pin Configuration
4
GND
5
BIT 1 (MSB)
6
NC
7
BIT 2
8
BIT 3
18 VDD
17 BIT 10 (LSB)
16 NC
15 BIT 9
14 BIT 8
19
VREF
20
RFB
1
NC
2
IOUT1
3
IOUT
2
13
BIT 7
12
BIT 6
11
NC
10
BIT 5
9
BIT 4
AD7533
TOP VIEW
(Not to Scale)
NC = NO CONNECT
01134-005
Figure 5. 20-Terminal LCC Pin Configuration
01134-006
1201923
4
5
6
7
8
18
17
16
15
14
910 11 12 13
NC = NO CONNECT
GND
BIT 1 (MSB)
NC
BIT 2
BIT 3
V
DD
BIT 10 (LSB)
NC
BIT 9
BIT 8
I
OUT
2
I
OUT
1
NC
R
FB
V
REF
BIT 4
BIT 5
NC
BIT 6
BIT 7
PIN 1
INDENTFIER
AD7533
TOP VIEW
(Not to scale)
Figure 6. 20-Lead PLCC Pin Configuration
Table 3. Pin Function Descriptions
Pin Number
16-Lead PDIP, SOIC, CERDIP 20-Lead LCC, PLCC Mnemonic Description
1 2 IOUT1 DAC Current Output.
2 3 IOUT2 DAC Analog Ground. This pin should normally be tied to the
analog ground of the system.
3 4 GND Ground.
4 to 13 5, 7 to 10, 12 to 15, 17 BIT 1 to BIT 10 MSB to LSB.
14 18 VDD Positive Power Supply Input. These parts can be operated from
a supply of 5 V to 16 V.
15 19 VREF DAC Reference Voltage Input Terminal.
16 20 RFB DAC Feedback Resistor Pin. Establish voltage output for the DAC
by connecting RFB to external amplifier output.
NA 1, 6, 11, 16 NC No Connect.
AD7533
Rev. C | Page 7 of 12
CIRCUIT DESCRIPTION
GENERAL CIRCUIT INFORMATION
The AD7533 is a 10-bit multiplying DAC that consists of a
highly stable thin-film R-2R ladder and ten CMOS current
switches on a monolithic chip. Most applications require the
addition of only an output operational amplifier and a voltage
or current reference.
The simplified D/A circuit is shown in Figure 7. An inverted
R- 2R ladder structure is used, that is, the binarily weighted
currents are switched between the IOUT1 and IOUT2 bus lines,
thus maintaining a constant current in each ladder leg
independent of the switch state.
20kΩ
S1 S2 S3 SN
I
OUT
2
V
REF
I
OUT
1
R
FB
20kΩ20kΩ20kΩ
10kΩ
BIT 1 (MSB) BIT 10 (LSB)
DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE)
BIT 2 BIT 3
10kΩ10kΩ
10kΩ
20kΩ
01134-001
Figure 7. Functional Diagram
One of the CMOS current switches is shown in Figure 8. The
geometries of Device 1, Device 2, and Device 3 are optimized to
make the digital control inputs DTL/TTL/CMOS compatible
over the full military temperature range. The input stage drives
two inverters (Device 4, Device 5, Device 6, and Device 7),
which in turn drive the two output N channels. The on
resistances of the switches are binarily sealed so that the voltage
drop across each switch is the same. For example, Switch 1 in
Figure 8 is designed for an on resistance of 20 Ω, Switch 2 for
40 Ω, and so on. For a 10 V reference input, the current through
Switch 1 is 0.5 mA, the current through Switch 2 is 0.25 mA,
and so on, thus maintaining a constant 10 mV drop across each
switch. It is essential that each switch voltage drop be equal if
the binarily weighted current division property of the ladder is
to be maintained.
DTL/TTL/
CMOS
INPUT
V
+
13
2
TO LADDER
5
4
250Ω
7
6
89
I
OUT
1I
OUT
2
01134-007
Figure 8. CMOS Switch
EQUIVALENT CIRCUIT ANALYSIS
The equivalent circuits for all digital inputs high and digital
inputs low are shown in Figure 9 and Figure 10. In Figure 9 with
all digital inputs low, the reference current is switched to IOUT2.
The current source ILEAKAGE is composed of surface and junction
leakages to the substrate, while the I/1024 current source represents
a constant 1-bit current drain through the termination resistor
on the R-2R ladder. The on capacitance of the output N channel
switch is 100 pF, as shown on the IOUT2 terminal. The off switch
capacitance is 35 pF, as shown on the IOUT1 terminal. Analysis of
the circuit for all digital inputs high, as shown in Figure 10, is
similar to Figure 9; however, the on switches are now on
Ter minal IOUT1. Therefore, there is the 100 pF at that terminal.
I
OUT
2
I
OUT
1
V
REF
I
REF
R
FB
I
LEAKAGE
R
01134-008
R
R 10kΩ
100pF
I
LEAKAGE
35pF
I/1024
Figure 9. Equivalent Circuit—All Digital Inputs Low
I
OUT
2
I
OUT
1
V
REF
I
REF
R
FB
I
LEAKAGE
R
01134-009
R
100pF
I
LEAKAGE
35pF
I/1024
R 10kΩ
Figure 10. Equivalent Circuit—All Digital Inputs High
AD7533
Rev. C | Page 8 of 12
OPERATION
UNIPOLAR BINARY CODE
Table 4. Unipolar Binary Operation
(2-Quadrant Multiplication)
Digital Input Analog Output
MSB LSB (VOUT as shown in Figure 11)
1 1 1 1 1 1 1 1 1 1 ⎟
⎠
⎞
⎜
⎝
⎛
−1024
1023
REF
V
1 0 0 0 0 0 0 0 0 1 ⎟
⎠
⎞
⎜
⎝
⎛
−1024
513
REF
V
1 0 0 0 0 0 0 0 0 0 ⎟
⎠
⎞
⎜
⎝
⎛
=
⎟
⎠
⎞
⎜
⎝
⎛
−21024
512 REF
REF
V
V
0 1 1 1 1 1 1 1 1 1 ⎟
⎠
⎞
⎜
⎝
⎛
−1024
511
REF
V
0 0 0 0 0 0 0 0 0 1 ⎟
⎠
⎞
⎜
⎝
⎛
−1024
1
REF
V
0 0 0 0 0 0 0 0 0 0 0
1024
0=
⎟
⎠
⎞
⎜
⎝
⎛
−REF
V
Nominal LSB magnitude for the circuit of Figure 11 is given by
⎟
⎠
⎞
⎜
⎝
⎛
=1024
1
REF
VLSB
3
14
1
16
2
15
4
13
AD7533
UNIPOLAR
DIGITAL
INPUT
MSB
V
DD
V
REF
I
OUT
1
V
OUT
I
OUT
2
R
FB
C1
GND
BIPOLAR
ANALOG INPUT
±10V
R1
1kΩR2
330Ω
LSB
NOTES
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
2. C1 PHASE COMPENSATION (5pF TO 15pF) MAY BE REQUIRED
WHEN USING HIGH SPEED AMPLIFIER.
01134-010
Figure 11. Unipolar Binary Operation (2-Quadrant Multiplication)
BIPOLAR (OFFSET BINARY) CODE
Table 5. Unipolar Binary Operation
(4-Quadrant Multiplication)
Digital Input Analog Output
MSB LSB (VOUT as shown in Figure 12)
1 1 1 1 1 1 1 1 1 1 ⎟
⎠
⎞
⎜
⎝
⎛
+512
511
REF
V
1 0 0 0 0 0 0 0 0 1 ⎟
⎠
⎞
⎜
⎝
⎛
+512
1
REF
V
1 0 0 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1 1 1 ⎟
⎠
⎞
⎜
⎝
⎛
−512
1
REF
V
0 0 0 0 0 0 0 0 0 1 ⎟
⎠
⎞
⎜
⎝
⎛
−512
511
REF
V
0 0 0 0 0 0 0 0 0 0 ⎟
⎠
⎞
⎜
⎝
⎛
−512
512
REF
V
Nominal LSB magnitude for the circuit of Figure 12 is given by
⎟
⎠
⎞
⎜
⎝
⎛
=512
1
REF
VLSB
3
14
1
16
2
15
4
13
AD7533
BIPOLAR
DIGITAL
INPUT
MSB
V
DD
V
REF
I
OUT
1
V
OUT
I
OUT
2
C1
GND
A1
A2
±10V
BIPOLAR
ANALOG INPUT
R1
1kΩR2
330Ω
R3
10kΩ
R6
5kΩ
R4
20kΩ
LSB
NOTES
1. R3, R4, AND R5 SELECTED FOR MATCHING AND TRACKING.
2. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
3. C1 PHASE COMPENSATION (5pF TO 15pF) MAY BE REQUIRED
WHEN USING HIGH SPEED AMPLIFIERS.
01134-011
R5
20kΩ
Figure 12. Bipolar Operation (4-Quadrant Multiplication)
AD7533
Rev. C | Page 9 of 12
APPLICATIONS
3
14
1
16
2
15
4
13
AD7533
OP97 OP97
MAGNITUDE
BITS
SIGN BIT
DIGITAL
INPUT
MSB
V
DD
V
REF
I
OUT
1
V
OUT
I
OUT
2
R
FB
GND
BIPOLAR
ANALOG INPUT
±10V
10kΩ10kΩ
5kΩ
1/2 AD7512DIJN
LSB
01134-012
Figure 13. 10-Bit and Sign Multiplying DAC
3
14
1
16
2
15
4
13
AD7533
OP97
OP97
DIGITAL
FREQUENCY
CONTROL
WORD
MSB
+15V
V
DD
NC
V
REF
I
OUT
1
6.8V
(2)
SQUARE
WAVE
TRIANGULAR
WAVE
I
OUT
2
C
t
GND
CALIBRATE
10V 1kΩ
4.7kΩ
LSB
01134-013
10kΩ
1%
10kΩ
1%
f = N ( )
R
t
= 10kΩ
0 < N ≤ (1 2
10
)
1
8R
t
C
t
Figure 14. Programmable Function Generator
3
16
2
1
14
15
4
13
AD7533
DIGITAL
INPUT
“D”
BIT 1
BIT 10
MSB
V
REF
I
OUT
2
V
OUT
V
IN
I
OUT
1
R
FB
GND
+15
V
LSB
01134-014
V
OUT
=
D= +
where:
–V
IN
D
0 < D ≤
BIT 1
2
1
BIT 2
2
2
+…BIT 10
2
10
1023
1024
Figure 15. Divider (Digitally Controlled Gain)
3
14
1
16
2
15
4
13
AD7533
DIGITAL
INPUT
“D”
MSB
+15V
V
REF
–VREFD
VOU
T
RFB
GND
R1
R2
LSB
01134
-
015
BIT 1
BIT 10
VOUT = VREF = –
D= +
where:
R2
R1 + R2
0 < D ≤
BIT 1
21
BIT 2
22+…BIT 10
210
1023
1024
R1D
R1 + R2
IOUT1
IOUT2
Figure 16. Modified Scale Factor and Offset
3
14
1
16
2
15
4
13
AD7533
AD790
COMPARATOR
DIGITAL
INPUT
(TEST LIMIT)
MSB
+15V
TEST INPUT
(0 TO – V
REF
)
I
OUT
1
FAIL/PASS
TEST
I
OUT
2
GND
V
REF
LSB
01134-016
Figure 17. Digitally Programmable Limit Detector
.
AD7533
Rev. C | Page 10 of 12
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
COMPLIANT TO JEDEC STANDARDS MS-001-AB
073106-B
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
16
18
9
0.100 (2.54)
BSC
0.800 (20.32)
0.790 (20.07)
0.780 (19.81)
0.210 (5.33)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.005 (0.13)
MIN
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.015 (0.38)
GAUGE
PLANE
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
Figure 18. 16-Lead Plastic Dual In-Line Package [PDIP]
(N-16)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013- AA
112906-B
10.50 (0.4134)
10.10 (0.3976)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75 (0.0295)
0.25 (0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
C
OPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
16 9
8
1
1.27 (0.0500)
BSC
Figure 19. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimensions shown in millimeters and (inches)
AD7533
Rev. C | Page 11 of 12
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.840 (21.34) MAX
15°
0°
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
0
.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.310 (7.87)
0.220 (5.59)
0.005 (0.13) MIN 0.098 (2.49) MAX
0.100 (2.54) BSC
PIN 1
18
9
16
SEATING
PLANE
0.150
(3.81)
MIN
0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
Figure 20. 16-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-16)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
1
20 4
9
8
13
19
14
3
18
BOTTOM
VIEW
0.028 (0.71)
0.022 (0.56)
45° TYP
0.015 (0.38)
MIN
0.055 (1.40)
0.045 (1.14)
0.050 (1.27)
BSC
0.075 (1.91)
REF
0.011 (0.28)
0.007 (0.18)
R TYP
0.095 (2.41)
0.075 (1.90)
0.100 (2.54) REF
0.200 (5.08)
REF
0.150 (3.81)
BSC
0.075 (1.91)
REF
0.358 (9.09)
0.342 (8.69)
SQ
0.358
(9.09)
MAX
SQ
0.100 (2.54)
0.064 (1.63)
0.088 (2.24)
0.054 (1.37)
022106-A
Figure 21. 20-Terminal Ceramic Leadless Chip Carrier [LCC]
(E-20-1)
Dimensions shown in inches and (millimeters)
COMPLIANT TO JEDEC STANDARDS MO-047-AA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.020 (0.50)
R
BOTTOM
VIEW
(PINS UP)
0.021 (0.53)
0.013 (0.33) 0.330 (8.38)
0.290 (7.37)
0.032 (0.81)
0.026 (0.66)
0.056 (1.42)
0.042 (1.07) 0.20 (0.51)
MIN
0.120 (3.04)
0.090 (2.29)
3
4
19
18
8
9
14
13
TOP VIEW
(PINS DOWN)
0.395 (10.03)
0.385 (9.78) SQ
0.356 (9.04)
0.350 (8.89) SQ
0.048 (1.22 )
0.042 (1.07)
0.048 (1.22)
0.042 (1.07)
0.020
(0.51)
R
0.050
(1.27)
BSC
0.180 (4.57)
0.165 (4.19)
0.045 (1.14)
0.025 (0.64) R
PIN 1
IDENTIFIER
Figure 22. 20-Lead Plastic Leaded Chip Carrier [PLCC]
(P-20)
Dimensions shown in inches and (millimeters)
AD7533
Rev. C | Page 12 of 12
ORDERING GUIDE
Model Temperature Range Package Description Package Option
Nonlinearity
(% FSR max)
AD7533ACHIPS DIE
AD7533JN −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16 ±0.2
AD7533JNZ1 −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16 ±0.2
AD7533KN −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16 ±0.1
AD7533KNZ1−40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16 ±0.1
AD7533LN −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16 ±0.05
AD7533LNZ1 −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16 ±0.05
AD7533JP −40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20 ±0.2
AD7533JP-REEL −40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20 ±0.2
AD7533JPZ1−40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20 ±0.2
AD7533JPZ-REEL1−40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20 ±0.2
AD7533KP −40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20 ±0.1
AD7533KP-REEL −40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20 ±0.1
AD7533KPZ1−40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20 ±0.1
AD7533KPZ-REEL1−40°C to +85°C 20-Lead Plastic Leaded Chip Carrier [PLCC] P-20 ±0.1
AD7533KR −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 ±0.1
AD7533KR-REEL −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 ±0.1
AD7533KRZ1−40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 ±0.1
AD7533KRZ-REEL1−40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16 ±0.1
AD7533AQ −40°C to +85°C 16-Lead Ceramic Dual In-Line Package [CERDIP] Q-16 ±0.2
AD7533BQ −40°C to +85°C 16-Lead Ceramic Dual In-Line Package [CERDIP] Q-16 ±0.1
AD7533CQ −40°C to +85°C 16-Lead Ceramic Dual In-Line Package [CERDIP] Q-16 ±0.05
AD7533SQ −55°C to +125°C 16-Lead Ceramic Dual In-Line Package [CERDIP] Q-16 ±0.2
AD7533UQ −55°C to +125°C 16-Lead Ceramic Dual In-Line Package [CERDIP] Q-16 ±0.05
AD7533UQ/883B −55°C to +125°C 16-Lead Ceramic Dual In-Line Package [CERDIP] Q-16 ±0.05
AD7533TE/883B −55°C to +125°C 20-Terminal Ceramic Leadless Chip Carrier [LCC] E-20-1 ±0.1
T
1Z = RoHS compliant part.
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01134-0-3/07(C)
TTT
