CY7C63310 CY7C638xx CY7C639xx CONFIDENTIAL PRELIMINARY enCoReTM II Low-Speed USB Peripheral Controller 1.0 Features * enCoRe II USB--"enhanced Component Reduction" -- Crystalless oscillator with support for an external crystal or resonator. The internal oscillator eliminates the need for an external crystal or resonator -- Internal 3.3V regulator and internal USB pull-up resistor -- Configurable IO for real-world interface without external components * USB Specification Compliance -- Conforms to USB Specification, Version 2.0 -- Conforms to USB HID Specification, Version 1.1 -- Each 3.3V pin supports high-impedance input, internal pull-up, open drain output or traditional CMOS output * SPI serial communication -- Master or slave operation -- Configurable up to 2-Mbit/second transfers -- Supports half duplex single data line mode for optical sensors * 2-channel 8-bit or 1-channel 16-bit capture timer. Capture timers registers store both rising and falling edge times -- Two registers each for two input pins -- Separate registers for rising and falling edge capture -- Supports one Low-Speed USB device address -- Supports one control endpoint and two data endpoints -- Integrated USB transceiver * Enhanced 8-bit microcontroller -- Harvard architecture -- M8C CPU speed can be up to 24 MHz or sourced by an external crystal, resonator, or signal * Internal memory -- Up to 256 bytes of RAM * * * * * * -- Up to eight Kbytes of Flash including EEROM emulation * Interface can auto-configure to operate as PS/2 or USB -- No external components for switching between PS/2 and USB modes * * * * -- No GPIO pins needed to manage dual-mode capability * Low power consumption -- Typically 10 mA at 6 MHz * -- 10-uA sleep * In-system re-programmability -- Allows easy firmware update * General-purpose I/O ports -- Up to 36 General Purpose I/O (GPIO) pins -- High current drive on GPIO pins. Configurable 8- or 50-mA/pin current sink on designated pins -- Each GPIO port supports high-impedance inputs, configurable pull-up, open drain output, CMOS/TTL inputs, and CMOS output -- Maskable interrupts on all I/O pins * 125-mA 3.3V voltage regulator can power external 3.3V devices * 3.3V I/O pins -- 4 I/O pins with 3.3V logic levels Cypress Semiconductor Corporation Document 38-08035 Rev. *C * -- Simplifies interface to RF inputs for wireless applications Internal low-power wake-up timer during suspend mode -- Periodic wake-up with no external components Programmable Interval Timer interrupts Reduced RF emissions at 27 MHz and 96 MHz Advanced development tools based on Cypress MicroSystems PSoCTM tools Watchdog timer (WDT) low-voltage detection with user-configurable threshold voltages Improved output drivers to reduce EMI Operating voltage from 4.0V to 5.25VDC Operating temperature from 0-70C Available in 16/18/24/40-pin PDIP, 16/18/24-pin SOIC, 24pin QSOP, 28/48-pin SSOP, and DIE form Industry standard programmer support 1.1 Applications The CY7C633xx/CY7C638xx/CY7C639xx is targeted for the following applications: * PC HID devices -- Mice (optomechanical, optical, trackball) -- Keyboards * Gaming -- Joysticks -- Game pads -- Console keyboards * General Purpose -- Barcode scanners -- POS terminal -- Consumer electronics -- Toys -- Remote controls 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised December 13, 2004 CONFIDENTIAL PRELIMINARY 2.0 Introduction Cypress has reinvented its leadership position in the lowspeed USB market with a new family of innovative microcontrollers. Introducing enCoRe II USB -- "enhanced Component Reduction." Cypress has leveraged its design expertise in USB solutions to advance its family of low-speed USB microcontrollers, which enable peripheral developers to design new products with a minimum number of components. The enCoRe II USB technology builds on to the enCoRe family. The enCoRe family has an integrated oscillator that eliminates the external crystal or resonator reducing overall cost. Also integrated into this chip are other external components commonly found in low-speed USB applications such as pullup resistors, wake-up circuitry, and a 3.3V regulator. All of this adds up to a lower system cost. The enCoRe II is 8-bit Flash-programmable microcontroller with integrated low-speed USB interface. The instruction set has been optimized specifically for USB and PS/2 operations, although the microcontrollers can be used for a variety of other embedded applications. The enCoRe II features up to 36 general-purpose I/O (GPIO) pins to support USB, PS/2 and other applications. The I/O pins are grouped into five ports (Port 0 to 4). The pins on Port 0 and Port 1 may each be configured individually while the pins on Ports 2, 3, and 4 may only be configured as a group. Each GPIO port supports high-impedance inputs, configurable pullup, open drain output, CMOS/TTL inputs, and CMOS output with up to five pins that support programmable drive strength of up to 50-mA sink current. GPIO Port 1 features four pins that interface at a voltage level of 3.3 volts. Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller. Each GPIO port has its own GPIO interrupt vector with the exception of GPIO Port 0. GPIO Port 0 has three dedicated pins that have independent interrupt vectors (P0.2 - P0.4). The enCoRe II features an internal oscillator. With the presence of USB traffic, the internal oscillator can be set to precisely tune to USB timing requirements (24 MHz 1.5%). Optionally, an external 12-MHz or 24-MHz crystal can be used to provide a higher precision reference for USB operation. The clock generator provides the 12-MHz and 24-MHz clocks that remain internal to the microcontroller. The enCoRe II has up to eight Kbytes of Flash for user's code and up to 256 bytes of RAM for stack space and user variables. In addition, the enCoRe II includes low-voltage reset logic, a Watchdog timer, a vectored interrupt controller, a 16-bit FreeRunning Timer, and Capture Timers. The low-voltage reset (LVR) logic detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at Flash address 0x0000. The LVR may reset the parts when Vcc drops below a programmable trip voltage or it may be configurable to generate a LVR/POR interrupt to inform the processor about the low-voltage event. The Watchdog timer Document 38-08035 Rev. *C CY7C63310 CY7C638xx CY7C639xx can be used to ensure the firmware never gets stalled in an infinite loop. The microcontroller supports 23 maskable interrupts in the vectored interrupt controller. Interrupt sources include a USB bus reset, LVR/POR, a programmable interval timer, a 1.024ms output from the Free Running Timer, three USB endpoints, two capture timers, five GPIO Ports, three GPIO pins, two SPI, a 16-bit free running timer wrap, an internal wake-up timer, and a bus active interrupt. The wake-up timer causes periodic interrupts when enabled. The USB endpoints interrupt after a USB transaction complete is on the bus. The capture timers interrupt whenever a new timer value is saved due to a selected GPIO edge event. A total of eight GPIO interrupts support both TTL or CMOS thresholds. For additional flexibility, on the edge sensitive GPIO pins, the interrupt polarity is programmable to be either rising or falling. The free-running 16-bit timer provides two interrupt sources: the programmable interval timer with 1 microsecond resolution and the 1.024 ms outputs. The timer can be used to measure the duration of an event under firmware control by reading the timer at the start and at the end of an event, then calculating the difference between the two values. The two 8-bit capture timers save a programmable 8-bit range of the free-running timer when a GPIO edge occurs on the two capture pins (P0.0, P0.1). The two 8-bit captures can be ganged into a single 16bit capture. The enCoRe II includes an integrated USB serial interface engine (SIE) that allows the chip to easily interface to a USB host. The hardware supports one USB device address with three endpoints. The USB D+ and D- pins can alternately be used as PS/2 SCLK and SDATA signals so that products can be designed to respond to either USB or PS/2 modes of operation. PS/2 operation is supported with internal pull-up resistors on SCLK and SDATA and an interrupt to signal the start of PS/2 activity. In USB mode the integrated pull-up resistor on D- can be controlled under firmware. No external components are necessary for dual USB and PS/2 systems, and no GPIO pins need to be dedicated to switching between modes. Slow edge rates operate in both modes to reduce EMI. The enCoRe II supports in-system programming by using the D+ and D- pins as the serial programming mode interface. The programming protocol is not USB. 3.0 Conventions In this document, bit positions in the registers are shaded to indicate which members of the enCoRe II family implement the bits. Available in all enCoRe II family members CY7C639xx and CY7C638xx only CY7C639xx only Page 2 of 70 CY7C63310 CY7C638xx CY7C639xx CONFIDENTIAL PRELIMINARY 4.0 Logic Block Diagram 3.3V Regulator Low-Speed USB/PS2 Transceiver and Pull-up Low-Speed USB SIE Interrupt Control 4 3VIO/SPI Pins 16 Extended I/O Pins 16 GPIO Pins Wakeup Timer Internal 24 MHz Oscillator M8C CPU Clock Control POR / Low-Voltage Detect Flash Up to 8K Byte 12-bit Timer Capture Timers Watchdog Timer Vdd Crystal Oscillator RAM Up to 256 Byte Figure 4-1. CY7C633xx/CY7C638xx/CY7C639xx Block Diagram Document 38-08035 Rev. *C Page 3 of 70 CY7C63310 CY7C638xx CY7C639xx CONFIDENTIAL PRELIMINARY 5.0 Packages/Pinouts Top View CY7C63801/3 16-pin SOIC CY7C63310 16-pin SOIC CY7C63801 16-pin PDIP CY7C63310 16-pin PDIP SSEL/P1.3 SCLK/P1.4 SMOSI/P1.5 SMISO/P1.6 P0.6/TIO1 TIO1/P0.5 INT2/P0.4 INT1/P0.3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 P1.2/VREG VDD P1.1/SCLK/DP1.0/SDATA/D+ VSS P0.0 P0.1 P0.2/INT0 CY7C63813 18-pin SOIC P0.7 P0.6/TIO1 P0.5/TIO0 P0.4/INT2 P0.3/INT1 P0.2/INT0 P0.1 P0.0 VSS 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P1.3/SSEL P1.2/VREG VDD P1.1/SCLK/DP1.0/SDATA/D+ CY7C63823 24-pin QSOP NC P0.7 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 INT1/P0.3 INT0/P0.2 P0.1 P0.0 P2.1 P2.0 NC 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P3.1 P3.0 P1.3/SSEL P1.2/VREG VDD P1.1/SCLK/DP1.0/SDATA/D+ VSS P0.6/TIO1 P0.5/TIO0 P0.4/INT2 P0.3/INT1 P0.2/INT0 P0.1 P0.0 VSS P1.6/SMISO P1.5/SMOSI P1.4/SCLK P1.3/SSEL P1.2/VREG VDD P1.1/SCLK/DP1.0/SDATA/D+ 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 CY7C63813 18-pin PDIP CY7C63823 24-pin PDIP P3.0 P3.1 SCLK/P1.4 SMOSI/P1.5 SMISO/P1.6 P1.7 NC NC P0.7 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 SSEL/P1.3 SCLK/P1.4 SMOSI/P1.5 SMISO/P1.6 P1.7 P0.7 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 P1.2/VREG VDD P1.1/SCLKD/DP1.0/SDATA/D+ VSS P0.0 P0.1 P0.2/INT0 P0.3/INT1 CY7C63823 24-pin SOIC P1.3/SSEL P1.2/VREG VDD P1.1/SCLK/DP1.0/SDATA/D+ VSS P2.0 P2.1 P0.0 P0.1 P0.2/INT0 P0.3/INT1 NC P0.7 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 INT1/P0.3 INT0/P0.2 P0.1 P0.0 P2.1 P2.0 VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 NC P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P3.1 P3.0 P1.3/SSEL P1.2/VREG VDD P1.1/SCLK/DP1.0/SDATA/D+ CY7C63903 28-pin SSOP VDD P2.7 P2.6 P2.5 P2.4 P0.7 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 INT1/P0.3 INT0/P0.2 CLKOUT/P0.1 CLKIN/P0.0 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS P3.7 P3.6 P3.5 P3.4 P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P1.3/SSEL P1.2/VREG VDD P1.1/SCLK/DP1.0/SDATA/D+ Figure 5-1. Package Configurations Document 38-08035 Rev. *C Page 4 of 70 CY7C63310 CY7C638xx CY7C639xx CONFIDENTIAL PRELIMINARY Top View NC NC NC NC VDD P4.1 P4.0 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 P0.7 P0.6/TIO1 P0.5/TIO0 P0.4/INT2 P0.3/INT1 P0.2/INT0 P0.1/CLKOUT P0.0/CLKIN VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NC NC P4.0 7 NC P2.7 8 NC P2.6 9 VSS P2.5 10 P4.3 P2.4 11 P2.3 12 P4.2 P2.2 13 P3.7 P3.6 P3.5 P3.4 P3.3 P2.1 14 P2.0 15 P3.2 P0.7 16 P3.1 P0.6/TIO1 17 P0.5/TIO0 18 P3.0 P0.4/INT2 19 P1.7 P0.3/INT1 20 P1.6/SMISO P0.2/INT0 21 P1.5/SMOSI P1.4/SCLK P0.1/CLKOUT 22 P1.3/SSEL P1.2/VREG VDD P1.1/SCLK/DP1.0/SDATA/D+ 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 40 P3.6 39 P3.5 38 P3.4 37 P3.3 36 P3.2 35 P3.1 34 P3.0 33 P1.7 32 P1.6/SMISO 31 P1.5/SMOSI 30 P1.4/SCLK 29 P1.3/SSEL 28 P1.2/VREG P1.1/SCLK/D- 26 VSS P4.3 P4.2 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P1.3/SSEL P1.2/VREG VDD P1.1/SCLK/DP1.0/SDATA/D+ 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P0.0/CLKIN 23 Vss 24 P1.0/SDATA/D+ 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CY7C63923-XC DIE P4.1 Vdd NC NC NC NC NC NC NC Vss P4.3 P4.2 P3.7 VDD P4.1 P4.0 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 P0.7 P0.6/TIO1 P0.5/TIO0 P0.4/INT2 P0.3/INT1 P0.2/INT0 P0.1/CLKOUT P0.0/CLKIN VSS CY7C63923 48-pin SSOP 6 5 4 3 2 1 48 47 46 44 43 42 41 CY7C63913 40-pin PDIP 27 Vdd Figure 5-1 Package Configurations (continued) 5.1 Pinouts Assignments Table 5-1. Pin Assignments 24 48 40 28 24 24 18 18 16 16 Die SSOP PDIP SSOP QSOP SOIC PDIP SIOC PDIP SOIC PDIP Pad Name 7 3 7 P4.0 6 2 6 P4.1 42 38 42 P4.2 43 39 43 P4.3 34 30 35 31 20 18 1 34 P3.0 19 2 35 P3.1 36 32 19 36 P3.2 37 33 37 P3.3 38 34 24 38 P3.4 39 35 25 39 P3.5 40 36 26 40 P3.6 41 37 27 41 P3.7 15 11 11 11 18 15 P2.0 14 10 10 10 17 14 P2.1 13 9 13 P2.2 12 8 12 P2.3 11 7 5 11 P2.4 10 6 4 10 P2.5 9 5 3 9 P2.6 8 4 2 8 P2.7 Document 38-08035 Rev. *C Description GPIO Port 4 - configured as a group (nibble) GPIO Port 3 - configured as a group (byte) GPIO Port 2 - configured as a group (byte) Page 5 of 70 CY7C63310 CY7C638xx CY7C639xx CONFIDENTIAL PRELIMINARY Table 5-1. Pin Assignments (continued) 24 48 40 28 24 24 18 18 16 16 Die SSOP PDIP SSOP QSOP SOIC PDIP SIOC PDIP SOIC PDIP Pad Name Description 25 21 15 14 13 20 10 15 9 13 25 P1.0/SDATA/ GPIO Port 1 bit 0 / PS2 IO Data / USB D+ D+ 26 22 16 15 14 21 11 16 10 14 26 P1.1/SCLK/ D- GPIO Port 1 bit 1 / PS2 IO Clock / USB D- 28 24 18 17 16 23 13 18 12 16 28 P1.2/VREG GPIO Port 1 bit 2 - Configured individually. 3.3V if regulator is enabled (add reference) 29 25 19 18 17 24 14 1 13 1 29 P1.3/SSEL GPIO Port 1 bit 3 - Configured individually. Alternate function is SSEL signal of the SPI bus TTL voltage thresholds 30 26 20 21 20 3 15 2 14 2 30 P1.4/SCLK GPIO Port 1 bit 4 - Configured individually. Alternate function is SCLK signal of the SPI bus TTL voltage thresholds 31 27 21 22 21 4 16 3 15 3 31 P1.5/SMOSI GPIO Port 1 bit 5 - Configured individually. Alternate function is SMOSI signal of the SPI bus TTL voltage thresholds 32 28 22 23 22 5 17 4 16 4 32 P1.6/SMISO GPIO Port 1 bit 6 - Configured individually. Alternate function is SMISO signal of the SPI bus TTL voltage thresholds 33 29 23 24 23 6 18 5 33 P1.7 GPIO Port 1 bit 7 - Configured individually. 23 19 13 9 9 16 8 13 7 11 23 P0.0/CLKIN GPIO Port 0 bit 0 - Configured individually. On CY7C639xx, optional Clock In when external crystal oscillator is disabled or crystal input when external crystal oscillator is enabled. On CY7C638xx and CY7C63310, oscillator input when configured as Clock In 22 18 12 8 8 15 7 12 6 10 22 P0.1 / CLKOUT GPIO Port 0 bit 1- Configured individually On CY7C639xx, optional clock out when external crystal oscillator is disabled or crystal output drive when external crystal oscillator is enabled. On CY7C638xx and CY7C63310, oscillator output when configured as Clock out. 21 17 11 7 7 14 6 11 5 9 21 P0.2/INT0 GPIO port 0 bit 2 - Configured individually Optional rising edge interrupt INT0 20 16 10 6 6 13 5 10 4 8 20 P0.3/INT1 GPIO port 0 bit 3 - Configured individually Optional rising edge interrupt INT1 19 15 9 5 5 12 4 9 3 7 19 P0.4/INT2 GPIO port 0 bit 4 - Configured individually Optional rising edge interrupt INT2 18 14 8 4 4 11 3 8 2 6 18 P0.5/TIO0 GPIO port 0 bit 5 - Configured individually Alternate function Timer capture inputs or Timer output TIO0 17 13 7 3 3 10 2 7 1 5 17 P0.6/TIO1 GPIO port 0 bit 6 - Configured individually Alternate function Timer capture inputs or Timer output TIO1 16 12 6 2 2 9 1 6 16 P0.7 GPIO port 0 bit 7 - Configured individually Not in 16 pin PDIP or SOIC package 1 1 7 1,2,3,4 Document 38-08035 Rev. *C 1,2, NC 3,4 No connect Page 6 of 70 CY7C63310 CY7C638xx CY7C639xx CONFIDENTIAL PRELIMINARY Table 5-1. Pin Assignments (continued) 24 48 40 28 24 24 18 18 16 16 Die SSOP PDIP SSOP QSOP SOIC PDIP SIOC PDIP SOIC PDIP Pad 45,46, 47,48 5 1 27 23 44 40 24 20 6.0 24 8 1 16 15 22 - - - - 28 13 12 19 9 5 12 17 11 15 27 14 8 12 24 44 CPU Architecture This family of microcontrollers is based on a high performance, 8-bit, Harvard architecture microprocessor. Five registers control the primary operation of the CPU core. These registers are affected by various instructions, but are not directly accessible through the register space by the user. Table 6-1. CPU Registers and Mnemonics Register Mnemonic Flags CPU_F Program Counter CPU_PC Accumulator CPU_A Stack Pointer CPU_SP Index CPU_X The 16-bit Program Counter Register (CPU_PC) allows for direct addressing of the full eight Kbytes of program memory space. Document 38-08035 Rev. *C Name 45, NC 46, 47, 48 12 VDD Description No connect Power VSS The Accumulator Register (CPU_A) is the general-purpose register that holds the results of instructions that specify any of the source addressing modes. The Index Register (CPU_X) holds an offset value that is used in the indexed addressing modes. Typically, this is used to address a block of data within the data memory space. The Stack Pointer Register (CPU_SP) holds the address of the current top-of-stack in the data memory space. It is affected by the PUSH, POP, LCALL, CALL, RETI, and RET instructions, which manage the software stack. It can also be affected by the SWAP and ADD instructions. The Flag Register (CPU_F) has three status bits: Zero Flag bit [1]; Carry Flag bit [2]; Supervisory State bit [3]. The Global Interrupt Enable bit [0] is used to globally enable or disable interrupts. The user cannot manipulate the Supervisory State status bit [3]. The flags are affected by arithmetic, logic, and shift operations. The manner in which each flag is changed is dependent upon the instruction being executed (i.e., AND, OR, XOR). See Table 8-1. Page 7 of 70 CY7C63310 CY7C638xx CY7C639xx CONFIDENTIAL PRELIMINARY 7.0 CPU Registers 7.1 Flags Register The Flags Register can only be set or reset with logical instruction. Table 7-1. CPU Flags Register (CPU_F) [0xF7] [R/W] Bit # 7 6 5 4 3 2 1 0 Field Reserved Reserved Reserved XIO Super Carry Zero Global IE Read/Write - - - R/W R RW RW RW Default 0 0 0 0 0 0 1 0 Bit [7:5]: Reserved Bit 4: XIO Set by the user to select between the register banks 0 = Bank 0 1 = Bank 1 Bit 3: Super Indicates whether the CPU is executing user code or Supervisor Code. (This code cannot be accessed directly by the user) 0 = User Code 1 = Supervisor Code Bit 2: Carry Set by CPU to indicate whether there has been a carry in the previous logical/arithmetic operation 0 = No Carry 1 = Carry Bit 1: Zero Set by CPU to indicate whether there has been a zero result in the previous logical/arithmetic operation 0 = Not Equal to Zero 1 = Equal to Zero Bit 0: Global IE Determines whether all interrupts are enabled or disabled 0 = Disabled 1 = Enabled 7.1.1 Accumulator Register Table 7-2. CPU Accumulator Register (CPU_A) Bit # 7 6 5 Field 4 3 2 1 0 CPU Accumulator [7:0] Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 1 0 Bit [7:0]: CPU Accumulator [7:0] 8-bit data value holds the result of any logical/arithmetic instruction that uses a source addressing mode 7.1.2 Index Register Table 7-3. CPU X Register (CPU_X) Bit # 7 6 5 4 Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Field 3 2 X [7:0] Bit [7:0]: X [7:0] 8-bit data value holds an index for any instruction that uses an indexed addressing mode Document 38-08035 Rev. *C Page 8 of 70 CY7C63310 CY7C638xx CY7C639xx CONFIDENTIAL PRELIMINARY 7.1.3 Stack Pointer Register Table 7-4. CPU Stack Pointer Register (CPU_SP) Bit # 7 6 5 4 Field 3 2 1 0 Stack Pointer [7:0] Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 3 2 1 0 Bit [7:0]: Stack Pointer [7:0] 8-bit data value holds a pointer to the current top-of-stack 7.1.4 CPU Program Counter High Register Table 7-5. CPU Program Counter High Register (CPU_PCH) Bit # 7 6 5 Field 4 Program Counter [15:8] Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 3 2 1 0 Bit [7:0]: Program Counter [15:8] 8-bit data value holds the higher byte of the program counter 7.1.5 CPU Program Counter Low Register Table 7-6. CPU Program Counter Low Register (CPU_PCL) Bit # 7 6 5 Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Field 4 Program Counter [7:0] Bit [7:0]: Program Counter [7:0] 8-bit data value holds the lower byte of the program counter 7.2 Addressing Modes 7.2.1 Source Immediate Examples The result of an instruction using this addressing mode is placed in the A register, the F register, the SP register, or the X register, which is specified as part of the instruction opcode. Operand 1 is an immediate value that serves as a source for the instruction. Arithmetic instructions require two sources. Instructions using this addressing mode are two bytes in length. ADD A, 7 ;In this case, the immediate value ;of 7 is added with the Accumulator, ;and the result is placed in the ;Accumulator. MOV X, 8 ;In this case, the immediate value ;of 8 is moved to the X register. AND F, 9 ;In this case, the immediate value ;of 9 is logically ANDed with the F ;register and the result is placed ;in the F register. Table 7-7. Source Immediate Opcode Instruction Operand 1 Immediate Value Document 38-08035 Rev. *C 7.2.2 Source Direct The result of an instruction using this addressing mode is placed in either the A register or the X register, which is specified as part of the instruction opcode. Operand 1 is an address that points to a location in either the RAM memory space or the register space that is the source for the instruction. Arithmetic instructions require two sources, the second source is the A register or X register specified in the opcode. Instructions using this addressing mode are two bytes in length. Page 9 of 70 CY7C63310 CY7C638xx CY7C639xx CONFIDENTIAL PRELIMINARY Examples Table 7-8. Source Direct Opcode Operand 1 Instruction ADD [7], A ;In this case, the value in ;the memory location at ;address 7 is added with the ;Accumulator, and the result ;is placed in the memory ;location at address 7. The ;Accumulator is unchanged. MOV REG[8], A ;In this case, the Accumula;tor is moved to the regis;ter space location at ;address 8. The Accumulator ;is unchanged. 7.2.5 Destination Indexed Source Address Examples: ADD MOV 7.2.3 A, [7] X, REG[8] ;In this case, the ;value in ;the RAM memory location at ;address 7 is added with the ;Accumulator, and the result ;is placed in the Accumulator. ;In this case, the value in ;the register space at address ;8 is moved to the X register. Source Indexed The result of an instruction using this addressing mode is placed in either the A register or the X register, which is specified as part of the instruction opcode. Operand 1 is added to the X register forming an address that points to a location in either the RAM memory space or the register space that is the source for the instruction. Arithmetic instructions require two sources, the second source is the A register or X register specified in the opcode. Instructions using this addressing mode are two bytes. The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is added to the X register forming the address that points to the location of the result. The source for the instruction is the A register. Arithmetic instructions require two sources, the second source is the location specified by Operand 1 added with the X register. Instructions using this addressing mode are two bytes in length. Table 7-11. Destination Indexed Opcode Table 7-9. Source Indexed Opcode Instruction Operand 1 Source Index ADD A, [X+7] ;In this case, the value in ;the memory location at ;address X + 7 is added with ;the Accumulator, and the ;result is placed in the ;Accumulator. MOV X, REG[X+8] ;In this case, the value in ;the register space at ;address X + 8 is moved to ;the X register. 7.2.4 Instruction Destination Direct The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is an address that points to the location of the result. The source for the instruction is either the A register or the X register, which is specified as part of the instruction opcode. Arithmetic instructions require two sources, the second source is the location specified by Operand 1. Instructions using this addressing mode are two bytes in length. Destination Index Example ADD Examples Operand 1 7.2.6 [X+7], A ;In this case, the value in the ;memory location at address X+7 ;is added with the Accumulator, ;and the result is placed in ;the memory location at address ;x+7. The Accumulator is ;unchanged. Destination Direct Immediate The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is the address of the result. The source for the instruction is Operand 2, which is an immediate value. Arithmetic instructions require two sources, the second source is the location specified by Operand 1. Instructions using this addressing mode are three bytes in length. Table 7-12. Destination Direct Immediate Opcode Instruction Operand 1 Destination Address Operand 2 Immediate Value Table 7-10. Destination Direct Opcode Instruction Operand 1 Destination Address Document 38-08035 Rev. *C Page 10 of 70 CY7C63310 CY7C638xx CY7C639xx CONFIDENTIAL PRELIMINARY Examples Example ADD [7], 5 ;In this case, value in the mem;ory location at address 7 is ;added to the immediate value of ;5, and the result is placed in ;the memory location at address 7. MOV MOV REG[8], 6 ;In this case, the immediate ;value of 6 is moved into the ;register space location at ;address 8. 7.2.9 7.2.7 Destination Indexed Immediate The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is added to the X register to form the address of the result. The source for the instruction is Operand 2, which is an immediate value. Arithmetic instructions require two sources, the second source is the location specified by Operand 1 added with the X register. Instructions using this addressing mode are three bytes in length. Table 7-13. Destination Indexed Immediate Opcode Operand 1 Instruction Destination Index Operand 2 Immediate Value [7], [8] ;In this case, the value in the ;memory location at address 8 is ;moved to the memory location at ;address 7. Source Indirect Post Increment The result of an instruction using this addressing mode is placed in the Accumulator. Operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) for the source of the instruction. The indirect address is incremented as part of the instruction execution. This addressing mode is only valid on the MVI instruction. The instruction using this addressing mode is two bytes in length. Refer to the PSoC Designer: Assembly Language User Guide for further details on MVI instruction. Table 7-15. Source Indirect Post Increment Opcode Operand 1 Instruction Source Address Address Example MVI A, [8] Examples ADD MOV 7.2.8 [X+7], REG[X+8], 5 6 ;In this case, the value in ;the memory location at ;address X+7 is added with ;the immediate value of 5, ;and the result is placed ;in the memory location at ;address X+7. ;In this case, the immedi;ate value of 6 is moved ;into the location in the ;register space at ;address X+8. Destination Direct Direct 7.2.10 ;In this case, the value in the ;memory location at address 8 is ;an indirect address. The memory ;location pointed to by the indi;rect address is moved into the ;Accumulator. The indirect ;address is then incremented. Destination Indirect Post Increment The result of an instruction using this addressing mode is placed within the memory space. Operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) for the destination of the instruction. The indirect address is incremented as part of the instruction execution. The source for the instruction is the Accumulator. This addressing mode is only valid on the MVI instruction. The instruction using this addressing mode is two bytes in length. The result of an instruction using this addressing mode is placed within the RAM memory. Operand 1 is the address of the result. Operand 2 is an address that points to a location in the RAM memory that is the source for the instruction. This addressing mode is only valid on the MOV instruction. The instruction using this addressing mode is three bytes in length. Table 7-16. Destination Indirect Post Increment Table 7-14. Destination Direct Direct MVI Opcode Instruction Operand 1 Destination Address Document 38-08035 Rev. *C Operand 2 Source Address Opcode Operand 1 Instruction Destination Address Address Example [8], A ;In this case, the value in ;the memory location at ;address 8 is an indirect ;address. The Accumulator is ;moved into the memory loca;tion pointed to by the indi;rect address. The indirect ;address is then incremented. Page 11 of 70 CY7C63310 CY7C638xx CY7C639xx CONFIDENTIAL PRELIMINARY 8.0 Instruction Set Summary needed, the Instruction Set Summary tables are described in detail in the PSoC Designer Assembly Language User Guide (available on the www.cypress.com web site). Bytes Flags Cycles Instruction Format Opcode Hex Bytes Flags Cycles Instruction Format Opcode Hex Bytes Cycles Opcode Hex The instruction set is summarized in Table 8-1 by numerically and serves as a quick reference. If more information is Table 8-1. Instruction Set Summary Sorted Numerically by Opcode Order[1, 2] Instruction Format Flags 00 15 1 SSC 2D 8 2 OR [X+expr], A Z 5A 5 2 MOV [expr], X 01 4 2 ADD A, expr C, Z 2E 9 3 OR [expr], expr Z 5B 4 1 MOV A, X 02 6 2 ADD A, [expr] C, Z 2F 10 3 OR [X+expr], expr Z 5C 4 1 MOV X, A 03 7 2 ADD A, [X+expr] C, Z 30 9 1 HALT 5D 6 2 MOV A, reg[expr] Z 04 7 2 ADD [expr], A C, Z 31 4 2 XOR A, expr Z 5E 7 2 MOV A, reg[X+expr] Z 05 8 2 ADD [X+expr], A C, Z 32 6 2 XOR A, [expr] Z 5F 10 3 MOV [expr], [expr] 06 9 Z 3 ADD [expr], expr C, Z 33 7 2 XOR A, [X+expr] Z 60 5 2 MOV reg[expr], A 07 10 3 ADD [X+expr], expr C, Z 34 7 2 XOR [expr], A Z 61 6 2 MOV reg[X+expr], A 08 4 1 PUSH A 35 8 2 XOR [X+expr], A Z 62 8 3 MOV reg[expr], expr 09 4 2 ADC A, expr C, Z 36 9 3 XOR [expr], expr Z 63 9 3 MOV reg[X+expr], expr 0A 6 2 ADC A, [expr] C, Z 37 10 3 XOR [X+expr], expr Z 64 4 1 ASL A C, Z 0B 7 2 ADC A, [X+expr] C, Z 38 5 2 ADD SP, expr 65 7 2 ASL [expr] C, Z 0C 7 2 ADC [expr], A C, Z 39 5 2 CMP A, expr 66 8 2 ASL [X+expr] C, Z 0D 8 2 ADC [X+expr], A C, Z 3A 7 2 CMP A, [expr] 67 4 1 ASR A C, Z 0E 9 3 ADC [expr], expr C, Z 3B 8 2 CMP A, [X+expr] 68 7 2 ASR [expr] C, Z 0F 10 3 ADC [X+expr], expr C, Z 3C 8 3 CMP [expr], expr 69 8 2 ASR [X+expr] C, Z 10 4 1 PUSH X 3D 9 3 CMP [X+expr], expr 6A 4 1 RLC A C, Z 11 4 2 SUB A, expr C, Z 3E 10 2 MVI A, [ [expr]++ ] 6B 7 2 RLC [expr] C, Z 12 6 2 SUB A, [expr] C, Z 3F 10 2 MVI [ [expr]++ ], A 6C 8 2 RLC [X+expr] C, Z 13 7 2 SUB A, [X+expr] C, Z 40 4 1 NOP 6D 4 1 RRC A C, Z 14 7 2 SUB [expr], A C, Z 41 9 3 AND reg[expr], expr Z 6E 7 2 RRC [expr] C, Z 15 8 2 SUB [X+expr], A C, Z 42 10 3 AND reg[X+expr], expr Z 6F 8 2 RRC [X+expr] C, Z 16 9 3 SUB [expr], expr C, Z 43 3 OR reg[expr], expr Z 70 4 2 AND F, expr C, Z 17 10 3 SUB [X+expr], expr C, Z 44 10 3 OR reg[X+expr], expr Z 71 4 2 OR F, expr C, Z 18 5 1 POP A 45 3 XOR reg[expr], expr Z 72 4 2 XOR F, expr C, Z 19 4 2 SBB A, expr C, Z 46 10 3 XOR reg[X+expr], expr Z 73 4 1 CPL A Z 1A 6 2 SBB A, [expr] C, Z 47 8 3 TST [expr], expr Z 74 4 1 INC A C, Z Z 9 9 if (A=B) Z=1 if (A