CONFIDENTIAL

enCoRe™ II

Low-Speed USB Peripheral Controlle

CY7C63310

CY7C638xx

• USB Specification Compliance

— Conforms to USB HID Specification, Version 1.1

— Up to eight Kbytes of Flash including EEROM

• General-purpose I/O ports

— Up to 36 General Purpose I/O (GPIO) pins

— High current drive on GPIO pins. Configurable 8- or

— Each GPIO port supports high-impedance inputs,

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speed USB market with a new family of innovative microcon-

trollers. Introducing enCoRe II USB — “enhanced Component

Reduction.” Cypress has leveraged its design expertise in

USB solutions to advance its family of low-speed USB micro-

controllers, which enable peripheral developers to design new

products with a minimum number of components. The

has been optimized specifically for USB and PS/2 operations,

although the microcontrollers can be used for a variety of other

embedded applications.

pins to support USB, PS/2 and other applications. The I/O pins

are grouped into five ports (Port 0 to 4). The pins on Port 0 and

Port 1 may each be configured individually while the pins on

Ports 2, 3, and 4 may only be configured as a group. Each

troller. Each GPIO port has its own GPIO interrupt vector with

pins that have independent interrupt vectors (P0.2 - P0.4).

The enCoRe II features an internal oscillator. With the

presence of USB traffic, the internal oscillator can be set to

precisely tune to USB timing requirements (24 MHz ±1.5%).

Optionally, an external 12-MHz or 24-MHz crystal can be used

to provide a higher precision reference for USB operation. The

remain internal to the microcontroller.

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5.0 Packages/Pinouts

Figure 5-1. Package Configurations

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address a block of data within the data memory space.

the PUSH, POP, LCALL, CALL, RETI, and RET instructions,

which manage the software stack. It can also be affected by

[1]; Carry Flag bit [2]; Supervisory State bit [3]. The Global

Interrupt Enable bit [0] is used to globally enable or disable

Table 5-1. Pin Assignments (continued)

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7.1.1 Accumulator Register

7.1.2 Index Register

Table 7-1. CPU Flags Register (CPU_F) [0xF7] [R/W]

0 = No Carry

Set by CPU to indicate whether there has been a zero result in the previous logical/arithmetic operation

8-bit data value holds the result of any logical/arithmetic instruction that uses a source addressing mode

Table 7-3. CPU X Register (CPU_X)

Bit [7:0]: X [7:0]

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7.1.3 Stack Pointer Register

X register, which is specified as part of the instruction opcode.

The result of an instruction using this addressing mode is

placed in either the A register or the X register, which is

specified as part of the instruction opcode. Operand 1 is an

Table 7-4. CPU Stack Pointer Register (CPU_SP)

8-bit data value holds a pointer to the current top-of-stack

Table 7-5. CPU Program Counter High Register (CPU_PCH)

Bit [7:0]: Program Counter [15:8]

Bit [7:0]: Program Counter [7:0]

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protection level for blocks 0 through 3; the second address is

for blocks 4 through 7. The 64th byte will store the protection

level for blocks 252 through 255.

places zeros in all locations of the protection block. To set the

ORs it with the current values in the protection block. The

block. The EraseBlock function does not change the

for its eight Kbytes of user data.

Flash macro with the highest address range. A bulk program

BLOCKID 0,FAh Flash block number (00h—FFh)

POINTER 0,FBh First of 64 addresses in SRAM, where

DELAY 0,FEh For a CPU speed of 12 MHz set to

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destroy all traces of the previous contents. The bulk program

the Flash is destroyed and the Flash is left in an unpro-

grammed state, ready to accept one of the various write

commands. The protection bits for all user data are also reset

to the zero state

The parameter block values that must be set, besides the

keys, are the CLOCK and DELAY values.

broken up into eight tables of eight bytes. The tables are

the CY7C638xx and CY7C639xx parts consist of 64-bytes.

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10.1.1 Clock Control Registers

Table 10-1. IOSC Trim (IOSCTR) [0x34] [R/W]

The effective frequency change of the offset input is controlled through the gain input. A lower value of the gain setting increases

(KHz/offsetStep) at each bit, typical conditions (24 MHz operation):

Gain bit 0 = -1.5KHz

Gain bit 1 = -3.0KHz

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10.1.3 External Clock Trim

Amplifier transconductance setting. The Xgm settings are recommended for resonators with frequencies of interest for the

12MHz Ceramic 011 41

Bit 6: Reserved

These bits control the bias current of the low-power oscillator.

Important Note: Do not program the 32-KHz Bias Trim [1:0] field with the reserved 10b value as the oscillator does not oscillate

at all corner conditions with this setting

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MHz Oscillator, the divide by two is always enabled

0 = USBCLK source is divided by two. This is the correct setting to use when the Internal 24MHz Oscillator is used, or when the

requirement of 1.5% tolerance (see Table 10-6)

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at the expense of a slightly higher than average sleep current

Note: The periodic Sleep Duty Cycle enabling is independent with the sleep interval shown in the Sleep [1:0] bits below

Note: Sleep intervals are approximate

Bit [2:0]: CPU Speed [2:0]

the device are the same as if the part was operating at 24 MHz. The operating voltage requirements are not relaxed until the

(in 32KHz clock)

01 512 15.6 mSec 47 mSec

11 32768 1 Sec 3 Sec

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10.1.7 USB Oscillator Lock Configuration

1 = Disable the oscillator lock from performing the course-tune portion of its retuning. The oscillator lock must be allowed to

0 = Enable. With the presence of USB traffic, the Internal 24-MHz Oscillator precisely tunes to 24 MHz ± 1.5%

1 = Disable. The Internal 24-MHz Oscillator is not trimmed based on USB packets. This setting is useful when the internal

Bit [7:6]: TCAPCLK Divider [1:0]

0 0 = Divider Value 2

0 1 = Divider Value 4

1 0 = Divider Value 6

1 0 = Divider value of 3

1 1 = Divider value of 4

Bit [1:0]: ITMRCLK Select

0 0 = Internal 24-MHz Oscillator

0 1 = External crystal oscillator – external crystal oscillator on CLKIN and CLKOUT if the external crystal oscillator is enabled,

CLKIN input if the external crystal oscillator is disabled

1 1 = TCAPCLK

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Table 11-1. System Status and Control Register (CPU_SCR) [0xFF] [R/W]

this bit is set, it indicates that the GIE bit in the CPU_F register is also set which, in turn, indicates that the microprocessor will

service interrupts

Bit 6: Reserved

1 = A POR event has occurred. (Note that WDR events will not occur until this bit is cleared)

Set by the user to enable CPU sleep state. CPU will remain in sleep mode until any interrupt is pending. The Sleep bit is covered

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When the CPU enters sleep mode the CPUCLK Select (Bit 1,

crystal oscillator is used, firmware will need to switch the clock

prior to disabling the external oscillator.

routine (if enabled).

The Sleep interrupt allows the microcontroller to wake up

periodically and poll system components while maintaining

very low average power consumption. The Sleep interrupt

may also be used to provide periodic interrupts during non-