NVMFS5833NWFT3G - ON Semiconductor

September, 2014 − Rev. 1 1Publication Order Number:

NVMFS5833N/D

NVMFS5833N

Power MOSFET

40 V, 7.5 mW, 86 A, Single N−Channel,

SO−8FL

Features

•Low RDS(on)

•Low Capacitance

•Optimized Gate Charge

•AEC−Q101 Qualified and PPAP Capable

•NVMFS5833NWF − Wettable Franks Option for Enhanced Optical

Inspection

•These Devices are Pb−Free and are RoHS Compliant

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

Parameter Symbol Value Unit

Drain−to−Source Voltage VDSS 40 V

Gate−to−Source Voltage VGS "20 V

Continuous Drain Cur

rent RYJ−mb

(Notes 1, 2, 3 & 4) Steady

State

Tmb = 25°CID86 A

Tmb = 100°C 61

Power Dissipation

RYJ−mb (Notes 1, 2, 3

)

Tmb = 25°CPD112 W

Tmb = 100°C 56

Continuous Drain Cur

rent RqJA

(Notes 1, 3 & 4) Steady

State

TA = 25°CID16 A

TA = 100°C11

Power Dissipation

RqJA (Notes 1 & 3) TA = 25°CPD3.7 W

TA = 100°C 1.8

Pulsed Drain Current TA = 25°C, tp = 10 msIDM 324 A

Operating Junction and Storage Temperature TJ, Tstg −55 to

175 °C

Source Current (Body Diode) IS86 A

Single Pulse Drain−to−Source Avalanche

Energy (TJ = 25°C, IL(pk) = 36 A, L = 0.1 mH) EAS 65 mJ

Lead Temperature for Soldering Purposes

(1/8″ from case for 10 s) TL260 °C

Stresses exceeding those listed in the Maximum Ratings table may damage the

device. If any of these limits are exceeded, device functionality should not be

assumed, damage may occur and reliability may be af fected.

THERMAL RESISTANCE MAXIMUM RATINGS

Parameter Symbol Value Unit

Junction−to−Mounting Board (top) − Steady

State (Notes 2, 3) RYJ−mb 1.3 °C/W

Junction−to−Ambient − Steady State (Note 3) RqJA 41

1. The entire application environment impacts the thermal resistance values shown,

they are not constants and are only valid for the particular conditions noted.

2. Psi (Y) is used as required per JESD51−12 for packages in which

substantially less than 100% of the heat flows to single case surface.

3. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.

4. Continuous DC current rating. Maximum current for pulses as long as

1 second are higher but are dependent on pulse duration and duty cycle/

SO−8 FLAT LEAD

CASE 488AA

STYLE 1

MARKING DIAGRAM

http://onsemi.com

5833 = Specific Device Code

xx = N (NVMFS5833N) or

= WF (NVMFS5833NWF)

A = Assembly Location

Y = Year

W = Work Week

ZZ = Lot Traceability

5833xx

AYWZZ

V(BR)DSS RDS(ON) MAX ID MAX

40 V 7.5 mW @ 10 V 86 A

G (4)

S (1,2,3)

N−CHANNEL MOSFET

D (5)

Device Package Shipping†

ORDERING INFORMATION

NVMFS5833NT1G SO−8FL

(Pb−Free) 1500 /

Tape & Ree

NVMFS5833NT3G SO−8FL

(Pb−Free) 5000 /

Tape & Ree

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer t o our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

NVMFS5833NWFT1G SO−8FL

(Pb−Free) 1500 /

Tape & Ree

NVMFS5833NWFT3G SO−8FL

(Pb−Free) 5000 /

Tape & Ree

NVMFS5833N

http://onsemi.com

ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)

Parameter Symbol Test Condition Min Typ Max Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA40 V

Drain−to−Source Breakdown Voltage

Temperature Coefficient V(BR)DSS/TJ32.6 mV/°C

Zero Gate Voltage Drain Current IDSS VGS = 0 V,

VDS = 40 V TJ = 25°C 1.0 mA

TJ = 125°C 100

Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = ±20 V ±100 nA

ON CHARACTERISTICS (Note 5)

Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250 mA2.0 3.5 V

Threshold Temperature Coefficient VGS(TH)/TJ−7.6 mV/°C

Drain−to−Source On Resistance RDS(on) VGS = 10 V, ID = 40 A 6.2 7.5 mW

Forward Transconductance gFS VDS = 5 V, ID = 5 A 38 S

CHARGES AND CAPACITANCES

Input Capacitance Ciss

VGS = 0 V, f = 1.0 MHz, VDS = 25 V

1714 pF

Output Capacitance Coss 210

Reverse Transfer Capacitance Crss 144

Total Gate Charge QG(TOT)

VGS = 10 V, VDS = 32 V,

ID = 40 A

32.5 nC

Threshold Gate Charge QG(TH) 2.77

Gate−to−Source Charge QGS 7.37

Gate−to−Drain Charge QGD 9

SWITCHING CHARACTERISTICS (Note 6)

T urn−On Delay Time td(on)

VGS = 10 V, VDS = 20 V,

ID = 40 A, RG = 2.5 W

10.23 ns

Rise Time tr19.5

T urn−Off Delay Time td(off) 23.60

Fall Time tf3.00

DRAIN−SOURCE DIODE CHARACTERISTICS

Forward Diode Voltage VSD VGS = 0 V,

IS = 40 A TJ = 25°C 0.85 1.2 V

TJ = 125°C 0.7

Reverse Recovery Time tRR

VGS = 0 V, dIS/dt = 100 A/ ms,

IS = 40 A

23.5 ns

Charge Time ta13.5

Discharge Time tb10

Reverse Recovery Charge QRR 14 nC

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

5. Pulse Test: pulse width = 300 ms, duty cycle v 2%.

6. Switching characteristics are independent of operating junction temperatures.

NVMFS5833N

http://onsemi.com

TYPICAL CHARACTERISTICS

110

0 0.5 1.0 1.5 2.0 3.0

Figure 1. On−Region Characteristics

VDS, DRAIN−TO−SOURCE VOLTAGE (V)

ID, DRAIN CURRENT (A)

10 V

VGS = 6 V

5.5 V

8 V

4.5 V

4.0 V

5.0 V

TJ = 25°C

123 4 7

VDS = 3 V

TJ = 25°C

TJ = −55°C

TJ = 125°C

Figure 2. Transfer Characteristics

VGS, GATE−TO−SOURCE VOLTAGE (V)

ID, DRAIN CURRENT (A)

456 8 10

Figure 3. On−Resistance vs. Gate−to−Source

Voltage

VGS, GATE−TO−SOURCE VOLTAGE (V)

RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)

ID = 40 A

TJ = 25°C

6.0

6.2

6.3

6.4

10 20 30 40 50

Figure 4. On−Resistance vs. Drain Current and

Gate Voltage

ID, DRAIN CURRENT (A)

RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)

TJ = 25°C

VGS = 10 V

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

−50 −25 0 25 50 75 100 125 150 175

Figure 5. On−Resistance Variation with

Temperature

TJ, JUNCTION TEMPERATURE (°C)

RDS(on), DRAIN−TO−SOURCE

RESISTANCE (NORMALIZED)

VGS = 10 V

ID = 40 A

1000

10000

100000

20 25 30

Figure 6. Drain−to−Source Leakage Current

vs. Voltage

VDS, DRAIN−TO−SOURCE VOLTAGE (V)

IDSS, LEAKAGE (nA)

TJ = 85°C

TJ = 150°C

VGS = 0 V

100

2.5 56

100

110

13 6.1

15105

100

TJ = 125°C

5.9

NVMFS5833N

http://onsemi.com

TYPICAL CHARACTERISTICS

200

400

600

800

1000

1200

1400

1600

1800

2000

2200

01020530

Figure 7. Capacitance Variation

VDS, DRAIN−TO−SOURCE VOLTAGE (V)

C, CAPACITANCE (pF)

TJ = 25°C

VGS = 0 V

Ciss

Coss

Crss 0

0 4 12 16 20 24 32

Figure 8. Gate−to−Source Voltage vs. Total

Charge

Qg, TOTAL GATE CHARGE (nC)

VGS, GATE−TO−SOURCE VOLTAGE (V)

VGS = 10 V

VDD = 32 V

ID = 40 A

TJ = 25°C

Qgs Qgd

100

1000

1 10 100

Figure 9. Resistive Switching Time Variation

vs. Gate Resistance

RG, GATE RESISTANCE (W)

t, TIME (ns)

VDD = 20 V

ID = 40 A

VGS = 10 V

td(off)

td(on)

0.4 0.6 0.7 0.8 0.9

Figure 10. Diode Forward Voltage vs. Current

VSD, SOURCE−TO−DRAIN VOLTAGE (V)

IS, SOURCE CURRENT (A)

TJ = 25°C

VGS = 0 V

0.01

0.1

100

0.1 1 10 100

VGS = 10 V

TC = 25°C

2 oz. 650 mm2

Cu Pad

RDS(on) Limit

Thermal Limit

Package Limit

100 ms

10 ms

1 ms

10 ms

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

VDS, DRAIN−TO−SOURCE VOLTAGE (V)

ID, DRAIN CURRENT (A)

11E−06 1E−05

Figure 12. Avalanche Characteristics

TIME IN AVALANCHE (s)

IPEAK (A)

TJ (initial) = 25°C

15 25 8 28

TJ = 125°C

0.5

100

1E−04 1E−03

TJ (initial) = 85°C

NVMFS5833N

http://onsemi.com

TYPICAL CHARACTERISTICS

0.01

0.1

100

0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000

Figure 13. Thermal Response

PULSE TIME (sec)

RqJA(t) (°C/W) EFFECTIVE TRANSIENT

THERMAL RESISTANCE

0.1

Duty Cycle = 0.5

0.2

0.05

0.02

0.01

Single Pulse

NVMFS5833N

http://onsemi.com

PACKAGE DIMENSIONS

M3.00 3.40

q0 −−−

3.80

DFN5 5x6, 1.27P

(SO−8FL)

CASE 488AA

ISSUE K NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION D1 AND E1 DO NOT INCLUDE

MOLD FLASH PROTRUSIONS OR GATE

BURRS.

1234

TOP VIEW

SIDE VIEW

BOTTOM VIEW

E1 q

0.20 C

2 X

DIM MIN NOM

MILLIMETERS

A0.90 1.00

A1 0.00 −−−

b0.33 0.41

c0.23 0.28

D5.15

D1 4.70 4.90

D2 3.80 4.00

E6.15

E1 5.70 5.90

E2 3.45 3.65

e1.27 BSC

G0.51 0.61

K1.20 1.35

L0.51 0.61

L1 0.125 REF

0.10 C

DETAIL A

e/2

A0.10 B

0.05 cL

DETAIL A

3 X

4 X

SEATING

PLANE

MAX

1.10

0.05

0.51

0.33

5.10

4.20

6.10

3.85

0.71

1.50

0.71

STYLE 1:

PIN 1. SOURCE

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

1.270

0.750

1.000

0.905

0.475

4.530

1.530

4.560

0.495

3.200

1.330

0.965

3X 4X

PIN 5

(EXPOSED PAD)

5.00 5.30

6.00 6.30

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,

copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC

reserves the r ight t o m ake c hanges wit hout f urt her n ot ice t o a ny p roduct s h erein. SCILLC makes no warrant y, r epresentat ion o r g uar antee r egar ding the suitability o f i t s p r oducts f or any

particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without

limitation s pecial, c onsequential o r i ncidental d amages. “T ypical” parameters which m ay b e p rovided i n S CILLC d ata s heets a nd/or s pecificat ions can and d o v ary i n d if ferent a pplications

and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC

does not convey any license under i ts p at ent rights nor the rights o f ot hers. SCILLC products are not d esigned, i nt ended, or authorized for use as components in systems intended for

surgical implant i nto t he b ody, o r o t her a pplicat ions i ntended t o s upport o r s ustain l ife, o r f or a ny o ther a pplication i n w hich t he f ailure o f t he S CILLC p roduct c ould c reate a s ituation w here

personal injury or death may occur. Should Buyer purchase o r u se S CILLC p r oduct s f o r a ny s u ch u nint ended o r u naut horized application, Buyer shall indemnify a nd hold SCILLC and

its o f ficers, e mployees, s ubsidiaries, a ff iliates, and dist ributors h armless against a ll claims, c osts, d amages, and e xpenses, a nd r easonable a ttorney f ees a rising o ut o f, d irectly o r indirectly ,

any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or m anuf acture

of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

UBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

NVMFS5833N/D

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your loc

Sales Representative