1
Features
•Single 2.7V - 3.6V Supply
•Dual-interface Architecture
–RapidS
™ Serial Interface: 40 MHz Maximum Clock Frequency
(SPI Modes 0 and 3 Compatible for Frequencies up to 33 MHz)
–Rapid8
™ 8-bit Interface: 20 MHz Maximum Clock Frequency
•P age Pr ogram Operation
– Dedicated Intelligent Programming Operation
– 16,384 Pages (1,056 Bytes/Page) Main Memory
•A utomat ed Page and Bloc k Erase Operations
•Two 105 6-byte SRAM Data Buffers – Allows Receiving of Data
while Reprogramming the Flash Array
•Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
•Low-power Dissipation
– 10 mA Active Read Current Typical – Seri al Interface
– 12 mA Acti ve Read Current Typical – 8-bi t Interface
– 5 µA CMOS Standb y Current Typical
•Hardwar e Data Pr otection
•Security : 128-b yte Security Register
– 64-byte Us er Programmable Space
– Unique 64-b yte Device Identifier
•100,000 Pr ogram/Erase Cycles Per Page Typical
•Data Retention – 10 Year s
•Commercial and Industrial Temperature Ranges
Description
The AT 45DB1282 is a 2.7-volt, dual-interf ace sequential access Flash memory ideally
suited for a wide variety of digital voice-, image-, prog ram code- and data-storage
128-megabit
2.7-volt
Dual-interface
DataFlash®
AT45DB1282
Preliminary
™
Note: *Optional Use – See pin description text
for connection informa tion.
Pin Configurations
Pin Name Function
CS Chip Select
SCK/CLK Serial Cloc k/Clock
SI Serial Input
SO Serial Output
I/O7 - I/O0 8-bit Input /Output
WP Hardware Page Write
Protect Pin
RESET Chip Reset
RDY/BUSY Ready/Busy
SER/BYTE Ser ia l /8 - b it In te r face
Control
TSOP Top View: Type 1
CBGA Top Vie w
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
NC
RDY/BUSY
RESET
WP
NC
NC
NC
VCC
GND
NC
NC
NC
NC
CS
SCK
SI*
SO*
NC
NC
NC
NC
NC
NC
NC
I/O7*
I/O6*
I/O5*
I/O4*
VCCP*
GNDP*
I/O3*
I/O2*
I/O1*
I/O0*
SER/BYTE*
CLK
NC
NC
NC
A
B
C
D
E
F
G
H
J
12345
NC
I/O2
I/O1
I/O0
NC
SER/BYTE
SCK/CLK
CS
SO
GNDP
NC
GND
RDY/BUSY
SI
VCCP
I/O7
VCC
WP
RESET
NC
I/O6
I/O5
I/O4
I/O3
NC
Rev. 2472C–DFLSH–11/03
2AT45DB1282 2472C–DFLSH–11/03
applications. This device utilizes Atmel’s e-STAC™ Multi-L evel C ell (MLC) memory
technology, which allows a single cell to store two bits of information delivering a
very cost effective high density Flash memory. The AT45DB128 2 supports RapidS
serial interface and Rap id8 8-bit interface. Rapid S serial interface is SPI comp atible for
fre quenc ies up to 33 MH z. The dua l-inte rface allows a ded icat ed seri al int erfac e to be
connected to a DSP and a dedicated 8-bit interface to be connected to a microcontroller
or vice versa. However, t he use of either i nterf ace is purely opt ional. Its 138,412,032 bits
of mem ory a re organize d as 16 ,384 pa ges of 1,05 6 bytes each. In ad dition to t he 132-
meg abit main memory, the AT45DB12 82 also contains two SRAM buffers of 1,05 6
bytes eac h. The buf fers allow the receiving of data while a page in the mai n Memory is
being reprogram med, as wel l as wri ting a continuous data st ream . EE PROM em ulation
(bit or byte alterability) is easily handled with a self-contained three step read-modify-
w rite op er ation . Unli ke co nv ention al F lash mem orie s th at are a cce ssed rand oml y wit h
multiple address lines and a parallel interface, the DataFlash uses either a RapidS serial
interface or a 8-bit Rap id8 i nterface to s eque ntially acc ess it s dat a. The s imple sequen-
tial access d ramatically reduces active pin count, facilitates hardware layout, increases
system reliability, minimizes switching noise, and reduces package size. The device is
optimized for use in many commercial and industrial applications where high-density,
lo w-pi n c oun t, l ow-v ol tage an d lo w-po w er ar e e ss entia l. T he d ev ice op erate s a t cl ock
frequen cies up to 4 0 MHz with a typical active read cu rrent consum ption of 10 mA.
To allow for simple in-system reprogrammability, the AT45DB1282 does not require
high input v oltages f or progr amm ing. The devi ce operat es fro m a sin gle pow er supply,
2. 7V to 3.6 V, for bo th th e pro gra m an d rea d o pera tions . Th e AT 45D B12 82 is en able d
thro ugh the chip se lect pin (CS ) and acc ess ed vi a a t hre e- wire inte rfac e con si sting of
the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK), or an 8-bit interface
consi sting of the input/output pins (I/O7 - I/O0) and the clock pin (CLK).
All programming and erase c ycles are self-timed.
Block Diagram
Memory Array To pr ov ide optimal f lex ib ilit y , the m e mory array of the AT 45D B1282 is di vided int o t hree
levels of granularity comprising of sectors, bloc ks, and pages. The “Memory Architec-
tur e Diagr am” illu strates the bre akdo wn of each le vel and d etails th e nu mber o f pages
per sector and block. All program op erations to the Dat aFlash occu r on a p age by pa ge
basis . The erase operations can be performed at the block or page level.
FLASH MEMORY ARRAY
PAGE (1056 BYTES)
BUFFER 2 (1056 BYTES)BUFFER 1 (1056 BYTES)
I/O INTERFACE
SCK/CLK
CS
RESET
VCC
GND
RDY/BUSY
SER/BYTE
WP
SOSI I/O7 - I/O0
3
AT45DB1282
2472C–DFLSH–11/03
Memory Architecture Diagram
De vice Operation The device operation is controlled by instructions from the host processor. The list of
inst ruction s and thei r assoc iated op code s are c ontaine d in T ables 1 throu gh 4. A va lid
instruction starts with the falling edge of CS follow ed by the ap propriate 8-bit opcode
and t he de sired bu ffer or m ain me mory a ddre ss locat ion. W hile the CS pin i s low, tog-
gling the SCK/CLK pin controls the loading of the opcode and the desired buffer or main
memory address location through either the SI (serial input) pin or the 8-bit input pins
(I/O7 - I/O 0). All inst ructions, ad dresses, an d data are transferred with the m ost sign ifi-
cant bit (MSB) first.
Buffer addressing is referenced in the datasheet using the terminology BFA10 - BFA0 to
denote the 11 address bits required to designate a byte address within a buffer. Main
me mor y ad dress ing is re fere nced u sing the term inol ogy P A1 3 - P A0 and BA 10 - BA 0,
where PA13 - PA0 denotes the 14 address bits required to designate a page address
and BA10 - BA0 denotes the 11 address bits required to designate a byte address within
the page.
Read Commands By spec ifying the appropriate opc ode, data can be read from the m ain memory or from
eithe r one of the tw o SRA M data buffers. The D ataF lash sup ports Ra pidS an d Ra pid8
pr otocol s for M ode 0 and M ode 3 . Plea se r efer to th e “Det ailed B it-le vel Re ad Ti ming”
diagrams in this datasheet for details on the clock cycle sequences for each mode.
CONTINUOUS ARRAY READ: By suppl ying a n initial starting addres s for the main
memory array, the Continuous Array Read command can be utilized t o sequentially
read a c on tin uous s tream of data f rom the device by sim ply providi ng a c lock s ignal; no
additional addressing information or control signals need to be provided. The DataFlash
incorporates an internal address counter that will automatically increment on every clock
cycle, allowing one continuous read operation without the need of additional address
seq uences . To perf orm a contin uous rea d, a n opcode of E8H must be c locked into th e
devic e followed b y four ad dress bytes (which com prises 7 do n’t ca re bits plus th e 25-bit
page and byte address sequence) and a series of don’t care clock cycles (24 if usi ng the
serial interface or 19 if using the 8-bit interface). The first 14 bits (PA13 - PA0) of the
SECTOR 0 = 8 Pages
8,448 bytes (8K + 256)
SECTOR 1 = 248 Pages
261,888 bytes (248K + 7,936)
Block = 8,448 bytes
(8K + 256)
8 Pages
SECTOR 0
SECTOR 1
Page = 1,056 bytes
(1K + 32)
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
PAGE 16,382
PAGE 16,383
BLOCK 0
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
BLOCK 1
SECTOR ARCHITECTURE BLOCK ARCHITECTURE PAGE ARCHITECTURE
BLOCK 0
BLOCK 1
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
BLOCK 2046
BLOCK 2047
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
SECTOR 2
SECTOR 64 = 256 Pages
270,336 bytes (256K + 8K)
BLOCK 2
SECTOR 2 = 256 Pages
270,336 bytes (256K + 8K)
SECTOR 63 = 256 Pages
270,336 bytes (256K + 8K)
SECTOR 3 = 256 Pages
270,336 bytes (256K + 8K)
4AT45DB1282 2472C–DFLSH–11/03
25-b it address sequ ence s pecify which page of the main mem ory array to read, and t he
last 11 bits (BA10 - BA0) of the 25-bit address sequence specify the starting byte
address within the page. The 24 or 19 don’t care clock cycles that follow the four
addres s bytes are needed t o initialize the read operat ion. Following the don’t c are clock
cycles, additional clock pulses on the SCK/CLK pin will result in data being output on
either the SO (serial output) pin or the eight output pins (I/O7- I/O0).
The CS pin must remain low during the loading of the opcode, the address bytes, the
don’t care bytes, and the reading of data. When the end of a page in main memory is
reache d duri ng a Continuous A rray Read, t he device wi ll continue reading at the begin-
ning o f the next pag e with no dela ys inc urred during the page bound ary crossover (th e
crossover from the end of one page to the beginning of the next page). When the last bit
(or byte if using the 8-bit interf ace mode) in the main m emory array has been read, t he
dev ice will con tinue reading bac k at the b eginni ng of the first page of mem ory. As w ith
cro ssing ov er page bou ndaries, no delays wi ll b e incurred wh en wrappin g around f rom
the end of the array to the begi nning of the array.
A low -to-hi gh tra nsition on the CS pin will terminat e the re ad operation and tri-state t he
output pins (SO or I/O7-I/O0). The maximum SCK/CLK frequency allowable for the Con-
tinuous Array Read is defined by the fCAR specification. The Continuous Array Read
bypa sses both data buffers and leave s the contents of the buffers unchanged.
MAIN MEMORY PAGE READ: A main memory page read allows the user to read data
directly from any one of the 16384 pages in the main memory, bypassing both of the
data buffers and leaving the contents of the buffers unchanged. To start a page read, an
opc ode o f D2H must be clo cked i nto th e devic e fol lowed by fou r addres s by tes (w hich
comprise 7 don’t care bits plus the 25-bit page and byte address sequence) and a series
of don’t care clock cycles (24 if using the serial interface or 19 if using the 8-bit inter-
face). The first 14 bits (PA13 - PA0) of the 25-bit address sequence s pecify the page in
main memory to be read, and the last 11 bits (BA10 - BA0) of the 25-bit address
sequence specify the starting byte address within that page. The 24 or 19 don’t care
cloc k c ycles th at fol low the four a ddres s by tes ar e sent to initi alize th e re ad ope ratio n.
Following the don’t care bytes, additional pulses on SCK/CLK result in data being output
on either the SO (serial output) pin or the eight output pins (I/O7 - I/O0). The CS pin
must remain low during the loading of the opcode, the address bytes, the don’t care
bytes, and the reading of data. When the end of a page in main memory is reached, the
device will continue reading back at the beginning of the same page. A low-to-high tran-
sition on the CS pin will terminate the read operation and tri-state the output pins (SO or
I/O7 - I/O0). The maxim um SCK/CLK frequency allowable for the Main Memory Page
Read is defined by the fSCK specificatio n. The Mai n Memory Page Read bypass es both
data buffe rs and leaves the contents of the buffers unchan ged.
BUFFE R READ : Data can be read from either one of the two buffers, using dif ferent
opcodes to specify which buffer to read from. With the serial interface, an opcode of
D4H is used to read data from buffer 1, and an opcode of D6H is used to read data from
buffer 2. Likewise with the 8-bit interface an opcode of 54H is used to read data from
buf fer 1 and a n opco de of 56H i s us ed to read d ata fr om b uffer 2 . To pe rform a bu ffer
read, the op code mu st be clo cked i nto the de vice follow ed by fou r add ress bytes com-
prised of 21 don’t care bits and 11 buffer address bits (BFA10 - BFA0). Following the
fou r address byte s, add itional don ’t care bytes (on e by te if using the seria l interface or
two byt es if u sing t he 8-bit interface) mus t be clocked in to initialize the read op eration.
Since the buffer size is 1056 bytes, 11 buffer address bits are required to specify the first
byte of dat a to be read from the bu ffer. The CS pin must remain low during the loadi ng
of the opcode, the address bytes, the don’t care bytes, and the reading of data. When
the end of a buffer is reache d, the device will continue reading back at the beginning of
th e buff er. A l ow-t o-hig h trans ition on the C S pin w ill te rmin ate th e read opera tion and
tri-state the output pins (SO or I/O7 - I/O0).
5
AT45DB1282
2472C–DFLSH–11/03
Program and Erase Commands
BUFFER WRITE: Data can be clocked in from the input pins (SI or I/O7 - I/O0) into
either buffer 1 or buffer 2. To load data into either buffer, a 1-byte opcode, 84H for buffer
1 or 87H for buffer 2, must be clocked into the dev ice, followed by four address bytes
comprised of 21 don’t care bits and 11 buffer address bits (BFA10 - BFA0). The 11
buffer address bits specify the first byte in the buffer to be written. After the last address
byte has been clocked into the device, data can then be clocked in on subsequent clock
cycles. If the end of the data buffer is reached, the device will wrap around back to the
beginning of the buffe r. Data w ill cont inue to be lo aded int o t he buf fer unt il a low- to-hi gh
transition is detected on the CS pin.
BUFFER TO MAIN MEMORY PA GE PROGRAM: A previously-erased page within main
me mo ry can be pro gr am me d wi th t he c on tent s of ei th er b uffe r 1 or buf fe r 2. T he pr o-
gramming time is selectable by the system through the use of different opcodes
between a normal mode and a fast mode (the fast program option will consume more
current). A 1-byte opcode, 88H for buffer 1 or 89H for buffer 2 (98H for buffer 1 fast pro-
gram or 99H for buffer 2 fast program), must be clocked into the device followed by four
addres s bytes consisting of 7 don’t care bits, 14 page address bits (PA13 - PA0) that
specify the page in the main memory to be written and 11 don’t care bits. When a low-to-
high transi tion o ccurs on the CS pin, th e part w ill prog ram t he data s tored in the buffer
into the s pecified p age i n t he m ain memory . It is neces sary that the page i n m ain mem -
ory that is being programmed has been previously erased using one of the erase
commands (Page Erase or Block Erase). The programming of the page i s internally self-
timed and shoul d take place in a maximum time of tP for normal program ming or tFP for
fast program ming. During th is time , the status register and the RDY /BUSY pin will indi-
cate that the part is busy.
PAG E ERASE: Th e Page Era se comm and can be used t o indi vidually erase any page
in the mai n memory ar ray allow ing the Buffer to Main M emory Page P rogram to be ut i-
lized at a later time. To perform a page erase, an opcode of 81H must be loaded into the
dev ice, followed by four address bytes comprise d of 7 don’t care bits, 14 pa ge address
bits (PA13 - P A0) tha t sp ecify th e pa ge in the m ain me mory to be erase d an d 11 don ’t
care bits. When a low-to-high transition occurs on the CS pin, the part will erase the
selected page (the erased state is a logical 1). The erase operation is internally self-
timed and should take place in a maximum time of t PE. During this time, the status regis-
ter and the RDY/BUSY pin will indicate that the part is busy.
BLOC K ERASE: A block of eight pages can be erased at one time. This command is
useful when large amounts of data has to be written into the device. This will avoid using
multip le Page E rase Command s. To perform a block erase, an opco de of 50 H must be
loaded into the device, followed by four address bytes comprised of 7 don’t care bits, 11
page address bits (PA13 -PA3) and 14 don’t care bits. The 11 page address bits are
used to specify which block of eight pages is to be erased. When a low-to-high transition
occu rs on the CS pi n, th e par t wi ll er ase t he sel ec ted bl ock of e ight p ag es. Th e e rase
operation is internally self-timed and should take place in a maximum time of tBE. During
this time, the status registe r and the RDY/BUSY pin will indicate that the part is busy.
6AT45DB1282 2472C–DFLSH–11/03
Addi tional Comm ands MAIN M EMORY PAGE TO BUFFER TRAN SFER: A page of data can be transferred
from the m ain memory to either buffer 1 or buffer 2. To start the operation, a 1-byte
opco de, 53H for b uffer 1 and 55H for buffer 2, mus t be clocked into the device, followed
by four address bytes comprised of 7 don’t care bits, 14 page address bits (PA13- PA0),
which s pecify the page in mai n m em ory tha t is to be tr ansfe rred, a nd 11 don’t c are bits.
The CS pin must be low while toggling the SCK/CLK pin to load the opcode and the
addres s bytes from the input pins (SI or I/O7 - I/O0). The transfer of the page of data
from th e m ain mem ory t o the buf f er will begin when the CS pin transitions from a l ow to
a high state. During the t rans fer of a page of dat a (tXFR), the s tat us regist er can be read
or the RDY/BUSY can be monitored to determine whether the transfer has been
completed.
MAIN MEMORY PAGE TO BUFFER COMPARE: A page of data in main memory can
be c ompared to the data in bu ffer 1 o r buffer 2. To initiate the operation, a 1-byte
opco de, 60H for b uffer 1 and 61H for buffer 2, mus t be clocked into the device, followed
by four address bytes consisting of 7 don’t care bits, 14 page address bits (PA13 - PA 0)
that specify the page in the m ain memory that is to be compared to the buffer, and 11
don’t care bits. The CS pin must be low while toggling the SCK/CLK pin to load the
opco de and the addres s by tes from the inp ut pins (SI or I/O7 - I/O0). On the low-to-high
transition of the CS pin, the 1056 by tes i n the se lected m ain m em ory page wil l b e com -
pared with the 1056 bytes in buffer 1 or buffer 2. During this time (tXFR), the status
regist er and the RD Y/BUSY p in will indicate that the part is busy. On c ompletion of the
compare operat ion , bit 6 of the status register is updat ed with the result of the com pare.
STAT US RE G ISTER RE AD: The status register can be us ed to determin e the device’s
read y/bu sy s tat us, th e res ult of a Mai n Me mory Pag e to B uffer Comp are o pe ration , or
the device density. To read the status register, an op code must be loaded into the
device. After the opcode and optional dummy byte(s) is clocked in, the 1-byte status
reg iste r will be cl ocke d out o n the ou tput pins ( SO or I /O7 - I/O 0), st art ing wi th the ne xt
clock cycle. In case of serial interface, opc ode D7H is followed with an optional dumm y
byte (8 c locks). For S erial applica tions over 25 MHz, opcode mu st be alwa ys followed
with a dummy byte. In case of applications with 8-bit interface, opcode D7H and two
dummy clock cycles should be used. When using the serial interface, the data in the sta-
tus register, starting with the MSB (bit 7), will be clocked out on the SO pin during the
next eight cloc k cycles.
Blo ck Era se Addr es sing
PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Block
00000000000XXX 0
00000000001XXX 1
00000000010XXX 2
00000000011XXX 3
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
11111111100XXX2044
11111111101XXX2045
11111111110XXX2046
11111111111XXX2047
7
AT45DB1282
2472C–DFLSH–11/03
The six most-significant bits of the status register will contain device information, while
th e rema ining t wo lea st-sig nifican t bits a re reserv ed fo r future use a nd will h ave unde-
fined values. After the one byte of the status register has been clocked out, the
seq uence will rep eat itsel f (as long as CS remai ns low and S CK/CLK is being toggled).
Th e dat a in the statu s reg ister i s co nsta ntly up da ted, so eac h re peat ing seque nc e wil l
outpu t new data.
R eady/b usy stat us is ind icate d using b it 7 o f the stat us regist er. If bit 7 i s a 1, then the
device is not busy and is ready to accept the next command. If bit 7 is a 0, then the
devic e is in a busy stat e. Since t he dat a i n t he st atus registe r is cons ta ntly updat ed, the
user must t oggle SCK/CLK pin to check the ready/busy status. There are five operations
that can c ause the de vice to be in a bus y stat e: Main Memo ry Page to Buffer Tran sfer,
Main Memory Page to Buffer Compare, Buffer to Main Memory Page Program, Page
Erase and Bloc k Erase.
Th e res ult of t he m ost r ecent M ain Memo ry Pag e to Buffe r Co mpar e ope ration is ind i-
cated using bit 6 of the status register. If bit 6 is a 0, then the dat a in the main mem ory
page matc hes the data in the buffer. If bit 6 is a 1, then at least one bit of the data in the
main memory page does not match the data in the buffer.
The device density is indicated using bits 5, 4, 3, and 2 of the status register. For the
AT45DB1282, the four bits are 0, 1, 0, 0. The decimal value of these four binary bits
does not equate to the device density; the four bits represent a combinational code
relating to differing densities of DataFlash devices.
St atu s Reg ist er For mat
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RDY/BUSY COMP0100XX
8AT45DB1282 2472C–DFLSH–11/03
Manufacturer and Device ID Read
This instruction allows the user t o read the Manuf acturer ID, De vice I D, and E xtended De vice I nformation. This mode is only
offered via the serial interface with clock frequenci es up to 25 MHz. A 1-byte opcode, 9FH, must be clocked into the device
while the CS pin is low. After the opcode is clocked in, the Manufacturer ID, 2 bytes of De vi ce I D and Extended Device Inf or-
mation will be clocked out on the SO pin. The fourth byt e of the sequence output is the Extended Device Inf ormation String
Length byte. This byte is used to signify how many bytes of Extended Device Infor m ation will be output.
Manufacturer and Device ID Information
Not e: Base d on J EDE C publ ic ation 106 ( JEP 10 6), Ma nufac turer ID data c an be com pr ise d of any numb er o f byt es. So me ma nu fact ure rs may have
Manufacturer ID codes that are two , three or even four bytes long with the first byte(s) in the sequence being 7FH. A system should detec t code
7FH as a “Continuation Code” and continue to read Manufacturer ID bytes. The first non-7FH byte would signify the last byte of Manufacturer ID
data. For Atmel (and some other manufacture rs), the Manufacturer ID data is compri sed of only one by te.
Byte 1 – Manufacturer ID
Hex
Value
JEDEC Assigned Code
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1FH 0 0 0 1 1 1 1 1 Manufacturer ID 1FH = Atmel
Byte 2 – Device ID (Part 1)
Hex
Value
Family Code Density Code
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Family Code 001 = DataFlash
29H 0 0 1 0 1 0 0 1 Density Code 01001 = 128-Mbit
Byte 3 – Device ID (Part 2)
Hex
Value
MLC Code Product Version Code
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MLC Code 001 = 2-Bit/Cell Technology
20H 0 0 1 0 0 0 0 0 Product Version 00000 = Initial Version
Byte 4 – Extended Device Inf ormation String Length
Hex
Value
Byte Count
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
00H 0 0 0 0 0 0 0 0 Byte Count 00H = 0 Bytes of Information
9FH
Manufacturer ID
Byte n Device ID
Byte 1 Device ID
Byte 2
This information
would only be output
if the Extended Device
Information String Length
value was something
other than 00H.
Extended
Device
Information
String Length
Extended
Device
Information
Byte x
Extended
Device
Information
Byte x + 1
CS
1FH 29H 20H 00H Data Data
SI
SO
Opcode
Each transition
represents 8 bits
9
AT45DB1282
2472C–DFLSH–11/03
Security Register The AT45DB1282 contains a specialized register that can be used for security purposes
in system design. The Security Register is a unique 128-byte register that is divided into
two portions. The first 64 bytes (byte 0 to byte 63) of this register are allocated as a one-
time user programmable space. Once these 64 bytes have been programmed, they
s houl d not be repro gr amme d. T he r ema ini ng 64 by tes of th is reg ist er (by te 6 4 to byt e
127 ) are fa ctory program med by Atmel and will contain a unique numbe r for ea ch
devic e. The factory programme d data is fixed and cannot be changed.
The Se cu rity Register can be read by clocking in opcode 77H to the device followed by
four address by tes (which are comprised of 21 don’t care bits plus 11 byte address bits)
and a series of don’t care clock cycles (24 if using the serial interface and 19 if using the
8-bi t int erfac e). Th e Se curity Regi ste r Read can be term ina ted by assert ing CS low to
high after the 128-byt e s ecurity register has been read out. The continuation of clocking
pas t that wi ll resu lt in ind etermi nate dat a on the outp ut. Se e the opc ode ta ble on p ag e
13 for this mode.
To program the first 64 bytes of the Security Register, a two step sequence must be
us ed. The first step req uire s tha t the user loa ds the desi red data int o Buffer 1 by us ing
the Buffer 1 Write operation (opcode 84H – see Buffer Write description). The user
should specify the starting buffer address as location zero and should write a full
64 bytes of information into the buf fer . Otherwise, the first 64 bytes of the buffer may
contain data that was previously stored in the buffer. It is not necessary to fill the remain-
ing 992 byt es (by te locations 64 through 1055) of the buf fer with data. A fter the Buffer 1
Write operation has been completed, the Security Register can be subsequently pro-
grammed by reselecting the device and clocking in opcode 9AH into the device followed
by four don’t care bytes (32 clock cycles if using the serial interface and four clock
cycles if using the 8-bit interface). After the final don’t care clock cycle has been
completed, a low-to-high transition on the CS pin will cause the d evic e to in itiate an
internally self-timed program operation in which the contents of Buffer 1 will be pro-
grammed into the Security Register. Only the first 64 bytes of data in Buffer 1 will be
programmed into the Security Register; the remaining 992 bytes of the buffer will be
ignored. The S ecurity Regis ter program operation shoul d take place in a maxim um time
of tP.
Operation Mode
Summary The m odes des cribed can be s eparat ed into two gro ups – modes t hat make us e of the
Flash memory array (Group A) and modes that do not make use of the Flash memory
array (Group B).
Group A m odes co nsist of:
1. Main Memor y Page Read
2. Continuous Array Read
3. Main Memor y Page to Buffer 1 (or 2) Trans fer
4. Main Memor y Page to Buffer 1 (or 2) C ompare
5. Buffer 1 (or 2) to Main Memory Page Program
6. Page Erase
7. Block Erase
Group B m odes co nsist of:
1. Buff er 1 (or 2) Read
2. Buff er 1 (or 2) Write
3. Status Register Read
10 AT45DB1282 2472C–DFLSH–11/03
If a Group A mode is in progress (not fully completed), then another mode in Group A
should not be started. However, during this time in which a Group A mode is in
progres s, modes in Group B can be started, except the first two Group A commands
(Memory Array Read Commands).
Th is giv es t he Da t aFlash the ab ilit y to virtually accom m odat e a continuous data s trea m.
W hile d ata is be ing progr amm ed int o ma in me mory from bu ff er 1, da ta can be loa de d
into buffer 2 (or vice versa). See application note AN-4 (“Using Atmel’s Serial
DataFlash”) for more details.
Pin De scr ipt ion s SERIAL/8-BIT INTERFACE CONTROL (SER/BYTE): The DataFlash may be config-
ured to utilize either its serial port or 8-bit port th rough the use of the serial/8-bit control
pin (S ER/BYTE). When the SER /BYTE p in is hel d hi gh, t he s eria l po rt (S I an d S O) of
the DataFlas h will be used for all data transfers, and the 8-bit port (I/O7 - I/O0) will be in
a hi gh im peda nce state. Any data pre sen ted on th e 8-bi t port w hile SER/BY TE is he ld
high will be ignore d. Whe n the SE R/BYTE is he ld low, the 8-b it port wil l be used for al l
data trans fers, and t he SO pi n of the serial port will be in a high i mpe dance sta te. While
SER/BYTE is low, any data presented on t he SI pin will be igno red. Switc hing between
the serial port and 8-bit port should only be done while the CS pin is high and the device
is not busy in an internally self-timed operation.
The SER/BYTE pin is internally pulled high; therefore, if the 8-bit port is never to be
used, then connection of the SER/BYTE pin is not necessary. In addition, if the
SER/BYTE pin is not connected or if the SER/BYTE pin is always driven high externally,
then th e 8-bi t input/ output pins (I/O7-I/O0), th e V CCP pin, and the GNDP pi n should be
treated as “don’t connects”.
SERIAL INPUT (SI): The SI pin is an input-only pin and is used to shift data serially into
the device. The SI pin is used for all data input, including opcodes and address
sequences. If the SER/BYTE pin is always driven low, then the SI pin should be a “don’t
connect”.
SE R I AL OU TP U T ( S O): T he SO pin is an output -only pin and i s used to s hift d ata s eri-
ally out from the device. If the SER/BYTE pin is always driven low, then the SO pin
should be a “don’t connect”.
8-BIT INPUT/OUTPUT (I/O7-I/O0): The I/O7-I/O0 pins are bidirectional and us ed to
clock data into and out of the device. The I/O7-I/O0 pins are us ed for all data input,
inc lu ding opcod es and a dd res s se quenc es. T h e use o f the se pins is o ption al, and t he
pins should be treated as “don’t connects” if the SER/ BYTE pin is not connected or if the
SER/BYTE pin is always driven high externa lly.
SER IAL CLOCK/CL OCK (SCK /CLK ): The SC K and CL K pin s are inp ut-onl y pins an d
ar e used to control the f low of data to an d from the DataF lash. The S CK and CL K pins
are used for serial and 8 -bit interface respectively. Data is a lways cl ocked into the
devic e on the rising edge of S CK /CL K and clo cked out of th e dev ice on t he falli ng ed ge
of SCK/CLK.
CHIP SELECT (CS): The DataFlash is selected when the CS pin is low. When the
devic e is not selected, data will n ot be accepted on the input pins (SI or I/O7-I/O0), and
th e outp ut pins (SO or I/O7 -I/O 0) wi ll re main in a high im peda nce sta te. A hi gh-to- low
transition on t he CS pin i s required to start an operation, and a l ow-to-high t rans ition on
the CS pin is required to end an operation.
HA RDWARE PAG E W RITE PROTEC T: If the WP pin is held low, the first 256 pages
(sectors 0 and 1) of the ma in memory cannot be reprogram m ed. The onl y way to repro-
gr am the first 25 6 page s is to first dri ve the prot ect pin h igh an d the n use the p rogram
11
AT45DB1282
2472C–DFLSH–11/03
commands previously mentioned. If this pin and feature are not utilized it is recom-
mended that the WP pin be driven high extern ally.
RESET: A lo w state on the reset pin (RESET) w ill te rmina te the op erati on in progre ss
and reset the internal state machine to an idle state. The device will remain in the reset
condition as long as a low level is present on the RESET pin. Normal operation can
resume onc e the RES ET pin is brought back to a high level.
The dev ice inc orpora tes an interna l pow er-on re set cir cui t, so ther e are no restri ctions
on the RESET pin during power-on sequences. If t his pi n and feature are not utilized it i s
recommended that the RESET pin be driven high externally.
READY/BUSY: This o pen drain out put pin wil l b e driven lo w when t he device i s busy i n
an internally self-timed operation. This pin, which is normally in a high state (through
an external pull-up resistor), will be pulled low during programming/erase operations,
compare operat ion s, and page-to-buffer transfers.
The busy status indicates that the Flash memory array and one of the buffers cannot be
accessed; read and write operations to the other buffer can still be performed.
8-BIT PORT SUPPLY VOLTAGE (VCCP AND GNDP): The VCCP and GNDP p ins are
us ed to supp ly p ower for the 8-b it input/ou tput p ins ( I/O 7-I/O 0). The VC CP and G NDP
pins need to be used if the 8-bit port is to be utilized; however, these pins should be
treated as “don’t connects” if the SER/ BYTE pin is not connected or if the SER/BYTE pin
is always driven high externally.
Power-on/Reset State When power is first applied to the device, or when recovering from a reset condition, the
devic e will default to Mode 3. In addition, the output pins (SO or I/O7 - I/O0) will be in a
high impedance state, and a high-to-low transition on the CS pin will be required to start
a valid instruction. The mode (Mode 3 or Mode 0) will be automatically selected on every
falling edge of CS by sampling the inactive clock state. After power is applied and VCC is
at th e minimu m datash eet value, th e syste m shoul d wait 20 m s befo re an op erationa l
mode is started.
System
Considerations The RapidS serial interface is controlled by the serial clock SCK, serial input SI and chip
select CS p ins . The se qu ential 8-bit Ra pid8 is co ntro lled by t he cl ock C LK, 8 I /Os and
ch ip select CS pins. These signals must rise and fall monotonically and be free from
noise. Ex cessive noise or ringing on these pins can be misinterpreted as multiple edges
and cause improper operation of the device. The PC board traces must be kept to a
minimum d istan ce or appropriately te rmin ated to ensure proper operat ion. If neces sary,
decoupling capacitors can be added on these pins to provide filtering against noise
glitch es.
As system complexity continues to increase, voltage regulation is becoming mo re
impo rtant. A k ey elem ent of any v ol tag e regul ation sc hem e is i ts current s ourcing c apa-
bility. Like all Flash memories, the peak current for DataFlash occur during the
programming and erase operation. The regulator needs to supply this peak current
requirement. An under specified regulator can cause current starvation. Besides
increasing system noise, current starvation during program ming or erase can lead to
improper operation and possible data corruption.
12 AT45DB1282 2472C–DFLSH–11/03
Note: 1. The Security Register Program command utilizes data stored in Buffer 1. Therefore,
this command must be used in conj unction wit h the Buffer 1 write command. See the
Securit y Register description for details.
Table 1. Read Commands
Command Serial/8-bit Opcode
Main Memor y Page Read Both D2h
Continuous Array Read Both E8h
Buffe r 1 R ead Seri a l D4h
Buffe r 2 R ead Seri a l D6h
Buffer 1 Read 8-bit 54h
Buffer 2 Read 8-bit 56h
Table 2. Program and Erase Commands
Command Serial/8-bit Opcode
Buffer 1 Write Both 84h
Buffer 2 Write Both 87h
Buffer 1 to Main Memory Page Program Both 88h
Buffer 1 to Main Memor y Page Program,
Fast Pr og ra m Both 98h
Buffer 2 to Main Memory Page Program Both 89h
Buffer 2 to Main Memor y Page Program,
Fast Pr og ra m Both 99h
Page Erase Both 81h
Block E r as e Bot h 50h
Table 3. Additional Commands
Command Serial/8-bit Opcode
Main Memor y Page to Buffer 1 Transfer Both 53h
Main Memor y Page to Buffer 2 Transfer Both 55h
Main Memor y Page to Buf fer 1 Compare Both 60h
Main Memor y Page to Buf fer 2 Compare Both 61h
Status Register Read Both D7h
Manufacturer and Device ID Read Serial 9Fh
Security Register Program(1) Both 9Ah
Security Register Read Both 77h
13
AT45DB1282
2472C–DFLSH–11/03
Notes: P = Page Address Bit
B = Byte/Buf fer Address Bit
x = Don’t Car e
*The num ber with (*) is for 8-bi t interface.
Table 4. Detailed Bit-level Addressing Sequence
Opcode Opcode
Address Byte Address Byte Address Byte Address Byte
Additional
Don’t Care
Bytes*
50h 01010000xxxxxxxP PPPPPPPP PPxxxxxx xxxxxxxx N/A
53h 01010011xxxxxxxP PPPPPPPP PPPPPxxx xxxxxxxx N/A
54h 01010100xxxxxxxx xxxxxxxx xxxxxBBBBBBBBBBB 2*
55h 01010101xxxxxxxP PPPPPPPP PPPPPxxx xxxxxxxx N/A
56h 01010110xxxxxxxx xxxxxxxx xxxxxBBBBBBBBBBB 2*
60h 01100000xxxxxxxP PPPPPPPP PPPPPxxx xxxxxxxx N/A
61h 01100001xxxxxxxP PPPPPPPP PPPPPxxx xxxxxxxx N/A
77h 01110111xxxxxxxx xxxxxxxx xxxxxBBBBBBBBBBB 3 or 19*
81h 10000001xxxxxxxP PPPPPPPP PPPPPxxx xxxxxxxx N/A
84h 10000100xxxxxxxx xxxxxxxx xxxxxBBBBBBBBBBB N/A
87h 10000111xxxxxxxx xxxxxxxx xxxxxBBBBBBBBBBB N/A
88h 10001000xxxxxxxP PPPPPPPP PPPPPxxx xxxxxxxx N/A
89h 10001001xxxxxxxP PPPPPPPP PPPPPxxx xxxxxxxx N/A
98h 10011000xxxxxxxP PPPPPPPP PPPPPxxx xxxxxxxx N/A
99h 10011001xxxxxxxP PPPPPPPP PPPPPxxx xxxxxxxx N/A
9Ah 10011010 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx N/A
9Fh 10011111 N/A N/A N/A N/A N/A
D2h 11010010xxxxxxxP PPPPPPPP PPPPPBBB BBBBBBBB 3 or 19*
D4h 11010100xxxxxxxx xxxxxxxx xxxxxBBBBBBBBBBB 1
D6h 11010110xxxxxxxx xxxxxxxx xxxxxBBBBBBBBBBB 1
D7h 11010111 N/A N/A N/A N/A 1/0 or 1*
E8h 11101000xxxxxxxP PPPPPPPP PPPPPBBB BBBBBBBB 3 or 19*
PA13
PA12
PA11
PA
10
PA9
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
BA10
BA9
BA8
BA7
BA6
BA5
BA4
BA3
BA2
BA1
BA0
14 AT45DB1282 2472C–DFLSH–11/03
Note: 1. After power is applied and VCC i s at t he minimum specifi ed datasheet value, the sys tem should w ait 20 ms before an opera-
tional mo de is started.
Notes: 1. ICC1 dur ing a bu f fer r ea d i s 25 mA m a ximum .
2. ICC2 during a bu f fer r ea d is 25 mA m aximu m .
Absolute Maximum Rat ings*
Temp e ra tu re u nd e r B ia s .. ... ....... .......... .......... -5 5 °C to +125°C*NO TICE: Stress es beyond those li sted und er “Absolute
Maximum Ratings” may cause permanent dam-
age to the de vice . Thi s is a stress r ating onl y and
functi onal operation of the device at these o r any
other conditi ons beyond those indicated in the
operational sections of this specification is not
impli ed. Exposure to absolute maximum rating
condit ions f or e xtended p eriods ma y aff ect device
reliability.
Storage Temperat ure............. .......... .. ..... ....... -65°C to +15 0°C
All Input Voltages
(in cluding NC Pins)
wit h R e spe ct to Gr o und ........ .......... .......... .......-0.6 V to +6. 25 V
All Output Voltages
wit h R e spe ct to Gr o und ........ .......... .......... .-0. 6 V to VCC + 0.6V
DC and AC Operating Range
AT45DB1282
Operating Temperature (Ca se) Com. 0°C to 70°C
Ind. -40°C to 85°C
VCC Power Supply(1) 2.7V to 3.6V
DC Characteristics
Symbol Parameter Condition Min Typ Max Units
ISB Standby Current CS, RESET, WP = VIH, all
inputs at CMOS levels 515µA
ICC1(1) Active Current, Read
Ope ration, Serial Inter face f = 20 MH z ; IOUT = 0 mA;
VCC = 3.6V 10 20 mA
ICC2(2) Active Current, Read
Ope ration, 8-bit Interface f = 10 MHz ; IOUT = 0 mA;
VCC = 3.6V 12 20 mA
ICC3 Active Current, Program
Ope ration, Page Program VCC = 3.6V 50 mA
ICC4 Active Current, Program
Ope ration, F ast Page Program VCC = 3.6V 65 mA
ICC5 Ac ti ve Cur rent , Page Erase
Operation VCC = 3.6V 50 mA
ICC6 Ac ti ve Cur rent , Block Erase
Operation VCC = 3.6V 50 mA
ILI Input Load Curren t VIN = CMOS level s 1 µA
ILO Out put Leaka ge Current VI/O = CMOS levels 1 µA
VIL Input Low Voltage VCC x 0.3 V
VIH Input High Voltage VCC x 0.7 V
VOL Output Low Volta ge IOL = 1.6 mA; VCC = 2.7V 0.4 V
VOH Output High Voltage IOH = -100 µA VCC - 0.2V V
15
AT45DB1282
2472C–DFLSH–11/03
AC Characteristics – RapidS Serial Interface
Symbol Parameter Min Typ Max Units
fSCK SCK Frequency 40 MHz
fCAR SCK Frequency for Continuous Arra y Read 40 MHz
tWH SCK High Tim e 9 ns
tWL SCK Low Time 9 ns
tCS Minimum CS High Time 250 ns
tCSS CS Setup Time 250 ns
tCSH CS Hold Time 250 ns
tCSB CS High to RDY/BUSY Low 150 ns
tSU Data In Setup Time 5 ns
tHData In Hold Time 7 ns
tHO Ou tp ut Hold Ti me 2 ns
tDIS Output Disable Time 10 ns
tVOutput Valid 10 ns
tXFR Page to Buffer Transfer/Compare Time 500 µs
tPPage Programming Tim e 50 ms
tFP Fast Page Programming Time 15 ms
tPE Page Erase Time 25 ms
tBE Block Erase Time 50 ms
tRST RESET Pulse Width 10 µs
tREC RESET Recovery Time 1 µs
16 AT45DB1282 2472C–DFLSH–11/03
Input Test Waveforms and Measurement Levels
tR, tF < 2 ns (10% to 90%)
Output Test Load
AC Characteristics – Rapid8 8-bit Interface
Symbol Parameter Min Typ Max Units
fSCK1 CLK Frequency 20 MHz
fCAR1 CLK Fr equency for Cont inuous Arra y Read 20 MHz
tWH CLK High Time 16 ns
tWL CLK Low Time 16 ns
tCS Minimum CS High Time 250 ns
tCSS CS Setup Time 250 ns
tCSH CS Hold Time 250 ns
tCSB CS High to RDY/BUSY Low 150 ns
tSU Data In Setup Time 10 ns
tHData In Hold Time 10 ns
tHO Ou tp ut Hold Ti me 3 ns
tDIS Output Disable Time 15 ns
tVOutput Valid 15 ns
tXFR Page to Buffer Transfer/Compare Time 500 µs
tPPage Programming Tim e 50 ms
tFP Fast Page Programming Time 15 ms
tPE Page Erase Time 25 ms
tBE Block Erase Time 50 ms
tRST RESET Pulse Width 10 µs
tREC RESET Recovery Time 1 µs
AC
DRIVING
LEVELS
AC
MEASUREMENT
LEVEL
0.45V
1.5V
2.4V
DEVICE
UNDER
TEST
30 pF
17
AT45DB1282
2472C–DFLSH–11/03
AC Waveforms Six different timi ng waveforms are s hown below. Wavef orm 1 shows the SCK/CLK sig-
nal b eing low whe n CS make s a high-to-low transition, and waveform 2 shows the
SCK/CLK signal being high when CS makes a high-to-low transition. In both cases, out-
put SO becomes valid while the SCK/CLK signal is still low (SCK/CLK low time is
sp ecified a s tWL). T iming wa veforms 1 and 2 co nform to Ra pidS serial interfac e but f or
frequencies up to 33 MHz. Waveforms 1 and 2 are compatible with SPI Mode 0 and SPI
Mode 3, respe ctively.
Waveform 3 and waveform 4 illustrate general timing diagram for RapidS serial inter-
face. T hese are similar to waveform 1 and waveform 2, except that output SO is not
restricted t o becom e v alid during t he tWL perio d. These timing waveforms are valid over
the full frequency range (maximum frequency = 40 MHz) of the RapidS serial case.
W aveform 5 and wavef orm 6 are for 8-bit Rapid8 interface ov er the full freq uency range
of operation (ma ximum frequ ency = 20 MHz).
Waveform 1 – SPI Mode 0 Compatible (for Frequencies up to 33 MHz)
Waveform 2 – SPI Mode 3 Compatible (for Frequencies up to 33 MHz)
CS
SCK/CLK
SI
SO
tCSS
VALID IN
tH
tSU
tWH tWL tCSH
tCS
tV
HIGH IMPEDANCE VALID OUT
tHO tDIS
HIGH IMPEDANCE
CS
SCK/CLK
SO
tCSS
VALID IN
tH
tSU
tWL tWH tCSH
tCS
tV
HIGH Z VALID OUT
tHO tDIS
HIGH IMPEDANCE
SI
18 AT45DB1282 2472C–DFLSH–11/03
Waveform 3 – RapidS Mode 0 (for all Frequencies)
Waveform 4 – RapidS Mode 3 (for all Frequencies)
Waveform 5 – Rapid8 Mode 0 (FMAX = 20 MHz)
Waveform 6 – Rapid8 Mode 3 (FMAX = 20 MHz)
CS
SCK/CLK
SI
SO
tCSS
VALID IN
tH
tSU
tWH tWL tCSH
tCS
tV
HIGH IMPEDANCE VALID OUT
tHO tDIS
HIGH IMPEDANCE
CS
SCK/CLK
SO
tCSS
VALID IN
tH
tSU
tWL tWH tCSH
tCS
tV
HIGH Z VALID OUT
tHO tDIS
HIGH IMPEDANCE
SI
CS
SCK/CLK
I/O7 - I/O0
(INPUT)
I/O7 - I/O0
(OUTPUT)
tCSS
VALID IN
tH
tSU
tWH tWL tCSH
tCS
tV
HIGH IMPEDANCE VALID OUT
tHO tDIS
HIGH IMPEDANCE
CS
SCK/CLK
I/O7 - I/O0
(OUTPUT)
tCSS
VALID IN
t
H
t
SU
t
WL
t
WH
t
CSH
t
CS
t
V
HIGH Z VALID OUT
t
HO
t
DIS
HIGH IMPEDANCE
I/O7 - I/O0
(INPUT)
19
AT45DB1282
2472C–DFLSH–11/03
Reset Timing
Note: The CS si gnal should be in the high st ate before the RESET signal is deasserted.
Command Sequence for Read/Write Operations
(Except Status Register Read, Manufacturer and Device ID Read)
Write Operations
The followi ng bl ock diagram and waveforms illustra te the various write sequences availabl e.
CS
SCK/CLK
RESET
SO or I/O7 - I/O0
(OUTPUT)
HIGH IMPEDANCE HIGH IMPEDANCE
SI or I/O7 - I/O0
(INPUT)
tRST
tREC tCSS
SI or I/O7 - I/O0
(INPUT) CMD 8 bits 8 bits 8 bits
MSB
7 Bits Don't
Care Page Address
(PA13 - PA0)
X X X X X X X X X X X X X X X X LSB
X X X X X X X X
8 bits
X X X X X X X X
Byte/Buffer Address
(BA10 - BA0/BFA10 - BFA0)
FLASH MEMORY ARRAY
PAGE (1056 BYTES)
BUFFER 2 (1056 BYTES)BUFFER 1 (1056 BYTES)
I/O INTERFACE
SI
BUFFER 1 TO
MAIN MEMORY
PAGE PROGRAM
BUFFER 2 TO
MAIN MEMORY
PAGE PROGRAM
BUFFER 1
WRITE BUFFER 2
WRITE
I/O7 - I/O0
20 AT45DB1282 2472C–DFLSH–11/03
Buffer Write
Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page)
Rea d Oper ati on s
The followi ng bl ock diagram and waveforms illustra te the various read sequences av ailable.
SI or I/O7 - I/O0
(INPUT) CMD
X
X···X, BFA10-8
BFA7-0
nn+1 Last Byte
· Completes writing into selected buffer
CS
X
SI or I/O7 - I/O0
(INPUT)
CMD
XXXXXXX PA13 PA12-5
CS
Starts self-timed erase/program operation
X···X
PA4-0, XXX
Each transition
represents 8 bits
FLASH MEMORY ARRAY
PAGE (1056 BYTES)
BUFFER 2 (1056 BYTES)BUFFER 1 (1056 BYTES)
I/O INTERFACE
MAIN MEMORY
PAGE TO
BUFFER 1
MAIN MEMORY
PAGE TO
BUFFER 2
MAIN MEMORY
PAGE READ
BUFFER 1
READ BUFFER 2
READ
SO I/O7 - I/O0
n = 1st byt e
n+1 = 2nd byte
21
AT45DB1282
2472C–DFLSH–11/03
Main Memory Page Read
Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer)
Buffer Read
SI or I/O7 - I/O0
(INPUT)
CMD xxx...PA13 PA12-5 BA7-0 X
X
CS
n n+1
SO or I/O7 - I/O0
(OUTPUT)
PA4-0, BA10-8
24 Cycles for Serial
19 Cycles for Parallel
Starts reading page data into buffer
SI or I/O7 - I/O0
(INPUT)
CMD XX...PA13 PA12-5 X
CS
SO or I/O7 - I/O0
(OUTPUT)
PA4-0, XXX
I/O7-I/O0
(INPUT)
CMD X
X···X, BFA10-8 BFA7-0
CS
n n+1
I/O7-I/O0
(OUTPUT)
X
ADDR ADDR
X
1 Dummy Byte (Serial)
2 Dummy Bytes (Parallel)
Each transition
represents 8 bits
n = 1st byt e read
n+1 = 2nd byte read
22 AT45DB1282 2472C–DFLSH–11/03
Detailed Bit-level Read Timing – RapidS Serial Interface Mode 0
Continuous Array Read (Opcode: E8H)
Main Memory Page Read (Opcode: D2H)
SI
11XXX
CS
SO
SCK
12 62 63 64 65 66 67
HIGH IMPEDANCE
D7D6D5D2D1D0D7D6D5
DATA OUT
BIT 0
OF
PAGE n+1
BIT 8,447
OF
PAGE n
LSB MSB
t
SU
t
V
SI 11010 XXX
CS
SO
SCK 12345 60 61 62 63 64 65 66 67
XX
HIGH IMPEDANCE
COMMAND OPCODE
t
SU
D7D6D5
DATA OUT
MSB
t
V
D4
23
AT45DB1282
2472C–DFLSH–11/03
Detailed Bit-level Read Timing – RapidS Serial Interface Mode 0 (Continued)
Buffer Read (Opcode: D4H or D6H)
Status Register Read (Opcode: D7H)
Manufacturer and Device ID Read (Opcode: 9FH)
SI 11010 XXX
CS
SO
SCK 12345 44 45 46 47 48 49 50 51
XX
HIGH IMPEDANCE
COMMAND OPCODE
t
SU
D7D6D5
DATA OUT
MSB
t
V
D4
SI 11010111
CS
SO
SCK 12345 7891011 12 15 16
HIGH IMPEDANCE STATUS REGISTER OUTPUT
COMMAND OPCODE
MSB
tSU
6
D1D0D7
LSB MSB
D7D6D5
tV
D4
tV
DON’T CARE FOR
FREQ. OVER 25 MHz
SI 10- 011111
CS
SO
SCK 12345 7891011 12 16 17
HIGH IMPEDANCE PRODUCT ID OUTPUT
COMMAND OPCODE
MSB
tSU
6
100
MSBLSB
000
tV
1
24 AT45DB1282 2472C–DFLSH–11/03
Detailed Bit-level Read Timing – RapidS Serial Interface Mode 3
Continuous Array Read (Opcode: E8H)
Main Memory Page Read (Opcode: D2H)
SI 11XXX
CS
SO
SCK 12 63 64 65 66 67
HIGH IMPEDANCE D7D6D5D2D1D0D7D6D5
BIT 0
OF
PAGE n+1
BIT 8,447
OF
PAGE n
LSB MSB
tSU
tVDATA OUT
SI 11010 XXX
CS
SO
SCK 12345 61 62 63 64 65 66 67
XX
HIGH IMPEDANCE D7D6D5
DATA OUT
COMMAND OPCODE
MSB
tSU
tV
D4
68
25
AT45DB1282
2472C–DFLSH–11/03
Detailed Bit-level Read Timing – RapidS Serial Interface Mode 3 (Continued)
Buffer Read (Opcode: D4H or D6H)
Status Register Read (Opcode: D7H)
Manufacturer and Device ID Read (Opcode: 9FH)
SI 11010 XXX
CS
SO
SCK 12345 45 46 47 48 49 50 51
XX
HIGH IMPEDANCE D7D6D5
DATA OUT
COMMAND OPCODE
MSB
tSU
tV
D4
52
SI 11010111
CS
SO
SCK 12345 7891011 12 17 18
HIGH IMPEDANCE D7D6D5
STATUS REGISTER OUTPUT
COMMAND OPCODE
MSB
tSU
tV
6
D4D0D7
LSB MSB D6
tV
DON’T CARE FOR
FREQ. OVER 25 MHz
SI 10011111
CS
SO
SCK 12345 7891011 12 17 18
HIGH IMPEDANCE 000
PRODUCT ID OUTPUT
COMMAND OPCODE
MSB
tSU
tV
6
110
LSB MSB 0
26 AT45DB1282 2472C–DFLSH–11/03
Detailed 8-bit Read Timing – Rapid8 Mode 0
Continuous Array Read (Opcode: E8H)
Main Memory Page Read (Opcode: D2H)
I/O7-I/O0
(INPUT)
CMD ADDR XXX
CS
I/O7-I/O0
(OUTPUT)
CLK
12 22 23 24 25 26 27
HIGH IMPEDANCE
DATA DATA DATA DATA DATA DATA DATA DATA DATA
DATA OUT
BYTE 0
OF
PAGE n+1
BYTE 1055
OF
PAGE n
t
SU
t
V
I/O7-I/O0
(INPUT)
CMD ADDR ADDR ADDR ADDR
XXX
CS
I/O7-I/O0
(OUTPUT)
CLK 12345 20 21 22 23 24 25 26 27
XX
HIGH IMPEDANCE DATA DATA DATA
DATA OUT
COMMAND OPCODE
t
SU
tV
DATA
27
AT45DB1282
2472C–DFLSH–11/03
Detailed 8-bit Timing – R apid8 Mode 0 (Con tinued)
Buffer Read (Opcode: 54H or 56H)
Status Register Read (Opcode: D7H)
I/O7-I/O0
(INPUT)
CMD XXADDR
CS
I/O7-I/O0
(OUTPUT)
CLK 12345 8
HIGH IMPEDANCE
COMMAND OPCODE
tSU
tVDATA OUT
DATA DATA DATA
MSB
76
ADDR XX
I/O7-I/O0
(INPUT)
CMD
CS
I/O7-I/O0
(OUTPUT)
CLK
123
HIGH IMPEDANCE
t
SU
XX DATA
t
V
DATA DATA
STATUS
REGISTER OUTPUT
28 AT45DB1282 2472C–DFLSH–11/03
Detailed 8-bit Read Timing – Rapid8 Mode 3
Continuous Array Read (Opcode: E8H)
Main Memory Page Read (Opcode: D2H)
I/O7-I/O0
(INPUT)
CMD ADDR XXX
CS
I/O7-I/O0
(OUTPUT)
CLK
12 23 24 25 26 27
HIGH IMPEDANCE
DATA DATA DATA DATA DATA DATA DATA DATA DATA
BYTE 0
OF
PAGE n+1
BYTE 1055
OF
PAGE n
t
SU
t
V
DATA OUT
I/07-I/O0
(INPUT)
CMD ADDR ADDR ADDR ADDR
XXX
CS
I/07-I/O0
(OUTPUT)
CLK
12345 21 22 23 24 25 26 27
XX
HIGH IMPEDANCE
DATA DATA DATA
DATA OUT
COMMAND OPCODE
tSU
tV
DATA
28
29
AT45DB1282
2472C–DFLSH–11/03
Detailed 8-bit Read Timing – Rapid8 Mode 3 (Continued)
Buffer Read (Opcode: 54H or 56H)
Status Register Read (Opcode: D7H)
I/O7-I/O0
(INPUT) CMD XXADDR ADDR
CS
I/O7-I/O0
(OUTPUT)
CLK 123456879
HIGH IMPEDANCE DATA DATA DATA
DATA OUT
tSU
tV
10
XX
I/O7-I/O0
(INPUT) CMD
CS
I/O7-I/O0
(OUTPUT)
CLK 123
HIGH
IMPEDANCE XX DATA
STATUS REGISTER
OUTPUT
tSU
tV
DATA
30 AT45DB1282 2472C–DFLSH–11/03
Figu re 1. Algorithm for Programming or Reprogramming of the Entire Array Sequentially
Notes: 1. This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-by-
page.
2. A page is wri tten using a Buffer 1 or Buffer 2 Write operation followed by a Buffer (1 to 2) to Main Memory Page Program
operation (ei ther regul arly or in Fast Program ).
3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page
withi n the ent ire array.
START
END
provide address
and data
BUFFER WRITE
(84h, 87h)
BUFFER TO MAIN
MEMORY PAGE PROGRAM
(88h, 89h) or (98h, 99h)
Page Erase
(81h)
31
AT45DB1282
2472C–DFLSH–11/03
Figu re 2. Algorithm for Randomly Modifying Data
Notes: 1. To preserve data integrity, each page of a DataFlash sector must be updated/rewritten at least once within every 2,000
cumulative page er ase/pr ogra m operations.
2. A P age Address Pointer must be maintai ned to indicate which page i s to be re wri tten.
3. Other algorithms can be used to rewrite por tions of the Flash array. Low-power applications may choose to wait until 2,000
cumulative page erase/program operations have accumulated before rewriting all pages of the sector. See application note
AN-4 (“Using Atmel’s Serial Data Flash”) f or more details.
BUFFER WRITE
(84h, 87h)
PAGE ERASE
(81h)
BUFFER TO MAIN
MEMORY PAGE PROGRAM
(88h, 89h) or (98h, 99h)
START
MAIN MEMORY PAGE
TO BUFFER TRANSFER
(53h, 55h)
provide address of
page to modify
If planning to modify multiple
bytes currently stored within
a page of the Flash array
INCREMENT PAGE
ADDRESS POINTER(2)
END
Sector Addressing
PA13 PA12 PA11 PA10 PA9 PA8 P A7 PA6 PA5 PA4 PA3 PA2 - PA0 Sector
00000000000 X 0
000000XXXXX X 1
000001XXXXX X 2
000010XXXXX X 3
••••••••••• • •
••••••••••• • •
••••••••••• • •
111100XXXXX X 61
111101XXXXX X 62
111110XXXXX X 63
111111XXXXX X 64
32 AT45DB1282 2472C–DFLSH–11/03
Note: 1. RapidS Serial Interface.
Ordering Information
fSCK
(MHz)
ICC (mA)
Ordering Code Package Operation RangeActive Standby
40(1) 20(1) 0.015 AT45DB1282-TC 40T Commercial
(0°C to 70°C)
40(1) 20(1) 0.015 AT45DB1282-TI 40T Industrial
(-40°C to 85°C)
40(1) 20(1) 0.015 AT45DB1282-CC 44C2 Commercial
(0°C to 70°C)
40(1) 20(1) 0.015 AT45DB1282-CI 44C2 Industrial
(-40°C to 85°C)
Package Type
40T 40-lead, (10 x 20 mm) Plastic Thin Sma ll Outl ine Package, Type I (TSOP)
44C2 44-b a ll, (8 x 12 mm ) Pla s ti c C h ip -s iz e Ba ll G r id Ar ray Pack age (C B GA )
33
AT45DB1282
2472C–DFLSH–11/03
Packaging Information
40T – TSOP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
40T, 40-lead (10 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP) B
40T
10/18/01
PIN 1
D1 D
Pin 1 Identifier
b
e
EA
A1
A2
0º ~ 8º c
L
GAGE PLANE
SEATING PLANE
L1
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This package conforms to JEDEC reference MO-142, Variation CD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 19.80 20.00 20.20
D1 18.30 18.40 18.50 Note 2
E 9.90 10.00 10.10 Note 2
L 0.50 0.60 0.70
L1 0.25 BASIC
b 0.17 0.22 0.27
c 0.10 – 0.21
e 0.50 BASIC
34 AT45DB1282 2472C–DFLSH–11/03
44C2 – CBGA
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
44C2, 44-ball (5 x 9 Array), 8 x 12 x 1.2 mm Body, 0.4 mm Ball
Plastic Chip-scale Ball Grid Array Package (CBGA) A
44C2
06/10/03
Side View
T op View
Bottom View
A
B
C
D
E
F
G
H
J
1
2
3
4
5
2.00 REF
2.00 REF
Marked A1
Identifier
D
E
D1
E1
e
e
Øb
A
A1
0.12
Seating Plane
C
C
A1 Ball Corner
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A – – 1.20
A1 0.25 – –
D 7.90 8.00 8.10
D1 4.00 TYP
E 11.90 12.00 12.10
E1 8.00 TYP
e 1.00 TYP
Ø
b 0.40 TYP
Pr inted o n rec ycled pa per.
2472C–DFLSH–11/03 /xM
Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard
warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for a ny
errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and
does not make any commitment to update the information contained herein. No licenses to patents or other intellectual proper ty of Atmel are
gran ted by th e Com pany in conn ecti on w ith th e sale of A tme l prod uc ts, exp ressl y or by im pli catio n. Atme l’s pro duct s ar e no t aut ho rized for us e
as critical components in life support devices or systems.
Atmel Corporation Atmel Operations
2325 O rchard Park way
San Jos e, CA 95131, USA
Tel: 1(4 08) 4 41-0311
Fax : 1(408) 487-260 0
Regional Headquarters
Europe
Atm el Sa rl
Rout e des Ars enau x 41
Case P ostale 8 0
CH- 1705 Fri bourg
Switzerland
Tel: (41 ) 26-4 26-55 55
Fax : (4 1) 26- 426-550 0
Asia
Room 121 9
Chin achem Gold en Plaza
77 Mod y Ro ad Tsims hatsu i
East Kowloon
Hong K ong
Tel: (85 2) 27 21-9778
Fax : (8 52) 2722 -136 9
Japan
9F, T onetsu Sh inkaw a Bl dg.
1-24 -8 Shi nkawa
Chuo- ku, Tok yo 10 4-0033
Japan
Tel: (81 ) 3-35 23-35 51
Fax : (8 1) 3-3 523-758 1
Memory
2325 O rch ard Parkw ay
San Jo se, C A 95131 , U SA
Tel : 1(408 ) 441-031 1
Fax: 1(408) 43 6-43 14
Microcontrollers
2325 O rch ard Parkw ay
San Jo se, C A 95131 , U SA
Tel : 1(408 ) 441-031 1
Fax: 1(408) 43 6-43 14
La Ch antrer ie
BP 70 602
44306 Na ntes Cede x 3, Fra nce
Tel : (33) 2-4 0-18 -18-18
Fax: (33) 2-40-18-19-60
ASIC/ASSP/Smart Cards
Zone I n dustrie lle
13106 Rousse t Ced ex, France
Tel : (33) 4-4 2-53 -60-00
Fax: (33) 4-42-53-60-01
1150 E ast C heyenn e Mtn. Blvd.
Col orado Spri ngs, CO 8 0906, USA
Tel : 1(719 ) 576-330 0
Fax: 1(719) 54 0-17 59
Scottish Enterprise Technology Park
Maxwell Building
East Kilbrid e G7 5 0QR, S cotlan d
Tel : (44) 13 55-803- 000
Fax: (44) 1355 -242 -743
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 H eilbr onn, Ge rmany
Tel: (49) 71-31-67-0
Fax : (4 9) 71- 31-67-234 0
1150 Ea st Ch eyenne M tn. B lvd.
Colo rado Spr ings, CO 80 906, USA
Tel: 1(7 19) 57 6-3300
Fax : 1( 719) 540 -1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de R ocheplei ne
BP 123
38521 S aint- Egreve Cedex, France
Tel: (33) 4-76-58-30-00
Fax : (3 3) 4-7 6-58-34- 80
Literature Requests
www.atmel.com/literature
© Atmel Corporation 2003. All rights reserved. Atmel® and combinations thereof, and Da taF lash® are the registered trademarks, and Rap-
idS™, Rapid8™ and e-STAC™ are the trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be the trade-
marks of others.
