Hitachi Single-Chip Microcomputer H8S/2194 Series, H8S/2194F-ZTATTM H8S/2194, HD6432194, HD64F2194, H8S/2193, HD6432193 H8S/2192, HD6432192 H8S/2191, HD6432191 Hardware Manual ADE-602-160 Ver 0.1 11/20/98 Hitachi, Ltd. Notice When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Contents Contents ..... .....................................................................................................i Section 1 Overview ........................................................................................1 1.1 Overview ......................................................................................................................... 1 1.2 Internal Block Diagram.................................................................................................... 6 1.3 Pin Arrangement and Functions ....................................................................................... 7 1.3.1 Pin Arrangement................................................................................................. 7 1.3.2 Pin Functions ...................................................................................................... 8 Section 2 CPU................................................................................................15 2.1 Overview ......................................................................................................................... 15 2.1.1 Features .............................................................................................................. 15 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU ................................... 16 2.1.3 Differences from H8/300 CPU ............................................................................ 17 2.1.4 Differences from H8/300H CPU ......................................................................... 17 2.2 CPU Operating Modes ..................................................................................................... 18 2.3 Address Space.................................................................................................................. 23 2.4 Register Configuration ..................................................................................................... 24 2.4.1 Overview ............................................................................................................ 24 2.4.2 General Registers................................................................................................ 25 2.4.3 Control Registers ................................................................................................ 26 2.4.4 Initial Register Values ........................................................................................ 27 2.5 Data Formats.................................................................................................................... 28 2.5.1 General Register Data Formats ........................................................................... 28 2.5.2 Memory Data Formats ........................................................................................ 30 2.6 Instruction Set.................................................................................................................. 31 2.6.1 Overview ............................................................................................................ 31 2.6.2 Instructions and Addressing Modes..................................................................... 31 2.6.3 Table of Instructions Classified by Function ....................................................... 33 2.6.4 Basic Instruction Formats ................................................................................... 43 2.6.5 Notes on Use of Bit-Manipulation Instructions.................................................... 44 2.7 Addressing Modes and Effective Address Calculation...................................................... 44 2.7.1 Addressing Mode................................................................................................ 44 2.7.2 Effective Address Calculation............................................................................. 47 2.8 Processing States.............................................................................................................. 51 2.8.1 Overview ............................................................................................................ 51 2.8.2 Reset State .......................................................................................................... 52 2.8.3 Exception-Handling State ................................................................................... 53 2.8.4 Program Execution State..................................................................................... 54 Rev. 0.1, 11/98, page i of xviii 2.8.5 Power-Down State .............................................................................................. 54 2.9 Basic Timing ................................................................................................................... 55 2.9.1 Overview ............................................................................................................ 55 2.9.2 On-Chip Memory (ROM, RAM)......................................................................... 55 2.9.3 On-Chip Supporting Module Access Timing....................................................... 56 Section 3 MCU Operating Modes .................................................................... 57 3.1 Overview ......................................................................................................................... 57 3.1.1 Operating Mode Selection .................................................................................. 57 3.1.2 Register Configuration........................................................................................ 57 3.2 Register Descriptions ....................................................................................................... 58 3.2.1 Mode Control Register (MDCR)......................................................................... 58 3.2.2 System Control Register (SYSCR)...................................................................... 58 3.3 Operating Mode Descriptions........................................................................................... 59 3.3.1 Mode 1 ............................................................................................................... 59 3.4 Address Map in Each Operating Mode............................................................................. 60 Section 4 Power-Down State.......................................................................... 63 4.1 Overview ......................................................................................................................... 63 4.1.1 Register Configuration........................................................................................ 67 4.2 Register Descriptions ....................................................................................................... 67 4.2.1 Standby Control Register (SBYCR) .................................................................... 67 4.2.2 Low-Power Control Register (LPWRCR) ........................................................... 69 4.2.3 Timer Register A (TMA) .................................................................................... 71 4.2.4 Module Stop Control Register (MSTPCR) .......................................................... 73 4.3 Medium-Speed Mode....................................................................................................... 74 4.4 Sleep Mode...................................................................................................................... 75 4.4.1 Sleep Mode......................................................................................................... 75 4.4.2 Clearing Sleep Mode .......................................................................................... 75 4.5 Module Stop Mode .......................................................................................................... 76 4.5.1 Module Stop Mode ............................................................................................. 76 4.6 Standby Mode.................................................................................................................. 77 4.6.1 Standby Mode..................................................................................................... 77 4.6.2 Clearing Standby Mode ...................................................................................... 77 4.6.3 Setting Oscillation Settling Time after Clearing Standby Mode .......................... 77 4.7 Watch Mode .................................................................................................................... 79 4.7.1 Watch Mode ....................................................................................................... 79 4.7.2 Clearing Watch Mode......................................................................................... 79 4.8 Subsleep Mode................................................................................................................. 80 4.8.1 Subsleep Mode ................................................................................................... 80 4.8.2 Clearing Subsleep Mode ..................................................................................... 80 4.9 Subactive Mode ............................................................................................................... 81 4.9.1 Subactive Mode .................................................................................................. 81 Rev. 0.1, 11/98, page ii of xviii 4.9.2 Clearing Subactive Mode.................................................................................... 81 4.10 Direct Transition ............................................................................................................ 82 4.10.1 Overview of Direct Transition........................................................................... 82 Section 5 Exception Handling ........................................................................83 5.1 Overview ......................................................................................................................... 83 5.1.1 Exception Handling Types and Priority............................................................... 83 5.1.2 Exception Handling Operation............................................................................ 84 5.1.3 Exception Sources and Vector Table................................................................... 84 5.2 Reset................................................................................................................................ 86 5.2.1 Overview ............................................................................................................ 86 5.2.2 Reset Sequence................................................................................................... 86 5.2.3 Interrupts after Reset........................................................................................... 87 5.3 Interrupts ......................................................................................................................... 88 5.4 Trap Instruction ............................................................................................................... 89 5.5 Stack Status after Exception Handling ............................................................................. 90 5.6 Notes on Use of the Stack ................................................................................................ 91 Section 6 Interrupt Controller...........................................................................93 6.1 Overview ......................................................................................................................... 93 6.1.1 Features .............................................................................................................. 93 6.1.2 Block Diagram.................................................................................................... 94 6.1.3 Pin Configuration................................................................................................ 95 6.1.4 Register Configuration........................................................................................ 95 6.2 Register Descriptions ....................................................................................................... 96 6.2.1 System Control Register (SYSCR)...................................................................... 96 6.2.2 Interrupt Control Registers A to D (ICRA to ICRD)............................................ 97 6.2.3 IRQ Enable Register (IENR)............................................................................... 98 6.2.4 IRQ Edge Select Registers (IEGR)...................................................................... 99 6.2.5 IRQ Status Register (IRQR)................................................................................ 100 6.2.6 Port Mode Register (PMR1)................................................................................ 101 6.3 Interrupt Sources.............................................................................................................. 102 6.3.1 External Interrupts .............................................................................................. 102 6.3.2 Internal Interrupts ............................................................................................... 104 6.3.3 Interrupt Exception Vector Table........................................................................ 104 6.4 Interrupt Operation........................................................................................................... 107 6.4.1 Interrupt Control Modes and Interrupt Operation ................................................ 107 6.4.2 Interrupt Control Mode 0 .................................................................................... 109 6.4.3 Interrupt Control Mode 1 .................................................................................... 111 6.4.4 Interrupt Exception Handling Sequence .............................................................. 114 6.4.5 Interrupt Response Times ................................................................................... 115 6.5 Usage Notes..................................................................................................................... 116 6.5.1 Contention between Interrupt Generation and Disabling ..................................... 116 Rev. 0.1, 11/98, page iii of xviii 6.5.2 Instructions that Disable Interrupts...................................................................... 117 6.5.3 Interrupts during Execution of EEPMOV Instruction .......................................... 117 Section 7 ROM .............................................................................................. 119 7.1 Overview ......................................................................................................................... 119 7.1.1 Block Diagram ................................................................................................... 119 7.2 Overview of Flash Memory.............................................................................................. 120 7.2.1 Features .............................................................................................................. 120 7.2.2 Block Diagram ................................................................................................... 121 7.2.3 Flash Memory Operating Modes......................................................................... 122 7.2.4 Pin Configuration ............................................................................................... 126 7.2.5 Register Configuration........................................................................................ 126 7.3 Flash Memory Register Descriptions................................................................................ 127 7.3.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 127 7.3.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 130 7.3.3 Erase Block Registers 1 and 2 (EBR1, EBR2) .................................................... 131 7.3.4 Serial/Timer Control Register (STCR)................................................................ 132 7.4 On-Board Programming Modes........................................................................................ 133 7.4.1 Boot Mode.......................................................................................................... 134 7.4.2 User Program Mode............................................................................................ 139 7.5 Programming/Erasing Flash Memory............................................................................... 141 7.5.1 Program Mode .................................................................................................... 141 7.5.2 Program-Verify Mode......................................................................................... 142 7.5.3 Erase Mode......................................................................................................... 144 7.5.4 Erase-Verify Mode ............................................................................................. 144 7.6 Flash Memory Protection ................................................................................................. 146 7.6.1 Hardware Protection ........................................................................................... 146 7.6.2 Software Protection ............................................................................................ 147 7.6.3 Error Protection .................................................................................................. 148 7.7 Interrupt Handling when Programming/Erasing Flash Memory........................................ 149 7.8 Flash Memory Writer Mode............................................................................................. 150 7.8.1 Writer Mode Setting ........................................................................................... 150 7.8.2 Socket Adapters and Memory Map ..................................................................... 150 7.8.3 Writer Mode Operation....................................................................................... 151 7.8.4 Memory Read Mode ........................................................................................... 153 7.8.5 Auto-Program Mode ........................................................................................... 156 7.8.6 Auto-Erase Mode................................................................................................ 158 7.8.7 Status Read Mode............................................................................................... 159 7.8.8 Status Polling...................................................................................................... 161 7.8.9 Writer Mode Transition Time ............................................................................. 162 7.8.10 Notes On Memory Programming ...................................................................... 162 7.9 Flash Memory Programming and Erasing Precautions...................................................... 163 Rev. 0.1, 11/98, page iv of xviii Section 8 RAM...............................................................................................165 8.1 Overview ......................................................................................................................... 165 8.1.1 Block Diagram.................................................................................................... 165 Section 9 Clock Pulse Generator ....................................................................167 9.1 Overview ......................................................................................................................... 167 9.1.1 Block Diagram.................................................................................................... 167 9.1.2 Register Configuration........................................................................................ 167 9.2 Register Descriptions ....................................................................................................... 168 9.2.1 Standby Control Register (SBYCR) .................................................................... 168 9.2.2 Low-Power Control Register (LPWRCR) ........................................................... 169 9.3 Oscillator ......................................................................................................................... 170 9.3.1 Connecting a Crystal Resonator .......................................................................... 170 9.3.2 External Clock Input........................................................................................... 172 9.4 Duty Adjustment Circuit .................................................................................................. 175 9.5 Medium-Speed Clock Divider.......................................................................................... 175 9.6 Bus Master Clock Selection Circuit.................................................................................. 175 9.7 Subclock Oscillator Circuit .............................................................................................. 176 9.7.1 Connecting 32.768 kHz Crystal Resonator.......................................................... 176 9.7.2 External Clock Input........................................................................................... 177 9.7.3 When Subclock is not Needed............................................................................. 177 9.8 Subclock Waveform Shaping Circuit ............................................................................... 178 9.9 Notes on the Resonator .................................................................................................... 178 Section 10 I/O Port.........................................................................................179 10.1 Overview ....................................................................................................................... 179 10.1.1 Port Functions................................................................................................... 179 10.1.2 Port Input.......................................................................................................... 179 10.1.3 MOS Pull-Up Transistors .................................................................................. 181 10.2 Port 0 ............................................................................................................................. 183 10.2.1 Overview .......................................................................................................... 183 10.2.2 Register Configuration...................................................................................... 184 10.2.3 Pin Functions .................................................................................................... 185 10.2.4 Pin States .......................................................................................................... 185 10.3 Port 1 ............................................................................................................................. 186 10.3.1 Overview .......................................................................................................... 186 10.3.2 Register Configuration...................................................................................... 186 10.3.3 Pin Functions .................................................................................................... 190 10.3.4 Pin States .......................................................................................................... 191 10.4 Port 2 ............................................................................................................................. 192 10.4.1 Overview .......................................................................................................... 192 10.4.2 Register Configuration...................................................................................... 192 10.4.3 Pin Functions .................................................................................................... 196 Rev. 0.1, 11/98, page v of xviii 10.4.4 Pin States.......................................................................................................... 198 10.5 Port 3 ............................................................................................................................. 199 10.5.1 Overview .......................................................................................................... 199 10.5.2 Register Configuration...................................................................................... 199 10.5.3 Pin Functions .................................................................................................... 203 10.5.4 Pin States.......................................................................................................... 205 10.6 Port 4 ............................................................................................................................. 206 10.6.1 Overview .......................................................................................................... 206 10.6.2 Register Configuration...................................................................................... 206 10.6.3 Pin Functions .................................................................................................... 209 10.6.4 Pin States.......................................................................................................... 211 10.7 Port 5 ............................................................................................................................. 212 10.7.1 Overview .......................................................................................................... 212 10.7.2 Register Configuration...................................................................................... 212 10.7.3 Pin Functions .................................................................................................... 215 10.7.4 Pin States.......................................................................................................... 216 10.8 Port 6 ............................................................................................................................. 217 10.8.1 Overview .......................................................................................................... 217 10.8.2 Register Configuration...................................................................................... 218 10.8.3 Pin Functions .................................................................................................... 221 10.8.4 Operation.......................................................................................................... 222 10.8.5 Pin States.......................................................................................................... 223 10.9 Port 7 ............................................................................................................................. 224 10.9.1 Overview .......................................................................................................... 224 10.9.2 Register Configuration...................................................................................... 224 10.9.3 Pin Functions .................................................................................................... 226 10.9.4 Pin States.......................................................................................................... 226 10.10 Port 8 ........................................................................................................................... 227 10.10.1 Overview ........................................................................................................ 227 10.10.2 Register Configuration.................................................................................... 227 10.10.3 Pin Functions .................................................................................................. 230 10.10.4 Pin States ........................................................................................................ 232 Section 11 Timer A........................................................................................ 233 11.1 Overview ....................................................................................................................... 233 11.1.1 Features ............................................................................................................ 233 11.1.2 Block Diagram.................................................................................................. 234 11.1.3 Register Configuration...................................................................................... 234 11.2 Descriptions of Respective Registers.............................................................................. 235 11.2.1 Timer Mode Register A (TMA) ........................................................................ 235 11.2.2 Timer Counter A (TCA) ................................................................................... 237 11.2.3 Module Stop Control Register (MSTPCR) ........................................................ 237 Rev. 0.1, 11/98, page vi of xviii 11.3 Operation ....................................................................................................................... 238 11.3.1 Operation as the Interval Timer......................................................................... 238 11.3.2 Operation of the Timer for Clocks .................................................................... 238 11.3.3 Initializing the Counts....................................................................................... 238 Section 12 Timer B ..........................................................................................239 12.1 Overview ....................................................................................................................... 239 12.1.1 Features ............................................................................................................ 239 12.1.2 Block Diagram.................................................................................................. 239 12.1.3 Pin Configuration.............................................................................................. 240 12.1.4 Register Configuration...................................................................................... 240 12.2 Descriptions of Respective Registers.............................................................................. 241 12.2.1 Timer Mode Register B (TMB)......................................................................... 241 12.2.2 Timer Counter B (TCB).................................................................................... 243 12.2.3 Timer Load Register B (TLB)........................................................................... 243 12.2.4 Port Mode Register 5 (PMR5)........................................................................... 244 12.2.5 Module Stop Control Register (MSTPCR) ........................................................ 244 12.3 Operation ....................................................................................................................... 245 12.3.1 Operation as the Interval Timer......................................................................... 245 12.3.2 Operation as the Auto Reload Timer ................................................................. 245 12.3.3 Event Counter................................................................................................... 246 Section 13 Timer J ...........................................................................................247 13.1 Overview ....................................................................................................................... 247 13.1.1 Features ............................................................................................................ 247 13.1.2 Block Diagram.................................................................................................. 248 13.1.3 Pin Configuration.............................................................................................. 249 13.1.4 Register Configuration...................................................................................... 249 13.2 Descriptions of Respective Registers.............................................................................. 250 13.2.1 Timer Mode Register J (TMJ)........................................................................... 250 13.2.2 Timer J Control Register (TMJC)...................................................................... 254 13.2.3 Timer J Status Register (TMJS) ........................................................................ 256 13.2.4 Timer Counter J (TCJ) ...................................................................................... 257 13.2.5 Timer Counter K (TCK).................................................................................... 257 13.2.6 Timer Load Register J (TLJ)............................................................................. 258 13.2.7 Timer Load Register K (TLK) .......................................................................... 258 13.2.8 Module Stop Control Register (MSTPCR) ........................................................ 259 13.3 Operation ....................................................................................................................... 260 13.3.1 8-bit Reload Timer (TMJ-1).............................................................................. 260 13.3.2 8-bit Reload Timer (TMJ-2).............................................................................. 260 13.3.3 Remote Controlled Data Transmission.............................................................. 261 Rev. 0.1, 11/98, page vii of xviii Section 14 Timer L ........................................................................................ 265 14.1 Overview ....................................................................................................................... 265 14.1.1 Features ............................................................................................................ 265 14.1.2 Block Diagram.................................................................................................. 266 14.1.3 Register Configuration...................................................................................... 267 14.2 Descriptions of Respective Registers.............................................................................. 268 14.2.1 Timer L Mode Register (LMR)......................................................................... 268 14.2.2 Linear Time Counter (LTC).............................................................................. 270 14.2.3 Reload/Compare Match Register (RCR) ........................................................... 270 14.2.4 Module Stop Control Register (MSTPCR) ........................................................ 271 14.3 Operation ....................................................................................................................... 272 14.3.1 Compare Match Clear Operation....................................................................... 272 Section 15 Timer R ........................................................................................ 275 15.1 Overview ....................................................................................................................... 275 15.1.1 Features ............................................................................................................ 275 15.1.2 Block Diagram.................................................................................................. 275 15.1.3 Pin Configuration.............................................................................................. 277 15.1.4 Register Configuration...................................................................................... 277 15.2 Descriptions of Respective Registers.............................................................................. 278 15.2.1 Timer R Mode Register 1 (TMRM1) ................................................................ 278 15.2.2 Timer R Mode Register 2 (TMRM2) ................................................................ 280 15.2.3 Timer R Control/Status Register (TMRCS)....................................................... 283 15.2.4 Timer R Capture Register 1 (TMRCP1)............................................................ 285 15.2.5 Timer R Capture Register 2 (TMRCP2)............................................................ 286 15.2.6 Timer R Load Register 1 (TMRL1) .................................................................. 286 15.2.7 Timer R Load Register 2 (TMRL2) .................................................................. 287 15.2.8 Timer R Load Register 3 (TMRL3) .................................................................. 287 15.2.9 Module Stop Control Register (MSTPCR) ........................................................ 288 15.3 Operation ....................................................................................................................... 289 15.3.1 Reload Timer Counter Equipped with Capturing Function TMRU-1................. 289 15.3.2 Reload Timer Counter Equipped with Capturing Function TMRU-2................. 290 15.3.3 Reload Counter Timer TMRU-3 ....................................................................... 290 15.3.4 Mode Identification .......................................................................................... 291 15.3.5 Reeling Controls ............................................................................................... 291 15.3.6 Acceleration and Braking Processes of the Capstan Motor................................ 291 15.3.7 Slow Tracking Mono-multi Function ................................................................ 292 15.4 Interrupt Cause............................................................................................................... 294 15.5 Exemplary Settings for Respective Functions................................................................. 295 15.5.1 Mode Identification .......................................................................................... 295 15.5.2 Reeling Controls ............................................................................................... 296 15.5.3 Slow Tracking Mono-multi Function ................................................................ 296 Rev. 0.1, 11/98, page viii of xviii 15.5.4 Acceleration and Braking Processes of the Capstan Motor ................................ 297 Section 16 Timer X1 ......................................................................................299 16.1 Overview ....................................................................................................................... 299 16.1.1 Features ............................................................................................................ 299 16.1.2 Block Diagram.................................................................................................. 300 16.1.3 Pin Configuration.............................................................................................. 301 16.1.4 Register Configuration...................................................................................... 302 16.2 Descriptions of Respective Registers.............................................................................. 303 16.2.1 Free Running Counter (FRC) ............................................................................ 303 16.2.2 Output Comparing Register A and B (OCRA and OCRB)................................. 304 16.2.3 Input Capture Register A Through D (ICRA Through ICRD)............................ 305 16.2.4 Timer Interrupt Enabling Register (TIER)......................................................... 307 16.2.5 Timer Control/Status Register X (TCSRX) ....................................................... 309 16.2.6 Timer Control Register X (TCRX).................................................................... 314 16.2.7 Timer Output Comparing Control Register (TOCR).......................................... 316 16.2.8 Module Stop Control Register (MSTPCR) ........................................................ 318 16.3 Operation ....................................................................................................................... 319 16.3.1 Operation of the Timer X1................................................................................ 319 16.3.2 Counting Timing of the FRC............................................................................. 320 16.3.3 Output Comparing Signal Outputting Timing.................................................... 321 16.3.4 FRC Clearing Timing ....................................................................................... 321 16.3.5 Input Capture Signal Inputting Timing.............................................................. 322 16.3.6 Input Capture Flag (ICFA through ICFD) Setting Up Timing............................ 323 16.3.7 Output Comparing Flag (OCFA and OCFB) Setting Up Timing........................ 324 16.3.8 Overflow Flag (CVF) Setting Up Timing .......................................................... 324 16.4 Operation Mode of the Timer X1 ................................................................................... 325 16.5 Interrupt Causes ............................................................................................................. 326 16.6 Exemplary Uses of the Timer X1 ................................................................................... 327 16.7 Precautions when Using the Timer X1 ........................................................................... 328 16.7.1 Competition between Writing and Clearing with the FRC................................. 328 16.7.2 Competition between Writing and Counting Up with the FRC .......................... 329 16.7.3 Competition between Writing and Comparing Match with the OCR ................. 330 16.7.4 Changing Over the Internal Clocks and Counter Operations.............................. 331 Section 17 Watchdog Timer (WDT)...............................................................333 17.1 Overview ....................................................................................................................... 333 17.1.1 Features ............................................................................................................ 333 17.1.2 Block Diagram.................................................................................................. 334 17.1.3 Register Configuration...................................................................................... 335 17.2 Register Descriptions ..................................................................................................... 336 17.2.1 Watchdog Timer Counter (WTCNT) ................................................................ 336 17.2.2 Watchdog Timer Control/Status Register (WTCSR) ......................................... 336 Rev. 0.1, 11/98, page ix of xviii 17.2.3 System Control Register (SYSCR).................................................................... 339 17.2.4 Notes on Register Access.................................................................................. 340 17.3 Operation ....................................................................................................................... 341 17.3.1 Watchdog Timer Operation............................................................................... 341 17.3.2 Interval Timer Operation .................................................................................. 342 17.3.3 Timing of Setting of Overflow Flag (OVF) ....................................................... 343 17.4 Interrupts ....................................................................................................................... 344 17.5 Usage Notes................................................................................................................... 344 17.5.1 Contention between Watchdog Timer Counter (WTCNT) ................................ 344 17.5.2 Changing Value of CKS2 to CKS0 ................................................................... 345 17.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode............... 345 Section 18 8-Bit PWM..................................................................................... 347 18.1 Overview ....................................................................................................................... 347 18.1.1 Features ............................................................................................................ 347 18.1.2 Block Diagram.................................................................................................. 347 18.1.3 Pin Configuration.............................................................................................. 348 18.1.4 Register Configuration...................................................................................... 348 18.2 Register Descriptions ..................................................................................................... 349 18.2.1 Bit PWM Data Registers 0, 1, 2 and 3............................................................... 349 18.2.2 8-bit PWM Control Register (PW8CR) ............................................................. 350 18.2.3 Port Mode Register 3 (PMR3)........................................................................... 351 18.2.4 Module Stop Control Register (MSTPCR) ........................................................ 352 18.3 8-Bit PWM Operation .................................................................................................... 353 Section 19 12-Bit PWM ................................................................................. 355 19.1 Overview ....................................................................................................................... 355 19.1.1 Features ............................................................................................................ 355 19.1.2 Block Diagram.................................................................................................. 356 19.1.3 Pin Configuration.............................................................................................. 357 19.1.4 Register Configuration...................................................................................... 357 19.2 Register Descriptions ..................................................................................................... 358 19.2.1 12-Bit PWM Control Registers (CPWCR, DPWCR)......................................... 358 19.2.2 12-Bit PWM Data Registers (DPWDR, CPWDR)............................................. 361 19.3 Operation ....................................................................................................................... 362 19.3.1 Output Waveform ............................................................................................. 362 Section 20 14-Bit PWM ................................................................................. 365 20.1 Overview ....................................................................................................................... 365 20.1.1 Features ............................................................................................................ 365 20.1.2 Block Diagram.................................................................................................. 366 20.1.3 Pin Configuration.............................................................................................. 366 20.1.4 Register Configuration...................................................................................... 367 Rev. 0.1, 11/98, page x of xviii 20.2 Register Descriptions ..................................................................................................... 367 20.2.1 PWM Control Register (PWCR) ....................................................................... 367 20.2.2 PWM Data Registers U and L (PWDRU, PWDRL) .......................................... 368 20.2.3 Module Stop Control Register (MSTPCR) ........................................................ 369 20.3 14-Bit PWM Operation .................................................................................................. 370 Section 21 Prescalar Unit ...............................................................................371 21.1 Overview ....................................................................................................................... 371 21.1.1 Features ............................................................................................................ 371 21.1.2 Block Diagram.................................................................................................. 372 21.1.3 Pin Configuration.............................................................................................. 373 21.1.4 Register Configuration...................................................................................... 373 21.2 Registers ........................................................................................................................ 374 21.2.1 Input Capture Register 1 (ICR1) ....................................................................... 374 21.2.2 Prescalar Unit Control/Status Register (PCSR).................................................. 375 21.2.3 Port Mode Register 1 (PMR1)........................................................................... 377 21.3 Noise Cancel Circuit ...................................................................................................... 378 21.4 Operation ....................................................................................................................... 378 21.4.1 Prescalar S (PSS) .............................................................................................. 378 21.4.2 Prescalar W (PSW) ........................................................................................... 379 21.4.3 Stable Oscillation Wait Time Count.................................................................. 379 21.4.4 8-Bit PWM ....................................................................................................... 380 21.4.5 8-Bit Input Capture Using IC Pin ...................................................................... 380 21.4.6 Frequency Division Clock Output ..................................................................... 380 Section 22 Serial Communication Interface 1 (SCI1) .....................................381 22.1 Overview ....................................................................................................................... 381 22.1.1 Features ............................................................................................................ 381 22.1.2 Block Diagram.................................................................................................. 383 22.1.3 Pin Configuration.............................................................................................. 384 22.1.4 Register Configuration...................................................................................... 384 22.2 Register Descriptions ..................................................................................................... 385 22.2.1 Receive Shift Register (RSR)............................................................................ 385 22.2.2 Receive Data Register (RDR) ........................................................................... 385 22.2.3 Transmit Shift Register (TSR)........................................................................... 386 22.2.4 Transmit Data Register (TDR) .......................................................................... 386 22.2.5 Serial Mode Register (SMR) ............................................................................. 387 22.2.6 Serial Control Register (SCR) ........................................................................... 390 22.2.7 Serial Status Register (SSR).............................................................................. 393 22.2.8 Bit Rate Register (BRR) ................................................................................... 397 22.2.9 Serial Interface Mode Register (SCMR)............................................................ 404 22.2.10 Module Stop Control Register (MSTPCR) ...................................................... 405 Rev. 0.1, 11/98, page xi of xviii 22.3 Operation ....................................................................................................................... 406 22.3.1 Overview .......................................................................................................... 406 22.3.2 Operation in Asynchronous Mode..................................................................... 409 22.3.3 Multiprocessor Communication Function.......................................................... 417 22.3.4 Operation in Synchronous Mode ....................................................................... 424 22.4 SCI Interrupts................................................................................................................. 433 22.5 Usage Notes................................................................................................................... 434 Section 23 Serial Communication Interface 2 (SCI2) ..................................... 437 23.1 Overview ....................................................................................................................... 437 23.1.1 Features ............................................................................................................ 437 23.1.2 Block Diagram.................................................................................................. 438 23.1.3 Pin Configuration.............................................................................................. 439 23.1.4 Register Configuration...................................................................................... 439 23.2 Register Descriptions ..................................................................................................... 440 23.2.1 Starting Address Register (STAR) .................................................................... 440 23.2.2 Ending Address Register (EDAR)..................................................................... 440 23.2.3 Serial Control Register 2 (SCR2) ...................................................................... 441 23.2.4 Serial Control Status Register 2 (SCSR2).......................................................... 443 23.2.5 Module Stop Control Register (MSTPCR) ........................................................ 445 23.3 Operation ....................................................................................................................... 446 23.3.1 Clock ................................................................................................................ 446 23.3.2 Data Transfer Format........................................................................................ 446 23.3.3 Data Transfer Operations .................................................................................. 449 23.4 Interrupt Sources............................................................................................................ 453 Section 24 I2C Bus Interface (IIC)................................................................. 455 24.1 Overview ....................................................................................................................... 455 24.1.1 Features ............................................................................................................ 455 24.1.2 Block Diagram.................................................................................................. 456 24.1.3 Pin Configuration.............................................................................................. 457 24.1.4 Register Configuration...................................................................................... 458 24.2 Register Descriptions ..................................................................................................... 459 2 24.2.1 I C Bus Data Register (ICDR)........................................................................... 459 24.2.2 Slave Address Register (SAR) .......................................................................... 462 24.2.3 Second Slave Address Register (SARX) ........................................................... 463 2 24.2.4 I C Bus Mode Register (ICMR) ........................................................................ 464 2 24.2.5 I C Bus Control Register (ICCR) ...................................................................... 466 2 24.2.6 I C Bus Status Register (ICSR) ......................................................................... 474 24.2.7 Serial/Timer Control Register (STCR) .............................................................. 479 24.2.8 Module Stop Control Register (MSTPCR) ........................................................ 480 Rev. 0.1, 11/98, page xii of xviii 24.3 Operation ....................................................................................................................... 481 2 24.3.1 I C Bus Data Format ......................................................................................... 481 24.3.2 Master Transmit Operation ............................................................................... 482 24.3.3 Master Receive Operation................................................................................. 484 24.3.4 Slave Receive Operation................................................................................... 486 24.3.5 Slave Transmit Operation ................................................................................. 488 24.3.6 IRIC Setting Timing and SCL Control .............................................................. 490 24.3.7 Noise Canceler.................................................................................................. 491 24.3.8 Sample Flowcharts............................................................................................ 492 24.3.9 Initialization of Internal State............................................................................ 495 24.4 Usage Notes ................................................................................................................... 496 Section 25 A/D Converter ..............................................................................503 25.1 Overview ....................................................................................................................... 503 25.1.1 Features ............................................................................................................ 503 25.1.2 Block Diagram.................................................................................................. 504 25.1.3 Pin Configuration.............................................................................................. 505 25.1.4 Register Configuration...................................................................................... 506 25.2 Register Descriptions ..................................................................................................... 507 25.2.1 Software-Triggered A/D Result Register (ADR) ............................................... 507 25.2.2 Hardware-Triggered A/D Result Register (AHR) .............................................. 507 25.2.3 A/D Control Register (ADCR) .......................................................................... 508 25.2.4 A/D Control/Status Register (ADCSR).............................................................. 511 25.2.5 Trigger Select Register (ADTSR) ..................................................................... 514 25.2.6 Port Mode Register 0 (PMR0)........................................................................... 515 25.2.7 Module Stop Control Register (MSTPCR) ........................................................ 515 25.3 Interface to Bus Master .................................................................................................. 516 25.4 Operation ....................................................................................................................... 518 25.4.1 Software-Triggered A/D Conversion................................................................. 518 25.4.2 Hardware- or External-Triggered A/D Conversion ............................................ 519 25.5 Interrupt Sources............................................................................................................ 520 Section 26 Address Trap Controller (ATC) ....................................................521 26.1 Overview ....................................................................................................................... 521 26.1.1 Features ............................................................................................................ 521 26.1.2 Block Diagram.................................................................................................. 521 26.1.3 Register Configuration...................................................................................... 522 26.2 Register Descriptions ..................................................................................................... 522 26.2.1 Address Trap Control Register (ATCR) ............................................................ 522 26.2.2 Trap Address Register 2 to 0 (TAR2 to TAR0) ................................................. 523 26.3 Precautions in Usage ...................................................................................................... 524 26.3.1 Basic Operations............................................................................................... 524 26.3.2 Enable............................................................................................................... 526 Rev. 0.1, 11/98, page xiii of xviii 26.3.3 Bcc Instruction.................................................................................................. 527 26.3.4 BSR Instruction ................................................................................................ 531 26.3.5 JSR Instruction ................................................................................................. 532 26.3.6 JMP Instruction................................................................................................. 533 26.3.7 RTS Instruction................................................................................................. 534 26.3.8 SLEEP Instruction ............................................................................................ 534 26.3.9 Competing Interrupt.......................................................................................... 538 Section 27 Servo Circuits............................................................................... 541 27.1 Overview ....................................................................................................................... 541 27.1.1 Functions .......................................................................................................... 541 27.1.2 Block Diagram.................................................................................................. 542 27.2 Servo Port ...................................................................................................................... 543 27.2.1 Overview .......................................................................................................... 543 27.2.2 Block Diagram.................................................................................................. 543 27.2.3 Pin Configuration.............................................................................................. 545 27.2.4 Register Configuration...................................................................................... 546 27.2.5 Register Descriptions ........................................................................................ 546 27.2.6 DFG/DPG Input Signals.................................................................................... 554 27.3 Reference Signal Generators .......................................................................................... 554 27.3.1 Overview .......................................................................................................... 554 27.3.2 Block Diagram.................................................................................................. 554 27.3.3 Register Configuration...................................................................................... 556 27.3.4 Register Descriptions ........................................................................................ 557 27.3.5 Description of Operation................................................................................... 562 27.4 HSW (Head-switch) Timing Generator .......................................................................... 577 27.4.1 Overview .......................................................................................................... 577 27.4.2 Block Diagram.................................................................................................. 578 27.4.3 Register Configuration...................................................................................... 580 27.4.4 Register Descriptions ........................................................................................ 580 27.4.5 Description of Operation................................................................................... 592 27.4.6 Interruption....................................................................................................... 597 27.4.7 Cautions............................................................................................................ 598 27.5 Four-head High-speed Switching Circuit for Special Playback....................................... 599 27.5.1 Overview .......................................................................................................... 599 27.5.2 Block Diagram.................................................................................................. 599 27.5.3 Pin Configuration.............................................................................................. 600 27.5.4 Register Description ......................................................................................... 600 27.6 Drum Speed Error Detector............................................................................................ 603 27.6.1 Overview .......................................................................................................... 603 27.6.2 Block Diagram.................................................................................................. 603 27.6.3 Register Configuration...................................................................................... 605 27.6.4 Register Descriptions ........................................................................................ 606 Rev. 0.1, 11/98, page xiv of xviii 27.6.5 Description of Operation................................................................................... 611 27.6.6 fH Correction in Trick Play Mode ...................................................................... 613 27.7 Drum Phase Error Detector ............................................................................................ 614 27.7.1 Overview .......................................................................................................... 614 27.7.2 Block Diagram.................................................................................................. 614 27.7.3 Register Configuration...................................................................................... 616 27.7.4 Register Descriptions ........................................................................................ 617 27.7.5 Description of Operation................................................................................... 620 27.7.6 Phase Comparison............................................................................................. 622 27.8 Capstan Speed Error Detector ........................................................................................ 623 27.8.1 Overview .......................................................................................................... 623 27.8.2 Block Diagram.................................................................................................. 623 27.8.3 Register Configuration...................................................................................... 625 27.8.4 Register Descriptions ........................................................................................ 626 27.8.5 Description of Operation................................................................................... 630 27.9 Capstan Phase Error Detector......................................................................................... 632 27.9.1 Overview .......................................................................................................... 632 27.9.2 Block Diagram.................................................................................................. 632 27.9.3 Register Configuration...................................................................................... 633 27.9.4 Register Descriptions ........................................................................................ 633 27.9.5 Description of Operation................................................................................... 637 27.10 X-Value and Tracking Adjustment Circuit ................................................................... 639 27.10.1 Overview ........................................................................................................ 639 27.10.2 Block Diagram................................................................................................ 639 27.10.3 Description of Registers .................................................................................. 641 27.11 Digital Filters ............................................................................................................... 644 27.11.1 Overview ........................................................................................................ 644 27.11.2 Block Diagram................................................................................................ 644 27.11.3 Arithmetic Buffer............................................................................................ 645 27.11.4 Register Configuration .................................................................................... 647 27.11.5 Register Description........................................................................................ 648 27.11.6 Filter Characteristics ....................................................................................... 656 27.11.7 Operations in Case of Transient Response....................................................... 658 -1 27.11.8 Initialization of Z .......................................................................................... 658 27.12 Additional V Signal...................................................................................................... 660 27.12.1 Overview ........................................................................................................ 660 27.12.2 Pin Configuration............................................................................................ 661 27.12.3 Register Configuration .................................................................................... 661 27.12.4 Register Description........................................................................................ 661 27.12.5 Additional V Pulse Signal ............................................................................... 663 27.13 CTL Circuit.................................................................................................................. 665 27.13.1 Overview ........................................................................................................ 665 27.13.2 Block Diagram................................................................................................ 665 Rev. 0.1, 11/98, page xv of xviii 27.13.3 Pin Configuration............................................................................................ 666 27.13.4 Register Configuration.................................................................................... 666 27.13.5 Register Descriptions ...................................................................................... 667 27.13.6 Operation........................................................................................................ 681 27.13.7 CTL Input Section .......................................................................................... 683 27.13.8 Duty Discriminator ......................................................................................... 686 27.13.9 CTL Output Section........................................................................................ 692 27.13.10 Trapezoid Waveform Circuit......................................................................... 695 27.13.11 Note on CTL Interrupt .................................................................................. 696 27.14 Frequency Dividers ...................................................................................................... 696 27.14.1 Overview ........................................................................................................ 696 27.14.2 CTL Frequency Divider .................................................................................. 696 27.14.3 CFG Frequency Divider .................................................................................. 699 27.14.4 DFG Noise Removal Circuit ........................................................................... 707 27.15 Sync Signal Detector.................................................................................................... 709 27.15.1 Overview ........................................................................................................ 709 27.15.2 Block Diagram................................................................................................ 710 27.15.3 Pin Configuration............................................................................................ 711 27.15.4 Register Configuration.................................................................................... 711 27.15.5 Register Descriptions ...................................................................................... 712 27.15.6 Noise Detection .............................................................................................. 720 27.15.7 Activation of the Sync Signal Detector ........................................................... 723 27.16 Servo Interrupt ............................................................................................................. 723 27.16.1 Overview ........................................................................................................ 723 27.16.2 Register Configuration.................................................................................... 723 27.16.3 Register Description........................................................................................ 724 Section 28 Electrical Characteristics .............................................................. 731 28.1 Absolute Maximum Ratings........................................................................................... 731 28.2 Electrical Characteristics of HD64F2194 ....................................................................... 732 28.2.1 DC Characteristics of HD64F2194.................................................................... 732 28.2.2 Allowable Output Currents of HD64F2194 ....................................................... 740 28.2.3 AC Characteristics of HD64F2194.................................................................... 741 28.2.4 Serial Interface Timing of HD64F2194............................................................. 745 28.2.5 A/D Converter Characteristics of HD64F2194 .................................................. 750 28.2.6 Servo Section Electrical Characteristics of HD64F2194.................................... 750 28.2.7 FLASH Memory Characteristics ....................................................................... 754 28.2.8 Usage Note ....................................................................................................... 755 28.3 Electrical Characteristics of HD6432194, HD6432193, ......... HD6432192 and HD6432191 756 28.3.1 DC Characteristics of HD6432194, HD6432193, ............HD6432192 and HD6432191 .......................................................................... 756 Rev. 0.1, 11/98, page xvi of xviii 28.3.2 Allowable Output Currents of HD6432194, HD6432193, ............HD6432192 and HD6432191 .......................................................................... 764 28.3.3 AC Characteristics of HD6432194, HD6432193, ............HD6432192 and HD6432191 .......................................................................... 765 28.3.4 Serial Interface Timing of HD6432194, HD6432193, ............HD6432192 and HD6432191 .......................................................................... 769 28.3.5 A/D Converter Characteristics of HD6432194, ............HD6432193, HD6432192 and HD6432191 ..................................................... 774 28.3.6 Servo Section Electrical Characteristics of ............HD6432194, HD6432193, HD6432192 and HD6432191................................. 774 Appendix A Instruction Set ............................................................................779 A.1 Instructions ..................................................................................................................... 779 A.2 Instruction Codes ............................................................................................................ 790 A.3 Operation Code Map ....................................................................................................... 800 A.4 Number of Execution States ............................................................................................ 804 A.5 Bus Status During Instruction Execution ......................................................................... 814 A.6 Change of Condition Codes............................................................................................. 823 Appendix B Internal I/O Registers..................................................................829 B.1 Addresses ........................................................................................................................ 829 B.2 Function List ................................................................................................................... 836 Appendix C Pin Circuit Diagrams ..................................................................953 C.1 Pin Circuit Diagrams ....................................................................................................... 953 Appendix D Port States in the Difference Processing States ...........................967 D.1 Pin Circuit Diagrams....................................................................................................... 967 Appendix E Usage Notes................................................................................969 E.1 Power Supply Rise and Fall Order ................................................................................... 969 E.2 Pin Handling When the High-Speed Switching Circuit ......... for Four-Head Special Playback Is Not Used ............................................................... 970 E.3 Sample External Circuits ................................................................................................. 971 Appendix F List of Product Codes..................................................................973 Appendix G External Dimensions ..................................................................975 Rev. 0.1, 11/98, page xvii of xviii Rev. 0.1, 11/98, page xviii of xviii Section 1 Overview 1.1 Overview The H8S/2194 Series comprise microcomputers (MCUs) built around the H8S/2000 CPU, employing Hitachi's proprietary architecture, and equipped with supporting modules on-chip. The H8S/2000 has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300 and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300, H8/300L, or H8/300H Series. The H8S/2194 Series is incorporated with digital servo circuit, ROM, RAM, seven types of timers, three types of PWM, two types of serial communication interface, I2C bus interface, A/D converter, and I/O port as on-chip supporting modules. The on-chip ROM is either flash memory (F-ZTAT*) or mask ROM, with a capacity of 128, 112, 96, or 80 kbytes. ROM is connected to the CPU via a 16-bit data bus, enabling both byte and word data to be accessed in one state. Instruction fetching has been speeded up, and processing speed increased. The features of the H8S/2194 Series are shown in table 1.1. Note: * F-ZTAT is a trademark of Hitachi, Ltd. Rev. 0.1, 11/98, page 1 of 975 Table 1.1 Features of the H8S/2194 Series (1) Item Specifications CPU * General-register architecture * Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) * High-speed operation suitable for real-time control * Maximum operating frequency: 10 MHz/4 to 5.5 V Operable by 32 kHz subclock * High-speed arithmetic operations 8/16/32-bit register-register add/subtract: 100 ns (10 MHz operation) 16 x 16-bit register-register multiply: 2000 ns (10 MHz operation) 32 / 16-bit register-register divide: 2000 ns (10 MHz operation) * Instruction set suitable for high-speed operation * Sixty-five basic instructions * 8/16/32-bit transfer/arithmetic and logic instructions * Unsigned/signed multiply and divide instructions * Powerful bit-manipulation instructions * CPU operating modes * Advanced mode: 16-Mbyte address space * Seven types of timer are incorporated Timer (1) Timer A * 8-bit interval timer * Clock source can be selected among 8 types of internal clock of which frequencies are divided from the system clock () and subclock (SUB) * Functions as clock time base by subclock input (2) Timer B * Functions as 8-bit interval timer or reload timer * Clock source can be selected among 7 types of internal clock or external event input (3) Timer J * Functions as two 8-bit down counters or one 16-bit down counter (reload timer/event counter timer/timer output, etc., 5 types of operation modes) * Remote controlled transmit function * Take up/Supply Reel Pulse Frequency division Rev. 0.1, 11/98, page 2 of 975 Table 1.1 Features of the H8S/2194 Series (2) Item Specifications Timer (4) Timer L 8-bit up/down counter Clock source can be selected among 2 types of internal clock, CFG frequency division signal, and PB and REC-CTL (control pulse) Compare-match clearing function/auto reload function (5) Timer R Three reload timers Mode discrimination Reel control Capstan motor acceleration/deceleration detection function Slow tracking mono-multi (6) Timer X1 16-bit free-running counter Clock source can be selected among 3 types of internal clock and DVCFG Two output compare outputs Four input capture inputs (7) Watchdog timer Functions as watchdog timer or 8-bit interval timer Generates reset signal or NMI at overflow Prescaler unit PWM * Divides system clock frequency and generates frequency division clock for supporting module functions * Divides subclock frequency and generates input clock for Timer A (clock time base) * Generates 8-bit PWM frequency and duty period * 8-bit input capture at external signal edge * Frequency division clock output enabled * Three types of PWM are incorporated (1) 14-bit PWM: Pulse resolution type x 1 channel (2) 8-bit PWM: Duty control type x 4 channels (3) 12-bit PWM: Pulse pitch control type x 2 channels Rev. 0.1, 11/98, page 3 of 975 Table 1.1 Features of the H8S/2194 Series (3) Item Specifications Serial communication interface (SCI) * Two types of serial communication interface is incorporated (1) SCI1 * Asynchronous mode or synchronous mode selectable * Desired bit rate selectable with built-in baud rate generator * Multiprocessor communication function (2) SCI2 * 32-byte data automatically transferrable * Transfer clock selectable among seven types of internal/external clock * Conforms to Phillips I C bus interface standard * Single master mode/slave mode * Arbitration lost condition can be identified * Supports two slave addresses * Resolution: 10 bits * Input: 12 channels * High-speed conversion: 13.4 s minimum conversion time (10 MHz operation) * Sample-and-hold function * A/D conversion can be activated by software or external trigger Address trap controller * Interrupt occurs when the preset address is found during bus cycle * To-be-trapped addresses can be individually set at three different locations I/O port * 60 input/output pins * 8 input-only pins * Can be switched for each supporting module * Digital servo circuits on-chip * Input and output circuits * Error detection circuit * Phase and gain compensation * On-chip sync signal detection circuit * Can separately detect horizontal and vertical sync signals * Noise detection function 2 I C bus interface A/D converter Servo circuit Sync signal 2 Rev. 0.1, 11/98, page 4 of 975 Table 1.1 Features of the H8S/2194 Series (4) Item Specifications Memory * Flash memory or mask ROM * High-speed static RAM Power-down state * * Sleep mode * Module stop mode * Standby mode * Subclock operation Subactive mode, watch mode, subsleep mode Interrupt controller * Clock pulse generator Packages Medium-speed mode Seven external interrupt pins (10,, ,54 to ,54) * 43 internal interrupt sources * Three priority levels settable * Two types of clock pulse generator on-chip * System clock pulse generator: 8 to 10 MHz * Subclock pulse generator: 32.768 kHz * 112-pin plastic QFP (FP-112) Product lineup Rev. 0.1, 11/98, page 5 of 975 1.2 Internal Block Diagram Port 3 Port 4 Port 5 External address bus External data bus NMI RES FWE MD0 VCC VCC VCC VCC VSS VSS VSS VSS VSS X1 X2 OSC1 OSC2 Subclock pulse generator System clock pulse generator External data bus External address bus P53/TRIG P52/TMBI P51 P50/ADTRG Port 6 AN8 AN9 ANA ANB P47 P46/FTOB P45/FTOA P44/FTID P43/FTIC P42/FTIB P41/FTIA P40/PWM14 P67/RP7 P66/RP6 P65/RP5 P64/RP4 P63/RP3 P62/RP2 P61/RP1 P60/RP0 Port 7@ P07/AN7 P06/AN6 P05/AN5 P04/AN4 P03/AN3 P02/AN2 P01/AN1 P00/AN0 ROM P77/PPG7 P76/PPG6 P75/PPG5 P74/PPG4 P73/PPG3 P72/PPG2 P71/PPG1 P70/PPG0 Internal address bus Bus controller Port 1 RAM Interrupt controller Address trap controller 8-bit PWM Prescaler unit Watchdog timer Timer A Port 0 P17/TMOW P16/IC P15/IRQ5 P14/IRQ4 P13/IRQ3 P12/IRQ2 P11/IRQ1 P10/IRQ0 H8S/2000 CPU P37/TMO P36/BUZZ P35/PWM3 P34/PWM2 P33/PWM1 P32/PWM0 P31/STRB P30/CS Internal data bus Timer L Timer B SCI1 analog port P27/SCK2 P26/SO2 P25/SI2 P24/SCL P23/SDA P22/SCK1 P21/SO1 P20/SI1 Port 2 An internal block diagram of the H8S/2194 Series is shown in figure 1.1. SCI2 Timer J I 2 C bus interface Timer R A/D converter Timer X1 Servo circuit 14-bit PWM Csync Servo pins (CTL input/output amplifier, three-level output, etc.) H.Amp SW/PS1 C.Rotary/PS0 COMP/PS2 DPG/PS3 EXCTL/PS4 DFG DRMPWM CAPPWM AUDIO FF VIDEO FF Vpulse CLT(+) CLT(-) CTLBias CTLAmp(o) CTLSMT(i) CTLFB CTL REF CFG SVCC SVSS Sync signal detection Port 8 AVCC AVSS P87 P86 P85 P84 P83/SV2 P82/SV1 P81/EXCAP P80/EXTTRG Figure 1.1 Internal Block Diagram of H8S/2194 Series Rev. 0.1, 11/98, page 6 of 975 1.3 Pin Arrangement and Functions 1.3.1 Pin Arrangement 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 VSS P72/PPG2 VCC P71/PPG1 P70/PPG0 P67/RP7 P66/RP6 P65/RP5 P64/RP4 P63/RP3 P62/RP2 P61/RP1 P60/RP0 MD0 VCC OSC2 VSS OSC1 RES X1 X2 NMI FWE P17/TMOW P16/IC P15/IRQ5 P14/IRQ4 P13/IRQ3 The pin arrangement of the H8S/2194 Series is shown in figure 1.2. 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 FP-112 (Top view) P12/IRQ2 P11/IRQ1 P10/IRQ0 P27/CSK2 P26/SO2 P25/SI2 P24/SCL P23/SDA P22/SCK1 P21/SO1 P20/SI1 VCC P37/TMO VSS P36/BUZZ P35/PWM3 P34/PWM2 P33/PWM1 P32/PWM0 P31/STRB P30/CS P47 P46/FTOB P45/FTOA P44/FTID P43/FTIC P42/FTIB P41/FTIA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Vpulse VSS CTLREF 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 CTL(+) SVSS CTL(-) CTLBias CTLFB CTLAmp(o) CTLSMT(i) CFG SVCC AVCC P00/AN0 P01/AN1 P02/AN2 P03/AN3 P04/AN4 P05/AN5 P06/AN6 P07/AN7 AN8 AN9 ANA ANB AVSS P50/ADTRG P51 P52/TMBI P53/TRIG P40/PWM14 P73/PPG3 P74/PPG4 P75/PPG5 P76/PPG6 P77/PPG7 P80/EXTTRG P81/EXCAP P82/SV1 P83/SV2 P84 P85 P86 P87 Csync AUDIO FF VIDEO FF CAP PWM DRM PWM C.Rotary/PS0 H.Amp sw/PS1 COMP/PS2 EXCTL/PS4 DPG/PS3 DFG VCC Figure 1.2 Pin Arrangement of H8S/2194 Series Rev. 0.1, 11/98, page 7 of 975 1.3.2 Pin Functions Table 1.2 summarizes the functions of the H8S/2194 Series pins. Table 1.2 Pin Functions (1) Type Symbol Pin No. I/O Name and Function Power supply Vcc 45, 70, 82, 109 Input Power supply: All Vcc pins should be connected to the system power supply (+5V) Vss 43, 68, 84, 111 Input Ground: All Vcc pins should be connected to the system power supply (0V) SVcc 9 Input Servo power supply: SVcc pin should be connected to the servo analog power supply (+5V) SVss 2 Input Servo ground: SVss pin should be connected to the servo analog power supply (0V) AVcc 10 Input Analog power supply: Power supply pin for A/D converter. It should be connected to the system power supply (+5V) when the A/D converter is not used AVss 23 Input Analog ground: Ground pin for A/D converter. It should be connected to the system power supply (0V) OSC1 67 Input Connected to a crystal oscillator. It can also input an external clock. See section 9, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator and external clock input OSC2 69 Output X1 65 Input X2 64 Output MD0 71 Input Clock Operating mode control Rev. 0.1, 11/98, page 8 of 975 Connected to a 32.768 kHz crystal oscillator. See section 9, Clock Pulse Generator, for typical connection diagrams Mode pins: These pins set the operating mode. These pins should not be changed while the MCU is in operation Table 1.2 Pin Functions (2) Type Symbol Pin No. I/O Name and Function System control 5(6 66 Input Reset input: When this pin is driven low, the chip is reset FWE 62 Input Flash memory enable: Enables/disables flash memory programming. This pin is available only with MCU with flash memory on-chip. For mask ROM type, do not connect anything to this pin ,54 54 Input External interrupt request 0: External interrupt input pin for which rising edge sense, falling edge sense or both edges sense are selectable ,54 Input External interrupt requests 1 to 5: External interrupt input pins for which rising or falling edge sense are selectable ,54 55 56 57 58 59 10, 63 Input Nonmaskable interrupt: Nonmaskable interrupt input pin for which rising edge sense, falling edge sense or both edges sense are selectable ,& 60 Input Input capture input: Input capture input pin for prescaler unit TMOW 61 Output Frequency division clock output: Output pin for clock of which frequency is divided by prescaler TMBI 26 Input Timer B event input: Input pin for events to be input to Timer B counter ,54 55 56 Input ,54 Timer J event input: Input pin for events to be input to Timer J RDT-1or RDT-2 counter TMO 44 Output Timer J timer output: Output pin for toggle at underflow of RDT-1 of Timer J, or remote controlled transmit data BUZZ 42 Output Timer J buzzer output: Output pin for toggle which is selectable among fixed frequency, 1Hz frequency divided from subclock (32 kHz), and frequency division CTL signal Interrupts ,54 ,54 ,54 Prescaler unit Timers Rev. 0.1, 11/98, page 9 of 975 Table 1.2 Pin Functions (3) Type Symbol Pin No. I/O Name and Function Timers ,54 57 Input Timer R input capture: Input pin for input capture of Timer R TMRU-1 or TMRU-2 FTOA FTOB 33 34 Output Timer X1 output compare A and B output: Output pin for output compare A and B of Timer X1 FTIA FTIB FTIC FTID 29 30 31 32 Input Timer X1 input capture A, B, C and D input: Input pin for input capture A, B, C and D of Timer X1 PWM0 PWM1 PWM2 PWM3 38 39 40 41 Output 8-bit PWM square waveform output: Output pin for waveform generated by 8-bit PWM 0, 1, 2 and 3 PWM14 28 Output 14-bit PWM square waveform output: Output pin for waveform generated by 14-bit PWM SCK1 SCK2 48 53 Input /output SCI clock input/output: Clock input pins for SCI 1 and 2 SI1 SI2 46 51 Input SCI receive data input: Receive data input pins for SCI 1 and 2 SO1 SO2 47 52 Output SCI transmit data output: Transmit data output pins for SCI 1 and 2 STRB 37 Output SCI2 strobe output: This pin outputs strobe pulse for each byte transmit by SCI2 &6 36 Input SCI2 chip select input: This pin controls the transfer start of SCI2 SCL 50 Input /output I C bus interface clock input/output: 2 Clock input/output pin for I C bus interface SDA 49 Input /output I C bus interface data input/output: 2 Data input/output pin for I C bus interface PWM Serial communication interface (SCI) 2 I C bus interface Rev. 0.1, 11/98, page 10 of 975 2 2 Table 1.2 Pin Functions (4) Type Symbol A/D converter Servo circuits Pin No. I/O Name and Function AN7 to AN0 18 to 11 Input Analog input channels 7 to 0: Analog data input pins. A/D conversion is started by a software triggering AN8 AN9 ANA ANB 19 20 21 22 Input Analog input channels 8, 9, A and B: Analog data input pins. A/D conversion is started by an external, hardware, or software triggering $'75* 24 Input A/D conversion external trigger input: Pin for input of an external trigger to start A/D conversion AUDIO FF 99 Output Audio FF: Output pin for audio head switching signal VIDEO FF 100 Output Video FF: Output pin for video head switching signal CAPPWM 101 Output Capstan mix: 12-bit PWM output pin giving result of capstan speed error and phase error after filtering DRMPWM 102 Output Drum mix: 12-bit PWM output pin giving result of drum speed error and phase error after filtering Vpulse 110 Output Additional V pulse: Three-level output pin for additional V signal synchronized to the Video FF signal C.Rotary /PS0 103 Output, input/ output Color rotary signal: Output pin for color signal processing control signal in four-head special-effects playback H.AmpSW/P 104 S1 Output, input/ output Head-amp switch: Output pin for preamplifier output select signal in four-head special-effects playback. This pin can also be used as a general port when not used COMP /PS2 105 Input, input/ output Compare input: Input pin for signal giving the result of preamplifier output comparison in four-head special-effects playback. This pin can also be used as a general port when not used CTL (+) CTL (-) 1 3 Input /output CTL head (+) and (-) pins: I/O pins for CTL signals CTL Bias 4 Input CTL primary amp bias supply: Bias supply pin for CTL primary amp Rev. 0.1, 11/98, page 11 of 975 Table 1.2 Pin Functions (5) Type Symbol Pin No. I/O Name and Function Servo circuits CTL Amp (o) 6 Output CTL amp output: Output pin for CTL amp CTL SMT (l) 7 Input CTL Schmitt amp input: Input pin for CTL Schmitt amp CTLFB 5 Input CLT feedback input: Input pin for CTL amp high-range characteristics control CTLREF 112 Output CTL amp reference voltage output: Output pin for 1/2Vcc (SV) CFG 8 Input Capstan FG input: Schmitt comparator input pin for CFG signal DFG 108 Input Drum FG input: Schmitt input pin for DFG signal DPG/PS3 107 Input, input/ output Drum PG input: Schmitt input pin for DPG signal. This pin can also be used as a general port when not used EXCTL /PS4 106 Input, input/ output External CTL input: Input pin for external CTL signal. This pin can also be used as a general port when not used Csync 98 Input Mixed sync signal input: Input pin for mixed sync signal EXCAP 91 Input Capstan external sync signal input: Signal input pin for external synchronization of capstan phase control EXTTRG 90 Input External trigger signal input: Signal input pin for synchronization with reference signal generator SV1 92 Output Servo monitor output pin 1: Output pin for servo module internal signal SV2 93 Output Servo monitor output pin 2: Output pin for servo module internal signal PPG7 to PPG0 89 to 85, Output 83, 81, 80 Rev. 0.1, 11/98, page 12 of 975 PPG: Output pin for HSW timing generator. To be used when head switching is required as well as Audio FF and Video FF Table 1.2 Pin Functions (6) Type Symbol Pin No. I/O Name and Function I/O port P07 to P00 11 to 18 Input Port 0: 8-bit input pins P17 to P10 61 to 54 Input /output Port 1: 8-bit I/O pins P27 to P20 53 to 46 Input /output Port 2: 8-bit I/O pins P37 to P30 44, 42 to 36 Input /output Port 3: 8-bit I/O pins P47 to P40 35 to 28 Input /output Port 4: 8-bit I/O pins P53 to P50 27 to 24 Input /output Port 5: 4-bit I/O pins P67 to P60 79 to 72 Input /output Port 6: 8-bit I/O pins P77 to P70 89 to 85, Input 83, 81, 80 /output Port 7: 8-bit I/O pins P87 to P80 97 to 90 Input /output Port 8: 8-bit I/O pins RP7 to RP0 79 to 72 Output Realtime output port: 8-bit realtime output pins TRIG 27 Input Realtime output port trigger input: Input pin for realtime output port trigger Rev. 0.1, 11/98, page 13 of 975 Rev. 0.1, 11/98, page 14 of 975 Section 2 CPU 2.1 Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control. 2.1.1 Features The H8S/2000 CPU has the following features. * Upward-compatible with H8/300 and H8/300H CPUs Can execute H8/300 and H8/300H object programs * General-register architecture Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) * Sixty-five basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 16-Mbyte address space Program: 16 Mbytes Data: 16 Mbytes (4 Gbytes architecturally) * High-speed operation All frequently-used instructions execute in one or two states Maximum clock rate: 10 MHz 8/16/32-bit register-register add/subtract: 100 ns 8 x 8-bit register-register multiply: 1200 ns Rev. 0.1, 11/98, page 15 of 975 16 / 8-bit register-register divide: 1200 ns 16 x 16-bit register-register multiply: 2000 ns 32 / 16-bit register-register divide: 2000 ns * Two CPU operating modes Normal mode*/Advanced mode * Power-down state Transition to power-down state by SLEEP instruction CPU clock speed selection Note: * Normal mode is not available for this LSI. 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are shown below. * Register configuration The MAC register is supported only by the H8S/2600 CPU. * Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU. * Number of execution states The number of execution states of the MULXU and MULXS instructions differ as follows. Number of Execution States Instruction Mnemonic H8S/2600 H8S/2000 MULXU MULXU.B Rs, Rd 3 12 MULXU.W Rs, Erd 4 20 MULXS.B Rs, Rd 4 13 MULXS.W Rs, Erd 5 21 MULXS There are also differences in the address space, EXR register functions, power-down state, etc., depending on the product. Rev. 0.1, 11/98, page 16 of 975 2.1.3 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. * More general registers and control registers Eight 16-bit extended registers, and one 8-bit control register, have been added. * Expanded address space Normal mode supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. * Enhanced addressing mode The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Signed multiply and divide instructions have been added. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast. 2.1.4 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements. * Additional control register One 8-bit control register has been added. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast. Rev. 0.1, 11/98, page 17 of 975 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space (architecturally the maximum total address space is 4 Gbytes, with a maximum of 16 Mbytes for the program area and a maximum of 4 Gbytes for the data area). The mode is selected by the mode pins of the microcontroller. Normal mode* Maximum 64 kbytes for program and data areas combined Advanced mode Maximum 16 Mbytes for program and data areas combined CPU operating mode Note: * Normal mode is not available for this LSI. Figure 2.1 CPU Operating Modes (1) Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU. (a) Address Space A maximum address space of 64 kbytes can be accessed. (b) Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. If the general register is referenced in the register indirect addressing mode with predecrement (@-Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (En) will be affected. (c) Instruction Set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. Rev. 0.1, 11/98, page 18 of 975 (d) Exception Vector Table and Memory Indirect Branch Addresses In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The configuration of the exception vector table in normal mode is shown in figure 2.2. For details of the exception vector table, see section 5, Exception Handling. H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Reset exception vector (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Figure 2.2 Exception Vector Table (Normal Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table. Rev. 0.1, 11/98, page 19 of 975 (e) Stack Structure When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.3. The extended control register (EXR) is not pushed onto the stack. For details, see section 5, Exception Handling. SP PC (16 bits) SP CCR CCR* PC (16 bits) (a) Subroutine Branch (b) Exception Handling Note: * Ignored when returning. Figure 2.3 Stack Structure in Normal Mode (2) Advanced Mode (a) Address Space Linear access is provided to a 16-Mbyte maximum address space (architecturally a maximum 16-Mbyte program area and a maximum 4-Gbyte data area, with a maximum of 4 Gbytes for program and data areas combined). (b) Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. (c) Instruction Set All instructions and addressing modes can be used. Rev. 0.1, 11/98, page 20 of 975 (d) Exception Vector Table and Memory Indirect Branch Addresses In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.4). For details of the exception vector table, see section 5, Exception Handling. H'00000000 Reserved Reset exception vector H'00000003 H'00000004 Reserved H'00000007 H'00000008 Exception vector table H'0000000B (Reserved for system use) H'0000000C H'00000010 Reserved Exception vector 1 Figure 2.4 Exception Vector Table (Advanced Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also the exception vector table. Rev. 0.1, 11/98, page 21 of 975 (e) Stack Structure In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.5. The extended control register (EXR) is not pushed onto the stack. For details, see section 5, Exception Handling. SP Reserved CCR SP PC (24 bits) PC (24 bits) (a) Subroutine Branch (b) Exception Handling Figure 2.5 Stack Structure in Advanced Mode Rev. 0.1, 11/98, page 22 of 975 2.3 Address Space Figure 2.6 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. H'0000 H'00000000 H'FFFF Program area H'00FFFFFF Data area Cannot be used with this LSI H'FFFFFFFF (a) Normal mode* (b) Advanced mode Note: * Normal mode is not available for this LSI. Figure 2.6 Memory Map Rev. 0.1, 11/98, page 23 of 975 2.4 Register Configuration 2.4.1 Overview The CPU has the internal registers shown in figure 2.7. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) 15 0 7 0 7 0 ER0 E0 R0H R0L ER1 E1 R1H R1L ER2 E2 R2H R2L ER3 E3 R3H R3L ER4 E4 R4H R4L ER5 E5 R5H R5L ER6 E6 R6H R6L ER7 (SP) E7 R7H R7L Control Registers (CR) 23 0 PC 7 6 5 4 3 2 1 0 EXR* T - - - - I2 I1 I0 7 6 5 4 3 2 1 0 CCR I UI H U N Z V C [Legend] : SP : PC EXR : : T I2 to I0 : CCR : : I : UI Stack pointer Program counter Extended control register Trace bit Interrupt mask bits Condition-code register Interrupt mask bit User bit or interrupt mask bit H U N Z V C Note: * Does not affect operation in this LSI. Figure 2.7 CPU Registers Rev. 0.1, 11/98, page 24 of 975 : : : : : : Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag 2.4.2 General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8-bit registers. Figure 2.8 illustrates the usage of the general registers. The usage of each register can be selected independently. Address registers 32-bit registers 16-bit registers 8-bit registers E registers (extended registers) (E0 to E7) RH registers (R0H to R7H) ER registers (ER0 to ER7) R registers (R0 to R7) RL registers (R0L to R7L) Figure 2.8 Usage of General Registers General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.9 shows the stack. Rev. 0.1, 11/98, page 25 of 975 Free area SP (ER7) Stack area Figure 2.9 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), and 8-bit condition-code register (CCR). (1) Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.) (2) Extended Control Register (EXR) An 8-bit register. In this LSI, this register does not affect operation. Bit 7: Trace Bit (T) This bit is reserved. In this LSI, this bit does not affect operation. Bits 6 to 3: Reserved These bits are reserved. They are always read as 1. Bits 2 to 0: Interrupt Mask Bits (I2 to I0) These bits are reserved. In this LSI, these bits do not affect operation. (3) Condition: Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7: Interrupt Mask Bit (I) Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exception-handling sequence. For details, see section 6, Interrupt Controller. Rev. 0.1, 11/98, page 26 of 975 Bit 6: User Bit or Interrupt Mask Bit (UI) Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask bit. For details, see section 6, Interrupt Controller. Bit 5: Half-Carry Flag (H) When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. Bit 4: User Bit (U) Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3: Negative Flag (N) Stores the value of the most significant bit (sign bit) of data. Bit 2: Zero Flag (Z) Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Bit 1: Overflow Flag (V) Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise. Bit 0: Carry Flag (C) Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: (a) Add instructions, to indicate a carry (b) Subtract instructions, to indicate a borrow (c) Shift and rotate instructions, to store the carry The carry flag is also used as a bit accumulator by bit-manipulation instructions. Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, see section 29, Appendix A.1, List of Instructions. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. 2.4.4 Initial Register Values Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset. Rev. 0.1, 11/98, page 27 of 975 2.5 Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4bit BCD data. 2.5.1 General Register Data Formats Figure 2.10 shows the data formats in general registers. Data type General Register Data Format 1-bit data RnH 7 6 5 4 3 2 1 0 1-bit data RnL Don't care 4-bit BCD data RnH 4-bit BCD data RnL 7 0 Don't care 7 7 4 3 7 6 5 4 3 2 1 0 0 Upper digit Lower digit Don't care 7 RnH 7 4 3 0 Upper digit Lower digit Don't care Byte data 0 0 Don't care MSB Byte data LSB RnL 7 0 Don't care MSB Figure 2.10 General Register Data Formats (1) Rev. 0.1, 11/98, page 28 of 975 LSB Data Type General Register Word data Rn Data format 15 0 MSB Word data LSB En 15 0 MSB Longword data LSB ERn 31 16 15 MSB En 0 Rn LSB [Legend] ERn : General register ER En : General register E Rn : General register R RnH : General register RH RnL : General register RL MSB : Most significant bit LSB : Least significant bit Figure 2.10 General Register Data Formats (2) Rev. 0.1, 11/98, page 29 of 975 2.5.2 Memory Data Formats Figure 2.11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. Data Type Data Format Address 7 1-bit data Address L Byte data Address L MSB Word data Address 2M MSB 7 0 6 5 4 3 Address 2M+1 Longword data 2 1 0 LSB LSB Address 2N MSB Address 2N+1 Address 2N+2 Address 2N+3 LSB Figure 2.11 Memory Data Formats When ER7 (SP) is used as an address register to access the stack, the operand size should be word size or longword size. Rev. 0.1, 11/98, page 30 of 975 2.6 Instruction Set 2.6.1 Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Data transfer MOV *1 Arithmetic *1 Size Types BWL 5 POP , PUSH WL LDM, STM L MOVFPE, MOVTPE B ADD, SUB, CMP, NEG BWL ADDX, SUBX, DAA, DAS B INC, DEC BWL ADDS, SUBS L MULXU, DIVXU, MULXS, DIVXS BW EXTU, EXTS WL 19 TAS B Logic operations AND, OR, XOR, NOT BWL 4 Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BWL 8 Bit manipulation RSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR B 14 Branch Bcc , JMP, BSR, JSR, RTS 5 System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 9 Block data transfer EEPMOV 1 *2 Total: 65 types Notes: B: byte size; W: word size; L: longword size. 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. Bcc is the general name for conditional branch instructions. Rev. 0.1, 11/98, page 31 of 975 2.6.2 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2000 CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes Logic operation Arithmetic operations @@aa:8 -- BWL -- -- @(d:16, PC) BWL -- -- @(d:8, PC) @-ERn/@ERn+ BWL -- -- @aa:32 @(d:32, ERn) BWL -- -- @aa:24 @(d:16, ERn) BWL -- -- @aa:16 @ERn MOV POP, PUSH LDM, STM MOVFPE, MOVTPE* ADD, CMP SUB ADDX, SUBX ADDS, SUBS INC, DEC DAA, DAS MULXU, DIVXU MULXS, DIVXS NEG EXTU, EXTS TAS AND, OR, XOR NOT @aa:8 Rn BWL -- -- Instruction Shift Bit manipulation Bcc, BSR Branch JMP, JSR RTS TRAPA RTE SLEEP LDC STC ANDC, ORC, XORC NOP Block data transfer System control #xx Data transfer Function Addressing Modes B -- -- BWL -- -- -- -- -- BWL -- -- -- -- -- -- -- -- -- -- -- -- WL L -- -- -- -- -- -- -- B -- -- -- -- -- -- BWL WL B -- -- -- BWL BWL B L BWL B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BW -- -- -- -- -- -- -- -- -- -- -- -- -- BW -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BWL WL -- -- -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BWL BWL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- BWL BWL B -- -- -- -- -- -- B B -- -- B -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- W W -- -- B -- -- -- -- -- -- -- -- -- -- B -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BW [Legend] B: Byte W: Work L: Longword Note: * Cannot be used in this LSI. Rev. 0.1, 11/98, page 32 of 975 2.6.3 Table of Instructions Classified by Function Table 2.3 to 2.10 summarize the instructions in each functional category. The notation used in table 2.3 is defined below. Operation Notation Rd General register (destination)* Rs General register (source)* Rn General register* ERn General register (32-bit register) (EAd) Destination operand (EAs) Source operand EXR Extended control register CCR Condition-code register N N (negative) flag in CCR Z Z (zero) flag in CCR V V (overflow) flag in CCR C C (carry) flag in CCR PC Program counter SP Stack pointer #IMM Immediate data Disp Displacement + Addition - Subtraction x Multiplication / Division Logical AND Logical OR * Logical exclusive OR Move NOT (logical complement) :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Rev. 0.1, 11/98, page 33 of 975 Table 2.3 Data Transfer Instructions Instruction Size* Function MOV B/W/L (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register MOVFPE B Cannot be used in this LSI MOVTPE B Cannot be used in this LSI POP W/L @SP+ Rn Pops a general register from the stack POP.W Rn is identical to MOV.W @SP+, Rn POP.L ERn is identical to MOV.L @SP+, ERn PUSH W/L Rn @-SP Pushes a general register onto the stack PUSH.W Rn is identical to MOV.W Rn, @-SP PUSH.L ERn is identical to MOV.L ERn, @-SP LDM L @SP+ Rn (register list) Pops two or more general registers from the stack STM L Rn (register list) @-SP Pushes two or more general registers onto the stack Note: * Size refers to the operand size. B: Byte W: Word L: Longword Rev. 0.1, 11/98, page 34 of 975 Table 2.4 Arithmetic Instructions (1) Instruction Size* Function ADD SUB B/W/L Rd Rs Rd, Rd #IMM Rd ADDX SUBX B INC DEC B/W/L ADDS SUBS B DAA DAS B/W MULXU B/W Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction) Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only) Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register Rd decimal adjust Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x16 bits 32 bits MULXS B/W Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x16 bits 32 bits DIVXU B/W Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits x 8-bit quotient and 8-bit remainder or 32 bits / 16 bits x 16-bit quotient and 16-bit remainder Note: * Size refers to the operand size. B: Byte W: Word L: Longword Rev. 0.1, 11/98, page 35 of 975 Table 2.4 Arithmetic Instructions (2) Instruction Size* Function DIVXS B/W Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder CMP B/W/L Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result NEG B/W/L 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register EXTU W/L Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left EXTS W/L Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit TAS B @ERd - 0, 1 (<bit 7> of @ERd) Tests memory contents, and sets the most significant bit (bit 7) to 1 Note: * Size refers to the operand size. B: Byte W: Word L: Longword Rev. 0.1, 11/98, page 36 of 975 Table 2.5 Logic Instructions Instruction Size* Function AND B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data OR B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data XOR B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data NOT B/W/L ~ Rd Rd Takes the one's complement (logical complement) of general register contents Note: * Size refers to the operand size. B: Byte W: Word L: Longword Table 2.6 Shift Instructions Instruction Size* SHAL SHAR B/W/L SHLL SHLR B/W/L ROTL ROTR B/W/L ROTXL ROTXR B/W/L Note: Function Rd (shift) Rd Performs an arithmetic shift on general register contents A 1-bit or 2-bit shift is possible Rd (shift) Rd Performs a logical shift on general register contents A 1-bit or 2-bit shift is possible Rd (rotate) Rd Rotates general register contents 1-bit or 2-bit rotation is possible Rd (rotate) Rd Rotates general register contents through the carry flag 1-bit or 2-bit rotation is possible * Size refers to the operand size. B: Byte W: Word L: Longword Rev. 0.1, 11/98, page 37 of 975 Table 2.7 Bit Manipulation Instructions (1) Instruction Size* Function BSET B 1 (<bit-No.> of <EAd>) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register BCLR B 0 (<bit-No.> of <EAd>) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register BNOT B ~ (<bit-No.> of <EAd>) (<bit-No.> of <EAd>) Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register BTST B ~ (<bit-No.> of <EAd>) Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register BAND B C (<bit-No.> of <EAd>) C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag BIAND B C [~(<bit-No.> of <EAd>)] C ANDs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag The bit number is specified by 3-bit immediate data BOR B C (<bit-No.> of <EAd>) C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag BIOR B C [~(<bit-No.> of <EAd>)] C ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag The bit number is specified by 3-bit immediate data Note: * Size refers to the operand size. B: Byte Rev. 0.1, 11/98, page 38 of 975 Table 2.7 Bit Manipulation Instructions (2) Instruction Size* Function BOXR B C (<bit-No.> of <EAd>) C Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag BIXOR B C [~ (<bit-No.> of <EAd>)] C Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag The bit number is specified by 3-bit immediate data BLD B (<bit-No.> of <EAd>) C Transfers a specified bit in a general register or memory operand to the carry flag BILD B ~ (<bit-No.> of <EAd>) C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag The bit number is specified by 3-bit immediate data BST B C (<bit-No.> of <EAd>) Transfers the carry flag value to a specified bit in a general register or memory operand BIST B ~ C (<bit-No.> of <EAd>) Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand The bit number is specified by 3-bit immediate data Note: * Size refers to the operand size. B: Byte Table 2.8 Branch Instructions Instruction Size* Function Bcc JMP BSR JSR Branches to a specified address if a specified condition is true The branching conditions are listed below Branches unconditionally to a specified address Branches to a subroutine at a specified address Branches to a subroutine at a specified address RTS Returns from a subroutine Rev. 0.1, 11/98, page 39 of 975 Table 2.9 System Control Instructions Instruction Size* Function TRAPA Starts trap-instruction exception handling RTE Returns from an exception-handling routine SLEEP Causes a transition to a power-down state LDC B/W (EAs) CCR, (EAs) EXR Moves contents of a general register or memory or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid STC B/W CCR (EAd), EXR (EAd) Transfers CCR or EXR contents to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid ANDC B CCR #IMM CCR, EXR #IMM EXR Logically ANDs the CCR or EXR contents with immediate data ORC B CCR #IMM CCR, EXR #IMM EXR Logically ORs the CCR or EXR contents with immediate data XORC B CCR #IMM CCR, EXR #IMM EXR Logically exclusive-ORs the CCR or EXR contents with immediate data NOP PC + 2 PC Only increments the program counter Note: * Size refers to the operand size. B: Byte W: Word Rev. 0.1, 11/98, page 40 of 975 Table 2.10 Block Data Transfer Instructions Instruction Size* Function EEPMOV.B if R4L 0 then Repeat @ER5+@er6+ R4L-1R4L Until R4L = 0 else next; EEPMOV.W if R4 0 then Repeat @ER5+@er6+ R4-1R4 Until R4 = 0 else next; Transfers a data block according to parameters set in general registers R4L or R4, ER5, and ER6 R4L or R4: size of block (bytes) ER5: starting source address ER6: starting destination address Execution of the next instruction begins as soon as the transfer is completed Rev. 0.1, 11/98, page 41 of 975 2.6.4 Basic Instruction Formats The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.12 shows examples of instruction formats. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rm rn ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op rn rm MOV.B@(d:16, Rn), Rm, etc. EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc. Figure 2.12 Instruction Formats (Examples) (1) Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. (2) Register Field Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. (3) Effective Address Extension Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. (4) Condition Field Specifies the branching condition of Bcc instructions. Rev. 0.1, 11/98, page 42 of 975 2.6.5 Notes on Use of Bit-Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, carry out bit manipulation, then write back the byte of data. Caution is therefore required when using these instructions on a register containing write-only bits, or a port. The BCLR instruction can be used to clear internal I/O register flags to 0. In this case, the relevant flag need not be read beforehand if it is clear that it has been set to 1 in an interrupt handling routine, etc. 2.7 Addressing Modes and Effective Address Calculation 2.7.1 Addressing Mode The CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except programcounter relative and memory indirect. Bit-manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.11 Addressing Modes No. Addressing Mode Symbol 1 Register direct Rn 2 Register indirect @ERn 3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn) 4 Register indirect with post-increment @ERn+ @-ERn Register indirect with pre-decrement 5 Absolute address @aa:8/#@aa:16/@aa:24/@aa:32 6 Immediate #xx:8/#xx:16/#xx:32 7 Program-counter relative @(d:8,PC)/@(d:16,PC) 8 Memory indirect @@aa:8 Rev. 0.1, 11/98, page 43 of 975 (1) Register Direct-Rn The register field of the instruction code specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32bit registers. (2) Register Indirect-@Ern The register field of the instruction code specifies an address register (ERn) which contains the address of the operand in memory. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). (3) Register Indirect with Displacement-@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. (4) Register Indirect with Post-Increment or Pre-Decrement-@ERn+ or @-ERn (a) Register indirect with post-increment-@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. For word or longword access, the register value should be even. (b) Register indirect with pre-decrement-@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. For word or longword access, the register value should be even. (5) Absolute Address-@aa:8, @aa:16, @aa:24, or @aa:32 The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2.12 indicates the accessible absolute address ranges. Rev. 0.1, 11/98, page 44 of 975 Table 2.12 Absolute Address Access Ranges Absolute Address Data address Normal Mode Advanced Mode 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF 16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H007FFF, H'FF8000 to H'FFFFFF 32 bits (@aa:32) Program instruction address H'000000 to H'FFFFFF 24 bits (@aa:24) (6) Immediate-#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. (7) Program-Counter Relative-@(d:8, PC) or @(d:16, PC) This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. (8) Memory Indirect-@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode the memory operand is a word operand and the branch address is 16 bits long. In advanced mode the memory operand is a longword operand, the first byte of which is assumed to be all 0 (H'00). Note that the first part of the address range is also the exception vector area. For further details, see section 5, Exception Handling. Rev. 0.1, 11/98, page 45 of 975 Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal Mode (b) Advanced Mode Figure 2.13 Branch Address Specification in Memory Indirect Mode If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or an instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) 2.7.2 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Rev. 0.1, 11/98, page 46 of 975 Table 2.13 Effective Address Calculation (1) No. Addressing Mode and Instruction Format 1 Register direct (Rn) op 2 Effective Address Calculation Effective Address (EA) Operand is general register contents rm rn Register indirect (@ERn) 31 0 3 24 23 0 Don't care General register contents op 31 r Register indirect with displacement @(d:16, ERn) or @(d:32, ERn) 31 0 General register contents 31 op r disp 31 0 0 Sign extension 4 24 23 Don't care disp Register indirect with post-increment or pre-decrement * Register indirect with post-increment @ERn+ 31 0 24 23 0 Don't care General register contents op 31 r 1, 2, or 4 * Register indirect with pre-decrement @-ERn 31 0 General register contents 31 op 24 23 0 Don't care r Operand Size Byte Word Longword Value Added 1 2 4 1, 2, or 4 Rev. 0.1, 11/98, page 47 of 975 Table 2.13 Effective Address Calculation (2) No. Addressing Mode and Instruction Format 5 Absolute address Effective Address Calculation Effective Address (EA) @aa:8 31 op 24 23 Don't care abs @aa:16 31 op 0 H'FFFF 24 23 16 15 Sign extension 0 24 23 0 Don't care abs @aa:24 31 op 87 Don't care abs @aa:32 op 31 abs 6 Immediate #xx:8/#xx:16/#xx:32 op 7 24 23 0 Don't care Operand is immediate data IMM Program-counter relative @(d:8, PC)/@(d:16, PC) 0 23 PC contents op disp Rev. 0.1, 11/98, page 48 of 975 23 Sign extension 0 disp 31 24 23 Don't care 0 Table 2.13 Effective Address Calculation (3) No. Addressing Mode and Instruction Format 8 Memory indirect @@aa:8 * Effective Address Calculation Effective Address (EA) Normal mode op abs 31 87 0 abs H'000000 31 24 23 Don't care 16 15 0 H'00 0 15 Memory contents * Advanced mode op abs 31 87 H'000000 31 0 abs 0 Memory contents 31 24 23 0 Don't care Rev. 0.1, 11/98, page 49 of 975 2.8 Processing States 2.8.1 Overview The CPU has four main processing states: the reset state, exception-handling state, program execution state, and power-down state. Figure 2.14 shows a diagram of the processing states. Figure 2.15 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped. Exception-handling state A transient state in which the CPU changes the normal processing flow in response to a reset, interrupt or trap instruction. Processing states Program execution state The CPU executes program instructions in sequence. Sleep mode Power-down state CPU operation is stopped to conserve power.* Standby mode Note: * The power-down state also includes a medium-speed mode, modue stop mode, sub-active mode, sub-sleep mode and watch mode. Figure 2.14 Processing States Rev. 0.1, 11/98, page 50 of 975 En d of Re ex qu ce es pt tf io or n ha ex ce nd pt ion ling ha nd lin g Program execution state upt rr Inte Exception-handling state S w LE SS ith EP BY LS in =0 ON stru =0 ct , ion Sleep mode est u req S w LE SS ith EP BY LS in =0 ON stru =0 ct , ion External interrupt request Standby mode Power-down state*2 RES = High Reset state *1 Notes: 1. From any state, a transition to the reset state occurs whenever RES goes low. A transition can also be made to the reset state when the watchdog timer overflows. 2. The power-down state also includes a watch mode, subactive mode, subsleep mode, etc. For details, see section 4, Power-Down State. Figure 2.15 State Transitions 2.8.2 Reset State When the 5(6 input goes low all current processing stops and the CPU enters the reset state. All interrupts are disabled in the reset state. Reset exception handling starts when the 5(6 signal changes from low to high. The reset state can also be entered by a watchdog timer overflow. For details, see section 17, Watchdog Timer. Rev. 0.1, 11/98, page 51 of 975 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. (1) Types of Exception Handling and Their Priority Exception handling is performed for resets, interrupts, and trap instructions. Table 2.14 indicates the types of exception handling and their priority. Trap instruction exception handling is always accepted in the program execution state. Exception handling and the stack structure depend on the interrupt control mode set in SYSCR. Table 2.14 Exception Handling Types and Priority Priority Type of Exception Detection Timing High Reset Synchronized with clock Exception handling starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows Interrupt End of instruction execution or end of exception-handling *1 sequence When an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence Trap instruction When TRAPA instruction is executed Exception handling starts when a trap *2 (TRAPA) instruction is executed Low Start of Exception Handling Notes: 1. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or immediately after reset exception handling. 2. Trap instruction exception handling is always accepted in the program execution state. (2) Reset Exception Handling After the 5(6 pin has gone low and the reset state has been entered, when 5(6 goes high again, reset exception handling starts. When reset exception handling starts the CPU fetches a start address (vector) from the exception vector table and starts program execution from that address. All interrupts, including NMI, are disabled during reset exception handling and after it ends. (3) Interrupt Exception Handling and Trap Instruction Exception Handling When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer (ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start address (vector) from the exception vector table and program execution starts from that start address. Rev. 0.1, 11/98, page 52 of 975 Figure 2.16 shows the stack after exception handling ends. Normal Mode SP *2 Advanced Mode CCR CCR*1 SP CCR PC (24 bits) PC (16 bits) Notes: 1. Ignored when returning. 2. Normal mode is not available for this LSI. Figure 2.16 Stack Structure after Exception Handling (Examples) Rev. 0.1, 11/98, page 53 of 975 2.8.4 Program Execution State In this state the CPU executes program instructions in sequence. 2.8.5 Power-Down State The power-down state includes both modes in which the CPU stops operating and modes in which the CPU does not stop. There are five modes in which the CPU stops operating: sleep mode, standby mode, subsleep mode, and watch mode. There are also three other power-down modes: medium-speed mode, module stop mode, and subactive mode. In medium-speed mode, the CPU operates on a medium-speed clock. Module stop mode permits halting of the operation of individual modules, other than the CPU. Subactive mode, subsleep mode, and watch mode are power-down modes that use subclock input. For details, see section 4, Power-Down State. (1) Sleep Mode A transition to sleep mode is made if the SLEEP instruction is executed while the software standby bit (SSBY) in the standby control register (SBYCR) and the LSON bit in the lowpower control register (LPWRCR) are both cleared to 0. In sleep mode, CPU operations stop immediately after execution of the SLEEP instruction. The contents of CPU registers are retained. (2) Standby Mode A transition to standby mode is made if the SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1 and the LSON bit in LPWRCR and the TMA3 bit in the TMA (timer A) are both cleared to 0. In standby mode, the CPU and clock halt and all MCU operations stop. As long as a specified voltage is supplied, the contents of CPU registers and on-chip RAM are retained. Rev. 0.1, 11/98, page 54 of 975 2.9 Basic Timing 2.9.1 Overview The CPU is driven by a system clock, denoted by the symbol . The period from one rising edge of to the next is referred to as a "state." The memory cycle or bus cycle consists of one or two states. Different methods are used to access on-chip memory and on-chip supporting modules. 2.9.2 On-Chip Memory (ROM, RAM) On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and word transfer instruction. Figure 2.17 shows the on-chip memory access cycle. Bus cycle T1 Internal address bus Address Internal read signal Read access Internal data bus Read data Internal write signal Write access Internal data bus Write data Figure 2.17 On-Chip Memory Access Cycle Rev. 0.1, 11/98, page 55 of 975 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.18 shows the access timing for the on-chip supporting modules. Bus cycle T2 T1 Internal address bus Address Internal read signal Read access Internal data bus Read data Internal write signal Write access Internal data bus Write data Figure 2.18 On-Chip Supporting Module Access Cycle Rev. 0.1, 11/98, page 56 of 975 Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection This LSI has one operating mode (mode 1). This mode is selected depending on settings of the mode pin (MD0). Table 3.1 lists the MCU operating modes. Table 3.1 MCU Operating Mode Selection MCU Operating Mode MD0 CPU Operating Mode Description 0 0 1 1 Advanced Single-chip mode The CPU's architecture allows for 4 Gbytes of address space, but this LSI actually accesses a maximum of 16 Mbytes. Mode 1 operation starts in single-chip mode after reset release. This LSI can only be used in mode 1. This means that the mode pins must be set at mode 1. Do not changes the inputs at the mode pins during operation. 3.1.2 Register Configuration This LSI has a mode control register (MDCR) that indicates the inputs at the mode pin (MD0) and a system control register (SYSCR) and that controls the operation of this LSI. Table 3.2 summarizes these registers. Table 3.2 MCU Registers Name Abbreviation R/W Initial Value Address* Mode control register MDCR R/W Undetermined H'FFE9 System control register SYSCR R/W H'09 H'FFE8 Note: * Lower 16 bits of the address. Rev. 0.1, 11/98, page 57 of 975 3.2 Register Descriptions 3.2.1 Mode Control Register (MDCR) 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- MDS0 Initial value : 0 0 0 0 0 0 0 --* R/W : -- -- -- -- -- -- -- R Bit : Note: * Determined by MD0 pin MDCR is an 8-bit read-only register monitors the current operating mode of this LSI. Bit 7 to 1: Reserved. These bits cannot be modified and are always set at 0. Bit 0: Mode Select 0 (MDS0) This bit indicates the value which reflects the input levels at mode pin (MD0) (the current operating mode). Bit MDS0 corresponds to MD0 pin. They are read-only bits-they cannot be written to. The mode pin (MD0) input levels are latched into these bits when MDCR is read. 3.2.2 System Control Register (SYSCR) Bit : 7 6 5 4 3 -- -- INTM1 INTM0 XRST 0 0 1 Initial value : 0 0 R/W : -- -- Bits 7 and 6: Reserved. Rev. 0.1, 11/98, page 58 of 975 R R/W R 2 1 NMIEG1 NMIEG0 0 R/W 0 -- 0 1 R/W -- Bits 5 and 4: Interrupt control modes 1 and 0 (INTM1, INTM0) These bits are for selecting the interrupt control mode of the interrupt controller. For details of the interrupt control modes, see section 6.4.1, Interrupt Operation Flow. Bit 5 INTM1 Bit 4 INTM0 Interrupt Control Mode Description 0 0 0 Interrupt is controlled by bit I 1 1 Interrupt is controlled by bits I and UI, and ICR 0 2 Cannot be used in this LSI 1 3 Cannot be used in this LSI 1 (Initial value) Bit 3: External Reset (XRST) Indicates the reset source. When the watchdog timer is used, a reset can be generated by watchdog timer overflow as well as by external reset input. XRST is a read-only bit. It is set to 1 by an external reset and cleared to 0 by watchdog timer overflow. Bit 3 XRST Description 0 A reset is generated by watchdog timer overflow 1 A reset is generated by an external reset (Initial value) Bits 2 and 1: NMI edge select 1 and 0 (NMIG1, 0) Select the input edge for NMI interrupt. Bit 2 NIMIEG1 Bit 1 NIMIEG0 Description 0 0 An interrupt request occurs at falling edge of NMI input 1 An interrupt request occurs at rising edge of NMI input * An interrupt request occurs at rising or falling edge of NMI input 1 Note: * (Initial value) Don't care Bit 0: Reserved. 3.3 Operating Mode Descriptions 3.3.1 Mode 1 The CPU can access a 16 Mbyte address space in advanced mode. Rev. 0.1, 11/98, page 59 of 975 3.4 Address Map in Each Operating Mode Vector area H'0000FF On-chip ROM (80 kbytes) Absolute address, 16 bits H'000000 H8S/2192 Memory indirect branch address H8S/2191 H'000000 Vector area On-chip ROM (96 kbytes) H'007FFF H'013FFF H'017FFF H'FFD000 Internal I/O register H'FFD2FF H'FFFF00 H'FFFFAF H'FFFFB0 Internal I/O register H'FFFFFF 3 kbytes On-chip RAM Absolut e address, 8 bits H'FFF3B0 Absolute address, 16 bits H'FF8000 H'FFD000 Internal I/O register H'FFD2FF H'FFF3B0 On-chip RAM H'FFFFAF H'FFFFB0 Internal I/O register H'FFFFFF Figure 3.1 Address Map (1) Rev. 0.1, 11/98, page 60 of 975 H8S/2193 H'000000 H8S/2194 H'000000 Vector area Vector area On-chip ROM (112 kbytes) On-chip ROM (128 kbytes) H'01BFFF H'01FFFF H'FFD000 Internal I/O register H'FFD2FF H'FFD000 Internal I/O register H'FFD2FF H'FFF3B0 H'FFF3B0 On-chip RAM On-chip RAM H'FFFFAF H'FFFFB0 H'FFFFAF H'FFFFB0 Internal I/O register Internal I/O register H'FFFFFF H'FFFFFF Figure 3.2 Address Map (2) Rev. 0.1, 11/98, page 61 of 975 Rev. 0.1, 11/98, page 62 of 975 Section 4 Power-Down State 4.1 Overview In addition to the normal program execution state, this LSI has a power-down state in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on. This LSI operating modes are as follows: 1. 2. 3. 4. 5. 6. 7. 8. High-speed mode Medium-speed mode Subactive mode Sleep mode Subsleep mode Watch mode Module stop mode Standby mode Of these, 2 to 8 are power-down modes. Certain combinations of these modes can be set. After a reset, the MCU is in high-speed mode. Table 4.1 shows the internal chip states in each mode, and table 4.2 shows the conditions for transition to the various modes. Figure 4.1 shows a mode transition diagram. Rev. 0.1, 11/98, page 63 of 975 Table 4.1 H8S/2194 Series Internal States in Each Mode High- Medium- Function Speed Speed System clock Functioning Functioning Functioning Functioning Halted Subclock pulse generator Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning CPU operation External interrupts Module Sleep Instructions Functioning Mediumspeed Halted Registers Retained NIMI Stop Watch Functioning Halted Subactive Subsleep Standby Halted Halted Halted Subclock operation Retained Halted Halted Retained Retained Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning IRQ0 IRQ1 IRQ2 Halted Halted Functioning Halted IRQ3 IRQ4 IRQ5 On-chip supporting module operation Timer A Functioning Functioning Functioning Functioning Subclock /halted operation (retained) Subclock operation Subclock operation Halted (retained) Timer B Functioning Functioning Functioning Functioning Halted /halted (retained) (retained) Halted (retained) Halted (retained) Halted (retained) Halted (reset) Halted (reset) Halted (reset) Timer J Timer R Timer X1 Functioning Halted /halted (reset) (reset) Watchdog timer Functioning Functioning Functioning Functioning Halted (retained) Halted (retained) Halted (retained) Halted (retained) IIC Functioning Functioning Functioning Functioning Halted /halted (retained) (retained) Halted (retained) Halted (retained) Halted (retained) SCI1 Functioning Halted /halted (reset) (reset) Halted (reset) Halted (reset) Halted (reset) SCI2 Functioning Halted /halted (retained) (retained) Halted (retained) Halted (retained) Halted (retained) Functioning Halted /halted (reset) (reset) Halted (reset) Halted (reset) Halted (reset) 14-bit PWM 8-bit PWM A/D I/O Functioning Functioning Functioning Functioning Retained Functioning Retained Halted Servo Functioning Functioning Halted (reset) Halted (reset) Halted (reset) Functioning Halted /halted (reset) (reset) Halted (reset) Notes: 1. "Halted (retained)" means that internal register values are retained. The internal state is "operation suspended." 2. "Halted (reset)" means that internal register values and internal states are initialized. Rev. 0.1, 11/98, page 64 of 975 3. In module stop mode, only modules for which a stop setting has been made are halted (reset or retained). 4. In the power-down mode, the analog section of the servo circuits are not turned off, therefore Vcc (Servo) current does not go low. When power-down is needed, externally shut down the analog system power. Reset state Program-halted state Program execution state SLEEP instruction a Standby mode Interrupt 1 SLEEP instruction a Interrupt 1 SLEEP instruction b Interrupt 2 SLEEP instruction b SLEEP instruction b Interrupt 2 Interrupt 3 h SLEEP instruction c Sleep (high-speed) mode SLEEP instruction d SLEEP instruction e Active (medium-speed) mode SLEEP Interrupt 2 instruction c Watch mode SLEEP instruction e Active (high-speed) mode g Program-halted state Sleep (medium-speed) mode Interrupt 3 SLEEP instruction d Subactive mode SLEEP instruction 1 Interrupt 4 Subsleep mode Power-down mode Conditions for mode transition (1) Conditions for mode transition (2) Interruption factor Flag LSON SSBY TMA3 DTON 0 1 0 * 1 NMI, IRQ0 to 1 b * 1 1 0 2 NMI, IRQ0 to 1, Timer A interruption c 0 1 1 1 3 All interruption (excluding servo system) d 1 1 1 1 4 NMI, IRQ0 to 5, Timer A interruption e 0 0 * * f 1 0 1 * a g SCK2 to 0 = 0 h SCK2 to 0 0 (either 1 bit = 0) Note: * Don't care Note: When a transition is made between modes by means of an interrupt, transition cannot be made on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the interrupt request Figure 4.1 Mode Transitions Rev. 0.1, 11/98, page 65 of 975 Table 4.2 Power-Down Mode Transition Conditions Control Bit States at Time of Transition State before Transition High-speed /mediumspeed Subactive SSBY TMA3 LSON DTON State after Transition by SLEEP Instruction State after Return by Interrupt 0 * 0 * Sleep High-speed *1 /medium-speed 0 * 1 * 1 0 0 * Standby High-speed *1 /medium-speed 1 0 1 * 1 1 0 0 Watch High-speed *1 /medium-speed 1 1 1 0 Watch Subactive 1 1 0 1 1 1 1 1 Subactive 0 0 * * 0 1 0 * 0 1 1 * Subsleep Subactive 1 0 * * 1 1 0 0 Watch High-speed *2 /medium-speed 1 1 1 0 Watch Subactive 1 1 0 1 High-speed *2 /medium-speed 1 1 1 1 Notes: * Don't care : Do not set. 1. Returns to the state before transition. 2. Mode varies depending on the state of SCK2 to SCK0. Rev. 0.1, 11/98, page 66 of 975 4.1.1 Register Configuration The power-down state is controlled by the SBYCR, LPWRCR, TMA (Timer A), and MSTPCR registers. Table 4.3 summarizes these registers. Table 4.3 Power-Down State Registers Name Abbreviation R/W Initial Value Address* Standby control register SBYCR R/W H'00 H'FFEA Low-power control register LPWRCR R/W H'00 H'FFEB Module stop control register MSTPCRH R/W H'FF H'FFEC MSTPCRL R/W H'FF H'FFED TMA R/W H'30 H'FFBA Timer mode register Note: * Lower 16 bits of the address. 4.2 Register Descriptions 4.2.1 Standby Control Register (SBYCR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 -- -- SCK1 SCK0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W -- -- R/W R/W SBYCR is an 8-bit readable/writable register that performs power-down mode control. SBYCR is initialized to H'00 by a reset. Rev. 0.1, 11/98, page 67 of 975 Bit 7: Software Standby (SSBY) Determines the operating mode, in combination with other control bits, when a power-down mode transition is made by executing a SLEEP instruction. The SSBY setting is not changed by a mode transition due to an interrupt, etc. Bit 7 SSBY Description 0 Transition to sleep mode after execution of SLEEP instruction in high-speed mode or medium-speed mode Transition to subsleep mode after execution of SLEEP instruction in subactive mode (Initial value) 1 Transition to standby mode, subactive mode, or watch mode after execution of SLEEP instruction in high-speed mode or medium-speed mode Transition to watch mode or high-speed mode after execution of SLEEP instruction in subactive mode Bits 6 to 4: Standby Timer Select 2 to 0 (STS2 to STS0) These bits select the time the MCU waits for the clock to stabilize when standby mode, watch mode, or subactive mode is cleared and a transition is made to high-speed mode or mediumspeed mode by means of a specific interrupt or instruction. With crystal oscillation, see table 4.5 and make a selection according to the operating frequency so that the standby time is at least 10 ms (the oscillation settling time). With an external clock, any selection can be made. (With FLASH ROM version, do not set the standby time to 16 states.) Bit 6 STS2 Bit 5 STS1 Bit 4 STS0 Description 0 0 0 Standby time = 8192 states 0 0 1 Standby time = 16384 states 0 1 0 Standby time = 32768 states 0 1 1 Standby time = 65536 states 1 0 0 Standby time = 131072 states 1 0 1 Standby time = 262144 states 1 1 * Standby time = 16 states *1 Notes: * Don't care 1. With FLASH ROM version, do not set the standby time to 16 states. The standby time is 32 states when transited to medium-speed mode /32 (SCK1=1, SCK0=0). Bit 3, 2: Reserved. These bits cannot be modified and are always read as 0. Rev. 0.1, 11/98, page 68 of 975 Bits 1, 0: System Clock Select 1, 0 (SCK1, SCK0) These bits select the CPU clock for the bus master in high-speed mode and medium-speed mode. Bit 1 SCK1 Bit 2 SCK0 Description 0 0 Bus master is in high-speed mode (Initial value) 0 1 Medium-speed clock is /16 1 0 Medium-speed clock is /32 1 1 Medium-speed clock is /64 Rev. 0.1, 11/98, page 69 of 975 4.2.2 Low-Power Control Register (LPWRCR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 DTON LSON NESEL -- -- -- SA1 SA0 0 0 0 0 0 0 0 0 R/W R/W R/W -- -- -- R/W R/W LPWRCR is an 8-bit readable/writable register that performs power-down mode control. LPWRCR is initialized to H'00 by a reset. Bit 7: Direct-Transfer On Flag (DTON) Specifies whether a direct transition is made between high-speed mode, medium-speed mode, and subactive mode when making a power-down transition by executing a SLEEP instruction. The operating mode to which the transition is made after SLEEP instruction execution is determined by a combination of other control bits. Bit 7 DTON Description 0 * When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, standby mode, or watch mode * When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode or watch mode (Initial value) * When a SLEEP instruction is executed in high-speed mode or medium-speed mode, transition is made directly to subactive mode, or a transition is made to sleep mode or standby mode * When a SLEEP instruction is executed in subactive mode, a transition is made directly to high-speed mode, or a transition is made to subsleep mode 1 Rev. 0.1, 11/98, page 70 of 975 Bit 6: Low-Speed On Flag (LSON) Determines the operating mode in combination with other control bits when making a powerdown transition by executing a SLEEP instruction. Also controls whether a transition is made to high-speed mode or to subactive mode when watch mode is cleared. Bit 6 LSON Description 0 * When a SLEEP instruction is executed in high-speed mode or medium-speed mode, transition is made to sleep mode, standby mode, or watch mode * When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode, or directly to high-speed mode * After watch mode is cleared, a transition is made to high-speed mode (Initial value) * When a SLEEP instruction is executed in high-speed mode a transition is made to watch mode, subactive mode, sleep mode or standby mode * When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode or watch mode * After watch mode is cleared, a transition is made to subactive mode 1 Bit 5: Noise Elimination Sampling Frequency Select (NESEL) Selects the frequency at which the subclock (w) generated by the subclock pulse generator is sampled with the clock () generated by the system clock oscillator. When = 5 MHz or higher, clear this bit to 0. Bit 5 NESEL Description 0 Sampling at divided by 16 1 Sampling at divided by 4 Bits 4 to 2: Reserved. These bits cannot be modified and are always read as 0. Rev. 0.1, 11/98, page 71 of 975 Bit 1, 0: Subactive mode clock select 1, 0 (SA1, SA0) These bits select the CPU operating clock in the subactive mode. These bits cannot be modified in the subactive mode. Bit 1 SA1 Bit 0 SA0 Description 0 0 Operating clock of CPU is w/8 0 1 Operating clock of CPU is w/4 1 * Operating clock of CPU is w/2 Note: 4.2.3 * (Initial value) Don't care Timer Register A (TMA) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 TMAOV TMAIE -- -- TMA3 TMA2 TMA1 TMA0 0 0 1 1 0 0 0 0 R/(W)* R/W R/W R/W R/W R/W R/W R/W Note: * Only 0 can be written, to clear the flag. The timer register A (TMA) controls timer A interrupts and selects input clock. Only Bit 3 is explained here. For details of other bits, see section 11.1, Timer Mode Register A. TMA is a readable/writable register which is initialized to H'30 by a reset. Rev. 0.1, 11/98, page 72 of 975 Bit 3: Clock source, prescaler select (TMA3) Selects Timer A clock source between PSS and PSW. Also controls transition operation to the power-down mode. The operation mode to which the MCU is transited after SLEEP instruction execution is determined by the combination with other control bits than this bit. For details, see the description of Clock Select 2 to 0 in section 11.1, Timer Mode Register A. Bit 3 TMA3 Description 0 * Timer A counts -based prescaler (PSM) divided clock pulses * When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode or software standby mode (Initial value) * Timer A counts w-based prescaler (PSM) divided clock pulses * When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, watch mode, or subactive mode * When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode, watch mode, or high-speed mode 1 4.2.4 Module Stop Control Register (MSTPCR) MSTPCRH Bit : 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR comprises two 8-bit readable/writable registers that perform module stop mode control. MSTPCR is initialized to H'FFFF by a reset. Rev. 0.1, 11/98, page 73 of 975 MSTRCRH and MSTPCRL Bits 7 to 0: Module Stop (MSTP 15 to MSTP 0) These bits specify module stop mode. See table 4.4 for the method of selecting on-chip supporting modules. MSTPCRH, MSTPCRL Bits 7 to 0 MSTP 15 to MSTP 0 Description 0 Module stop mode is cleared 1 Module stop mode is set 4.3 (Initial value) Medium-Speed Mode When the SCK1 and SCK0 bits in SBYCR are set to 1 in high-speed mode, the operating mode changes to medium-speed mode at the end of the bus cycle. In medium-speed mode, the CPU operates on the operating clock (16, 32 or 64) specified by the SCK1 and SCK0 bits. The on-chip supporting modules other than the CPU always operate on the high-speed clock (). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if 16 is selected as the operating clock, onchip memory is accessed in 16 states, and internal I/O registers in 32 states. Medium-speed mode is cleared by clearing the both bits SCK1 and SCK0 to 0. A transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. If a SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON bit in LPWRCR are cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored. If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, and the LSON bit in LPWRCR and the TMA3 bit in TMA (Timer A) are both cleared to 0, a transition is made to software standby mode. When standby mode is cleared by an external interrupt, medium-speed mode is restored. When the 5(6 pin is driven low, a transition is made to the reset state, and medium-speed mode is cleared. The same applies in the case of a reset caused by overflow of the watchdog timer. Figure 4.2 shows the timing for transition to and clearance of medium-speed mode. Rev. 0.1, 11/98, page 74 of 975 Medium-speed mode Internal , supporting module clock CPU clock Internal address bus SBYCR SBYCR Internal write signal Figure 4.2 Medium-Speed Mode Transition and Clearance Timing 4.4 Sleep Mode 4.4.1 Sleep Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON bit in LPWRCR are both cleared to 0, the CPU enters sleep mode. In sleep mode, CPU operation stops but the contents of the CPU's internal registers are retained. Other supporting modules (excluding the servo circuit) do not stop. 4.4.2 Clearing Sleep Mode Sleep mode is cleared by any interrupt, or with the 5(6 pin. (1) Clearing with an Interrupt When an interrupt request signal is input, sleep mode is cleared and interrupt exception handling is started. Sleep mode will not be cleared if interrupts are disabled, or if interrupts other than NMI have been masked by the CPU. (2) Clearing with the 5(6 Pin When the 5(6 pin is driven low, the reset state is entered. When the 5(6 pin is driven high after the prescribed reset input period, the CPU begins reset exception handling. Rev. 0.1, 11/98, page 75 of 975 4.5 Module Stop Mode 4.5.1 Module Stop Mode Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. Table 4.4 shows MSTP bits and the on-chip supporting modules. When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts operating again at the end of the bus cycle. In module stop mode, the internal states of modules other than the SCI1, A/D converter, Timer X1, and Servo circuit, are retained. After reset release, all modules are in module stop mode. When an on-chip supporting module is in module stop mode, read/write access to its registers is disabled. Table 4.4 MSTP Bits and Corresponding On-Chip Supporting Modules Register Bit Module MSTPCRH MSTP15 Timer A MSTP14 Timer B MSTP13 Timer J MSTP12 Timer L MSTP11 Timer R MSTP10 Timer X1 MSTP9 MSTP8 Serial communication interface 1 (SCI1) MSTP7 Serial communication interface 2 (SCI2) MSTP6 I C bus interface (IIC) MSTP5 14-bit PWM MSTP4 8-bit PWM MSTP3 MSTPCRL 2 MSTP2 A/D converter MSTP1 Servo circuit MSTP0 Rev. 0.1, 11/98, page 76 of 975 4.6 Standby Mode 4.6.1 Standby Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, the LSON bit in LPWRCR is cleared to 0, and the TMA3 bit in TMA (Timer A) is cleared to 0, standby mode is entered. In this mode, the CPU, on-chip supporting modules, and oscillator (except for subclock oscillator) all stop. However, contents of the CPU's internal registers and data in the built-in RAM as well as functions of the SCII, timer X1 and built-in peripheral circuits (except the servo circuit) are maintained in the current state. The I/O port, at this time, is caused to the high impedance state. In this mode the oscillator stops, and therefore power dissipation is significantly reduced. 4.6.2 Clearing Standby Mode Standby mode is cleared by an external interrupt (NMI pin, or pin ,54 to ,54, or by means of the 5(6 pin. (1) Clearing with an Interrupt When an NMI, ,54 to ,54 interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SYSCR, stable clocks are supplied to the entire chip, standby mode is cleared, and interrupt exception handling is started. Standby mode cannot be cleared with an ,54 to ,54 interrupt if the corresponding enable bit has been cleared to 0 or has been masked by the CPU. (2) Clearing with the 5(6 Pin When the 5(6 pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire chip. Note that the 5(6 pin must be held low until clock oscillation stabilizes. When the 5(6 pin goes high, the CPU begins reset exception handling. 4.6.3 Setting Oscillation Settling Time after Clearing Standby Mode Bits STS2 to STS0 in SBYCR should be set as described below. (1) Using a Crystal Oscillator Set bits STS2 to STS0 so that the standby time is at least 10 ms (the oscillation settling time). Table 4.5 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. Rev. 0.1, 11/98, page 77 of 975 Table 4.5 Oscillation Settling Time Settings STS2 STS1 STS0 Standby Time 10 MHz 8 MHz Unit 0 0 0 8192 states 0.8 1.0 ms 1 16384 states 1.6 2.0 0 32768 states 3.3 4.1 1 65536 states 6.6 8.2 0 131072 states 13.1 16.4 1 262144 states 26.2 32.8 1.6 2.0 1 1 0 1 Note: * * 16 states *1 s : Recommended time setting Don't care (2) Using an External Clock Any value can be set. Note: 1. With FLASH ROM version, do not set the standby time to 16 states. The standby time is 32 states when transited to medium-speed mode /32 (SCK1 = 1, SCK0 = 0). 4.7 Watch Mode 4.7.1 Watch Mode If a SLEEP instruction is executed in high-speed mode, medium-speed mode or subactive mode when the SSBY in SBYCR is set to 1, the DTON bit in LPWRCR is cleared to 0, and the TMA3 bit in TMA (Timer A) is set to 1, the CPU makes a transition to watch mode. In this mode, the CPU and all on-chip supporting modules except Timer A stop. As long as the prescribed voltage is supplied, the contents of some of the CPU's internal registers and on-chip RAM are retained, and I/O ports are placed in the high-impedance state. 4.7.2 Clearing Watch Mode Watch mode is cleared by an interrupt (Timer A interrupt, NMI pin, or pin ,54 to ,54), or by means of the 5(6 pin. (1) Clearing with an Interrupt When an interrupt request signal is input, watch mode is cleared and a transition is made to high-speed mode or medium-speed mode if the LSON bit in LPWRCR is cleared to 0, or to subactive mode if the LSON bit is set to 1. When making a transition to medium-speed mode, after the elapse of the time set in bits STS2 to STS0 in SBYCR, stable clocks are supplied to the entire chip, and interrupt exception handling is started. Rev. 0.1, 11/98, page 78 of 975 Watch mode cannot be cleared with an ,54 to ,54 interrupt if the corresponding enable bit has been cleared to 0, or with an on-chip supporting module interrupt if acceptance of the relevant interrupt has been disabled by the interrupt enable register or masked by the CPU. See section 4.6.3, Setting Oscillation Settling Time after Clearing Standby Mode, for the oscillation settling time setting when making a transition from watch mode to high-speed mode. (2) Clearing with the 5(6 Pin See (2) Clearing with the 5(6 Pin in section 4.6.2, Clearing Standby Mode. 4.8 Subsleep Mode 4.8.1 Subsleep Mode If a SLEEP instruction is executed in subactive mode when the SSBY in SBYCR is cleared to 0, the LSON bit in LPWRCR is set to 1, and the TMA3 bit in TMA (Timer A) is set to 1, the CPU makes a transition to subsleep mode. In this mode, the CPU and all on-chip supporting modules other than Timer A stop. As long as the prescribed voltage is supplied, the contents of the CPU, some of its on-chip registers and onchip RAM are retained, and I/O ports retain their states prior to the transition. 4.8.2 Clearing Subsleep Mode Subsleep mode is cleared by an interrupt (Timer A interrupt, NMI pin, or pin ,54 to ,54), or by means of the 5(6 pin. (1) Clearing with an Interrupt When an interrupt request signal is input, subsleep mode is cleared and interrupt exception handling is started. Subsleep mode cannot be cleared with an ,54 to ,54 interrupt if the corresponding enable bit has been cleared to 0, or with an on-chip supporting module interrupt if acceptance of the relevant interrupt has been disabled by the interrupt enable register or masked by the CPU. (2) Clearing with the 5(6 Pin See (2) Clearing with the 5(6 Pin in section 4.6.2, Clearing Standby Mode. Rev. 0.1, 11/98, page 79 of 975 4.9 Subactive Mode 4.9.1 Subactive Mode If a SLEEP instruction is executed in high-speed mode when the SSBY bit in SBYCR, the DTON bit in LPWRCR, and the TMA3 bit in TMA (Timer A) are all set to 1, the CPU makes a transition to subactive mode. When an interrupt is generated in watch mode, if the LSON bit in LPWRCR is set to 1, a transition is made to subactive mode. When an interrupt is generated in subsleep mode, a transition is made to subactive mode. In subactive mode, the CPU performs sequential program execution at low speed on the subclock. In this mode, all on-chip supporting modules other than Timer A stop. 4.9.2 Clearing Subactive Mode Subsleep mode is cleared by a SLEEP instruction, or by means of the 5(6 pin. (1) Clearing with a SLEEP Instruction When a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the DTON bit in LPWRCR is cleared to 0, and the TMA3 bit in TMA (Timer A) is set to 1, subactive mode is cleared and a transition is made to watch mode. When a SLEEP instruction is executed while the SSBY bit in SBYCR is cleared to 0, the LSON bit in LPWRCR is set to 1, and the TMA3 bit in TMA (Timer A) is set to 1, a transition is made to subsleep mode. When a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the DTON bit is set to 1 and the LSON bit is cleared to 0 in LPWRCR, and the PSS bit in TCSR (WDT1) is set to 1, a transition is made directly to high-speed or medium-speed mode. Fort details of direct transition, see section 4.10, Direct Transition. (2) Clearing with the 5(6 Pin See (2) Clearing with the 5(6 Pin in section 4.6.2, Clearing Standby Mode. Rev. 0.1, 11/98, page 80 of 975 4.10 Direct Transition 4.10.1 Overview of Direct Transition There are three operating modes in which the CPU executes programs: high-speed mode, medium-speed mode, and subactive mode. A transition between high-speed mode and subactive mode without halting the program* is called a direct transition. A direct transition can be carried out by setting the DTON bit in LPWRCR to 1 and executing a SLEEP instruction. After the transition, direct transition interrupt exception handling is started. (1) Direct Transition from High-Speed Mode to Subactive Mode If a SLEEP instruction is executed in high-speed mode while the SSBY bit in SBYCR, the LSON bit and DTON bit in LPWRCR, and the TMA3 bit in TMA (Timer A) are all set to 1, a transition is made to subactive mode. (2) Direct Transition from Subactive Mode to High-Speed Mode/Medium-Speed Mode If a SLEEP instruction is executed in subactive mode while the SSBY bit in SBYCR is set to 1, the LSON bit is cleared to 0 and the DTON bit is set to 1 in LPWRCR, and the TMA3 bit in TMA (Timer A) is set to 1, after the elapse of the time set in bits STS2 to STS0 in SBYCR, a transition is made to directly to high-speed mode. Note: * At the time of transition from subactive mode to high- or medium-speed mode, an oscillation stabilization wait time is generated. Rev. 0.1, 11/98, page 81 of 975 Rev. 0.1, 11/98, page 82 of 975 Section 5 Exception Handling 5.1 Overview 5.1.1 Exception Handling Types and Priority As table 5.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 5.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions are accepted at all times in the program execution state. Exception handling sources, the stack structure, and the operation of the CPU vary depending on the interrupt control mode set by the INTM0 and INTM1 bits in SYSCR. Table 5.1 Exception Types and Priority Priority Exception Type Start of Exception Handling High Reset Starts immediately after a low-to-high transition at the 5(6 pin, or when the watchdog timer overflows Trace Low *1 Starts when execution of the current instruction or exception handling ends, if the trace (T) bit is set to 1 Interrupt Starts when execution of the current instruction or exception *2 handling ends, if an interrupt request has been issued Direct transition Started by a direct transition resulting from execution of a SLEEP instruction Trap instruction *3 (TRAPA) Started by execution of a trap instruction (TRAPA) Notes: 1. Traces are enabled only in interrupt control modes 2 and 3. (They cannot be used in this LSI.) Trace exception handling is not executed after execution of an RTE instruction. 2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 3. Trap instruction exception handling requests are accepted at all times in the program execution state. Rev. 0.1, 11/98, page 83 of 975 5.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: [1] The program counter (PC) and condition-code register (CCR) are pushed onto the stack. [2] The interrupt mask bits are updated. The T bit is cleared to 0. [3] A vector address corresponding to the exception source is generated, and program execution starts from that address. For a reset exception, steps [2] and [3] above are carried out. 5.1.3 Exception Sources and Vector Table The exception sources are classified as shown in figure 5.1. Different vector addresses are assigned to different exception sources. Table 5.2 lists the exception sources and their vector addresses. * Reset * Trace (cannot be used in this LSI) External interrupts ... NMI, IRQ5 to IRQ0 Exception sources * Interrupts Internal interrupts ... Interrupt sources in on-chip supporting modules * Direct transition * Trap instruction Figure 5.1 Exception Sources Rev. 0.1, 11/98, page 84 of 975 Table 5.2 Exception Vector Table Exception Source Vector Number Vector Address*1 Reset 0 H'0000 to H'0003 Reserved for system use 1 H'0004 to H'0007 2 3 H'0008 to H'000B H'000C to H'000F 4 H'0010 to H'0013 Direct transition 5 6 H'0014 to H'0017 H'0018 to H001B External interrupt NMI Trap instruction (4 sources) 7 8 H'001C to H'001F H'0020 to H'0023 9 H'0024 to H'0027 #0 10 11 12 13 14 15 16 H'0028 to H'002B H'002C to H'002F H'0030 to H'0033 H'0034 to H'0037 H'0038 to H'003B H'003C to H'003F H'0040 to H'0043 #1 17 H'0044 to H'0047 #2 Internal interrupt (IC) Internal interrupt (HSW1) 18 19 20 H'0048 to H'004B H'004C to H'004F H'0050 to H'0053 External interrupt IRQ0 IRQ1 IRQ2 IRQ3 21 22 23 24 H'0054 to H'0057 H'0058 to H'005B H'005C to H'005F H'0060 to H'0063 IRQ4 IRQ5 25 26 27 33 H'0064 to H'0067 H'0068 to H'006B H'006C to H'006F H'0084 to H'0087 Reserved for system use Address trap Reserved Internal interrupt *2 30 H'0088 to H'008B 67 H'010C to H'010F Notes: 1. Lower 16 bits of the address. 2. For details on internal interrupt vectors, see section 6.3.3, Interrupt Exception Vector Table. Rev. 0.1, 11/98, page 85 of 975 5.2 Reset 5.2.1 Overview A reset has the highest exception priority. When the 5(6 pin goes low, all processing halts and the MCU enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip supporting modules. Immediately after a reset, interrupt control mode 0 is set. Reset exception handling begins when the 5(6 pin changes from low to high. The MCUs can also be reset by overflow of the watchdog timer. For details, see section 17, Watchdog Timer. 5.2.2 Reset Sequence The MCU enters the reset state when the 5(6 pin goes low. To ensure that the chip is reset, hold the 5(6 pin low during the oscillation stabilizing time of the clock oscillator when powering on. To reset the chip during operation, hold the 5(6 pin low for at least 20 states. For pin states in a reset, see Appendix D.1, Pin Circuit Diagrams. When the 5(6 pin goes high after being held low for the necessary time, the chip starts reset exception handling as follows: [1] The internal state of the CPU and the registers of the on-chip supporting modules are initialized, and the I bit is set to 1 in CCR. [2] The reset exception vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figures 5.2 shows examples of the reset sequence. Rev. 0.1, 11/98, page 86 of 975 Vector fetch Internal Fetch of first program processing instruction RES (1) Internal address bus (3) Internal read signal High level Internal write signal Internal data bus (1) (2) (3) (4) (2) (4) : Reset exception vector address ((1) = H'0000 or H'000000) : Start address (contents of reset exception vector address) : Start address ((3) = (2)) : First program instruction Figure 5.2 Reset Sequence (Mode 1) 5.2.3 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx:32, SP). Rev. 0.1, 11/98, page 87 of 975 5.3 Interrupts Interrupt exception handling can be requested by seven external sources (NMI and ,54 to ,54) and internal sources in the on-chip supporting modules. Figure 5.3 shows the interrupt sources and the number of interrupts of each type. The on-chip supporting modules that can request interrupts include the watchdog timer (WDT), prescaler unit (PSU), Timers A, B, J, L, R and X1 (TMR), serial communication interface (SCI), 2 A/D converter (ADC), I C bus interface (IIC), servo circuits, synchronized detection, address trap, etc. Each interrupt source has a separate vector address. NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to either three priority/mask levels to enable multiplexed interrupt control. For details on interrupts, see section 6, Interrupt Controller. NMI (1) External interrupts IRQ5 to IRQ0 (6) WDT*1 (1) Interrupts PSU (1) TMR (15) SCI (6) Internal interrupts ADC (1) IIC (1) Servo circuits (9) Synchronized detection (1) Address trap (3) Notes: Numbers in parentheses are the numbers of interrupt sources. 1. When the watchdog timer is used as an interval timer, it generates an interrupt request at each counter overflow. Figure 5.3 Interrupt Sources and Number of Interrupts Rev. 0.1, 11/98, page 88 of 975 5.4 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 5.3 shows the status of CCR and EXR after execution of trap instruction exception handling. Table 5.3 Status of CCR and EXR after Trap Instruction Exception Handling CCR EXR* Interrupt Control Mode I UI I2 to I0 T 0 1 1 1 1 Legend: 1: Set to 1 0: Cleared to 0 : Retains value prior to execution. *: Does not affect operation in this LSI. Rev. 0.1, 11/98, page 89 of 975 5.5 Stack Status after Exception Handling Figure 5.4 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP CCR CCR* PC (16 bits) Interrupt control modes 0 and 1 Note: * Ignored on return. Figure 5.4 (1) Stack Status after Exception Handling (Normal Mode)* Note: * Normal mode is not available for this LSI. SP CCR PC (24 bits) Interrupt control modes 0 and 1 Figure 5.4 (2) Stack Status after Exception Handling (Advanced Mode) Rev. 0.1, 11/98, page 90 of 975 5.6 Notes on Use of the Stack When accessing word data or longword data, this chip assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W Rn (or MOV.W @SP+, Rn) POP.L ERn (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 5.5 shows an example of what happens when the SP value is odd. CCR SP R1L SP H'FFFEFA H'FFFEFB PC PC H'FFFEFC H'FFFEFD SP H'FFFEFF TRAPA instruction executed SP set to H'FFFEFF [Legend] CCR PC R1L SP MOV.B R1L, @-ER7 Data saved above SP Contents of CCR lost : Condition-code register : Program counter : General register R1L : Stack pointer Note: This diagram illustrates an example in which the interrupt control mode is 0, is advanced mode. Figure 5.5 Operation when SP Value is Odd Rev. 0.1, 11/98, page 91 of 975 Rev. 0.1, 11/98, page 92 of 975 Section 6 Interrupt Controller 6.1 Overview 6.1.1 Features This LSI controls interrupts by means of an interrupt controller. The interrupt controller has the following features: (1) Two Interrupt Control Modes Either of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). (2) Priorities Settable with ICR An interrupt control register (ICR) is provided for setting interrupt priorities. Three priority levels can be set for each module for all interrupts except NMI. (3) Independent Vector Addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. (4) Seven External Interrupt Pins NMI is the highest-priority interrupt, and is accepted at all times. Falling edge, rising edge, or both edge detection can be selected for the NMI interrupt. Falling edge, rising edge, or both edge detection can be selected for interrupt IRQ0. Falling edge or rising edge can be individually selected for interrupts IRQ5 to IRQ1. Rev. 0.1, 11/98, page 93 of 975 6.1.2 Block Diagram A block diagram of the interrupt controller is shown in figure 6.1. INTM1, INTM0 SYSCR NMIEG1, NMIEG0 NM input Interrupt request NMI input unit Vector number IRQ input IRQ input unit IRQR IEGR IENR Priority determination I, UI CCR Internal interrupt requests CPU ICR Interrupt controller [Legend] IEGR : IRQ edge select register IENR : IRQ enable register IRQR : IRQ status register ICR : Interrupt control register SYSCR : System control register Figure 6.1 Block Diagram of Interrupt Controller Rev. 0.1, 11/98, page 94 of 975 6.1.3 Pin Configuration Table 6.1 summarizes the pins of the interrupt controller. Table 6.1 Interrupt Controller Pins Name Symbol I/O Function Nonmaskable interrupt 10, Input Nonmaskable external interrupt; rising, falling, or both edges can be selected External interrupt request ,54 Input Maskable external interrupts; rising, falling, or both edges can be selected External interrupt requests 1 to 5 ,54 Input Maskable external interrupts: rising, or falling edges can be selected 6.1.4 to ,54 Register Configuration Table 6.2 summarizes the registers of the interrupt controller. Table 6.2 Interrupt Controller Registers Name Abbreviation R/W Initial Value Address*1 System control register SYSCR R/W H'00 H'FFE8 IRQ edge select register IEGR R/W H'00 H'FFF0 IRQ enable register IENR R/W H'00 H'FFF1 H'00 H'FFF2 *2 IRQ status register IRQR R/ (W) Interrupt control register A ICRA R/W H'00 H'FFF3 Interrupt control register B ICRB R/W H'00 H'FFF4 Interrupt control register C ICRC R/W H'00 H'FFF5 Interrupt control register D ICRD R/W H'00 H'FFF6 Port mode register 1 PMR1 R/W H'00 H'FFCE Notes: 1. Lower 16 bits of the address. 2. Only 0 can be written, for flag clearing. Rev. 0.1, 11/98, page 95 of 975 6.2 Register Descriptions 6.2.1 System Control Register (SYSCR) Bit : 7 -- 6 -- 5 INTM1 4 INTM0 3 XRST 2 NMIEG1 1 NMIEG0 0 -- Initial value : 0 -- 0 -- 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 -- R/W : SYSCR is an 8-bit readable register that selects the interrupt control mode and the detected edge for 10,. Only bits 5, 4, 2 and 1 are described here; for details on the other bits, see section 3.2.1, System Control Register (SYSCR). SYSCR is initialized to H'00 by a reset. Bits 5 and 4: Interrupt Control Mode (INTM1, INTM0) These bits select one of two interrupt control modes for the interrupt controller. The INTM1 bit must not be set to 1. Bit 5 Bit 4 Interrupt INTM1 INTM0 Control Mode Description 0 0 0 Interrupts are controlled by I bit (Initial value) 1 1 Interrupts are controlled by I and UI bits and ICR 0 Cannot be used in this LSI 1 Cannot be used in this LSI 1 Bit 2 and 1: 10, Pin Detected Edge Select (NMIEG1, NMIEG0) Selects the detected edge for the 10, pin. Bit 2 Bit 1 NIMIEG1 NIMIEG0 Description 0 0 Interrupt request generated at falling edge of 10, pin 1 Interrupt request generated at rising edge of 10, pin * Interrupt request generated at both falling and rising edges of 10, pin 1 Note: * Don't care Rev. 0.1, 11/98, page 96 of 975 (Initial value) 6.2.2 Interrupt Control Registers A to D (ICRA to ICRD) Bit : 7 ICR7 6 ICR6 5 ICR5 4 ICR4 3 ICR3 2 ICR2 1 ICR1 0 ICR0 Initial value : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W R/W : The ICR registers are four 8-bit readable/writable registers that set the interrupt control level for interrupts other than NMI. The correspondence between ICR settings and interrupt sources is shown in table 6.3. The ICR registers are initialized to H'00 by a reset. Bit 7 to 0: Interrupt Control Level (ICR7 to ICR0) Sets the control level for the corresponding interrupt source. Bit n ICRn Description 0 Corresponding interrupt source is control level 0 (non-priority) 1 Corresponding interrupt source is control level 1 (priority) (Initial value) (n = 7 to 0) Table 6.3 ICRA ICRB ICRC ICRD Correspondence between Interrupt Sources and ICR Settings ICRA7 ICRA6 ICRA5 ICRA4 ICRA3 ICRA2 ICRA1 CIRA0 Reserved Input capture HSW1 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Reserved ICRB7 ICRB6 ICRB5 ICRB4 ICRB3 ICRB2 ICRB1 ICRB0 Reserved Reserved Servo (drum, capstan latch) Timer A Timer B Timer J Timer R Timer L ICRC7 ICRC6 ICRC5 ICRC4 ICRC3 ICRC2 ICRC1 ICRC0 Timer X1 Synchronized detection Watchdog timer Servo IIC SCI1 (UART) SCI2 A/D (with 32-bit buffer) ICRD7 ICRD6 ICRD5 ICRD4 ICRD3 ICRD2 ICRD1 ICRD0 HSW2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Rev. 0.1, 11/98, page 97 of 975 6.2.3 IRQ Enable Register (IENR) Bit : 7 -- 6 -- 5 IRQ5E 4 IRQ4E 3 IRQ3E 2 IRQ2E 1 IRQ1E 0 IRQ0E Initial value : 0 -- 0 -- 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W R/W : IENR is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests IRQ5 to IRQ0. IENR is initialized to H'00 by a reset. Bits 7 and 6: Reserved These bits are reserved. Do not write 1 to them. Bits 5 to 0: IRQ5 to IRQ0 Enable (IRQ5E to IRQ0E) These bits select whether IRQ5 to IRQ0 are enabled or disabled. Bit n IRQnE Description 0 IRQn interrupt disabled 1 IRQn interrupt enabled (Initial value) (n = 5 to 0) Rev. 0.1, 11/98, page 98 of 975 6.2.4 IRQ Edge Select Registers (IEGR) 7 6 5 4 3 -- IRQ5EG IRQ4EG IRQ3EG IRQ2EG Initial value : 0 0 0 0 0 0 0 0 R/W : -- R/W R/W R/W R/W R/W R/W R/W Bit : 2 1 0 IRQ1EG IRQ0EG1 IRQ0EG0 IEGR is an 8-bit readable/writable register that selects detected edge of the input at pins ,54 to ,54. IEGR register is initialized to H'00 by a reset. Bit 7: Reserved This bit is reserved. Do not write 1 to it. Bits 6 to 2: ,54 to ,54 Pins Detected Edge Select (IRQ5EG to IRQ1EG) These bits select detected edge for interrupts IRQ5 to IRQ1. Bits 6 to 2 IRQnEG Description 0 Interrupt request generated at falling edge of ,54Q pin input 1 Interrupt request generated at rising edge of ,54Q pin input (Initial value) (n = 5 to 1) Bits 1 and 0: ,54 Pin Detected Edge Select (IRQ0EG1, IRQ0EG0) These bits select detected edge for interrupt IRQ0. Bit 1 IRQ0EG1 Bit 0 IRQ0EG0 0 0 Interrupt request generated at falling edge of ,54 pin input (Initial value) 0 1 Interrupt request generated at rising edge of ,54 pin input 1 * Interrupt request generated at both falling and rising edges of ,54 pin input Note: * Description Don't care Rev. 0.1, 11/98, page 99 of 975 6.2.5 IRQ Status Register (IRQR) Bit : 7 -- 6 -- 5 IRQ5F 4 IRQ4F 3 IRQ3F 2 IRQ2F 1 IRQ1F 0 IRQ0F Initial value : 0 -- 0 -- 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* R/W : Note: * Only 0 can be written, to clear the flag. IRQR is an 8-bit readable/writable register that indicates the status of IRQ5 to IRQ0 interrupt requests. IRQR is initialized to H'00 by a reset. Bit 7 and 6: Reserved These bits are reserved. Do not write 1 to them. Bits 5 to 0: IRQ5 to IRQ0 Flags These bits indicate the status of IRQ5 to IRQ0 interrupt requests. Bit n IRQnF Description 0 [Clearing conditions] (Initial value) Cleared by reading IRQnF set to 1, then writing 0 in IRQnF When IRQn interrupt exception handling is executed 1 [Setting conditions] (1) When a falling edge occurs in ,54Q input while falling edge detection is set (IRQnEG = 0) (2) When a rising edge occurs in (IRQnEG = 0) ,54Q input while rising edge detection is set (3) When a falling or rising edge occurs in ,54 input while both-edge detection is set (IRQ0EG1 = 1) (n = 5 to 0) Rev. 0.1, 11/98, page 100 of 975 6.2.6 Port Mode Register (PMR1) Bit : Initial value : R/W : 7 PMR17 6 PMR16 5 PMR15 4 PMR14 3 PMR13 2 PMR12 1 PMR11 0 PMR10 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Port Mode Register 1 (PMR1) controls pin function switching-over of port 1. Switching is specified for each bit. PMR1 is an 8-bit readable/writable register and is initialized to H'00 by a reset. Only bits 5 to 0 are explained here. For details, see section 10, I/O Port. Bits 5 to 0: P15/,54 to P10/,54 pin switching (PMR15 to PMR10) These bits are for setting the P1n/,54Q pin as the input pin for P1n or as the ,54Q pin for external interrupt request input. Bit n PMR1n Description 0 P1n/,54Q pin functions as the P1n input/output pin 1 P1n/IRQn pin functions as the ,54Q input/output pin (Initial value) (N = 5 to 0) The following is the notes on switching the pin function by PMR1. (1) When the port is set as the ,& input pin or ,54 to ,54 input pin, the pin level must be High or Low regardless of active mode or power-down mode. Do not set the pin level at Medium. (2) Switching the pin function of P16/,& or P15/,54 to P10/,54 may be mistakenly identified as edge detection and detection signal may be generated. To prevent this, operate as follows: (a) Set the interrupt enable/disable flag to disable before switching the pin function. (b) Clear the applicable interrupt request flag to 0 after switching the pin function and executing another instruction. Rev. 0.1, 11/98, page 101 of 975 (Program example) : MOV.B R0L,@IENR Interrupt disabled MOV.B R1L,@PMR1 Pin function change NOP Optional instruction BCLR m @IRQR Applicable interrupt clear MOV.B R1L,@IENR Interrupt enabled : 6.3 Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ5 to IRQ0) and internal interrupts. 6.3.1 External Interrupts There are seven external interrupt sources; NMI and IRQ5 to IRQ0. Of these, NMI, and IRQ1 to IRQ0 can be used to restore this chip from standby mode. (1) NMI Interrupt NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode and the status of the CPU interrupt mask bits. The NMIEG1 and NMIEG0 bits in SYSCR can be used to select whether an interrupt is requested at a rising, falling edge or both edges on the 10, pin. The vector number for NMI interrupt exception handling is 7. (2) IRQ5 to IRQ0 Interrupts Interrupts IRQ5 to IRQ0 are requested by an input signal at pins ,54 to ,54. Interrupts IRQ5 to IRQ0 have the following features: (a) Using IEGR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pin ,54. (b) Using IEGR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins ,54 to ,54. (c) Enabling or disabling of interrupt requests IRQ5 to IRQ0 can be selected with IENR. (d) The interrupt control level can be set with ICR. (e) The status of interrupt requests IRQ5 to IRQ0 is indicated in IRQR. IRQR flags can be cleared to 0 by software. A block diagram of interrupts IRQ5 to IRQ0 is shown in figure 6.2. Rev. 0.1, 11/98, page 102 of 975 IRQnE IRQnEG IRQnF Edge detection circuit IRQn input S IRQn interrupt request Q R Note: n = 5 to 0 Clear signal Figure 6.2 Block Diagram of Interrupts IRQ5 to IRQ0 Figure 6.3 shows the timing of IRQnF setting. Internal IRQn input pin IRQnF Figure 6.3 Timing of IRQnF Setting The vector numbers for IRQ5 to IRQ0 interrupt exception handling are 21 to 26. Upon detection of IRQ5 to IRQ0 interrupts, the applicable pin is set in the port register 1 (PMR1) as ,54Q pin. Rev. 0.1, 11/98, page 103 of 975 6.3.2 Internal Interrupts There are 33 sources for internal interrupts from on-chip supporting modules. (1) For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. If any one of these is set to 1, an interrupt request is issued to the interrupt controller. (2) The interrupt control level can be set by means of ICR. 6.3.3 Interrupt Exception Vector Table Table 6.4 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Priorities among modules can be set by means of ICR. The situation when two or more modules are set to the same priority, and priorities within a module, are fixed as shown in table 6.4. Table 6.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities (1) Priority Interrupt Source Origin of Interrupt Vector Source No. Vector address ICR High Reset External pin 0 H'0000 to H'0003 Reserved 1 H'0004 to H'0007 2 H'0008 to H'000B 3 H'000C to H'000F 4 H'0010 to H'0013 5 H'0014 to H'0017 Instruction 6 H'0018 to H'001B Direct transition External pin 7 H'001C to H'001F Instruction 8 H'0020 to H'0023 TRAPA#1 9 H'0024 to H'0027 TRAPA#2 10 H'0028 to H'002B TRAPA#3 11 H'002C to H'002F 12 H'0030 to H'0033 13 H'0034 to H'0037 14 H'0038 to H'003B 15 H'003C to H'003F NMI Trap instruction TRAPA#0 Reserved Low Rev. 0.1, 11/98, page 104 of 975 Remarks Table 6.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities (2) Priority Interrupt Source High Address trap #0 Origin of Interrupt Vector Source No. Vector address ICR ATC 16 H'0040 to H'0043 #1 17 H'0044 to H'0047 #2 18 H'0048 to H'004B IC PSU 19 H'004C to H'004F ICRA6 HSW1 Servo circuit 20 H'0050 to H'0053 ICRA5 IRQ0 External pin 21 H'0054 to H'0057 ICRA4 IRQ1 22 H'0058 to H'005B ICRA3 IRQ2 23 H'005C to H'005F ICRA2 IRQ3 24 H'0060 to H'0063 IRQ4 25 H'0064 to H'0067 IRQ5 26 H'0068 to H'006B 27 H'006C to H'006F 28 H'0070 to H'0073 29 H'0074 to H'0077 30 H'0078 to H'007B 31 H'007C to H'007F 32 H'0080 to H'0083 33 H'0084 to H'0087 34 H'0088 to H'008B 35 H'008C to H'008F Reserved Drum latch 1 (speed) Servo circuit Capstan latch 1 (speed) ICRB5 Timer A 36 H'0090 to H'0093 ICRB4 TMBI Timer B 37 H'0094 to H'0097 ICRB3 TMJ1I Timer J 38 H'0098 to H'009B ICRB2 39 H'009C to H'009F 40 H'00A0 to H'00A3 TMR2I 41 H'00A4 to H'00A7 TMR3I 42 H'00A8 to H'00AB 43 H'00AC to H'00AF TMR1I Low ICRA1 TMAI TMJ2I TMLI Timer R Timer L Remarks ICRB1 ICRB0 Rev. 0.1, 11/98, page 105 of 975 Table 6.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities (3) Priority Interrupt Source Origin of Interrupt Vector Source No. Vector address ICR High Timer X1 ICRC7 ICXA 44 H'00B0 to H'00B3 ICXB 45 H'00B4 to H'00B7 ICXC 46 H'00B8 to H'00BB ICXD 47 H'00BC to H'00BF OCX1 48 H'00C0 to H'00C3 OCX2 49 H'00C4 to H'00C7 OVFX 50 H'00C8 to H'00CB VD interrupts Sync signal detection 51 H'00CC to H'00CF ICRC6 Reserved 52 H'00D0 to H'00D3 8-bit interval timer Watchdog timer 53 H'00D4 to H'00D7 ICRC5 CTL Servo circuit 54 H'00D8 to H'00DB ICRC4 Drum latch 2 (speed) 55 H'00DC to H'00DF Capstan latch 2 (speed) 56 H'00E0 to H'00E3 Drum latch 3 (phase) 57 H'00E4 to H'00D7 Capstan latch 3 (phase) 58 H'00E8 to H'00EB IIC 59 H'00EC to H'00EF ICRC3 SCI1 (UART) 60 H'00F0 to H'00F3 ICRC2 RXI 61 H'00F4 to H'00F7 TXI 62 H'00F8 to H'00FB TEI 63 H'00FC to H'00FF 64 H'0100 to H'0103 65 H'0104 to H'0107 IIC SCI1 SCI2 ERI TEI SCI2 ABTI Low ICRC1 A/D conversion end A/D 66 H'0108 to H'010B ICRC0 HSW2 Servo circuit 67 H'010C to H'010F ICRD7 Rev. 0.1, 11/98, page 106 of 975 Remarks 6.4 Interrupt Operation 6.4.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in this LSI differ depending on the interrupt control mode. NMI interrupts and address trap interrupts are accepted at all times except in the reset state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. Table 6.5 shows the interrupt control modes. The interrupt controller performs interrupt control according to the interrupt control mode set by the INTM1 and INTM0 bits in SYSCR, the priorities set in ICR, and the masking state indicated by the I and UI bits in the CPU's CCR. Table 6.5 Interrupt Control Modes SYSCR Interrupt Control Mode INTM1 INTM0 Priority Setting Register Interrupt Mask Bits 0 0 0 ICR I Interrupt mask control is performed by the I bit Priority can be set with ICR 1 ICR I, UI 3-level interrupt mask control is performed by the I and UI bits Priority can be set with ICR 1 Description Figure 6.4 shows a block diagram of the priority decision circuit. Rev. 0.1, 11/98, page 107 of 975 ICR I UI Interrupt acceptance control and 3-level mask control Interrupt source Default priority determination Vector number Interrupt control modes 0 and 1 Figure 6.4 Block Diagram of Interrupt Priority Determination Operation (1) Interrupt Acceptance Control and 3-Level Control In interrupt control modes 0 and 1, interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in CCR, and ICR (control level). Table 6.6 shows the interrupts selected in each interrupt control mode. Table 6.6 Interrupts Selected in Each Interrupt Control Mode Interrupt Mask Bit Interrupt Control Mode I UI Selected Interrupts 0 0 * All interrupts (control level 1 has priority) 1 * NMI and address trap interrupts 0 * All interrupts (control level 1 has priority) 1 0 NMI, address trap and control level 1 interrupts 1 NMI and address trap interrupts 1 Note: * Don't care (2) Default Priority Determination The priority is determined for the selected interrupt, and a vector number is generated. If the same value is set for ICR, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. Interrupt sources with a lower priority than the accepted interrupt source are held pending. Table 6.7 shows operations and control signal functions in each interrupt control mode. Rev. 0.1, 11/98, page 108 of 975 Table 6.7 Operations and Control Signal Functions in Each Interrupt Control Mode Interrupt Acceptance Control, 3-Level Control Setting Interrupt Control Mode INTM1 INTM0 0 0 0 1 1 I UI ICR Default Priority Determination IM PR IM IM PR Legend: : Interrupt operation control performed IM: Used as interrupt mask bit PR: Sets priority : Not used 6.4.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU's CCR, and ICR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1. Control level 1 interrupt sources have higher priority. Figure 6.5 shows a flowchart of the interrupt acceptance operation in this case. (1) If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. (2) When interrupt requests are sent to the interrupt controller, a control level 1 interrupt, according to the control level set in ICR, has priority for selection, and other interrupt requests are held pending. If a number of interrupt requests with the same control level setting are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 6.4 is selected. (3) The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I bit is set to 1, only an NMI or an address trap interrupt is accepted, and other interrupt requests are held pending. (4) When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. (5) The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. (6) Next, the I bit in CCR is set to 1. This disables all interrupts except NMI and address trap. (7) A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. Rev. 0.1, 11/98, page 109 of 975 Program execution state No Interrupt generated? Yes Yes NMI No Yes Address trap interrupt? No Control level 1 interrupt? No Hold pending Yes IC No No IC Yes Yes No HSW1 HSW1 Yes No Yes HSW2 HSW2 Yes Yes I=0 No Yes Save PC and CCR I1 Read vector address Branch to interrupt handling routine Figure 6.5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev. 0.1, 11/98, page 110 of 975 6.4.3 Interrupt Control Mode 1 Three-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by means of the I and UI bits in the CPU's CCR, and ICR. (1) Control level 0 interrupt requests are enabled when the I bit is cleared to 0, and disabled when set to 1. (2) Control level 1 interrupt requests are enabled when the I bit or UI bit is cleared to 0, and disabled when both the I bit and the UI bit are set to 1. For example, if the interrupt enable bit for an interrupt request is set to 1, and H'04, H'00, H'00 and H'00 are set in ICRA, ICRB, ICRC and ICRD respectively, (i.e. IRQ2 interrupt is set to control level 1 and other interrupts to control level 0), the situation is as follows: (1) When I = 0, all interrupts are enabled (Priority order: NMI > IRQ2 > IC > HSW1 > ...) (2) When I = 1 and UI = 0, only NMI, address trap and IRQ2 interrupts are enabled (3) When I = 1 and UI = 1, only NMI and address trap interrupts are enabled Figure 6.6 shows the state transitions in these cases. I0 Only NMI, address trap and IRQ2 interrupts enabled All interrupts enabled I 1, UI 0 I0 Exception handling execution or I 1, UI 1 UI 0 Exception handling execution or UI 1 Only NMI and address trap interrupts enabled Figure 6.6 Example of State Transitions in Interrupt Control Mode 1 Figure 6.7 shows an operation flowchart of interrupt reception. Rev. 0.1, 11/98, page 111 of 975 (1) If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. (2) When interrupt requests are sent to the interrupt controller, a control level 1 interrupt, according to the control level set in ICR, has priority for selection, and other interrupt requests are held pending. If a number of interrupt requests with the same control level setting are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 6.4 is selected. (3) The I bit is then referenced. If the I bit is cleared to 0, the UI bit has no effect. An interrupt request set to interrupt control level 0 is accepted when the I bit is cleared to 0. If the I bit is set to 1, only NMI and address trap interrupts are accepted, and other interrupt requests are held pending. An interrupt request set to interrupt control level 1 has priority over an interrupt request set to interrupt control level 0, and is accepted if the I bit is cleared to 0, or if the I bit is set to 1 and the UI bit is cleared to 0. When both the I bit and the UI bit are set to 1, only NMI and address trap interrupts are accepted, and other interrupt requests are held pending. (4) When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. (5) The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. (6) Next, the I and UI bits in CCR are set to 1. This masks all interrupts except NMI and address trap. (7) A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. Rev. 0.1, 11/98, page 112 of 975 Program execution state No Interrupt generated? Yes Yes NMI No Yes Address trap interrupt? No No Control level 1 interrupt? Hold pending Yes IC No No IC Yes Yes No HSW1 HSW1 Yes Yes HSW2 HSW2 Yes I=0 No Yes No Yes Yes I=0 UI = 0 No No Yes Save PC and CCR I 1, UI 1 Read vector address Branch to interrupt handling routine Figure 6.7 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1 Rev. 0.1, 11/98, page 113 of 975 Rev. 0.1, 11/98, page 114 of 975 Figure 6.8 Interrupt Exception Handling Instruction code (Not executed.) Instruction prefetch address (Not executed.) SP-2 SP-4 (2)(4) (3) (5) (7) (4) (3) Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (1) Instruction prefetch Internal operation Interrupt acceptance (1) Internal data bus Internal write signal Internal read signal Internal address bus Interrupt request signal Interrupt level determination Wait for end of instruction (6) (5) (8) (7) (10)(12) (13) (14) (6)(8) (9)(11) Stack (12) (11) Internal operation (14) (13) Interrupt handling routine instruction prefetch First instruction of interrupt handling routine Interrupt handling routine start address ((13) = (10)(12)) Saved PC and saved CCR Vector address Interrupt handling routine start address (vector address contents) (10) (9) Vector fetch 6.4.4 Interrupt Exception Handling Sequence Figure 6.8 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control 0 is set in advanced mode, and the program area and stack area are in onchip memory. 6.4.5 Interrupt Response Times Table 6.8 shows interrupt response times-the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The symbols used in table 6.8 are explained in table 6.9. Table 6.8 No. 1 Interrupt Response Times Number of States Advanced Mode *1 Interrupt priority determination 3 *2 2 Number of wait states until executing instruction ends 1 to 19+2SI 3 PC, CCR stack save 2Sk 4 Vector fetch 2SI 5 6 *3 Instruction fetch 2SI *4 Internal processing 2 Total (using on-chip memory) Notes: 1. 2. 3. 4. Table 6.9 12 to 32 Two states in case of internal interrupt. Refers to DIVXS instruction. Prefetch after interrupt acceptance and interrupt handling routine prefetch. Internal processing after interrupt acceptance and internal processing after vector fetch. Number of States in Interrupt Handling Routine Execution Object of Access Symbol Internal Memory Instruction fetch SI 1 Branch address read SJ Stack manipulation SK Rev. 0.1, 11/98, page 115 of 975 6.5 Usage Notes 6.5.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared to 0. Figure 6.9 shows an example in which the OCIAE bit in timer X1 TIER is cleared to 0. TIER write cycle by CPU OCIA interrupt exception handling Internal address bus TIER address Internal write signal OCIAE OCFA OCIA interrupt signal Figure 6.9 Contention between Interrupt Generation and Disabling Rev. 0.1, 11/98, page 116 of 975 The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. 6.5.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts except NMI are disabled and the next instruction is always executed. When the I bit or UI bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 6.5.3 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W R4,R4 BNE L1 Rev. 0.1, 11/98, page 117 of 975 Rev. 0.1, 11/98, page 118 of 975 Section 7 ROM 7.1 Overview The H8S/2194 has 128 kbytes of on-chip ROM (flash memory or mask ROM), the H8S/2193 has 112 kbytes, the H8S/2192 has 96 kbytes, and the H8S/2191 has 80 kbytes. The ROM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte and word data in one state, enabling faster instruction fetches and higher processing speed. The flash memory versions of the H8S/2194 can be erased and programmed on-board as well as with a general-purpose PROM programmer. 7.1.1 Block Diagram Figure 7.1 shows a block diagram of the ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'000000 H'000001 H'000002 H'000003 H'01FFFE H'01FFFF Figure 7.1 ROM Block Diagram (H8S/2194) Rev. 0.1, 11/98, page 119 of 975 7.2 Overview of Flash Memory 7.2.1 Features The features of the flash memory are summarized below. * Four flash memory operating modes Program mode Erase mode Program-verify mode Erase-verify mode * Programming/erase methods The flash memory is programmed 32 bytes at a time. Erasing is performed by block erase (in single-block units). When erasing all blocks, the individual blocks must be erased sequentially, individually blocks must be erased sequentially. Block erasing can be performed as required on 1-kbyte, 8-kbyte, 16-kbyte, 28-kbyte, and 32-kbyte blocks. * Programming/erase times The flash memory programming time is 10 ms (typ.) for simultaneous 32-byte programming, equivalent to 300 s (typ.) per byte, and the erase time is 100 ms (typ.) per block. * Reprogramming capability The flash memory can be reprogrammed up to 100 times. * On-board programming modes There are two modes in which flash memory can be programmed/erased/verified on-board: Boot mode User program mode * Automatic bit rate adjustment If data transfer on boot mode, automatic adjustment is possible at host transfer bit rates and MCU's bit rates. * Protect modes There are three protect modes, hardware, software, and error protect, which allow protected status to be designated for flash memory program/erase/verify operations. * Writer mode Flash memory can be programmed/erased in writer mode, using a PROM programmer, as well as in on-board programming mode. Rev. 0.1, 11/98, page 120 of 975 Block Diagram Internal address bus Internal data bus (16 bits) STCR FLMCR1 * Module bus 7.2.2 FLMCR2 * EBR1 EBR2 Bus interface/controller Operating mode FWE pin Mode pin * * Flash memory (128 kbytes) [Legend] : Serial timer control register STCR FLMCR1 : Flash memory control register 1 FLMCR2 : Flash memory control register 2 : Erase block register 1 EBR1 : Erase block register 2 EBR2 Note:* These registers are exclusively used for the flash memory. If you try to read these addresses with the mask ROM version, values read becomes uncertain. Data write is also disabled with the above version. Figure 7.2 Block Diagram of Flash Memory Rev. 0.1, 11/98, page 121 of 975 7.2.3 Flash Memory Operating Modes (1) Mode Transitions When each mode pin and the FWE pin are set in the reset state and a reset-start is executed, the MCU enters one of the operating modes shown in figure 7.3. In user mode, flash memory can be read but not programmed or erased. Flash memory can be programmed and erased in boot mode, user program mode, and writer mode. WE Reset state User program mode RES = 0 RES = 0 0 =0 FWE = 1, MD0 = 0, P12 = P13 = P14 = 1 FWE = 1 SWE = 1 FWE = 0 or SWE = 0 RES or 1 = User mode =0 RE S MD1 F = 1, Boot mode On-board program mode Writer mode Note: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. Figure 7.3 Flash Memory Mode Transitions Rev. 0.1, 11/98, page 122 of 975 (2) On-Board Programming Modes (a) Boot mode 2. Writing control program transfer 1. Initial state The flash memory is in the erased state when the device is shipped. The description here applies to the case where the old program version or data is being rewritten. The user should prepare the programming control program and new application program beforehand in the host. When boot mode is entered, the boot program in this chip (originally incorporated in the chip) is started, and SCI communication check is carried out, and the boot program required for flash memory erasing is automatically transferred to the RAM boot program area. <Host> <Host> Writing control program Writing control program New application program New application program <This LSI> <This LSI> SCI Boot program <Flash memory> <RAM> SCI Boot program <Flash memory> <RAM> Boot program area Application program (old version) Application program (old version) 3. Flash memory initialization 4. Writing new application program The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, entire flash memory erasure is performed, without regard to blocks. The programming control program transferred from the host to RAM by SCI communication is executed, and the new application program in the host is written into the flash memory. <Host> <Host> Writing control program New application program <This LSI> <This LSI> SCI Boot program <Flash memory> <Flash memory> <RAM> Boot program area Flash memory erase SCI Boot program <RAM> Writing control program New application program Program execution state Figure 7.4 Boot Mode Rev. 0.1, 11/98, page 123 of 975 (b) User program mode 1. Initial state 2. Programming/erase control program transfer (1) The FWE assessment program that confirms that the FWE pin has been driven high, and (2) the program that will transfer the programming/erase control program from the flash memory to on-chip RAM should be written into the flash memory by the user beforehand. (3) The programming/erase control program should be prepared in the host or in the flash memory. When the FWE pin is driven high, user software confirms this fact, executes the transfer program in the flash memory, and transfers the programming/erase control program to RAM. <Host> <Host> Programming/erase control program New application program New application program <This LSI> <This LSI> SCI Boot program <Flash memory> SCI Boot program <Flash memory> <RAM> <RAM> FWE assessment program Transfer program FWE assessment program Transfer program Programming/erase control program Application program (old version) Application program (old version) 3. Flash memory initialization 4. Writing new application program The programming/erase control program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. <Host> <Host> New application program <This LSI> <This LSI> SCI Boot program <Flash memory> <RAM> FWE assessment program Transfer program SCI Boot program <RAM> <Flash memory> FWE assessment program Transfer program Programming/erase control program Programming/erase control program New application program Flash memory erase Program execution state Figure 7.5 User Program Mode (Example) Rev. 0.1, 11/98, page 124 of 975 (3) Differences between Boot Mode and User Program Mode Boot Mode User Program Mode Entire memory erase Yes Yes Block erase No Yes Programming control program* Program/program-verify Erase/erase-verify Program/program-verify Note: * To be provided by the user, in accordance with the recommended algorithm. (4) Block Configuration The flash memory is divided into two 32-kbyte blocks, two 8-kbyte blocks, one 16-kbyte block, one 28-kbyte block, and four 1-kbyte blocks. Address H'00000 1 kbyte 1 kbyte 1 kbyte 1 kbyte 28 kbytes 128 kbytes 16 kbytes 8k bytes 8k bytes 32 kbytes 32 kbytes Address H'1FFFF 128-kbyte version Figure 7.6 Flash Memory Block Configuration Rev. 0.1, 11/98, page 125 of 975 7.2.4 Pin Configuration The flash memory is controlled by means of the pins shown in table 7.3. Table 7.3 Flash Memory Pins Pin Name Abbreviation I/O Function Reset 5(6 Input Reset Flash write enable FWE Input Flash program/erase protection by hardware Mode 0 MD0 Input Sets this LSI operating mode Port 12 P12 Input Sets this LSI operating mode when MD0 = 0 Port 13 P13 Input Sets this LSI operating mode when MD0 = 0 Port 14 P14 Input Sets this LSI operating mode when MD0 = 0 Transmit data SO1 Output Serial transmit data output Receive data SI1 Input Serial receive data input 7.2.5 Register Configuration The registers used to control the flash memory when enabled are shown in table 7.4. In order for these registers to be accessed, the FLSHE bit must be set to 1 in STCR. Table 7.4 Flash Memory Registers Register Name Abbreviation Flash memory control register 1 FLMCR1 Flash memory control register 2 Erase block register 1 *5 *5 FLMCR2 *5 EBR1 *5 R/W R/W *2 R/W *2 R/W *2 *2 Erase block register 2 EBR2 R/W Serial timer control register STCR R/W Notes: 1. 2. 3. 4. Initial Value Address*1 *3 H'FFF8 *4 H'FFF9 *4 H'FFFA *4 H'00 H'FFFB H'00 H'FFEE H'00 H'00 H'00 Lower 16 bits of the address. When the FWE bit in FLMCR1 is not set at 1, writes are disabled. When a high level is input to the FWE pin, the initial value is H'80. When a low level is input to the FWE pin, or if a high level is input and the SWE bit in FLMCR1 is not set, these registers are initialized to H'00. 5. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte accesses are valid for these registers, the access requiring 2 states. These registers are exclusively used for the flash memory. If you try to read these addresses with the mask ROM version, values read becomes uncertain. Data write is also disabled with the above version. Rev. 0.1, 11/98, page 126 of 975 7.3 Flash Memory Register Descriptions 7.3.1 Flash Memory Control Register 1 (FLMCR1) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 FWE SWE -- -- EV PV E P --* 0 0 0 0 0 0 0 R R/W -- -- R/W R/W R/W R/W Note: * Determined by the state of the FWE pin. FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE to 1 when FWE = 1. Program mode is entered by setting SWE to 1 when FWE = 1, then setting the PSU bit in FLMCR2, and finally setting the P bit. Erase mode is entered by setting SWE to 1 when FWE = 1, then setting the ESU bit in FLMCR2, and finally setting the E bit. FLMCR1 is initialized by a reset, and in standby mode. Its initial value is H'80 when a high level is input to the FWE pin, and H'00 when a low level is input. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes to the SWE bit in FLMCR1 are enabled only when FWE = 1; writes to the EV and PV bits only when FWE=1 and SWE=1; writes to the E bit only when FWE = 1, SWE = 1, and ESU = 1; and writes to the P bit only when FWE = 1, SWE = 1, and PSU = 1. Bit 7: Flash Write Enable (FWE) Sets hardware protection against flash memory programming/erasing. Bit 7 FWE Description 0 When a low level is input to the FWE pin (hardware-protected state) 1 When a high level is input to the FWE pin Rev. 0.1, 11/98, page 127 of 975 Bit 6: Software Write Enable (SWE) Enables or disables flash memory programming. SWE should be set before setting bits ESU, PSU, EV, PV, E, P, and EB9 to EB0, and should not be cleared at the same time as these bits. Bit 6 SWE Description 0 Writes are disabled 1 Writes are enabled [Setting condition] Setting is available when FWE = 1 is selected (Initial value) Bit 5 and 4: Reserved These bits cannot be modified and are always read as 0. Bit 3: Erase-Verify (EV) Selects erase-verify mode transition or clearing. Do not set the SWE, ESU, PSU, PV, E, or P bit at the same time. Bit 3 EV Description 0 Erase-verify mode cleared 1 Transition to erase-verify mode [Setting condition] Setting is available when FWE = 1 and SWE = 1 are selected (Initial value) Bit 2: Program-Verify (PV) Selects program-verify mode transition or clearing. Do not set the SWE, ESU, PSU, EV, E, or P bit at the same time. Bit 2 PV Description 0 Program-verify mode cleared 1 Transition to program-verify mode [Setting condition] Setting is available when FWE = 1 and SWE = 1 are selected Rev. 0.1, 11/98, page 128 of 975 (Initial value) Bit 1: Erase (E) Selects erase mode transition or clearing. Do not set the SWE, ESU, PSU, EV, PV, or P bit at the same time. Bit 1 E Description 0 Erase mode cleared 1 Transition to erase mode [Setting condition] Setting is available when FWE = 1, SWE = 1, and ESU = 1 are selected (Initial value) Bit 0: Program (P) Selects program mode transition or clearing. Do not set the SWE, PSU, ESU, EV, PV, or E bit at the same time. Bit 0 P Description 0 Program mode cleared 1 Transition to program mode [Setting condition] Setting is available when FWE = 1, SWE = 1, and PSU = 1 are selected 7.3.2 (Initial value) Flash Memory Control Register 2 (FLMCR2) Bit : 7 6 5 4 3 2 1 0 FLER -- -- -- -- -- ESU PSU Initial value : 0 0 0 0 0 0 0 0 R/W : R -- -- -- -- -- R/W R/W FLMCR2 is an 8-bit register that monitors the presence or absence of flash memory program/erase protection (error protection) and performs setup for flash memory program/erase mode. FLMCR2 is initialized to H'00 by a reset, and in hardware standby mode. The ESU and PSU bits are cleared to 0 in software standby mode, hardware protect mode, and software protect mode. Rev. 0.1, 11/98, page 129 of 975 Bit 7: Flash Memory Error (FLER) Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-protection state. Bit 7 FLER Description 0 Flash memory is operating normally Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode (Initial value) 1 An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 7.8.3, Error Protection Bits 6 to 2: Reserved These bits cannot be modified and are always read as 0. Bit 1: Erase Setup (ESU) Prepares for a transition to erase mode. Set this bit to 1 before setting the E bit to 1 in FLMCR1. Do not set the SWE, PSU, EV, PV, E, or P bit at the same time. Bit 1 ESU Description 0 Erase setup cleared 1 Erase setup [Setting condition] When FWE = 1, and SWE = 1 (Initial value) Bit 0: Program Setup (PSU) Prepares for a transition to program mode. Set this bit to 1 before setting the P bit to 1 in FLMCR1. Do not set the SWE, ESU, EV, PV, E, or P bit at the same time. Bit 0 PSU Description 0 Program setup cleared 1 Program setup [Setting condition] When FWE = 1, and SWE = 1 Rev. 0.1, 11/98, page 130 of 975 (Initial value) 7.3.3 Erase Block Registers 1 and 2 (EBR1, EBR2) Bit : 7 6 5 4 3 2 1 0 EBR1 : -- -- -- -- -- -- EB9 EB8 Initial value : 0 0 0 0 0 0 0 0 R/W : -- -- -- -- -- -- R/W R/W Bit : 7 6 5 4 3 2 1 0 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W EBR2 : Initial value : R/W : EBR1 and EBR2 are registers that specify the flash memory erase area block by block; bits 1 and 0 in EBR1 (128-kbyte versions only) and bits 7 to 0 in EBR2 are readable/writable bits. EBR1 and EBR2 are each initialized to H'00 by a reset, in standby mode, when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in FLMCR1 is not set. When a bit in EBR1 or EBR2 is set, the corresponding block can be erased. Other blocks are erase-protected. Set only one bit in EBR1 or EBR2 (more than one bit cannot be set). The flash memory block configuration is shown in table 7.5. Table 7.5 Flash Memory Erase Blocks Block (Size) 128-kbyte Versions Address EB0 (1 kbyte) H'000000 to H'0003FF EB1 (1 kbyte) H'000400 to H'0007FF EB2 (1 kbyte) H'000800 to H'000BFF EB3 (1 kbyte) H'000500 to H'000FFF EB4 (28 kbytes) H'001000 to H'007FFF EB5 (16 kbytes) H'008000 to H'00BFFF EB6 (8 kbytes) H'00C000 to H'00DFFF EB7 (8 kbytes) H'00E000 to H'00FFFF EB8 (32 kbytes) H'010000 to H'017FFF EB9 (32 kbytes) H'018000 to H'01FFFF Rev. 0.1, 11/98, page 131 of 975 7.3.4 Serial/Timer Control Register (STCR) : Bit 7 6 5 4 3 2 1 0 -- IICX IICRST -- FLSHE -- -- -- Initial value : 0 0 0 0 0 0 0 0 R/W : -- R/W R/W -- R/W -- -- -- STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode, and on-chip flash memory (in F-ZTAT versions), and also selects the IIC serial clock frequency. For details on functions not related to on-chip flash memory, see section 24.2.7, Serial/Timer Control Register (STCR), and descriptions of individual modules. If a module controlled by STCR is not used, do not write 1 to the corresponding bit. STCR is initialized to H'00 by a reset. 2 Bits 6 to 5: I C Control (IICX, IICRST) 2 2 These bits control the operation of the I C bus interface. For details, see section 24, I C Bus Interface. Bit 3: Flash Memory Control Register Enable (FLSHE) Setting the FLSHE bit to 1 enables read/write access to the flash memory control registers. If FLSHE is cleared to 0, the flash memory control registers are deselected. In this case, the flash memory control register contents are retained. Bit 3 FLSHE Description 0 Flash memory control registers deselected 1 Flash memory control registers selected Bits 7, 4 and 2 to 0: Reserved Rev. 0.1, 11/98, page 132 of 975 (Initial value) 7.4 On-Board Programming Modes When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 7.6. For a diagram of the transitions to the various flash memory modes, see figure 7.3. Table 7.6 Setting On-Board Programming Modes Mode Pin Mode Name FWE Boot mode 1 User program mode 1 *1 MD0 P12 P13 *2 *2 P14 *2 0 1 1 1 1 Notes: 1. In user program mode, the FWE pin should not be constantly set to 1. Set FWE to 1 to make a transition to user program mode before performing a program/erase/verify operation. 2. Can be used as I/O ports after boot mode is initiated. Rev. 0.1, 11/98, page 133 of 975 7.4.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The channel 1 SCI to be used is set to asynchronous mode. When a reset-start is executed after the MCU's pins have been set to boot mode, the boot program built into the MCU is started and the programming control program prepared in the host is serially transmitted to the MCU via the SCI. In the MCU, the programming control program received via the SCI is written into the programming control program area in on-chip RAM. After the transfer is completed, control branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). The transferred programming control program must therefore include coding that follows the programming algorithm given later. The system configuration in boot mode is shown in figure 7.7, and the boot program mode execution procedure in figure 7.8. This LSI Flash memory Host Write data reception Verify data transmission SI1 SCI1 SO1 Figure 7.7 System Configuration in Boot Mode Rev. 0.1, 11/98, page 134 of 975 On-chip RAM Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate This LSI measures low period of H'00 data transmitted by host This LSI calculates bit rate and sets value in bit rate register After bit rate adjustment, transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00) and transmits one H'55 data byte Upon receiving H'55, this LSI sends part of the boot program to RAM Check flash memory data, and if data has already been written, erase all blocks After confirming that all flash memory data has been erased, this LSI transmits one H'AA data byte to host Host transmits number of user program bytes (N), upper byte followed by lower byte This LSI transmits received number of bytes to host as verify data (echo-back) n=1 Host transmits user program sequentially in byte units This LSI transmits received user program to host as verify data (echo-back) n+1 n Transfer received programming control program to on-chip RAM No n = N? Yes End of transmission Transmit one H'AA data byte to host, and execute programming control program transferred to onchip RAM Note : If a memory cell does not operate normally and cannot be erased, one H'FF byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. Figure 7.8 Boot Mode Execution Procedure Rev. 0.1, 11/98, page 135 of 975 (1) Automatic SCI Bit Rate Adjustment Start bit D0 D1 D2 D3 D4 D5 D6 D7 Low period (9 bits) measured (H'00 data) Stop bit High period (1 or more bits) Figure 7.9 Automatic SCI Bit Rate Adjustment When boot mode is initiated, the MCU measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The MCU calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the MCU. If reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. Depending on the host's transmission bit rate and the MCU's system clock frequency, there will be a discrepancy between the bit rates of the host and the MCU. To ensure correct SCI operation, the host's transfer bit rate should be set to (2400, 4800, or 9600) bps. Table 7.7 shows typical host transfer bit rates and system clock frequencies for which automatic adjustment of the MCU's bit rate is possible. The boot program should be executed within this system clock range. Table 7.7 System Clock Frequencies for which Automatic Adjustment of This LSI Bit Rate is Possible Host Bit Rate System Clock Frequency for which Automatic Adjustment of This LSI Bit Rate is Possible 9600 bps 8 MHz to 10 MHz 4800 bps 4 MHz to 10 MHz 2400 bps 2 MHz to 10 MHz Rev. 0.1, 11/98, page 136 of 975 (2) On-Chip RAM Area Divisions in Boot Mode In boot mode, the 2048-byte area from H'FFEFB0 to H'FFF7AF is reserved for use by the boot program, as shown in figure 7.10. The area to which the programming control program is transferred is H'FFF7B0 to H'FFFFAF (2048 bytes). The boot program area can be used when the programming control program transferred into RAM enters the execution state. A stack area should be set up as required. H'FFEFB0 Boot program area* (2048 bytes) H'FFF7B0 Programming control program area (2048 bytes) H'FFFFAF Note: * The boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to RAM. Note that the boot program reamins stored in this area after a branch is made to the programming control program. Figure 7.10 RAM Areas in Boot Mode Rev. 0.1, 11/98, page 137 of 975 (3) Notes on Use of User Mode: (a) When the chip comes out of reset in boot mode, it measures the low period of the input at the SCI's SI1 pin. The reset should end with SI1 pin high. After the reset ends, it takes about 100 states for the chip to get ready to measure the low period of the SI1 pin input. (b) In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. Boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. (c) Interrupts cannot be used while the flash memory is being programmed or erased. (d) The SI1 and SO1 pins should be pulled up on the board. (e) Before branching to the programming control program (RAM area H'FFF3B0), the chip terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data output pin, SO1, goes to the high-level output state (P21PCR = 1, P21PDR = 1). The contents of the CPU's internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program. The initial values of other on-chip registers are not changed. (f) Boot mode can be entered by making the pin settings shown in table 7.6 and executing a reset-start. *1 When the chip detects the boot mode setting at reset release , it retains that state internally. P12, P13 and P14 can be used as the I/O ports. Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then *1 setting the FWE pin and mode pins, and executing reset release . Boot mode can also be cleared by a WDT overflow reset. If the mode pin input levels are changed in boot mode, the boot mode state will be maintained in the microcomputer, and boot mode continued, unless a reset occurs. However, the FWE pin must not be driven low while the boot program is running or flash *2 memory is being programmed or erased . Notes: 1. Mode pin and FWE pin input must satisfy the mode programming setup time (tMDS = 4 states) with respect to the reset release timing. 2. For further information on FWE application and disconnection, see section 7.9, Flash Memory Programming and Erasing Precautions. Rev. 0.1, 11/98, page 138 of 975 7.4.2 User Program Mode When set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board means of FWE control and supply of programming data, and storing a program/erase control program in part of the program area as necessary. In this mode, the chip starts up in mode 1 and applies a high level to the FWE pin. The flash memory itself cannot be read while the SWE bit is set to 1 to perform programming or erasing, so the control program that performs programming and erasing should be run in on-chip RAM or external memory. Figure 7.11 shows the procedure for executing the program/erase control program when transferred to on-chip RAM. Write the FWE assessment program and transfer program (and the program/erase control program if necessary) beforehand MD0 = 1 Reset start Transfer program/erase control program to RAM Branch to program/erase control program in RAM area FWE = high * Execute program/erase control program (flash memory rewriting) Clear FWE * Branch to flash memory application program Note: Do not apply a constant high level to the FWE pin. Apply a high level to the FWE pin only when the flash memory is programmed or erased. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. * For further information on FWE application and disconnection, see section 7.9, Flash Memory Programming and Erasing Precautions. Figure 7.11 User Program Mode Execution Procedure (Preliminary) Rev. 0.1, 11/98, page 139 of 975 7.5 Programming/Erasing Flash Memory In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by setting the PSU and ESU bits in FLMCR2, and the P, E, PV, and EV bits in FLMCR1. The flash memory cannot be read while being programmed or erased. Therefore, the program that controls flash memory programming/erasing (the programming control program) should be located and executed in on-chip RAM or external memory. Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, EV, PV, E, and P bits in FLMCR1, and the ESU and PSU bits in FLMCR2, is executed by a program in flash memory. 2. When programming or erasing, set FWE to 1 (programming/erasing will not be executed if FWE = 0). 3. Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. 7.5.1 Program Mode Follow the procedure shown in the program/program-verify flowchart in figure 7.12 to write data or programs to flash memory. Performing program operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. Programming should be carried out 32 bytes at a time. Table 28.9 in section 28.2.7, Flash Memory Characteristics lists wait time (x, y, z, , , , and ) after setting or clearing each bit on the flash memory control registers 1 and 2 (FLMCR1 and FLMCR2) and the maximum write count (N). Following the elapse of (x) s or more after the SWE bit is set to 1 in flash memory control register 1 (FLMCR1), 32-byte program data is stored in the program data area and reprogram data area, and the 32-byte data in the reprogram data area written consecutively to the write addresses. The lower 8 bits of the first address written to must be H'00, H'20, H'40, H'60, H'80, H'A0, H'C0, or H'E0. Thirty-two consecutive byte data transfers are performed. The program address and program data are latched in the flash memory. A 32-byte data transfer must be performed even if writing fewer than 32 bytes; in this case, H'FF data must be written to the extra addresses. Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. Set more than (y + z + + ) s as the WDT overflow period. After this, preparation for program mode (program setup) is carried out by setting the PSU bit in FLMCR2, and after the elapse of (y) s or more, the operating mode is switched to program mode by setting the P bit in FLMCR1. The time during which the P bit is set is the flash memory programming time. Make a program setting so that the time for one programming operation is within the range of (z) s. Rev. 0.1, 11/98, page 140 of 975 7.5.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of a given programming time, the programming mode is exited (the P bit in FLMCR1 is cleared, then the PSU bit in FLMCR2 is cleared at least () s later). The watchdog timer is cleared after the elapse of () s or more, and the operating mode is switched to program-verify mode by setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of () s or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least () s after the dummy write before performing this read operation. Next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 7.12) and transferred to the reprogram data area. After 32 bytes of data have been verified, exit programverify mode, wait for at least () s, then clear the SWE bit in FLMCR1. If reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. However, ensure that the program/program-verify sequence is not repeated more than (N) times on the same bits. Rev. 0.1, 11/98, page 141 of 975 Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. START Set SWE bit in FLMCR1 Wait (x) s *5 Store 32-byte program data in program data area and reprogram data area *4 n=1 m=0 Write 32-byte data in RAM reprogram data area consecutively to flash memory *1 Enable WDT Set PSU bit in FLMCR2 Wait (y) s *5 Set P bit in FLMCR1 Start of programming Wait (z) s *5 Clear P bit in FLMCR1 End of programming Wait () s *5 Clear PSU bit in FLMCR2 nn+1 Wait () s *5 Disable WDT Set PV bit in FLMCR1 Wait () s *5 H'FF dummy write to verify address Wait () s *5 Read verify data *2 Increment address Program data = verify data? NO m=1 YES Reprogram data computation *3 Transfer reprogram data to reprogram data area NO RAM End of 32-byte data verification? YES Clear PV bit in FLMCR1 Program data storage area (32 bytes) Wait () s Reprogram data storage area (32 bytes) Notes: *4 *5 NO m = 0? *5 n N? NO YES Clear SWE bit in FLMCR1 YES Clear SWE bit in FLMCR1 End of programming Programming failure 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00, H'20, H'40, H'60, H'80, H'A0, H'C0,, or H'E0. A 32-byte data transfer must be performed even if writing fewer than 32 bytes; in this case, H'FF data must be written to the extra addresses. 2. Verify data is read in 16-bit (word) units. 3. Even in case of the bit which is already-programmed in the 32-byte programming loop, perform additional programming if the bit fails at the next verify. 4. An area for storing program data (32 bytes) and reprogram data (32 bytes) must be provided in RAM. The contents of the latter are rewritten as programming progresses. 5. The values of x, y, z, , , , , and N are explained in section 28.2.7 FLASH Memory Characteristics. Program data 0 Verify data 0 Reprogram data 1 0 1 1 1 0 1 0 1 1 Comments When written data and verify data are matching, no further writing takes place Programming incomplete; reprogram -- Still in erased state; no action Figure 7.12 Program/Program-Verify Flowchart Rev. 0.1, 11/98, page 142 of 975 7.5.3 Erase Mode Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 7.13. Table 28.9 in section 28.2.7, Flash Memory Characteristics lists wait time (x, y, z, , , , and ) after setting or clearing each bit on the flash memory control registers 1 and 2 (FLMCR1 and FLMCR2) and the maximum clearing count (N). To perform data or program erasure, make a 1 bit setting for the flash memory area to be erased in erase block register 1 or 2 (EBR1 or EBR2) at least (x) s after setting the SWE bit to 1 in flash memory control register 1 (FLMCR1). Next, the watchdog timer is set to prevent overerasing in the event of program runaway, etc. Set more than (y + z + + ) ms as the WDT overflow period. After this, preparation for erase mode (erase setup) is carried out by setting the ESU bit in FLMCR2, and after the elapse of (y) s or more, the operating mode is switched to erase mode by setting the E bit in FLMCR1. The time during which the E bit is set is the flash memory erase time. Ensure that the erase time does not exceed (z) ms. Note: With flash memory erasing, preprogramming (setting all data in the memory to be erased to 0) is not necessary before starting the erase procedure. 7.5.4 Erase-Verify Mode In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. After the elapse of the erase time, erase mode is exited (the E bit in FLMCR1 is cleared, then the ESU bit in FLMCR2 is cleared at least () s later), the watchdog timer is cleared after the elapse of () s or more, and the operating mode is switched to erase-verify mode by setting the EV bit in FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of () s or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least () s after the dummy write before performing this read operation. If the read data has been erased (all 1), a dummy write is performed to the next address, and erase-verify is performed. If the read data has not been erased, set erase mode again, and repeat the erase/erase-verify sequence in the same way. However, ensure that the erase/erase-verify sequence is not repeated more than (N) times. When verification is completed, exit erase-verify mode, and wait for at least () s. If erasure has been completed on all the erase blocks, clear the SWE bit in FLMCR1. If there are any unerased blocks, make a 1 bit setting in EBR1 or EBR2 for the flash memory area to be erased, and repeat the erase/eraseverify sequence in the same way. Rev. 0.1, 11/98, page 143 of 975 START *1 Set SWE bit in FLMCR1 Wait (x) s *2 n=1 Set EBR1, EBR2 *4 Enable WDT Set ESU bit in FLMCR2 Wait (y) s *2 Start of erase Set E bit in FLMCR1 *2 Wait (z) ms Halt erase Clear E bit in FLMCR1 Wait () s *2 Clear ESU bit in FLMCR2 Wait () s *2 Disable WDT Set EV bit in FLMCR1 Wait () s *2 nn+1 Set block start address to verify address H'FF dummy write to verify address Wait () s *2 Read verify data *3 Increment address Verify data = all 1? NO YES NO Last address of block? YES Clear EV bit in FLMCR1 Clear EV bit in FLMCR1 Wait () s Wait () s *2 NO End of erasing of all erase blocks? YES Notes: 1. 2. 3. 4. 5. *2 *5 *2 n N? NO YES Clear SWE bit in FLMCR1 Clear SWE bit in FLMCR1 End of erasing Erase failure Preprogramming (setting erase block data to all 0) is not necessary. The values of x, y, z, , , , , and N are explained in section 28.2.7 FLASH Memory Characteristics. Verify data is read in 16-bit (word) units. Set only one bit in EBR1 or EBR2. More than one bit cannot be set. Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially. Figure 7.13 Erase/Erase-Verify Flowchart (Single-Block Erase) Rev. 0.1, 11/98, page 144 of 975 7.6 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 7.6.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Hardware protection is reset by settings in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2). (See table 7.8.) Table 7.8 Hardware Protection Functions Item Description Program Erase FWE pin protection * When a low level is input to the FWE pin, FLMCR1, FLMCR2 (excluding the FLER bit), EBR1, and EBR2 are initialized, and the program/erase-protected state is entered Yes Yes Reset/standby protection * Yes In a reset (including a WDT overflow reset) and in standby mode, FLMCR1, FLMCR2, EBR1, and EBR2 are initialized, and the program/erase-protected state is entered Yes * In a reset via the 5(6 pin, the reset state is not entered unless the 5(6 pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the 5(6 pin low for the 5(6 pulse width specified in the AC characteristics section Rev. 0.1, 11/98, page 145 of 975 7.6.2 Software Protection Software protection can be implemented by setting the SWE bit in FLMCR1 and erase block registers 1 and 2 (EBR1, EBR2). When software protection is in effect, setting the P or E bit in flash memory control register 1 (FLMCR1) does not cause a transition to program mode or erase mode. (See table 7.9.) Table 7.9 Software Protection Functions Item Description Program Erase SWE bit protection * Clearing the SWE bit to 0 in FLMCR1 sets the program/erase-protected state for all blocks (Execute in on-chip RAM or external memory) Yes Yes Block specification protection * Erase protection can be set for individual blocks by settings in erase block registers 1 and 2 (EBR1, EBR2) - Yes * Setting EBR1 and EBR2 to H'00 places all blocks in the erase-protected state Rev. 0.1, 11/98, page 146 of 975 7.6.3 Error Protection In error protection, an error is detected when MCU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. FLER bit setting conditions are as follows: (1) When flash memory is read during programming/erasing (including a vector read or instruction fetch) (2) Immediately after exception handling (excluding a reset) during programming/erasing (3) When a SLEEP instruction (including standby) is executed during programming/erasing Error protection is released only by a reset and in hardware standby mode. Figure 7.14 shows the flash memory state transition diagram. Program mode Erase mode Reset (hardware protection) RES = 0 RD VF PR ER FLER = 0 RD VF PR ER FLER = 0 Er ro ro St ccu an rre db nc y e S RE =0 Error occurrence FLMCR1, FLMCR2, EBR1, EBR2 initialization state RES = 0 Error protection mode RD VF PR ER FLER = 1 Standby mode Standby mode release Error protection mode (standby) RD VF PR ER FLER = 1 FLMCR1, FLMCR2 (except FLER bit), EBR1, EBR2 initialization state RD: Memory read possible VF : Verify-read possible PR : Programming possible ER : Erasing possible RD: Memory read possible VF : Verify-read possible PR : Programming possible ER : Erasing possible Figure 7.14 Flash Memory State Transitions Rev. 0.1, 11/98, page 147 of 975 7.7 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI input is disabled when flash memory is being programmed or erased (when the P or E bit is set in FLMCR1), and while the boot program is executing in boot *1 mode , to give priority to the program or erase operation. There are three reasons for this: (1) Interrupt during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. (2) In the interrupt exception handling sequence during programming or erasing, the vector *2 would not be read correctly , possibly resulting in MCU runaway. (3) If interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. For these reasons, in on-board programming mode alone there are conditions for disabling interrupt, as an exception to the general rule. However, this provision does not guarantee normal erasing and programming or MCU operation. All requests, including NMI input, must therefore be disabled inside and outside the MCU during FWE application. Interrupt is also disabled in the error-protection state while the P or E bit remains set in FLMCR1. Notes: 1. Interrupt requests must be disabled inside and outside the MCU until data write by the write control program is complete. 2. The vector may not be read correctly in this case for the following two reasons: * If flash memory is read while being programmed or erased (while the P or E bit is set in FLMCR1), correct read data will not be obtained (undetermined values will be returned). * If the interrupt entry in the NMI vector table has not been programmed yet, interrupt exception handling will not be executed correctly. Rev. 0.1, 11/98, page 148 of 975 7.8 Flash Memory Writer Mode 7.8.1 Writer Mode Setting Programs and data can be written and erased in writer mode as well as in the on-board programming modes. In writer mode, the on-chip ROM can be freely programmed using a PROM programmer that supports Hitachi microcomputer device type with 128-kbyte on-chip flash memory. Flash memory read mode, auto-program mode, auto-erase mode, and status read mode are supported with these device types. In auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. 7.8.2 Socket Adapters and Memory Map In writer mode, a socket adapter is mounted on the writer programmer. The socket adapter product codes are listed in table 7.10. Figure 7.15 shows the memory map in writer mode. Table 7.10 Socket Adapter Product Codes Product Codes Package Socket Adapter Product Code HD64F2194 112-pin QFP ME2194ESHF1H (MINATO ELECTRONICS INC.) MCU mode This LSI H'000000 Writer mode H'00000 On-chip ROM area H'01FFFF H'1FFFF Figure 7.15 Memory Map in Writer Mode Rev. 0.1, 11/98, page 149 of 975 7.8.3 Writer Mode Operation Table 7.11 shows how the different operating modes are set when using writer mode, and table 7.12 lists the commands used in writer mode. Details of each mode are given below. (1) Memory Read Mode Memory read mode supports byte reads. (2) Auto-Program Mode Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of auto-programming. (3) Auto-Erase Mode Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used to confirm the end of auto-erasing. (4) Status Read Mode Status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the FO6 signal. In status read mode, error information is output if an error occurs. Table 7.11 Settings for Each Operating Mode in Writer Mode Pin Names Mode FWE &( 2( :( FO0 to FO7 FA0 to FA17 Read H or L L L H Data output Ain Output disable H or L L H H Hi-z X H or L L H L Data input Ain H or L L X X Hi-z X Command write Chip disable *1 *3 *2 Notes: 1. Chip disable is not a standby state; internally, it is an operation state. 2. Ain indicates that there is also address input in auto-program mode. 3. For command writes when making a transition to auto-program or auto-erase mode, input a high level to the FWE pin. Rev. 0.1, 11/98, page 150 of 975 Table 7.12 Writer Mode Commands 1st Cycle 2nd Cycle Command Name Number of Cycles Mode Address Data Mode Address Data Memory read mode 1+n write X H'00 Read RA Dout Auto-program mode 129 write X H'40 write WA Din Auto-erase mode 2 write X H'20 write X H'20 Status read mode 2 write X H'71 write X H'71 Notes: 1. In auto-program mode. 129 cycles are required for command writing by a simultaneous 128-byte write. 2. In memory read mode, the number of cycles depends on the number of address write cycles (n). 7.8.4 Memory Read Mode (1) After the end of an auto-program, auto-erase, or status read operation, the command wait state is entered. To read memory contents, a transition must be made to memory read mode by means of a command write before the read is executed. (2) Command writes can be performed in memory read mode, just as in the command wait state. (3) Once memory read mode has been entered, consecutive reads can be performed. (4) After power-on, memory read mode is entered. Table 7.13 AC Characteristics in Memory Read Mode (1) (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Symbol Min Max Unit Command write cycle tnxtc 20 s &( hold time tceh 0 ns &( setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Write pulse width twep 70 ns :( rise time tr 30 ns :( fall time tf 30 ns Notes Rev. 0.1, 11/98, page 151 of 975 Memory read mode Command write ADDRESS ADDRESS STABLE CE OE WE twep tceh tnxtc tces tf tr DATA DATA DATA tdh tds Note: Data is latched on the rising edge of WE. Figure 7.16 Memory Read Mode Timing Waveforms after Command Write Table 7.14 AC Characteristics when Entering Another Mode from Memory Read Mode (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Symbol Min Max Unit Command write cycle tnxtc 20 s &( hold time tceh 0 ns &( setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Write pulse width twep 70 ns :( rise time tr 30 ns :( fall time tf 30 ns Rev. 0.1, 11/98, page 152 of 975 Notes XX mode command write ADDRESS ADDRESS STABLE CE twep tceh tnxtc OE tces WE tf DATA tr H'XX DATA tdh tds Note: Do not enable WE and OE at the same time. Figure 7.17 Timing Waveforms when Entering Another Mode from Memory Read Mode Table 7.15 AC Characteristics in Memory Read Mode (2) (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Symbol Min Max Unit Access time tacc 20 s &( output delay time tce 150 ns 2( output delay time toe 150 ns Output disable delay time tdf 100 ns Data output hold time toh 5 ns ADDRESS ADDRESS STABLE Notes ADDRESS STABLE CE VIL OE tacc VIL VIH WE tacc DATA toh toh DATA DATA Figure 7.18 Timing Waveforms for &(/2( Enable State Read Rev. 0.1, 11/98, page 153 of 975 ADDRESS ADDRESS STABLE ADDRESS STABLE tacc CE tce tce OE toe toe VIH WE tdf tdf tacc DATA DATA DATA toh toh Figure 7.19 Timing Waveforms for &(/2( Clocked Read 7.8.5 Auto-Program Mode (1) AC Characteristics Table 7.16 AC Characteristics in Auto-Program (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Symbol Min Max Unit Command write cycle tnxtc 20 s &( hold time tceh 0 ns &( setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Write pulse width twep 70 ns Status polling start time twsts 1 ms Status polling access time tspa 150 ns Address setup time tas 0 ns Address hold time tah 60 ns Memory write time twrite 1 3000 ms tr 30 ns :( rise time :( fall time tf 30 ns Write setup time tpns 100 ns Write end setup time tpnh 100 ns Rev. 0.1, 11/98, page 154 of 975 Notes FWE tpns tpnh ADDRESS ADDRESS STABLE CE tceh tas tah tnxtc OE tnxtc twep WE FO7 Data transfer 1 byte to 128 bytes tces tf twsts tspa twrite(1 to 3,000 ms) Programming operation end identification signal tr tds tdh Programming normal end identification signal FO6 Programming wait DATA H'40 DATA DATA FO0 to 5 = 0 Figure 7.20 Auto-Program Mode Timing Waveforms (2) Notes on Use of Auto-Program Mode (a) In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out by executing 128 consecutive byte transfers. (b) A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. (c) The lower 8 bits of the transfer address must be H'00 or H'80. If a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. (d) Memory address transfer is performed in the second cycle (figure 7.20). Do not perform transfer after the second cycle. (e) Do not perform a command write during a programming operation. (f) Perform one auto-programming operation for a 128-byte block for each address. Characteristics are not guaranteed for two or more programming operations. (g) Confirm normal end of auto-programming by checking FO6. Alternatively, status read mode can also be used for this purpose (FO7 status polling uses the auto-program operation end identification pin). (h) The status polling FO6 and FO7 pin information is retained until the next command write. Until the next command write is performed, reading is possible by enabling &( and 2(. Rev. 0.1, 11/98, page 155 of 975 7.8.6 Auto-Erase Mode (1) AC Characteristics Table 7.17 AC Characteristics in Auto-Erase Mode (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Symbol Min Max Unit Command write cycle tnxtc 20 s &( hold time tceh 0 ns &( setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Write pulse width twep 70 ns Status polling start time tests 1 ms Status polling access time tspa 150 ns Memory erase time terase 100 40000 ms :( rise time tr 30 ns :( fall time tf 30 ns Erase setup time tens 100 ns Erase end setup time tenh 100 ns Notes FWE tens tenh ADDRESS CE tces tceh tspa OE tests tnxtc twep WE tf tr terase (100 to 40000ms) Erase end identification signal tds FO7 tdh Erase normal end identification signal FO6 DATA CLin DLin H'20 H'20 FO0 to 5 = 0 Figure 7.21 Auto-Erase Mode Timing Waveforms Rev. 0.1, 11/98, page 156 of 975 tnxtc (2) Notes on Use of Erase-Program Mode (a) Auto-erase mode supports only entire memory erasing. (b) Do not perform a command write during auto-erasing. (c) Confirm normal end of auto-erasing by checking FO6. Alternatively, status read mode can also be used for this purpose (FO7 status polling uses the auto-erase operation end identification pin). (d) The status polling FO6 and FO7 pin information is retained until the next command write. Until the next command write is performed, reading is possible by enabling &( and 2(. 7.8.7 Status Read Mode (1) Status read mode is used to identify what type of abnormal end has occurred. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. (2) The return code is retained until a command write for other than status read mode is performed. Table 7.18 AC Characteristics in Status Read Mode (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Symbol Min Max Unit Command write cycle tnxtc 20 s &( hold time tceh 0 ns &( setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Write pulse width twep 70 ns toe 150 ns 2( output delay time tdf 100 ns output delay time tce 150 ns :( rise time tr 30 ns :( fall time tf 30 ns Disable delay time &( Notes Rev. 0.1, 11/98, page 157 of 975 ADDRESS CE tnxtc tce OE tnxtc twep WE tces tf tceh tds DATA tnxtc twep tf tdf toe tceh tces tr tr tds tdh tdh H'71 H'71 DATA Note: FO2 and FO3 are undefined. Figure 7.22 Status Read Mode Timing Waveforms Table 7.19 Status Read Mode Return Commands Pin Name FO7 Attribute FO6 Normal end Command identificaerror tion Initial value 0 0 Indica-tions Normal end: 0 Command error: 1 Abnormal end: 1 FO5 FO4 Programming error 0 FO3 FO2 FO1 Erase error ProgramEffective ming or address erase count error exceeded 0 0 0 0 Count exceeded: 1 Effective address error: 1 0 ProgramErase error: ming error: 1 1 Otherwise: Otherwise: 0 Otherwise: 0 0 Note: FO2 and FO3 are undefined. Rev. 0.1, 11/98, page 158 of 975 FO0 Otherwise: Otherwise: 0 0 7.8.8 Status Polling (1) The FO7 status polling flag indicates the operating status in auto-program or auto-erase mode. (2) The FO6 status polling flag indicates a normal or abnormal end in auto-program or autoerase mode. Table 7.20 Status Polling Output Truth Table Pin Names Internal Operation in Progress Abnormal End Normal End FO7 0 1 0 1 FO6 0 0 1 1 FO0 to FO5 0 0 0 0 Rev. 0.1, 11/98, page 159 of 975 7.8.9 Writer Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the writer mode setup period. After the writer mode setup time, a transition is made to memory read mode. Table 7.21 Command Wait State Transition Time Specifications Item Symbol Min Max Unit Standby release (oscillation stabilization time) tosc1 10 ms Writer mode setup time tbmv 10 ms VCC hold time tdwn 0 ms VCC tosc1 Notes tbmv tdwn Memory read mode Command wait state RES Auto-program mode Auto-erase mode Command Don't care wait state Normal/abnormal end identification FWE Note: Except in auto-program mode and auto-erase mode, drive the FWE input pin low. Figure 7.23 Oscillation Stabilization Time, Boot Program Transfer Time, and Power Supply Fall Sequence Rev. 0.1, 11/98, page 160 of 975 Don't care 7.8.10 Notes On Memory Programming (1) When programming addresses which have previously been programmed, carry out autoerasing before auto-programming. (2) When performing programming using writer mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1. The flash memory is initially in the erased state when the device is shipped by Hitachi. For other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level. 2. Auto-programming should be performed once only on the same address block. Rev. 0.1, 11/98, page 161 of 975 7.9 Flash Memory Programming and Erasing Precautions Precautions concerning the use of on-board programming mode and writer mode are summarized below. (1) Use the Specified Voltages and Timing for Programming and Erasing Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports Hitachi microcomputer device type with 128-kbyte on-chip flash memory. Do not select the HN28F101 setting for the PROM programmer, and only use the specified socket adapter. Incorrect use will result in damaging the device. (2) Powering On and Off Do not apply a high level to the FWE pin until VCC has stabilized. Also, drive the FWE pin low before turning off VCC. When applying or disconnecting VCC, fix the FWE pin low and place the flash memory in the hardware protection state. The power-on and power-off timing requirements should also be satisfied in the event of a power failure and subsequent recovery. (3) FWE Application/Disconnection FWE application should be carried out when MCU operation is in a stable condition. If MCU operation is not stable, fix the FWE pin low and set the protection state. The following points must be observed concerning FWE application and disconnection to prevent unintentional programming or erasing of flash memory: (a) Apply FWE when the VCC voltage has stabilized within its rated voltage range. (b) In boot mode, apply and disconnect FWE during a reset. (c) In user program mode, FWE can be switched between high and low level regardless of the reset state. FWE input can also be switched during program execution in flash memory. (d) Do not apply FWE if program runaway has occurred. (e) Disconnect FWE only when the SWE, ESU, PSU, EV, PV, P, and E bits in FLMCR1 and FLMCR2 are cleared. Make sure that the SWE, ESU, PSU, EV, PV, P, and E bits are not set by mistake when applying or disconnecting FWE. (4) Do Not Apply a Constant High Level to the FWE Pin Apply a high level to the FWE pin only when programming or erasing flash memory. A system configuration in which a high level is constantly applied to the FWE should be avoided. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. Rev. 0.1, 11/98, page 162 of 975 (5) Use the Recommended Algorithm when Programming and Erasing Flash Memory The recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. When setting the P or E bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. (6) Do Not Set or Clear the SWE Bit During Program Execution in Flash Memory Clear the SWE bit before executing a program or reading data in flash memory. When the SWE bit is set, data in flash memory can be rewritten, but flash memory should only be accessed for verify operations (verification during programming/erasing). (7) Do Not Use Interrupts while Flash Memory is Being Programmed or Erased All interrupt requests, including NMI, should be disabled during FWE application to give priority to program/erase operations. (8) Do Not Perform Additional Programming. Erase the Memory before Reprogramming. In on-board programming, perform only one programming operation on a 32-byte programming unit block. In writer mode, too, perform only one programming operation on a 128-byte programming unit block. Programming should be carried out with the entire programming unit block erased. (9) Before Programming, Check that the Chip is Correctly Mounted in the PROM Programmer. Overcurrent damage to the device can result if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned. (10)Do Not Touch the Socket Adapter or Chip During Programming. Touching either of these can cause contact faults and write errors. Rev. 0.1, 11/98, page 163 of 975 Rev. 0.1, 11/98, page 164 of 975 Section 8 RAM 8.1 Overview The H8S/2194, H8S/2193, H8S/2192 and H8S/2191 have 3 kbytes of on-chip high-speed static RAM. The on-chip RAM is connected to the CPU by a 16-bit data bus, enabling both byte data and word data to be accessed in one state. This makes it possible to perform fast word data transfer. 8.1.1 Block Diagram Figure 8.1 shows a block diagram of the on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'FFE3B0 H'FFE3B1 H'FFE3B2 H'FFE3B3 H'FFE3B4 H'FFE3B5 H'FFFFAE H'FFFFAF Figure 8.1 Block Diagram of RAM (H8S/2194) Rev. 0.1, 11/98, page 165 of 975 Rev. 0.1, 11/98, page 166 of 975 Section 9 Clock Pulse Generator 9.1 Overview This LSI has a built-in clock pulse generator (CPG) that generates the system clock (), the bus master clock, and internal clocks. The clock pulse generator consists of a system clock oscillator, a duty adjustment circuit, clock selection circuit, medium-speed clock divider, subclock oscillator, and subclock division circuit. 9.1.1 Block Diagram Figure 9.1 shows a block diagram of the clock pulse generator. Duty adjustment circuit System clock oscillator OSC1 OSC2 /16, /32, /64 w/2, w/4, w/8 or SUB Bus master clock To CPU Mediumspeed clock divider Clock selection circuit SUB X1 Subclock division circuit Subclock oscillator X2 Internal clock To supporting modules Timer A count clock SUB (w/2, w/4, w/8) Figure 9.1 Block Diagram of Clock Pulse Generator 9.1.2 Register Configuration The clock pulse generator is controlled by SBYCR and LPWRCR. Table 9.1 shows the register configuration. Table 9.1 CPG Registers Name Abbreviation R/W Initial Value Address* Standby control register SBYCR R/W H'00 H'FFEA Low-power control register LPWRCR R/W H'00 H'FFEB Note: * Lower 16 bits of the address. Rev. 0.1, 11/98, page 167 of 975 9.2 Register Descriptions 9.2.1 Standby Control Register (SBYCR) 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 -- -- SCK1 SCK0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W -- -- R/W R/W Bit : Initial value : R/W : SBYCR is an 8-bit readable/writable register that performs power-down mode control. Only bits 0 and 1 are described here. For a description of the other bits, see section 4.2.1, Standby Register (SBYCR). SBYCR is initialized to H'00 by a reset. Bits 1 and 0: System Clock Select 1 and 0 (SCK1, SCK0) These bits select the bus master clock for high-speed mode and medium-speed mode. Bit 1 Bit 0 SCK1 SCK0 Description 0 0 Bus master is in high-speed mode 1 Medium-speed clock is /16 0 Medium-speed clock is /32 1 Medium-speed clock is /64 1 Rev. 0.1, 11/98, page 168 of 975 (Initial value) 9.2.2 Low-Power Control Register (LPWRCR) 7 6 5 4 3 2 1 0 DTON LSON NESEL -- -- -- SA1 SA0 0 0 0 0 0 0 0 0 R/W R/W R/W -- -- -- R/W R/W Bit : Initial value : R/W : LPWRCR is an 8-bit readable/writable register that performs power-down mode control. Only bit 1 and 0 is described here. For a description of the other bits, see section 4.2.2, LowPower Control Register (LPWRCR). LPWRCR is initialized to H'00 by a reset. Bits 1 and 0: Subactive Mode Clock Select (SA1, SA0) Selects CPU clock for subactive mode. In subactive mode, writes are disabled. Bit 1 Bit 0 SA1 SA0 Description 0 0 CPU operating clock is w/8 1 CPU operating clock is w/4 * CPU operating clock is w/2 1 Note: * (Initial value) Don't care Rev. 0.1, 11/98, page 169 of 975 9.3 Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 9.3.1 Connecting a Crystal Resonator (1) Circuit Configuration A crystal resonator can be connected as shown in the example in figure 9.2. An AT-cut parallel-resonance crystal should be used. CL1 OSC1 Rf Rf = 1M 20% OSC2 CL2 CL1 = CL2 = 10 to 22pF Figure 9.2 Connection of Crystal Resonator (Example) (2) Crystal Resonator Figure 9.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 9.2 and the same frequency as the system clock (). CL L Rs OSC1 OSC2 C0 AT-cut parallel-resonance type Figure 9.3 Crystal Resonator Equivalent Circuit Table 9.2 Crystal Resonator Parameters Frequency (MHz) 8 10 RSmax () 80 60 COmax (pF) 7 7 Rev. 0.1, 11/98, page 170 of 975 (3) Note on Board Design When a crystal resonator is connected, the following points should be noted. Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. See figure 9.4. When designing the board, place the crystal resonator and its load capacitors as close as possible to the OSC1 and OSC2 pins. Avoid Signal A Signal B This chip CL2 OSC1 Rf OSC2 CL1 Figure 9.4 Example of Incorrect Board Design 9.3.2 External Clock Input (1) Circuit Configuration An external clock signal can be input as shown in the examples in figure 9.5. If the OSC2 pin is left open, make sure that stray capacitance is no more than 10 pF. In example (b), make sure that the external clock is held high in standby mode, subactive mode, subsleep mode, and watch mode. OSC1 OSC2 External clock input Open (a) OSC2 pin left open OSC1 External clock input OSC2 (b) Completely clock input at OSC2 pin Figure 9.5 External Clock Input (Examples) Rev. 0.1, 11/98, page 171 of 975 (2) External Clock The external clock signal should have the same frequency as the system clock (). Table 9.3 and figure 9.6 show the input conditions for the external clock. Table 9.3 External Clock Input Conditions VCC = 4.0 to 5.5 V Item Symbol Min Max Unit Test Conditions External clock input low pulse width tCPL 40 ns Figure 9.6 External clock input high pulse width tCPH 40 ns External clock rise time tCPr 10 ns External clock fall time tCPf 10 ns tCPH tCPL OSC1 tCPr tCPf Figure 9.6 External Clock Input Timing Table 9.4 shows the external clock output settling delay time, and figure 9.7 shows the external clock output settling delay timing. The oscillator and duty adjustment circuit have a function for adjusting the waveform of the external clock input at the OSC1 pin. When the prescribed clock signal is input at the OSC1 pin, internal clock signal output is fixed after the elapse of the external clock output settling delay time (tDEXT). As the clock signal output is not fixed during the tDEXT period, the reset signal should be driven low to maintain the reset state. Rev. 0.1, 11/98, page 172 of 975 Table 9.4 External Clock Output Settling Delay Time (Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = AVSS = 0 V) Item Symbol Min Max Unit Notes External clock output settling delay time tDEXT* 500 s Figure 9.7 Note: * VCC tDEXT includes 20 tCYC of 5(6 pulse width (tRESW). 4.0 V OSC1 (Internal) RES tDEXT* Note: * tDEXT includes 20 tcyc of RES pulse width (tRESW). Figure 9.7 External Clock Output Settling Delay Timing Rev. 0.1, 11/98, page 173 of 975 9.4 Duty Adjustment Circuit When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock (). 9.5 Medium-Speed Clock Divider The medium-speed divider divides the system clock to generate /16, /32, and /64 clocks. 9.6 Bus Master Clock Selection Circuit The bus master clock selection circuit selects the system clock () or one of the medium-speed clocks (/16, /32 or /64) to be supplied to the bus master (CPU), according to the settings of bits SCK2 to SCK0 in SBYCR. Rev. 0.1, 11/98, page 174 of 975 9.7 Subclock Oscillator Circuit 9.7.1 Connecting 32.768 kHz Crystal Resonator When using a subclock, connect a 32.768 kHz crystal resonator to X1 and X2 pins as shown in figure 9.8. For precautions on connecting, see section 9.3.1 (3), Note on Board Design. The subclock input conditions are shown in figure 9.10. C1 X1 X2 C2 C1 = C2 = 15 pF (Typ) Figure 9.8 Connecting a 32.768 kHz Crystal Resonator (Example) Figure 9.9 shows a crystal resonator equivalent circuit. CS Ls Rs X1 X2 C0 C0 = 1.5 pF (Typ) RS = 14 k (Typ) fW = 32.768 kHz Note: Values shown are the reference values. Figure 9.9 32.768 kHz Crystal Resonator Equivalent Circuit Rev. 0.1, 11/98, page 175 of 975 9.7.2 External Clock Input (1) Circuit Configuration When external clock input connect to the X1 pin, and X2 pin should remain open as connection example of figure 9.10. External clock input X1 X2 Open Figure 9.10 Connection Example When Inputting External Clock 9.7.3 When Subclock is not Needed Connect X1 pin to VCC, and X2 pin should remain open as shown in figure 9.11. VCC X1 X2 Open Figure 9.11 Terminal When Subclock is not Needed Rev. 0.1, 11/98, page 176 of 975 9.8 Subclock Waveform Shaping Circuit To eliminate noise in the subclock input from the X1 pin, this circuit samples the clock using a clock obtained by dividing the clock. The sampling frequency is set with the NESEL bit in LPWRCR. For details, see section 4.2.2, Low-Power Control Register (LPWRCR). The clock is not sampled in subactive mode, subsleep mode, or watch mode. 9.9 Notes on the Resonator Resonator characteristics are closely related to the user board design. Perform appropriate TM assessment of resonator connection, mask version and F-ZTAT , by referring to the connection example given in this section. The resonator circuit rate differs depending on the free capacity of the resonator and the execution circuit, so consult with the resonator manufacturer before determination. Make sure the voltage applied to the resonator pin does not exceed the maximum rated voltage. Rev. 0.1, 11/98, page 177 of 975 Rev. 0.1, 11/98, page 178 of 975 Section 10 I/O Port 10.1 Overview 10.1.1 Port Functions This LSI has seven 8-bit I/O ports (including one CMOS high-current port), one 4-bit I/O port, and one 8-bit input port. Table 10.1 shows the functions of each port. Each I/O part a port control register (PCR) that controls an input and output and a port data register (PDR) for storing output data. The input and output can be controlled in a unit of bit. The pin whose peripheral function is used both as an alternative function can set the pin function in a unit of bit by a port mode register (PMR). 10.1.2 Port Input (1) Reading a Port When a general port of PCR = 0 (input) is read, the pin level is read. When a general port of PCR = 1 (output) is read, the value of the corresponding PDR bit is read. When the pins (excluding AN7 to AN0 and RP7 to RP0 pins) set to the peripheral function are read, the results are as given in items (1) and (2) according to the PCR value. (2) Processing Input Pins The general input port or general I/O port is gated by read signals. Unused pins can be left open if they are not read. However, if an open pin is read, a feedthrough current may apply during the read period according to an intermediate level. The read period is about one-state. Relevant ports: P0, P1, P2, P3, P4, P5, P6, P7, P8 When an alternative pin is set to an alternative function other than the general I/O, always set the pin level to a high or low level. If the pin is left open, a feedthrough current applies according to an intermediate level, which adversely affects reliability, causes malfunctions, and in the worst case may damage the pin. Because the PMR is not initialized in low power consumption mode, pay attention to the pin input level after the mode has been shifted to the low power consumption mode. Relevant pins: ,&, ,54 to ,54, SCK1, SCK2, SI1, SI2, &6, FTIA, FTIB, FTIC, FTID, TRIG, TMBI, $'75*, EXCAP, EXTTRG Rev. 0.1, 11/98, page 179 of 975 Table 10.1 Port Functions (1) Port Description Pins Alternative Functions Function Switching Register Port 0 P07 to P00 input-only ports P70/AN7 to P00/AN0 Analog data input channels 7 to 0 PMR0 Port 1 P17 to P10 I/O ports (Built-in MOS pull-up transistors) P17/TMOW Prescalar unit frequency division clock output PMR1 P16/,& Prescalar unit input capture input P15/,54 to P10/,54 External interrupt request input P27/SCK2 SCI2 clock I/O P26/SO2 SCI2 transmit data output Port 2 Port 3 Port 4 Port 5 P27 to P20 I/O ports (Built-in MOS pull-up transistors) P37 to P30 I/O ports (Built-in MOS pull-up transistors) P47 to P40 I/O ports P53 to P50 I/O ports P25/SI2 SCI2 receive data input P24/SCL I C bus interface clock I/O P23/SDA I C bus interface data I/O P22/SCK1 SCI1 clock I/O P21/SO1 SCI1 transmit data output 2 PMR2 ICCR 2 P20/SI1 SCI1 receive data input P37/TMO Timer J timer output P36/BUZZ Timer J buzzer output P35/PWM3 to P32/PWM0 8-bit PWM output P31/STRB SCI2 strobe output P30/&6 SCI2 chip select input SMR SCR PMR3 P47 None P46/FTOB Timer X output compare B output TOCR P45/FTOA Timer X output compare A output P44/FTID Timer X input capture D input P43/FTIC Timer X input capture C input P42/FTIB Timer X input capture B input P41/FTIA Timer X input capture A input P40/PWM14 14-bit PWM output PMR4 P53/TRIG Realtime output port trigger input PMR5 P52/TMBI Timer B event input P51 None P50/$'75* A/D conversion start external trigger input ADTSR Port 6 P67 to P60 I/O ports P67/RP7 to P60/RP0 Realtime output port PMR6 Port 7 P77 to P70 I/O ports P77/PPG7 to P70/PPG0 PPG output PMR7 Port 8 P87 to P80 I/O ports (High-current ports) P87 to P84 None P83/SV2 P82/SV1 Servo monitor output PMR8 P81/EXCAP Capstan external synchronous signal input P80/EXTTRG External trigger signal input Rev. 0.1, 11/98, page 180 of 975 10.1.3 MOS Pull-Up Transistors The MOS pull-up transistors in ports 1 to 3 can be switched on or off by the MOS pull-up select registers 1 to 3 (PUR1 to PUR3) in units of bits. Settings in PUR1 to PUR3 are valid when the pin function is set to an input by PCR1 to PCR3. If the pin function is set to an output, the MOS pull-up transistor is turned off. Figure 10.1 shows the circuit configuration of a pin with a MOS pull-up transistor. When the pin whose peripheral function is used both as an alternative function is set to the alternative output function, the MOS pull-up transistor is turned off. When the pin is set to the alternative input function, the MOS pull-up transistor is controlled according to the PUR setting regardless of PCR. LPWRM PUR VCC VCC PCR PDR VSS Input data LPWRM : Low power consumption mode signal (The MOS pull-up transistor is turned off in reset, standby, and watch modes.) PUR : MOS pull-up select register PCR : Port control register PDR : Port data register Figure 10.1 Circuit Configuration of Pin with MOS Pull-Up Transistor Rev. 0.1, 11/98, page 181 of 975 10.2 Port 0 10.2.1 Overview Port 0 is an 8-bit input-only port. Table 10.2 shows the port 0 configuration. Port 0 consists of pins that are used both as standard input ports (P07 to P00) and analog input channels (AN7 to AN0). It is switched by port mode register 0 (PMR0). Table 10.2 Port 0 Configuration Port Function Alternative Function Port 0 P07 (standard input port) AN7 (analog input channel) P06 (standard input port) AN6 (analog input channel) P05 (standard input port) AN5 (analog input channel) P04 (standard input port) AN4 (analog input channel) P03 (standard input port) AN3 (analog input channel) P02 (standard input port) AN2 (analog input channel) P01 (standard input port) AN1 (analog input channel) P00 (standard input port) AN0 (analog input channel) 10.2.2 Register Configuration Table 10.3 shows the port 0 register configuration. Table 10.3 Port 0 Register Configuration Name Abbrev. R/W Size Initial Value Address* Port mode register 0 PMR0 R/W Byte H'00 H'FFCD Port data register 0 PDR0 R Byte H'FFC0 Note: * Lower 16 bits of the address. Rev. 0.1, 11/98, page 182 of 975 (1) Port Mode Register 0 (PMR0) Bit : Initial value : R/W : 7 PMR07 6 PMR06 5 PMR05 4 PMR04 3 PMR03 2 PMR02 1 PMR01 0 PMR00 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Port mode register 0 (PMR0) controls switching of each pin function of port 0. The switching is specified in a unit of bit. PMR0 is an 8-bit read/write enable register. When reset, PMR0 is initialized to H'00. Bits 7 to 0: P07/AN7 to P00/AN0 Pin Switching (PMR07 to PMR00) PMR07 to PMR00 sets whether the P0n/ANn pin is used as a P0n input pin or an ANn pin for the analog input channel of an A/D converter. Bit n PMR0n Description 0 The P0n/ANn pin functions as a P0n input pin 1 The P0n/ANn pin functions as an ANn input pin (Initial value) (n = 7 to 0) (2) Port Data Register 0 (PDR0) Bit@: Initial value : R/W : 7 PDR07 6 PDR06 5 PDR05 4 PDR04 3 PDR03 2 PDR02 1 PDR01 0 PDR00 -- R -- R -- R -- R -- R -- R -- R -- R Port data register 0 (PDR0) reads the port states. When the corresponding bit of PMR0 is 0 (general input port), the pin state is read if PDR0 is read. When the corresponding bit of PMR0 is 1 (analog input channel), 1 is read if PDR0 is read. PDR0 is an 8-bit read-only register. When PDR0 is reset, its values become undefined. Rev. 0.1, 11/98, page 183 of 975 10.2.3 Pin Functions This section describes the pin functions of port 0 and their selection methods. (1) P07/AN7 to P00/AN0 P07/AN7 to P00/AN0 are switched according to the PMR0n bit of PMR0 as shown below. PMR0n Pin Function 0 P0n input pin 1 ANn input pin (n = 7 to 0) 10.2.4 Pin States Table 10.4 shows the pin 0 states in each operation mode. Table 10.4 Port 0 Pin States Pins Reset Active Sleep Standby Watch Subactive Subsleep PN7/AN7 to P00/AN0 Highimpedance Highimpedance Highimpedance Highimpedance Highimpedance Highimpedance Rev. 0.1, 11/98, page 184 of 975 Highimpedance 10.3 Port 1 10.3.1 Overview Port 1 is an 8-bit I/O port. Table 10.5 shows the port 1 configuration. Port 1 consists of pins that are used both as standard I/O ports (P17 to P10) and frequency division clock output (TMOW), input capture input (,&), or external interrupt request inputs (,54 to ,54). It is switched by port mode register 1 (PMR1) and port control register 1 (PCR1). Port 1 can select the functions of MOS pull-up transistors. Table 10.5 Port 1 Configuration Port Function Alternative Function Port 1 P17 (standard I/O port) TMOW (frequency division clock output) P16 (standard I/O port) ,& P15 (standard I/O port) ,54 (external interrupt request input) P14 (standard I/O port) ,54 (external interrupt request input) P13 (standard I/O port) ,54 (external interrupt request input) P12 (standard I/O port) ,54 (external interrupt request input) P11 (standard I/O port) ,54 (external interrupt request input) P10 (standard I/O port) ,54 (external interrupt request input) 10.3.2 (input capture input) Register Configuration Table 10.6 shows the port 1 register configuration. Table 10.6 Port 1 Register Configuration Name Abbrev. R/W Size Initial Value Address* Port mode register 1 PMR1 R/W Byte H'00 H'FFCE Port control register 1 PCR1 W Byte H'00 H'FFD1 Port data register 1 PDR1 R/W Byte H'00 H'FFC1 MOS pull-up select register 1 PUR1 R/W Byte H'00 H'FFE1 Note: * Lower 16 bits of the address. Rev. 0.1, 11/98, page 185 of 975 (1) Port Mode Register 1 (PMR1) Bit : Initial value : R/W : 7 PMR17 6 PMR16 5 PMR15 4 PMR14 3 PMR13 2 PMR12 1 PMR11 0 PMR10 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Port mode register 1 (PMR1) controls switching of each pin function of port 1. The switching is specified in a unit of bit. PMR1 is an 8-bit read/write enable register. When reset, PMR1 is initialized to H'00. Note the following items when the pin functions are switched by PMR1. (1) If port 1 is set to an ,& input pin and ,54 to ,54 by PMR1, the pin level needs be set to the high or low level regardless of the active mode and low power consumption mode. The pin level must not be set to an intermediate level. (2) When the pin functions of P16/,& and P15/,34 to P10/,54 are switched by PMR1, they are incorrectly recognized as edge detection according to the state of a pin signal and a detection signal may be generated. To prevent this, perform the operation in the following procedure. (a) Before switching the pin functions, inhibit an interrupt enable flag from being interrupted. (b) After having switched the pin functions, clear the relevant interrupt request flag to 0 by a single instruction. (Program Example) : MOV.B ROL,@IENR Interrupt disabled MOV.B R1L,@PMR1 Pin function change NOP Optional instruction BCLR m @IRQR Applicable interrupt clear MOV.B R1L,@IENR Interrupt enabled : Rev. 0.1, 11/98, page 186 of 975 Bit 7: P17/TMOW Pin Switching (PMR17) PMR17 sets whether the P17/TMOW pin is used as a P17 I/O pin or a TMOW pin for the frequency division clock output. Bit 7 PMR17 Description 0 The P17/TMOW pin functions as a P17 I/O pin 1 The P17/TMOW pin functions as a TMOW output pin (Initial value) Bit 6: P16/,& Pin Switching (PMR16) PMR16 sets whether the P16/,& pin as a P16 I/O pin or an ,& pin for the input capture input of the prescalar unit. The ,& pin has a built-in noise cancel circuit. See section 21, Prescalar Unit. Bit 6 PMR16 Description 0 The P16/,& pin functions as a P16 I/O pin 1 The P16/,& pin functions as an,& input pin (Initial value) Bits 5 to 0: P15/,54 to P10/,54 Pin Switching (PMR15 to PMR10) PMR15 to PMR10 set whether the P1n/,54Q pin is used as a P1n I/O pin or an ,54Q pin for the external interrupt request input. Bit n PMR1n Description 0 The P1n/,54Q pin functions as a P1n I/O pin 1 The P1n/,54Q pin functions as an ,54Q input pin (Initial value) (n = 5 to 0) Rev. 0.1, 11/98, page 187 of 975 (2) Port Control Register 1 (PCR1) Bit : Initial value : R/W : 7 PCR17 6 PCR16 5 PCR15 4 PCR14 3 PCR13 2 PCR12 1 PCR11 0 PCR10 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Port control register 1 (PCR1) controls the I/Os of pins P17 to P10 of port 1 in a unit of bit. When PCR1 is set to 1, the corresponding P17 to P10 pins become output pins, and when it is set to 0, they become input pins. When the relevant pin is set to a general I/O by PMR1, settings of PCR1 and PDR1 become valid. PCR1 is an 8-bit write-only register. When PCR1 is read, 1 is read. When reset, PCR1 is initialized to H'00. Bit n PCR1n Description 0 The P1n pin functions as an input pin 1 The P1n pin functions as an output pin (Initial value) (n = 7 to 0) (3) Port Data Register 1 (PDR1) Bit : Initial value : R/W : 7 PDR17 6 PDR16 5 PDR15 4 PDR14 3 PDR13 2 PDR12 1 PDR11 0 PDR10 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Port data register 1 (PDR1) stores the data for the pins P17 to P10 of port 1. When PCR1 is 1 (output), the PDR1 values are directly read if port 1 is read. Accordingly, the pin states are not affected. When PCR1 is 0 (input), the pin states are read if port 1 is read. PDR1 is an 8-bit read/ write enable register. When reset, PDR1 is initialized to H'00. Rev. 0.1, 11/98, page 188 of 975 (4) MOS Pull-Up Select Register 1 (PUR1) Bit : 7 PUR17 6 PUR16 5 PUR15 4 PUR14 3 PUR13 2 PUR12 1 PUR11 0 PUR10 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial value : R/W : MOS pull-up selector register 1 (PUR1) controls the on and off of the MOS pull-up transistor of port 1. Only the pin whose corresponding bit of PCR1 was set to 0 (input) becomes valid. When the corresponding bit of PCR1 is set to 1 (output), the corresponding bit of PUR1 becomes invalid and the MOS pull-up transistor is turned off. PUR1 is an 8-bit read/ write enable register. When reset, PUR1 is initialized to H'00. Bit n PUR1n Description 0 The P1n pin has no MOS pull-up transistor 1 The P1n pin has a MOS pull-up pin (Initial value) (n = 7 to 0) 10.3.3 Pin Functions This section describes the port 1 pin functions and their selection methods. (1) P17/TMOW P17/TMOW is switched as shown below according to the PMR17 bit in PMR1 and the PCR17 bit in PCR1. PMR17 PCR17 Pin Function 0 0 P17 input pin 1 P17 output pin * TMOW output pin 1 (2) P16/,& P16/,& is switched as shown below according to the PMR16 bit in PMR1, the NC on/off bit in prescalar unit control/status register (PCSR), and the PCR16 bit in PCR1. PMR16 PCR16 NC on/off Pin Function 0 0 * P16 input pin 1 1 * P16 output pin 0 1 ,& input pin Noise cancel invalid Noise cancel valid Rev. 0.1, 11/98, page 189 of 975 (3) P15/,54 to P10/,54 P15/,54 to P10/,54 are switched as shown below according to the PMR1n bit in PMR1 and the PCR1n bit in PCR1. PMR1n PCR1n Pin Function 0 0 P1n input pin 1 P1n output pin * ,54Q 1 input pin (n = 5 to 0) Notes: 1. * Don't care. 2. The ,54 to ,54 input pins can select the leading or falling edge as an edge sense (the ,54 pin can select both edges). See section 6.2.4, Edge Select Register (IEGR). 3. ,54 or ,54 can be used as a timer J event input and ,54 can be used as a timer R input capture input. For details, see section 13, "Timer J" or section 15, "Timer R". 10.3.4 Pin States Table 10.7 shows the port 1 pin states in each operation mode. Table 10.7 Port 1 Pin States Pins Reset P17/TMOW HighP16/,& impedance P15/,54 to P10/,54 Active Sleep Standby Watch Subactive Subsleep Operation Holding Highimpedance Highimpedance Operation Holding Note: If the ,& input pin and ,54 to ,54 input pins are set, the pin level need be set to the high or low level regardless of the active mode and low power consumption mode. Note that the pin level must not reach an intermediate level. Rev. 0.1, 11/98, page 190 of 975 10.4 Port 2 10.4.1 Overview Port 2 is an 8-bit I/O port. Table 10.8 shows the port 2 configuration. Port 2 consists of pins that are used both as standard I/O ports (P27 to P20) and SCI clock I/O 2 (SCK1, SCK2), receive data input (SI1, SI2), send data output (SO1, SO2), I C bus interface clock I/O (SCL), or data I/O (SCL). It is switched by port mode register 2 (PRM2), serial mode 2 register (SMR), serial control register 2 (SCR), I C bus control register (ICCR), and port control register (PCR2). Port 2 can select the MOS pull-up function. Table 10.8 Port 2 Configuration Port Function Alternative Function Port 2 P27 (standard I/O port) SCK2 (SCI2 clock I/O) P26 (standard I/O port) SO2 (SCI2 transmit data output) P25 (standard I/O port) SI2 (SCI2 receive data input) P24 (standard I/O port) SCL (I C bus interface clock I/O) P23 (standard I/O port) SDA (I C bus interface data I/O) P22 (standard I/O port) SCK1 (SCI1 clock I/O) P21 (standard I/O port) SO1 (SCI1 transmit data output) P20 (standard I/O port) SI1 (SCI1 receive data input) 10.4.2 2 2 Register Configuration Table 10.9 shows the port 2 register configuration. Table 10.9 Port 2 Register Configuration Name Abbrev. R/W Size Initial Value Address* Port mode register 2 PMR2 R/W Byte H'1E H'FFCF Port control register 2 PCR2 W Byte H'00 H'FFD2 Port data register 2 PDR2 R/W Byte H'00 H'FFC2 MOS pull-up select register 2 PUR2 R/W Byte H'00 H'FFE2 Note: * Lower 16 bits of the address. Rev. 0.1, 11/98, page 191 of 975 (1) Port Mode Register 2 (PMR2) Bit : Initial value : R/W : 7 PMR27 6 PMR26 5 PMR25 4 --- 3 --- 2 --- 1 --- 0 PMR20 0 R/W 0 R/W 0 R/W 1 --- 1 --- 1 --- 1 --- 0 R/W Port mode register 2 (PMR0) controls switching of each pin function of port 2. The switching is specified in a unit of bit. The switching of the P22/SCK1, P21/SO1, and P20/SI1 pin functions is controlled by SMR and SCR. See section 22, SCI1. PMR2 is an 8-bit read/write enable register. When reset, PMR2 is initialized to H'1E. If the SCK1, SCK2, SI1, and SI1 input pins are set, the pin level need be set to the high or low level regardless of the active mode and low power consumption mode. Note that the pin level must not reach an intermediate level Bit 7: P27/SCK2 Pin Switching (PMR27) PMR27 sets whether the P27/SCK2 pin is used as a P27 I/O pin or an SKC2 pin for the SCI2 clock I/O. Bit 7 PMR27 Description 0 The P27/SCK2 pin functions as a P27 I/O pin 1 The P27/SCK2 pin functions as an SCK2 I/O pin (Initial value) Bit 6: P26/SO2 Pin Switching (PMR26) PMR26 sets whether the P26/SO2 pin as a P26 I/O pin or an SO2 pin for the SCI2 send data output. Bit 6 PMR26 Description 0 The P26/SO2 pin functions as a P26 I/O pin 1 The P26/SO2 pin functions as an SO2 input pin Rev. 0.1, 11/98, page 192 of 975 (Initial value) Bit 5: P25/SI2 Pin Switching (PMR25) PMR26 sets whether the P25/SI2 pin as a P25 I/O pin or an SI2 pin for the SCI2 receive data input. Bit 5 PMR25 Description 0 The P25/SI2 pin functions as a P25 I/O pin 1 The P25/SI2 pin functions as an SI2 input pin (Initial value) Bits 4 to 1: Reserved Bits Reserved bits. When the bits are read, 1 is always read. The write operation is invalid. Bit 0: P26/SO2 Pin PMOS Control (PMR20) PMR20 controls the PMOS ON and OFF of the P26/SO2 pin output buffer. Bit 0 PMR20 Description 0 The P26/SO2 pin functions as CMOS output 1 The P26/SO2 pin functions as NMOS open drain output (Initial value) (2) Port Control Register 2 (PCR2) Bit : Initial value : R/W : 7 PCR27 6 PCR26 5 PCR25 4 PCR24 3 PCR23 2 PCR22 1 PCR21 0 PCR20 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Port control register 2 (PCR2) controls the I/Os of pins P27 to P20 of port 2 in a unit of bit. When PCR2 is set to 1, the corresponding P27 to P20 pins become output pins, and when it is set to 0, they become input pins. When the relevant pin is set to a general I/O by PMR1, settings of PCR2 and PDR2 are valid. PCR2 is an 8-bit write-only register. When PCR2 is read, 1 is read. When reset, PCR2 is initialized to H'00. Bit n PCR2n Description 0 The P2n pin functions as an input pin 1 The P2n pin functions as an output pin (Initial value) (n = 7 to 0) Rev. 0.1, 11/98, page 193 of 975 (3) Port Data Register 2 (PDR2) Bit : Initial value : R/W : 7 PDR27 6 PDR26 5 PDR25 4 PDR24 3 PDR23 2 PDR22 1 PDR21 0 PDR20 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Port data register 2 (PDR2) stores the data for the pins P27 to P20 of port 2. When PCR2 is 1 (output), the PDR2 values are directly read if port 2 is read. Accordingly, the pin states are not affected. When PCR2 is 0 (input), the pin states are read if port 2 is read. PDR2 is an 8-bit read/write enable register. When reset, PDR2 is initialized to H'00. (4) MOS Pull-Up Select Register 2 (PUR2) Bit : Initial value : R/W : 7 PUR27 6 PUR26 5 PUR25 4 PUR24 3 PUR23 2 PUR22 1 PUR21 0 PUR20 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W MOS pull-up selector register 2 (PUR2) controls the ON and OFF of the MOS pull-up transistor of port 2. Only the pin whose corresponding bit of PCR1 was set to 0 (input) becomes valid. If the corresponding bit of PCR2 is set to 1 (output), the corresponding bit of PUR2 becomes invalid and the MOS pull-up transistor is turned off. PUR2 is an 8-bit read/write enable register. When reset, PUR2 is initialized to H'00. Bit n PMR2n Description 0 The P2n pin has no MOS pull-up transistor 1 The P2n pin has a MOS pull-up transistor (Initial value) (n = 7 to 0) Rev. 0.1, 11/98, page 194 of 975 10.4.3 Pin Functions This section describes the port 2 pin functions and their selection methods. (1) P27/SCK2 P27/SCK2 is switched as shown below according to the PMR27 bit in PMR2, the PCR27 bit in PCR2, and the SCK2 to SCK0 bits in serial control register 2 (SCR2). PMR27 PCR27 CKS2 to CKS0 Pin Function 0 0 * P27 input pin 1 1 Note: * * P27 output pin Other than 111 SCK2 output pin 111 SCK2 input pin Don't care. (2) P26/SO2 P26/SO2 is switched as shown below according to the PMR26 bit in PMR2 and the PCR26 bit in PCR2. PMR26 PCR26 Pin Function 0 0 P26 input pin 1 P26 output pin * SO2 output pin 1 Note: * Don't care. (3) P25/SI2 P25/SI2 is switched as shown below according to the PMR25 bit in PMR2 and the PCR25 bit in PCR2. PMR25 PCR25 Pin Function 0 0 P25 input pin 1 P25 output pin * SI2 input pin 1 Note: * Don't care. Rev. 0.1, 11/98, page 195 of 975 (4) P24/SCL P24/SCL2 is switched as shown below according to the ICE bit in the I2C bus control register and the PCR24 bit in PCR2. ICE PCR24 Pin Function 0 0 P24 input pin 1 P24 output pin * SCL I/O pin 1 Note: * Don't care. (5) P23/SDA P23/SDA is switched as shown below according to the ICE bit in the I2C bus control register and the PCR23 bit in PCR2. ICE PCR23 Pin Function 0 0 P23 input pin 1 P23 output pin * SDA I/O pin 1 Note: * Don't care. (6) P22/SCK1 P22/SCK1 is switched as shown below according to the PCR22 bit in PCR2, the C/$ bit in SMR, and the CKE1 and CKE0 bits in SCR. CKE1 C/$ CKE0 PCR22 Pin Function 0 0 0 0 P22 input pin 1 P22 output pin * SCK1 output pin 1 1 1 Note: * * * Don't care. Rev. 0.1, 11/98, page 196 of 975 SCK1 input pin (7) P21/SO1 P21/SO1 is switched as shown below according to the PCR21 bit in PCR2 and the TE bit in SCR. TE PCR21 Pin Function 0 0 P21 input pin 1 P21 output pin * SO1 output pin 1 Note: * Don't care. (8) P20/SI1 P20/SI1 is switched as shown below according to the PCR20 bit in PCR2 and the RE bit in SCR. RE PCR20 Pin Function 0 0 P20 input pin 1 P20 output pin * SI1 input pin 1 Note: * 10.4.4 Don't care. Pin States Table 10.10 shows the port 2 pin states in each operation mode. Table 10.10 Port 2 Pin States Pins Reset Active Sleep Standby Watch Subactive Subsleep P27/SCK2 P26/SO2 P25/SI2 P24/SCL P23/SDA P22/SCK1 P21/SO1 P20/SI1 Highimpedance Operation Holding Highimpedance Highimpedance Operation Holding Note: If the SCK1, SCK2, SI1, and SI2 input pins are set, the pin level needs be set to the high or low level regardless of the active mode and low power consumption mode. Note that the pin level must not reach an intermediate level. Rev. 0.1, 11/98, page 197 of 975 10.5 Port 3 10.5.1 Overview Port 3 is an 8-bit I/O port. Table 10.11 shows the port 3 configuration. Port 3 consists of pins that are used both as standard I/O ports (P37 to P30) and timer J timer output (TMO), buzzer output (BUZZ), 8-bit PWN outputs (PWN3 to PWN0), SCI2 strobe output (STRB), or chip select input (&6). It is switched by port mode register 3 (PRM3) and port control register 3 (PCR3). Port 3 can select the MOS pull-up function. Table 10.11 Port 3 Configuration Port Function Alternative Function Port 3 P37 (standard I/O port) TMO (timer J timer output) P36 (standard I/O port) BUZZ (timer J buzzer output) P35 (standard I/O port) PWM3 (8-bit PWM output) P34 (standard I/O port) PWM2 (8-bit PWM output) P33 (standard I/O port) PWM1 (8-bit PWM output) P32 (standard I/O port) PWM0 (8-bit PWM output) P31 (standard I/O port) STRB (SCI2 strobe output) P30 (standard I/O port) &6 10.5.2 (SCI2 chip select input) Register Configuration Table 10.12 shows the port 3 register configuration. Table 10.12 Port 3 Register Configuration Name Abbrev. R/W Size Initial Value Address* Port mode register 3 PMR3 R/W Byte H'00 H'FFD0 Port control register 3 PCR3 W Byte H'00 H'FFD3 Port data register 3 PDR3 R/W Byte H'00 H'FFC3 MOS pull-up select register 3 PUR3 R/W Byte H'00 H'FFE3 Note: * Lower 16 bits of the address. Rev. 0.1, 11/98, page 198 of 975 (1) Port Mode Register 3 (PMR3) Bit : Initial value : R/W : 7 PMR37 6 PMR36 5 PMR35 4 PMR34 3 PMR33 2 PMR32 1 PMR31 0 PMR30 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Port mode register 3 (PMR3) controls switching of each pin function of port 3. The switching is specified in a unit of bit. PMR3 is an 8-bit read/write enable register. When reset, PMR3 is initialized to H'00. If the &6 input pin is set, the pin level need be set to the high or low level regardless of the active mode and low power consumption mode. Note that the pin level must not reach an intermediate level. Bit 7: P37/TMO Pin Switching (PMR37) PMR37 sets whether the P37/TMO pin is used as a P37 I/O pin or a TMO pin for the timer J output timer. Bit 7 PMR37 Description 0 The P37/TMO pin functions as a P37 I/O pin 1 The P37/TMO pin functions as a TMO output pin (Initial value) Note: If the TMO pin is used for remote control sending, a careless timer output pulse may be output when the remote control mode is set after the output has been switched to the TMO output. Perform the switching and setting in the following order. [1] Set the remote control mode. [2] Set the TMJ-1 and 2 counter data of the timer J. [3] Switch the P37/TMO pin to the TMO output pin. [4] Set the ST bit to 1. Bit 6: P36/BUZZ Pin Switching (PMR36) PMR36 sets whether the P36/BUZZ pin as a P36 I/O pin or an BUZZ pin for the timer J buzzer output. For the selection of the BUZZ output, see the "Timer J Control Register (TMJC)". Bit 6 PMR36 Description 0 The P36/BUZZ pin functions as a P36 I/O pin 1 The P36/BUZZ pin functions as a BUZZ output pin (Initial value) Rev. 0.1, 11/98, page 199 of 975 Bits 5 to 2: P35/PWM3 to P32/PWM0 Pin Switching (PMR35 to PMR32) PMR35 to PMR32 set whether the P3n/PWMm pin is used as a P3n I/O pin or a PWMm pin for the 8-bit PWM output. Bit n PMR3n Description 0 The P3n/PWMm pin functions as a P3n I/O pin 1 The P3n/PWMm pin functions as a PWMm output pin (Initial value) (n = 5 to 2, m = 3 to 0) Bit 1: P31/STRB Pin Switching (PMR31) PMR31 sets whether the P31/STRB pin is used as a P31 I/O pin or an STRB pin for the SCI2 strobe output. Bit 1 PMR31 Description 0 The P31/STRB pin functions as a P31 I/O pin 1 The P31/STRB pin functions as an STRB output pin (Initial value) Bit 0: P30/&6 Pin Switching (PMR30) PMR30 sets whether the P30/&6 pin is used as a P30 I/O pin or a &6 pin for the SCI2 chip select input. Bit 0 PMR30 Description 0 The P30/&6 pin functions as a P30 I/O pin 1 The P30/&6 pin functions as a &6 input pin Rev. 0.1, 11/98, page 200 of 975 (Initial value) (2) Port Control Register 3 (PCR3) Bit : Initial value : R/W : 7 PCR37 6 PCR36 5 PCR35 4 PCR34 3 PCR33 2 PCR32 1 PCR31 0 PCR30 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Port control register 3 (PCR3) controls the I/Os of pins P37 to P30 of port 3 in a unit of bit. When PCR3 is set to 1, the corresponding P37 to P30 pins become output pins, and when it is set to 0, they become input pins. When the relevant pin is set to a general I/O by PMR3, settings of PCR3 and PDR3 become valid. PCR3 is an 8-bit write-only register. When PCR3 is read, 1 is read. When reset, PCR3 is initialized to H'00. Bit n PCR3n Description 0 The P3n pin functions as an input pin 1 The P3n pin functions as an output pin (Initial value) (n = 7 to 0) (3) Port Data Register 3 (PDR3) Bit : Initial value : R/W : 7 PDR37 6 PDR36 5 PDR35 4 PDR34 3 PDR33 2 PDR32 1 PDR31 0 PDR30 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Port data register 3 (PDR3) stores the data for the pins P37 to P30 of port 3. When PCR3 is 1 (output), the PDR3 values are directly read if port 3 is read. Accordingly, the pin states are not affected. When PCR3 is 0 (input), the pin states are read if port 3 is read. PDR3 is an 8-bit read/write enable register. When reset, PDR3 is initialized to H'00. Rev. 0.1, 11/98, page 201 of 975 (4) MOS Pull-Up Select Register 3 (PUR3) Bit : 7 PUR37 6 PUR36 5 PUR35 4 PUR34 3 PUR33 2 PUR32 1 PUR31 0 PUR30 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial value : R/W : MOS pull-up selector register 3 (PUR3) controls the ON and OFF of the MOS pull-up transistor of port 3. Only the pin whose corresponding bit of PCR3 was set to 0 (input) becomes valid. If the corresponding bit of PCR3 is set to 1 (output), the corresponding bit of PUR3 becomes invalid and the MOS pull-up transistor is turned off. PUR3 is an 8-bit read/write enable register. When reset, PUR3 is initialized to H'00. Bit n PCR3n Description 0 The P3n pin has no MOS pull-up transistor 1 The P3n pin has a MOS pull-up transistor (Initial value) (n = 7 to 0) 10.5.3 Pin Functions This section describes the port 3 pin functions and their selection methods. (1) P37/TMO P37/TMO is switched as shown below according to the PMR37 bit in PMR3 and the PCR37 bit in PCR3. PMR37 PCR37 Pin Function 0 0 P37 input pin 1 P37 output pin * TMO output pin 1 Note: * Don't care. Rev. 0.1, 11/98, page 202 of 975 (2) P36/BUZZ P36/BUZZ is switched as shown below according to the PMR36 bit in PMR3 and the PCR36 bit in PCR3. PMR36 PCR36 Pin Function 0 0 P36 input pin 1 P36 output pin * BUZZ output pin 1 Note: * Don't care. (3) P35/PWM3 to P32/PWM0 P35/PWM3 to P32/PWM0 are switched as shown below according to the PMR3n bit in PMR3 and the PCR3n bit in PCR3. PMR3n PCR3n Pin Function 0 0 P3n input pin 1 P3n output pin * PWMm output pin 1 (n = 5 to 2, m = 3 to 0) Note: * Don't care. (4) P31/STRB P31/STRB is switched as shown below according to the PMR31 bit in PMR3 and the PCR31 bit in PCR3. PMR31 PCR31 Pin Function 0 0 P31 input pin 1 P31 output pin * STRB output pin 1 Note: * Don't care. (5) P30/&6 P30/&6 is switched as shown below according to the PMR30 bit in PMR3 and the PCR30 bit in PCR3. PMR30 PCR30 Pin Function 0 0 P30 input pin 1 P30 output pin * &6 1 Note: * input pin Don't care. Rev. 0.1, 11/98, page 203 of 975 10.5.4 Pin States Table 10.13 shows the port 3 pin states in each operation mode. Table 10.13 Port 3 Pin States Pins Reset Active Sleep Standby Watch Subactive Subsleep P37/TMO P36/BUZZ P35/PWM3 to P32/PWM0 P31/STRB P30/&6 Highimpedance Operation Holding Highimpedance Highimpedance Operation Holding Note: If the &6 input pin is set, the pin level need be set to the high or low level regardless of the active mode and low power consumption mode. Note that the pin level must not reach an intermediate level. 10.6 Port 4 10.6.1 Overview Port 4 is an 8-bit I/O port. Table 10.14 shows the port 4 configuration. Port 4 consists of pins that are used both as standard I/O ports (P47 to P40) and output compare output (FTOA, FTOB), input capture input (FTIA, FTIB, FTIC, FTID) or 14-bit PWM output (PWM14). It is switched by port mode register 4 (PRM4), timer output compare control register (TOCR), and port control register 4 (PCR4). Table 10.14 Port 4 Configuration Port Function Alternative Function Port 4 P47 (standard I/O port) None P46 (standard I/O port) FTOB (timer X1 output compare output) P45 (standard I/O port) FTOA (timer X1 output compare output) P44 (standard I/O port) FTID (timer X1 input capture input) P43 (standard I/O port) FTIC (timer X1 input capture input) P42 (standard I/O port) FTIB (timer X1 input capture input) P41 (standard I/O port) FTIA (timer X1 input capture input) P40 (standard I/O port) PWM14 (14-bit PWM output) Rev. 0.1, 11/98, page 204 of 975 10.6.2 Register Configuration Table 10.15 shows the port 4 register configuration. Table 10.15 Port 4 Register Configuration Name Abbrev. R/W Size Initial Value Address* Port mode register 4 PMR4 R/W Byte H'FE H'FFDB Port control register 4 PCR4 W Byte H'00 H'FFD4 Port data register 4 PDR4 R/W Byte H'00 H'FFC4 Note: * Lower 16 bits of the address. (1) Port Mode Register 4 (PMR4) Bit : 7 --- 6 --- 5 --- 4 --- 3 --- 2 --- 1 --- 0 PMR40 Initial value : R/W : 1 --- 1 --- 1 --- 1 --- 1 --- 1 --- 1 --- 0 R/W Port mode register 4 (PMR4) controls switching of the P40/PWM14 pin function. The switchings of the P46/FTOB and P45/FTOA functions are controlled by TOCR. See section 16, Timer X1. The FTIA, FTIB, FTIC, and FTID inputs always function. PMR4 is an 8-bit read/write enable register. When reset, PMR4 is initialized to H'FE. Because the FTIA, FTIB, FTIC, and FTID inputs always function, the alternative pin need always be set to the high or low level regardless of the active mode and low power consumption mode. Note that the pin level must not reach an intermediate level (excluding reset, standby, and watch modes). Because the FTIA, FTIB, FTIC, and FTID inputs always function, each input uses the input edge to the alternative general I/O pins P44, P43, P42, and P41 as input signals. Bits 7 to 1: Reserved Bits Reserved bits. When the bits are read, 1 is always read. The write operation is invalid. Bit 0: P40/PWM14 Pin Switching (PMR40) PMR40 sets whether the P40/PWM pin is used as a P40 I/O pin or a PWM14 pin for the 14-bit PWM square wave output. Bit 0 PMR40 Description 0 The P40/PWM14 pin functions as a P40 I/O pin 1 The P40/PWM14 pin functions as a PWM14 output pin (Initial value) Rev. 0.1, 11/98, page 205 of 975 (2) Port Control Register 4 (PCR4) Bit : Initial value : R/W : 7 PCR47 6 PCR46 5 PCR45 4 PCR44 3 PCR43 2 PCR42 1 PCR41 0 PCR40 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Port control register 4 (PCR4) controls the I/Os of pins P47 to P40 of port 4 in a unit of bit. When PCR4 is set to 1, the corresponding P47 to P40 pins become output pins, and when it is set to 0, they become input pins. When the relevant pin is set to a general I/O by PMR4, settings of PCR4 and PDR4 become valid. PCR4 is an 8-bit write-only register. When PCR4 is read, 1 is read. When reset, PCR4 is initialized to H'00. Bit n PCR4n Description 0 The P4n pin functions as an input pin 1 The P4n pin functions as an output pin (Initial value) (n = 7 to 0) (3) Port Data Register 4 (PDR4) Bit : Initial value : R/W : 7 PDR47 6 PDR46 5 PDR45 4 PDR44 3 PDR43 2 PDR42 1 PDR41 0 PDR40 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Port data register 4 (PDR4) stores the data for the pins P47 to P40 of port 4. When PCR4 is 1 (output), the PDR4 values are directly read if port 3 is read. Accordingly, the pin states are not affected. When PCR4 is 0 (input), the pin states are read if port 4 is read. PDR4 is an 8-bit read/write enable register. When reset, PDR4 is initialized to H'00. Rev. 0.1, 11/98, page 206 of 975 10.6.3 Pin Functions This section describes the port 4 pin functions and their selection methods. (1) P47/FTCI P47/FTCI is switched as shown below according to the PCR47 bit in PCR4. PCR47 Pin Function 0 P47 input pin 1 P47 output pin (2) P46/FTOB P46/FTOB is switched as shown below according to the PCR46 bit in PCR4 and the OEB bit in TOCR. OEB PCR46 Pin Function 0 0 P46 input pin 1 P46 output pin * FTOB output pin 1 Note: * Don't care. (3) P45/FTOA P45/FTOA is switched as shown below according to the PCR45 bit in PCR4 and the OEA bit in TOCR. OEA PCR45 Pin Function 0 0 P45 input pin 1 P45 output pin * FTOA output pin 1 Note: * Don't care. (4) P44/FTID P44/FTID is switched as shown below according to the PCR44 bit in PCR4. PCR44 Pin Function 0 P44 input pin 1 P44 output pin FTID input pin Rev. 0.1, 11/98, page 207 of 975 (5) P43/FTIC P43/FTIC is switched as shown below according to the PCR43 bit in PCR4. PCR43 Pin Function 0 P43 input pin 1 P43 output pin FTIC input pin (6) P42/FTIB P42/FTIB is switched as shown below according to the PCR42 bit in PCR4. PCR42 Pin Function 0 P42 input pin 1 P42 output pin FTIB input pin (7) P41/FTIA P41/FTIA is switched as shown below according to the PCR41 bit in PCR4. PCR41 Pin Function 0 P41 input pin 1 P41 output pin FTIA input pin (8) P40/PWM14 P40/PWM14 is switched as shown below according to the PMR40 bit in PMR4 and the PCR40 bit in PCR4. PMR40 PCR40 Pin Function 0 0 P40 input pin 1 P40 output pin * PWM14 input pin 1 Note: * Don't care. Rev. 0.1, 11/98, page 208 of 975 10.6.4 Pin States Table 10.16 shows the port 4 pin states in each operation mode. Table 10.16 Port 4 Pin States Pins Reset Active Sleep Standby Watch Subactive Subsleep P47 P46/FTOB P45/FTOA P44/FTID P43/FTIC P42/FTIB P41/FTIA P40/ PWM14 Highimpedance Operation Holding Highimpedance Highimpedance Operation Holding Note: Because the FTIA, FTIB, FTIC, and FTID inputs always function, the alternative pin need be set to the high or low level regardless of the active mode and low power consumption mode. Note that the pin level must not reach an intermediate level (excluding reset, standby, and watch modes). 10.7 Port 5 10.7.1 Overview Port 5 is a 4-bit I/O port. Table 10.17 shows the port 5 configuration. Port 5 consists of pins that are used both as standard I/O ports (P53 to P50) and realtime output port trigger input (TRIG), timer B event input (TMBI), or A/D conversion start external trigger input ($'75*). It is switched by port mode register 5 (PMR5), A/D trigger select register (ADTSR), and port control register 5 (PCR5). Table 10.17 Port 5 Configuration Port Function Alternative Function Port 5 P53 (standard I/O port) TRIG (realtime output port trigger input) P52 (standard I/O port) TMBI (timer B event input) P51 (standard I/O port) None P50 (standard I/O port) $'75* (A/D conversion start external trigger input) Rev. 0.1, 11/98, page 209 of 975 10.7.2 Register Configuration Table 10.18 shows the port 5 register configuration. Table 10.18 Port 5 Register Configuration Name Abbrev. R/W Size Initial Value Address* Port mode register 5 PMR5 R/W Byte H'F1 H'FFDC Port control register 5 PCR5 W Byte H'F0 H'FFD5 Port data register 5 PDR5 R/W Byte H'F0 H'FFC5 Note: * Lower 16 bits of the address. (1) Port Mode Register 5 (PMR5) Bit : Initial value : R/W : 7 6 5 4 --- --- --- --- 3 PMR53 2 PMR52 1 PMR51 --- 0 1 --- 1 --- 1 --- 1 --- 0 R/W 0 R/W 0 R/W 1 --- Port mode register 5 (PMR5) controls switching of each pin function of port 5 and specifies the edge sense of the timer B event input (TMBI). The switching of the P50/$'75* pin function is controlled by ADTSR. See section 25, A/D Converter. PMR5 is an 8-bit read/write enable register. When reset, PMR5 is initialized to H'F1. If the TRIG, TMBI, and $'75* pin pins are set, the alternative pin need always be set to the high or low level regardless of the active mode and low power consumption mode. Note that the pin level must not reach an intermediate level. Bits 7 to 4: Reserved Bits Reserved bits. When the bits are read, 1 is always read. The write operation is invalid. Bit 3: P53/TRIG Pin Switching (PMR53) PMR53 sets whether the P53/TRIG pin is used as a P53 I/O pin or a TRIG pin for the realtime output port trigger input. Bit 3 PMR53 Description 0 The P53/TRIG pin functions as a P53 I/O pin 1 The P53/TRIG pin functions as a TRIG input pin Rev. 0.1, 11/98, page 210 of 975 (Initial value) Bit 2: P52/TMBI Pin Switching (PMR52) PMR52 sets whether the P52/TMBI pin is used as a P52 I/O pin or a TMBI pin for the timer B event input. Bit 2 PMR52 Description 0 The P52/TMBI pin functions as a P52 I/O pin 1 The P52/TMBI pin functions as a TMBI input pin (Initial value) Bit 1: Timer B event input edge select (PMR51) PMR51 selects the input edge sense of the TMBI pin. Bit 1 PMR51 Description 0 The timer B event input detects the falling edge 1 The timer B event input detects the rising edge (Initial value) Bit 0: Reserved Bit Reserved bit. When the bit is read, 1 is always read. The write operation is invalid. Rev. 0.1, 11/98, page 211 of 975 (2) Port Control Register 5 (PCR5) Bit : 7 --- 6 --- 5 --- 4 --- 3 PCR53 2 PCR52 1 PCR51 0 PCR50 Initial value : R/W : 1 --- 1 --- 1 --- 1 --- 0 W 0 W 0 W 0 W Port control register 5 (PCR5) controls the I/Os of pins P53 to P50 of port 5 in a unit of bit. When PCR5 is set to 1, the corresponding P53 to P50 pins become output pins, and when it is set to 0, they become input pins. When the relevant pin is set to a general I/O, settings of PCR5 and PDR5 are valid. PCR5 is an 8-bit write-only register. When PCR5 is read, 1 is read. When reset, PCR5 is initialized to H'F0. Bits 7 to 4 are reserved bits. Bit n PCR5n Description 0 The P5n pin functions as an input pin 1 The P5n pin functions as an output pin (Initial value) (n = 3 to 0) (3) Port Data Register 5 (PDR5) Bit : 7 --- 6 --- 5 --- 4 --- 3 PDR53 2 PDR52 1 PDR51 0 PDR50 Initial value : R/W : 1 --- 1 --- 1 --- 1 --- 0 R/W 0 R/W 0 R/W 0 R/W Port data register 5 (PDR5) stores the data for the pins P53 to P50 of port 5. When PCR5 is 1 (output), the PDR5 values are directly read if port 5 is read. Accordingly, the pin states are not affected. When PCR5 is 0 (input), the pin states are read if port 5 is read. PDR5 is an 8-bit read/write enable register. When reset, PDR5 is initialized to H'F0. Bits 7 to 4 are reserved bits. Rev. 0.1, 11/98, page 212 of 975 10.7.3 Pin Functions This section describes the port 5 pin functions and their selection methods. (1) P53/TRIG P53/TRIG is switched as shown below according to the PMR53 bit in PMR5 and the PCR53 bit in PCR5. PMR53 PCR53 Pin Function 0 0 P53 input pin 1 P53 output pin * TRIG input pin 1 Note: * Don't care. (2) P52/TMBI P52/TMBI is switched as shown below according to the PMR52 bit in PMR5 and the PCR52 bit in PCR5. PMR52 PCR52 Pin Function 0 0 P52 input pin 1 P52 output pin * TMBI input pin 1 Note: * Don't care. (3) P51 P51 is switched as shown below according to the PCR51 bit in PCR5. PCR51 Pin Function 0 P51 input pin 1 P51 output pin (4) P50/$'75* P50/$'75* is switched as shown below according to the PCR50 bit in PCR5 and the TRGS1 and TRG0 bits in ADTSR. TRGS1, TRGS0 PCR31 Pin Function Other than 11 0 P50 input pin 1 P50 output pin * $'75* 11 Note: * input pin Don't care. Rev. 0.1, 11/98, page 213 of 975 10.7.4 Pin States Table 10.19 shows the port 5 pin states in each operation mode. Table 10.19 Port 3 Pin States Pins Reset Active Sleep Standby Watch Subactive Subsleep P53/TRIG P52/TMBI P51 P50/ Highimpedance Operation Holding Highimpedance Highimpedance Operation Holding $'57* Note: If the TRIG, TMBI, and $'75* input pins are set, the alternative pin need always be set to the high or low level regardless of the active mode and low power consumption mode. Note that the pin level must not reach an intermediate level. 10.8 Port 6 10.8.1 Overview Port 6 is an 8-bit I/O port. Table 10.20 shows the port 6 configuration. Port 6 consists of pins that are used both as standard I/O ports (P67 to P60) and realtime output ports (RP7 to RP0). It is switched by port mode register 6 (PMR6) and port control register 6 (PCR6). The realtime output function can instantaneously switch the output data by an external or internal trigger input. Table 10.20 Port 6 Configuration Port Function Alternative Function Port 6 P67 (standard I/O port) RP7 (realtime output port pin) P66 (standard I/O port) RP6 (realtime output port pin) P65 (standard I/O port) RP5 (realtime output port pin) P64 (standard I/O port) RP4 (realtime output port pin) P63 (standard I/O port) RP3 (realtime output port pin) P62 (standard I/O port) RP2 (realtime output port pin) P61 (standard I/O port) RP1 (realtime output port pin) P60 (standard I/O port) RP0 (realtime output port pin) Rev. 0.1, 11/98, page 214 of 975 10.8.2 Register Configuration Table 10.21 shows the port 6 register configuration. Table 10.21 Port 6 Register Configuration Name Abbrev. R/W Size Initial Value Address* Port mode register 6 PMR6 R/W Byte H'00 H'FFDD Port control register 6 PCR6 W Byte H'00 H'FFD6 Port data register 6 PDR6 R/W Byte H'00 H'FFC6 Realtime output trigger select register RTPSR R/W Byte H'00 H'FFE5 Realtime output trigger edge RTPEGR select register R/W Byte H'FC H'FFE4 Port control register slave 6 PCRS6 Byte H'00 Port data register slave 6 Byte H'00 Note: * PDRS6 Lower 16 bits of the address. (1) Port Mode Register 6 (PMR6) Bit : Initial value : R/W : 7 PMR67 6 PMR66 5 PMR65 4 PMR64 3 PMR63 2 PMR62 1 PMR61 0 PMR60 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Port mode register 6 (PMR6) controls switching of each pin function of port 6. The switching is specified in units of bits. PMR6 is an 8-bit read/write enable register. When reset, PMR6 is initialized to H'00. Bits 7 to 0: P67/RP7 to P60/RP0 Pin Switching (PMR67 to PMR60) PMR67 to PMR60 set whether the P6n/RPn pin is used as a P6n I/O pin or an RPn pin for the realtime output port. Bit n PMR6n Description 0 The P6n/RPn pin functions as a P6n I/O pin 1 The P6n/RPn pin functions as an RPn output pin (Initial value) (n = 7 to 0) Rev. 0.1, 11/98, page 215 of 975 (2) Port Control Register 6 (PCR6) Bit : 7 PCR67 6 PCR66 5 PCR65 4 PCR64 3 PCR63 2 PCR62 1 PCR61 0 PCR60 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Initial value : R/W : Port control register 6 (PCR6) selects the general I/O of port 6 and controls the realtime output in a unit of bit together with PMR6. When PMR6 = 0, the corresponding P67 to P60 pins become general output pins if PCR6 is set to 1, and they become general input pins if it is set to 0. When PMR6 = 1, PCR6 controls the corresponding RP7 to RP0 realtime output pins. For details, see section 10.8.4, Operation. PCR6 is an 8-bit write-only register. When PCR6 is read, 1 is read. When reset, PCR6 is initialized to H'00. PMR6 PCR6 Bit n Bit n PMR6n PCR6n Description 0 0 The P6n/RPn pin functions as a P6n general I/O input pin (Initial value) 1 The P6n/RPn pin functions as a P6n general output pin * The P6n/RPn pin functions as an RPn realtime output pin 1 Note: * Don't care. (n = 7 to 0) (3) Port Data Register 6 (PDR6) Bit : Initial value : R/W : 7 PDR67 6 PDR66 5 PDR65 4 PDR64 3 PDR63 2 PDR62 1 PDR61 0 PDR60 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Port data register 6 (PDR6) stores the data for the pins P67 to P60 of port 6. For PMR6 = 0, when PCR6 is 1 (output), the PDR6 values are directly read if port 6 is read. Accordingly, the pin states are not affected. When PCR6 is 0 (input), the pin states are read if port 6 is read. For PMR6 = 1, port 6 becomes a realtime output pin. For details, see section 10.8.4, Operation. PDR6 is an 8-bit read/write enable register. When reset, PDR6 is initialized to H'00. Rev. 0.1, 11/98, page 216 of 975 (4) Realtime Output Trigger Select Register (RTPSR) Bit : 7 RTPSR7 6 RTPSR6 5 RTPSR5 4 RTPSR4 3 RTPSR3 2 RTPSR2 1 RTPSR1 0 RTPSR0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Initial value : R/W : The realtime output trigger select register (RTPSR) sets whether the external trigger (TRIG pin input) or the internal trigger (HSW) is used as an trigger input for the realtime output in a unit of bit. For the internal trigger HSW, see section 27.4, HSW Timing Generation Circuit. RTPSR is an 8-bit read/write enable register. When reset, RTPSR is initialized to H'00. Bit n RTPSRn Description 0 Selects the external trigger (TRIG pin input) as a trigger input 1 Selects the internal trigger (HSW) a trigger input (Initial value) (n = 7 to 0) (5) Real Time Output Trigger Edge Select Register (RTPEGR) Bit : 7 --- 6 --- 5 --- 4 --- 3 --- 2 --- Initial value : R/W : 1 --- 1 --- 1 --- 1 --- 1 --- 1 --- 1 0 RTPEGR1 RTPEGR0 0 R/W 0 R/W The realtime output trigger edge select register (RTPEGR) specifies the edge sense of the external or internal trigger input for the realtime output. RTPEGR is an 8-bit read/write enable register. When reset, RTPEGR is initialized to H'FC. Bits 7 to 2: Reserved Bits Reserved bits. When the bits are read, 1 is always read. The write operation is invalid. Bits 1 and 0: Realtime Output Trigger Edge Select (RTPEGR1, RTPEGR0) RTPEGR1 and RTPEGR0 select the edge sense of the external or internal trigger input for the realtime output. Bit 1 Bit 0 RTPEGR1 RTPEGR0 Description 0 0 Inhibits a trigger input 1 Selects the rising edge of a trigger input 0 Selects the falling edge of a trigger input 1 Selects both the leading and falling edges of a trigger input 1 (Initial value) Rev. 0.1, 11/98, page 217 of 975 10.8.3 Pin Functions This section describes the port 6 pin functions and their selection methods. (1) P67/RP7 to P60/RP0 P67/RP7 to P60/RP0 are switched as shown below according to the PMR6n bit in PMR6 and the PCR6n bit in PCR6. PMR6n PCR6n Pin Function Output Value Value When PDR6n was read 0 0 P6n input pin P6n pin 1 P6n output pin PDR6n PDR6n 0 RPn output pin High-impedance* 1 1 Note: * PDRS6n* When PMR6n = 1 (realtime output pin), indicates the state after the PCR6n setup value has been transferred to PCRS6n by a trigger input. (n = 7 to 0) Rev. 0.1, 11/98, page 218 of 975 10.8.4 Operation Port 6 can be used as a realtime output port or general I/O output port by PMR6. Port 6 functions as a realtime output port when PMR6 = 1 and as a general I/O port when PMR6 = 0. The operation per port 6 function is shown below. (See figure 10.2.) RTPEGR write Internal trigger HSW External trigger TRIG CK RTPEGR Selection circuit RTPSR write CK RTPSR Internal data bus RMR6 write CK RMR6 RDR6 write CK CK RDR6 P6/RP RDRS6 RDR6 read Selection circuit RCR6 write CK CK RCR6 RCRS6 [Legend] PMR6 : Port mode register 6 RTPSR : Realtime output trigger select register PCR6 : Port control register 6 RTPEGR : Realtime output trigger edge select register PDR6 : Port data register 6 HSW : Internal trigger signal PCRS6 : Port control register slave 6 TRIG : External trigger pin PDRS6 : Port data register slave 6 Figure 10.2 Port 6 Function Block Diagram Rev. 0.1, 11/98, page 219 of 975 (1) Operation of the Realtime Output Port (PMR6 = 1) When PMR6 is 1, it operates as a realtime output port. When a trigger is input, PMR6 transfers the PDR6 data to PDRS6 and the PCR6 data to PCRS6, respectively. In this case, when PCRS6 is 1, the PDRS6 data of the corresponding bit is output to the RP pin. When PCRS6 is 0, the RP pin of the corresponding bit is output to the high-impedance state. In other words, the pin output state (High or Low) or high-impedance state can instantaneously be switched by a trigger input. Adversely, when PDR6 is read, the PDR6 values are read regardless of the PCR6 and PCRS6 values. (2) Operation of the general I/O port (PMR6 = 0) When PMR6 is 0, it operates as a general I/O port. When data is written to PDR6, the same data is also written to PDRS6. Accordingly, because both PDR6 and PDRS6 and both PCR6 and PCRS6 can be handled as one register, respectively, they can be used in the same way as a normal general I/O port. In other words, if PCR6 is 1, the PDR6 data of the corresponding bit is output to the P6 pin. If PCR6 is 0, the P6 pin of the corresponding bit becomes an input. Adversely, assuming that PDR6 is read, the PDR6 values are read when PCR6 is 1 and the pin values are read when PCR6 is 0. 10.8.5 Pin States Table 10.22 shows the port 6 pin states in each operation mode. Table 10.22 Port 6 Pin States Pins Reset Active Sleep Standby Watch Subactive Subsleep P67/RP7 to P60/RP0 Highimpedance Operation Holding Highimpedance Highimpedance Operation Rev. 0.1, 11/98, page 220 of 975 Holding 10.9 Port 7 10.9.1 Overview Port 7 is an 8-bit I/O port. Table 10.23 shows the port 7 configuration. Port 7 consists of pins that are used both as standard I/O ports (P77 to P70) and HSW timing generation circuit (programmable pattern generator: PPG) outputs (PPG7 to PPG0). It is switched by port mode register 7 (PMR7) and port control register 7 (PCR7). For the programmable generator (PPG), see section 27.4, HSW Timing Generation Circuit. Table 10.23 Port 7 Configuration Port Function Alternative Function Port 7 P77 (standard I/O port) PPG7 (HSW timing output) P76 (standard I/O port) PPG6 (HSW timing output) P75 (standard I/O port) PPG5 (HSW timing output) P74 (standard I/O port) PPG4 (HSW timing output) P73 (standard I/O port) PPG3 (HSW timing output) P72 (standard I/O port) PPG2 (HSW timing output) P71 (standard I/O port) PPG1 (HSW timing output) P70 (standard I/O port) PPG0 (HSW timing output) 10.9.2 Register Configuration Table 10.24 shows the port 7 register configuration. Table 10.24 Port 7 Register Configuration Name Abbrev. R/W Size Initial Value Address* Port mode register 7 PMR7 R/W Byte H'00 H'FFDE Port control register 7 PCR7 W Byte H'00 H'FFD7 Port control register 7 PDR7 R/W Byte H'00 H'FFC7 Note: * Lower 16 bits of the address. Rev. 0.1, 11/98, page 221 of 975 (1) Port Mode Register 7 (PMR7) Bit : Initial value : R/W : 7 PMR77 6 PMR76 5 PMR75 4 PMR74 3 PMR73 2 PMR72 1 PMR71 0 PMR70 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Port mode register 7 (PMR7) controls switching of each pin function of port 7. The switching is specified in a unit of bit. PMR7 is an 8-bit read/write enable register. When reset, PMR7 is initialized to H'00. Bits 7 to 0: P77/PPG7 to P70/PPG0 Pin Switching (PMR77 to PMR70) PMR77 to PMR70 set whether the P7n/PPGn pin is used as a P7n I/O pin or a PPGn pin for the HSW timing generation circuit output. Bit n PMR7n Description 0 The P7n/PPGn pin functions as a P7n I/O pin 1 The P7n/PPGn pin functions as a PPGn output pin (Initial value) (n = 7 to 0) Rev. 0.1, 11/98, page 222 of 975 (2) Port Control Register 7 (PCR7) Bit : Initial value : R/W : 7 PCR77 6 PCR76 5 PCR75 4 PCR74 3 PCR73 2 PCR72 1 PCR71 0 PCR70 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Port control register 7 (PCR7) controls the I/Os of pins P77 to P70 of port 7 in a unit of bit. When PCR7 is set to 1, the corresponding P77 to P70 pins become output pins, and when it is set to 0, they become input pins. When the corresponding pin is set to the general I/O by PMR7, settings of PCR7 and PDR7 become valid. PCR7 is an 8-bit write-only register. When PCR7 is read, 1 is read. When reset, PCR7 is initialized to H'00. Bit n PCR7n Description 0 The P7n pin functions as an input pin 1 The P7n pin functions as an output pin (Initial value) (n = 7 to 0) Rev. 0.1, 11/98, page 223 of 975 (3) Port Data Register 7 (PDR7) Bit : Initial value : R/W : 7 PDR77 6 PDR76 5 PDR75 4 PDR74 3 PDR73 2 PDR72 1 PDR71 0 PDR70 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Port data register 7 (PDR7) stores the data for the pins P77 to P70 of port 7. When PCR7 is 1 (output), the PDR7 values are directly read if port 7 is read. Accordingly, the pin states are not affected. When PCR7 is 0 (input), the pin states are read if port 7 is read. PDR7 is an 8-bit read/write enable register. When reset, PDR7 is initialized to H'00. 10.9.3 Pin Functions This section describes the port 7 pin functions and their selection methods. (1) P77/PPG7 to P70/PPG0 P77/PPG7 to P70/PPG0 are switched as shown below according to the PMR7n bit in PMR7 and the PCR7n bit in PCR7. PMR7n PCR7n Pin Function 0 0 P7n input pin 1 P7n output pin * PPGn input pin 1 Note: 10.9.4 * Don't care. (n = 7 to 0) Pin States Table 10.25 shows the port 7 pin states in each operation mode. Table 10.25 Port 7 Pin States Pins Reset P77/PPG7 to HighP70/PPG0 impedance Active Sleep Standby Watch Subactive Subsleep Operation Holding Highimpedance Highimpedance Operation Rev. 0.1, 11/98, page 224 of 975 Holding 10.10 Port 8 10.10.1 Overview Port 8 is an 8-bit I/O port. Table 10.26 shows the port 8 configuration. Port 8 is a CMOS high-current I/O port. The sink current is 20 mA max. (VOL = 1.5 V) and up to four pins can simultaneously be set on. Port 8 consists of pins that are used both as high-current I/O ports (P87 to P80) and servo monitor output (SV1, SV2), capstan external synchronous signal input (EXCAP), or external trigger signal input (EXTTRG). It is switched by port mode register 8 (PMR8) and port control register 8 (PCR8). Table 10.26 Port 8 Configuration Port Function Alternative Function Port 8 P87 (high-current I/O port) None P86 (high-current I/O port) None P85 (high-current I/O port) None P84 (high-current I/O port) None P83 (high-current I/O port) SV2 (servo monitor output) P82 (high-current I/O port) SV1 (servo monitor output) P81 (high-current I/O port) EXCAP (capstan external synchronous signal input) P80 (high-current I/O port) EXTTRG (external trigger signal input) 10.10.2 Register Configuration Table 10.27 shows the port 8 register configuration. Table 10.27 Port 8 Register Configuration Name Abbrev. R/W Size Initial Value Address* Port mode register 8 PMR8 R/W Byte H'F0 H'FFDF Port control register 8 PCR8 W Byte H'00 H'FFD8 Port data register 8 PDR8 R/W Byte H'00 H'FFC8 Note: * The address indicates the low-order 16 bits. Rev. 0.1, 11/98, page 225 of 975 (1) Port Mode Register 8 (PMR8) Bit : 7 --- 6 --- 5 --- 4 --- 3 PMR83 2 PMR82 1 PMR81 0 PMR80 Initial value : R/W : 1 --- 1 --- 1 --- 1 --- 0 R/W 0 R/W 0 R/W 0 R/W Port mode register 8 (PMR8) controls switching of each pin function of port 8. The switching is specified in a unit of bit. PMR8 is an 8-bit read/write enable register. When reset, PMR8 is initialized to H'F0. If the EXCAP and EXTTRG input pins are set, the pin level need always be set to the high or low level regardless of the active mode and low power consumption mode. Note that the pin level must not reach an intermediate level. Bits 7 to 4: Reserved Bits Reserved bits. When the bits are read, 1 is always read. The write operation is valid. Bit 3: P83/SV2 Pin Switching (PMR83) PMR83 sets whether the P83/SV2 pin is used as a P83 I/O pin or an SV2 pin for the servo monitor output. For the selection of the SV2 output, see section 27, Servo Circuit. Bit 3 PMR83 Description 0 The P83/SV2 pin functions as a P83 I/O pin 1 The P83/SV2 pin functions as an SV2 output pin Rev. 0.1, 11/98, page 226 of 975 (Initial value) Bit 2: P82/SV1 Pin Switching (PMR82) PMR82 sets whether the P82/SV1 pin is used as a P82 I/O pin or an SV1 pin for the servo monitor output. For the selection of the SV1 output, see section 27, Servo Circuit. Bit 2 PMR82 Description 0 The P82/SV1 pin functions as a P82 I/O pin 1 The P82/SV1 pin functions as an SV1 output pin (Initial value) Bit 1: P81/EXCAP Pin Switching (PMR81) PMR81 sets whether the P83/EXCAP pin is used as a P81 I/O pin or an EXTTRG pin for the capstan external synchronous signal input. Bit 1 PMR81 Description 0 The P81/EXCAP pin functions as a P81 I/O pin 1 The P81/EXCAP pin functions as an EXCAP input pin (Initial value) Bit 0: P80/EXTTRG Pin Switching (PMR80) PMR80 sets whether the P80/EXTTRG pin is used as a P80 I/O pin or an EXTTRG pin for the external trigger signal input. Bit 0 PMR80 Description 0 The P80/EXTTRG pin functions as a P80 I/O pin 1 The P80/EXTTRG pin functions as an EXTTRG input pin (Initial value) Rev. 0.1, 11/98, page 227 of 975 (2) Port Control Register 8 (PCR8) Bit : Initial value : R/W : 7 PCR87 6 PCR86 5 PCR85 4 PCR84 3 PCR83 2 PCR82 1 PCR81 0 PCR80 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Port control register 8 (PCR8) controls the I/Os of pins P87 to P80 of port 8 in a unit of bit. When PCR8 is set to 1, the corresponding P87 to P80 pins become output pins, and when it is set to 0, they become input pins. When the corresponding pin is set to a general I/O, settings of PCR8 and PDR8 become valid. PCR8 is an 8-bit write-only register. When PCR8 is read, 1 is read. When reset, PCR8 is initialized to H'00. Bit n PCR8n Description 0 The P8n pin functions as an input pin 1 The P8n pin functions as an output pin (Initial value) (n = 7 to 0) (3) Port Data Register 8 (PDR8) Bit : Initial value : R/W : 7 PDR87 6 PDR86 5 PDR85 4 PDR84 3 PDR83 2 PDR82 1 PDR81 0 PDR80 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Port data register 8 (PDR8) stores the data for the pins P87 to P80 of port 8. When PCR8 is 1 (output), the PDR8 values are directly read if port 8 is read. Accordingly, the pin states are not affected. When PCR8 is 0 (input), the pin states are read if port 8 is read. PDR8 is an 8-bit read/write enable register. When reset, PDR8 is initialized to H'00. Rev. 0.1, 11/98, page 228 of 975 10.10.3 Pin Functions This section describes the port 8 pin functions and their selection methods. (1) P87 to P84 P87 to P84 are switched as shown below according to the PCR8n bit in PCR8. PCR8n Pin Function 0 P8n input pin 1 P8n output pin (n = 7 to 4) Note: * Don't care. (2) P83/SV2 P83/SV2 is switched as shown below according to the PMR83 bit in PMR8 and the PCR83 bit in PCR8. PMR83 PCR83 Pin Function 0 0 P83 input pin 1 P83n output pin * SV2 output pin 1 Note: * Don't care. Rev. 0.1, 11/98, page 229 of 975 (3) P82/SV1 P82/SV1 is switched as shown below according to the PMR82 bit in PRM8 and the PCR82 bit in PCR8. PMR82 PCR82 Pin Function 0 0 P82 input pin 1 P82 output pin * SV1 output pin 1 Note: * Don't care. (4) P81/EXCAP P81/EXCAP is switched as shown below according to the PMR81 bit in PRM8 and the PCR81 bit in PCR8. PMR81 PCR81 Pin Function 0 0 P81 input pin 1 P81 output pin * EXCAP input pin 1 Note: * Don't care. (5) P80/EXTTRG P80/EXTTRG is switched as shown below according to the PMR80 bit in PRM8 and the PCR80 bit in PCR8. PMR80 PCR80 Pin Function 0 0 P80 input pin 1 P80 output pin * EXTTRG input pin 1 Note: * Don't care. Rev. 0.1, 11/98, page 230 of 975 10.10.4 Pin States Table 10.28 shows the port 8 pin states in each operation mode. Table 10.28 Port 8 Pin States Pins Reset Active Sleep Standby Watch Subactive Subsleep P87 to P84 P83/SV2 P83/SV1 P81/ EXCAP P80/ EXTTRG Highimpedance Operation Holding Highimpedance Highimpedance Operation Holding Note: If the EXCAP and EXTTRG input pins are set, the pin level need always be set to the high or low level regardless of the active mode and low power consumption mode. Note that the pin level must not reach an intermediate level. Rev. 0.1, 11/98, page 231 of 975 Rev. 0.1, 11/98, page 232 of 975 Section 11 Timer A 11.1 Overview The Timer A is an 8-bit interval timer. It can be used as a clock timer when connected to a 32.768 kHz crystal oscillator. 11.1.1 Features Features of the Timer A are as follows: * Choices of eight different types of internal clocks (/16384, /8192, /4096, /1024, /512, /256, /64 and /16) are available for your selection. * Four different overflowing cycles (1s, 0.5s, 0.25s and 0.03125s) are selectable as a clock timer. (When using a 32.768 kHz crystal oscillator.) * Requests for interrupt will be output when the counter overflows. Rev. 0.1, 11/98, page 233 of 975 11.1.2 Block Diagram Figure 11.1 shows a block diagram of the Timer A. 1/4 TMA Prescaler W (PSW) w/128 Prescaler S (PSS) System clock /256 * /128 * /64 * /16384, /8192, /4096, /1024, /512, /256, /64, /16 /8 * TCA Overflowing of the interval timer Interrupting circuit Internal data bus 32 kHz w Crystal oscillator Interrupt requests Prescaler unit [Legend] TMA : Timer mode register A TCA : Timer counter A Note: * Selectable only when the prescaler W output (w/128) is working as the input clock to the TCA. Figure 11.1 Block Diagram of the Timer A 11.1.3 Register Configuration Table 11.1 shows the register configuration of the Timer A. Table 11.1 Register configuration Name Abbrev. R/W Size Initial Value Address* Timer mode register A TMA R/W Byte H'30 H'FFBA Timer counter A TCA R Byte H'00 H'FFBB Note: * Lower 16 bits of the address. Rev. 0.1, 11/98, page 234 of 975 11.2 Descriptions of Respective Registers 11.2.1 Timer Mode Register A (TMA) Bit : 7 TMAOV Initial value : R/W : 6 5 4 3 2 1 0 TMAIE -- -- TMA3 TMA2 TMA1 TMA0 0 0 1 1 0 0 0 0 R/(W)* R/W -- -- R/W R/W R/W R/W Note: * Only 0 can be written to clear the flag. The timer mode register A (TMA) works to control the interrupts of the Timer A and to select the input clock. TMA is an 8-bit read/write register. When reset, the TMA will be initialized to H'30. Bit 7: Timer A Overflow Flag (TMAOV) This is a status flag indicating the fact that the TCA is overflowing (H'FF H'00). Bit 7 TMAOV Description 0 [Clearing conditions] (Initial value) When 0 is written to the TMAOV flag after reading the TMAOV flag under the status where TMAOV = 1 1 [Setting conditions] When the TCA overflows Bit 6: Enabling Interrupt of the Timer A (TMAIE) This bit works to permit/prohibit occurrence of interrupt of the Timer A (TMAI) when the TCA overflows and when the TMAOV of the TMA is set to 1. Bit 6 TMAIE Description 0 Prohibits occurrence of interrupt of the Timer A (TMAI) 1 Permits occurrence of interrupt of the Timer A (TMAI) (Initial value) Bits 5 and 4: Reserved These bits are reserved. When they are read, 1 will always be readout. Writes are disabled. Rev. 0.1, 11/98, page 235 of 975 Bit 3: Selection of the Clock Source and Prescaler (TMA3) This bit works to select the PSS or PSW as the clock source for the Timer A. Bit 3 TMA3 Description 0 Selects the PSS as the clock source for the Timer A 1 Selects the PSW as the clock source for the Timer A (Initial value) Bits 2 to 0: Clock Selection (TMA2 to TMA0) These bits work to select the clock to input to the TCA. In combination with the TMA3 bit, the choices are as follows: Bit 3 Bit 2 Bit 1 Bit 0 TMA3 TMA2 TMA1 TMA0 Prescaler division ratio (interval timer) or Operation overflow cycle (time base) mode 0 0 0 0 PSS, /16384 (Initial value) 1 PSS, /8192 0 PSS, /4096 1 PSS, /1024 0 PSS, /512 1 PSS, /256 1 0 PSS, /64 1 PSS, /16 0 0 1s 1 0.5s 0 0.25s 1 0.03125s 0 Works to clear the PSW and TCA to H'00 1 1 1 0 0 1 1 0 1 1 0 1 Note: = f osc Rev. 0.1, 11/98, page 236 of 975 Interval timer mode Clock time base mode 11.2.2 Timer Counter A (TCA) Bit : 7 6 5 4 3 2 1 0 TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 Initial value : 0 0 0 0 0 0 0 0 R/W : R R R R R R R R The timer counter A (TCA) is an 8-bit up-counter which counts up on inputs from the internal clock. The inputting clock can be selected by TMA3 to TMA0 bits of the TMA When the TCA overflows, the TMAOV bit of the TMA is set to 1. The TCA can be cleared by setting the TMA3 and TMA2 bits of the TMA to 11. The TCA is always readable. When reset, the TCA will be initialized into H'00. 11.2.3 Module Stop Control Register (MSTPCR) MSTPCRH Bit : 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode. When the MSTP15 bit is set to 1, the Timer A stops its operation at the ending point of the bus cycle to shift to the module stop mode. For more information, see section 4.5, Module Stop Mode. When reset, the MSTPCR will be initialized into H'FFFF. Bit 7: Module Stop (MSTP15) This bit works to designate the module stop mode for the Timer A. MSTPCRH Bit 7 MSTP15 Description 0 Cancels the module stop mode of the Timer A 1 Sets the module stop mode of the Timer A (Initial value) Rev. 0.1, 11/98, page 237 of 975 11.3 Operation The Timer A is an 8-bit timer for use as an interval timer and as a clock time base connecting to a 32.768 kHz crystal oscillator. 11.3.1 Operation as the Interval Timer When the TMA3 bit of the TMA is cleared to 0, the Timer A works as an 8-bit interval timer. When resetince the TCA is cleared to H'00 and as the TMA3 bit is cleared to 0, the Timer A continues counting up as the interval counter without interrupts right after resetting. As the operation clock for the Timer A, selection can be made from eight different types of internal clocks being output from the PSS by the TMA2 to TMA0 bits of the TMA. When the clock signal is input after the reading of the TCA reaches H'FF, the Timer A overflows and the TMAOV bit of the TMA will be set to 1. At this time, when the TMAIE bit of the TMA is 1, interrupt occurs. When overflowing occurs, the reading of the TCA returns to H'00 before resuming counting up. Consequently, it works as the interval timer to produce overflow outputs periodically at every 256 input clocks. 11.3.2 Operation of the Timer for Clocks When the TMA3 bit of the TMA is set to 1, the Timer A works as a time base for the clock. As the overflow cycles for the Timer A, selection can be made from four different types by counting the clock being output from the PSW by the TMA1 bit and TMA0 bit of the TMA. 11.3.3 Initializing the Counts When the TMA3 and TMA2 bits are set to 11, the PSW and TCA will be cleared to H'00 to come to a stop. At this state, writing 10 to the TMA3 bit and TMA2 bit makes the Timer A to start counting from H'00 under the time base mode for clocks. After clearing the PSW and TCA using the TMA3 and TMA2 bits, writing 00 or 01 to the TMA3 bit and TMA2 bit work to make the Timer A to start counting from H'00 under the interval timer mode. However, since the PSS is not cleared, the period to the first count is not constant. Rev. 0.1, 11/98, page 238 of 975 Section 12 Timer B 12.1 Overview The Timer B is an 8-bit up-counter. The Timer B is equipped with two different types of functions namely, the interval function and the auto reloading function. 12.1.1 Features * Selection from choices of seven different types of internal clocks (/16384, /4096, /1024, /512, /128, /32 and /8) or selection of external clock are possible. * When the counter overflows, a interrupt request will be issued. 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the Timer B. TMB Clock sources /4096 TCB /1024 Overflowing /512 /128 Re-loading /32 /8 TMBI TLB Internal data bus /16384 Interrupting circuit [Legend] TMB TCB TLB TMBI : Timer mode register B : Timer counter B : Timer re-loading register B : Event input terminal of the Timer B Timer B Interrupt requests Figure 12.1 Block diagram of the Timer B Rev. 0.1, 11/98, page 239 of 975 12.1.3 Pin Configuration Table 12.1 shows the pin configuration of the Timer B. Table 12.1 Pin Configuration Name Abbrev. I/O Function Event inputs to the Timer B TMBI Input Event input pin for inputs to the TCB 12.1.4 Register Configuration Table 12.2 shows the register configuration of the Timer B. The TCB and TLB are being allocated to the same address. Reading or writing determines the accessing register. Table 12.2 Register Configuration Name Abbrev. R/W Size Initial Value Address* Timer mode register B TMB R/W Byte H'18 H'D110 Timer counter B TCB R Byte H'00 H'D111 Timer load register B TLB W Byte H'00 H'D111 Port mode register 5 PMR5 R/W Byte H'F1 H'FFDC Note: * Lower 16 bits of the address. Rev. 0.1, 11/98, page 240 of 975 12.2 Descriptions of Respective Registers 12.2.1 Timer Mode Register B (TMB) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 TMB17 TMBIF TMBIE -- -- TMB12 TMB11 TMB10 0 0 0 1 1 0 0 0 R/W R/(W)* R/W -- -- R/W R/W R/W Note: Only 0 can be written to clear the flag. The TMB is an 8-bit read/write register which works to control the interrupts, to select the auto reloading function and to select the input clock. When reset, the TMB is initialized to H'18. Bit 7: Selecting the Auto Reloading Function (TMB17) This bit works to select the auto reloading function of the Timer B. Bit 7 TMB17 Description 0 Selects the interval function 1 Selects the auto reloading function (Initial value) Bit 6: Interrupt Requesting Flag for the Timer B (TMBIF) This is an interrupt requesting flag for the Timer B. It indicates the fact that the TCB is overflowing. Bit 6 TMBIF Description 0 [Clearing conditions] When 0 is written after reading 1 1 [Setting conditions] When the TCB overflows (Initial value) Rev. 0.1, 11/98, page 241 of 975 Bit 5: Enabling Interrupt of the Timer B (TMBIE) This bit works to permit/prohibit occurrence of interrupt of the Timer B when the TCB overflows and when the TMBIF is set to 1. Bit 5 TMBIE Description 0 Prohibits occurrence of interrupt of the Timer B 1 Permits occurrence of interrupt of the Timer B (Initial value) Bits 4 to 3: Reserved These bits are reserved. When they are read, 1 will always be readout. Writes are disabled. Bits 2 to 0: Clock Selection (TMB12 to TMB10) These bits work to select the clock to input to the TCB. Selection of the rising edge or the falling edge is workable with the external event inputs. Bit 2 Bit 1 Bit 0 TMB12 TMB11 TMB10 Descriptions 0 0 0 Internal clock: Counts at /16384 0 0 1 Internal clock: Counts at /4096 0 1 0 Internal clock: Counts at /1024 0 1 1 Internal clock: Counts at /512 1 0 0 Internal clock: Counts at /128 1 0 1 Internal clock: Counts at /32 1 1 0 Internal clock: Counts at /8 1 1 1 Counts at the rising edge and the falling edge of external event inputs (TMBI) * Note: * (Initial value) The edge selection for the external event inputs is made by setting the PMR51 of the port mode register 5 (PMR5). See section 12.2.4, Port Mode Register 5 (PMR5). Rev. 0.1, 11/98, page 242 of 975 12.2.2 Timer Counter B (TCB) Bit : 7 6 5 4 3 2 1 0 TCB17 TCB16 TCB15 TCB14 TCB13 TCB12 TCB11 TCB10 Initial value : 0 0 0 0 0 0 0 0 R/W : R R R R R R R R The TCB is an 8-bit readable register which works to count up by the internal clock inputs and external event inputs. The input clock can be selected by the TMB12 to TMB10 of the TMB. When the TCB overflows (H'FF H'00 or H'FF TLB setting), a interrupt request of the Timer B will be issued. When reset, the TCB is initialized to H'00. 12.2.3 Timer Load Register B (TLB) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 TLB17 TLB16 TLB15 TLB14 TLB13 TLB12 TLB11 TLB10 0 0 0 0 0 0 0 0 W W W W W W W W The TLB is an 8-bit write only register which works to set the reloading value of the TCB. When the reloading value is set to the TLB, the value will be simultaneously loaded to the TCB and the TCB starts counting up from the set value. Also, during an auto reloading operation, when the TCB overflows, the value of the TLB will be loaded to the TCB. Consequently, the overflowing cycle can be set within the range of 1 to 256 input clocks. When reset, the TLB is initialized to H'00. Rev. 0.1, 11/98, page 243 of 975 12.2.4 Port Mode Register 5 (PMR5) Bit : 7 6 5 4 3 2 1 0 -- -- -- -- PMR53 PMR52 PMR51 -- 0 0 0 1 R/W -- Initial value : 1 1 1 1 R/W : -- -- -- -- R/W R/W The port mode register 5 (PMR5) works to changeover the pin functions of the port 5 and to designate the edge sense of the event inputs of the Timer B (TMBI). The PMR5 is an 8-bit read/write register. When reset, the PMR5 will be initialized to H'F1. See section 10.7, Port 5 for other information than bit 1. Bit 1: Selecting the Edges of the Event Inputs to the Timer B (PMR51) This bit works to select the input edge sense of the TMBI pins. Bit 1 PMR51 Description 0 Detects the falling edge of the event inputs to the Timer B 1 Detects the rising edge of the event inputs to the Timer B Rev. 0.1, 11/98, page 244 of 975 (Initial value) 12.2.5 Module Stop Control Register (MSTPCR) MSTPCRH Bit : 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode. When the MSTP14 bit is set to 1, the Timer B stops its operation at the ending point of the bus cycle to shift to the module stop mode. For more information, see section 4.5, Module stop mode. When reset, the MSTPCR is initialized to H'FFFF. Bit 6: Module Stop (MSTP14) This bit works to designate the module stop mode for the Timer B. MSTPCRH Bit 6 MSTP14 Description 0 Cancels the module stop mode of the Timer B 1 Sets the module stop mode of the Timer B (Initial value) Rev. 0.1, 11/98, page 245 of 975 12.3 Operation 12.3.1 Operation as the Interval Timer When the TMB17 bit of the TMB is set to 0, the Timer B works as an 8-bit interval timer. When reset, since the TCB is cleared to H'00 and as the TMB17 bit is cleared to 0, the Timer B continues counting up as the interval timer without interrupts right after resetting. As the clock source for the Timer B, selection can be made from seven different types of internal clocks being output from the prescaler unit by the TMB12 to TMB10 bits of the TMB or an external clock through the TMBI input pin can be chosen instead. When the clock signal is input after the reading of the TCB reaches H'FF, the Timer B overflows and the TMBIF bit of the TMB will be set to 1. At this time, when the TMBIE bit of the TMB is 1, interrupt occurs. When overflowing occurs, the reading of the TCB returns to H'00 before resuming counting up. When a value is set to the TLB while the interval timer is in operation, the value which has been set to the TLB will be loaded to the TCB simultaneously. 12.3.2 Operation as the Auto Reload Timer When the TMB17 of the TMB is set to 1, the Timer B works as an 8-bit auto reload timer. When a reload value is set in the TLB, the value is loaded onto the TCB at the same time, and the TCB starts counting up from the value. When the clock signal is input after the reading of the TCB reaches H'FF, the Timer B overflows and the TLB value is loaded onto the TCB, then the TCB continues counting up from the loaded value. Accordingly, overflow interval can be set within the range of 1 to 256 clocks depending on the TLB value. Clock source and interrupts in the auto reload operation are the same as those in the interval operation. When the TLB value is re-set while the auto reload timer is in operation, the value which has been set to the TLB will be loaded onto the TCB simultaneously. 12.3.3 Event Counter The Timer B works as an event counter using the TMBI pin as the event input pin. When the TMB12 to TMB10 are set to 111, the external event will be selected as the clock source and the TCB counts up at the leading edge or the trailing edge of the TMBI pin inputs. Rev. 0.1, 11/98, page 246 of 975 Section 13 Timer J 13.1 Overview The Timer J consists of twin 8-bit counters. It carries seven different operation modes such as reloading and event counting. 13.1.1 Features The Timer J consists of twin 8-bit reloading timers and it is usable under the various functions as follows: (a) Twin 8-bit reloading timers (Among the two, one is capable to make timer outputs) (b) Twin 8-bit event counters (Capable to make reloading) (c) 8-bit event counter (Capable to make reloading) + 8-bit reload timer (d) 16-bit event counter (Capable to make 16-bit reloading) (e) 16-bit reload timer (Capable to make 16-bit reloading) (f) Remote controlled transmissions (g) "Take up/Supply reel pulse" dividing (8 bit x 2 units) 13.1.2 Block Diagram Figure 13.1 is a block diagram of the Timer J. The Timer J consists of two reload timers namely, TMJ-1 and TMJ-2. Rev. 0.1, 11/98, page 247 of 975 Clock sources IRQ1 /4 /256 /512 Rev. 0.1, 11/98, page 248 of 975 8/16 Reloading register TLJ ST Synchronization PS11,10 Figure 13.1 Block Diagram of the Timer J T/R 8/16 ST : Timer output/Remote controller output changeover : 8-bit/16-bit operation changeover : Starting the remote controlled operation PS21,20 : TMJ-2 input clock selection PS11,10 : TMJ-1 input clock selection TMO TLK : Timer load register K BUSS Output Control Monitor Output Control T/R TCK : Timer counter K REMOout : TMJ-2 toggle output (Remote controller transmission data) TGL : TMJ-2 toggle plug TLJ : Timer load register J : TMJ-1 timer output : Buzzer output Edge detection TMO Toggle TGL TCJ : Timer counter J REMOout BUZZ Internal data bus Reloading register (Burst/space PS21,20 width register TLK Reloading TCK Underflow Down-counter (8-bit) TMJ-2 /4096 /8192 PB/REC-CTL DVCTL TCA7 TMO [Legend] Note: * At the Low level under the timer mode. * Reloading TCJ Under- flow Downcounter (8-bit) TMJ-1 Toggle Clock sources IRQ2 /2048 /16384 Interrupt request by the TMJ2 Interrupt request by the TMJ1 TMJ-2 Interrupting circuit TMJ-1 Interrupting circuit BUZZ 13.1.3 Pin Configuration Table 13.1 shows the pin configuration of the Timer J. Table 13.1 Pin Configuration Name Abbrev. I/O Function Event input pin ,54 Input Event inputs to the TMJ-1 Event input pin ,54 Input Event inputs to the TMJ-2 13.1.4 Register Configuration Table 13.2 shows the register configuration of the Timer J. The TCJ and TLJ or the TCK and TLK are being allocated to the same address respectively. Reading or writing determines the accessing register. Table 13.2 Register Configuration Name Abbrev. R/W Size Initial Value Address*2 Timer mode register J TMJ R/W Byte H'00 H'D13A Timer J control register TMJC R/W Byte H'09 H'D13B Byte H'3F H'D13C *1 Timer J status register TMJS R/(W) Timer counter J TCJ R Byte H'FF H'D139 Timer counter K TCK R Byte H'FF H'D138 Timer load register J TLJ W Byte H'FF H'D139 Timer load register K TLK W Byte H'FF H'D138 Notes: 1. Only 0 can be written to clear the flag. 2. Lower 16 bits of the address. Rev. 0.1, 11/98, page 249 of 975 13.2 Descriptions of Respective Registers 13.2.1 Timer Mode Register J (TMJ) 7 6 5 4 3 2 1 0 PS11 PS10 ST 8/16 PS21 PS20 TGL T/R Bit : Initial value : R/W : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R R/W The timer mode register J (TMJ) works to select the inputting clock for the TMJ-1 and TMJ-2 and to set the operation mode. The TMJ is an 8-bit register and Bit-1 is for read only and all the remaining bits are applicable to read/write. When reset, the TMJ is initialized to H'00. Under all other modes than the remote controlling mode, writing into the TMJ works to initialize the counters (TCJ and TCK) to H'FF. Bits 7 and 6: Selecting the Inputting Clock to the TMJ-1 (PS11 and PS10) These bits work to select the clock to input to the TMJ-1. Selection of the rising edge or the falling edge is workable for counting by use of an external clock. Bit 7 Bit 6 PS11 PS10 Description 0 0 Counting by the PSS, /512 1 Counting by the PSS, /256 0 Counting by the PSS, /4 1 Counting at the rising edge or the falling edge of the external clock inputs (,54) * 1 Note: * (Initial value) The edge selection for the external clock inputs is made by setting the edge select register (IEGR). See section 6.2.4, Edge Select Register (IEGR) for more information. When using an external clock under the remote controlling mode, set the opposite edge with the IRQ1 and the IRQ2 when using an external clock under the remote controlling mode. (When IRQ1 falling, select IRQ2 rising and when IRQ1 rising, select IRQ2 falling) Rev. 0.1, 11/98, page 250 of 975 Bit 5: Starting the Remote Controlled Operation (ST) This bit works to start the remote controlled operations. When this bit is set to 1, clock signal is supplied to the TMJ-1 to start signal transmissions. When this bit is cleared to 0, clock supply stops to discontinue the operation. The ST bit will be valid under the remote controlling mode, namely, when the Bit 0 (T/R bit) is 1 and the Bit 4 (8/16 bit) is 0. Under other modes than the remote controlling mode, it will be fixed to 0. When a shift to the low power consumption mode is made during remote controlled operation, the ST bit will be cleared to 0. When resuming operation after returning to the active mode, write 1. Bit 5 ST Description 0 Works to stop clock signal supply to the TMJ-1 under the remote controlling mode (Initial value) 1 Works to supply clock signal to the TMJ-1 under the remote controlling mode Bit 4: Switching Over Between 8-bit/16-bit Operations (8/16) This bit works to choose if using the Timer J as two units of 8-bit timer/counter or if using it as a single unit of 16-bit timer/counter. Even under 16-bit operations, TMJ1I interrupt requests from the TMJ-1 will be valid. Bit 4 8/16 Description 0 Makes the TMJ-1 and TMJ-2 operate separately 1 Makes the TMJ-1 and TMJ-2 operate altogether as 16-bit timer/counter (Initial value) Bits 3 and 2: Selecting the Inputting Clock to the TMJ-2 (PS21 and PS20) This bit works to select the clock to input to the TMJ-2. Selection of the leading edge or the trailing edge is workable for counting by use of an external clock. Bit 3 Bit 2 PS21 PS20 Description 0 0 Counting by the PSS, /16384 1 Counting by the PSS, /2048 0 Counting at underflowing of the TMJ-1 1 Counting at the leading edge or the trailing edge of the external clock inputs (,54) * 1 Note: * (Initial value) The edge selection for the external clock inputs is made by setting the edge select register (IEGR). See section 6.2.4, Edge Select Register (IEGR) for more information. Rev. 0.1, 11/98, page 251 of 975 Bit 1: TMJ-2 Toggle Flag (TGL) This flag indicates the toggled status of the underflowing with the TMJ-2. Reading only is workable. It will be cleared to 0 under the low power consumption mode. Bit 1 TGL Description 0 The toggle output of the TMJ-2 is 0 1 The toggle output of the TMJ-2 is 0 (Initial value) Bit 0: Switching Over Between Timer Output/Remote Controlling Output (T/R) This bit works to select if using the timer outputs from the TMJ-1 as the output signal through the TMO pin or if using the toggle outputs (remote controlled transmission data) from the TMJ-2 as the output signal through the TMO pin. Bit 0 T/R Description 0 Timer outputs from the TMJ-1 1 Toggle outputs from the TMJ-2 (remote controlled transmission data) (Initial value) Selecting the Operation Mode The operation mode of the Timer J is determined by the Bit 4 (8/16) and Bit 0 (T/R) of the TMJ. TMJ Bit 4 Bit 0 8/16 T/R Description 0 0 8-bit timer x 2 1 Remote controlling mode * 16-bit timer 1 Note: * (Initial value) Don't care. When writing is made into the TMJ under the timer mode, the counters (TCJ and TCK) will be initialized (H'FF). Consequently, writing into the reloading registers (TLJ an TLK) should be conducted after finishing settings with the TMJ. Under the remote controlling mode, although the TLJ and the TLK will not be initialized even when writing is made into the TMJ, follow the sequence listed below when starting a remote controlling operation. Rev. 0.1, 11/98, page 252 of 975 (1) Make setting to the remote controlling mode with the TMJ. (2) Write the data into the TLJ and TLK. (3) Start the remote controlled operation by use of the TMJ. (ST bit = 1) Even under 16-bit operations, TMJ1I interrupt requests from the TMJ-1 will be valid. 13.2.2 Timer J Control Register (TMJC) Bit : 7 6 5 4 3 2 1 0 BUZZ1 BUZZ0 MON1 MON0 -- TMJ2IE TMJ1IE -- 0 0 0 0 1 0 0 1 R/W R/W R/W R/W -- R/W R/W -- Initial value : R/W : The timer J control register works to select the buzzer output frequency and to control permission/prohibition of interrupts. The TMJC is an 8-bit read/write register. When reset, the TMJC is initialized to H'09. Bits 7 and 6: Selecting the Buzzer Output (BUZZ1 or BUZZ0) This bit works to select if using the buzzer outputs as the output signal through the BUZZ pin or if using the monitor signals as the output signal through the BUZZ pin. When setting is made to the monitor signals, choose the monitor signal using the MON1 bit and MON0 bit. Bit 7 Bit 6 BUZZ1 BUZZ0 Description 0 0 /4096 (Initial value) 2.44 kHz 1 /8192 1.22 kHz 0 Works to output monitor signals 1 Works to output BUZZ signals from the Timer J 1 Frequency when = 10MHz Rev. 0.1, 11/98, page 253 of 975 Bits 5 and 4: Selecting the Monitor Signals (MON1 or MON0) These bits work to select the type of signals being output through the BUZZ pin for monitoring purpose. These settings are valid only when the BUZZ1 and BUZZ0 bits are being set to 1 and 0. When PB-CTL or REC-CTL is chosen, signal duties will be output as they are. In case of DVCTL signals, signals from the CTL dividing circuit will be toggled before being output. Signal waveforms divided by the CTL dividing circuit into "n-divisions" will further be divided into halves. (Namely, "2n" divisions, 50% duty waveform). In case of TCA7, Bit 7 of the counter of the Timer A will be output. (50% duty) When the prescaler is being used with the Timer A, 1Hz outputs are available. Bit 5 Bit 4 MON1 MON0 Description 0 0 PB or REC-CTL 1 DVCTL * Outputs TCA7 1 Note: * (Initial value) Don't care. Bits 3: Reserved This bit is reserved. When this is read, 1 will always be readout. Writes are disabled. Bit 2: Enabling Interrupt of the TMJ2I (TMJ2IE) This bit works to permit/prohibit occurrence of TMJ2I interrupt of the TMJS in 1-set of the TMJ2I. Bit 2 TMJ2IE Description 0 Prohibits occurrence of TMJ2I interrupt 1 Permits occurrence of TMJ2I interrupt (Initial value) Bit 1: Enabling Interrupt of the TMJ1I (TMJ1IE) This bit works to permit/prohibit occurrence of TMJ1I interrupt of the TMJS in 1-set of the TMJ1I. Bit 1 TMJ1IE Description 0 Prohibits occurrence of TMJ1I interrupt 1 Permits occurrence of TMJ1I interrupt Rev. 0.1, 11/98, page 254 of 975 (Initial value) Bit 0: Reserved This bit is reserved. When this is read, 1 will always be readout. Writes are disabled. 13.2.3 Timer J Status Register (TMJS) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 TMJ2I TMJ1I -- -- -- -- -- -- 0 0 1 1 1 1 1 1 R/(W)* R/(W)* -- -- -- -- -- -- Note: * Only 0 can be written to clear the flag. The timer J status register (TMJS) works to indicate issuance of the interrupt request of the Timer J. The TMJS is an 8-bit read/write register. When reset, the TMJS is initialized to H'3F. Bit 7: TMJ2I Interrupt Requesting Flag (TMJ2I) Bit 7 TMJ2I Description 0 [Clearing conditions] When 0 is written after reading 1 1 [Setting conditions] When the TMJ-2 underflows (Initial value) Bit 6: TMJ1I Interrupt Requesting Flag (TMJ1I) This is the TMJ1I interrupt requesting flag. This flag is set out when the TMJ-1 underflows. TMJ1I interrupt requests will also be made under a 16-bit operation. Bit 6 TMJ1I Description 0 [Clearing conditions] When 0 is written after reading 1 1 [Setting conditions] When the TMJ-1 underflows (Initial value) Bits 5 to 0: Reserved These bits are reserved. When they are read, 1 will always be readout. Writes are disabled. Rev. 0.1, 11/98, page 255 of 975 13.2.4 Timer Counter J (TCJ) 7 6 5 4 3 2 1 0 TDR17 TDR16 TDR15 TDR14 TDR13 TDR12 TDR11 TDR10 Initial value : 1 1 1 1 1 1 1 1 R/W : R R R R R R R R Bit : The time counter J (TCJ) is an 8-bit readable down-counter which works to count down by the internal clock inputs or external clock inputs. The inputting clock can be selected by the PS11 and PS10 bits of the TMJ. TCJ values can be readout always. Nonetheless, when the 8/16 bit of the TMJ is being set to 1 (means when setting is made to 16-bit operation), reading is possible under the word command only. At this time, the TCK of the TMJ-2 can be read by the upper 8 bits and the TCJ can be read by the lower 8 bits. When the TCJ underflows (H'00 Reloading value), regardless of the operation mode setting of the 8/16 bit, the TMJ1I bit of the TMJS will be set to 1 bit. The TCJ and TLJ are being allocated to the same address. When reset, the TCJ is initialized to H'FF. 13.2.5 Timer Counter K (TCK) 7 6 5 4 3 2 1 0 TDR27 TDR26 TDR25 TDR24 TDR23 TDR22 TDR21 TDR20 Initial value : 1 1 1 1 1 1 1 1 R/W : R R R R R R R R Bit : The time counter K (TCK) is an 8-bit readable down-counter which works to count down by the internal clock inputs or external clock inputs. The inputting clock can be selected by the PS21 and PS20 bits of the TMJ. TCK values can be readout always. Nonetheless, when the 8/16 bit of the TMJ is being set to 1 (means when setting is made to 16-bit operation), reading is possible under the word command only. At this time, the TCK can be read by the upper 8 bits and the TCJ of the TMJ-1 can be read by the lower 8 bits. When the TCK underflows (H'00 Reloading value), the TMJ2I bit of the TMJS will be set to 1. The TCK and TLK are being allocated to the same address. When reset, the TCK is initialized to H'FF. Rev. 0.1, 11/98, page 256 of 975 13.2.6 Timer Load Register J (TLJ) 7 6 5 4 3 2 1 0 TLR17 TLR16 TLR15 TLR14 TLR13 TLR12 TLR11 TLR10 Initial value : 1 1 1 1 1 1 1 1 R/W : W W W W W W W W Bit : The timer load register J (TLJ) is an 8-bit write only register which works to set the reloading value of the TCJ. When the reloading value is set to the TLJ, the value will be simultaneously loaded to the TCJ and the TCJ starts counting down from the set value. Also, during an auto reloading operation, when the TCJ underflows, the value of the TLJ will be loaded to the TCJ. Consequently, the underflowing cycle can be set within the range of 1 to 256 input clocks. Nonetheless, when the 8/16 bit of the TMJ is being set to 1 (means when setting is made to 16-bit operation), writing is possible under the word command only. At this time, the upper 8 bits can be written into the TLK of the TMJ-2 and the lower 8 bits can be written into the TLJ. The TLJ and TCJ are being allocated to the same address. When reset, the TLJ is initialized to H'FF. 13.2.7 Timer Load Register K (TLK) Bit : 7 6 5 4 3 2 1 0 TLR27 TLR26 TLR25 TLR24 TLR23 TLR22 TLR21 TLR20 Initial value : 1 1 1 1 1 1 1 1 R/W : W W W W W W W W The timer load register K (TLK) is an 8-bit write only register which works to set the reloading value of the TCK. When the reloading value is set to the TLK, the value will be simultaneously loaded to the TCK and the TCK starts counting down from the set value. Also, during an auto reloading operation, when the TCK underflows, the value of the TLK will be loaded to the TCK. Consequently, the underflowing cycle can be set within the range of 1 to 256 input clocks. Nonetheless, when the 8/16 bit of the TMJ is being set to 1 (means when setting is made to 16-bit operation), writing is possible under the word command only. At this time, the upper 8 bits can be written into the TLK and the lower 8 bits can be written into the TLJ of the TMJ-1. The TLK and TCK are being allocated to the same address. When reset, the TLK is initialized to H'FF. Rev. 0.1, 11/98, page 257 of 975 13.2.8 Module Stop Control Register (MSTPCR) MSTPCRH Bit : 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode. When the MSTP13 bit is set to 1, the Timer J stops its operation at the ending point of the bus cycle to shift to the module stop mode. For more information, see section 4.5, Module Stop Mode. When reset, the MSTPCR is initialized to H'FFFF. Bit 5: Module Stop (MSTP13) This bit works to designate the module stop mode for the Timer J. MSTPCRH Bit 5 MSTP13 Description 0 Cancels the module stop mode of the Timer J 1 Sets the module stop mode of the Timer J Rev. 0.1, 11/98, page 258 of 975 (Initial value) 13.3 Operation 13.3.1 8-bit Reload Timer (TMJ-1) The TMJ-1 is an 8-bit reload timer. As the clock source, dividing clock or edge signals through the ,54 pin are being used. By selecting the edge signals through the ,54 pin, it can also be used as an event counter. While it is working as an event counter, its reloading function is workable simultaneously. When data are written into the reloading register, these data will be written into the counter simultaneously. Also, when the counter underflows, reloading will be made to the data counter of the reloading register. When the counter underflows, TMJ1I interrupt requests will be issued. The underflow will be toggled and, by a appropriate selection of the dividing clock, buzzer outputs will be issued or carrier frequencies for remote controlling transmissions can be acquired. The TMJ-1 and TMJ-2, in combination, can be used as a 16-bit reload timer. Nonetheless, when they are being used, in combination, as a 16-bit timer, word command only is valid and the TCK works as the down counter for the upper 8 bits and the TCJ works as the down counter for the lower 8 bits, means a reloading register of total 16 bits. When data are written into a 16-bit reloading register, the same data will be written into the 16bit counter. Also, when the 16-bit counter underflows, the data of the 16-bit reloading register will be reloaded into the counter. Even when they are making a 16-bit operation, the TMJ1I interrupt requests of the TMJ-1 and BUZZ outputs are effective. In case these functions are not necessary, make them invalid by programming. The TMJ-1 and TMJ-2, in combination, can be used for remote controlled data transmission. Regarding the remote controlled data transmission, see section 13.3.3, Remote Controlled Data Transmission. 13.3.2 8-bit Reload Timer (TMJ-2) The TMJ-2 is an 8-bit down-counting reload timer. As the clock source, dividing clock, edge signals through the ,54 pin or the underflow signals from the TMJ-1 are being used. By selecting the edge signals through the ,54 pin, it can also be used as an event counter. While it is working as an event counter, its reloading function is workable simultaneously. When data are written into the reloading register, these data will be written into the counter simultaneously. Also, when the counter underflows, reloading will be made to the data counter of the reloading register. When the counter underflows, TMJ2I interrupt requests will be issued. The TMJ-2 and TMJ-1, in combination, can be used as a 16-bit reload timer. For more information on the 16-bit reload timer, see section 13.3.1, 8-bit Reload Timer (TMJ-1). The TMJ-2 and TMJ-1, in combination, can be operated by remote controlled data transmission. Rev. 0.1, 11/98, page 259 of 975 Regarding the remote controlled data transmission, see section 13.3.3, Remote Controlled Data Transmission. Rev. 0.1, 11/98, page 260 of 975 13.3.3 Remote Controlled Data Transmission The Timer J is capable of making remote controlled data transmission. The carrier frequencies for the remote controlled data transmission can be generated by the TMJ-1 and the burst width duration and the space width duration can be setup by the TMJ-2. The data having been written into the reloading register TMJ-1 and into the burst/space duration register (TLK) of the TMJ-2 will be loaded to the counter at the same time as the remote controlled data transmission starts. (Remote controlled data transmission starting bit (ST) 1) While remote controlled data transmission is being made, the contents of the burst/space duration register will be loaded to the counter only while reloading is being made by underflow signals. Even when a writing is made to the burst/space duration register while remote controlled data transmission is being made, reloading operation will not be made until an underflow signal is issued. The TMJ-2 issues TMJ2I interrupt requests by the underflow signals. The TMJ-1 performs normal reloading operation (including the TMJ1I interrupt requests). Figure 13.2 shows the output waveform for the remote controlled data transmission function. When a shift to the low power consumption mode is effected while remote controlled data transmission is being made, the ST bit will be cleared to 0. When resuming the remote controlled data transmission after returning to the active mode, write 1. TMJ-1 can generate the carrier frequencies Remote controlled data transmission outputs Burst width Space width TMJ-2 toggle output =1 Setting the remote controlled mode Setting the burst width ST bit 1 Setting the space width Underflow Burst width TMJ-2 toggle output =0 TMJ-2 toggle output = 1 Setting the burst width Setting the space width Underflow Underflow Figure 13.2 Remote Controlled Data Transmission Output Waveform Rev. 0.1, 11/98, page 261 of 975 Figure 13.3 Timer Output Timing Rev. 0.1, 11/98, page 262 of 975 Remote controlled data transmission output TMO REMOout UDF TMJ-2 TMO (BUZZ) UDF TMJ-1 When the Timer J is set to the remote controlled operation mode, since the start bit (ST) is being set or cleared in synchronization with the inputting clock to the TMJ-2, a delay upto a cycle of the inputting clock at the maximum occurs, namely, after the ST bit has been set to 1 until the remote controlled data transmission starts. Consequently, when the TLK is updated during the period after setting the ST bit to 1 until the next cycle of the inputting clock comes, the initial burst width will be changed like shown in figure 13.4. Therefore, when making remote controlled data transmission, determine I/O of the TGL bit at the time of the first burst width control operation without fail. (Or, set the space width to the TLK after waiting for a cycle of the inputting clock.) After that, operations can be continued by interrupts. Similarly, pay attention to the control works when ending remote controlled data transmission. Exemple) 1) 2) 3) 4) 5] 6] Set the burst width with the TLK. ST bit 1 Execute the procedure 4) if the TGL flag = 1. Set the space width with the TLK under the status where the TGL flag = 1. Make TMJ-2 interrupt. Set the burst width with the TLK. : n) After making TMJ-2 interrupt, make setting of the ST 0 under the status where the TGL flag = 0. Inputting clock to the TMJ-2 Interrupt Interrupt TGL flag ST 1 TLK setting (Burst width) (B) Burst width according to (B) Remote controlled data transmission starts here. Delay Space width according to (S) ST 0 Delay The period during which the space width settig can be made. (S) If an updating is made with the TLK during this period, the burst width will be changed. Stopping the remote controlled data transmission Figure 13.4 Controls of the Remote Controlled Data Transmission Rev. 0.1, 11/98, page 263 of 975 Rev. 0.1, 11/98, page 264 of 975 Section 14 Timer L 14.1 Overview The Timer A is an 8-bit up/down counter using the control pulses or the CFG division signals as the clock source. 14.1.1 Features Features of the Timer L are as follows: * Choices of two different types of internal clocks (/128 and /64), DVCFG2 (CFG division signal 2), PB and REC-CTL (control pulses) are available for your selection. In case the PB-CTL is not available, such as when reproducing un-recorded tapes, tape count can be made by the DVCFG2. Selection of the leading edge or the trailing edge is workable with the CTL pulse counting. * Interrupts occur when the counter overflows or underflows and at occurrences of compare match clear. * It is possible to switch over between the up-counting and down-counting functions with the counter. Rev. 0.1, 11/98, page 265 of 975 14.1.2 Block Diagram Figure 14.1 shows a block diagram of the Timer L. LMR INTERNAL CLOCK /128 /64 Read LTC PB and REC-CTL OVF/UDF Internal data bus DVCFG2 Reloading Match clear Comparator Interrupting circuit RCR Write [Legend] DVCFG2 : Division signal 2 of the CFG PB and REC-CTL : Control pluses necessary when making reproduction and storage LMR : Timer L mode register LTC : Linear time counter RCR : Reload/compare match register OVF : Overflow UDF : Underflow Figure 14.1 Block Diagram of the Timer L Rev. 0.1, 11/98, page 266 of 975 Interrupt request 14.1.3 Register Configuration Table 14.1 shows the register configuration of the Timer L. The linear time counter (LTC) and the reload compare patch register (RCR) are being allocated to the same address. Reading or writing determines the accessing register. Table 14.1 Register Configuration Name Abbrev. R/W Size Initial Value Address* Timer L mode register LMR R/W Byte H'30 H'D112 Linear time counter LTC R Byte H'00 H'D113 Reload/compare match register RCR W Byte H'00 H'D113 Note: * Lower 16 bits of the address. Rev. 0.1, 11/98, page 267 of 975 14.2 Descriptions of Respective Registers 14.2.1 Timer L Mode Register (LMR) Bit : Initial value : 7 6 5 4 3 2 1 0 LMIF LMIE -- -- IMR3 IMR2 IMR1 IMR0 0 R/W : R /(W)* 0 1 1 0 0 0 0 R/W -- -- R/W R/W R/W R/W Note: * Only 0 can be written to clear the flag. The timer L mode register A (LMR) is an 8-bit read/write register which works to control the interrupts, to select between up-counting and down-counting and to select the clock source. When reset, the LMR is initialized to H'30. Bit 7: Timer L Interrupt Requesting Flag (LMIF) This is the Timer L interrupt requesting flag. It indicates occurrence of overflow or underflow of the LTC or occurrence of compare match clear. Bit 7 LMIF 0 1 Description [Clearing conditions] (Initial value) When 0 is written after reading 1 [Setting conditions] When the LTC overflows, underflows or when compare match clear has occurred Rev. 0.1, 11/98, page 268 of 975 Bit 6: Enabling Interrupt of the Timer L (LMIE) This bit works to permit/prohibit occurrence of interrupt of the Timer L when the LTC overflows, underflows or when compare match clear has occurred. Bit 6 LMIE Description 0 Prohibits occurrence of interrupt of the Timer L 1 Permits occurrence of interrupt of the Timer L (Initial value) Bits 5 and 4: Reserved These bits are reserved. When they are read, 1 will always be readout. Writes are disabled. Bit 3: Up-count/Down-count Control (LMR3) This bit is for selection if the Timer L is to be controlled to the up-counting function or downcounting function. (1) When Controlled to the Up-counting Function When any other values than H'00 are input to the RCR, the LTC will be cleared to H'00 before starting counting up. When the LTC value and the RCR value match, the LTC will be cleared to H'00. Also, interrupt requests will be issued by the match signal. (Compare patch clear function) When H'00 is set to the RCR, the counter makes 8-bit interval timer operation to issue a interrupt request when overflowing occurs. (Interval timer function) (2) When Controlled to the Down-counting Function When a value is set to the RCR, the set value is reloaded to the LTC and counting down starts from that value. When the LTC underflows, the value of the RCR will be reloaded to the LTC. Also, when the LTC underflows, a interrupt request will be issued. (Auto reload timer function) Bit 3 LMR3 Description 0 Controlling to the up-counting function 1 Controlling to the up-counting function (Initial value) Rev. 0.1, 11/98, page 269 of 975 Bits 2 to 0: Clock Selection (LMR2 to LMR0) The bits LMR2 to LMR0 work to select the clock to input to the Timer L. Selection of the leading edge or the trailing edge is workable for counting by the PB and the REC-CTL. Bit 2 Bit 1 Bit 0 R2 LMR1 LMR0 Description 0 0 0 Counts at the rising edge of the PB and REC-CTL (Initial value) 1 Counts at the falling edge of the PB and REC-CTL 1 * Counts the DVCFG2 0 * Counts at /128 of the internal clock 1 * Counts at /64 of the internal clock 1 Note: * 14.2.2 Don't care. Linear Time Counter (LTC) 7 6 5 4 3 2 1 0 LTC7 LTC6 LTC5 LTC4 LTC3 LTC2 LTC1 LTC0 Initial value : 0 0 0 0 0 0 0 0 R/W : R R R R R R R R Bit : The linear time counter (LTC) is a readable 8-bit up/down-counter. The inputting clock can be selected by the LMR2 to LMR0 bits of the LMR. When reset, the LTC is initialized to H'00. Rev. 0.1, 11/98, page 270 of 975 14.2.3 Reload/Compare Match Register (RCR) 7 6 5 4 3 2 1 0 RCR7 RCR6 RCR5 RCR4 RCR3 RCR2 RCR1 RCR0 Bit : Initial value : 0 0 0 0 0 0 0 0 R/W : W W W W W W W W The reload/compare match register (RCR) is an 8-bit write only register. When the Timer L is being controlled to the up-counting function, when a compare match value is set to the RCR, the LTC will be cleared at the same time and the LTC will then start counting up from the initial value (H'00). While, when the Timer L is being controlled to the down-counting function, when a reloading value is set to the RCR, the same value will be loaded to the LTC at the same time and the LTC will then start counting up from said value. Also, when the LTC underflows, the value of the RCR will be reloaded to the LTC. When reset, the RCR is initialized to H'00. 14.2.4 Module Stop Control Register (MSTPCR) MSTPCRH Bit : 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode. When the MSTP12 bit is set to 1, the Timer L stops its operation at the ending point of the bus cycle to shift to the module stop mode. For more information, see section 4.5, Module Stop Mode. When reset, the MSTPCR is initialized to H'FFFF. Rev. 0.1, 11/98, page 271 of 975 Bit 4: Module Stop (MSTP12) This bit works to designate the module stop mode for the Timer L. MSTPCRH Bit 4 MSTP12 Description 0 Cancels the module stop mode of the Timer L 1 Sets the module stop mode of the Timer L 14.3 (Initial value) Operation The Timer L is an 8-bit up/down counter. The inputting clock for the Timer L can be selected by the LMR2 to LMR0 bits of the LMR from the choices of the internal clock (/128 and /64), DVCDG2, PB and REC-CTL. The Timer L is provided with three different types of operation modes, namely, the compare match clear mode when controlled to the up-counting function, the auto reloading mode when controlled to the down-counting function and the interval timer mode. Respective operation modes and operation methods will be explained below. 14.3.1 Compare Match Clear Operation When the LMR3 bit of the LMR is cleared to 0, the Timer L will be controlled to the upcounting function. When any other values than H'00 are written into the RCR, the LTC will be cleared to H'00 simultaneously before starting counting up. Figure 14.2 shows the clear timing of the LTC. When the LTC value and the RCR value match (compare match), the LTC readings will be cleared to H'00 to resume counting from H'00. Figure 14.3 indicated on the next page shows the compare match clear timing. 1 state Write signal N RCR H' 00 LTC Figure 14.2 RCR Writing and LTC Clearing Timing Chart Rev. 0.1, 11/98, page 272 of 975 PB-CTL Count-up signal Compare match clear signal RCR LTC N N-1 N H' 00 Interrupt request Figure 14.3 Compare Match Clearing Timing Chart (In case the rising edge of the PB-CTL is selected) Rev. 0.1, 11/98, page 273 of 975 Rev. 0.1, 11/98, page 274 of 975 Section 15 Timer R 15.1 Overview The Timer R consists of triple 8-bit down-counters. It carries VCR mode identification function and slow tracking function in addition to the reloading function and event counter function. 15.1.1 Features The Timer R consists of triple 8-bit reloading timers. By combining the functions of three units of reloading timers/counters and by combining three units of timers, it can be used for the following applications: (1) Applications making use of the functions of three units of reloading timers. (2) For identification of the VCR mode. (3) For reel controls. (4) For acceleration and braking of the capstan motor when being applied to intermittent movements. (5) Slow tracking mono-multi applications. 15.1.2 Block Diagram The Timer R consists of three units of reload timer counters, namely, two units of reload timer counters equipped with capturing function (TMRU-1 and TMRU-2) and a unit of reload timer counter (TMRU-3). Figure 15.1 is a block diagram of the Timer R. Rev. 0.1, 11/98, page 275 of 975 Figure 15.1 Block Diagram of the Timer R Rev. 0.1, 11/98, page 276 of 975 Notes: DVCTL Reloading register (8 bits) Reloading register (8 bits) TMRL3 TMRU-3 Down-counter (8 bits) Capture register (8 bits) *1 Underflow Down-counter Under- (8 bits) flow TMRU-1 *2 TMRCP1 RLD/ CAP TMRL1 S R Q TMRL2 AC/BR CLR2 Resetting Available/ Not available Capture register (8 bits) TMRCP2 Res SLW CAPF CP/ SLM Res braking Acceleration Acceleration/ braking R Q Down-counter S (8 bits) Under- CFG mask F/F TMRU-2 flow Reloading register (8 bits) PS21,20 Clock selection (2 bits) Internal bus LAT Latch clock selection Clock source /64 /128 /256 Reloading Available/ not available RLD Internal bus RLCK Reloading clock selection TMRI3 Interrupt request TMRI1 Interrupt request TMRI2 Interrupt request 1. When the DVCTL is being used as the clock source, reloading will be made when the counter underflows and when the dividing clock is being used as the clock source, reloading will be made by the DVCTL. 2. When the LAT bit = 0, the capture signal against the TMRU-1 will not be output. Clock selection (2 bits) PS31,30 Clock sources /1024 /2048 /4096 External signals IRQ3 CFG Clock sources /4 /256 /512 CPS PS11,10 Clock selection (2 bits) Interrupting circuit 15.1.3 Pin Configuration Table 15.1 shows the pin configuration of the Timer R. Table 15.1 Pin Configuration Name Abbrev. I/O Function Input capture inputting pin ,54 Input Input capture inputting for the Timer R 15.1.4 Register Configuration Table 15.2 shows the register configuration of the Timer R. Table 15.2 Register Configuration Name Abbrev. R/W Size Initial Value Address Timer R mode register 1 TMRM1 R/W Byte H'00 H'D118 Timer R mode register 2 TMRM2 R/W Byte H'00 H'D119 Timer R control/status register TMRCS R/W Byte H'03 H'D11F Timer R capture register 1 TMRCP1 R Byte H'FF H'D11A Timer R capture register 2 TMRCP2 R Byte H'FF H'D11B Timer R load register 1 TMRL1 W Byte H'FF H'D11C Timer R load register 2 TMRL2 W Byte H'FF H'D11D Timer R load register 3 TMRL3 W Byte H'FF H'D11E Note: Memories of respective registers will be preserved even under the low power consumption mode. Nonetheless, the CAPF flag and SLW flag of the TMRM2 will be cleared to 0. Rev. 0.1, 11/98, page 277 of 975 15.2 Descriptions of Respective Registers 15.2.1 Timer R Mode Register 1 (TMRM1) 7 6 5 4 3 2 1 0 CLR2 AC/BR RLD RLCK PS21 PS20 RLD/CAP CPS Bit : Initial value : R/W : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The timer R mode register 1 (TMRM1) works to control the acceleration and braking processes and to select the inputting clock for the TMRU-2. This is an 8-bit read/write register. When reset, the TMRM1 is initialized to H'00. Bit 7: Selecting Clearing/Not Clearing of TMRU-2 (CLR2) This bit is used for selecting if the TMRU-2 counter reading is to be cleared or not as it is captured. Bit 7 CLR2 Description 0 TMRU-2 counter reading is not to be cleared as soon as it is captured. (Initial value) 1 TMRU-2 counter reading is to be cleared as soon as it is captured Bit 6: Selecting the Acceleration/Braking Processing (AC/BR) This bit works to control occurrences of interrupt requests to detect completion of acceleration or braking while the capstan motor is making intermittent revolutions. For more information, see section 15.3.6, Acceleration and Braking of the Capstan Motor. Bit 6 AC/BR Description 0 Acceleration 1 Braking Rev. 0.1, 11/98, page 278 of 975 (Initial value) Bit 5: Selection if Using the TMRU-2 for Reloading or Not Doing So (RLD) This bit is used for selecting if the TMRU-2 reload function is to be turned on or not. Bit 5 RLD Description 0 Not using the TMRU-2 as the reload timer 1 Using the TMRU-2 as the reload timer (Initial value) Bit 4: Selection of the Reloading Timing for the TMRU-2 (RLCK) This bit works to select if the TMRU-2 is reloading by the CFG or by underflowing of the TMRU-2 counter. This choice is valid only when the bit 5 (RLD) is being set to 1. Bit 4 RLCK Description 0 Reloading at the rising edge of the CFG 1 Reloading by underflowing of the TMRU-2 (Initial value) Bits 3 and 2: Selecting the Clock Source for the TMRU-2 (PS21 and PS20) These bits work to select the inputting clock to the TMRU-2. Bit 3 Bit 2 PS21 PS20 Description 0 0 Counting by underflowing of the TMRU-1 1 Counting by the PSS, /256 0 Counting by the PSS, /128 1 Counting by the PSS, /64 1 (Initial value) Bit 1: Selection of the Operation Mode of the TMRU-1 (RLD/CAP) This bit works to select if the operation mode of the TMRU-1 is reload timer mode or capture timer mode. Under the capture timer mode, reloading operation will not be made. Also, the counter reading will be cleared as soon as capture has been made. Bit 1 RLD/CAP Description 0 The TMRU-1 works as the reloading timer 1 The TMRU-1 works as the capture timer (Initial value) Rev. 0.1, 11/98, page 279 of 975 Bit 0: Selection of the Capture Signals of the TMRU-1 (CPS) In combination with the LAT bit (Bit 7) of the TMR2, this bit works to select the capture signals of the TMRU-1. This bit becomes valid when the LAT bit is being set to 1. It will also become valid when the RLD/CAP bit (Bit 1) is being set to 1. Nonetheless, it will be invalid when the RLD/CAP bit (Bit 1) is being set to 0. Bit 0 CPS Description 0 Capture signals at the rising edge of the CFG 1 Capture signals at the edge of the IRQ3 15.2.2 (Initial value) Timer R Mode Register 2 (TMRM2) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 LAT PS11 PS10 PS31 PS30 CP/SLM CAPF SLW 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/(W)* R/(W)* The timer R mode register 2 (TMRM2) is an 8-bit read/write register which works to identify the operation mode and to control the slow tracking processing. When reset, the TMRM2 is initialized to H'00. Note: * The CAPF bit and the SLW bit, respectively, works to latch the interrupt causes and writing 0 only is valid. Consequently, when these bits are being set to 1, respective interrupt requests will not be issued. Therefore, it is necessary to check these bits during the course of the interrupt processing routine to have them cleared. Also, priority is given to the set and, when an interrupt cause occur while the a clearing command (BCLR, MOV, etc.) is being executed, the CAPF bit and the SLW bit will not be cleared respectively and it thus becomes necessary to pay attention to the clearing timing. Rev. 0.1, 11/98, page 280 of 975 Bit 7: Selection of the Capture Signals of the TMRU-2 (LAT) In combination with the CPS bit (Bit 0) of the TMRM1, this bit works to select the capture signals of the TMRU-2. TMRM2 TMRM1 Bit 7 Bit 0 LAT CPS Description 0 * Captures when the TMRU-3 underflows 1 0 Captures at the rising edge of the CFS 1 Captures at the edge of the IRQ3 Note: * (Initial value) Don't care. Bits 6 and 5: Selecting the Clock Source for the TMRU-1 (PS11 and PS10) These bits work to select the inputting clock to the TMRU-1. Bit 6 Bit 5 PS11 PS10 Description 0 0 Counting at the rising edge of the CFG 1 Counting by the PSS, /4 0 Counting by the PSS, /256 1 Counting by the PSS, /512 1 (Initial value) Bits 4 and 3: Selecting the Clock Source for the TMRU-3 (PS31 and PS30) These bits work to select the inputting clock to the TMRU-3. Bit 4 Bit 3 PS31 PS30 Description 0 0 Counting at the rising edge of the DVCTL from the dividing circuit.(Initial value) 1 Counting by the PSS, /4096 0 Counting by the PSS, /2048 1 Counting by the PSS, /1024 1 Rev. 0.1, 11/98, page 281 of 975 Bit 2: Selection of Interrupt Causes (CP/SLM) This bit works to select the interrupt causes for the TMRI3. Bit 2 CP/SLM Description 0 Makes interrupt requests upon the capture signals of the TMRU-2 valid (Initial value) 1 Makes interrupt requests upon ending of the slow tracking mono-multi valid Bit 1: Capture Signal Flag (CAPF) This is a flag being set out by the capture signal of the TMRU-2. Although both reading/writing are possible, 0 only is valid for writing. Also, priority is being given to the set and, when the "capture signal" and "writing 0" occur simultaneously, this flag bit remains being set to 1 and the interrupt request will not be issued and it is necessary to be attentive about this fact. When the CP/SLM bit (Bit 2) is being set to 1, this CAPF bit should always be set to 0. The CAPF flag is cleared to 0 under the low power consumption mode. Bit 1 CAPF Description 0 [Clearing conditions] When 0 is written after reading 1 1 [Setting conditions] At occurrences of the TMRU-2 capture signals while the CP/SLM bit is being set to 0 (Initial value) Bit 0: Slow Tracking Mono-multi Flag (SLW) This is a flag being set out when the slow tracking mono-multi processing ends. Although both reading/writing are possible, 0 only is valid for writing. Also, priority is being given to the set and, when "ending of the slow tracking mono-multi processing" and "writing 0" occur simultaneously, this flag bit remains being set to 1 and the interrupt request will not be issued and it is necessary to be attentive about this fact. When the CP/SLM bit (Bit 2) is being set to 0, this SLW bit should always be set to 0. The SLW flag is cleared to 0 under the low power consumption mode. Bit 0 SLW Description 0 [Clearing conditions] When 0 is written after reading 1 1 [Setting conditions] When the slow tracking mono-multi processing ends while the CP/SLM bit is being set to 1 Rev. 0.1, 11/98, page 282 of 975 (Initial value) 15.2.3 Timer R Control/Status Register (TMRCS) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 TMRI3E TMRI2E TMRI1E TMRI3 TMRI2 TMRI1 -- -- 0 0 0 0 0 0 1 1 R/W R/W R/W R/(W)* R/(W)* R/(W)* -- -- Note: * Only 0 can be written to clear the flag. The timer R control/status register (TMRCS) works to control the interrupts of the Timer R. The TMRCS is an 8-bit read/write register. When reset, the TMRCS is initialized to H'03. Bit 7: Enabling the TMRI3 Interrupt (TMRI3E) This bit works to permit/prohibit occurrence of the TMRI3 interrupt when an interrupt cause being selected by the CP/SLM bit of the TMRM2 has occurred, such as occurrences of the TMRU-2 capture signals or when the slow tracking mono-multi processing ends, and the TMRI3 has been set to 1. Bit 7 TMRI3E Description 0 Prohibits occurrences of TMRI3 interrupts 1 Permits occurrences of TMRI3 interrupts (Initial value) Bit 6: Enabling the TMRI2 Interrupt (TMRI2E) This bit works to permit/prohibit occurrence of the TMRI2 interrupt when the TMRI2 has been set to 1 by issuance of the underflow signal of the TMRU-2 or by ending of the slow tracking mono-multi processing. Bit 6 TMRI2E Description 0 Prohibits occurrences of TMRI2 interrupts 1 Permits occurrences of TMRI2 interrupts (Initial value) Rev. 0.1, 11/98, page 283 of 975 Bit 5: Enabling the TMRI1 Interrupt (TMRI1E) This bit works to permit/prohibit occurrence of the TMRI1 interrupt when the TMRI1 has been set to 1 by issuance of the underflow signal of the TMRU-1. Bit 5 TMRI1E Description 0 Prohibits occurrences of TMRI1 interrupts 1 Permits occurrences of TMRI1 interrupts (Initial value) Bit 4: TMRI3 Interrupt Requesting Flag (TMRI3) This is the TMRI3 interrupt requesting flag. It indicates occurrence of an interrupt cause being selected by the CP/SLM bit of the TMRM2, such as occurrences of the TMRU-2 capture signals or ending of the slow tracking mono-multi processing. Bit 4 TMRI3 Description 0 [Clearing conditions] When 0 is written after reading 1 1 [Setting conditions] At occurrence of the interrupt cause being selected by the CP/SLM bit of the TMRM2 (Initial value) Bit 3: TMRI2 Interrupt Requesting Flag (TMRI2) This is the TMRI2 interrupt requesting flag. It indicates occurrences of the TMRU-2 underflow signals or ending of the acceleration/braking processing of the capstan motor. Bit 3 TMRI2 Description 0 [Clearing conditions] When 0 is written after reading 1 1 [Setting conditions] At occurrences of the TMRU-2 underflow signals or ending of the acceleration /braking processing of the capstan motor Rev. 0.1, 11/98, page 284 of 975 (Initial value) Bit 2: TMRI1 Interrupt Requesting Flag (TMRI1) This is the TMRI1 interrupt requesting flag. It indicates occurrences of the TMRU-1 underflow signals. Bit 2 TMRI1 Description 0 [Clearing conditions] When 0 is written after reading 1. 1 [Setting conditions] When the TMRU-1 underflows. (Initial value) Bits 1 and 0: Reserved These bits are reserved. When they are read, 1 will always be readout. Writes are disabled. 15.2.4 Timer R Capture Register 1 (TMRCP1) Bit : 7 6 5 4 3 2 1 0 TMRC17 TMRC16 TMRC15 TMRC14 TMRC13 TMRC12 TMRC11 TMRC10 Initial value : 1 1 1 1 1 1 1 1 R/W : R R R R R R R R The timer R capture register 1 (TMRCP1) works to store the capture data of the TMRU-1. During the course of the capturing operation, the TMRU-1 counter readings are captured by the TMRCP1 at the CFG edge or the IRQ3 edge. The capturing operation of the TMRU-1 is being performed using 16 bits, in combination with the capturing operation of the TMRU-2. The TMRCP1 is an 8-bit read only register. When reset, the TMRCS is initialized to H'FF. Notes: 1. When the TMRCP1 is readout while the capture signal is being received, the reading data become unstable. Pay attention to the timing for reading out. 2. When a shift to the low power consumption mode is made while the capturing operating is in progress, the counter reading becomes unstable. After returning to the active mode, always write "H'FF" into the TMRL1 to initialize the counter. Rev. 0.1, 11/98, page 285 of 975 15.2.5 Timer R Capture Register 2 (TMRCP2) Bit : 7 6 5 4 3 2 1 0 TMRC27 TMRC26 TMRC25 TMRC24 TMRC23 TMRC22 TMRC21 TMRC20 Initial value : 1 1 1 1 1 1 1 1 R/W : R R R R R R R R The timer R capture register 2 (TMRCP2) works to store the capture data of the TMRU-2. At each CFG edge, IRQ3 edge, or at occurrence of underflow of the TMRU-3, the TMRU-2 counter readings are captured by the TMRCP2. The TMRCP2 is an 8-bit read only register. When reset, the TMRCS will be initialized into H'FF. Notes: 1. When the TMRCP2 is readout while the capture signal is being received, the reading data become unstable. Pay attention to the timing for reading out. 2. When a shift to the low power consumption mode is made, the counter reading becomes unstable. After returning to the active mode, always write "H'FF" into the TMRL2 to initialize the counter. 15.2.6 Timer R Load Register 1 (TMRL1) 7 6 5 4 3 2 1 0 TMR17 TMR16 TMR15 TMR14 TMR13 TMR12 TMR11 TMR10 Initial value : 1 1 1 1 1 1 1 1 R/W : W W W W W W W W Bit : The timer R load register 1 (TMRL1) is an 8-bit write only register which works to set the load value of the TMRU-1. When a load value is set to the TMRL1, the same value will be set to the TMRU-1 counter simultaneously and the counter starts counting down from the set value. Also, when the counter underflows during the course of the reload timer operation, the TMRL1 value will be set to the counter. When reset, the TMRL1 is initialized to H'FF. Rev. 0.1, 11/98, page 286 of 975 15.2.7 Timer R Load Register 2 (TMRL2) 7 6 5 4 3 2 1 0 TMR27 TMR26 TMR25 TMR24 TMR23 TMR22 TMR21 TMR20 Initial value : 1 1 1 1 1 1 1 1 R/W : W W W W W W W W Bit : The timer R load register 2 (TMRL2) is an 8-bit write only register which works to set the load value of the TMRU-2. When a load value is set to the TMRL2, the same value will be set to the TMRU-2 counter simultaneously and the counter starts counting down from the set value. Also, when the counter underflows or a CFG edge is detected during the course of the reload timer operation, the TMRL2 value will be set to the counter. When reset, the TMRL2 is initialized to H'FF. 15.2.8 Timer R Load Register 3 (TMRL3) Bit : 7 6 5 4 3 2 1 0 TMR37 TMR36 TMR35 TMR34 TMR33 TMR32 TMR31 TMR30 Initial value : 1 1 1 1 1 1 1 1 R/W : W W W W W W W W The timer R load register 3 (TMRL3) is an 8-bit write only register which works to set the load value of the TMRU-3. When a load value is set to the TMRL3, the same value will be set to the TMRU-3 counter simultaneously and the counter starts counting down from the set value. Also, when the counter underflows or a DVCTL edge is detected, the TMRL2 value will be set to the counter. (Reloading will be made by the underflowing signals when the DVCTL signal is selected as the clock source, and reloading will be made by the DVCTL signals when the dividing clock is selected as the clock source.) When reset, the TMRL3 is initialized to H'FF. Rev. 0.1, 11/98, page 287 of 975 15.2.9 Module Stop Control Register (MSTPCR) MSTPCRH Bit : 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The MSTPCR are 8-bit read/write twin registers which work to control the module stop mode. When the MSTP11 bit is set to 1, the Timer R stops its operation at the ending point of the bus cycle to shift to the module stop mode. For more information, see section 4.5, Module Stop Mode. When reset, the MSTPCR is initialized to H'FFFF. Bit 3: Module Stop (MSTP11) This bit works to designate the module stop mode for the Timer R. MSTPCRH Bit 3 MSTP11 Description 0 Cancels the module stop mode of the Timer R 1 Sets the module stop mode of the Timer R Rev. 0.1, 11/98, page 288 of 975 (Initial value) 15.3 Operation 15.3.1 Reload Timer Counter Equipped with Capturing Function TMRU-1 The reload timer counter equipped with capturing function, TMRU-1, consists of an 8-bit downcounter, a reloading register and a capture register. The clock source can be selected from among the leading edge of the CFG signals and three types of dividing clocks. It is also selectable whether using it as a reload counter or as a capture counter. Even when the capturing function is selected, the counter readings can be updated by writing the values into the reloading register. When the counter underflows, the TMRI1 interrupt request will be issued. The initial values of the TMRU-1 counter, reloading register and capturing register are all H'FF. (1) Operation of the Reload Timer When a value is written into to the reloading register, the same value will be written into the counter simultaneously. Also, when the counter underflows, the reloading register value will be reloaded to the counter. The TMRU-1 is a dividing circuit for the CFG. In combination with the TMRU-2 and TMRU-3, it can also be used for the mode identification purpose. (2) Capturing Operation Capturing operation is carried out in combination with the TMRU-2 using the combined 16 bits. It can be so programmed that the counter may be cleared by the capture signal. The CFG edges or IRQ3 edges are used as the capture signals. It is possible to issue the TMRI3 interrupt request by the capture signal. In addition to the capturing function being worked out in combination with the TMRU-2, the TMRU-1 can be used as a 16-bit CFG counter. Selecting the IRQ3 as the capture signal, the CFG within the duration of the reel pulse being input into the ,54 pin can be counted by the TMRU-1. Rev. 0.1, 11/98, page 289 of 975 15.3.2 Reload Timer Counter Equipped with Capturing Function TMRU-2 The reload timer counter equipped with capturing function, TMRU-2, consists of an 8-bit downcounter, a reloading register and a capture register. The clock source can be selected from among the undedrflowing signal of the TMRU-1 and three types of dividing clocks. Also, although the reloading function is workable during its capturing operation, equipping or not of the reloading function is selectable. Even when without-reloading-function is chosen, the counter reading can be updated by writing the values to the reloading register. When the counter underflows, the TMRI2 interrupt request will be issued. The initial values of the TMRU-2 counter, reloading register and capturing register are all H'FF. (1) Operation of the Reload Timer When a value is written into to the reloading register, the same value will be written into the counter, simultaneously. Also, when the counter underflows, the reloading register value will be reloaded to the counter. The TMRU-2 can make acceleration and braking work for the capstan motor using the reload timer operation. (2) Capturing Operation Using the capture signals, the counter reading can be latched into the capturing register. As the capture signal, you can choose from among edges of the CFG, edges of the IRQ3 or the underflow signals of the TMRU-3. It is possible to issue the TMRI3 interrupt request by the capture signal. The capturing function (stopping the reloading function) of the TMRU-2, in combination with the TMRU-1 and TMRU-3, can also be used for the mode identification purpose. 15.3.3 Reload Counter Timer TMRU-3 The reload counter timer TMRU-3 consists of an 8-bit down-counter and a reloading register. Its clock source can be selected from between the undedrflowing signal of the counter and the edges of the DVCTL signals. (When the DVCTL signal is selected as the clock source, reloading will be effected by the underflowing signals and when the dividing clock is selected as the clock source, reloading will be effected by the DVCTL signals.) The reloading signal works to reload the reloading register value into the counter. Also, when a value is written into to the reloading register, the same value will be written into the counter, simultaneously. The initial values of the counter and the reloading register are H'FF. The underflowing signals can be used as the capturing signal for the TMRU-2. The TMRU-3 can also be used as a dividing circuit for the DVCTL. Also, in combination with the TMRU-1 and TMRU-2 (capturing function), the TMRU-3 can be used for the mode Rev. 0.1, 11/98, page 290 of 975 identification purpose. Since the divided signals of the DVCTL are being used as the clock source, CTL signals (DVCTL) conforming to the double speed can be input when making searches. These DVCTL signals can also be used for phase controls of the capstan motor. Also, by selecting the dividing clock as the clock source, it is possible to make a delay with the edges of the DVCTL to provide the slow tracking mono-multi function. 15.3.4 Mode Identification When making mode identification (2/4/6 identification) of the SP/LP/EP modes of reproducing tapes, the TMRU-1 (CFG dividing circuit), TMRU-2 (capturing function/without reloading function) and TMRU-3 (DVCTL dividing circuit) of the Timer R should be used. The Timer R will become to the aforementioned status after a reset. Under the aforementioned status, the divided CFG should be written into the reloading register of the TMRU-1 and divided DVCTL should be written into the reloading register of the TMRU3. When the TMRU-3 underflows, the counter value of the TMRU-2 is captured. Such capturing register value represents the number of the CFG within the DVCTL cycle. As aforementioned, the Timer R can work to count the number of the CFG corresponding to "n" times of DVCTL's or to identify the mode being searched. For exemplary settings for the register, see section 15.5.1, Mode Identification. 15.3.5 Reeling Controls CFG counts can be captured by making 16-bit capturing operation combining the TMRU-1 and TMRU-2. By choosing the IRQ3 as the capture signal, and by counting the CFG within the duration of the reel pulse being input through the ,54 pin, reeling controls, etc. can be effected. For exemplary settings for the register, see section 15.5.2, Reeling Controls. 15.3.6 Acceleration and Braking Processes of the Capstan Motor When making intermittent movements such as those for slow reproductions or for still reproductions, it is necessary to conduct quick accelerations and abrupt stoppings of the capstan motor. The acceleration and braking processes will function to check if the revolution of a capstan motor has reached the prescribed rate when accelerated or braked. For this purpose, the TMRU-2 (reloading function) should be used. When making accelerations: (1) Set the AC/BR bit of the TMRM1 to acceleration. (Set to 1). Also, use the rising edge of the CFG as the reloading signal. (2) Set the prescribed time on the CFG frequency to deem as the acceleration has been finished, into the reloading register. Rev. 0.1, 11/98, page 291 of 975 (3) The TMRU-2 will work to down-count the reloading data. (4) In case the acceleration has not been finished (in case the CFG signal is not input even when the prescribed time has elapsed = underflowing of down-counting has occurred), such underflowing works to set to CFG mask F/F (masking movement) and the reload timer will be cleared by the CFG. (5) When the acceleration has been finished (when the CFG signal is input before the prescribed time has elapsed = reloading movement has been made before the down counter underflows), an interrupt request will be issued because of the CFG. When making breaking: (1) Set the AC/BR bit of the TMRM1 to braking. (Clear to 0). Also, use the rising edge of the CFG as the reloading signal. (2) Set the prescribed time on the CFG frequency to deem as the braking has been finished, into the reloading register. (3) The TMRU-2 will work to down-count the reloading data. (4) In case the braking has not been finished (when the CFG signal is input before the prescribed time has elapsed = reloading movement has been made before the down counter underflows), the reload timer movement will continue. (5) When the acceleration has been finished (when the CFG signal is not input even when the prescribed time has elapsed = underflowing of down-counting has occurred), interrupt request will be issued because of the underflowing signal. The acceleration and braking processes should be employed when making special reproductions, in combination with the slow tracking mono-multi function being outlined below. For exemplary settings for the register, see section 15.5.4, Acceleration and Braking Processes of the Capstan Motor. 15.3.7 Slow Tracking Mono-multi Function When performing slow reproductions or still reproductions, the braking timing for the capstan motor is determined by use of the edge of the DVCTL signal. The slow tracking mono-multi function works to measure the time from the rising edge of the DVCTL signal down to the desired point to issue the interrupt request. In actual programming, this interrupt should be used to activate the brake of the capstan motor. The TMRU-3 should be used to perform time measurements for the slow tracking mono-multi function. Also, the braking process can be made using the TMRU-2. Figure 15.2 below shows the exemplary time series movements when a slow reproduction is being performed. For exemplary settings for the register, see section 15.5.3, Slow Tracking Mono-multi Function. Rev. 0.1, 11/98, page 292 of 975 Compensation for vertical vibrations (Supplementary V-pulse) HSW FG acceleration detection Accelerating the capstan motor Hi-Z Acceleration process DVCTL Interrupt Slow tracking moto-multi Slow tracking delay Braking the capstan motor Braking the drum motor FG stopping detection Reloading Reverse rotation Forward rotation Braking process Servo Compensation for horizontal vibrations Compensation for horizontal vibrations Frame feeds H.AmpSW C.Rotary [Legend] Hi-Z : High impedance state In case of 4-head SP mode. In case of 2-head application, H.AmpSW and C.Rotary should be "Low". Figure 15.2 Exemplary Time Series Movements when a Slow Reproduction Is Being Performed Rev. 0.1, 11/98, page 293 of 975 15.4 Interrupt Cause The interrupt causes for the Timer R are 3-causes of the TMRI3 bit through TMRI1 bit of the timer R control/status register (TMRCS). (a) Interrupts being caused by the underflowing of the TMRU-1 (TMRI1) These interrupts will constitute the timing for reloading with the TMRU-1. (b) Interrupts being caused by the underflowing of the TMRU-2 or by an end of the acceleration or braking process (TMRI2) When interrupts occur at the reload timing of the TMRU-2, clear the AC/BR (acceleration/braking) bit of the timer R mode register 1 (TMRM1) to 0. (c) Interrupts being caused by the capture signals of the TMRU-2 and by ending the slow tracking mono-multi process (TMRI3) Since these two interrupt causes are constituting the OR, it becomes necessary to determine which interrupt cause is occurring using the software. Respective interrupt causes are being set to the CAPF flag or the SLW flag of the timer R mode register 2 (TMRM2), have the software determine which. Since the CAPF flag and the SLW flag will not be cleared automatically, program the software to clear them. (Writing 0 only is valid for these flags.) Unless these flags are cleared, detection of the next cause becomes unworkable. Also, if the CP/SLM bit is changed leaving these flags un-cleared as they are, these flags will get cleared. Rev. 0.1, 11/98, page 294 of 975 15.5 Exemplary Settings for Respective Functions 15.5.1 Mode Identification When making mode identification (2/4/6 identification) of the SP/LP/EP modes of reproducing tapes, the TMRU-1 (CFG dividing circuit), TMRU-2 (capturing function/without reloading function) and TMRU-3 (DVCTL dividing circuit) of the Timer R should be used. The Timer R will become to the aforementioned status after a reset. Under the aforementioned status, the divided CFG should be written into the reloading register of the TMRU-1 and divided DVCTL should be written into the reloading register of the TMRU3. When the TMRU-3 underflows, the counter value of the TMRU-2 is captured. Such capturing register value represents the number of the CFG within the DVCTL cycle. As aforementioned, the Timer R can work to count the number of the CFG corresponding to "n" times of DVCTL's or to identify the mode being searched. * Exemplary settings (1) Setting the timer R mode register 1 (TMRM1) CLR2 bit (Bit 7) = 1: Works to clear after making the TMRU-2 capture. RLD bit (Bit 5) = 0: Sets the TMRU-3 without reloading function. PS21 and PS20 (Bits 3 and 2) = (0 and 0): The underflowing signals of the TMRU-1 are to be used as the clock source for the TMRU-2. RLD/CAP bit (Bit 1) = 0: The TMRU-1 has been set to make the reload timer operation. (2) Setting the timer R mode register 2 (TMRM2) LAT bit (Bit 7) = 0: The underflowing signals of the TMRU-3 are to be used as the capture signal for the TMRU-2. PS11 and PS10 (Bits 6 and 5) = (0 and 0): The leading edge of the CFG signal is to be used as the clock source for the TMRU-1. PS31 and PS30 (Bits 4 and 3) = (0 and 0): The leading edge of the DVCTL signal is to be used as the clock source for the TMRU-3. CP/SLM bit (Bit 2) = 0: The capture signal is to work to issue the TMRI3 interrupt request. (3) Setting the timer R load register 1 (TMRL1) Set the dividing value for the CFG. The set value should become (n - 1) when divided by "n". (4) Setting the timer R load register 3 (TMRL3) Set the dividing value for the DVCTL. The set value should become (n - 1) when divided by "n". Rev. 0.1, 11/98, page 295 of 975 15.5.2 Reeling Controls CFG counts can be captured by making 16-bit capturing operation combining the TMRU-1 and TMRU-2. By choosing the IRQ3 as the capture signal, and by counting the CFG within the duration of the reel pulse being input through the ,54 pin, reeling controls, etc. can be effected. * Exemplary settings (1) Setting P13/,54 pin as the ,54 pin Set the PMR13 bit (Bit 3) of the port mode register 1 (PMR1) to 1. See section 10.3.2, Port Mode Register (PMR1). (2) Setting the timer R mode register 1 (TMRM1) CLR2 bit (Bit 7) = 1: Works to clear after making the TMRU-2 capture. PS21 and PS20 (Bits 3 and 2) = (0 and 0): The underflowing signals of the TMRU-1 are to be used as the clock source for the TMRU-2. RLD/CAP bit (Bit 1) = 1: The TMRU-1 has been set to make the capturing operation. CPS bit (Bit 0) = 1: The edge of the IRQ3 signal is to be used as the capture signal for the TMRU-1 and TMRU-2. (3) Setting the timer R mode register 2 (TMRM2) LAT bit (Bit 7) = 1: The edge of the IRQ3 signal is to be used as the capture signal for the TMRU-1 and TMRU-2. PS11 and PS10 (Bits 6 and 5) = (0 and 0): The rising edge of the CFG signal is to be used as the clock source for the TMRU-1. CP/SLM bit (Bit 2) = 0: The capture signal is to work to issue the TMRI3 interrupt request. 15.5.3 Slow Tracking Mono-multi Function When performing slow reproductions or still reproductions, the braking timing for the capstan motor is determined by use of the edge of the DVCTL signal. The slow tracking mono-multi function works to measure the time from the leading edge of the DVCTL signal down to the desired point to issue the interrupt request. In actual programming, this interrupt should be used to activate the brake of the capstan motor. The TMRU-3 should be used to perform time measurements for the slow tracking mono-multi function. Also, the braking process can be made using the TMRU-2. Rev. 0.1, 11/98, page 296 of 975 Exemplary settings (1) Setting the timer R mode register 2 (TMRM2) PS31 and PS30 (Bits 4 and 3) = Other than (0, 0): The dividing clock is to be used as the clock source for the TMRU-3. CP/SLM bit (Bit 2) = 1: The slow tracking delay signal is to work to issue the TMRI3 interrupt request. (2) Setting the timer R load register 3 (TMRL3) Set the slow tracking delay value. When the delay count is "n", the set value should be (n - 1). Regarding the delaying duration, see figure 15.2 Exemplary time series movements when a slow reproduction is being performed. 15.5.4 Acceleration and Braking Processes of the Capstan Motor When making intermittent movements such as those for slow reproductions or for still reproductions, it is necessary to conduct quick accelerations and abrupt stoppings of the capstan motor. The acceleration and braking processes will function to check if the revolution of a capstan motor has reached the prescribed rate when accelerated or braked. For this purpose, the TMRU-2 (reloading function) should be used. The acceleration and braking processes should be employed when making special reproductions, in combination with the slow tracking mono-multi function. Exemplary settings for the acceleration process (1) Setting the timer R mode register 1 (TMRM1) AC/BR bit (Bit 6) = 1: Acceleration process RLD bit (Bit 5) = 1: The TMRU-2 is to be used as the reload timer. RLCK bit (Bit 4) = 0: The TMRU-2 is to reload at the rising edge of the CFG. PS21 and PS20 (Bits 3 and 2) = Other than (0, 0): The dividing clock is to be used as the clock source for the TMRU-2. (2) Setting the timer R load register 2 (TMRL2) Set the count reading for the duration until the acceleration process finishes. When the count is "n", the set value should be (n - 1). Regarding the duration until the acceleration process finishes, see figure 15.2 Exemplary time series movements when a slow reproduction is being performed. Rev. 0.1, 11/98, page 297 of 975 Exemplary settings for the braking process (1) Setting the timer R mode register 1 (TMRM1) AC/BR bit (Bit 6) = 0: Braking process RLD bit (Bit 5) = 1: The TMRU-2 is to be used as the reload timer. RLCK bit (Bit 4) = 0: The TMRU-2 is to reload at the rising edge of the CFG. PS21 and PS20 (Bits 3 and 2) = Other than (0, 0): The dividing clock is to be used as the clock source for the TMRU-2. (2) Setting the timer R load register 2 (TMRL2) Set the count reading for the duration until the braking process finishes. When the count is "n", the set value should be (n - 1). Regarding the duration until the braking process finishes, see figure 15.2 Exemplary time series movements when a slow reproduction is being performed. Rev. 0.1, 11/98, page 298 of 975 Section 16 Timer X1 16.1 Overview The Timer X1 is capable of outputting two different types of independent waveforms using the free running counter (FRC) as the basic means and it is also applicable to measurements of the durations of input pulses and the cycles external clocks. 16.1.1 Features Listed below are the features of the Timer X1. * Choices of 4 different types of counter inputting clocks are available for your selection. You can select from among three different types of internal clocks (/4, /16 and /64) and the DVCFG. * Two independent output comparing functions Capable of outputting two different types of independent waveforms. * Four independent input capturing functions The rising edge or falling edge can be selected for use. The buffer operation can also be designated. * Counter clearing designation is workable. The counter readings can be cleared by compare match A. * Seven types of interrupt causes Comparing match x 2 causes, input capture x 4 causes and overflow x 1 cause are available for use and they can make respective interrupt requests independently. Rev. 0.1, 11/98, page 299 of 975 16.1.2 Block Diagram Figure 16.1 shows a block diagram of the Timer X1. FTIA* (HSW) FTIB* (VD) FTIC* (DVCTL) FTID* (NHSW) ICRA ICRB Input capture control ICRC ICRD TCRX Comparison circuit FRC (DVCFG) /4 / 16 / 64 Comparison circuit OCRA Output comparing output FTOA FTOB Internal data bus OCRB TOCR TCSRX TIER [Legend] TIER TCSRX FRC OCRA OCRB TCRX TOCR ICRA ICRB ICRC ICRD : Timer interrupt enabling register : Timer control/status register X : Free running counter : Output comparing register A : Output comparing register B : Timer control register X : Output comparing control register : Input capture register A : Input capture register B : Input capture register C : Input capture register D Note: * stands for the external terminal. ( ) stands for the internal signal. Figure 16.1 Block Diagram of the Timer X1 Rev. 0.1, 11/98, page 300 of 975 Interrupt request x 7 16.1.3 Pin Configuration Table 16.1 shows the pin configuration of the Timer X1. Table 16.1 Pin Configuration Name Abbrev. I/O Function Output comparing A output-pin FTOA Output Output pin for the output comparing A Output comparing B output-pin FTOB Output Output pin for the output comparing B Input capture A input-pin FTIA Input Input-pin for the input capture A Input capture B input-pin FTIB Input Input-pin for the input capture B Input capture C input-pin FTIC Input Input-pin for the input capture C Input capture D input-pin FTID Input Input-pin for the input capture D Rev. 0.1, 11/98, page 301 of 975 16.1.4 Register Configuration Table 16.2 shows the register configuration of the Timer X1. Table 16.2 Register Configuration Name Abbrev. R/W Timer interrupt enabling register TIER R/W *1 Initial Value Address*3 H'00 H'D100 H'00 H'D101 Timer control/status register X TCSRX R/ (W) Free running counter H FRCH R/W H'00 H'D102 Free running counter L FRCL R/W H'00 H'D103 Output comparing register AH OCRAH R/W H'FF H'D104 Output comparing register AL OCRAL R/W H'FF H'D105 Output comparing register BH OCRBH R/W H'FF H'D104 Output comparing register BL OCRBL R/W H'FF H'D105 Timer control register X TCRX R/W H'00 H'D106 Timer output comparing control register TOCR R/W H'00 H'D107 Input capture register AH ICRAH R H'00 H'D108 Input capture register AL ICRAL R H'00 H'D109 Input capture register BH ICRBH R H'00 H'D10A Input capture register BL ICRBL R H'00 H'D10B Input capture register CH ICRCH R H'00 H'D10C Input capture register CL ICRCL R H'00 H'D10D Input capture register DH ICRDH R H'00 H'D10E Input capture register DL ICRDL R H'00 H'D10F *2 *2 *2 *2 Notes: 1. Only 0 can be written to clear the flag for Bits 7 to 1. Bit 0 is readable/writable. 2. The addresses of the OCRA and OCRB are the same. Changeover between them are to be made by use of the TOCR bit and OCRS bit. 3. Lower 16 bits of the address. Rev. 0.1, 11/98, page 302 of 975 16.2 Descriptions of Respective Registers 16.2.1 Free Running Counter (FRC) Free running counter H (FRCH) Free running counter L (FRCL) FRC Bit : Initial value : R/W : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W FRCH FRCL The FRC is a 16-bit read/write up-counter which counts up by the inputting internal clock/external clock. The inputting clock is to be selected from the CKS1 and CKS0 of the TCRX. By the setting of the CCLRA bit of the TCSRX, the FRC can be cleared by comparing match A. When the FRC overflows (H'FFFF H'0000), the OVF of the TCSRX will be set to 1. At this time, when the OVIE of the TIER is being set to 1, an interrupt request will be issued to the CPU. Reading/writing can be made from and to the FRC through the CPU at 8-bit or 16-bit. The FRC is initialized to H'0000 when reset or under the standby mode, watch mode, subsleep mode, module stop mode or subactive mode. Rev. 0.1, 11/98, page 303 of 975 16.2.2 Output Comparing Register A and B (OCRA and OCRB) Output comparing register AH and BH (OCRAH and OCRBH) Output comparing register AL and BL (OCRAL and OCRBL) OCRA, OCRB Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W OCRAH, OCRBH OCRAL, OCRBL The OCR consists of twin 8-bit read/write registers (OCRA and OCRB). The contents of the OCR are always being compared with the FRC and, when the value of these two match, the OCFA and OCRB of the TCSRX will be set to 1. At this time, if the OCIAE and OCIB of the TIER are being set to 1, an interrupt request will be issued to the CPU. When performing compare matching, if the OEA and OEB of the TOCR are being set to 1, the level value having been set to the OLVLA and OLVLB of the TOCR will be output through the FTOA and FTOB pins. After resetting, 0 will be output through the FTOA and FTOB pins until the first compare matching occurs. Reading/writing can be made from and to the OCR through the CPU at 8-bit or 16-bit. The OCR is cleared to H'FFFF when reset or under the standby mode, watch mode, subsleep mode, module stop mode or subactive mode. Rev. 0.1, 11/98, page 304 of 975 16.2.3 Input Capture Register A Through D (ICRA Through ICRD) Input capture register AH to DH (ICRAH to ICRDH) Input capture register AL to DL (ICRAL to ICRDL) ICRA, ICRB, ICRC, ICRD Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : R R R R R R R R R R R R R R R R ICRAH, ICRBH, ICRCH, ICRDH ICRAL, ICRBL, ICRCL, ICRDL The ICR consists of four 16-bit read only registers (ICRA through ICRD). When the falling edge of the input capture input signal is detected, the value is transferred to the ICRA through ICRD. At this time, the ICFA through ICFD of the TCSRX are set to 1 simultaneously. At this time, if the IDIAE through IDIDE of the TCRX are all being set to 1, due interrupt request will be issued to the CPU. The edge of the input signal can be selected by setting the IEDGA through IEDGD of the TCRX. Also, the ICRC and ICRD can be used as the buffer register, respectively, of the ICRA and ICRB by setting the BUFEA and BUFEB of the TCRX to perform buffer operations. Figure 16.2 shows the connections necessary when using the ICRC as the buffer register of the ICRA. (BUFEA = 1) When the ICRC is used as the buffer of the ICRA, by setting IEDGA IEDGC, both of the rising and falling edges can be designated for use. In case of IEDGA = IEDGC, either one of the rising edge or the falling edge only is usable. Regarding selection of the input signal edge, see table 16.3. Note: Transference from the FRC to the ICR will be performed regardless of the value of the ICF. Rev. 0.1, 11/98, page 305 of 975 IEDGA BUFEA IEDGC Edge detection and capture signal generating circuit. FTIA ICRC ICRA FRC Figure 16.2 Buffer Operation (an example) Table 16.3 Input Signal Edge Selection when Making Buffer Operation IEDGA IEDGC Selection of the Input Signal Edge 0 0 Captures at the rising edge of the input capture input A (Initial value) 1 Captures at both rising and falling edges of the input capture input A 1 0 1 Captures at the rising edge of the input capture input A Reading can be made from the ICR through the CPU at 8-bit or 16-bit. For stable input capturing operation, maintain the pulse duration of the input capture input signals at 1.5 system clock () or more in case of single edge capturing and at 2.5 system clock () or more in case of both edge capturing. The ICR is initialized to H'0000 when reset or under the standby mode, watch mode, subsleep mode, module stop mode or subactive mode. 16.2.4 Timer Interrupt Enabling Register (TIER) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE ICSA 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The TIER is an 8-bit read/write register which works to control permission/prohibition of respective interrupt requests. The TIER is initialized to H'00 when reset or under the standby mode, watch mode, subsleep mode, module stop mode or subactive mode. Rev. 0.1, 11/98, page 306 of 975 Bit 7: Enabling the Input Capture Interrupt A (ICIAE) This bit works to permit/prohibit interrupt requests (ICIA) by the ICFA when the ICFA of the TCSRX is being set to 1. Bit 7 ICIAE Description 0 Prohibits interrupt requests (ICIA) by the ICFA 1 Permits interrupt requests (ICIA) by the ICFA (Initial value) Bit 6: Enabling the Input Capture Interrupt B (ICIBE) This bit works to permit/prohibit interrupt requests (ICIB) by the ICFB when the ICFB of the TCSRX is being set to 1. Bit 6 ICIBE Description 0 Prohibits interrupt requests (ICIB) by the ICFB 1 Permits interrupt requests (ICIB) by the ICFB (Initial value) Bit 5: Enabling the Input Capture Interrupt C (ICICE) This bit works to permit/prohibit interrupt requests (ICIC) by the ICFC when the ICFC of the TCSRX is being set to 1. Bit 5 ICICE Description 0 Prohibits interrupt requests (ICIC) by the ICFC 1 Permits interrupt requests (ICIC) by the ICFC (Initial value) Bit 4: Enabling the Input Capture Interrupt D (ICIDE) This bit works to permit/prohibit interrupt requests (ICID) by the ICFD when the ICFD of the TCSRX is being set to 1. Bit 4 ICIDE Description 0 Prohibits interrupt requests (ICID) by the ICFD 1 Permits interrupt requests (ICID) by the ICFD (Initial value) Rev. 0.1, 11/98, page 307 of 975 Bit 3: Enabling the Output Comparing Interrupt A (OCIAE) This bit works to permit/prohibit interrupt requests (OCIA) by the OCFA when the OCFA of the TCSRX is being set to 1. Bit 3 OCIAE Description 0 Prohibits interrupt requests (OCIA) by the OCFA 1 Permits interrupt requests (OCIA) by the OCFA (Initial value) Bit 2: Enabling the Output Comparing Interrupt B (OCIBE) This bit works to permit/prohibit interrupt requests (OCIB) by the OCFB when the OCFB of the TCSRX is being set to 1. Bit 2 OCIBE Description 0 Prohibits interrupt requests (OCIB) by the OCFB 1 Permits interrupt requests (OCIB) by the OCFB (Initial value) Bit 1: Enabling the Timer Overflow Interrupt (OVIE) This bit works to permit/prohibit interrupt requests (FOVI) by the OVF when the OVF of the TCSRX is being set to 1. Bit 1 OVIE Description 0 Prohibits interrupt requests (FOVI) by the OVF 1 Permits interrupt requests (FOVI) by the OVF (Initial value) Bit 0: Selecting the Input Capture A Signals (ICSA) This bit works to select the input capture A signals. Bit 0 ICSA Description 0 Selects the FTIA pin for inputting of the input capture A signals 1 Selects the HSW for inputting of the input capture A signals Rev. 0.1, 11/98, page 308 of 975 (Initial value) 16.2.5 Timer Control/Status Register X (TCSRX) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 ICFA ICFB ICFC ICFD OCFA OCFB OVF CCLRA 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/W Note: * Only 0 can be written to clear the flag for Bits 7 to 1. The TCSRX is an 8-bit register which works to select counter clearing timing and to control respective interrupt requesting signals. The TCSRX is initialized to H'00 when reset or under the standby mode, watch mode, subsleep mode, module stop mode or subactive mode. Meanwhile, as for the timing, see section 16.3, Operation. The FTIA through FTID pins are for fixed inputs inside the LSI under the low power consumption mode excluding the sleep mode. Consequently, when such shifts as "active mode low power consumption mode active mode" are made, wrong edges may be detected depending on the pin status or on the type of the detecting edge. To avoid such error, clear the interrupt requesting flag once immediately after shifting to the active mode from the low power consumption mode. Bit 7: Input Capture Flag A (ICFA) This is a status flag indicating the fact that the value of the FRC has been transferred to the ICRA by the input capture signals. When the BUFEA of the TCRX is being set to 1, the ICFA indicates the status that the FRC value has been transferred to the ICRA by the input capture signals and that the ICRA value before being updated has been transferred to the ICRC. This flag should be cleared by use of of the software. Such setting should only be made by use of the hardware. It is not possible to make this setting using a software. Bit 7 ICFA Description 0 [Clearing conditions] (Initial value) When 0 is written into the ICFA after reading the ICFA under the setting of ICFA = 1 1 [Setting conditions] When the value of the FRC has been transferred to the ICRA by the input capture signals Rev. 0.1, 11/98, page 309 of 975 Bit 6: Input Capture Flag B (ICFB) This is a status flag indicating the fact that the value of the FRC has been transferred to the ICRB by the input capture signals. When the BUFEB of the TCRX is being set to 1, the ICFB indicates the status that the FRC value has been transferred to the ICRB by the input capture signals and that the ICRB value before being updated has been transferred to the ICRC. This flag should be cleared by use of the software. Such setting should only be made by use of the hardware. It is not possible to make this setting using a software. Bit 6 ICFB Description 0 [Clearing conditions] (Initial value) When 0 is written into the ICFB after reading the ICFB under the setting of ICFB = 1 1 [Setting conditions] When the value of the FRC has been transferred to the ICRB by the input capture signals Bit 5: Input Capture Flag C (ICFC) This is a status flag indicating the fact that the value of the FRC has been transferred to the ICRC by the input capture signals. When an input capture signal occurs while the BUFEA of the TCRX is being set to 1, although the ICFC will be set out, data transference to the ICRC will not be performed. Therefore, in buffer operation, the ICFC can be used as an external interrupt by setting the ICICE bit to 1. This flag should be cleared by use of the software. Such setting should only be made by use of the hardware. It is not possible to make this setting using a software. Bit 5 ICFC Description 0 [Clearing conditions] (Initial value) When 0 is written into the ICFC after reading the ICFC under the setting of ICFC = 1 1 [Setting conditions] When the input capture signal has occurred Rev. 0.1, 11/98, page 310 of 975 Bit 4: Input Capture Flag D (ICFD) This is a status flag indicating the fact that the value of the FRC has been transferred to the ICRD by the input capture signals. When an input capture signal occurs while the BUFEB of the TCRX is being set to 1, although the ICFD will be set out, data transference to the ICRD will not be performed. Therefore, in buffer operation, the ICFD can be used as an external interrupt by setting the ICIDE bit to 1. This flag should be cleared by use of the software. Such setting should only be made by use of the hardware. It is not possible to make this setting using a software. Bit 4 ICFD Description 0 [Clearing conditions] (Initial value) When 0 is written into the ICFD after reading the ICFD under the setting of ICFD = 1 1 [Setting conditions] When the input capture signal has occurred Bit 3: Output Comparing Flag A (OCFA) This is a status flag indicating the fact that the FRC and the OCRA have come to a comparing match. This flag should be cleared by use of the software. Such setting should only be made by use of the hardware. It is not possible to make this setting using a software. Bit 3 OCFA Description 0 [Clearing conditions] (Initial value) When 0 is written into the OCFA after reading the OCFA under the setting of OCFA = 1 1 [Setting conditions] When the FRC and the OCRA have come to the comparing match Rev. 0.1, 11/98, page 311 of 975 Bit 2: Output Comparing Flag B (OCFB) This is a status flag indicating the fact that the FRC and the OCRB have come to a comparing match. This flag should be cleared by use of the software. Such setting should only be made by use of the hardware. It is not possible to make this setting using a software. Bit 2 OCFB Description 0 [Clearing conditions] (Initial value) When 0 is written into the OCFB after reading the OCFB under the setting of OCFB = 1 1 [Setting conditions] When the FRC and the OCRB have come to the comparing match Bit 1: Time Over Flow (OVF) This is a status flag indicating the fact that the FRC overflowed. (H'FFFF H'0000). This flag should be cleared by use of the software. Such setting should only be made by use of the hardware. It is not possible to make this setting using a software. Bit 1 OVF Description 0 [Clearing conditions] (Initial value) When 0 is written into the OVF after reading the OVF under the setting of OVF = 1 1 [Setting conditions] When the FRC value has become H'FFFF H'0000 Bit 0: Counter Clearing (CCLRA) This bit works to select if or not to clear the FRC by occurrence of comparing match A (matching signal of the FRC and OCRA). Bit 0 CCLRA Description 0 Prohibits clearing of the FRC by occurrence of comparing match A 1 Permits clearing of the FRC by occurrence of comparing match A Rev. 0.1, 11/98, page 312 of 975 (Initial value) 16.2.6 Timer Control Register X (TCRX) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The TCRX is an 8-bit read/write register which works to select the input capture signal edge, to designate the buffer operation and to select the inputting clock for the FRC. The TCRX is initialized to H'00 when reset or under the standby mode, watch mode, subsleep mode, module stop mode or subactive mode. Bit 7: Input Capture Signal Edge Selection A (IEDGA) This bit works to select the rising edge or falling edge of the input capture signal A (FTIA). Bit 7 IEDGA Description 0 Captures the falling edge of the input capture signal A 1 Captures the rising edge of the input capture signal A (Initial value) Bit 6: Input Capture Signal Edge Selection B (IEDGB) This bit works to select the rising edge or falling edge of the input capture signal B (FTIB). Bit 6 IEDGB Description 0 Captures the falling edge of the input capture signal B 1 Captures the rising edge of the input capture signal B (Initial value) Bit 5: Input Capture Signal Edge Selection C (IEDGC) This bit works to select the rising edge or falling edge of the input capture signal C (FTIC). However, when the DVCTL has been selected as the signal for the input capture signal edge selection C, this bit will not influence the operation. Bit 5 IEDGC Description 0 Captures the falling edge of the input capture signal C 1 Captures the rising edge of the input capture signal C (Initial value) Rev. 0.1, 11/98, page 313 of 975 Bit 4: Input Capture Signal Edge Selection D (IEDGD) This bit works to select the rising edge or falling edge of the input capture signal D (FTID). Bit 4 IEDGD Description 0 Captures the falling edge of the input capture signal D 1 Captures the rising edge of the input capture signal D (Initial value) Bit 3: Buffer Enabling A (BUFEA) This bit works to select if or not to use the ICRC as the buffer register for the ICRA. Bit 3 BUFEA Description 0 Using the ICRC as the buffer register for the ICRA 1 Not using the ICRC as the buffer register for the ICRA (Initial value) Bit 2: Buffer Enabling B (BUFEB) This bit works to select if or not to use the ICRD as the buffer register for the ICRB. Bit 2 BUFEB Description 0 Using the ICRD as the buffer register for the ICRB 1 Not using the ICRD as the buffer register for the ICRB (Initial value) Bits 1 and 0: Clock Select (CKS1, 0) These bits work to select the inputting clock to the FRC from among three types of internal clocks and the DVCFG. The DVCFG is the edge detecting pulse selected by the CFG dividing timer. Bit 1 Bit 0 CKS1 CKS0 Description 0 0 Internal clock: Counts at /4 0 1 Internal clock: Counts at /16 1 0 Internal clock: Counts at /64 1 1 DVCFG: The edge detecting pulse selected by the CFG dividing timer Rev. 0.1, 11/98, page 314 of 975 (Initial value) 16.2.7 Timer Output Comparing Control Register (TOCR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 ICSB ICSC ICSD OSRS OEA OEB OLVLA OLVLB 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The TOCR is an 8-bit read/write register which works to select input capture signals and output comparing output level, to permit output comparing outputs and to control switching over of the access of the OCRA and OCRB. See the section describing the timer interrupt enabling register (TIER) regarding the input capture inputs A. The TOCR is initialized to H'00 when reset or under the standby mode, watch mode, subsleep mode, module stop mode or subactive mode. Bit 7: Selecting the Input Capture B Signals (ICSB) This bit works to select the input capture B signals. Bit 7 ICSB Description 0 Selects the FTIB pin for inputting of the input capture B signals 1 Selects the VD as the input capture B signals (Initial value) Bit 6: Selecting the Input Capture C Signals (ICSC) This bit works to select the input capture C signals. The DVCTL is the edge detecting pulse selected by the CTL dividing timer. Bit 6 ICSC Description 0 Selects the FTIC pin for inputting of the input capture C signals 1 Selects the DVCTL as the input capture C signals (Initial value) Bit 5: Selecting the Input Capture D Signals (ICSD) This bit works to select the input capture D signals. Bit 5 ICSD Description 0 Selects the FTID pin for inputting of the input capture D signals 1 Selects the NHSW as the input capture D signals (Initial value) Rev. 0.1, 11/98, page 315 of 975 Bit 4: Selecting the Output Comparing Register (OCRS) The addresses of the OCRA and OCRB are the same. The OCRS works to control which register to choose when reading/writing this address. The choice will not influence the operation of the OCRA and OCRB. Bit 4 OCRS Description 0 Selects the OCRA register 1 Selects the OCRB register (Initial value) Bit 3: Enabling the Output A (OEA) This bit works to control the output comparing A signals. Bit 3 OEA Description 0 Prohibits the output comparing A signal outputs 1 Permits the output comparing A signal outputs (Initial value) Bit 2: Enabling the Output B (OEB) This bit works to control the output comparing B signals. Bit 2 OEB Description 0 Prohibits the output comparing B signal outputs 1 Permits the output comparing B signal outputs (Initial value) Bit 1: Output Level A (OLVLA) This bit works to select the output level to output through the FTOA pin by use of the comparing match A (matching signal between the FRC and OCRA). Bit 1 OLVLA Description 0 Low level 1 High level Rev. 0.1, 11/98, page 316 of 975 (Initial value) Bit 0: Output Level B (OLVLB) This bit works to select the output level to output through the FTOB pin by use of the comparing match B (matching signal between the FRC and OCRB). Bit 0 OLVLB Description 0 Low level 1 High level 16.2.8 (Initial value) Module Stop Control Register (MSTPCR) MSTPCRH Bit : 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The MSTPCR consists of twin 8-bit read/write registers and it works to control the module stop mode. When the MSTP10 bit is set to 1, the Timer X1 stops its operation at the ending point of the bus cycle to shift to the module stop mode. For more information, see section 4.5, Module Stop Mode. When reset, the MSTPCR is initialized to H'FFFF. Bit 2: Module Stop (MSTP10) This bit works to designate the module stop mode for the Timer X1. MSTPCRH Bit 2 MSTP10 Description 0 Cancels the module stop mode of the Timer X1 1 Sets the module stop mode of the Timer X1 (Initial value) Rev. 0.1, 11/98, page 317 of 975 16.3 Operation 16.3.1 Operation of the Timer X1 (1) Output Comparing Operation Right after resetting, the FRC is initialized to H'0000 to start counting up. The inputting clock can be selected from among three different types of internal clocks or the external clock by setting the CKS1 and CKS0 of the TCRX. The contents of the FRC are always being compared with the OCRA and OCRB and, when the value of these two match, the level set by the the OLVLA and OLVLB of the TOCR is output through the FTOA pin and FTOB pin. After resetting, 0 will be output through the FTOA and FTOB pins until the first compare matching occurs. Also, when the CCLRA of the TCSRX is being set to 1, the FRC will be cleared to H'0000 when the comparing match A occurs. (2) Input Capturing Operation Right after resetting, the FRC is initialized to H'0000 to start counting up. The inputting clock can be selected from among three different types of internal clocks or the external clock by setting the CKS1 and CKS0 of the TCRX. The inputs are transferred to the IEDGA through IEDGD of the TCRX through the FTIA through FTID pins and, at the same time, the ICFA through ICFD of the TCSRX are set to 1. At this time, if the ICIAE through ICIED of the TIER are being set to 1, due interrupt request will be issued to the CPU. When the BUFEA and BUFEB of the TCRX are set to 1, the ICRC and ICRD work as the buffer register, respectively, of the ICRA and ICRB. When the edge selected by setting the IEDGA through IEDGD of the TCRX is input through the FTIA and FTIB pins, the value at the time of the FRC is transferred to the ICRA and ICRB and, at the same time, the values of the ICRA and ICRB before updating are transferred to the ICRC and ICRD. At this time, when the ICFA and ICFB are being set to 1 and if the ICIAE and ICIBE of the TIER are being set to 1, due interrupt request will be issued to the CPU. Rev. 0.1, 11/98, page 318 of 975 16.3.2 Counting Timing of the FRC The FRC is counted up by the inputting clock. By setting the CKS1 and CKS0 of the TCRX, the inputting clock can be selected from among three different types of clocks (/4, /16 and /64) and the DVCFG. (1) In Case of Internal Clock Operation By setting the CKS1 and CKS0 bits of the TCRX, three types of internal clocks (/4, /16 and /64), generated by dividing the system clock () can be selected. Figure 16.3 shows the timing chart at this time. Internal clock FRC input clock FRC N-1 N N+1 Figure 16.3 Count Timing in Case of Internal Clock Operation (2) In Case of DVCFG Clock Operation By setting the CKS1 and CKS0 bits of the TCRX to 1, DVCFG clock input can be selected. The DVCFG clock makes counting by use of the edge detecting pulse being selected by the CFG dividing timer. Figure 16.4 shows the timing chart at this time. CFG DVCFG FRC input clock FRC N N+1 Figure 16.4 Count Timing in Case of CFG Clock Operation Rev. 0.1, 11/98, page 319 of 975 16.3.3 Output Comparing Signal Outputting Timing When a comparing match occurs, the output level having been set by the OLVL of the TOCR is output through the output comparing signal outputting pins (FTOA and FTOB). Figure 16.5 shows the timing chart in case of the output comparing signal outputting A. FRC N OCRA N N+1 N+1 N N Comparing match signal *1 Clearing OLVLA FTOA Output comparing signal outputting A pin Note: 1. Execution of the command is to be designated by the software. Figure 16.5 Output Comparing Signal Outputting A Timing 16.3.4 FRC Clearing Timing The FRC can be cleared when the comparing match A occurs. Figure 16.6 shows the timing chart when doing so. Comparing match A signal FRC N H' 0000 Figure16.6 FRC Clearing Timing by Occurrence of the Comparing Match A Rev. 0.1, 11/98, page 320 of 975 16.3.5 Input Capture Signal Inputting Timing (1) Input Capture Signal Inputting Timing As for the input capture signal inputting, rising or falling edge is selected by settings of the IEDGA through IEDGD bits of the TCRX. Figure 16.7 shows the timing chart when the rising edge is selected (IEDGA through IEDGD = 1). Input capture signal inputting pin Input capture signal Figure 16.7 Input Capture Signal Inputting Timing (under normal state) (2) Input Capture Signal Inputting Timing when Making Buffer Operation Buffer operation can be made using the ICRA or ICRD as the buffer of the ICRA or ICRB. Figure 16.8 shows the input capture signal inputting timing chart in case both of the rising and falling edges are designated (IEDGA = 1 and IEDGC = 0, or IEDGA = 0 and IEDGC = 1), using the ICRC as the buffer register for the ICRA (BUFEA = 1). FTIA Input capture signal FRC n n+1 N ICRA M n n N ICRC m M M n Figure 16.8 Input Capture Signal Inputting Timing Chart Under the Buffer Mode (under normal state) Rev. 0.1, 11/98, page 321 of 975 Even when the ICRC or ICRD is used as the buffer register, the input capture flag will be set up corresponding to the designated edge change of respective input capture signals. For example, when using the ICRC as the buffer register for the ICRA, when an edge change having been designated by the IEDGC bit is detected with the input capture signals C and if the ICIEC bit is duly set, an interrupt request will be issued. However, in this case, the FRC value will not be transferred to the ICRC. 16.3.6 Input Capture Flag (ICFA through ICFD) Setting Up Timing The input capture signal works to set the ICFA through ICFD to "1" and, simultaneously, the FRC value is transferred to the corresponding ICRA through ICRD. Figure 16.9 shows the timing chart for the above. Input capture signal ICFA to ICFD FRC N ICRA to ICRD N Figure 16.9 ICFA through ICFD Setting Up Timing Rev. 0.1, 11/98, page 322 of 975 16.3.7 Output Comparing Flag (OCFA and OCFB) Setting Up Timing The OCFA and OCFB are being set to 1 by the comparing match signal being output when the values of the OCRA, OCRB and FRC match. The comparing match signal is generated at the last state of the value match (the timing of the FRC's updating the matching count reading). After the values of the OCRA, OCRB and FRC match, up until the count up clock signal is generated, the comparing match signal will not be issued. Figure 16.10 shows the OCFA and OCFB setting timing chart. FRC N OCRA, OCRB N N+1 Comparing match signal OCFA, OCFB Figure 16.10 OCF Setting Up Timing 16.3.8 Overflow Flag (CVF) Setting Up Timing The OVF is set to when the FRC overflows (H'FFFF H'0000). Figure 16.11 shows the timing chart for this case. FRC H'FFFF H'0000 Overflowing signal OVF Figure 16.11 OVF Setting Up Timing Rev. 0.1, 11/98, page 323 of 975 16.4 Operation Mode of the Timer X1 Table 16.4 indicated below shows the operation mode of the Timer X1. Table 16.4 Operation Mode of the Timer X1 Operation mode Reset Active Sleep Module Watch Subactive Standby Subsleep stop FRC Reset Functions Functions Reset Reset Reset Reset Reset OCRA, OCRB Reset Functions Functions Reset Reset Reset Reset Reset ICRA to ICRD Reset Functions Functions Reset Reset Reset Reset Reset TIER Reset Functions Functions Reset Reset Reset Reset Reset TCRX Reset Functions Functions Reset Reset Reset Reset Reset TOCR Reset Functions Functions Reset Reset Reset Reset Reset TCSRX Reset Functions Functions Reset Reset Reset Reset Reset Rev. 0.1, 11/98, page 324 of 975 16.5 Interrupt Causes Total seven interrupt causes exist with the Timer X1, namely, ICIA through ICID, OCIA, OCIB and FOVI. Table 16.5 given below lists the contents of respective interrupt causes. Respective interrupt requests can be permitted or prohibited by setting of respective interrupt enabling bits of the TIER. Also, independent vector addresses are being allocated to respective interrupt causes. Table 16.5 Interrupt Causes of the Timer X1 Abbreviations of the Interrupt Causes Priority Degree Contents ICIA Interrupt request by the ICFA High ICIB Interrupt request by the ICFB ICIC Interrupt request by the ICFC ICID Interrupt request by the ICFD OCIA Interrupt request by the OCFA OCIB Interrupt request by the OCFB FOVI Interrupt request by the OVF Low Rev. 0.1, 11/98, page 325 of 975 16.6 Exemplary Uses of the Timer X1 Figure 16.12 indicated below shows an example of outputting at optional phase difference of the pulses of the 50% duty. For this setting, follow the procedures listed below. (1) set the CCLRA bit of the TCSRX to "1". (2) Each time a comparing match occurs, the OLVIA bit and the OLVLB bit are reversed by use of the software. FRC H'FFFF Clearing the counter OCRA OCRB H'0000 FTOA FTOB Figure 16.12 An Exemplary Pulse Outputting Rev. 0.1, 11/98, page 326 of 975 16.7 Precautions when Using the Timer X1 Pay great attention to the fact that the following competitions and operations occur during operation of the Timer X1. 16.7.1 Competition between Writing and Clearing with the FRC When a counter clearing signal is issued under the T2 state where the FRC is under the writing cycle, writing into the FRC will not be effected and the priority will be given to clearing of the FRC. Figure 16.13 shows the timing chart in this case. Writing cycle with the FRC T1 T2 Address FRC address Internal writing signal Counter clearing signal FRC N H'0000 Figure 16.13 Competition between Writing and Clearing with the FRC Rev. 0.1, 11/98, page 327 of 975 16.7.2 Competition between Writing and Counting Up with the FRC When a counting up cause occurs under the T2 state where the FRC is under the writing cycle, the counting up will not be effected and the priority will be given to count writing. Figure 16.14 shows the timing chart in this case. Writing cycle with the FRC T1 T2 Address FRC address Internal writing signal Inputting clock to the FRC FRC N M Writing data Figure 16.14 Competition between Writing and Counting Up with the FRC Rev. 0.1, 11/98, page 328 of 975 16.7.3 Competition between Writing and Comparing Match with the OCR When a comparing match occurs under the T2 state where the OCRA and OCRB are under the writing cycle, the priority will be given to writing of the OCR and the comparing match signal will be prohibited. Figure 16.15 shows the timing chart in this case. Writing cycle with the OCR T1 T2 Address OCR address Internal writing signal FRC N OCR N N+1 M Writing data Comparing match signal Will be prohibited Figure 16.15 Competition between Writing and Comparing Match with the OCR Rev. 0.1, 11/98, page 329 of 975 16.7.4 Changing Over the Internal Clocks and Counter Operations Depending on the timing of changing over the internal clocks, the FRC may count up. Table 16.6 indicated below shows the relations between the timing of changing over the internal clocks (Re-writing of the CKS1 and CKS0) and the FRC operations. When using an internal clock, the counting clock is being generated detecting the falling edge of the internal clock dividing the system clock (). For this reason, like Item No. 3 of table 16.6, count clock signals are issued deeming the timing before the changeover as the falling edge to have the FRC to count up. Also, when changing over between an internal clock and the external clock, the FRC may count up. Table 16.6 Changing Over the Internal Clocks and the FRC Operation (1) No. 1 Re-writing timing for the CKS1 and CKS0 FRC operation Low Low level changeover Clock before the changeover Clock after the changeover Count clock FRC N N+1 Re-writing of the CKS1 and CKS0 2 Low High level changeover Clock before the changeover Clock after the changeover Count clock FRC N N+1 N+2 Re-writing of the CKS1 and CKS0 Rev. 0.1, 11/98, page 330 of 975 Table 16.6 Changing Over the Internal Clocks and the FRC Operation (2) No. 3 Re-writing timing for the CKS1 and CKS0 High Low level changeover FRC operation Clock before the changeover Clock after the changeover * Count clock FRC N N+1 N+2 Re-writing of the CKS1 and CKS0 4 High High level changeover Clock before the changeover Clock after the changeover Count clock FRC N N+1 N+2 Re-writing of the CKS1 and CKS0 Note: * The count clock signals are issued deeming the changeover timing as the falling edge to have the FRC to count up. Rev. 0.1, 11/98, page 331 of 975 Rev. 0.1, 11/98, page 332 of 975 Section 17 Watchdog Timer (WDT) 17.1 Overview This LSI has an on-chip watchdog timer with one channel (WDT) for monitoring system operation. The WDT outputs an overflow signal if a system crash prevents the CPU from writing to the timer counter, allowing it to overflow. At the same time, the WDT can also generate an internal reset signal or internal NMI interrupt signal. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer mode, an interval timer interrupt is generated each time the counter overflows. 17.1.1 Features WDT features are listed below. * Switchable between watchdog timer mode and interval timer mode WOVI interrupt generation in interval timer mode * Internal reset or internal interrupt generated when the timer counter overflows Choice of internal reset or NMI interrupt generation in watchdog timer mode * Choice of 8 counter input clocks Maximum WDT interval: system clock period x 131072 x 256 Rev. 0.1, 11/98, page 333 of 975 17.1.2 Block Diagram Figure 17.1 shows block diagram of WDT. WOVI (Interrupt request signal) Internal NMI interrupt request signal Interrupt control * Reset control Overflow Clock /2 / 64 / 128 / 512 / 2048 / 8192 / 32768 / 131072 Clock select Internal reset signal* WTCNT WTCSR Module bus WDT [Legend] WTCSR : Timer control/status register WTCNT : Timer counter Note: * The internal reset signal can be generated by means of a register setting. Figure 17.1 Block Diagram of WDT Rev. 0.1, 11/98, page 334 of 975 Bus interface Internal bus Internal clock source 17.1.3 Register Configuration The WDT has two registers, as summarized in table 17.2. These registers control clock selection, WDT mode switching, the reset signal, etc. Table 17.2 WDT Registers Address*1 Name Abbrev. R/W *3 Initial Value Write*2 Read H'00 H'FFBC H'FFBC Watchdog timer control/status register WTCSR R/ (W) Watchdog timer counter WTCNT R/W H'00 H'FFBC H'FFBD System control register SYSCR R/W H'09 H'FFE8 H'FFE8 Notes: 1. Lower 16 bits of the address. 2. For details of write operations, see section 17.2.4, Notes on Register Access. 3. Only 0 can be written in bit 7, to clear the flag. Rev. 0.1, 11/98, page 335 of 975 17.2 Register Descriptions 17.2.1 Watchdog Timer Counter (WTCNT) Bit : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W : TCNT is an 8-bit readable/writable* up-counter. When the TME bit is set to 1 in WTCSR, WTCNT starts counting pulses generated from the internal clock source selected by bits CKS2 to CKS0 in WTCSR. When the count overflows (changes from H'FF to H'00), the OVF flag in WTCSR is set to 1. WTCNT is initialized to H'00 by a reset, or when the TME bit is cleared to 0. Note: * WTCNT is write-protected by a password to prevent accidental overwriting. For details see section 17.2.4, Notes on Register Access. Rev. 0.1, 11/98, page 336 of 975 17.2.2 Watchdog Timer Control/Status Register (WTCSR) Bit : Initial value : R/W : 7 6 5 OVF WT/IT TME 0 0 0 0 R/(W)* R/W R/W R/W 4 3 2 1 0 CKS2 CKS1 CKS0 0 0 0 0 R/W R/W R/W R/W RSTS RST/NMI Note: * Only 0 can be written to clear the flag. WTCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be input to WTCNT, and the timer mode. WTCSR is initialized to H'00 by a reset. Note: * WTCSR is write-protected by a password to prevent accidental overwriting. For details see section 17.2.4, Notes on Register Access. Bit 7: Overflow Flag (OVF) A status flag that indicates that WTCNT has overflowed from H'FF to H'00. Bit 7 OVF Description 0 [Clearing conditions] (1) Write 0 in the TME bit (2) Read WTCSR when OVF = 1, then write 0 in OVF 1 [Setting condition] When WTCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset (Initial value) Bit 6: Timer Mode Select (WT/,7) Selects whether the WDT is used as a watchdog timer or interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request (WOVI) when TCNT overflows. If used as a watchdog timer, the WDT generates a reset or NMI interrupt when TCNT overflows. Bit 6 WT/,7 Description 0 Interval timer mode: Sends the CPU an interval timer interrupt request (WOVI) when WTCNT overflows (Initial value) 1 Watchdog timer mode: Sends the CPU a reset or NMI interrupt request when WTCNT overflows Rev. 0.1, 11/98, page 337 of 975 Bit 5: Timer Enable (TME) Selects whether WTCNT runs or is halted. Bit 5 TME Description 0 WTCNT is initialized to H'00 and halted 1 WTCNT counts (Initial value) Bit 4: Reset Select (RSTS) Reserved. This bit should not be set to 1. Bit 3: Reset or NMI (RST/10,) Specifies whether an internal reset or NMI interrupt is requested on WTCNT overflow in watchdog timer mode. Bit 3 RST/1,0, Description 0 An NMI interrupt request is generated 1 An internal reset request is generated (Initial value) Bits 2 to 0: Clock Select 2 to 0 (CKS2 to CKS0) These bits select an internal clock source, obtained by dividing the system clock () for input to WTCNT. WDT input clock selection Bit 2 Bit 1 Bit 0 Description CSK2 CSK1 CSK0 Clock Overflow Period* (when = 10 MHz) 0 0 0 /2 (Initial value) 51.2 s 1 /64 1.6 ms 0 /128 3.3 ms 1 /512 13.1 ms 0 /2048 52.4 ms 1 /8192 209.7 ms 0 /32768 838.9 ms 1 /131072 3.36 s 1 1 0 1 Note: * The overflow period is the time from when WTCNT starts counting up from H'00 until overflow occurs. Rev. 0.1, 11/98, page 338 of 975 17.2.3 System Control Register (SYSCR) Bit : 7 6 5 4 3 2 0 1 -- -- INTM1 INTM0 XRST Initial value : 0 0 0 0 1 0 0 1 R/W : -- -- R R/W R R/W R/W -- NMIEG1 NMIEG0 -- Only bit 3 is described here. For details on functions not related to the watchdog timer, see sections 3.2.2 and 6.2.1, System Control Register (SYSCR), and the descriptions of the relevant modules. Bit 3: External Reset (XRST) Indicates the reset source. When the watchdog timer is used, a reset can be generated by watchdog timer overflow in addition to external reset input. XRST is a read-only bit. It is set to 1 by an external reset, and cleared to 0 by watchdog timer overflow. Bit 3 XRST Description 0 Reset is generated by watchdog timer overflow 1 Reset is generated by external reset input (Initial value) Rev. 0.1, 11/98, page 339 of 975 17.2.4 Notes on Register Access The watchdog timer's WTCNT and WTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. (1) Writing to WTCNT and WTCSR These registers must be written to by a word transfer instruction. They cannot be written to with byte transfer instructions. Figure 17.2 shows the format of data written to WTCNT and WTCSR. WTCNT and WTCSR both have the same write address. For a write to WTCNT, the upper byte of the written word must contain H'5A and the lower byte must contain the write data. For a write to WTCSR, the upper byte of the written word must contain H'A5 and the lower byte must contain the write data. This transfers the write data from the lower byte to WTCNT or WTCSR. <WTCNT write> 15 Address : H'FFBC 8 7 H'5A 0 0 Write data <WTCSR write> 15 Address : H'FFBC 0 8 7 H'A5 0 Write data Figure 17.2 Format of Data Written to WTCNT and WTCSR (2) Reading WTCNT and WTCSR These registers are read in the same way as other registers. The read addresses are H'FFBC for WTCSR, and H'FFBD for WTCNT. Rev. 0.1, 11/98, page 340 of 975 17.3 Operation 17.3.1 Watchdog Timer Operation To use the WDT as a watchdog timer, set the WT/,7 and TME bits in WTCSR to 1. Software must prevent WTCNT overflows by rewriting the WTCNT value (normally by writing H'00) before overflow occurs. This ensures that WTCNT does not overflow while the system is operating normally. If WTCNT overflows without being rewritten because of a system crash or other error, the chip is reset, or an NMI interrupt is generated, for 518 system clock periods (518 ). This is illustrated in figure 17.3. An internal reset request from the watchdog timer and reset input from the 5(6 pin are handled via the same vector. The reset source can be identified from the value of the XRST bit in SYSCR. If a reset caused by an input signal from the 5(6 pin and a reset caused by WDT overflow occur simultaneously, the 5(6 pin reset has priority, and the XRST bit in SYSCR is set to 1. An NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin are handled via the same vector. Simultaneous handling of a watchdog timer NMI interrupt request and an NMI pin interrupt request must therefore be avoided. TCNT value Overflow H'FF Time H'00 WT/IT=1 TME=1 H'00 written to TCNT WOVF=1* WT/IT=1 TME=1 H'00 written to TCNT Internal reset generated Internal reset signal 518 system clock period WT/IT : Timer mode select bit TME : Timer enable bit Note: * Cleared to 0 by an internal reset when WOVF is set to 1. XRST is cleared to 0. Figure 17.3 Operation in Watchdog Timer Mode Rev. 0.1, 11/98, page 341 of 975 17.3.2 Interval Timer Operation To use the WDT as an interval timer, clear the WT/,7 bit in WTCSR to 0 and set the TME bit to 1. An interval timer interrupt (WOVI) is generated each time WTCNT overflows, provided that the WDT is operating as an interval timer, as shown in figure 17.4. This function can be used to generate interrupt requests at regular intervals. WTCNT value Overflow H'FF Overflow Overflow Overflow Time H'00 WT/IT=0 TME=1 WOVI WOVI WOVI WOVI : Interval timer interrupt request generation Figure 17.4 Operation in Interval Timer Mode Rev. 0.1, 11/98, page 342 of 975 WOVI 17.3.3 Timing of Setting of Overflow Flag (OVF) The OVF bit in WTCSR is set to 1 if WTCNT overflows during interval timer operation. At the same time, an interval timer interrupt (WOVI) is requested. This timing is shown in figure 17.5. If NMI request generation is selected in watchdog timer mode, when WTCNT overflows the OVF bit in WTCSR is set to 1 and at the same time an NMI interrupt is requested. CK WTCNT H'FF H'00 Overflow signal (internal signal) OVF Figure 17.5 Timing of OVF Setting Rev. 0.1, 11/98, page 343 of 975 17.4 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in WTCSR. OVF must be cleared to 0 in the interrupt handling routine. When NMI interrupt request generation is selected in watchdog timer mode, an overflow generates an NMI interrupt request. 17.5 Usage Notes 17.5.1 Contention between Watchdog Timer Counter (WTCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a WTCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 17.6 shows this operation. WTCNT write cycle T1 T2 Internal Internal address Internal write signal WTCNT input clock WTCNT N M Counter write data Figure 17.6 Contention between WTCNT Write and Increment Rev. 0.1, 11/98, page 344 of 975 17.5.2 Changing Value of CKS2 to CKS0 If bits CKS2 to CKS0 in WTCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS2 to CKS0. 17.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before switching the mode. Rev. 0.1, 11/98, page 345 of 975 Rev. 0.1, 11/98, page 346 of 975 Section 18 8-Bit PWM 18.1 Overview The 8-bit PWM incorporates 4 channels of the duty control method. Its outputs can be used to control a reel motor or loading motor. 18.1.1 Features * Conversion period: 256-state * Duty control method 18.1.2 Block Diagram Figure 18.1 shows a block diagram of the 8-bit PWM (1 channel). Internal data bus PW8CR PWMn Polarity specification PWRn R Match signal Comparator Q S OVF 27 20 Free-running counter (FRC) (n=3 to 0) [Legend] PWRn : 8-bit PWM data register n PW8CR: 8-bit PWM control register PWMn : 8-bit PWM square-wave output pin n OVF : Overflow signal from FRC lower 8-bit Figure 18.1 Block Diagram of 8-Bit PWM Rev. 0.1, 11/98, page 347 of 975 18.1.3 Pin Configuration Table 18.1 shows the 8-bit PWM pin configuration. Table 18.1 Pin Configuration Name Abbrev. I/O Function 8-bit PWM square-wave output pin 0 PWM0 Output 8-bit PWM square-wave output 0 8-bit PWM square-wave output pin 1 PWM1 Output 8-bit PWM square-wave output 1 8-bit PWM square-wave output pin 2 PWM2 Output 8-bit PWM square-wave output 2 8-bit PWM square-wave output pin 3 PWM3 Output 8-bit PWM square-wave output 3 18.1.4 Register Configuration Table 18.2 shows the 8-bit PWM register configuration. Table 18.2 8-Bit PWM Registers Name Abbrev. R/W Size Initial Value Address* 8-bit PWM data register 0 PWR0 W Byte H'00 H'D126 8-bit PWM data register 1 PWR1 W Byte H'00 H'D127 8-bit PWM data register 2 PWR2 W Byte H'00 H'D128 8-bit PWM data register 3 PWR3 W Byte H'00 H'D129 8-bit PWM control register PW8CR R/W Byte H'F0 H'D12A Port mode register 3 PMR3 R/W Byte H'00 H'FFD0 Note: * Lower 16 bits of the address. Rev. 0.1, 11/98, page 348 of 975 18.2 Register Descriptions 18.2.1 Bit PWM Data Registers 0, 1, 2 and 3 (PWR0, PWR1, PWR2, PWR3) (1) PWR0 Bit : Initial value : R/W : 7 PW07 6 PW06 5 PW05 4 PW04 3 PW03 2 PW02 1 PW01 0 PW00 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 7 PW17 6 PW16 5 PW15 4 PW14 3 PW13 2 PW12 1 PW11 0 PW10 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 7 PW27 6 PW26 5 PW25 4 PW24 3 PW23 2 PW22 1 PW21 0 PW20 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 7 PW37 6 PW36 5 PW35 4 PW34 3 PW33 2 PW32 1 PW31 0 PW30 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W (2) PWR1 Bit : Initial value : R/W : (3) PWR2 Bit : Initial value : R/W : (4) PWR3 Bit : Initial value : R/W : 8-bit PWM data registers 0, 1, 2 and 3 (PWR0, PWR1, PWR2, PWR3) control the duty cycle at 8-bit PWM pins. The data written in PWR0, PWR1, PWR2 and PWR3 correspond to the highlevel width of one PWM output waveform cycle (256 states). When data is set in PWR0, PWR1, PWR2 and PWR3, the contents of the data are latched in the PWM waveform generators, updating the PWM waveform generation data. PWR0, PWR1, PWR2 and PWR3 are write-only registers. When read, all bits are always read as 1. PWR0, PWR1, PWR2 and PWR3 are initialized to H'00 by a reset. Rev. 0.1, 11/98, page 349 of 975 18.2.2 8-bit PWM Control Register (PW8CR) Bit : 7 -- 6 -- 5 -- 4 -- 3 PWC3 2 PWC2 1 PWC1 0 PWC0 Initial value : R/W : 1 -- 1 -- 1 -- 1 -- 0 R/W 0 R/W 0 R/W 0 R/W The 8-bit PWM control register (PW8CR) is an 8-bit readable/writable register that controls PWM functions. PW8CR is initialized to H'00 by a reset. Bits 7 to 4: Reserved These bits are reserved. They are always read as 1. Writes are disabled. Bits 3 to 0: Output Polarity Select (PWC3 to PWC0) These bits select the output polarity of PWMn pin between positive or negative (reverse). Bit n PWCn Description 0 PWMn pin output has positive polarity 1 PWMn pin output has negative polarity (Initial value) (n = 3 to 0) Rev. 0.1, 11/98, page 350 of 975 18.2.3 Port Mode Register 3 (PMR3) Bit : Initial value : R/W : 7 PMR37 6 PMR36 5 PMR35 4 PMR34 3 PMR33 2 PMR32 1 PMR31 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 PMR30 0 R/W The port mode register 3 (PMR3) controls function switching of each pin in the port 3. Switching is specified for each bit. The PMR3 is a 8-bit readable/writable register and is initialized to H'00 by a reset. For bits other than 5 to 2, see section 10.5, Port 3. Bits 5 to 2: P35/PWM3 to P32/PWM0 Pin Switching (PMR35 to PMR32) These bits set whether the P3n/PWMn pin is used as I/O pin or it is used as 8-bit PWM output PWMm pin. Bit n PMR3n Description 0 P3n/PMWm pin functions as P3n I/O pin 1 P3n/PMWm pin functions as PWMm output pin (Initial value) (n = 5 to 2, m = 3 to 0) Rev. 0.1, 11/98, page 351 of 975 18.2.4 Module Stop Control Register (MSTPCR) MSTPCRH Bit : 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The MSTPCR consists of two 8-bit readable/writable registers that control module stop mode. When MSTP4 bit is set to 1, the 8-bit PWM stops its operation upon completion of the bus cycle and transits to the module stop mode. For details, see section 4.5, Module Stop Mode. The MSTPCR is initialized to H'FFFF by a reset. Bit 4: Module Stop (MSTP4) This bit sets the module stop mode of the 8-bit PWM. MSTPCRL Bit 4 MSTP4 Description 0 8-bit PWM module stop mode is released 1 8-bit PWM module stop mode is set Rev. 0.1, 11/98, page 352 of 975 (Initial value) 18.3 8-Bit PWM Operation The 8-bit PWM outputs PWM pulses having a cycle length of 256 states and a pulse width determined by the data registers (PWR). The output PWM pulse can be converted to a DC voltage through integration in a low-pass filter. Figure 18.2 shows the output waveform example of 8-bit PWM. The pulse width (Twidth) can be obtained by the following expression: Twidth = (1/) x (PWR setting value) FRC lower 8-bit value H'FF PWRn setting value H'00 PWRn pin output (Positive polarity) (n=3 to 0) Pulse width T width Pulse width T width T width T width (Negative polarity) Pulse cycle (256 states) Pulse cycle (256 states) Figure 18.2 8-bit PWM Output Waveform (Example) Rev. 0.1, 11/98, page 353 of 975 Rev. 0.1, 11/98, page 354 of 975 Section 19 12-Bit PWM 19.1 Overview The 12-bit PWM incorporates 2 channels of the pulse pitch control method and functions as the drum and capstan motor controller. 19.1.1 Features Two on-chip 12-bit PWM signal generators are provided to control motors. These PWMs use the pulse-pitch control method (periodically overriding part of the output). This reduces lowfrequency components in the pulse output, enabling a quick response without increasing the clock frequency. The pitch of the PWM signal is modified in response to error data (representing lead or lag in relation to a preset speed and phase). Rev. 0.1, 11/98, page 355 of 975 19.1.2 Block Diagram Figure 19.1 shows a block diagram of the 12-bit PWM (1 channel). The PWM signal is generated by combining quantizing pulses from a 12-bit pulse generator with quantizing pulses derived from the contents of a data register. Low-frequency components are reduced because the two quantizing pulses have different frequencies. The error data is represented by an unsigned 12-bit binary number. /2 /4 /8 /16 /32 /64 /128 Counter Pulse generator Output control circuit CAPPWM or DRMPWM PWM data register PWM control register Error data Internal data bus Digital filter circuit * DFUCR [Legend] CAPPWM : Capstan mix pin DRMPWM : Drum mix pin Figure 19.1 Block Diagram of 12-Bit PWM (1 channel) Rev. 0.1, 11/98, page 356 of 975 PTON CP/DP 19.1.3 Pin Configuration Table 19.1 shows the 12-bit PWM pin configuration. Table 19.1 Pin Configuration Name Abbrev. I/O Function Capstan mix CAPPWM Output 12-bit PWM square-wave output Drum mix DRMPWM 19.1.4 Register Configuration Table 19.2 shows the 12-bit PWM register configuration. Table 19.2 12-Bit PWM Registers Name Abbrev. R/W Size Initial Value Address* 12-bit PWM control register CPWCR W Byte H'42 H'D07B DPWCR W Byte H'42 H'D07A CPWDR R/W Word H'F000 H'D07C DPWDR R/W Word H'F000 H'D078 12-bit PWM data register Note: * Lower 16 bits of the address. Rev. 0.1, 11/98, page 357 of 975 19.2 Register Descriptions 19.2.1 12-Bit PWM Control Registers (CPWCR, DPWCR) (1) CPWCR Bit : Initial value : R/W : 7 CPOL 6 CDC 5 CHiZ 4 CH/L 3 CSF/DF 2 CCK2 1 CCK1 0 CCK0 0 W 1 W 0 W 0 W 0 W 0 W 1 W 0 W 7 DPOL 6 DDC 5 DHiZ 4 DH/L 3 DSF/DF 2 DCK2 1 DCK1 0 DCK0 0 W 1 W 0 W 0 W 0 W 0 W 1 W 0 W (2) DPWCR Bit : Initial value : R/W : CPWCR is the PWM output control register for the capstan motor. DPWCR is the PWM output control register for the drum motor. Both are 8-bit writable registers. CPWCR and DPWCR are initialized to H'42 by a reset, or when in standby or module-stop mode. Bit 7: Polarity Invert (POL) This bit can invert the polarity of the modulated PWM signal for noise suppression and other purposes. This bit is invalid when fixed output is selected (when bit DC is set to 1). Bit 7 POL Description 0 Output with positive polarity 1 Output with inverted polarity Rev. 0.1, 11/98, page 358 of 975 (Initial value) Bit 6: Output Select (DC) Selects either PWM modulated output, or fixed output controlled by the pin output bits (Bits 5 and 4). Bits 5 and 4: PWM Pin Output (HiZ, H/L) When bit DC is set to 1, the 12-bit PWM output pins (CAPPWM, DRMPWM) output a value determined by the HiZ and H/L bits. The output is not affected by bit POL. In power-down modes, the 12-bit PWM circuit and pin statuses are retained. Before making a transition to a power-down mode, first set bits 6 (DC), 5 (HiZ), and 4 (H/L) of the 12-bit PWM control registers (CPWCR and DPWCR) to select a fixed output level. Choose one of the following settings: Bit 6 Bit 5 Bit 4 DC HiZ H/L Output state 1 0 0 Low output 1 High output 1 * High-impedance * * Modulation signal output 0 Note: * (Initial value) Don't care Bit 3: Output Data Select (SF/DF) Selects whether the data to be converted to PWM output is taken from the data register or from the digital filter circuit. Bit SF/DF Description 0 Modulation by error data from the digital filter circuit 1 Modulation by error data written in the data register (Initial value) Note: When PWMs output data from the digital filter circuit, the data consisting of the speed and phase filtering results are modulated by PWMs and output from the CAPPWM and DRMPWM pins. However, it is possible to output only drum phase filter results from CAPPWM pin and only capstan phase filter result from DRMPWM pin, by DFUCR settings of the digital filter circuit. See the section explaining the digital filter computation circuit. Rev. 0.1, 11/98, page 359 of 975 Bit 2 to 0: Carrier Frequency Select (CK2 to CK0) Selects the carrier frequency of the PWM modulated signal. Do not set them to 111. Bit 2 Bit 1 Bit 0 CK2 CK1 CK0 Description 0 0 0 2 1 4 0 8 1 16 0 32 1 64 0 128 1 (Do not set) 1 1 0 1 Rev. 0.1, 11/98, page 360 of 975 (Initial value) 19.2.2 12-Bit PWM Data Registers (DPWDR, CPWDR) (1) CPWDR Bit : Initial value : R/W : 15 14 13 12 -- -- -- -- 11 10 9 8 7 6 5 4 3 2 1 0 CPWDR11 CPWDR10 CPWDR9 CPWDR8 CPWDR7 CPWDR6 CPWDR5 CPWDR4 CPWDR3 CPWDR2 CPWDR1 CPWDR0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 -- -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W (2) DPWDR Bit : 15 14 13 12 -- -- -- -- Initial value : 1 R/W : -- 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 11 10 9 8 7 6 5 4 3 2 1 0 DPWDR11 DPWDR10 DPWDR9 DPWDR8 DPWDR7 DPWDR6 DPWDR5 DPWDR4 DPWDR3 DPWDR2 DPWDR1 DPWDR0 The 12-bit PWM data registers (DPWDR and CPWDR) are 12-bit readable/writable registers in which the data to be converted to PWM output is written. The data in these registers is converted to PWM output only when bit SF/DF of the corresponding control register is set to 1. The error data from the digital filter circuit is written in the data register, and then modulated by PWM. At this time, the error data from the digital filter circuit can be monitored by reading the data register. These registers can be accessed by word only, and cannot be accessed by byte. Byte access gives unassured results. Both registers are initialized to H'F000 by a reset. Rev. 0.1, 11/98, page 361 of 975 19.3 Operation 19.3.1 Output Waveform The PWM signal generator combines the error data with the output from an internal pulse generator to produce a pulse-width modulated signal. When Vcc/2 is set as the reference value, the following conditions apply: * When the motor is running at the correct sped and phase, the PWM signal is output with a 50% duty cycle. * When the motor is running behind the correct speed or phase, it is corrected by periodically holding part of the PWM signal low. The part held low depends on the size of the error. * When the motor is running ahead of the correct speed or phase, it is corrected by periodically holding part of the PWM signal high. The part held high depends on the size of the error. When the motor is running at the correct speed and phase, the error data is a 12-bit value representing 1/2 (1000 0000 0000), and the PWM output has the same frequency as the selected division clock. After the error data has been converted into a PWM signal, the PWM signal can be smoothed into a DC voltage by an external low-pass filter (LPF). The smoothes error data can be used to control the motor. Figure 19.2 shows sample waveform outputs. The 12-bit PWM pin outputs a low-level signal upon reset, in power-down mode or at modulestop. Rev. 0.1, 11/98, page 362 of 975 Figure 19.2 Sample Waveform Output by 12-Bit PWM (4 Bits) Rev. 0.1, 11/98, page 363 of 975 C13 C12 C11 C10 PWM data register Pwr3 2 1 0 "L" 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Corresponds to Pwr0=1 Corresponds to Pwr1=1 Corresponds to Pwr2=1 Pulse Generator Corresponds to Pwr3=1 Counter 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 Rev. 0.1, 11/98, page 364 of 975 Section 20 14-Bit PWM 20.1 Overview The 14-bit PWM is a pulse division type PWM which can be used for V-synthesizer, etc. 20.1.1 Features Features of the 14-bit PWM are given below: * Choice of two conversion periods A conversion period of 32768/ with a minimum modulation width of 2/, or a conversion period of 16384/ with a minimum modulation width of 1/, can be selected. * Pulse division method for less ripple Rev. 0.1, 11/98, page 365 of 975 20.1.2 Block Diagram Figure 20.1 shows a block diagram of the 14-bit PWM. PWDRL PWDRU /4 PWM waveform generator /2 [Legend] PWCR : PWM control register PWDRL : PWM data register L PWDRU: PWM data register U PWM14 : PWM14 output pin Figure 20.1 Block Diagram of 14-Bit PWM Rev. 0.1, 11/98, page 366 of 975 Internal data bus PWCR PWM14 20.1.3 Pin Configuration Table 20.1 shows the 14-bit PWM pin configuration. Table 20.1 Pin Configuration Name Abbrev. I/O Function PWM 14-bit square-wave output pin PWM14* Output 14-bit PWM square-wave output Note: * 20.1.4 This pin also functions as P40 general I/O pin. When using this pin, set the pin function by the port mode register 4 (PMR4). For details, see section 10.6, Port 4. Register Configuration Table 20.2 shows the 14-bit PWM register configuration. Table 20.2 14-Bit PWM Registers Name Abbrev. R/W Size Initial Value Address* PWM control register PWCR R/W Byte H'FE H'D122 PWM data register U PWDRU W Byte H'00 H'D121 PWM data register L PWDRL W Byte H'00 H'D120 Note: * Lower 16 bits of the address. 20.2 Register Descriptions 20.2.1 PWM Control Register (PWCR) Bit : 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 PWCR0 Initial value : R/W : 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 0 R/W The PWM control register (PWCR) is an 8-bit read/write register that controls the 14-bit PWM functions. PWCR is initialized to H'FE by a reset. Bits 7 to 1: Reserved These bits are reserved. They are always read as 1. Writes are disabled. Rev. 0.1, 11/98, page 367 of 975 Bit 0: Clock Select (PWCR0) Selects the clock supplied to the 14-bit PWM. Bit 0 PWCR0 Description 0 The input clock is /2 (t = 2/) (Initial value) The conversion period is 16384/, with a minimum modulation width of 1/ 1 The input clock is /4 (t = 4/) The conversion period is 32768/, with a minimum modulation width of 2/ Note: t/: Period of PWM clock input 20.2.2 PWM Data Registers U and L (PWDRU, PWDRL) (1) PWDRU Bit : 7 -- 6 -- Initial value : R/W : 1 -- 1 -- 5 4 3 2 1 0 PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0 0 W 0 W 0 W 0 W 0 W 0 W (2) PWDRL Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W PWM data registers U and L (PWDRU and PWDRL) indicate high level width in one PWN waveform cycle. PWDRU and PWDRL form a 14-bit write-only register, with the upper 6 bits assigned to PWDRU and the lower 8 bits to PWDRL. The value written in PWDRU and PWDRL gives the total high-level width of one PWM waveform cycle. Both PWDRU and PWDRL are accessible by byte access only. Word access gives unassured results. When 14-bit data is written in PWDRU and PWDRL, the contents are latched in the PWM waveform generator and the PWM waveform generation data is updated. When writing the 14bit data, follow these steps: (1) Write the lower 8 bits to PWDRL. (2) Write the upper 6 bits to PWDRU. Rev. 0.1, 11/98, page 368 of 975 Write the data first to PWDRL and then to PWDRU. PWDRU and PWDRL are write-only registers. When read, all bits always read 1. PWDRU and PWDRL are initialized to H'C000 by a reset. 20.2.3 Module Stop Control Register (MSTPCR) MSTPCRH Bit : 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The module stop control register (MSTPCR) consists of two 8-bit readable/writable registers that control the module stop mode functions. When the MSTP5 bit is set to 1, the 14-bit PWM operation stops at the end of the bus cycle and a transition is made to module stop mode. For details, see section 4.5, Module Stop Mode. MSTPCR is initialized to H'FFFF by a reset. Bit 5: Module Stop (MSTP5) Specifies the module stop mode of the 14-bit PWM. MSTPCRL Bit 5 MSTP5 Description 0 14-bit PWM module stop mode is released 1 14-bit PWM module stop mode is set (Initial value) Rev. 0.1, 11/98, page 369 of 975 20.3 14-Bit PWM Operation When using the 14-bit PWM, set the registers in this sequence: (1) Set bit PWM40 to 1 in port mode register 4 (PMR4) so that pin P40/PWM14 is designated for PWM output. (2) Set bit PWCR0 in the PWM control register (PWCR) to select a conversion period of either 32768/ (PWCR0 = 1) or 16384/ (PWCR0 = 0). (3) Set the output waveform data in PWM data registers U and L (PWDRU, PWDRL). Be sure to write byte data first to PWDRL and then to PWDRU. When the data is written in PWDRU, the contents of these registers are latched in the PWM waveform generator, and the PWM waveform generation data is updated in synchronization with internal signals. One conversion period consists of 64 pulses, as shown in figure 20.2. The total high-level width during this period (TH) corresponds to the data in PWDRU and PWDRL. This relation can be expressed as follows: TH = (data value in PWDRU and PWDRL + 64) x t/2 where to is the period of PWM clock input: 2/ (bit PWCR0 = 0) or 4/ (bit PWCR0 = 1). If the data value in PWDRU and PWDRL is from H'3FC0 to H'3FFF, the PWM output stays high. When the data value is H'0000, TH is calculated as follows: TH = 64 x t/2 = 32 t 1 conversion period t f1 t H1 t f2 t H2 t f63 t H3 t H63 t f64 t H64 T H = t H1 + t H2 + t H3 + ... + t H64 t f1 = t f2 = t f3 = ... = t f64 Figure 20.2 Waveform Output by 14-Bit PWM Rev. 0.1, 11/98, page 370 of 975 Section 21 Prescalar Unit 21.1 Overview The prescalar unit (PSU) has a 18-bit free running counter (FRC) that uses as a clock source and a 5-bit counter that uses W as a clock source. 21.1.1 Features * Prescalar S (PSS): Generates frequency division clocks that are input to peripheral functions. * Prescalar W (PSW): When a timer A is used as a clock time base, the PSW frequency-divides subclocks and generates input clocks. * Stable oscillation wait time count: During the return from the low power consumption mode excluding the sleep mode, the FRC counts the stable oscillation wait time. * 8-bit PWM The lower 8 bits of the FRC is used as 8-bit PWM cycle and duty cycle generation counters. (Conversion cycle: 256 states) * 8-bit input capture by ,& pins Catches the 8 bits of 215 to 28 of the FRC according to the edge of the ,& pin for remote control receiving. * Frequency division clock output: Can output the frequency division clock for the system clock or the frequency division clock for the subclock from the frequency division clock output pin (TMOW). Rev. 0.1, 11/98, page 371 of 975 21.1.2 Block Diagram Figure 21.1 shows a block diagram of the prescalar unit. PWM3 PWM2 PWM1 PWM0 Stable oscillation wait time count output Prescalar S /131072 to /2 MSB 27 6 bits 212 27 28 8 bits LSB 18-bit free running counter (FRC) 215 8 bits 28 IC pin /32 /4 /8 w/32 ICR1 Interrupt request /16 w/16 TMOW pin w/8 Prescalar W w/128 w/4 MSB 5-bit counter PCSR Internal data bus [Legend] ICR1 : Input capture register 1 PCSR : Prescalar unit control/status register IC : Input capture input pin TMOW : Frequency division clock output pin Figure 21.1 Block Diagram of Prescalar Unit Rev. 0.1, 11/98, page 372 of 975 LSB 21.1.3 Pin Configuration Table 21.1 shows the pin configuration of the prescalar unit. Table 21.1 Pin Configuration Name Abbrev. I/O Function Input capture input ,& Input Prescalar unit input capture input pin Frequency division clock output TMOW Output Prescalar unit frequency division clock output pin 21.1.4 Register Configuration Table 21.2 shows the register configuration of the prescalar unit. Table 21.2 Register Configuration Name Abbrev. R/W Size Initial Value Address* Input capture register 1 ICR1 R Byte H'00 H'D12C R/W Byte H'08 H'D12D Prescalar unit control/status PCSR register Note: * Lower 16 bits of the address. Rev. 0.1, 11/98, page 373 of 975 21.2 Registers 21.2.1 Input Capture Register 1 (ICR1) Bit : Initial value : R/W : 7 ICR17 6 ICR16 5 ICR15 4 ICR14 3 ICR13 2 ICR12 1 ICR11 0 ICR10 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 15 8 Input capture register 1 (ICR1) captures 8-bit data of 2 to 2 of the FRC according to the edge of the ,& pin. ICR1 is an 8-bit read-only register. The write operation becomes invalid. The ICR1 values are undefined until the first capture is generated after the mode has been set to the standby mode, watch mode, subactive mode, and subsleeve mode. When reset, ICR1 is initialized to H'00. 21.2.2 Prescalar Unit Control/Status Register (PCSR) Bit : Initial value : R/W : 7 ICIF 6 ICIE 5 ICEG 4 NCon/off 3 -- 2 DCS2 1 DCS1 0 DCS0 0 R/(W)* 0 R/W 0 R/W 0 R/W 1 -- 0 R/W 0 R/W 0 R/W Note: * Only 0 can be written to clear the flag. The prescalar unit control/status register (PCSR) controls the input capture function and selects the frequency division clock that is output from the TMOW pin. PCSR is an 8-bit read/write enable register. When reset, PCSR is initialized to H'08. Bit 7: Input Capture Interrupt Flag (ICIF) Input capture interrupt request flag. This indicates that the input capture was performed according to the edge of the ,& pin. Bit 7 ICIF Description 0 [Clear condition] When 0 is written after 1 has been read 1 [Set condition] When the input capture was performed according to the edge of the ,& pin Rev. 0.1, 11/98, page 374 of 975 (Initial value) Bit 6: Input Capture Interrupt Enable (ICIE) When ICIF was set to 1 by the input capture according to the edge of the ,& pin, ICIE enables and disables the generation of an input capture interrupt. Bit 6 ICIE Description 0 Disables the generation of an input capture interrupt 1 Enables the generation of an input capture interrupt (Initial value) Bit 5: ,& Pin Edge Select (ICEG) ICEG selects the input edge sense of the ,& pin. Bit 5 ICEG Description 0 Detects the falling edge of the ,& pin input 1 Detects the rising edge of the ,& pin input (Initial value) Bit 4: Noise Cancel ON/OFF (NCon/off) NCon/off selects enable/disable of the noise cancel function of the ,& pin. For the noise cancel function, see section 21.3, Noise Cancel Circuit. Bit 4 NCon/off Description 0 Disables the noise cancel function of the ,& pin 1 Enables the noise cancel function of the ,& pin (Initial value) Bit 3: Reseved Bit Reserved bit. When the bit is read, 1 is always read. The write operation is invalid. Rev. 0.1, 11/98, page 375 of 975 Bits 2 to 0: Frequency Division Clock Output Select (DCS2 to DCS0) DCS2 to DCS0 select eight types of frequency division clocks that are output from the TMOW pin. Bit 2 Bit 1 Bit 0 DCS2 DCS1 DCS0 Description 0 0 0 Outputs PSS, /32 1 Outputs PSS, /16 0 Outputs PSS, /8 1 Outputs PSS, /4 0 Outputs PSW, W/32 1 Outputs PSW, W/16 0 Outputs PSW, W/8 1 Outputs PSW, W/4 1 1 0 1 21.2.3 (Initial value) Port Mode Register 1 (PMR1) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PMR17 PMR16 PMR15 PMR14 PMR13 PMR12 PMR11 PMR10 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The port mode register 1 (PMR1) controls switching of each pin function of port 1. The switching is specified in a unit of bit. PMR1 is an 8-bit read/write enable register. When reset, PMR1 is initialized to H'00. Bit 7: P17/TMOW Pin Switching (PMR17) PMR17 sets whether the P17/TMOW pin is used as a P17 I/O pin or a TMOW pin for division clock output. Bit 7 PMR17 Description 0 The P17/TMOW pin functions as a P17 I/O pin 1 The P17/TMOW pin functions as a TMOW pin for division clock output Rev. 0.1, 11/98, page 376 of 975 (Initial value) Bit 6: P16/,& Pin Switching (PMR16) PMR16 sets whether the P16/,& pin is used as a P16 I/O pin or an ,& pin for the input capture input of the prescalar unit. Bit 6 PMR16 Description 0 The P16/,& pin functions as a P16 I/O pin 1 The P16/,& pin functions as an ,& input function 21.3 (Initial value) Noise Cancel Circuit The ,& pin has a built-in a noise cancel circuit. The circuit can be used for noise protection such as remote control receiving. The noise cancel circuit samples the input values of the ,& pin twice at an interval of 256 states. If the input values are different, they are assumed to be noise. The ,& pin can specify enable/disable of the noise cancel function according to the bit 4 (NCon/off) of the prescalar unit control/status register (PCSR). 21.4 Operation 21.4.1 Prescalar S (PSS) The PSS is a 17-bit counter that uses the system clock (=fosc) as an input clock and generates the frequency division clocks (/131072 to /2) of the peripheral function. The low-order 17 bits of the 18-bit free running counter (FRC) correspond to the PSS. The FRC is incremented by one clock. The PSS output is shared by the timer and serial communication interface (SCI), and the frequency division ratio can independently be set by each built-in peripheral function. When reset, the FRC is initialized to H'00000, and starts increment after reset has been released. Because the system clock oscillator is stopped in standby mode, watch mode, subactive mode, and subsleep mode, the PSS operation is also stopped. In this case, the FCR is also initialized to H'00000. The FRC cannot be read and written from the CPU. Rev. 0.1, 11/98, page 377 of 975 21.4.2 Prescalar W (PSW) PSW is a counter that uses the subclock as an input clock. The PSW also generates the input clock of the timer A. In this case, the timer A functions as a clock time base. When reset, the PSW is initialized to H'00, and starts increment after reset has been released. Even if the mode has been shifted to the standby mode *, watch mode *, subactive mode *, and subsleep mode *, the PSW continues the operation as long as the clocks are supplied by the X1 and X2 pins. The PSW can also be initialized to H'00 by setting the TMA3 and TMA2 bits of the timer mode register A (TMA) to 11. Note: * When the timer A is in module stop mode, the operation is stopped. Figure 21.2 shows the supply of the clocks to the peripheral function by the PSS and PSW. /131072 to /2 OSC1 OSC2 System fosc clock oscillator X1 Subclock oscillator X2 (fx) w System clock duty correction circuit Subclock frequency dividers (1/2, 1/4, and 1/8) Prescalar S Intermediate speed clock frequency divider w/4 Timer SCI TMOW pin w/128 Prescalar W System clock selection Timer A CPU ROM RAM Peripheral register I/O port Figure 21.2 Clock Supply 21.4.3 Stable Oscillation Wait Time Count For the count of the stable oscillation stable wait time during the return from the low power consumption mode excluding the sleep mode, see section 4, Power-Down State. Rev. 0.1, 11/98, page 378 of 975 21.4.4 8-Bit PWM This 8-bit PWM controls the duty control PWM signal in the conversion cycle 256 states. It 7 0 counts the cycle and the duty cycle at 2 to 2 of the FRC. It can be used for controlling reel motors and loading motors. For details, see section 18, 8-Bit PWM. 21.4.5 8-Bit Input Capture Using ,& Pin This function catches the 8-bit data of 2 to 2 of the FRC according to the edge of the ,& pin. It can be used for remote control receiving. For the edge of the ,& pin, the rising and falling edges can be selected. The ,& pin has a built-in noise cancel circuit. See section 21.3, Noise Cancel Circuit. An interrupt request is generated due to the input capture using the ,& pin. 15 8 Note: Rewriting the ICEG bit, NCon/off bit, or PMR16 bit is incorrectly recognized as edge detection according to the combinations between the state and detection edge of the ,& pin and the ICIF bit may be set after up to 384 seconds. 21.4.6 Frequency Division Clock Output The frequency division clock can be output from the TMOW pin. For the frequency division clock, eight types of clocks can be selected according to the DCS2 to DCS0 bits in PCSR. The clock in which the system clock was frequency-divided is output in active mode and sleep mode and the clock in which the subclock was frequency-divided is output in active mode*, sleep mode*, and subactive mode. Note: * When the timer A is in module stop mode, no clock is output. Rev. 0.1, 11/98, page 379 of 975 Rev. 0.1, 11/98, page 380 of 975 Section 22 Serial Communication Interface 1 (SCI1) 22.1 Overview The serial communication interface (SCI) can handle both asynchronous and clocked synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function). 22.1.1 Features SCI1 features are listed below. (1) Choice of asynchronous or synchronous serial communication mode (a) Asynchronous mode * Serial data communication is executed using an asynchronous system in which synchronization is achieved character by character Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA) * A multiprocessor communication function is provided that enables serial data communication with a number of processors * Choice of 12 serial data transfer formats Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Multiprocessor bit: 1 or 0 * Receive error detection: Parity, overrun, and framing errors * Break detection: Break can be detected by reading the SI1 pin level directly in case of a framing error (b) Clock synchronous mode * Serial data communication is synchronized with a clock Serial data communication can be carried out with other chips that have a synchronous communication function * One serial data transfer format Data length: 8 bits * Receive error detection: Overrun errors detected Rev. 0.1, 11/98, page 381 of 975 (2) Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data (3) Built-in baud rate generator allows any bit rate to be selected (4) Choice of serial clock source: internal clock from baud rate generator or external clock from SCK1 pin (5) Four interrupt sources Four interrupt sources (transmit-data-empty, transmit-end, receive-data-full, and receive error) that can issue requests independently 22.1.2 Block Diagram Module data bus RDR TDR BRR SCMR SSR SCR SI1 RSR TSR Baud rate generator SMR Transmission/ reception control Clock Parity gfeneration SO1 /4 /16 /64 Parity check External clock SCK [Legend] RSR RDR TSR TDR SMR SCR SSR SCMR BRR : Receive shift register : Receive data register : Transmit shift register : Transmit data register : Serial mode register : Serial control register : Serial status register : Serial interface mode register : Bit rate register Figure 22.1 Block Diagram of SCI Rev. 0.1, 11/98, page 382 of 975 TEI TXI RXI ERI Internal data bus Bus interface Figure 22.1 shows a block diagram of the SCI. 22.1.3 Pin Configuration Table 22.1 shows the serial pins used by the SCI. Table 22.1 SCI Pins Channel Pin Name Symbol I/O Function 1 Serial clock pin 1 SCK1 I/O SCI1 clock input/output Receive data pin 1 SI1 Input SCI1 receive data input Transmit data pin 1 SO1 Output SCI1 transmit data output 22.1.4 Register Configuration The SCI1 has the internal registers shown in table 22.2. These registers are used to specify asynchronous mode or synchronous mode, the data format, and the bit rate, and to control the transmitter/receiver. Table 22.2 SCI Registers Channel Name Abbrev. R/W Initial Value Address*1 1 Serial mode register 1 SMR1 R/W H'00 H'D148 Bit rate register 1 BRR1 R/W H'FF H'D149 Serial control register 1 SCR1 R/W H'00 H'D14A Transmit data register 1 TDR1 R/W H'FF H'D14B H'84 H'D14C Common 2 Serial status register 1 SSR1 R/(W)* Receive data register 1 RDR1 R H'00 H'D14D Serial interface mode register 1 SCMR1 R/W H'F2 H'D14E Module stop control register MSTPCRH R/W H'FF H'FFEC MSTPCRL R/W H'FF H'FFED Notes: 1. Lower 16 bits of the address. 2. Only 0 can be written, to clear flags. Rev. 0.1, 11/98, page 383 of 975 22.2 Register Descriptions 22.2.1 Receive Shift Register (RSR) Bit : 7 6 5 4 3 2 1 0 R/W : -- -- -- -- -- -- -- -- RSR is a register used to receive serial data. The SCI sets serial data input from the SI1 pin in RSR in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly read or written to by the CPU. 22.2.2 Receive Data Register (RDR) Bit : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 R/W : R R R R R R R R RDR is a register that stores received serial data. When the SCI has received one byte of serial data, it transfers the received serial data from RSR to RDR where it is stored, and completes the receive operation. After this, RSR is receiveenabled. Since RSR and RDR function as a double buffer in this way, continuous receive operations can be performed. RDR is a read-only register, and cannot be written to by the CPU. RDR is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. Rev. 0.1, 11/98, page 384 of 975 22.2.3 Transmit Shift Register (TSR) Bit : 7 6 5 4 3 2 1 0 R/W : -- -- -- -- -- -- -- -- TSR is a register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the SO1 pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from TDR to TSR, and transmission started, automatically. However, data transfer from TDR to TSR is not performed if the TDRE bit in SSR is set to 1. TSR cannot be directly read or written to by the CPU. 22.2.4 Transmit Data Register (TDR) Bit : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W : TDR is an 8-bit register that stores data for serial transmission. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts serial transmission. Continuous serial transmission can be carried out by writing the next transmit data to TDR during serial transmission of the data in TSR. TDR can be read or written to by the CPU at all times. TDR is initialized to H'FF by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. Rev. 0.1, 11/98, page 385 of 975 22.2.5 Serial Mode Register (SMR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W SMR is an 8-bit register used to set the SCI's serial transfer format and select the baud rate generator clock source. SMR can be read or written to by the CPU at all times. SMR is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. Bit 7: Communication Mode (C/$) Selects asynchronous mode or clock synchronous mode as the SCI operating mode. Bit 7 C/$ Description 0 Asynchronous mode 1 Clock synchronous mode (Initial value) Bit 6: Character Length (CHR) Selects 7 or 8 bits as the data length in asynchronous mode. In synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting. Bit 6 CHR Description 0 8-bit data 1 7-bit data* Note: * (Initial value) When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and LSBfirst/MSB-first selection is not available. Rev. 0.1, 11/98, page 386 of 975 Bit 5: Parity Enable (PE) In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In synchronous mode, or when a multiprocessor format is used, parity bit addition and checking is not performed, regardless of the PE bit setting. Bit 5 PE Description 0 Parity bit addition and checking disabled 1 Note: (Initial value) Parity bit addition and checking enabled* * When the PE bit is set to 1, the parity (even or odd) specified by the O/( bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/( bit. Bit 4: Parity Mode (O/() Selects either even or odd parity for use in parity addition and checking. The O/( bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. The O/( bit setting is invalid in synchronous mode, when parity bit addition and checking is disabled in asynchronous mode, and when a multiprocessor format is used. Bit 4 O/( Description 0 Even parity 1 *1 (Initial value) *2 Even parity Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. Rev. 0.1, 11/98, page 387 of 975 Bit 3: Stop Bit Length (STOP) Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bit setting is only valid in asynchronous mode. If synchronous mode is set the STOP bit setting is invalid since stop bits are not added. Bit 3 STOP Description *1 0 1 stop bit (Initial value) *2 1 2 stop bits Notes: 1. In transmission, a single 1 bit (stop bit) is added to the end of a transmit character before it is sent. 2. In transmission, two 1 bits (stop bits) are added to the end of a transmit character before it is sent. In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. Bit 2: Multiprocessor Mode (MP) Selects multiprocessor format. When multiprocessor format is selected, the PE bit and O/( bit parity settings are invalid. The MP bit setting is only valid in asynchronous mode; it is invalid in synchronous mode. For details of the multiprocessor communication function, see section 22.3.3, Multiprocessor Communication Function. Bit 2 MP Description 0 1 Multiprocessor function disabled Multiprocessor format selected (Initial value) Bits 1 and 0: Clock Select 1 and 0 (CKS1, CKS0) These bits select the clock source for the baud rate generator. The clock source can be selected from , /4, /16, and /64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 22.2.8, Bit Rate Register. Bit 1 CKS1 0 1 Bit 0 CKS0 0 1 0 1 Description clock /4 clock /16 clock /64 clock Rev. 0.1, 11/98, page 388 of 975 (Initial value) 22.2.6 Serial Control Register (SCR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. SCR can be read or written to by the CPU at all times. SCR is initialized to H'00 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. Bit 7: Transmit Interrupt Enable (TIE) Enables or disables transmit-data-empty interrupt (TXI) request generation when serial transmit data is transferred from TDR to TSR and the TDRE flag in SSR is set to 1. Bit 7 TIE Description 0 Transmit-data-empty interrupt (TXI) request disabled* 1 Transmit-data-empty interrupt (TXI) request enabled Note: * (Initial value) TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or clearing the TIE bit to 0. Bit 6: Receive Interrupt Enable (RIE) Enables or disables receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request generation when serial receive data is transferred from RSR to RDR and the RDRF flag in SSR is set to 1. Bit 6 RIE Description 0 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request disabled* (Initial value) 1 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request enabled Note: * RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF, FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to 0. Rev. 0.1, 11/98, page 389 of 975 Bit 5: Transmit Enable (TE) Enables or disables the start of serial transmission by the SCI. Bit 5 TE Description *1 0 Transmission disabled (Initial value) *2 1 Transmission enabled Notes: 1. The TDRE flag in SSR is fixed at 1. 2. In this state, serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0. SMR setting must be performed to decide the transmission format before setting the TE bit to 1. Bit 4: Receive Enable (RE) Enables or disables the start of serial reception by the SCI. Bit 4 RE 0 1 Notes: Description *1 Reception disabled *2 Reception enabled (Initial value) 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. 2. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. SMR setting must be performed to decide the reception format before setting the RE bit to 1. Bit 3: Multiprocessor Interrupt Enable (MPIE) Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when receiving with the MP bit in SMR set to 1. The MPIE bit setting is invalid in clock synchronous mode or when the MP bit is cleared to 0. Bit 3 MPIE 0 1 Note: * Description Multiprocessor interrupts disabled (normal reception performed) (Initial value) [Clearing conditions] (1) When the MPIE bit is cleared to 0 (2) When data with MPB = 1 is received Multiprocessor interrupts enabled* Receive interrupt (RXI) requests, receive-error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received. When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR , is not performed. When receive data with MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled. Rev. 0.1, 11/98, page 390 of 975 Bit 2: Transmit End Interrupt Enable (TEIE) Enables or disables transmit-end interrupt (TEI) request generation if there is no valid transmit data in TDR when the MSB is transmitted. Bit 2 TEIE Description 0 Transmit-end interrupt (TEI) request disabled* 1 Transmit-end interrupt (TEI) request enabled* Note: * (Initial value) TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0. Bits 1 and 0: Clock Enable 1 and 0 (CKE1, CKE0) These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or the serial clock input pin. The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in asynchronous mode. The CKE0 bit setting is invalid in synchronous mode, and in the case of external clock operation (CKE1 = 1). Note that the SCI's operating mode must be decided using SMR before setting the CKE1 and CKE0 bits. For details of clock source selection, see table 22.9 in section 22.3, Operation. Bit 1 CKE1 Bit 0 CKE0 Description 0 0 Asynchronous mode 1 1 0 1 *1 Internal clock/SCK pin functions as I/O port Clock synchronous mode Internal clock/SCK pin functions as serial *1 clock output Asynchronous mode Internal clock/SCK pin functions as clock *2 output Clock synchronous mode Internal clock/SCK pin functions as serial clock output Asynchronous mode External clock/SCK pin functions as clock *3 input Clock synchronous mode External clock/SCK pin functions as serial clock input Asynchronous mode External clock/SCK pin functions as clock *3 input Clock synchronous mode External clock/SCK pin functions as serial clock input Notes: 1. Initial value 2. Outputs a clock of the same frequency as the bit rate. 3. Inputs a clock with a frequency 16 times the bit rate. Rev. 0.1, 11/98, page 391 of 975 22.2.7 Serial Status Register (SSR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT 1 0 0 0 0 1 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Note: * Only 0 can be written to clear the flag. SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits. SSR can be read or written to by the CPU at all times. However, 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified. SSR is initialized to H'84 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. Bit 7: Transmit Data Register Empty (TDRE) Indicates that data has been transferred from TDR to TSR and the next serial data can be written to TDR. Bit 7 TDRE Description 0 [Clearing conditions] (1) When 0 is written in TDRE after reading TDRE = 1 (2) When the DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] (Initial value) (1) When the TE bit in SCR is 0 (2) When data is transferred from TDR to TSR and data can be written to TDR Rev. 0.1, 11/98, page 392 of 975 Bit 6: Receive Data Register Full (RDRF) Indicates that the received data is stored in RDR. Bit 6 RDRF Description 0 [Clearing conditions] When 0 is written in RDRF after reading RDRF = 1 1 [Setting conditions] When serial reception ends normally and receive data is transferred from RSR to RDR (Initial value) Note: RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCR is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost. Bit 5: Overrun Error (ORER) Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 5 ORER Description 0 [Clearing conditions] When 0 is written in ORER after reading ORER = 1 1 [Setting conditions] *2 When the next serial reception is completed while RDRF = 1 (Initial value) *1 Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1. In synchronous mode, serial transmission cannot be continued, either. Rev. 0.1, 11/98, page 393 of 975 Bit 4: Framing Error (FER) Indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. Bit 4 FER Description 0 [Clearing conditions] When 0 is written in FER after reading FER = 1 1 [Setting conditions] When the SCI checks the stop bit at the end of the receive data when reception ends, *2 and the stop bit is 0 (Initial value) *1 Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the FER flag is set to 1. In synchronous mode, serial transmission cannot be continued, either. Bit 3: Parity Error (PER) Indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. Bit 4 PER Description 0 [Clearing conditions] When 0 is written in PER after reading PER = 1 1 [Setting conditions] When, in reception, the number of 1 bits in the receive data plus the parity bit does *2 not match the parity setting (even or odd) specified by the O/( bit in SMR (Initial value) *1 Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In synchronous mode, serial transmission cannot be continued, either. Rev. 0.1, 11/98, page 394 of 975 Bit 2: Transmit End (TEND) Indicates that there is no valid data in TDR when the last bit of the transmit character is sent, and transmission has been ended. The TEND flag is read-only and cannot be modified. Bit 2 TEND Description 0 [Clearing conditions] (1) When 0 is written in TDRE after reading TDRE = 1 1 [Setting conditions] (Initial value) (1) When the TE bit in SCR is 0 (2) When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character Bit 1: Multiprocessor Bit (MPB) When reception is performed using a multiprocessor format in asynchronous mode, MPB stores the multiprocessor bit in the receive data. MPB is a read-only bit, and cannot be modified. Bit 1 MPB Description 0 [Clearing conditions] When data with a 0 multiprocessor bit is received 1 [Setting conditions] When data with a 1 multiprocessor bit is received Note: * (Initial value)* Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor format. Bit 0: Multiprocessor Bit Transfer (MPBT) When transmission is performed using a multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to the transmit data. The MPBT bit setting is invalid when a multiprocessor format is not used, when not transmitting, and in synchronous mode. Bit 0 MPBT Description 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted (Initial value) Rev. 0.1, 11/98, page 395 of 975 22.2.8 Bit Rate Register (BRR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SMR. BRR can be read or written to by the CPU at all times. BRR is initialized to H'FF by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. Table 22.3 shows sample BRR settings in asynchronous mode, and table 22.4 shows sample BRR settings in synchronous mode. Table 22.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency (MHz) 2 2.097152 2.4576 3 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 1 141 0.03 1 148 -0.04 1 174 -0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 -0.70 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 -2.48 0 15 0.00 0 19 -2.34 9600 0 6 -2.48 0 7 0.00 0 9 -2.34 19200 0 3 0.00 0 4 -2.34 31250 0 1 0.00 0 0 2 0.00 38400 0 1 0.00 Rev. 0.1, 11/98, page 396 of 975 Operating Frequency (MHz) 3.6864 4 4.9152 5 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 -0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 -1.36 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 5 0.00 0 7 0.00 0 7 1.73 31250 0 3 0.00 0 4 -1.70 0 4 0.00 38400 0 2 0.00 0 3 0.00 0 3 1.73 Table 22.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency (MHz) 6 6.144 7.3728 8 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 106 -0.44 2 108 0.08 2 130 -0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 -2.34 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 -2.34 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.40 0 7 0.00 38400 0 4 -2.34 0 4 0.00 0 5 0.00 Rev. 0.1, 11/98, page 397 of 975 Operating Frequency (MHz) 9.8304 10 Bit Rate (bits/s) n N Error (%) 110 2 174 150 2 127 300 1 600 1200 Error (%) n N -0.26 2 177 0.00 2 129 0.16 255 0.00 2 64 0.16 1 127 0.00 1 129 0.16 0 255 0.00 1 64 0.16 2400 0 127 0.00 0 129 0.16 4800 0 63 0.00 0 64 0.16 9600 0 31 0.00 0 32 -1.36 19200 0 15 0.00 0 15 1.73 31250 0 9 -1.70 0 9 0.00 38400 0 7 0.00 0 7 1.73 -0.25 Table 22.4 BRR Settings for Various Bit Rates (Synchronous Mode) 2 Bit Rate (bits/s) 110 250 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M 2.5 M 5M n 3 2 1 1 0 0 0 0 0 0 0 0 4 N 70 124 249 124 199 99 49 19 9 4 1 0* n 2 2 1 1 0 0 0 0 0 0 0 0 Operating Frequency (MHz) 8 N 249 124 249 99 199 99 39 19 9 3 1 0* 10 n N n N 3 1 2 1 1 0 0 0 0 0 0 0 124 249 124 199 99 199 79 39 19 7 3 1 1 1 0 0 0 0 0 0 249 124 249 99 49 24 9 4 0 0* Note: As far as possible, the setting should be made so that the error is no more than 1%. Legend: Blank: Cannot be set. --: Can be set, but there will be a degree of error. *: Continuous transfer is not possible. Rev. 0.1, 11/98, page 398 of 975 The BRR setting is found from the following equations. * Asynchronous mode: N= 64x22n-1xB x106-1 * Synchronous mode: N= 8x22n-1xB x106-1 Where B: Bit rate (bits/s) N: BRR setting for baud rate generator (0 N 255) : Operating frequency (MHz) n: Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.) SMR Setting n Clock CKS1 CKS0 0 0 0 1 /4 0 1 2 /16 1 0 3 /64 1 1 The bit rate error in asynchronous mode is found from the following equation: Error (%) = { x 106 - 1 } x 100 (N+1) x B x 64 x 22n-1 Table 22.5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 22.6 and 22.7 show the maximum bit rates with external clock input. Rev. 0.1, 11/98, page 399 of 975 Table 22.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) (MHz) Maximum Bit Rate (bits/s) n N 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 5 156250 0 0 6 187500 0 0 6.144 192000 0 0 7.3728 230400 0 0 8 250000 0 0 9.8304 307200 0 0 10 312500 0 0 Rev. 0.1, 11/98, page 400 of 975 Table 22.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 5 1.2500 78125 6 1.5000 83750 6.144 1.5360 96000 7.3728 1.8432 115200 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 Table 22.7 Maximum Bit Rate with External Clock Input (Synchronous Mode) (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 2 0.3333 333333.3 4 0.6667 666666.7 6 1.0000 1000000.0 8 1.3333 1333333.3 10 1.6667 1666666.7 Rev. 0.1, 11/98, page 401 of 975 22.2.9 Serial Interface Mode Register (SCMR) Bit : 7 6 5 4 3 2 1 0 -- -- -- -- SDIR SINV -- SMIF Initial value : 1 1 1 1 0 0 1 0 R/W : -- -- -- -- R/W R/W -- R/W SCMR is an 8-bit readable/writable register used to select SCI functions. SCMR is initialized to H'F2 by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. Bits 7 to 4: Reserved These bits cannot be modified and are always read as 1. Bit 3: Data Transfer Direction (SDIR) Selects the serial/parallel conversion format. Bit 3 SDIR Description 0 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first 1 TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first (Initial value) Bit 2: Data Invert (SINV) Specifies inversion of the data logic level. The SINV bit does not affect the logic level of the parity bit(s): parity bit inversion requires inversion of the O/( bit in SMR. Bit 2 SINV Description 0 TDR contents are transmitted without modification Receive data is stored in RDR without modification 1 TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form Rev. 0.1, 11/98, page 402 of 975 (Initial value) Bit 1: Reserved This bit cannot be modified and is always read as 1. Bit 0: Serial Communication Interface Mode Select (SMIF) Reserved bit. 1 should not be written in this bit. Bit 0 SMIF Description 0 Normal SCI mode 1 Reserved mode (Initial value) 22.2.10 Module Stop Control Register (MSTPCR) MSTPCRH Bit : 7 6 5 4 3 MSTPCRL 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 Initial value : 1 1 1 1 1 1 1 1 7 6 5 MSTP7 MSTP6 MSTP5 1 1 1 4 3 2 1 MSTP4 MSTP3 MSTP2 MSTP1 1 1 1 1 0 MSTP0 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control. When bit MSTP8 is set to 1, SCI1 operation stops at the end of the bus cycle and a transition is made to module stop mode. For details, see section 4.5, Module Stop Mode. MSTPCR is initialized to H'FFFF by a reset. Bit 0: Module Stop (MSTP8) Specifies the SCI1 module stop mode. MSTPCRH Bit 0 MSTP8 Description 0 SCI1 module stop mode is cleared 1 SCI2 module stop mode is set (Initial value) Rev. 0.1, 11/98, page 403 of 975 22.3 Operation 22.3.1 Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or synchronous mode and the transmission format is made using SMR as shown in table 22.8. The SCI clock is determined by a combination of the C/$ bit in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 22.9. (1) Asynchronous Mode Data length: Choice of 7 or 8 bits Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) Detection of framing, parity, and overrun errors, and breaks, during reception Choice of internal or external clock as SCI clock source -- When internal clock is selected: The SCI operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output -- When external clock is selected: A clock with a frequency of 16 times the bit rate must be input (the built-in baud rate generator is not used) (2) Clock Synchronous Mode Transfer format: Fixed 8-bit data Detection of overrun errors during reception Choice of internal or external clock as SCI clock source * When internal clock is selected: The SCI operates on the baud rate generator clock and a serial clock is output off-chip * When external clock is selected: The built-in baud rate generator is not used, and the SCI operates on the input serial clock Rev. 0.1, 11/98, page 404 of 975 Table 22.8 SMR Settings and Serial Transfer Format Selection SMR Settings Bit 7 Bit 6 Bit 2 Bit 5 Bit 3 SCI Transfer Format C/$ CHR MP PE STOP Mode Data length Multiprocessor bit Parity bit Stop bit length 0 0 0 0 0 Asynchronous mode 8-bit data No No 1 bit 1 1 2 bits 0 Yes 1 1 0 2 bits 0 7-bit data No 1 1 1 0 1 1 0 1 0 1 1 bit 2 bits Yes 1 0 1 bit 1 bit 2 bits Asynchronous mode (multiprocessor format) 8-bit data Yes No 1 bit 2 bits 7-bit data 1 bit 2 bits Clock synchronous mode 8-bit data No Rev. 0.1, 11/98, page 405 of 975 Table 22.9 SMR and SCR Settings and SCI Clock Source Selection SMR SCR Setting Bit 7 Bit 1 Bit 0 C/$ CKE1 CKE0 Mode Clock Source SCK Pin Function 0 0 0 Asynchronous mode Internal SCI does not use SCK pin SCI Transfer Clock 1 1 Outputs clock with same frequency as bit rate 0 External Inputs clock with frequency of 16 times the bit rate Internal Outputs serial clock External Inputs serial clock 1 1 0 0 Clock synchronous mode 1 1 0 1 Rev. 0.1, 11/98, page 406 of 975 22.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and followed by one or two stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-by-character basis. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 22.2 shows the general format for asynchronous serial communication. In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. One serial communication character consists of a start bit (low level), followed by data (in LSBfirst order), a parity bit (high or low level), and finally one or two stop bits (high level). In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in reception. The SCI samples the data on the 8th pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit. Idle state (mark state) 1 Serial data LSB 0 D0 1 MSB D1 D2 D3 D4 D5 Start bit Transmit/receive data 1 bit 7 or 8 bits D6 D7 0/1 Parity bit 1 1 Stop bit(s) 1 bit, 1 or 2 bits or none One unit of transfer data (character or frame) Figure 22.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) Rev. 0.1, 11/98, page 407 of 975 (1) Data Transfer Format Table 22.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected by settings in SMR. Table 22.10 Serial Transfer Formats (Asynchronous Mode) SMR Settings Serial Transfer Format and Frame Length CHR PE MP STOP 1 0 0 0 0 S 8-bit data STOP 0 0 0 1 S 8-bit data STOP STOP 0 1 0 0 S 8-bit data P STOP 0 1 0 1 S 8-bit data P STOP STOP 1 0 0 0 S 7-bit data STOP 1 0 0 1 S 7-bit data STOP STOP 1 1 0 0 S 7-bit data P STOP 1 1 0 1 S 7-bit data P STOP STOP 0 -- 1 0 S 8-bit data MPB STOP 0 -- 1 1 S 8-bit data MPB STOP STOP 1 -- 1 0 S 7-bit data MPB STOP 1 -- 1 1 S 7-bit data MPB STOP STOP [Legend] : Start bit S STOP : Stop bit : Parity bit P MPB : Multiprocessor bit Rev. 0.1, 11/98, page 408 of 975 2 3 4 5 6 7 8 9 10 11 12 (2) Clock Either an internal clock generated by the built-in baud rate generator or an external clock input at the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/$ bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 22.9. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is at the center of each transmit data bit, as shown in figure 22.3. 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 22.3 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode) Rev. 0.1, 11/98, page 409 of 975 (3) Data Transfer Operations (a) SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. When an external clock is used the clock should not be stopped during operation, including initialization, since operation is uncertain. Figure 22.4 shows a sample SCI initialization flowchart. Start initialization [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made. Clear TE and RE bits in SCR to 0 Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] Set data transfer format in SMR and SCMR [2] Set value in BRR [3] Wait No [2] Set the data transfer format in SMR and SCMR. [3] Write a value corresponding to the bit rate to BRR. This is not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the SO1 and SI1 pins to be used. 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [4] <Initialization completed> Figure 22.4 Sample SCI Initialization Flowchart Rev. 0.1, 11/98, page 410 of 975 (b) Serial Data Transmission (Asynchronous Mode) Figure 22.5 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. Initialization [1] Start transmission Read TDRE flag in SSR [1] No [1] SCI initialization: The SO1 pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. TDRE=1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 [4] Break output at the end of serial transmission: To output a break in serial transmission, set PCR for the port corresponding to the SO1 pin to 1, clear PDR to 0, then clear the TE bit in SCR to 0. No All data transmitted? Yes [3] Read TEND flag in SSR No TEND=1 Yes No Break output? [4] Yes Clear PDR to 0 and set PCR to 1 Clear TE bit in SCR to 0 < End > Figure 22.5 Sample Serial Transmission Flowchart Rev. 0.1, 11/98, page 411 of 975 In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. The serial transmit data is sent from the SO1 pin in the following order. [a] Start bit: One 0-bit is output. [b] Transmit data: 8-bit or 7-bit data is output in LSB-first order. [c] Parity bit or multiprocessor bit: One parity bit (even or odd parity), or one multiprocessor bit is output. A format in which neither a parity bit nor a multiprocessor bit is output can also be selected. [d] Stop bit(s): One or two 1-bits (stop bits) are output. [e] Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. Figure 22.6 shows an example of the operation for transmission in asynchronous mode. Rev. 0.1, 11/98, page 412 of 975 1 Data Start bit 0 D0 D1 Parity Stop bit bit D7 0/1 1 Data Start bit 0 D0 D1 Parity bit D7 0/1 Stop bit 1 1 Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and request TDRE flag cleared to 0 generated in TXI interrupt handling routine TXI interrupt request generated TEI interrupt request generated 1 frame Figure 22.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Rev. 0.1, 11/98, page 413 of 975 (c) Serial Data Reception (Asynchronous Mode) Figure 22.7 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. Initialization [1] SCI initialization: The SI1 pin is automatically designated as the receive data input pin. [1] Start reception Read ORER, PER, FER flags in SSR [2] Yes PERFERORER=1 [3] No Error handling [2][3] Receive error handling and break detection: If a receive error occurs, read the ORER, PER, and FER flags in SSR to identify the error. After performing the appropriate error handling, ensure that the PERE, PER, and FER flags are all cleared to 0. Reception cannot be resumed if any of these flags are set to 1. In the case of a framing error, a break can be detected by reading the value of the input port corresponding to the SI1 pin. (Continued on next page) Read RDRF flag in SSR [4] No RDRF=1 [4] SCI status check and receive data read: Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR, and clear the RDRF flag to 0. Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? [5] Yes Clear RE bit in SCR to 0 < End > Figure 22.7 Sample Serial Reception Data Flowchart (1) Rev. 0.1, 11/98, page 414 of 975 [3] Error handling No ORER=1 Yes Overrun error handling No FER=1 Yes Yes Break? No Framing error handling Clear RE bit in SCR to 0 No PER=1 Yes Parity error handling Clear ORER, PER, and FER flags in SSR to 0 < End > Figure 22.7 Sample Serial Reception Data Flowchart (2) Rev. 0.1, 11/98, page 415 of 975 In serial reception, the SCI operates as described below. [1] The SCI monitors the transmission line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. [2] The received data is stored in RSR in LSB-to-MSB order. [3] The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks. [a] Parity check: The SCI checks whether the number of 1 bits in the receive data agrees with the parity (even or odd) set in the O/( bit in SMR. [b] Stop bit check: The SCI checks whether the stop bit is 1. If there are two stop bits, only the first is checked. [c] Status check: The SCI checks whether the RDRF flag is 0, indicating that the receive data can be transferred from RSR to RDR. If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a receive error* is detected in the error check, the operation is as shown in table 22.11. Note: * Subsequent receive operations cannot be performed when a receive error has occurred. Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be cleared to 0. [4] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt (RXI) request is generated. Also, if the RIE bit in SCR is set to 1 when the ORER, PER, or FER flag changes to 1, a receive-error interrupt (ERI) request is generated. Table 22.11 Receive Errors and Conditions for Occurrence Receive Error Abbrev. Occurrence Condition Data Transfer Overrun error ORER When the next data reception is completed while the RDRF flag in SSR is set to 1 Receive data is not transferred from RSR to RDR Framing error FER When the stop bit is 0 Receive data is transferred from RSR to RDR Parity error PER When the received data differs Receive data is transferred from from the parity (even or odd) set in RSR to RDR SMR Rev. 0.1, 11/98, page 416 of 975 Figure 22.8 shows an example of the operation for reception in asynchronous mode. 1 Data Start bit 0 D0 D1 Parity Stop bit bit D7 0/1 1 Data Start bit 0 D0 D1 Parity Stop bit bit D7 0/1 0 1 Idle state (mark state) RDRF FER RXI interrupt RDR data read and RDRF flag request cleared to 0 in generation RXI interrupt handling routine ERI interrupt request generated by framing error 1 frame Figure 22.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) 22.3.3 Multiprocessor Communication Function The multiprocessor communication function performs serial communication using a multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing transmission lines. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. The transmitting station first sends the ID of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips the data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip the data until data with a 1 multiprocessor bit is again received. In this way, data communication is carried out among a number of processors. Figure 22.9 shows an example of inter-processor communication using a multiprocessor format. Rev. 0.1, 11/98, page 417 of 975 (1) Data Transfer Format There are four data transfer formats. When a multiprocessor format is specified, the parity bit specification is invalid. For details, see table 22.10. (2) Clock See the section on asynchronous mode. Transmitting station Serial communication line Receiving station A Receiving station B Receiving station C Receiving station D (ID=01) (ID=02) (ID=03) (ID=04) Serial data H'01 H'AA (MPB=1) ID transmission cycle: receiving station specification (MPB=0) Data transmission cycle: data transmission to receiving station specified by ID [Legend] MPB : Multiprocessor bit Figure 22.9 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) (3) Data Transfer Operations (a) Multiprocessor Serial Data Transmission Figure 22.10 shows a sample flowchart for multiprocessor serial data transmission. The following procedure should be used for multiprocessor serial data transmission. Rev. 0.1, 11/98, page 418 of 975 Initialization [1] Start transmission Read TDRE flag in SSR [2] [1] SCI initialization: The SO2 pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. No TDRE=1 [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Yes Write transmit data to TDR and set MPBT bit in SSR [4] Break output at the end of serial transmission: To output a break in serial transmission, set the port PCR to 1, clear PDR to 0, then clear the TE bit in SCR to 0. Clear TDRE flag to 0 No [3] Transmission end? Yes Read TEND flag in SSR No TEND=1 Yes No Break output? [4] Yes Clear PDR to 0 and set PCR to 1 Clear TE bit in SCR to 0 < End > Figure 22.10 Sample Multiprocessor Serial Transmission Flowchart Rev. 0.1, 11/98, page 419 of 975 In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated. The serial transmit data is sent from the SO2 pin in the following order. [a] Start bit: One 0-bit is output. [b] Transmit data: 8-bit or 7-bit data is output in LSB-first order. [c] Multiprocessor bit One multiprocessor bit (MPBT value) is output. [d] Stop bit(s): One or two 1-bits (stop bits) are output. [e] Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this time, a transmit-end interrupt (TEI) request is generated. Rev. 0.1, 11/98, page 420 of 975 Figure 22.11 shows an example of SCI operation for transmission using a multiprocessor format. 1 0 Multiprocessor Stop bit bit Data Start bit D0 D1 D7 0/1 1 0 Multiprocessor Stop bit bit 1 Data Start bit D0 D1 D7 0/1 1 Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and TDRE flag cleared to 0 request in TXI interrupt handling general routine TXI interrupt request generated TEI interrupt request generated 1 frame Figure 22.11 Example of SCI Operation in Transmission (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) (b) Multiprocessor Serial Data Reception Figure 22.12 shows a sample flowchart for multiprocessor serial reception. The following procedure should be used for multiprocessor serial data reception. Rev. 0.1, 11/98, page 421 of 975 Initialization [1] Start reception Set MPIE bit in SCR to 1 [2] Read ORER and FER flags in SSR Yes FERORER=1 No Read RDRF flag in SSR [3] [1] SCI initialization: The SI1 pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station's ID, clear the RDRF flag to 0. No RDRF=1 [4] SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. Yes Read receive data in RDR No This station's ID? Yes Read ORER and FER flags in SSR Yes [5] Receive error handling and break detectioon: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error handling, ensure that the ORER and FER flags are both cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the SI1 in value. FERORER=1 No Read RDRF flag in SSR [4] No RDRF=1 Yes Read receive data in RDR No All data received? [5] Error handling Yes Clear RE bit in SCR to 0 (Continued on next page) < End > Figure 22.12 Sample Multiprocessor Serial Reception Flowchart (1) Rev. 0.1, 11/98, page 422 of 975 [5] Error handling No ORER=1 Yes Overrun error handling No FER=1 Yes Yes Break? No Framing error handling Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 < End > Figure 22.12 Sample Multiprocessor Serial Reception Flowchart (2) Figure 22.13 shows an example of SCI operation for multiprocessor format reception. Rev. 0.1, 11/98, page 423 of 975 1 Data (ID1) Start bit 0 Stop MPB bit D0 D1 D7 1 1 Data (Data 1) Start bit 0 Stop MPB bit D0 D1 D7 0 1 1 Idle state (mark state) MPIE RDRF RDR value ID1 MPIE=0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine RXI interrupt request is not generated, and RDR retains its state If not this station's ID, MPIE bit is set to 1 again (a) Data does not match station's ID 1 Data (ID2) Start bit 0 Stop MPB bit D0 D1 D7 1 1 Data (Data 2) Start bit 0 Stop MPB bit D0 D1 D7 0 1 1 Idle state (mark state) MPIE RDRF RDR value ID2 ID1 MPIE=0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine Matches this station's ID, so reception continues, and data is received in RXI interrupt handling routine (b) Data matches station's ID Figure 22.13 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev. 0.1, 11/98, page 424 of 975 Data2 MPIE bit set to 1 again 22.3.4 Operation in Synchronous Mode In synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 22.14 shows the general format for synchronous serial communication. One unit of transfer data (character or frame) * * Synchronous clock LSB Serial data Bit 0 MSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Don't care Bit 7 Don't care Note: * High except in continuous transfer Figure 22.14 Data Format in Synchronous Communication In synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial clock. In synchronous serial communication, one character consists of data output starting with the LSB and ending with the MSB. After the MSB is output, the transmission line holds the MSB state. In synchronous mode, the SCI receives data in synchronization with the rising edge of the serial clock. (1) Data Transfer Format A fixed 8-bit data format is used. No parity or multiprocessor bits are added. (2) Clock Either an internal clock generated by the built-in baud rate generator or an external serial clock input at the SCK pin can be selected, according to the setting of the C/ $ bit in SMR and the CKE1 and CKE0 bits in SCR. For details on SCI clock source selection, see table 22.9. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin. Rev. 0.1, 11/98, page 425 of 975 Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. When only receive operations are performed, however, the serial clock is output until an overrun error occurs or the RE bit is cleared to 0. To perform receive operations in units of one character, select an external clock as the clock source. (3) Data Transfer Operations (a) SCI Initialization (Synchronous Mode) Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the settings of the RDRF, PER, FER, and ORER flags, or the contents of RDR. Figure 22.15 shows a sample SCI initialization flowchart. [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. Start initialization Clear TE and RE bits in SCR to 0 [2] Set the data transfer format in SMR and SCMR. Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] Set data transfer format in SMR and SCMR [2] Set value in BRR [3] [3] Write a value corresponding to the bit rate to BRR. This is not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the SO1 and SI1 pins to be used. Wait No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [4] <Transfer start> Figure 22.15 Sample SCI Initialization Flowchart Rev. 0.1, 11/98, page 426 of 975 (b) Serial Data Transmission (Synchronous Mode) Figure 22.16 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. [1] Initialization Start transmission Read TDRE flag in SSR [2] No [1] SCI initialization: The SO2 pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. TDRE=1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? [3] Yes Read TEND flag in SSR No TEND=1 Yes Clear TE bit in SCR to 0 < End > Figure 22.16 Sample Serial Transmission Flowchart Rev. 0.1, 11/98, page 427 of 975 In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated. When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an external clock has been specified, data is output synchronized with the input clock. The serial transmit data is sent from the SO1 pin starting with the LSB (bit 0) and ending with the MSB (bit 7). [3] The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the MSB (bit 7) is sent, and the SO1 pin maintains its state. If the TEIE bit in SCR is set to 1 at this time, a transmit-end interrupt (TEI) request is generated. [4] After completion of serial transmission, the SCK pin is held in a constant state. Figure 22.17 shows an example of SCI operation in transmission. Transfer direction Synchronous clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt handling routine TXI interrupt request generated 1 frame Figure 22.17 Example of SCI Operation in Transmission Rev. 0.1, 11/98, page 428 of 975 TEI interrupt request generated (c) Serial Data Reception (Synchronous Mode) Figure 22.18 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. When changing the operating mode from asynchronous to synchronous, be sure to check that the ORER, PER, and FER flags are all cleared to 0. The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor receive operations will be possible. Rev. 0.1, 11/98, page 429 of 975 [1] Initialization [1] SCI initialization: The SI1 pin is automatically designated as the receive data input pin. Start reception [2] Read ORER flag in SSR Yes [3] ORER=1 No [2][3] Receive error handling: IF a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error handling, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. Error handling (Continued below) Read RDRF flag in SSR [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by and RXI interrupt. [4] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0 No RDRF=1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? [5] Yes Clear RE bit in SCR to 0 < End > [3] Error handling Overrun error handling Clear ORER flag in SSR to 0 < End > Figure 22.18 Sample Serial Reception Flowchart Rev. 0.1, 11/98, page 430 of 975 In serial reception, the SCI operates as described below. [1] The SCI performs internal initialization in synchronization with serial clock input or output. [2] The received data is stored in RSR in LSB-to-MSB order. After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from RSR to RDR. If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a receive error is detected in the error check, the operation is as shown in table 22.11. Neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check. [3] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt (RXI) request is generated. Also, if the RIE bit in SCR is set to 1 when the ORER flag changes to 1, a receive-error interrupt (ERI) request is generated. Figure 22.19 shows an example of SCI operation in reception. Synchronous clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine RXI interrupt request generated ERI interrupt request generated by overrun error 1 frame Figure 22.19 Example of SCI Operation in Reception (d) Simultaneous Serial Data Transmission and Reception (Synchronous Mode) Figure 22.20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. Rev. 0.1, 11/98, page 431 of 975 Initialization [1] SCI initialization: The SO2 pin is designated as the transmit data output pin, and the SI1 pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. [1] Start transfer Read TDRE flag in SSR [2] No [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. TDRE=1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 Read ORER flag in SSR ORER=1 No Read RDRF flag in SSR Yes [3] Error handling [4] No RDR=1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? [5] Yes Clear TE and RE bits in SCR to 0 < End > [3] Receive error handling: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error handling, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial transmission/reception continuation procedure: To continue serial transmission/reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR and clear the TDRE flag to 0. Note: When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously. Figure 22.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations Rev. 0.1, 11/98, page 432 of 975 22.4 SCI Interrupts The SCI has four interrupt sources:the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 22.13 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in SCR. Each kind of interrupt request is sent to the interrupt controller independently. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. Table 22.13 SCI Interrupt Sources Channel Interrupt Source Description Priority* 1 ERI Interrupt by receive error (ORER, FER, or PER) High RXI Interrupt by receive data register full (RDRF) TXI Interrupt by transmit data register empty (TDRE) TEI Interrupt by transmit end (TEND) Low The TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt will have priority for acceptance, and the TDRE flag and TEND flag may be cleared. Note that the TEI interrupt will not be accepted in this case. 22.5 Usage Notes The following points should be noted when using the SCI. (1) Relation between Writes to TDR and the TDRE Flag The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1. Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1 before writing transmit data to TDR. Rev. 0.1, 11/98, page 433 of 975 (2) Operation when Multiple Receive Errors Occur Simultaneously If a number of receive errors occur at the same time, the state of the status flags in SSR is as shown in table 22.14. If there is an overrun error, data is not transferred from RSR to RDR, and the receive data is lost. Table 22.14 State of SSR Status Flags and Transfer of Receive Data SSR Status Flags RDRF ORER FER PER Receive Data Transfer RSR RDR Receive Errors 1 1 0 0 x Overrun error 0 0 1 0 Framing error 0 0 0 1 Parity error 1 1 1 0 x Overrun error + framing error 1 1 0 1 x Overrun error + parity error 0 0 1 1 Framing error + parity error 1 1 1 1 x Overrun error + framing error + parity error Notes: : Receive data is transferred from RSR to RDR. x: Receive data is not transferred from RSR to RDR. (3) Break Detection and Processing When a framing error (FER) is detected, a break can be detected by reading the SI1 pin value directly. In a break, the input from the SI1 pin becomes all 0s, and so the FER flag is set, and the parity error flag (PER) may also be set. Note that, since the SCI continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. (4) Sending a Break The SO1 pin has a dual function as an I/O port whose direction (input or output) is determined by PDR and PCR. This feature can be used to send a break. Between serial transmission initialization and setting of the TE bit to 1, the mark state is replaced by the value of PDR (the pin does not function as the SO1 pin until the TE bit is set to 1). Consequently, PCR and PDR for the port corresponding to the SO1 pin should first be set to 1. To send a break during serial transmission, first clear PDR to 0, then clear the TE bit to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the SO1 pin becomes an I/O port, and 0 is output from the SO1 pin. (5) Receive Error Flags and Transmit Operations (Synchronous Mode Only) Rev. 0.1, 11/98, page 434 of 975 Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. (6) Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the base clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the base clock. This is illustrated in figure 22.23. 16 clocks 8 clocks 0 7 15 0 7 15 0 Internal base clock Receive data Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 22.21 Receive Data Sampling Timing in Asynchronous Mode Thus the receive margin in asynchronous mode is given by equation (1) below. M = (0.5- D - 0.5 1 ) - (L-0.5) F - (1+F) x 100% 2N N .....(1) Where M: Receive margin (%) N: Ratio of bit rate to clock (N = 16) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 9 to 12) F: Absolute value of clock rate deviation Assuming values of F = 0 and D = 0.5 in equation (1), a receive margin of 46.875% is given by equation (2) below. When D = 0.5 and F = 0, Rev. 0.1, 11/98, page 435 of 975 M =(0.5- 1 2 x 16 ) x 100% =46.875% .....(2) However, this is only a theoretical value, and a margin of 20% to 30% should be allowed in system design. Rev. 0.1, 11/98, page 436 of 975 Section 23 Serial Communication Interface 2 (SCI2) 23.1 Overview The serial communication interface 2 (SCI2) that has a 32-byte data buffer carries out clocked synchronous serial transmission of 32 bytes by a single operation. 23.1.1 Features SCI2 features are listed below. * A 32-byte data transfer can be automatically carried out * Choice of 7 internal clocks (/256, /64, /32, /16, /8, /4, and /2) and an external clock as serial clock source * Interrupt occurs when transmission has been completed or an error has occurred * Data transfer at intervals of 1 byte can be set Data transfer can be carried out at intervals of 1 byte. The interval can be selected from a multiple of internal clock cycle by 56, 24, or 8 times * Start of data transfer can be controlled by input of chip select * Strobe pulse is output for each 1-byte transfer Rev. 0.1, 11/98, page 437 of 975 23.1.2 Block Diagram Figure 23.1 shows a block diagram of the SCI2. Internal clock /256, /64, /32, /16, /8, /4, /2 SCK2 SCK2 STAR Transmit/ receive control circuit CS EDAR SCR2 Internal data bus STRB SCSR2 Shift register SO2 Data buffer (32 bytes) Interrupt generation circuit SI2 Interrupt request [Legend] STAR : Starting address register SCK2 : SCI2 clock input/output pin ESAR : Ending address register STRB : SCI2 strobe signal output pin SCR2 : Serial control register 2 CS : SCI2 chip select signal input pin SCSR2: Serial control status register SO2 : SCI2 transmit data output pin SI2 : SCI2 receive data input pin Figure 23.1 Block Diagram of SCI2 Rev. 0.1, 11/98, page 438 of 975 23.1.3 Pin Configuration Table 23.1 shows pin configuration of the SCI2. Table 23.1 Pin Configuration Name Abbrev. I/O Function SCI2 Clock SCK2 I/O SCI2 clock input/output pin SCI2 Data input SI2 Input SCI2 receive data input pin SCI2 Data output SO2 Output SCI2 transmit data output pin SCI2 Strobe STRB Output SCI2 strobe signal output pin SCI2 Chip select &6 Input SCI2 chip select signal input pin 23.1.4 Register Configuration Table 23.2 shows register configuration of the SCI2. Table 23.2 Register Configuration Name Abbrev. R/W Initial Value Address* Starting address register STAR R/W H'E0 H'D0E0 Ending address register EDAR R/W H'E0 H'D0E1 Serial control register 2 SCR2 R/W H'20 H'D0E2 Serial control status register 2 SCSR2 R/W H'60 H'D0E3 Serial data buffer (32 bytes) R/W Undefined H'D0C0 to H'D0DF Note: * Lower 16 bits of the address.. Rev. 0.1, 11/98, page 439 of 975 23.2 Register Descriptions 23.2.1 Starting Address Register (STAR) Bit : Initial value : R/W : 7 6 5 -- -- -- 4 STA4 3 STA3 2 STA2 1 STA1 0 STA0 1 -- 1 -- 1 -- 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W The STAR is a readable/writable register that specifies the transfer starting address within the address space (H'FFD0C0 to H'FFD0DF) to which a 32-byte data buffer is assigned. The 5 loworder bits of the STAR correspond to the 5 low-order bits of the address of 32-byte buffer. The range for executing continuous data transfer on STAR and EDAR is specified. When the value of STAR is equal to that of EDAR, only one-byte transfer is carried out. Since the 7 to 5 bits of the STAR are reserved, writes are disabled. When each bit is read, 1 is read at all times. The STAR is initialized to H'E0 by a reset. 23.2.2 Ending Address Register (EDAR) Bit : 7 -- 6 -- 5 -- 4 EDA4 3 EDA3 2 EDA2 1 EDA1 0 EDA0 Initial value : R/W : 1 -- 1 -- 1 -- 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W The EDAR is a readable/writable register that specifies the transfer ending address within the address space (H'FFD0C0 to H'FFD0DF) to which 32-byte data buffer is assigned. The 5 loworder bits of EDAR correspond to the 5 low-order bits of the address of 32-byte buffer. The range for executing continuous data transfer is specified by the EDAR and the STAR. If the value of the STAR is equal to that of the EDAR, only one-byte transfer is carried out. Since the 7 to 5 bits of the EDAR are reserved, writes are disabled. When each bit is read, 1 is read at all times. The EDAR is initialized to H'E0 by a reset. Rev. 0.1, 11/98, page 440 of 975 23.2.3 Serial Control Register 2 (SCR2) Bit : 7 TEIE 6 ABTIE 5 -- 4 GAP1 3 GAP0 2 CKS2 1 CKS1 0 CKS0 Initial value : 0 R/W 0 R/W 1 -- 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W R/W : The SCR 2 is a readable/writable register that enables or disables generation of SCI2 interrupt and selects an data transfer interval and transfer clock when an internal clock is used. The SCR2 is initialized to H'20 by a reset. Bit 7: Transmit End Interrupt Enable (TEIE) Enables or disables the occurrence of transmit-end interrupt when data transfer has been completed and TEI of the SCR2 has been set to 1. Bit 7 TEIE Description 0 Transmit-end interrupt disabled 1 Transmit-end interrupt enabled (Initial value) Bit 6: Transmit Cutoff Interrupt (ABTIE) Enables or disables the occurrence of transmit-cutoff interrupt when the &6 pin has entered a high level during transmission and ABT of the SCRS2 has been set to 1. Bit 6 ABTIE Description 0 Transmit-cutoff interrupt disabled 1 Transmit-cutoff interrupt enabled (Initial value) Bit 5: Reserved Reserve bit. When read, 1 is read at all times. Writes are disabled. Rev. 0.1, 11/98, page 441 of 975 Bits 4 and 3: Transmit Data Interval Select 1 and 0 (GAP1, GAP0) When an internal clock is used, data can be transmitted at 1-byte intervals. During that time, the SCK2 pin retains the high level. When data is transmitted without intervals, the STRB signal retains the low level. Bit 4 Bit 3 GAP1 GAP0 Description 0 0 Data transmission without intervals 0 1 Data intervals: 8 clocks 1 0 Data intervals: 24 clocks 1 1 Data intervals: 56 clocks (Initial value) Bits 2 to 0: Transfer Clock Select 2 to 0 (CKS2 to CKS0) Selects transfer clock. Bit 2 Bit 1 Bit 0 CKS2 CKS1 CKS0 0 0 0 0 0 0 Transfer clock cycle SCK2 pin Clock source Prescaler division ratio = 10 MHz = 5 MHz SCK2 output /256 (Initial value) 25.6 s 51.2 s 1 /64 6.4 s 12.8 s 1 0 /32 3.2 s 6.4 s 0 1 1 /16 1.6 s 3.2 s 1 0 0 /8 0.8 s 1.6 s 1 0 1 /4 0.4 s 0.8 s 1 1 0 /2 0.4 s 1 1 1 SCK2 input Rev. 0.1, 11/98, page 442 of 975 Prescaler S External clock 23.2.4 Serial Control Status Register 2 (SCSR2) Bit : Initial value : R/W : 7 TEI 6 -- 5 -- 4 SOL 3 ORER 2 WT 1 ABT 0 STF 0 R/(W)* 1 -- 1 -- 0 R/W 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/W Note: * Only 0 can be written to clear the flag. The SCSR2 is an 8-bit register that indicates the SCI2's state of operation and error. The SCSR2 is initialized to H'60 by a reset. Bit 7: Transmit End Interrupt Request Flag (TEI) Indicates that data transmission or reception has been completed. Bit 7 TEI Description 0 [Clearing condition] When 0 is written after reading 1 1 [Setting condition] When transmission or reception has been completed (Initial value) Bits 6 and 5: Reserved These bits are reserved. When each bit is read, 1 is read at all times. Writes are disabled. Rev. 0.1, 11/98, page 443 of 975 Bit 4: Extension Data Bit (SOL) The SOL sets the output level of the SO2 pin. When read, the output level of the SO2 pin is read. Output of the SO2 pin after completion of transmission retains the value of final bit of transfer data, but the output level of the SO2 pin can be changed by operating this bit before or after transmission. However, setting of the SOL bit becomes invalid when the next transmission is started. Therefore, if the output level of the SO2 pin is changed after completion of transmission, write operation for SOL must be performed every time when transmission is terminated. Since writing to this register during data transfer may cause malfunction, write operation must not be performed during transmission. Bit 4 SOL Description 0 Read The SO2 pin output is at a low level Write The SO2 pin output is changed to a low level Read The SO2 pin output is at a high level Write The SO2 pin output is changed to a high level 1 (Initial value) Bit 3: Overrun Error Flag (ORER) The ORER indicates an occurrence of overrun error while an external clock is used. When excessive pulses are overlapped with the normal transfer clock caused by external noise, etc. during transmission, this bit is set to 1. At this time data transfer cannot be assured. When a clock is input after completion of transmission, it is also found to be in the state of overrun and this bit is set to 1. However, overrun is not detected when the &6 pin is at a high level. Bit 3 ORER Description 0 [Clearing condition] When 0 is written after reading 1 1 [Setting condition] When excessive pulses are overlapped with a normal transfer clock while an external clock is used, or when a clock is input after completion of transmission Rev. 0.1, 11/98, page 444 of 975 (Initial value) Bit 2: Wait Flag (WT) The WT indicates that read/ or write to serial data buffer (32 bytes) has been executed during transmission and in the &6 input standby mode. The instruction at that time is ignored and this bit is set to 1. Bit 2 WT Description 0 [Clearing condition] When 0 is written after reading 1 1 [Setting condition] When an instruction to read/write to serial data buffer (32 bits) is directed during transmission and in the &6 input standby mode (Initial value) Bit 1: Abort Flag (ABT) The ABT indicates that the &6 pin has entered a high level during transmission. When a high level of the &6 pin is detected during transfer, the transfer is immediately cut off, and this bit is set to 1, and then the SCK2 and SO2 pins go into the high impedance state. At this time values of internal registers other than SCSR2 and serial data buffer (32 bytes) are retained. Transfer cannot be carried out while this bit is set to 0. Resume transfer after clearing to 0. Bit 1 ABT Description 0 [Clearing condition] When 0 is written after reading 1 1 [Setting condition] During transfer and when &6 pin has entered a high level (Initial value) Rev. 0.1, 11/98, page 445 of 975 Bit 0: Start Flag (STF) The STF controls the start of transfer operations. When this bit is set to 1 and PMR30 of PMR3 is 0, transfer operation of the SCI2 is started. When PMR30 of PMR3 is 1, the low level of the &6 pin is detected and transfer is started. This bit retains 1 during transfer and in the &6 input standby mode, and it is cleared to 0 after completion of transfer and when transfer is cut off by the &6 pin. Therefore, this bit can be used as a busy flag. When this bit is cleared to 0 during transfer, the transfer is cut off and the SCI2 is initialized. At this time the contents of internal registers other than the SCR2 and the serial data buffer (32 bytes) are retained. Bit 0 STF Description 0 Read Transfer operations stops Write Transfer operation discontinues and the SCI2 is initialized Read During transfer operation or in Write Transfer operation starts 1 23.2.5 (Initial value) &6 input standby mode Module Stop Control Register (MSTPCR) MSTPCRH Bit : 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control. When the MSTPCR is set to 1, the SCI2 stops at the end of bus cycle and a transition is made to the module stop mode. For details, see section 4.5 Module Stop Mode. The MSTPCR is initialized to H'FFFF by a reset. Bit 7: Module Stop (MSTP7) Specifies the SCI2 module stop mode. MSTPCRL Bit 7 MSTP7 Description 0 SCI2 module stop mode is cleared 1 SCI2 module stop mode is set Rev. 0.1, 11/98, page 446 of 975 (Initial value) 23.3 Operation The SCI2, comprising a 32-byte serial data buffer, can continuously transmit a maximum of 32byte data by a single operation, synchronized with clock pulse. Installation of a register enables to select transmit, receive, or simultaneous transmit/receive. When transmit is set, the value of serial data buffer is retained even after completion of transmission. An internal or external clock can be selected as transfer clock. When an internal clock is selected, data can be transmitted at 1-byte intervals. The strobe signal can also be output from the STRB pin. When an external clock is selected, malfunction due to clock can be detected by the overrun flag. The start of transfer and its forced cutoff can be controlled by &6 input. Forced cutoff can be detected by the abort flag. 23.3.1 Clock Selection of a transfer clock can be made from seven internal clocks and an external clock. When an internal clock is selected, the SCK2 pin becomes a clock output pin. 23.3.2 Data Transfer Format Figures 23.2 and 23.3 show transfer format of the SCI2. LSB-first transfer that allows to transmit/receive from the lowest-order bit of data is performed. Transmit data is output from the fall of the transfer clock to its next fall. Receive data is collected at the rise of the transfer clock. When an internal clock is selected as a transfer clock, data can be transferred at intervals of 1 byte. The SCK2 output is retained at a high level between transfer data. The strobe signal can be output from the STRB pin. Selection of interval of transfer data is set at GAP1 or GAP0. Rev. 0.1, 11/98, page 447 of 975 Figure 23.2 Transfer Format (Transfer Data without Intervals) Rev. 0.1, 11/98, page 448 of 975 STRB CS SO2/SI2 SCK2 Bit 1 Start of transfer Bit 0 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 End of transfer Bit 7 Figure 23.3 Transfer Format (Transfer Data with Intervals) Rev. 0.1, 11/98, page 449 of 975 STRB CS SO2/SI2 SCK2 Start of transfer Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 8, 24, and 56 clocks Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 End of transfer 23.3.3 Data Transfer Operations (1) SCI2 Initialization To carry out data transfer, first initialize the SCI2 using software. Initialization is performed as described below: (1) Use PMR2, PMR3, STAR, EDAR and SCR2 to set the pin and transmission mode while STF of SCSR2 is set to 0. (2) The SCI2 pin is also used as a port. Switching of a port is performed on PMR3. The SO2 pin allows to select CMOS output or NMOS open drain output on PMR2. Transfer clock and transfer data intervals can be set on SCR2. (3) The starting and ending addresses in the transfer data area are set on STAR and EDAR. If the value of the ending address is smaller than that of the starting address, transfer data at H'FFD0DF and then return to H'FFD0C0 so that transfer to the ending address can be carried out as shows in figure 23.4. If the value of the starting address is equal to that of the ending address is equal, perform one-byte transfer. H' FFD0C0 End Ending address Start Starting address H' FFD0DF Figure 23.4 If The Value of The Ending Address is Smaller Than That of The Starting Address Rev. 0.1, 11/98, page 450 of 975 (2) Transmit Operations Transmit operations are performed as described below: (1) Set PMR26 and PMR27 of PMR2 to 1 and set them to the SO2 and SCK2 pins, respectively. Set the SO2 pin to the open drain output using PMR20 of PMR2 and set them to the &6 and STRB pins, respectively, using PMR30 and PMR31 of PMR3, as necessary. (2) Set the transfer clock and transfer data intervals (only when an internal clock is in operation) by setting SCR2. (3) Write transmit data to serial data buffer. In transmit operations, the contents of the data buffer will be retained even after the end of transmission. When the same data is transmitted again, it is not necessary to write data. (4) Set STAR to the 5 low-order bits at the transmission starting address and EDAR to the 5 low-order bits at the transmission ending address. (5) Set STF to 1. When PMR30 of PMR3 is set to 0, transmission is started by setting STF. While PMR30 of PMR3 is set to 1, transmission is started when low level of the &6 pin is detected. (6) After completion of transmission, TEI of SCSR2 is set to 1. STF is cleared to 0. When an internal clock is selected, synchronous clock is output from the SCK2 pin at the time of starting transmission. When transmission has been completed, synchronous clock is not output until the next STF is set. During that time, the SO2 pin continues to output the value of final bit of the immediately preceding data. When an external clock is selected, data is transmitted, synchronized with the clock input from the SCK2 pin. If the synchronous clock is continuously input after completion of transmission, no transmission is performed as the overrun state has been found and then ORER of the SCSR2 is set to 1. The SO2 pin continues to retain the value of final bit of the preceding data. However, if the &6 of PMR3 is set to 1, overrun is not detected when the &6 pin is at a high level. The output value of the SO2 pin while transmission is being stopped can be changed by SOL of SCSR2. Data buffer cannot be read or written from CPU during transmission or in the &6 standby mode. When a Read instruction has been executed, H'FF is read. Even if a Write instruction is executed, buffer does not change. When a Read/Write instruction has been executed during transmission or in the &6 input standby mode, WT of the SCRS2 is set. While PMR30 of PMR3 is set to 0, transmission is immediately cut off when a high level of the &6 pin has been detected during transmission, and ABT is set to 1, and then STF is cleared to 0. The SCK2 and SO2 pins enter the high impedance state. Therefore, note that transmission may not be carried out while ABT is set to 1, and thus transmission must be resumed after clearing to 0. Rev. 0.1, 11/98, page 451 of 975 (3) Receive Operations Receive operations are performed as described below: (1) Set PMR25 and PMR27 of PMR2 to 1 and set them to the SI2 and SCK2 pins, respectively. Set them to the &6 pin, using PMR30 of PMR3 as necessary. (2) Set the transfer clock and transfer data intervals (only when an internal clock is in operation) by setting SCR2. (3) Set STAR to 5 low-order bits at the receive starting address and EDAR to 5 low-order bits at the receive ending address. This enables to determine the area in the serial data buffer where receive data is stored. (4) Set STF to 1. When PMR30 of PMR3 is set to 0, reception is started by setting STF. While PMR30 of PMR3 is set to 1, reception is started when low level of the &6 pin is detected. (5) After completion of reception, TEI of SCSR2 is set to 1. STF is cleared to 0. (6) Read the receive data stored from the serial data buffer. When an internal clock is selected, synchronous clock is output from the SCK2 pin at the time of starting reception. When reception has been completed, synchronous clock is not output until the next STF is set. When an external clock is selected, data is received, synchronized with the clock input from the SCK2 pin. If the synchronous clock is continuously input after completion of reception, no reception is performed as the overrun state has been found and then ORER of the SCSR2 is set to 1. However, if the &6 of PMR3 is set to 1, overrun is not detected when the &6 pin is at a high level. Data buffer cannot be read or written from CPU during reception or in the &6 standby mode. When a Read instruction has been executed, H'FF is read. Even if a Write instruction is executed, buffer does not change. When a Read/Write instruction has been executed during reception or in the &6 input standby mode, WT of the SCRS2 is set. While &6 of PMR3 is set to 1, transmission is immediately cut off when a high level of the &6 pin has been detected during transmission, and ABT is set to 1, and then STF is cleared to 0. The SCK2 and SO2 pins enter the high impedance state. Therefore, note that transmission may not be carried out while ABT is set to 1, and thus transmission must be resumed after clearing to 0. Rev. 0.1, 11/98, page 452 of 975 (4) Simultaneous Transmit/Receive Operations Simultaneous transmit/receive operations are performed as described below: (1) Set PMR25, PMR26 and PMR27 of PMR2 to 1 and set them to the SI2, SO2 and SCK2 pins, respectively. Set the SO2 pin to open drain output, using PMR20 of PMR2, and set them to the &6 and STRB pins, respectively, using PMR30 and PMR31, as necessary. (2) Set the transfer clock and transfer data intervals (only when an internal clock is in operation) by setting SCR2. (3) Write transmit data to serial data buffer. In the simultaneous transmit/receive operations, the receive data is stored in the same address alternately with the transmit data. (4) Set STAR to 5 low-order bits at the transmission starting address and EDAR to 5 loworder bits at the transmission ending address. (5) Set STF to 1. When PMR30 of PMR3 is set to 0, transmission is started by setting STF. While PMR30 of PMR3 is set to 1, transmission is started when low level of the &6 pin is detected. (6) After completion of transmission, TEI of SCSR2 is set to 1. STF is cleared to 0. (7) Read the receive data stored from the serial data buffer. When an internal clock is selected, synchronous clock is output from the SCK2 pin at the time of starting transmission. When transmission has been completed, synchronous clock is not output until the next STF is set. During that time, the SO2 pin continues to output the value of final bit of the preceding data. When an external clock is selected, data is transmitted, synchronized with the clock input from the SCK2 pin. If the synchronous clock is continuously input after completion of transmission, no transmission is performed as the overrun state has been found and then ORER of the SCSR2 is set to 1. The SO2 pin continues to retain the value of final bit of the preceding data. However, if the CS of PMR3 is set to 1, overrun is not detected when the &6 pin is at a high level. The output value of the SO2 pin while transmission is being stopped can be changed by SOL of SCSR2. Data buffer cannot be read or written from CPU during transmission or in the &6 standby mode. When a Read instruction has been executed, H'FF is read. Even if a Write instruction is executed, buffer does not change. When a Read/Write instruction has been executed during transmission or in the &6 input standby mode, WT of the SCRS2 is set. While the CS of PMR3 is set to 1, transmission is immediately cut off when a high level of the &6 pin has been detected during transmission, and ABT is set to 1, and then STF is cleared to 0. The SCK2 and SO2 pins enter the high impedance state. Therefore, note that transmission may not be carried out while ABT is set to 1, and thus transmission must be resumed after clearing to 0. Rev. 0.1, 11/98, page 453 of 975 23.4 Interrupt Sources An interrupt source of the SCI2 is transmission cutoff by completion of transmission and the &6 pin, to which different vector addresses are assigned. On completion of data transfer, TEI of SCSR2 is set to 1, and transfer-end interrupt request is generated. This interrupt can specify enable/disable by setting TEIE of SCR2. While PMR30 of PMR3 is set to 1, transfer is cut off when the &6 pin enters a high level during data transfer, and ABT of SCSR2 is set to 1 and then transfer cutoff interrupt request is generated. This interrupt can specify enable/disable by setting ABTIE of SCR2. In the case of transfer cutoff by the &6 pin, overrun error, and read/write to serial data buffer during transfer and in the &6 standby mode, ABT, ORER, and WT of the SCSR2 is set to 1, respectively. These bits allow to determine error factors. Rev. 0.1, 11/98, page 454 of 975 Section 24 I2C Bus Interface (IIC) 24.1 Overview The I2C bus interface conforms to and provides a subset of the Philips I2C bus (inter-IC bus) interface functions. The register configuration that controls the I2C bus differs partly from the Philips configuration, however. Each I2C bus interface channel uses only one data line (SDA) and one clock line (SCL) to transfer data, saving board and connector space. 24.1.1 Features * Selection of addressing format or non-addressing format 2 I C bus format: addressing format with acknowledge bit, for master/slave operation Serial format: non-addressing format without acknowledge bit, for master operation only 2 2 * Conforms to Philips I C bus interface (I C bus format) 2 * Two ways of setting slave address (I C bus format) 2 * Start and stop conditions generated automatically in master mode (I C bus format) 2 * Selection of acknowledge output levels when receiving (I C bus format) 2 * Automatic loading of acknowledge bit when transmitting (I C bus format) 2 * Wait function in master mode (I C bus format) A wait can be inserted by driving the SCL pin low after data transfer, excluding acknowledgement. The wait can be cleared by clearing the interrupt flag. 2 * Wait function in slave mode (I C bus format) A wait request can be generated by driving the SCL pin low after data transfer, excluding acknowledgement. The wait request is cleared when the next transfer becomes possible. * Three interrupt sources 2 Data transfer end (including transmission mode transition with I C bus format and address reception after loss of master arbitration) Address match: when any slave address matches or the general call address is received in slave receive mode (I2C bus format) Stop condition detection * Selection of 16 internal clocks (in master mode) * Direct bus drive (with SCL and SDA pins) Two pins-P24/SCL and P23/SDA- (normally CMOS pins) function as NMOS-only outputs when the bus drive function is selected. Rev. 0.1, 11/98, page 455 of 975 24.1.2 Block Diagram Figure 24.1 shows a block diagram of the I2C bus interface. Figure 24.2 shows an example of I/O pin connections to external circuits. I/O pins are driven only by NMOS and apparently function as NMOS open-drain outputs. However, applicable voltages to input pins depend on the power (Vcc) voltage of this LSI. PS ICCR Clock control SCL Noise canceller ICMR Bus state decision circuit SDA ICSR Arbitration decision circuit ICDRT Output data control circuit ICDRS Internal data bus ICDRR Noise canceler Address comparator SAR, SARX [Legend] ICCR ICMR ICSR ICDR SAR SARX PS Interrupt generator : I2C control register : I2C mode register : I2C status register : I2C data register : Slave address register : Slave address register X : Prescaler 2 Figure 24.1 Block Diagram of I C Bus Interface Rev. 0.1, 11/98, page 456 of 975 Interrupt request VCC VCC SCLin SCL SCL SDA SDA SCLout SDAin SCLin This chip SCL SDA (Master) SCL SDA SDAout SCLin SCLout SCLout SDAin SDAin SDAout SDAout (Slave 1) (Slave 2) 2 Figure 24.2 I C Bus Interface Connections (Example: This Chip as Master) 24.1.3 Pin Configuration 2 Table 24.1 summarizes the input/output pins used by the I C bus interface. 2 Table 24.1 I C Bus Interface Pins Name Abbrev. I/O Function Serial clock pin SCL I/O IIC serial clock input/output Serial data pin SDA I/O IIC serial data input/output Rev. 0.1, 11/98, page 457 of 975 24.1.4 Register Configuration Table 24.2 summarizes the registers of the I2C bus interface. Table 24.2 Register Configuration Abbrev. R/W Initial Value Address*1 2 ICCR R/W H'01 H'D158 2 ICSR R/W H'00 H'D159 2 ICDR R/W -- H'D15E I C bus mode register 2 ICMR R/W H'00 H'D15F Slave address register SAR R/W H'00 H'D15F Second slave address register SARX R/W H'01 H'D15E Serial timer control register STCR R/W H'00 H'FFEE Module stop control register MSTPCRH R/W H'3F H'FFEC MSTPCRL R/W H'FF H'FFED Name I C bus control register I C bus status register I C bus data register *2 *2 *2 *2 Notes: 1. Lower 16 bits of the address. 2 2. The register that can be written or read depends on the ICE bit in the I C bus control 2 register. The slave address register can be accessed when ICE = 0, and the I C bus mode register can be accessed when ICE = 1. 2 The I C bus interface registers are assigned to the same addresses as other registers. Register selection is performed by means of the IICE bit in the serial/timer control register (STCR). 24.2 Register Descriptions 24.2.1 I C Bus Data Register (ICDR) 2 Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 ICDR7 ICDR6 ICDR5 ICDR4 ICDR3 ICDR2 ICDR1 ICDR0 -- -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W Rev. 0.1, 11/98, page 458 of 975 ICDRR Bit : 7 6 5 4 3 2 1 0 ICDRR7 ICDRR6 ICDRR5 ICDRR4 ICDRR3 ICDRR2 ICDRR1 ICDRR0 Initial value : -- -- -- -- -- -- -- -- R/W : R R R R R R R R ICDRS Bit : 7 6 5 4 3 2 1 0 ICDRS7 ICDRS6 ICDRS5 ICDRS4 ICDRS3 ICDRS2 ICDRS1 ICDRS0 Initial value : -- -- -- -- -- -- -- -- R/W : -- -- -- -- -- -- -- -- Bit : 7 6 5 4 3 2 1 0 ICDRT7 ICDRT6 ICDRT5 ICDRT4 ICDRT3 ICDRT2 ICDRT1 ICDRT0 Initial value : -- -- -- -- -- -- -- -- R/W : W W W W W W W W -- -- TDRE RDRF Initial value : 0 0 R/W : -- -- ICDRT TDRE, RDRF (Internal flag) Bit : ICDR is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. ICDR is divided internally into a shift register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). ICDRS cannot be read or written by the CPU, ICDRR is read-only, and ICDRT is write-only. Data transfers among the three registers are performed automatically in coordination with changes in the bus state, and affect the status of internal flags such as TDRE and RDRF. If IIC is in transmit mode and the next data is in ICDRT (the TDRE flag is 0) following transmission/reception of one frame of data using ICDRS, data is transferred automatically from ICDRT to ICDRS. If IIC is in receive mode and no previous data remains in ICDRR (the RDRF flag is 0) following transmission/reception of one frame of data using ICDRS, data is transferred automatically from ICDRS to ICDRR. Rev. 0.1, 11/98, page 459 of 975 If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and receive data are stored differently. Transmit data should be written justified toward the MSB side when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1. ICDR is assigned to the same address as SARX, and can be written and read only when the ICE bit is set to 1 in ICCR. The value of ICDR is undefined after a reset. The TDRE and RDRF flags are set and cleared under the conditions shown below. Setting the TDRE and RDRF flags affects the status of the interrupt flags. TDRE Description 0 The next transmit data is in ICDR (ICDRT), or transmission cannot be started [Clearing conditions] (Initial value) (1) When transmit data is written in ICDR (ICDRT) in transmit mode (TRS = 1) (2) When a stop condition is detected in the bus line state after a stop condition is 2 issued with the I C bus format or serial format selected 2 (3) When a stop condition is detected with the I C bus format selected (4) In receive mode (TRS = 0) (A 0 write to TRS during transfer is valid after reception of a frame containing an acknowledge bit) The next transmit data can be written in ICDR (ICDRT) [Setting conditions] (1) In transmit mode (TRS = 1), when a start condition is detected in the bus line state 2 after a start condition is issued in master mode with the I C bus format or serial format selected (2) When data is transferred from ICDRT to ICDRS (Data transfer from ICDRT to ICDRS when TRS = 1 and TDRE = 0, and ICDRS is empty) (3) When a switch is made from receive mode (TRS = 0) to transmit mode (TRS = 1) after detection of a start condition 1 RDRF Description 0 The data in ICDR (ICDRR) is invalid (Initial value) [Clearing condition] When ICDR (ICDRR) receive data is read in receive mode The ICDR (ICDRR) receive data can be read [Setting condition] When data is transferred from ICDRS to ICDRR (Data transfer from ICDRS to ICDRR in case of normal termination with TRS = 0 and RDRF = 0) 1 Rev. 0.1, 11/98, page 460 of 975 24.2.2 Slave Address Register (SAR) 7 6 5 4 3 2 1 0 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit : Initial value : R/W : SAR is an 8-bit readable/writable register that stores the slave address and selects the communication format. When the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device specified by the master device. SAR is assigned to the same address as ICMR, and can be written and read only when the ICE bit is cleared to 0 in ICCR. SAR is initialized to H'00 by a reset. Bits 7 to 1: Slave Address (SVA6 to SVA0) Set a unique address in bits SVA6 to SVA0, differing from the addresses of other slave devices 2 connected to the I C bus. Bit 0: Format Select (FS) Used together with the FSX bit in SARX to select the communication format. * I2C bus format: addressing format with acknowledge bit * Synchronous serial format: non-addressing format without acknowledge bit, for master mode only The FS bit also specifies whether or not SAR slave address recognition is performed in slave mode. SAR Bit 0 FS 0 SARX Bit 0 FSX 0 1 1 0 1 Operating Mode 2 I C bus format * SAR and SARX slave addresses recognized 2 I C bus format * SAR slave address recognized * SARX slave address ignored 2 I C bus format * SAR slave address ignored * SARX slave address recognized Synchronous serial format * SAR and SARX slave addresses ignored (Initial value) Rev. 0.1, 11/98, page 461 of 975 24.2.3 Second Slave Address Register (SARX) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 FSX 0 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W R/W SARX is an 8-bit readable/writable register that stores the second slave address and selects the communication format. When the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device specified by the master device. SARX is assigned to the same address as ICDR, and can be written and read only when the ICE bit is cleared to 0 in ICCR. SARX is initialized to H'01 by a reset and in hardware standby mode. Bits 7 to 1: Second Slave Address (SVAX6 to SVAX0) Set a unique address in bits SVAX6 to SVAX0, differing from the addresses of other slave 2 devices connected to the I C bus. Bit 0: Format Select X (FSX) Used together with the FS bit in SAR to select the communication format. * I2C bus format: addressing format with acknowledge bit * Synchronous serial format: non-addressing format without acknowledge bit, for master mode only The FSX bit also specifies whether or not SARX slave address recognition is performed in slave mode. For details, see the description of the FS bit in SAR. 24.2.4 2 I C Bus Mode Register (ICMR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 MLS WAIT CKS2 CKS1 CKS0 BC2 BC1 BC0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred first, performs master mode wait control, and selects the master mode transfer clock frequency and the transfer bit count. ICMR is assigned to the same address as SAR. ICMR can be written and read only when the ICE bit is set to 1 in ICCR. ICMR is initialized to H'00 by a reset. Rev. 0.1, 11/98, page 462 of 975 Bit 7: MSB-First/LSB-First Select (MLS) Selects whether data is transferred MSB-first or LSB-first. If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and receive data are stored differently. Transmit data should be written justified toward the MSB side when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1. 2 Do not set this bit to 1 when the I C bus format is used. Bit 7 MLS Description 0 MSB-first 1 LSB-first (Initial value) Bit 6: Wait Insertion Bit (WAIT) Selects whether to insert a wait between the transfer of data and the acknowledge bit, in master 2 mode with the I C bus format. When WAIT is set to 1, after the fall of the clock for the final data bit, the IRIC flag is set to 1 in ICCR, and a wait state begins (with SCL at the low level). When the IRIC flag is cleared to 0 in ICCR, the wait ends and the acknowledge bit is transferred. If WAIT is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted. The IRIC flag in ICCR is set to 1 on completion of the acknowledge bit transfer, regardless of the WAIT setting. The setting of this bit is invalid in slave mode. Bit 6 WAIT Description 0 Data and acknowledge bits transferred consecutively 1 Wait inserted between data and acknowledge bits (Initial value) Rev. 0.1, 11/98, page 463 of 975 Bits 5 to 3: Transfer Clock Select (CKS2 to CKS0) These bits, together with the IICX bit in the STCR register, select the serial clock frequency in master mode. They should be set according to the required transfer rate. STCR Bit 6 Bit 5 Bit 4 Bit 3 IICX CKS2 CKS1 CKS0 Clock = 5 MHz = 8 MHz = 10 MHz 0 0 0 0 /28 179 kHz 286 kHz 357 kHz 1 /40 125 kHz 200 kHz 250 kHz 0 /48 104 kHz 167 kHz 208 kHz 1 /64 78.1 kHz 125 kHz 156 kHz 0 /80 62.5 kHz 100 kHz 125 kHz 1 /100 50.0 kHz 80.0 kHz 100 kHz 0 /112 44.6 kHz 71.4 kHz 89.3 kHz 1 /128 39.1 kHz 62.5 kHz 78.1 kHz 0 /56 89.3 kHz 143 kHz 179 kHz 1 /80 62.5 kHz 100 kHz 125 kHz 0 /96 52.1 kHz 83.3 kHz 104 kHz 1 /128 39.1 kHz 62.5 kHz 78.1 kHz 0 /160 31.3 kHz 50.0 kHz 62.5 kHz 1 /200 25.0 kHz 40.0 kHz 50.0 kHz 0 /224 22.3 kHz 35.7 kHz 44.6 kHz 1 /256 19.5 kHz 31.3 kHz 39.1 kHz 1 1 0 1 1 0 0 1 1 0 1 Rev. 0.1, 11/98, page 464 of 975 Transfer Rate Bits 2 to 0: Bit Counter (BC2 to BC0) 2 Bits BC2 to BC0 specify the number of bits to be transferred next. With the I C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL line is low. The bit counter is initialized to 000 by a reset and when a start condition is detected. The value returns to 000 at the end of a data transfer, including the acknowledge bit. Bit 2 Bit 1 Bit 0 Bits/Frame BC2 BC1 BC0 Synchronous Serial Format I2C Bus Format 0 0 0 8 9 (Initial value) 1 1 2 0 2 3 1 3 4 0 4 5 1 5 6 0 6 7 1 7 8 1 1 0 1 Rev. 0.1, 11/98, page 465 of 975 2 24.2.5 I C Bus Control Register (ICCR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 ICE IEIC MST TRS ACKE BBSY IRIC SCP 0 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/(W)* W Note: * Only 0 can be written to clear the flag. 2 ICCR is an 8-bit readable/writable register that enables or disables the I C bus interface, enables or disables interrupts, selects master or slave mode and transmission or reception, enables or 2 disables acknowledgement, confirms the I C bus interface bus status, issues start/stop conditions, and performs interrupt flag confirmation. ICCR is initialized to H'01 by a reset. 2 Bit 7: I C Bus Interface Enable (ICE) 2 Selects whether or not the I C bus interface is to be used. When ICE is set to 1, port pins function as SCL and SDA input/output pins and transfer operations are enabled. When ICE is 2 cleared to 0, the I C bus interface module is disabled. The SAR and SARX registers can be accessed when ICE is 0. The ICMR and ICDR registers can be accessed when ICE is 1. Bit 7 ICE Description 0 I C bus interface module disabled, with SCL and SDA signal pins set to port function SAR and SARX can be accessed (Initial value) 1 I C bus interface module enabled for transfer operations (pins SCL and SCA are driving the bus) ICMR and ICDR can be accessed 2 2 2 Bit 6: I C Bus Interface Interrupt Enable (IEIC) 2 Enables or disables interrupts from the I C bus interface to the CPU. Bit 6 IEIC Description 0 Interrupts disabled 1 Interrupts enabled Rev. 0.1, 11/98, page 466 of 975 (Initial value) Bit 5: Master/Slave Select (MST) Bit 4: Transmit/Receive Select (TRS) 2 MST selects whether the I C bus interface operates in master mode or slave mode. 2 TRS selects whether the I C bus interface operates in transmit mode or receive mode. 2 In master mode with the I C bus format, when arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave receive mode. In slave receive mode with the addressing format (FS = 0 or FSX = 0), hardware automatically selects transmit or receive mode according to the R/W bit in the first frame after a start condition. Modification of the TRS bit during transfer is deferred until transfer of the frame containing the acknowledge bit is completed, and the changeover is made after completion of the transfer. MST and TRS select the operating mode as follows. Bit 5 Bit 4 MST TRS Description 0 0 Slave receive mode 1 Slave transmit mode 0 Master receive mode 1 Master transmit mode 1 (Initial value) Bit 5 MST Description 0 Slave mode (Initial value) [Clearing conditions] (1) When 0 is written by software 2 (2) When bus arbitration is lost after transmission is started in I C bus format master mode 1 Master mode [Setting conditions] (1) When 1 is written by software (in cases other than clearing condition 2) (2) When 1 is written in MST after reading MST = 0 (in case of clearing condition 2) Rev. 0.1, 11/98, page 467 of 975 Bit 4 TRS Description 0 Receive mode (Initial value) [Clearing conditions] (1) When 0 is written by software (in cases other than setting condition 3) (2) When 0 is written in TRS after reading TRS = 1 (in case of setting condition 3) 2 (3) When bus arbitration is lost after transmission is started in I C bus format master mode 1 Transmit mode [Setting conditions] (1) When 1 is written by software (in cases other than clearing conditions 3) (2) When 1 is written in TRS after reading TRS = 0 (in case of clearing conditions 3) 2 (3) When a 1 is received as the R/W bit of the first frame in I C bus format slave mode Bit 3: Acknowledge Bit Judgement Selection (ACKE) Specifies whether the value of the acknowledge bit returned from the receiving device when 2 using the I C bus format is to be ignored and continuous transfer is performed, or transfer is to be aborted and error handling, etc., performed if the acknowledge bit is 1. When the ACKE bit is 0, the value of the received acknowledge bit is not indicated by the ACKB bit, which is always 0. When the ACKE bit is 0, the TDRE, IRIC, and IRTR flags are set on completion of data transmission, regardless of the value of the acknowledge bit. When the ACKE bit is 1, the TDRE, IRIC, and IRTR flags are set on completion of data transmission when the acknowledge bit is 0, and the IRIC flag alone is set on completion of data transmission when the acknowledge bit is 1. Depending on the receiving device, the acknowledge bit may be significant, in indicating completion of processing of the received data, for instance, or may be fixed at 1 and have no significance. Bit 3 ACKE Description 0 The value of the acknowledge bit is ignored, and continuous transfer is performed (Initial value) 1 If the acknowledge bit is 1, continuous transfer is interrupted Rev. 0.1, 11/98, page 468 of 975 Bit 2: Bus Busy (BBSY) 2 The BBSY flag can be read to check whether the I C bus (SCL, SDA) is busy or free. In master mode, this bit is also used to issue start and stop conditions. A high-to-low transition of SDA while SCL is high is recognized as a start condition, setting BBSY to 1. A low-to-high transition of SDA while SCL is high is recognized as a stop condition, clearing BBSY to 0. To issue a start condition, use a MOV instruction to write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, use a MOV instruction to write 0 in BBSY and 0 in SCP. 2 It is not possible to write to BBSY in slave mode; the I C bus interface must be set to master transmit mode before issuing a start condition. MST and TRS should both be set to 1 before writing 1 in BBSY and 0 in SCP. Bit 2 BBSY Description 0 Bus is free [Clearing condition] When a stop condition is detected 1 Bus is busy [Setting condition] When a start condition is detected (Initial value) 2 Bit 1: I C Bus Interface Interrupt Request Flag (IRIC) 2 Indicates that the I C bus interface has issued an interrupt request to the CPU. IRIC is set to 1 at the end of a data transfer, when a slave address or general call address is detected in slave receive mode, when bus arbitration is lost in master transmit mode, and when a stop condition is detected. IRIC is set at different times depending on the FS bit in SAR and the WAIT bit in ICMR. See section 24.3.6, IRIC Setting Timing and SCL Control. The conditions under which IRIC is set also differ depending on the setting of the ACKE bit in ICCR. IRIC is cleared by reading IRIC after it has been set to 1, then writing 0 in IRIC. When the DTC is used, IRIC is cleared automatically and transfer can be performed continuously without CPU intervention. Rev. 0.1, 11/98, page 469 of 975 Bit 1 IRIC Description 0 Waiting for transfer, or transfer in progress (Initial value) [Clearing condition] (1) When 0 is written in IRIC after reading IRIC = 1 (1) Interrupt requested [Setting conditions] * 2 I C bus format master mode (1) When a start condition is detected in the bus line state after a start condition is issued (when the TDRE flag is set to 1 because of first frame transmission) (2) When a wait is inserted between the data and acknowledge bit when WAIT = 1 (3) At the end of data transfer (when the TDRE or RDRF flag is set to 1) (4) When a slave address is received after bus arbitration is lost (when the AL flag is set to 1) (5) When 1 is received as the acknowledge bit when the ACKE bit is 1 (when the ACKB bit is set to 1) * 2 I C bus format slave mode (1) When the slave address (SVA, SVAX) matches (when the AAS and AASX flags are set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the TDRE or RDRF flag is set to 1) (2) When the general call address is detected (when the ADZ flag is set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the TDRE or RDRF flag is set to 1) (3) When 1 is received as the acknowledge bit when the ACKE bit is 1 (when the ACKB bit is set to 1) (4) When a stop condition is detected (when the STOP or ESTP flag is set to 1) * Synchronous serial format (1) At the end of data transfer (when the TDRE or RDRF flag is set to 1) (2) When a start condition is detected with serial format selected Rev. 0.1, 11/98, page 470 of 975 2 When, with the I C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set IRIC to 1. Although each source has a corresponding flag, caution is needed at the end of a transfer. When the TDRE or RDRF internal flag is set, the readable IRTR flag may or may not be set. The IRTR flag (the DTC start request flag) is not set at the end of a data transfer up to detection of a retransmission start condition or stop condition after a slave address (SVA) or general call 2 address match in I C bus format slave mode. Even when the IRIC flag and IRTR flag are set, the TDRE or RDRF internal flag may not be set. The IRIC and IRTR flags are not cleared at the end of the specified number of transfers in continuous transfer using the DTC. The TDRE or RDRF flag is cleared, however, since the specified number of ICDR reads or writes have been completed. Table 24.3 shows the relationship between the flags and the transfer states. Note: * This LSI does not incorporate DTC. Rev. 0.1, 11/98, page 471 of 975 Table 24.3 Flags and Transfer States MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB State 1/0 1/0 0 0 0 0 0 0 0 0 0 Idle state (flag clearing required) 1 1 0 0 0 0 0 0 0 0 0 Start condition issuance 1 1 1 0 0 1 0 0 0 0 0 Start condition established 1 1/0 1 0 0 0 0 0 0 0 0/1 Master mode wait 1 1/0 1 0 0 1 0 0 0 0 0/1 Master mode transmit/receive end 0 0 1 0 0 0 1/0 1 1/0 1/0 0 Arbitration lost 0 0 1 0 0 0 0 0 1 0 0 SAR match by first frame in slave mode 0 0 1 0 0 0 0 0 1 1 0 General call address match 0 0 1 0 0 0 0 0 0 0 0 SARX match 0 1/0 1 0 0 0 0 0 0 0 0/1 Slave mode transmit/receive end (except after SARX match) 0 0 1/0 1 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1 Slave mode transmit/receive end (after SARX match) 0 1/0 0 1/0 1/0 0 0 0 0 0 0/1 Stop condition detected Bit 0: Start Condition/Stop Condition Prohibit (SCP) Controls the issuing of start and stop conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP. This bit is always read as 1. If 1 is written, the data is not stored. Bit 0 SCP Description 0 Writing 0 issues a start or stop condition, in combination with the BBSY flag 1 Reading always returns a value of 1 Writing is ignored Rev. 0.1, 11/98, page 472 of 975 (Initial value) 24.2.6 2 I C Bus Status Register (ICSR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 ESTP STOP IRTR AASX AL AAS ADZ ACKB 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/W Note: * Only 0 can be written to clear the flag. ICSR is an 8-bit readable/writable register that performs flag confirmation and acknowledge confirmation and control. ICSR is initialized to H'00 by a reset. Bit 7: Error Stop Condition Detection Flag (ESTP) 2 Indicates that a stop condition has been detected during frame transfer in I C bus format slave mode. Bit 7 ESTP Description 0 No error stop condition (Initial value) [Clearing condition] (1) When 0 is written in ESTP after reading ESTP = 1 (2) When the IRIC flag is cleared to 0 1 * 2 In I C bus format slave mode Error stop condition detected [Setting condition] * When a stop condition is detected during frame transfer * In other modes No meaning Rev. 0.1, 11/98, page 473 of 975 Bit 6: Normal Stop Condition Detection Flag (STOP) 2 Indicates that a stop condition has been detected after completion of frame transfer in I C bus format slave mode. Bit 6 STOP Description 0 No normal stop condition (Initial value) [Clearing condition] (1) When 0 is written in STOP after reading STOP = 1 (2) When the IRIC flag is cleared to 0 1 * 2 In I C bus format slave mode Error stop condition detected [Setting condition] * When a stop condition is detected after completion of frame transfer * In other modes No meaning Rev. 0.1, 11/98, page 474 of 975 2 Bit 5: I C Bus Interface Continuous Transmission/Reception Interrupt Request Flag (IRTR) 2 Indicates that the I C bus interface has issued an interrupt request to the CPU, and the source is completion of reception/transmission of one frame in continuous transmission/reception for which DTC activation is possible. When the IRTR flag is set to 1, the IRIC flag is also set to 1 at the same time. IRTR flag setting is performed when the TDRE or RDRF flag is set to 1. IRTR is cleared by reading IRTR after it has been set to 1, then writing 0 in IRTR. IRTR is also cleared automatically when the IRIC flag is cleared to 0. Note: * This LSI does not incorporate DTC. Bit 5 IRTR Description 0 Waiting for transfer, or transfer in progress (Initial value) [Clearing condition] (1) When 0 is written in IRTR after reading IRTR = 1 (2) When the IRIC flag is cleared to 0 1 Continuous transfer state [Setting condition] * In I C bus interface slave mode * When the TDRE or RDRF flag is set to 1 when AASX = 1 * In other modes * When the TDRE or RDRF flag is set to 1 2 Rev. 0.1, 11/98, page 475 of 975 Bit 4: Second Slave Address Recognition Flag (AASX) 2 In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in SARX. AASX is cleared by reading AASX after it has been set to 1, then writing 0 in AASX. AASX is also cleared automatically when a start condition is detected. Bit 4 AASX Description 0 Second slave address not recognized (Initial value) [Clearing condition] (1) When 0 is written in AASX after reading AASX = 1 (2) When a start condition is detected (3) In master mode 1 Second slave address recognized [Setting condition] * When the second slave address is detected in slave receive mode Bit 3: Arbitration Lost (AL) 2 This flag indicates that arbitration was lost in master mode. The I C bus interface monitors the bus. When two or more master devices attempt to seize the bus at nearly the same time, if the 2 I C bus interface detects data differing from the data it sent, it sets AL to 1 to indicate that the bus has been taken by another master. AL is cleared by reading AL after it has been set to 1, then writing 0 in AL. In addition, AL is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive mode. Bit 3 AL Description 0 Bus arbitration won (Initial value) [Clearing conditions] (1) When ICDR data is written (transmit mode) or read (receive mode) (2) When 0 is written in AL after reading AL = 1 1 Arbitration lost [Setting conditions] (1) If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode (2) If the internal SCL line is high at the fall of SCL in master transmit mode Rev. 0.1, 11/98, page 476 of 975 Bit 2: Slave Address Recognition Flag (AAS) 2 In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected. AAS is cleared by reading AAS after it has been set to 1, then writing 0 in AAS. In addition, AAS is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive mode. Bit 2 AAS Description 0 Slave address or general call address not recognized (Initial value) [Clearing conditions] (1) When ICDR data is written (transmit mode) or read (receive mode) (2) When 0 is written in AAS after reading AAS = 1 (3) In master mode 1 Slave address or general call address recognized [Setting condition] * When the slave address or general call address is detected in slave receive mode Bit 1: General Call Address Recognition Flag (ADZ) 2 In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition is the general call address (H'00). ADZ is cleared by reading ADZ after it has been set to 1, then writing 0 in ADZ. In addition, ADZ is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive mode. Bit 1 ADZ Description 0 General call address not recognized (Initial value) [Clearing conditions] (1) When ICDR data is written (transmit mode) or read (receive mode) (2) When 0 is written in ADZ after reading ADZ = 1 (3) In master mode 1 General call address recognized [Setting condition] * If the general call address is detected when FSX = 0 or FS = 0 is selected in the slave receive mode. Rev. 0.1, 11/98, page 477 of 975 Bit 0: Acknowledge Bit (ACKB) Stores acknowledge data. In transmit mode, after the receiving device receives data, it returns acknowledge data, and this data is loaded into ACKB. In receive mode, after data has been received, the acknowledge data set in this bit is sent to the transmitting device. When this bit is read, in transmission (when TRS = 1), the value loaded from the bus line (returned by the receiving device) is read. In reception (when TRS = 0), the value set by internal software is read. Bit 0 ACKB Description 0 Receive mode: 0 is output at acknowledge output timing (Initial value) Transmit mode: Indicates that the receiving device has acknowledged the data (signal is 0) 1 Receive mode: 1 is output at acknowledge output timing Transmit mode: Indicates that the receiving device has not acknowledged the data (signal is 1) 24.2.7 Serial/Timer Control Register (STCR) Bit : 7 6 5 4 3 2 1 0 -- IICX IICRST -- FLSHE -- -- -- Initial value : 0 0 0 0 0 0 0 0 R/W : -- R/W R/W -- R/W -- -- -- STCR is an 8-bit readable/writable register that controls the IIC operating mode. STCR is initialized to H'00 by a reset. Bit 7: Reserved This bit is reserved. 2 Bit 6: I C Transfer Select (IICX) This bit, together with bits CKS2 to CKS0 in ICMR of IIC, selects the transfer rate in master 2 mode. For details, see section 24.2.4, I C Bus Mode Register (ICMR). Rev. 0.1, 11/98, page 478 of 975 2 Bit 5: I C Controller Reset (IICRST) 2 This bit determines whether or not the controller section other than the I C register is reset. If 2 IICRST bit is set to 1 when hung-up by a communication error, etc., the I C controller section is 2 reset, enabling the entire I C to be reset without port setting or register initialization. For the detail, refer to section 24.3.9, Initialization of Internal State. The IIC controller can be reset by setting this flag once, then clearing it. Bit 5 IICRST Description 0 IIC controller is not reset 1 IIC controller is reset (Initial value) Bits 3: Flash Memory Control Resister Enable (FLSHE) This bit selects the control resister of the flash memory. For details, refer to section 7.3.4, Serial Timer Control Resister. Bits 4 and 2 to 0: Reserved These bits are reserved. 24.2.8 Module Stop Control Register (MSTPCR) MSTPCRH Bit : 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop mode control. When the corresponding bit in MSTPCR is set to 1, operation of the corresponding IIC channel is halted at the end of the bus cycle, and a transition is made to module stop mode. For details, see section 4.5, Module Stop Mode. MSTPCR is initialized to H'FFFF by a reset. It is not initialized in standby mode. Rev. 0.1, 11/98, page 479 of 975 MSTPCRL Bit 6: Module Stop (MSTP4) 2 Specifies I C module stop mode. MSTPCRL Bit 6 MSTP6 Description 0 I C module stop mode is cleared 1 Tra I C module stop mode is set (Initial value) 2 2 24.3 Operation 24.3.1 I C Bus Data Format (Initial value) 2 The I2C bus interface has serial and I2C bus formats. 2 The I C bus formats are addressing formats with an acknowledge bit. These are shown in figure 24.3. The first frame following a start condition always consists of 8 bits. The serial format is a non-addressing format with no acknowledge bit. This is shown in figure 24.4. 2 Figure 24.5 shows the I C bus timing. The symbols used in figures 24.3 to 24.5 are explained in table 24.4. (a) FS = 0 or FSX = 0 S 1 SLA 7 R/W 1 A 1 DATA n A 1 1 A/A 1 P 1 m Transfer bit count (n = 1 to 8) Transfer frame count (m = 1 or above) (b) Start condition transmission, FS = 0 or FSX = 0 S 1 SLA 7 R/W 1 A 1 DATA n1 1 A/A 1 S 1 SLA 7 m1 R/W 1 A 1 DATA n2 1 A/A 1 P 1 m2 Upper: Transfer bit count (n1 and N2 = 1 to 8) Lower: Transfer frame count (m1 and m2 = 1 or above) 2 2 Figure 24.3 I C Bus Data Formats (I C Bus Formats) Rev. 0.1, 11/98, page 480 of 975 FS = 1 and FSX = 1 S DATA DATA P 1 8 n 1 1 m Transfer bit count (n = 1 to 8) Transfer frame count (m = 1 or above) 2 Figure 24.4 I C Bus Data Format (Serial Format) SDA SCL S 1-7 8 9 SLA R/W A 1-7 8 DATA 9 A 1-7 8 DATA 9 A/A P 2 Figure 24.5 I C Bus Timing 2 Table 24.4 I C Bus Data Format Symbols S Start condition. The master device drives SDA from high to low while SCL is hig SLA Slave address, by which the master device selects a slave device R/: Indicates the direction of data transfer: from the slave device to the master device when R/: is 1, or from the master device to the slave device when R/: is 0 A Acknowledge. The receiving device (the slave in master transmit mode, or the master in master receive mode) drives SDA low to acknowledge a transfer DATA Transferred data. The bit length is set by bits BC2 to BC0 in ICMR. The MSB-first or LSB-first format is selected by bit MLS in ICMR P Stop condition. The master device drives SDA from low to high while SCL is high 24.3.2 Master Transmit Operation In master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The transmit procedure and operations in master transmit mode are described below. [1] Set bit ICE in ICCR to 1. Set bits MLS, WAIT, and CKS2 to CKS0 in ICMR, and bit IICX in STCR, according to the operating mode. [2] Read the BBSY flag in ICCR, check that the bus is free, then set MST and TRS to 1 in ICCR to select master transmit mode. After that, write 1 in BBSY and 0 in SCP. This generates a start condition by causing a high-to-low transition of SDA while SCL is high. As a result, Rev. 0.1, 11/98, page 481 of 975 the TDRE internal flag is set to 1 and the IRIC and IRTR flags are also set to 1. If IEIC is set to 1 in ICCR, a CPU interrupt is requested. [3] If bit FS is 0 in SAR or bit FSX is 0 in SARX, the first frame following the start condition contains a 7-bit slave address and indicates the transmit/receive direction. Write data (slave address + R/:) to ICDR. At this time, the TDRE internal flag is cleared to 0. The written address data is transferred to ICDRS, and the TDRE internal flag is set to 1 again. Clear IRIC flag to 0 so that the end of transfer can be determined. The master device outputs the written data together with a sequence of transmit clock pulses at the timing shown in figure 24.6. The selected slave device (the device with the matching slave address) drives SDA low at the ninth transmit clock pulse to acknowledge the data. [4] When one frame of data has been transmitted, the IRIC flag is set to 1 in ICCR at the rise of the ninth transmit clock pulse. After one frame has been transferred, if the TDRE internal flag is 1, SCL is automatically brought to the low level in synchronization with the internal clock and held low. [5] When another data is to be sent, write it in ICDR. After making sure that the data has been sent to ICDRS and the TDRE flag is set to 1, clear the IRIC flag to 0. Transmission of the next frame is turned on in synchronization with the internal clock. Rev. 0.1, 11/98, page 482 of 975 Steps [4] and [5] can be repeated to transmit data continuously. To end the transmission, clear IRIC, write dummy data in ICDR after making sure that the last data has been sent (the next transmission date is not present on ICDRT yet). Then, write 0 in BBSY and 0 in ICCR when IRIC is set again. This generates a stop condition by causing a low-to-high transition of SDA while SCL is high. Start condition issuance SCL (Master output) SDA (Master output) 1 2 3 4 5 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 7 Bit 1 8 9 Bit 0 1 2 Bit 7 Bit 6 [4] Slave address SDA (Slave output) Data 1 R/W A TDRE IRIC ICDRT ICDRS Interrupt request generated Interrupt request generated Data 1 Address + RW Data 1 Address + RW User processing [2] Write BBSY=1 and [3] Write ICDR SCP=0 (Start condition issuance) [3] Clear IRIC [5] Write ICDR [5] Clear IRIC Figure 24.6 Example of Timing in Master Transmit Mode (MLS = WAIT = 0) Rev. 0.1, 11/98, page 483 of 975 When continuously transmitting data, [6] Clear IRIC flag to 0 before startup of the 9th transmit clock of the data being transmitted, and then write the next transmit data in ICDR. [7] 1 frame data transmission ends, and upon startup of the 9th transmit clock, IRIC flag in ICCR is set to 1. At the same time, the next transmit data written in ICDR (ICDRT) is transferred to ICDRS, the flag in TDRE is set to 1, then the next frame transmission is executed, being synchronized with the internal clock. Steps [6] and [7] can be repeated to transmit data continuously. SCL (Master output) SDA (Master output) 1 2 3 4 5 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 7 Bit 1 Data 1 SDA (Slave output) 8 9 Bit 0 1 2 3 Bit 7 Bit 6 Bit 5 Data 2 [7] A TDRE Interrupt request generated IRIC ICDRT Data 1 Data 2 Data 3 [7] ICDRS Data 1 User processing Write ICDR Data 2 [6] Clear IRIC [6] Write ICDR [6] Clear IRIC [6] Write ICDR Figure 24.7 Example of Continuous Transmission Timing in Master Transmit Mode (MLS = WAIT = 0) Rev. 0.1, 11/98, page 484 of 975 24.3.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. The slave device transmits the data. The receive procedure and operations in master receive mode are described below. [1] Clear TRS to 0 in ICCR to switch from transmit mode to receive mode. Also, clear ICSR Ack B bit to 0 (setup of acknowledge data). [2] Read ICDR to start receiving (dummy data read). When ICDR is read, a receive clock is output in synchronization with the internal clock, and data is received. And, set the IRIC flag on ICCR to zero so that end of the signal receiving may be indicated. [3] At the ninth clock pulse the master device drives SDA low to acknowledge the data. When one frame of data has been received, the IRIC flag is set to 1 in ICCR at the rise of the ninth receive clock pulse. If IEIC is set to 1 in ICCR, a CPU interrupt is requested. If the RDRF internal flag is 0 at this time, it is set to 1, and continuous reception is performed. If reception of the next frame is completed before the ICDR read and IRIC flag clearing in step 4, SCL is automatically brought to the low level in synchronization with the internal clock and held low. [4] Read ICDR and clear IRIC to 0 in ICCR. At this time, RDRF flag is cleared to 0. Rev. 0.1, 11/98, page 485 of 975 Steps [3] and [4] can be repeated to receive data continuously. At the time the mode is first switched from master transmit mode to master receive mode and reception has just started, RDRF internal flag is cleared to 0, therefore data reception of the next frame is automatically started. To stop receiving, TRS bit must be set to 1 before startup of the next frame receive clock. To stop receiving, set TRS to 1, read ICDR, then write 0 in BBSY and 0 in SCP in ICCR. This generates a stop condition by causing a low-to-high transition of SDA while SCL is high. Master transmit mode Master receive mode SCL (Master output) 9 1 2 3 4 5 SDA (Slave output) A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 6 Bit 2 7 Bit 1 8 9 Bit 0 Data 1 SDA (Master output) 1 2 Bit 7 Bit 6 Data 2 [3] A RDRF IRIC Interrupt request generated Interrupt request generated ICDRS Data 2 ICDRR User processing Data 1 [1]Clear TRS to 0 [2]Read ICDR (dummy read) [2]Clear IRIC [4] Read ICDR [4] Clear IRIC Figure 24.8 Example of Timing in Master Receive Mode (MLS = WAIT = ACKB = 0) Rev. 0.1, 11/98, page 486 of 975 24.3.4 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The receive procedure and operations in slave receive mode are described below. [1] Set bit ICE in ICCR to 1. Set bits MLS in ICMR and bits MST and TRS in ICCR according to the operating mode. [2] A start condition output by the master device sets the BBSY flag to 1 in ICCR. [3] After the slave device detects the start condition, if the first frame matches its slave address, it functions as the slave device designated as the master device. If the 8th bit data (R/ :) is 0, TRS bit in ICCR remains 0 and executes slave receive operation. [4] At the ninth clock pulse of the receive frame, the slave device drives SDA low to acknowledge the transfer. At the same time, the IRIC flag is set to 1 in ICCR. If IEIC is 1 in ICCR, a CPU interrupt is requested. If the RDRF internal flag is 0, it is set to 1 and continuous reception is performed. If the RDRF internal flag is 1, the slave device holds SCL low from the fall of the receive clock until it has read the data in ICDR. [5] Read ICDR and clear IRIC to 0 in ICCR. At this time, the RDFR flag is cleared to 0. Steps [4] and [5] can be repeated to receive data continuously. When a stop condition is detected (a low-to-high transition of SDA while SCL is high), the BBSY flag is cleared to 0 in ICCR. Rev. 0.1, 11/98, page 487 of 975 Start condition issurance SCL (Master output) 1 2 3 Bit 7 Bit 6 Bit 5 4 5 Bit 4 Bit 3 6 7 8 9 1 2 SCL (Slave output) SDA (Master output) SDA (Slave output) Slave address Bit 2 Bit 1 Bit 0 R/W Bit 7 Bit 6 Data 1 [4] A RDRF IRIC Interrupt request generated ICDRS Address + R/W ICDRR User processing Address + R/W [5] Read ICDR [5] Clear IRIC Figure 24.9 Example of Timing in Slave Receive Mode (MLS = ACKB = 0) (1) Rev. 0.1, 11/98, page 488 of 975 SCL (Master output) 7 8 Bit 1 Bit 0 9 1 2 3 4 5 6 7 8 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 SCL (Slave output) SDA (Master output) Data 1 SDA (Slave output) Bit 7 Bit 6 [4] [4] Data 2 A A RDRF IRIC Interrupt request generated ICDRS Data 1 ICDRR Data 1 User processing [5] Read ICDR Interrupt request generated Data 2 Data 2 [5] Clear IRIC Figure 24.10 Example of Timing in Slave Receive Mode (MLS = ACKB = 0) (2) Rev. 0.1, 11/98, page 489 of 975 24.3.5 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data, and the master device outputs the transmit clock and returns an acknowledge signal. The transmit procedure and operations in slave transmit mode are described below. [1] Set bit ICE in ICCR to 1. Set bits MLS in ICMR and bits MST and TRS in ICCR according to the operating mode. [2] After the slave device detects a start condition, if the first frame matches its slave address, at the ninth clock pulse the slave device drives SDA low to acknowledge the transfer. At the same time, the IRIC flag is set to 1 in ICCR, and if the IEIC bit in ICCR is set to 1 at this time, an interrupt request is sent to the CPU. If the eighth data bit (R/ :) is 1, the TRS bit is set to 1 in ICCR, automatically causing a transition to slave transmit mode. The slave device holds SCL low from the fall of the transmit clock until data is written in ICDR. [3] Clear the IRIC flag to 0, then write data in ICDR. The written data is transferred to ICDRS, and the TDRE internal flag and the IRIC and IRTR flags are set to 1 again. Clear IRIC to 0, then write the next data in ICDR. The slave device outputs the written data serially in step with the clock output by the master device, with the timing shown in figure 24.11. [4] When one frame of data has been transmitted, at the rise of the ninth transmit clock pulse IRIC is set to 1 in ICCR. If the TDRE internal flag is 1, the slave device holds SCL low from the fall of the transmit clock until data is written in ICDR. The master device drives SDA low at the ninth clock pulse to acknowledge the data. The acknowledge signal is stored in the ACKB bit in ICSR, and can be used to check whether the transfer was carried out normally. If TDRE internal flag is set to 0, the data written in ICDR is transferred to ICDRS, then transmission starts and TDRE internal flag and IRIC and IRTR flags are all set to 1 again. [5] To continue transmitting, clear IRIC to 0, then write the next transmit data in ICDR. Steps [4] and [5] can be repeated to transmit continuously. To end the transmission, write H'FF in ICDR so that the SPA may be freed on the slave side. When a stop condition is detected (a low-to-high transition of SDA while SCL is high), the BBSY flag will be cleared to 0 in ICCR. Rev. 0.1, 11/98, page 490 of 975 Slave receive mode SCL (Master output) 8 Slave transmit mode 9 1 2 3 4 5 6 7 8 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 1 2 Bit 7 Bit 6 SCL (Slave output) SDA (Slave output) Bit 7 A SDA (Master output) R/W Bit 6 Data 1 [2] Data 2 A TDRE Interrupt request generated IRIC ICDRT Data 1 ICDRS User processing [3] Interrupt request generated Interrupt request generated Data 2 Data 1 [3] Clear IRIC [3] Write ICDR Data 2 [3] Write ICDR [5] Clear IRIC [5] Write ICDR Figure 24.11 Example of Timing in Slave Transmit Mode (MLS = 0) Rev. 0.1, 11/98, page 491 of 975 24.3.6 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is automatically held low after one frame has been transferred; this timing is synchronized with the internal clock. Figure 24.12 shows the IRIC set timing and SCL control. (a) When WAIT = 0, and FS = 0 or FSX = 0 (I2C bus format, no wait) SCL SDA 7 8 9 1 7 8 A 1 IRIC User processing Clear IRIC Write to ICDR (transmit) or read ICDR (receive) (b) When WAIT = 1, and FS = 0 or FSX = 0 (I2C bus format, wait inserted) SCL SDA 8 9 1 8 A 1 IRIC User processing Clear IRIC Clear IRIC Write to ICDR (transmit) or read ICDR (receive) (c) When FS = 1 and FSX = 1 (synchronous serial format) SCL SDA 7 8 1 7 8 1 IRIC User processing Clear IRIC Write to ICDR (transmit) or read ICDR (receive) Figure 24.12 IRIC Setting Timing and SCL Control Rev. 0.1, 11/98, page 492 of 975 24.3.7 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 24.13 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held. Sampling clock SCL or SDA input signal C C D Q Latch D Q Latch Match detector Internal SCL or SDA signal System clock period Sampling clock Figure 24.13 Block Diagram of Noise Canceler Rev. 0.1, 11/98, page 493 of 975 24.3.8 Sample Flowcharts Figures 24.14 to 24.17 show sample flowcharts for using the I2C bus interface in each mode. Start [1] Test the status of the SCL and SDA lines. Initialize [2] Select master transmit mode. Read BBSY flag in ICCR [3] Generate a start condition. [1] No [4] Set transmit data for the first byte (slave address +R/W) BBSY=0? Yes Set MST=1 and TRS=1 in ICCR [2] Write BBSY=1 and SCP=0 in ICCR Write transmit data in ICDR [5] Wait for 1 byte to be transmitted. [3] [6] Test for acknowledgement by the designated slave device. [4] [7] Set transmit data for the second and subsequent bytes. Clear IRIC flag in ICCR [8] Wait for 1 byte to be transmitted. Read IRIC flag in ICCR [9] Test for end of transfer. No [5] IRIC=1? [10] Generate a stop condition. Yes Read ACKB bit in ICSR ACKB=0? No [6] Yes Transmit mode? No Master receive mode Yes Write transmit data in ICDR [7] Clear IRIC flag in ICCR Read IRIC flag in ICCR No [8] IRIC=1? Yes Read ACKB bit in ICSR No [9] End of transmission (ACKB = 1)? Yes Write BBSY=0 and SCP=0 in ICCR [10] End Figure 24.14 Flowchart for Master Transmit Mode (Example) Rev. 0.1, 11/98, page 494 of 975 [1] Select receive mode. Master receive mode Set TRS=0 in ICCR [1] [2] Set acknowledge data. Set ACKB=0 in ICSR [2] [3] Start receiving. The first read is a dummy read. Last receive? Yes No Read ICDR [4] Wait for 1 byte to be received. [5] Set acknowledge data for the last receive. [3] [6] Start the last receive. Clear IRIC flag in ICCR [7] Wait for 1 byte to be received. Read IRIC flag in ICCR [8] Select transmit mode. No IRIC=1? [4] [9] Read the last receive data (if ICDR is read without selecting transmit mode, receive operations will resume). Yes Set ACKB=1 in ICSR Read ICDR [5] [10] Generate a stop condition. [6] Clear IRIC flag in ICCR Read IRIC flag in ICCR No [7] IRIC=1? Yes Set TRS=1 in ICCR Read ICDR [8] [9] Clear IRIC flag in ICCR Write BBSY=0 and SCP=0 in ICCR [10 ] End Figure 24.15 Flowchart for Master Receive Mode (Example) Rev. 0.1, 11/98, page 495 of 975 Start Initialize Set MST=0 and TRS=0 in ICCR [1] Set ACKB=0 in ICSR Read IRIC flag in ICCR No [2] IRIC=1? Yes Read AAS and ADZ flags in ICSR No AAS=1 and ADZ=0? General call address processing *Description omitted Yes Read TRS bit in ICCR No TRS=0? Slave transmit mode Yes Last receive? Yes No Read ICDR [3] Clear IRIC flag in ICCR Read IRIC flag in ICCR No [1] Select slave receive mode. [4] [2] Wait for 1 byte to be received (slave address) IRIC=1? Yes [3] Start receiving. The first read is a dummy read. Set ACKB=0 in ICSR [5] Read ICDR [6] [4] Wait for the transfer to end. [5] Set acknowledge data for the last receive. Clear IRIC flag in ICCR [6] Start the last receive. Read IRIC flag in ICCR No [7] IRIC=1? [7] Wait for the transfer to end. [8] Read the last receive data. Yes Read ICDR [8] Clear IRIC flag in ICCR End Figure 24.16 Flowchart for Slave Transmit Mode (Example) Rev. 0.1, 11/98, page 496 of 975 [1] Set transmit data for the second and subsequent bytes. Slave transmit mode Clear IRIC in ICCR [2] Wait for 1 byte to be transmitted. Write transmit data in ICDR [1] Clear IRIC flag in ICCR [4] Select slave receive mode. [5] Dummy read (to release the SCL line). Read IRIC flag in ICCR No [3] Test for end of transfer. [2] IRIC=1? Yes Read ACKB bit in ICSR No End of transmission (ACKB=1)? [3] Yes Set TRS=0 in ICCR [4] Read ICDR [5] Clear IRIC flag in ICCR End Figure 24.17 Flowchart for Slave Receive Mode (Example) 24.3.9 Initialization of Internal State This IIC is capable of forcibly initializing internal state of IIC if deadlock develops during communication. The initialization is done by resetting IICRST bit on STCR register once, then clearing it. (1) Range of Initialization The following is initialized by this function: * Internal flags of TDRE and RDRF * Programmable logic controller for signal receiving and sending. * Internal latches used for holding outputs from SCL and SDA pins (wait, clock, data output, etc.). The following is not initialized by this function: * Register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR and STCR). * Internal latches employed for maintaining data read from the registers which is used for setting or clearing flags on ICMR, ICCR, ICSR and DDCSWR registers. Rev. 0.1, 11/98, page 497 of 975 * Values on the ICMR register bit counters (BC2 to BC0). * Interrupt factors currently generated (interrupt factors transferred to the interrupt controller). (2) Precautions on Initialization * Interrupt flags and interrupt factors are not cleared by this function. Thus, you need to clear them own as needed. * Other register flags are not basically cleared, too. Thus, you need to clear them as needed. * Write data specified by IICRST bit is maintained. When clearing IIC, set IICRST bit once, then clear it using the MOV instruction. Don't try to use bit operation instructions such as BCLR. When another clearing is performed, predetermined setting must be written to all bits at the same time. * If you try to clear a flag while data sending or receiving is taking place, IIC module stops sending or receiving at that moment and frees the SCL and SDA pins. When resuming the communication, initialize registers as needed so that the system communication capability may function as intended. Clear function of this module does not directly rewrite value of BBSY bit. However, depending on state of SCL and SDA pins and the timing in which they are made free, BBSY bit can be cleared. Other bits and flags can also be affected by status change. In order to avoid these troubles, the following procedures must be observed in initialization of IIC. (1) Implement initialization of internal state through setting IICRST bit. (2) Execute the stop condition issue instruction (setting BBSY = 0 and SCP = 0 to write) and wait for a duration equivalent to 2 clocks of the transfer rate. (3) Execute initialization of internal state again through setting IICRST bit. (4) Initialize each IIC register (re-setting). 24.4 Usage Notes (1) In master mode, if an instruction to generate a start condition is immediately followed by an instruction to generate a stop condition, neither condition will be output correctly. To output consecutive start and stop conditions, after issuing the instruction that generates the start condition, read the relevant ports, check that SCL and SDA are both low, then issue the instruction that generates the stop condition. (2) Either of the following two conditions will start the next transfer. Pay attention to these conditions when reading or writing to ICDR. (a) Write access to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to ICDRS) Rev. 0.1, 11/98, page 498 of 975 (b) Read access to ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to ICDRR) (3) Table 24.5 shows the timing of SCL and SDA output in synchronization with the internal clock. Timings on the bus are determined by the rise and fall times of signals affected by the bus load capacitance, series resistance, and parallel resistance. 2 Table 24.5 I C Bus Timing (SCL and SDA Output) Item SCL output cycle time Symbol tSCLO SCL output high pulse width tSCLHO SCL output low pulse width tSCLLO SDA output bus free time tBUFO Start condition output hold time tSTAHO Retransmission start condition tSTASO output setup time Stop condition output setup time tSTOSO Data output setup time (master) tSDASO Data output setup time (slave) Data output hold time tSDAHO Note: 1. 6tcyc when IICX is 0, 12tcyc when 1. Output Timing 28tcyc to 256tcyc Unit ns 0.5tSCLO 0.5tSCLO 0.5tSCLO-1tcyc 0.5tSCLO-1tcyc 1tSCLO ns ns ns ns ns 0.5tSCLO-2tcyc 1tSCLLO-3tcyc 1 1tSCLL - (6tcyc or 12tcyc* ) 3tcyc ns ns ns ns Notes Figure 28.10 (reference) (4) SCL and SDA input is sampled in synchronization with the internal clock. The AC timing therefore depends on the system clock cycle tcyc, as shown in table 28.6 in section 28, 2 Electrical Characteristics. Note that the I C bus interface AC timing specifications will not be met with a system clock frequency of less than 5 MHz. 2 (5) The I C bus interface specification for the SCL rise time tsr is under 1000 ns (300 ns for 2 high-speed mode). In master mode, the I C bus interface monitors the SCL line and synchronizes one bit at a time during communication. If tsr (the time for SCL to go from low 2 to VIH) exceeds the time determined by the input clock of the I C bus interface, the high period of SCL is extended. The SCL rise time is determined by the pull-up resistance and load capacitance of the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance and load capacitance so that the SCL rise time does not exceed the values given in table 24.6. Rev. 0.1, 11/98, page 499 of 975 Table 24.6 Permissible SCL Rise Time (tsr) Values IICX tcyc Indication 0 7.5tcyc 1 17.5tcyc Time Indication [ns] I2C Bus Specification = 5 MHz (Max.) Normal mode High-speed mode Normal mode High-speed mode 2 1000 300 = 8 MHz 937 = 10 MHz 750 1000 300 (6) The I C bus interface specifications for the SCL and SDA rise and fall times are under 1000 2 ns and 300 ns. The I C bus interface SCL and SDA output timing is prescribed by tScyc and 2 tcyc, as shown in table 24.5. However, because of the rise and fall times, the I C bus interface specifications may not be satisfied at the maximum transfer rate. Table 24.7 shows output timing calculations for different operating frequencies, including the worst-case influence of rise and fall times. 2 tBUFO fails to meet the I C bus interface specifications at any frequency. The solution is either (a) to provide coding to secure the necessary interval (approximately 1 s) between issuance of a stop condition and issuance of a start condition, or (b) to select devices whose input 2 timing permits this output timing for use as slave devices connected to the I C bus. 2 tSCLLO in high-speed mode and tSTASO in standard mode fail to satisfy the I C bus interface specifications for worst-case calculations of tSr/tSf. Possible solutions that should be investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input timing permits this output timing for use as slave devices connected to 2 the I C bus. Rev. 0.1, 11/98, page 500 of 975 2 Table 24.7 I C Bus Timing (with Maximum Influence of tSr/tSf) Item tSCLHO tSCLLO tBUFO tSTAHO tSTASO tSTOSO tSDASO (master) tSDASO (slave) tSDAHO Time Indication (at Maximum Transfer Rate) [ns] tSr/tSf I2C Bus tcyc Influence Specificati = 5 MHz = 8 MHz Indication (Max.) on (Min.) 0.5tSCLO (-tSr) 0.5tSCLO (-tSf) 0.5tSCLO-1tcyc (-tSr) 0.5tSCLO-1tcyc (-tSf) 1tSCLO (-tSr) 0.5tSCLO+2tcyc (-tSr) 3 1tSCLLO* -3tcyc (-tSr) Normal mode -1000 4000 4000 = 10 MHz High-speed -300 mode Normal mode -250 600 950 4700 4750 High-speed -250 mode Normal mode -1000 1300 1000 *1 4700 3800 *1 3875 High-speed -300 mode Normal mode -250 1300 750 825 850 4000 4550 4625 4650 High-speed -250 mode Normal mode -1000 600 800 875 900 4700 9000 9000 9000 600 2200 2200 2200 4000 4400 4250 4200 600 1350 1200 1150 250 3100 3325 3400 100 400 625 700 250 1300 2200 2500 100 -1400 -500 -200 0 0 600 375 300 High-speed -300 mode Normal mode -1000 High-speed -300 mode Normal mode -1000 High-speed -300 mode 3 2 1tSCLL* -12tcyc* Normal mode -1000 (-tSr) High-speed -300 mode 3tcyc Normal mode 0 High-speed 0 mode *1 *1 *1 *1 *1 3900 *1 *1 *1 2 Notes: 1. Does not meet the I C bus interface specification. Remedial action such as the following is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate; (d) select slave devices whose input timing permits this output timing. The values in the above table will vary depending on the settings of the IICX bit and bits CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the 2 maximum transfer rate; therefore, whether or not the I C bus interface specifications are met must be determined in accordance with the actual setting conditions. 2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is (tSCLL - 6tcyc). Rev. 0.1, 11/98, page 501 of 975 2 3. Calculated using the I C bus specification values (standard mode: 4700 ns min.; highspeed mode: 1300 ns min.). (7) Precautions on reading ICDR at the end of master receive mode When terminating the master receive mode, set TRS bit to 1, and select "write" for ICCR BBSY = 0 and SCP = 0. This forces to move SDA from low to high level when SCL is at high level, thereby generating the stop condition. Now you can read received data from ICDR. If, however, any data is remaining on the buffer, received data on ICDRS is not transferred to ICDR, thus you won't be able to read the second byte data. When it is required to read the second byte data, issue the stop condition from the master receive state (TRS bit is 0). Before reading data from ICDR register, make sure that BBSY bit on ICCR register is 0, stop condition is generated and bus is made free. If you try to read received data after the stop condition issue instruction (setting ICCR's BBSY = 0 and SCP = 0 to write) has been executed but before the actual stop condition is generated, clock may not be appropriately signaled when the next master sending mode is turned on. Thus, reasonable care is needed for determining when to read the received data. After the master receive is complete, if you want to re-write IIC control bit (such as clearing MST bit) for switching the sending/receiving mode or modifying settings, it must be done during period (a) indicated in figure 24.18 (after making sure ICCR register BBSY bit is cleared to 0). Start condition Stop condition (a) SDA Bit 0 A SCL 8 9 Internal clock BBSY bit Master receive mode ICDR read inhibit period The stop condition issue instruction (BBSY = 0 and SCP = 0 set to write) is executed Generation of the stop condition is checked (BBSY = 0 is set to read) Start condition is issued Figure 24.18 Precautions on Reading the Master Receive Data Rev. 0.1, 11/98, page 502 of 975 Section 25 A/D Converter 25.1 Overview This LSI incorporates a 10-bit successive-approximations A/D converter that allows up to 12 analog input channels to be selected. 25.1.1 Features A/D converter features are listed below. * * * * 10-bit (analog input) or 6-bit (digital input) resolution 12 input channels Sample and hold function Choice of software, hardware (internal signal) triggering or external triggering for A/D conversion start. * A/D conversion end interrupt request generation Rev. 0.1, 11/98, page 503 of 975 25.1.2 Block Diagram Figure 25.1 shows a block diagram of the A/D converter. Internal data bus 10-bit D/A Successive approximation register Reference Voltage AVCC A D R A H R A D C S R A D C R AVSS A D T S R Hardware control circuit Vref Analog multiplexer AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 ANA ANB ADTRG (HSW timing generator) + DFG ADTRG Chopper type comparator Control circuit /2 /4 Sample-andhold circuit Interrupt request [Legend] ADR : Software trigger A/D result register AHR : Hardware trigger A/D result register ADCR : A/D control register ADCSR: A/D control/status register ADTSR: A/D trigger selection register ADTRG, DFG : Hardware trigger ADTRG : A/D external trigger input Figure 25.1 Block Diagram of A/D Converter Rev. 0.1, 11/98, page 504 of 975 25.1.3 Pin Configuration Table 25.1 summarizes the input pins used by the A/D converter. Table 25.1 A/D Converter Pins Name Abbrev. I/O Function Analog power supply pin AVCC Input Analog block power supply Analog ground pin AVSS Input Analog block ground and A/D conversion reference voltage Analog input pin 0 AN0 Input Analog input channel 0 Analog input pin 1 AN1 Input Analog input channel 1 Analog input pin 2 AN2 Input Analog input channel 2 Analog input pin 3 AN3 Input Analog input channel 3 Analog input pin 4 AN4 Input Analog input channel 4 Analog input pin 5 AN5 Input Analog input channel 5 Analog input pin 6 AN6 Input Analog input channel 6 Analog input pin 7 AN7 Input Analog input channel 7 Analog input pin 8 AN8 Input Analog input channel 8 Analog input pin 9 AN9 Input Analog input channel 9 Analog input pin A ANA Input Analog input channel A Analog input pin B ANB Input Analog input channel B A/D external trigger input pin $'75* Input External trigger input for starting A/D conversion Rev. 0.1, 11/98, page 505 of 975 25.1.4 Register Configuration Table 25.2 summarizes the registers of the A/D converter. Table 25.2 A/D Converter Registers R/W Size Initial Value Address*2 Software trigger A/D result ADRH register H R Byte H'00 H'D130 Software trigger A/D result ADRL register L R Byte H'00 H'D131 Hardware trigger A/D result register H AHRH R Byte H'00 H'D132 Hardware trigger A/D result register L AHRL R Byte H'00 H'D133 A/D control register ADCR R/W Byte H'40 H'D134 Byte H'01 H'D135 Name Abbrev. *1 A/D control/status register ADCSR R (W) A/D trigger selection register ADTSR R/W Byte H'FC H'D136 Port mode register 0 PMR0 R/W Byte H'00 H'FFCD Notes: 1. Only 0 can be written in bits 7 and 6, to clear the flag. Bits 3 to 1 are read-only. 2. Lower 16 bits of the address. Rev. 0.1, 11/98, page 506 of 975 25.2 Register Descriptions 25.2.1 Software-Triggered A/D Result Register (ADR) ADRH Bit : 15 14 13 12 11 ADRL 10 9 8 7 6 ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 Initial value : 0 0 0 0 0 0 0 0 0 0 R/W : R R R R R R R R R R 5 4 3 2 1 0 -- -- -- -- -- -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- The software-triggered A/D result register (ADR) is a register that stores the result of an A/D conversion started by software. The A/D-converted data is 10-bit data. Upon completion of software-triggered A/D conversion, the 10-bit result data is transferred to ADR and the data is retained until the next softwaretriggered A/D conversion completion. The upper 8 bits of the data are stored in the upper bytes (bits 15 to 8) of ADR, and the lower 2 bits are stored in the lower bytes (bits 7 and 6). Bits 5 to 0 are always read as 0. ADR can be read by the CPU at any time, but the ADR value during A/D conversion is not fixed. The upper bytes can always be read directly, but the data in the lower bytes is transferred via a temporary register (TEMP). For details, see section 25.3, Interface to Bus Master. ADR is a 16-bit read-only register which is initialized to H'0000 at a reset, and in module stop mode, standby mode, watch mode, subactive mode and subsleep mode. 25.2.2 Hardware-Triggered A/D Result Register (AHR) Error! Cannot open file. The hardware-triggered A/D result register (AHR) is a register that stores the result of an A/D conversion started by hardware (internal signal: ADTRG and DFG) or by external trigger input ($'75*). The A/D-converted data is 10-bit data. Upon completion of hardware- or external-triggered A/D conversion, the 10-bit result data is transferred to AHR and the data is retained until the next hardware- or external- triggered A/D conversion completion. The upper 8 bits of the data are stored in the upper bytes (bits 15 to 8) of AHR, and the lower 2 bits are stored in the lower bytes (bits 7 and 6). Bits 5 to 0 are always read as 0. AHR can be read by the CPU at any time, but the AHR value during A/D conversion is not fixed. The upper bytes can always be read directly, but the data in the lower bytes is transferred via a temporary register (TEMP). For details, see section 25.3, Interface to Bus Master. AHR is a 16-bit read-only register which is initialized to H'0000 at a reset, and in module stop mode, standby mode, watch mode, subactive mode and subsleep mode. Rev. 0.1, 11/98, page 507 of 975 25.2.3 A/D Control Register (ADCR) Bit : 7 CK 6 -- 5 HCH1 4 HCH0 3 SCH3 2 SCH2 1 SCH1 0 SCH0 Initial value : 0 R/W 1 -- 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W R/W : ADCR is a register that sets A/D conversion speed and selects analog input channel. When executing ADCR setting, make sure that the SST and HST flags in ADCSR is set to 0. ADCR is an 8-bit readable/writable register that is initialized to H'40 by a reset, and in module stop mode, standby mode, watch mode, subactive mode and subsleep mode. Bit 7: Clock Select (CK) Sets A/D conversion speed. Bit 7 CK Description 0 Conversion frequency is 266 states 1 Conversion frequency is 134 states (Initial value) Note: A/D conversion starts when 1 is written in SST, or when HST is set to 1. The conversion period is the time from when this start flag is set until the flag is cleared at the end of conversion. Actual sample-and-hold takes place (repeatedly) during the conversion frequency shown in figure 25.2. Rev. 0.1, 11/98, page 508 of 975 States Instruction execution MOV.B WRITE Start flag Conversion frequency Conversion period (134 or 266 states) Interrupt request flag IRQ sampling (CPU) Note: IRQ sampling; When conversion ends, the start flag is cleared and the interrupt request flag is set. The CPU recognizes the interrupt in the last execution state of an instruction, and executes interrupt exception handling after completing the instruction. Figure 25.2 Internal Operation of A/D Converter Bit 6: Reserved This bit cannot be modified and always reads 1. Writes are disabled. Bits 5 and 4: Hardware Channel Select (HCH1, HCH0) These bits select the analog input channel that is converted by hardware triggering or triggering by an external input. Only channels AN8 to ANB are available for hardware- or externaltriggered conversion. Bit 5 Bit 4 HCH1 HCH0 Analog Input Channel 0 0 AN8 1 AN9 0 ANA 1 ANB 1 (Initial value) Rev. 0.1, 11/98, page 509 of 975 Bits 3 to 0: Software Channel Select (SCH3 to SCH0) These bits select the analog input channel that is converted by software triggering. When channels AN0 to AN7 are used, appropriate pin settings must be made in port mode register 0 (PMR0). For pin settings, see section 25.2.6, Port Mode Register 0 (PMR0). Bit 3 Bit 2 Bit 1 Bit 0 SCH3 SCH2 SCH1 SCH0 Analog Input Channel 0 0 0 0 AN0 1 AN1 0 AN2 1 AN3 0 AN4 1 AN5 0 AN6 1 AN7 0 AN8 1 AN9 0 ANA 1 ANB * No channel selected for software-triggered conversion 1 1 0 1 1 0 0 1 1 * (Initial value) Notes: 1. If conversion is started by software when SCH3 to SCH0 are set to 11**, the conversion result is undetermined. Hardware- or external-triggered conversion, however, will be performed on the channel selected by HCH1 and HCH0. 2. *: Don't care. Rev. 0.1, 11/98, page 510 of 975 25.2.4 A/D Control/Status Register (ADCSR) Bit : 7 SEND 6 HEND 5 ADIE 4 SST 3 HST 2 BUSY 1 SCNL 0 -- Initial value : R/W : 0 R/(W)* 0 R/(W)* 0 R/W 0 R/W 0 R 0 R 0 R 1 -- Note: * Only 0 can be written to bits 7 and 6, to clear the flag. The A/D status register (ADCSR) is an 8-bit register that can be used to start or stop A/D conversion, or check the status of the A/D converter. A/D conversion starts when 1 is written in SST flag. A/D conversion can also start by setting HST flag to 1 by hardware- or external-triggering. For ADTRG start by HSW timing generator in hardware triggering, see section 27.4, HSW Timing Generator. When conversion ends, the converted data is stored in the software-triggered A/D result register (ADR) or hardware-triggered A/D result register (AHR), and the SST or HST bit is cleared to 0. If software-triggering and hardware- or external-triggering are generated at the same time, priority is given to hardware- or external-triggering. ADCSR is an 8-bit register which is initialized to H'01 by a reset, and in module stop mode, standby mode, watch mode, subactive mode and subsleep mode. Bit 7: Software A/D End Flag (SEND) Indicates the end of A/D conversion. Bit 7 SEND Description 0 [Clearing Conditions] 0 is written after reading 1 1 [Setting Conditions] Software-triggered A/D conversion has ended (Initial value) Bit 6: Hardware A/D End Flag (HEND) Indicates that hardware- or external-triggered A/D conversion has ended. Bit 6 HEND Description 0 [Clearing Conditions] 0 is written after reading 1 [Setting Conditions] Hardware- or external-triggered A/D conversion has ended (Initial value) Rev. 0.1, 11/98, page 511 of 975 Bit 5: A/D Interrupt Enable (ADIE) Selects enable or disable of interrupt (ADI) generation upon A/D conversion end. Bit 5 ADIE Description 0 Interrupt (ADI) upon A/D conversion end is disabled 1 Interrupt (ADI) upon A/D conversion end is enabled (Initial value) Bit 4: Software A/D Start Flag (SST) Starts software-triggered A/D conversion and indicates or controls the end of conversion. This bit remains 1 during software-triggered A/D conversion. When 0 is written in this bit, software-triggered A/D conversion operation can forcibly be aborted. Bit 4 SST Description 0 Read: Indicates that software-triggered A/D conversion has ended or been stopped (Initial value) Write: Software-triggered A/D conversion is aborted 1 Read: Indicates that software-triggered A/D conversion is in progress Write: Starts software-triggered A/D conversion Bit 3: Hardware A/D Status Flag (HST) Indicates the status of hardware- or external-triggered A/D conversion. When 0 is written in this bit, A/D conversion is aborted regardless of whether it was hardware-triggered or externaltriggered. Bit 5 HST Description 0 Read: Hardware- or external-triggered A/D conversion is not in progress(Initial value) Write: Hardware- or external-triggered A/D conversion is aborted. 1 Hardware- or external-triggered A/D conversion is in progress. Rev. 0.1, 11/98, page 512 of 975 Bit 2: Busy Flag (BUSY) During hardware- or external-triggered A/D conversion, if software attempts to start A/D conversion by writing to the SST bit, the SST bit is not modified and instead the BUSY flag is set to 1. This flag is cleared when the hardware-triggered A/D result register (AHR) is read. Bit 2 BUSY Description 0 No contention for A/D conversion 1 Indicates an attempt to execute software-triggered A/D conversion while hardware- or external-triggered A/D conversion was in progress (Initial value) Bit 1: Software-Triggered Conversion Cancel Flag (SCNL) Indicates that software-triggered A/D conversion was canceled by the start of hardware-triggered A/D conversion. This flag is cleared when A/D conversion is started by software. Bit 1 SCNL Description 0 No contention for A/D conversion 1 Indicates that software-triggered A/D conversion was canceled by the start of hardware-triggered A/D conversion (Initial value) Bit 0: Reserved This bit cannot be modified and always reads 1. Writes are disabled. 25.2.5 Trigger Select Register (ADTSR) Bit : 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 TRGS1 0 TRGS0 Initial value : R/W : 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 0 R/W 0 R/W The trigger select register (ADTSR) selects hardware- or external-triggered A/D conversion start factor. ADTSR is an 8-bit readable/writable register that is initialized to H'FC by a reset, and in module stop mode, standby mode, watch mode, subactive mode and subsleep mode. Rev. 0.1, 11/98, page 513 of 975 Bits 7 to 2: Reserved These bits are reserved and are always read as 1. Writes are disabled. Bits 1 and 0: Trigger Select These bits select hardware- or external-triggered A/D conversion start factor. Set these bits when A/D conversion is not in progress. Bit 1 Bit 0 TRGS1 TRGS0 Description 0 0 Hardware- or external-triggered A/D conversion is disabled (Initial value) 1 Hardware-triggered (ADTRG) A/D conversion is selected 0 Hardware-triggered (DFG) A/D conversion is selected 1 External-triggered ($'75*) A/D conversion is selected 1 25.2.6 Port Mode Register 0 (PMR0) Bit : Initial value : R/W : 7 PMR07 6 PMR06 5 PMR05 4 PMR04 3 PMR03 2 PMR02 1 PMR01 0 PMR00 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Port mode register 0 (PMR0) controls switching of each pin function of port 0. Switching is specified for each bit. PMR0 is an 8-bit readable/writable register and is initialized to H'00 by a reset. Bit 7 to 0: P07/AN7 to P00/AN0 pin switching (PMR07 to PMR00) These bits set the P0n/ANn pin as the input pin for P0n or as the ANn pin for A/D conversion analog input channel. Bit n PMR0n Description 0 P0n/ANn functions as a general-purpose input port 1 P0n/ANn functions as an analog input channel (Initial value) (n = 7 to 0) Rev. 0.1, 11/98, page 514 of 975 25.2.7 Module Stop Control Register (MSTPCR) MSTPCRH Bit : 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR consists of 8-bit readable/writable registers and performs module stop mode control. When the MSTP2 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus cycle and a transition is made to module stop mode. For details, see section 4.5, Module Stop Mode. MSTPCR is initialized to H'FFFF by a reset Bit 2: Module Stop (MSTP2) Specifies the A/D converter module stop mode. MSTPCRL Bit 2 MSTP2 Description 0 A/D converter module stop mode is cleared 1 A/D converter module stop mode is set (Initial value) Rev. 0.1, 11/98, page 515 of 975 25.3 Interface to Bus Master ADR and AHR are 16-bit registers, but the data bus to the bus master is only 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP). A data reading from ADR and AHR is performed as follows. When the upper byte is read, the upper byte value is transferred to the CPU and the lower byte value is transferred to TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When reading ADR and AHR, always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. Figure 25.3 shows the data flow for ADR access. The data flow for AHR access is the same. Upper byte read Module data bus Bus master (H'AA) Bus interface TEMP (H'40) ADRH (H'AA) ADRL (H'40) Lower byte read Bus master (H'40) Module data bus Bus interface TEMP (H'40) ADRH (H'AA) ADRL (H'40) Figure 25.3 ADR Access Operation (Reading H'AA40) Rev. 0.1, 11/98, page 516 of 975 25.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. 25.4.1 Software-Triggered A/D Conversion A/D conversion starts when software sets the software A/D start flag (SST bit) to 1. The SST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends. Conversion can be software-triggered on any of the 12 channels provided by analog input pins AN0 to ANB. Bits SCH3 to SCH0 in ADCR select the analog input pin used for softwaretriggered A/D conversion. Pins AN8 to ANB are also available for hardware- or externaltriggered conversion. When conversion ends, SEND flag in ADCSR bit is set to 1. If ADIE bit in ADCSR is also set to 1, an A/D conversion end interrupt occurs. If the conversion time or input channel selection in ADCR needs to be changed during A/D conversion, to avoid malfunctions, first clear the SST bit to 0 to halt A/D conversion. If software writes 1 in the SST bit to start software-triggered conversion while hardware- or external-triggered conversion is in progress, the hardware- or external-triggered conversion has priority and the software-triggered conversion is not executed. At this time, BUSY flag in ADCSR is set to 1. The BUSY flag is cleared to 0 when the hardware-triggered A/D result register (AHR) is read. If conversion is triggered by hardware while software-triggered conversion is in progress, the software-triggered conversion is immediately canceled and the SST flag is cleared to 0, and SCNL flag in ADCSR is set to 1. The SCNL flag is cleared when software writes 1 in the SST bit to start conversion after the hardware-triggered conversion ends. Rev. 0.1, 11/98, page 517 of 975 25.4.2 Hardware- or External-Triggered A/D Conversion The system contains the hardware trigger function that allows to turn on A/D conversion at a specified timing by use of the hardware trigger (internal signals: ADTRG and DFG) and the incoming external trigger ($'75*). This function can be used to measure an analog signal that varies in synchronization with an external signal at a fixed timing. To execute hardware- or external-triggered A/D conversion, select appropriate start factor in TRGS1 and TRGS0 bits in ADTSR. When the selected triggering occurs, HST flag in ADCSR is set to 1 and A/D conversion starts. The HST flag remains 1 during A/D conversion, and is automatically cleared to 0 when conversion ends. For ADTRG start by HSW timing generator in hardware triggering, see section 27.4, HSW Timing Generator. Setting of the analog input pins on four channels from AN8 to ANB can be modified with the hardware trigger or the incoming external trigger. Setting is done from HCH1 and HCH0 bits on ADCR. Pins AN8 to ANB are also available for software-triggered conversion. When conversion ends, HEND flag in ADCSR is set to 1. If ADIE bit in ADCSR is also set to 1, an A/D conversion end interrupt occurs. If the conversion time or input channel selection in ADCR needs to be changed during A/D conversion, to avoid malfunctions, first clear the HST flag to 0 to halt A/D conversion. If software writes 1 in the SST bit to start software-triggered conversion while hardware- or external-triggered conversion is in progress, the hardware- or external-triggered conversion has priority and the software-triggered conversion is not executed. At this time, BUSY flag in ADCSR is set to 1. The BUSY flag is cleared to 0 when the hardware-triggered A/D result register (AHR) is read. If conversion is triggered by hardware while software-triggered conversion is in progress, the software-triggered conversion is immediately canceled and the SST flag is cleared to 0, and SCNL flag in ADCSR is set to 1 (the SCNL flag is cleared when software writes 1 in the SST bit to start conversion after the hardware-triggered conversion ends). The analog input channel changes automatically from the channel that was undergoing software-triggered conversion (selected by bits SCH3 to SCH0 in ADCR) to the channel selected by bits HCH1 and HCH0 in ADCR for hardware- or external-triggered conversion. After the hardware- or external-triggered conversion ends, the channel reverts to the channel selected by the software-triggered conversion channel select bits in ADCR. Hardware- or external-triggered conversion has priority over software-triggered conversion, so the A/D interrupt-handling routine should check the SCNL and BUSY flags when it processes the converted data. Rev. 0.1, 11/98, page 518 of 975 25.5 Interrupt Sources When A/D conversion ends, SEND or HEND flag in ADCSR is set to 1. The A/D conversion end interrupt can be enabled or disabled by ADIE bit in ADCSR. Figure 25.4 shows the block diagram of A/D conversion end interrupt. A/D control/status register (ADCSR) SEND HEND ADIE A/D conversion end interrupt (ADI) To interrupt controller Figure 25.4 Block Diagram of A/D Conversion End Interrupt Rev. 0.1, 11/98, page 519 of 975 Rev. 0.1, 11/98, page 520 of 975 Section 26 Address Trap Controller (ATC) 26.1 Overview The address trap controller (ATC) is capable of generating interrupt by setting an address to trap, when the address set appears during bus cycle. 26.1.1 Features Address to trap can be set independently at three points. 26.1.2 Block Diagram Figure 26.1 shows a block diagram of the address trap controller. TRCR TAR0 TAR1 Internal bus Bus interface Modules bus TAR2 Trap condition comparator Interrupt request TRCR TAR0 to 2 : Trap control register : Trap address register 0 to 2 Figure 26.1 Block Diagram of ATC Rev. 0.1, 11/98, page 521 of 975 26.1.3 Register Configuration Table 26.1 Register List Name Abbrev. R/W Initial Value Address * Address trap control register ATCR R/W H'F8 H'FFB9 Trap address register 0 TAR0 R/W H'F00000 H'FFB0 to H'FFB2 Trap address register 1 TAR1 R/W H'F00000 H'FFB3 to H'FFB5 Trap address register 2 TAR2 R/W H'F00000 H'FFB6 to H'FFB8 Note: * Lower 16 bits of the address. 26.2 Register Descriptions 26.2.1 Address Trap Control Register (ATCR) Bit : 7 6 5 4 3 2 1 0 -- -- -- -- -- TRC2 TRC1 TRC0 Initial value : 1 1 1 1 1 0 0 0 R/W : -- -- -- -- -- R/W R/W R/W Bits 7 to 3: Reserved These bits are reserved. When read, 1 is read at all times. Writes are disabled. Bit 2: Trap Control 2 (TRC2) Sets ON/OFF operation of the address trap function 2. Bit 2 TRC2 Description 0 Address trap function 2 disabled 1 Address trap function 2 enabled Rev. 0.1, 11/98, page 522 of 975 (Initial value) Bit 1: Trap Control 1 (TRC1) Sets ON/OFF operation of the address trap function 1. Bit 1 TRC1 Description 0 Address trap function 1 disabled 1 Address trap function 1 enabled (Initial value) Bit 0: Trap Control 0 (TRC0) Sets ON/OFF operation of the address trap function 0. Bit 0 TRC0 Description 0 Address trap function 0 disabled 1 Address trap function 0 enabled 26.2.2 (Initial value) Trap Address Register 2 to 0 (TAR2 to TAR0) Error! Cannot open file. The TAR is composed of three 8-bit readable/writable registers (TARnA, B, and C)(n = 2 to 0) The TAR sets the address to trap. The function of the TAR2 to TAR0 is the same. The TAR is initialized to H'00 by a reset. TARA bits 7 to 0: Addresses 23 to 16 (A23 to A16) TARB bits 7 to 0: Addresses 15 to 8 (A15 to A8) TARC bits 7 to 0: Addresses 7 to 1 (A7 to A1) If the value installed in this register and internal address buses A23 to A1 match as a result of comparison, an interruption occurs. For the address to trap, set to the address where the first byte of an instruction exists. In the case of other addresses, it may not be considered that the condition has been satisfied. Bit 0 of this register is fixed at 0. The address to trap becomes an even address. The range where comparison is made is H'000000 to H'FFFFFE. 26.3 Precautions in Usage Address trap interrupt arises 2 states after prefetching the trap address. Trap interrupt may occur after the trap instruction has been executed, depending on a combination of instructions immediately preceding the setting up of the address trap. If the instruction to trap immediately follows the branch instruction or the conditional branch Rev. 0.1, 11/98, page 523 of 975 instruction, operation may differ, depending on whether the condition was satisfied or not, or the address to be stacked may be located at the branch. Figures 26.2 to 26.22 show specific operations. For information as to where the next instruction prefetch occurs during the execution cycle of the instruction, see appendix A.5 of this manual or section 2.7 Bus State during Execution of Instruction of the H8S/2000 Series Programming Manual. (R:W NEXT is the next instruction prefetch.) Rev. 0.1, 11/98, page 524 of 975 26.3.1 Basic Operations After terminating the execution of the instruction being executed in the second state from the trap address prefetch, the address trap interrupt exception handling is started. (1) Figure 26.2 shows the operation when the instruction immediately preceding the trap address is that of 3 states or more of the execution cycle and the next instruction prefetch occurs in the state before the last 2 states. The address to be stacked is 0260. MOV NOP Internal instruc- instruc- operation tion tion pre-fetch pre-fetch Data read Start of exception handling Address bus 025E 0260 0000 0262 (ER3 = H'0000) Address Immediately preceding 025E MOV.B @ER3+,R2L Instruction * 0260 NOP 0262 NOP 0264 NOP MOV execution * Trap setting address The underlines address is the one to be actually stacked. Interrupt request signal Figure 26.2 Basic Operations (1) Note: In the figure above, the NOP instruction is used as the typical example of instruction with execution cycle of 1 state. Other instructions with the execution cycle of 1 state also apply (Ex. MOV.B, Rs, Rd). Rev. 0.1, 11/98, page 525 of 975 (2) Figure 26.3 shows the operation when the instruction immediately preceding the trap address is that of 2 states or more of the execution cycle and the next instruction prefetch occurs in the second state from the last. The address to be stacked is 0268. MOV NOP Data instruc- instruc- read tion tion pre-fetch pre-fetch NOP instruction pre-fetch Start of exception handling Address bus 0266 0268 0000 026A MOV execution Immediately Address preceding 0266 MOV.B instruction R2L, @0000 * 0268 NOP 026A NOP 026C NOP 026C NOP execution * Trap setting address The underlines address is the one to be actually stacked. Interrupt request signal Figure 26.3 Basic Operations (2) (3) Figure 26.4 shows the operation when the instruction immediately preceding the trap address is that of 1 state or 2 states or more and the prefetch occurs in the last state. The address to be stacked is 025C. NOP NOP NOP NOP instruc- instruc- instruc- instruction tion tion tion pre-fetch pre-fetch pre-fetch pre-fetch Start of exception handling Address bus 0256 0258 025A 025C Address Immediately 0256 NOP * 0258 NOP preceding 025A NOP instruction 025C NOP 025E NOP 025E NOP NOP NOP execu- execu- execution tion tion Interrupt request signal Figure 26.4 Basic Operations (3) Rev. 0.1, 11/98, page 526 of 975 * Trap setting address The underlines address is the one to be actually stacked. 26.3.2 Enable The address trap function becomes valid after executing one instruction following the setting of the enable bit of the address trap control register (TRCR) to 1. 029C *029E 02A0 02A2 02A4 02A6 BSET #0, @TRCR MOV.W R0, R1 MOV.B R1L, R3H NOP CMP.W R0, R1 NOP After executing the MOV instruction, the address trap interrupt does not arise, and the next instruction is executed. * Trap setting address Figure 26.5 Enable 26.3.3 Bcc Instruction (1) When the condition is satisfied by Bcc instruction (8-bit displacement) If the trap address is the next instruction to the Bcc instruction and the condition is satisfied by the Bcc instruction and then branched, transition is made to the address trap interrupt after executing the instruction at the branch. The address to be stacked is 02A8. BEQ NOP CMP NOP instruc- instruc- instruc- instruction tion tion tion pre-fetch pre-fetch pre-fetch pre-fetch Start of exception handling Address bus 029C 029E 02A6 02A8 BEQ execution Interrupt request signal CMP execution 02AA (NEXT = H'02A6) 029C * 029E 02A0 02A2 02A4 02A6 02A8 BEQ NEXT:8 NOP NOP NOP NOP CMP.W R0, R1 NOP * Trap setting address The underlines address is the one to be actually stacked. Figure 26.6 When the Condition is Satisfied by Bcc Instruction (8-bit Displacement) Rev. 0.1, 11/98, page 527 of 975 (2) When the condition is not satisfied by Bcc instruction (8-bit displacement) If the trap address is the next instruction to the Bcc instruction and the condition is not satisfied by the Bcc instruction and thus it fails to branch, transition is made to the address trap interrupt after executing the trap address instruction and prefetching the next instruction. The address to be stacked is 02A2. BEQ NOP CMP NOP instruc- instruc- instruc- instruction tion tion tion pre-fetch pre-fetch pre-fetch pre-fetch Start of exception handling Address bus 029E 02A0 02A8 02A2 BEQ execution 02A4 NOP execution (NEXT = H'02A8) 029E * 02A0 02A2 02A4 02A6 NEXT: 02A8 02AA BEQ NEXT:8 NOP NOP NOP NOP CMP.W R0, R1 NOP * Trap setting address The underlines address is the one to be actually stacked. Interrupt request signal Figure 26.7 When the Condition is Not Satisfied by Bcc Instruction (8-bit Displacement) (3) When condition is not satisfied by Bcc instruction (16-bit displacement) If the trap address is the next instruction to the Bcc instruction and the condition is not satisfied by the Bcc instruction and thus it fails to branch, transition is made to the address trap interrupt after executing the trap address instruction (if the trap address instruction is that of 2 states or more. If the instruction is that of 1 state, after executing two instructions). The address to be stacked is 02C0. BEQ instruction pre-fetch Data fetch Internal operation NOP NOP NOP instruc- instruc- instruction tion tion pre-fetch pre-fetch pre-fetch Start of exception handling (NEXT = H'02C4) Address bus 02B8 02BA 02BC 02BE 02C0 BEQ execution Interrupt request signal NOP NOP execu- execution tion 02C2 02B8 BEQ NEXT:16 * 02BC NOP 02BE NOP 02C0 NOP 02C2 NOP NEXT: 02C4 NOP * Trap setting address The underlines address is the one to be actually stacked. Figure 26.8 When the Condition is Not Satisfied by Bcc Instruction (16-bit Displacement) Rev. 0.1, 11/98, page 528 of 975 (4) When the condition is not satisfied by Bcc instruction (Trap address at branch) When the trap address is at the branch of the Bcc instruction and the condition is not satisfied by the Bcc instruction and thus it fails to branch, transition is made into the address trap interrupt after executing the next instruction (if the next instruction is that of 2 states or more. If the next instruction is that of 1 state, after executing two instructions). The address to be stacked is 0262. BEQ NOP CMP NOP NOP instruc- instruc- instruc- instruc- instruction tion tion tion tion pre-fetch pre-fetch pre-fetch pre-fetch pre-fetch Start of exception handling Address bus 025C 025E 0266 0260 0262 BEQ execution Interrupt request signal NOP NOP execu- execution tion 0264 (NEXT = H'0266) 025C 025E 0260 0262 0264 NEXT: * 0266 0268 BEQ NEXT:8 NOP NOP NOP NOP CMP.W R0, R1 NOP * Trap setting address The underlines address is the one to be actually stacked. Figure 26.9 When the Condition is Not Satisfied by Bcc Instruction (Trap Address at Branch) Rev. 0.1, 11/98, page 529 of 975 26.3.4 BSR Instruction (1) BSR Instruction (8-bit displacement) When the trap address is the next instruction to the BSR instruction and the addressing mode is an 8-bit displacement, transition is made to the address trap interrupt after prefetching the instruction at the branch. The address to be stacked is 02C2. BSR NOP MOV instruc- instruc- instruction tion tion pre-fetch pre-fetch pre-fetch Stack saving Start of exception handling 0294 * 0296 0298 : Address bus (@ER0 = H'02C2) 0294 0296 02C2 SP-2 SP-4 BSR execution BSR @ER0 NOP NOP : 02C4 02C2 02C4 MOV.W R4, @OUT NOP * Trap setting address The underlines address is the one to be actually stacked. Interrupt request signal Figure 26.10 BSR Instruction (8-bit Displacement) Rev. 0.1, 11/98, page 530 of 975 26.3.5 JSR Instruction (1) JSR Instruction (Register indirect) When the trap address is the next instruction to the JSR instruction and the addressing mode is a register indirect, transition is made to the address trap interrupt after prefetching the instruction at the branch. The address to be stacked is 02C8. JSR NOP MOV instruc- instruc- instruction tion tion pre-fetch pre-fetch pre-fetch Stack saving Start of exception handling (@ER0 = H'02C8) 029A * 029C 029E : Address bus 029A 029C 02C8 SP-2 SP-4 02CA JSR @ER0 NOP NOP : 02C8 02CE JSRexecution MOV.W R4, @OUT NOP * Trap setting address The underlines address is the one to be actually stacked. Interrupt request signal Figure 26.11 JSR Instruction (Register indirect) (2) JSR Instruction (Memory indirect) When the trap address is the next instruction to the JSR instruction and the addressing mode is memory indirect, transition is made to the address trap interrupt after prefetching the instruction at the branch. The address to be stacked is 02EA. JSR NOP instruc- instruction tion pre-fetch pre-fetch Data fetch Stack saving NOP instruction pre-fetch Start of exception handling Address bus 0294 0296 006C 006E SP-2 SP-4 02EA JSR execution Interrupt request signal 02EC 006C : 0294 * 0296 0298 : 02EA 02EC H'02EA : JSR @@H'6C:8 NOP NOP : NOP NOP * Trap setting address The underlines address is the one to be actually stacked. Figure 26.12 JSR Instruction (Memory Indirect) Rev. 0.1, 11/98, page 531 of 975 26.3.6 JMP Instruction (1) JMP Instruction (Register indirect) When the trap address is the next instruction to the JMP instruction and the addressing mode is a register indirect, transition is made to the address trap interrupt after prefetching the instruction at the branch. The address to be stacked is 02AA. JMP NOP MOV instruc- instruc- instruction tion tion pre-fetch pre-fetch pre-fetch Data fetch NOP instruction pre-fetch Start of exception handling Address bus 029A 029C 02A4 02A6 02A8 02AA JMP execution 02AC MOV.L execution (@ER0 = H'02A4) 029A * 029C 029E 02A0 02A2 02A4 02AA JMP @ER0 NOP NOP NOP NOP MOV.L #DATA, ER1 NOP * Trap setting address The underlines address is the one to be actually stacked. Interrupt request signal Figure 26.13 JMP Instruction (Register Indirect) (2) JMP Instruction (Memory indirect) When the trap address is the next instruction to the JMP instruction and the addressing mode is memory indirect, transition is made to the address trap interrupt after prefetching the instruction at the branch. The address to be stacked is 02E4. JMP NOP instruc- instruction tion pre-fetch pre-fetch Data fetch Internal NOP opera- instruction tion pre-fetch Start of exception handling Address bus 0294 0296 006C 006E 006C 02E4 JMP execution 02E6 006C : 0294 * 0296 0298 : 02E4 02E6 H'02E4 : JMP @@H'6C:8 NOP NOP : NOP NOP * Trap setting address The underlines address is the one to be actually stacked. Interrupt request signal Figure 26.14 JMP Instruction (Memory Indirect) Rev. 0.1, 11/98, page 532 of 975 26.3.7 RTS Instruction When the trap address is the next instruction to the RTS instruction, transition is made to the address trap interrupt after reading the CCR and PC from the stack and prefetching the instruction at the return location. The address to be stacked is 0298. RTS NOP instruc- instruction tion pre-fetch pre-fetch Stack saving Internal NOP opera- instruction tion pre-fetch Start of exception handling (@ER0 = H'02C8) 0296 0298 029A Address bus 02AC 02AE SP SP+2 SP 0298 029A BSR SUB NOP NOP : 02AC * 02AE RTS execution : RTS NOP * Trap setting address The underlines address is the one to be actually stacked. Break interrupt request signal Figure 26.15 RTS Instruction 26.3.8 SLEEP Instruction (1) SLEEP Instruction 1 When the trap address is the SLEEP instruction and the instruction execution cycle immediately preceding the SLEEP instruction is that of 2 states or more and prefetch does not occur in the last state, the SLEEP instruction is not executed and transition is made to the address trap interrupt without going into SLEEP mode. The address to be stacked is 0274. MOV SLEEP Data NOP instruc- instrucinstrucwrite tion tion tion pre-fetch pre-fetch pre-fetch Start of exception handling Address bus 0272 0274 FFF9 MOV execution 0276 SP-2 SP-4 0272 * 0274 0276 0278 : SLEEP cancel MOV.B R2L, @FFF8 SLEEP NOP NOP : * Trap setting address The underlines address is the one to be actually stacked. Interrupt request signal Figure 26.16 SLEEP Instruction (1) Rev. 0.1, 11/98, page 533 of 975 (2) SLEEP Instruction 2 When the trap address is the SLEEP instruction and the instruction execution cycle immediately preceding the SLEEP instruction is that of 1 state 2 states or more and prefetch occurs in the last state, this puts in the SLEEP mode after execution of the SLEEP instruction, and the SLEEP mode is cancelled by the address trap interrupt and transition is made to the exception handling. The address to be stacked is 0264. NOP SLEEP NOP instruc- instruc- instruction tion tion pre-fetch pre-fetch pre-fetch Start of exception handling Address bus 0260 0262 0264 NOP SLEEP execution execution SP-2 SP-4 0260 * 0262 0264 0266 : SLEEP mode NOP SLEEP NOP NOP : * Trap setting address The underlines address is the one to be actually stacked. Interrupt request signal Figure 26.17 SLEEP Instruction (2) (3) SLEEP Instruction 3 When the trap address is the next instruction to the SLEEP instruction, this puts in the SLEEP mode after execution of the SLEEP instruction, and the SLEEP mode is cancelled by the address trap interrupt and transition is made to the exception handling. The address to be stacked is 0282. SLEEP NOP instruc- instruction tion pre-fetch pre-fetch Start of exception h andling Address bus 0280 0282 SLEEP execution SP-2 SP-4 NOP SLEEP NOP NOP : SLEEP mode Interrupt request signal Figure 26.18 SLEEP Instruction (3) Rev. 0.1, 11/98, page 534 of 975 027E 0280 * 0282 0284 : * Trap setting address The underlines address is the one to be actually stacked. (4) SLEEP Instruction 4 (Standby or Watch Mode Setting) When the trap address is the SLEEP instruction and the instruction immediately preceding the SLEEP instruction is that of 1 state or 2 states or more and prefetch occurs in the last state, this puts in the standby (watch) mode after execution of the SLEEP instruction. After that, if the standby (watch) mode is cancelled by the NMI interrupt, transition is made to NMI interrupt following the CCR and PC (at the address of 0266) stack saving and vector reading. However, if the address trap interrupt arises before starting execution of the NMI interrupt processing, transition is made to the address trap exception handling. The address to be stacked is the starting address of the NMI interrupt processing. NOP SLEEP NOP instruc- instruc- instruction tion tion pre-fetch pre-fetch pre-fetch NMI interrupt Address trap interruption 0262 * 0264 0266 Address bus 0262 0264 0266 SLEEP Standby execution mode NOP SLEEP NOP SP-2 SPCA SP-2 * Trap setting address Interrupt request signal Figure 26.19 SLEEP Instruction (4) (Standby or Watch Mode Setting) Rev. 0.1, 11/98, page 535 of 975 (5) SLEEP Instruction 5 (Standby or Watch Mode Setting) When the trap address is the next instruction to the SLEEP instruction, this puts in the standby (watch) mode after execution of the SLEEP instruction. After that, if the standby (watch) mode is cancelled by the NMI interruption, transition is made to the NMI interrupt following the CCR and PC (at the address of 0266) stack saving and vector reading. However, if the address trap interrupt arises before starting execution of the NMI interrupt processing, transition is made to the address trap exception handling. The address to be stacked is the starting address of the NMI interrupt processing. NOP SLEEP instruc- instruction tion pre-fetch pre-fetch NMI interruption Address trap interrupt 0280 0282 * 0284 Address bus 0280 0282 0284 SLEEP Standby execution mode NOP SLEEP NOP SP-2 SPCA SP-2 * Trap setting address Interrupt request signal Figure 26.20 SLEEP Instruction (5) (Standby or Watch Mode Setting) 26.3.9 Competing Interrupt (1) General Interrupt (Interrupt other than NMI) When the ATC interrupt request is made at the timing in (1) (A) against the general interrupt request, the interruption appears to take place in the ATC at the timing earlier than usual, because higher priority is assigned to the ATC interrupt processing (Simultaneous interrupt with the general interrupt has no effect on processing). The address to be stacked is 029E. For comparison, the case where the trap address is set at 02A0 if no general interrupt request was made is shown in (2). The address to be stacked is 02A4. Rev. 0.1, 11/98, page 536 of 975 0296 MOV.B R2L, @Port 029A NOP 029C NOP Set one of these to the 029E NOP 02A0 NOP trap address 02A2 NOP 02A4 NOP Start of general MOV NOP instruc- Data instruction tion read pre-fetch pre-fetch (1) Data write interrupt processing NOP NOP instruc- instruction tion pre-fetch pre-fetch Range of start of ATC interrupt processing Address bus 0296 0298 029A Port MOV execution 029C 029E 02A0 SP-2 SP-4 Vector Vector NOP NOP execu- execution tion General Interrupt request signal (A) Interrupt request signal 0296 MOV.B R2L, @Port 029A NOP 029C NOP 029E NOP 02A0 NOP Trap address 02A2 NOP 02A4 NOP Address to be stacked (2) MOV NOP instruc- Data instruction read tion pre-fetch pre-fetch Data write NOP NOP NOP NOP NOP instruc- instruc- instruc- instruc- instruction tion tion tion tion pre-fetch pre-fetch pre-fetch pre-fetch pre-fetch Start of ATC interrupt processing Address bus 0296 0298 029A Port MOV execution 029C 029E 02A0 02A2 02A4 02A6 SP-2 NOP NOP NOP NOP NOP execu- execu- execu- execu- execution tion tion tion tion Interrupt request signal Figure 26.21 Competing Interrupt (General Interrupt) Rev. 0.1, 11/98, page 537 of 975 (2) In case of NMI When the NMI interruption request is made at the timing in (1) (A) against the ATC interrupt request, the interrupt appears to take place in NMI at the timing earlier than usual, because higher priority is assigned to the NMI interrupt processing. The ATC interrupt processing starts after fetching the instruction at the starting address of the NMI interrupt processing. The address to be stacked is 02E0 for the NMI and 340 for the ATC. When the ATC interrupt request is made at the timing in (2) (B) against the NMI interrupt request, the ATC interrupt processing starts after fetching the instruction at the starting address of the NMI interrupt processing. The address to be stacked is 02E6 for the NMI and 0340 for the ATC. Rev. 0.1, 11/98, page 538 of 975 Figure 26.22 Competing Interrupt (In Case of NMI) Address bus (1) 02DC 02DE 02E0 NOP NOP NOP instruc- instruc- instruction tion tion pre-fetch pre-fetch pre-fetch 02E2 NMI interrupt processing NOP instruction pre-fetch SP-2 SP-4 Vector Vector Vector 0340 Start of ATC interrupt processing 0342 SP-6 SP-8 Vector Start of ATC interrupt processing ATC interrupt request signal NMI interrupt request signal Address bus (2) ATC interrupt request signal NMI interrupt request signal 02DC 02DE 02E0 02E2 02E4 02E6 NOP NOP NOP NOP NOP NOP instruc- instruc- instruc- instruc- instruc- instruction tion tion tion tion tion pre-fetch pre-fetch pre-fetch pre-fetch pre-fetch pre-fetch (A) NOP NOP execu- execution tion (B) 02E8 NOP instruction pre-fetch SP-2 SP-4 Vector Vector Vector 0340 NMI interrupt processing NMI vector read 02DC 02DE 02E0 02E2 02E4 02E6 02E8 : : 0340 NOP (1) Set to the trap address NOP NOP NOP NOP (2) Set one of these to NOP the trap address NOP : : The starting address of NMI interrupt 0342 Start of ATC Interrupt processing Rev. 0.1, 11/98, page 539 of 975 Rev. 0.1, 11/98, page 540 of 975 Section 27 Servo Circuits 27.1 Overview 27.1.1 Functions Servo circuits for a video cassette recorder are included on-chip. The functions of the servo circuits can be divided into four groups, as listed in table 27.1. Table 27.1 Servo Circuit Functions Group Function Description (1) Input and output circuits CTL I/O amplifier Gain variable input amplifier Output amplifier with rewrite mode Duty accuracy: 502% (Zero cross type comparator) Overlap input available: Three-level input method, DFG noise mask function V compensation, field detection, external signal sync, V sync when in REC mode, REF30 signal output to outside Head-switching signals, FIFO 20 stages Compatible with DFG counter soft-reset Chroma-rotary/head-amplifier switching output CFGDuty compensation input DFG, DPG separation/overlap input Reference signal generators HSW timing generator (2) Error detectors (3) Phase and gain compensation (4) Other circuits Four-head high-speed switching circuit for special playback 12-bit PWM Improved speed of carrier frequency Frequency division circuit With CFG mask, no CFG for phase or CTL mask Sync detection circuit Noise count, field discrimination, Hsync compensation, Hsync detection noise mask Drum speed error Lock detector function, pause at the counter detector overflow, R/W error latch register, limiter function Drum phase error Latch signal selectable, R/W error latch register detector Capstan speed error Lock detector function, pause at the counter detector overflow, R/W error latch register, limiter function Capstan phase error R/W error latch register detector X-value adjustment and (Separate setting available) tracking adjustment circuit Digital filter computation Computations performed automatically by circuit hardware Output gain variable: x 2 to x 64 (exponents of 2) -1 (Partial write in Z (high-order 8 bits) available) Additional V signal circuit Valid when in special playback CTL circuit Duty discrimination circuit, CTL head R/W control, compatible with wide aspect Rev. 0.1, 11/98, page 541 of 975 27.1.2 Block Diagram Figure 27.1 shows a block diagram of the servo circuits. PPG0 to 7/ (P70 to 77) PPG0 to 7/ (P70 to 77) PR0 to 7/ (P60 to 67) PR0 to 7/ (P60 to 67) EXTTRG Csync 4-head special playback controller Sync detector OSCH COMP(PS2) C.ROTARY(PS0) H.Amp SW(PS1) Additional V pulse generator Vpulse System clock VD REC:ON Res Drum system reference signal Capstan system reference signal XE:ON Head-switch timing generator AUDIOFF VIDEOFF ADTRIG DPG(PS3) Phase error detector Noise Det. Ep Digital filter DFG Speed error detector Es + Digital filter PWM + Gain up. CA P PWM PWM Gain up. Frequency divider CFG Speed error detector DVCFG2 DVCFG + Digital filter A/D converter CREF DRM PWM REF30P(PB:30Hz,REC:1/2VD) (HSW) + Es SV2(P83) ( ) EXCTL(PS4) ) DVCTL Internal signal monitor controller SV1(P82) ( ) REF30,REF30X,CREF, CTLMONI,DVCFG, DFG,DPG,DFG,etc Timer X1 Timer L Timer R REC PB.ASM Frequency divider CTLFB PB.CTL -+ CTL Amp -+ Gain control by register setting -+ CTL Head + Phase error detector Ep Digital filter (NTSC) PB. ASM REC (PAL) REF30X VISS circuit (Duty deter- DutyI/O minator) X-value adjustment REC-CTL generator (Assemble recording) REC-CTL CTL Head - EXCAP(P81) Figure 27.1 Block Diagram of Servo Circuits Rev. 0.1, 11/98, page 542 of 975 AN pins 27.2 Servo Port 27.2.1 Overview This LSI is equipped with seventeen pins dedicated to servo module and twenty-five dualpurpose pins used also for general-purpose port. It has also built-in input amplifier to amplify CTL signals, CTL output amplifier, CTL Schmitt comparator, and CFG zero cross type comparator. The CTL input amplifier allows gain adjustment by software. DFG and DPG signals, which are the signals to control the drum, allows selection between separate or overlap input. SV1 and SV2 pins allows to output to monitor the inside signals of the servo section. The signals to be output can be selected out of eight kinds of the signals. See section 27.2.5 (4), Servo Monitor Control Register (SVMCR). 27.2.2 Block Diagram (1) DFG and DPG input circuits The DFG and DPG input pins have on-chip Schmit circuits. Figure 27.2 shows the input circuits of DFG and DPG. DPG SW DFG DFG DPG DPG Res+LPM DPG SW Figure 27.2 Input Circuit of DFG and DPG Rev. 0.1, 11/98, page 543 of 975 (2) CFG Input Circuit CFG input pin has built-in an amplifier and a zero cross type comparator. Figure 27.3 shows the input circuit of CFG. + BIAS P250 VREF REF CFGCOMP - M250 F/F S CFGCOMP O R stp CFG + VREF + - CFG Res+ModuleSTOP Figure 27.3 CFG Input Circuit (3) CTL Input Circuit CTL input pin has built-in an amplifier. Figure 27.4 shows the input circuit of CTL. AMPON (PB-CTL) AMPSHORT (REC-CTL) CTLGR3 to 1 CTLFB CTLGR0 - + + - - + PB-CTL(+) PB-CTL(-) CTL(-) CTL(+) CTLREF CTLBias CTLFB CTLAmp(o) CTLSMT(i) Note Note: Be sure to set a capacitor between CTLAmp (o) and CTLSMT (i) Figure 27.4 CTL Input Circuit Rev. 0.1, 11/98, page 544 of 975 27.2.3 Pin Configuration Table 27.2 shows the pin configuration of servo section. P6n, P7n, P80 to P38 and PS1 to PS4 are general-purpose ports. As for P6, P7 and P8, see section 10, I/O Port. Table 27.2 Pin Configuration Name Abbrev. I/O Function Servo Vcc pin VCC (SV) Input Power source pin for servo section Servo Vss pin VSS (SV) Input Power source pin for servo section Audio head switching pin Audio FF Output Audio head switching signal output Video head switching pin Video FF Output Video head switching signal output Capstan mix pin CAPPWM Output 12-bit PWM square wave output Drum mix pin DRMPWM Output 12-bit PWM square wave output Additional V pulse pin Vpulse Output Additional V signal output Color rotary signal output pin C.Rotar/PS0 Output, I/O Control signal output port for processing color signals/general-purpose port Head amplifier switching pin H.Amp. SW/ PS1 Output, I/O Pre-amplifier output selection signal input/general-purpose port Compare signal input pin COMP/PS2 Input, I/O Pre-amplifier output result signal input/generalpurpose port CTL (+) I/O pin CTL (+) I/O CTL signal input/output CTL (-) I/O pin CTL (-) I/O CTL signal input/output CTL Bias input pin CTLBias Input CTL primary amplifier bias supply CTL Amp (O) output pin CTLAMP (O) Output CTL amplifier output CTL SMT (i) input pin CTLSMT (I) Input CTL Schmitt amplifier input CTL FB input pin CTLFB Input CTL amplifier high-range characteristics control CTL REF output pin CTLREF Output CTL amplifier reference voltage output Capstan FG amplifier input pin CFG Input CFG signal amplifier input Drum FG input pin DFG Input DFG signal input Drum PG input pin DPG/PS3 Input, I/O DPG signal input/general-purpose port External CTL signal input pin EXCTL/PS4 Input, I/O External CTL signal input/general-purpose port Complex sync signal input pin Csync Input, I/O Complex sync signal input External reference signal input pin P80/EXTTRG I/O, input General-purpose port/external reference signal input External capstan signal input pin P81/EXCAP I/O, input General-purpose port/external capstan signal input Servo monitor signal output pin 1 P82/SV1 I/O, output General-purpose port/servo monitor signal output Servo monitor signal output pin 2 P83/SV2 I/O, output General-purpose port/servo monitor signal output PPG output pin P7n/PPGn I/O, output General-purpose port/PPG output RTP output pin P6n/RPn I/O, output General-purpose port/RTP output Rev. 0.1, 11/98, page 545 of 975 27.2.4 Register Configuration Table 27.3 shows the register configuration of the servo port section. Table 27.3 Register Configuration Name Abbrev. R/W Size Initial Value Address Servo port mode register SPMR R/W Byte H'40 H'FD0A0 Servo control register SPCR W Byte H'E0 H'FD0A1 Servo data register SPDR R/W Byte H'E0 H'FD0A2 Servo monitor control register SVMCR R/W Byte H'C0 H'FD0A3 CTL gain control register CTLGR R/W Byte H'C0 H'FD0A4 27.2.5 Register Descriptions (1) Servo port mode register (SPMR) Bit : Initial value : R/W : 7 CTLSTOP 6 -- 0 R/W 1 -- 5 4 3 CFGCOMP EXCTLON DPGSW 0 R/W 0 R/W 0 R/W 2 COMP 1 H.Amp.SW 0 C.Rot 0 R/W 0 R/W 0 R/W An register to switch the servo port/general-purpose port, and the CFG input system. SPMR is an 8-bit read/write register. The bit 6 is a reserve bit; writing in it is invalid. If read is attempted, an undetermined value is read out. It is initialized to H'40 by a reset or stand-by. Bit 7: CTLSTOP Bit (CTLSTOP) Controls whether the CTL circuits is operated of stopped. Bit 7 CTLSTOP Description 0 CTL circuits operates 1 CTL circuits stops operation (Initial value) Bit 6: Reserved This bit is reserved. It cannot be written of read. If a read was attempted, an undetermined value is read out. Rev. 0.1, 11/98, page 546 of 975 Bit 5: CFG Input System Switching Bit (CFGCOMP) Selects whether the CFG input signal system is set to the zero cross type comparator system or digital signal input system. Bit 5 CFGCOMP Description 0 CFG signal input system is set to the zero cross type comparator system (Initial value) 1 CFG signal input system is set to the digital signal input system Bit 4: EXCTL Pin Switching Bit (EXCTLON) Selects whether EXCTL/PS4 pin is used as EXCTL input pin or PS4 (general-purpose I/O pin). Bit 4 EXCTLON Description 0 EXCTL/PS4 pin functions as EXCTL input pin 1 EXCTL/PS4 pin functions as PS4 I/O (Initial value) Bit 3: DPG Pin Switching Bit (DPGSW) Selects the drum control system input signals (DFG, DPG) as separate or overlapped inputs. Bit 3 DPGSW Description 0 Drum control system inputs are separate inputs (DPG/PS3 pin functions as DPG input pin) 1 Drum control system inputs are overlapped inputs (DPG/PS3 pin functions as PS3 input pin) (Initial value) Bit 2: COMP Pin Switching Pin (COMP) Selects whether COMP/PS2 pin is used as COMP input pin or PS2 (general-purpose I/O pin). Bit 2 COMP Description 0 COMP/PS2 pin functions as COMP input pin 1 COMP/PS2 pin functions as PS2 I/O pin (Initial value) Rev. 0.1, 11/98, page 547 of 975 Bit 1: H.Amp SW Pin Switching Pin (H.Amp.SW) Selects whether H.Amp SW/PS1 pin is used as H.Amp SW output pin or PS1 (general-purpose I/O pin). Bit 1 H.Amp.SW Description 0 H.Amp SW/PS1 pin functions as H.Amp SW output pin 1 H.Amp SW/PS1 pin functions as PS1 I/O pin (Initial value) Bit 0: C.Rotary Pin Switching Bit (C.Rot) Selects whether C.Rotary/PS0 pin is used as C.Rotary output pin or PS0 (general-purpose I/O pin). Bit 0 C.Rot Description 0 C.Rotary/PS0 pin functions as C.Rotary output pin 1 C.Rotary/PS0 pin functions as PS0 I/O pin (Initial value) (2) Servo Control Register (SPCR) Bit : 7 -- 6 -- 5 -- 4 SPCR4 3 SPCR3 2 SPCR2 1 SPCR1 0 SPCR0 Initial value : R/W : 1 -- 1 -- 1 -- 0 W 0 W 0 W 0 W 0 W Controls input and output of each pin (PS4 to PS0) for each bit when the servo port/generalpurpose port dual-purpose pin is used as general-purpose port. If SPCR is set to 1, the corresponding PS4 to PS0 pins function as output pins; if cleared to 0, they function input pins. Setting of SPCR and SPDR are valid if the corresponding pins are set to general-purpose I/O by SPMR. SPCR is a 8-bit write-only register. If a read was attempted, an undetermined value is read out. Bits 7 to 5 are reserved bits. Writes are disabled. SPCR is initialized to H'E0 by a reset or stand-by. Bit n SPCRn Description 0 PSn pin functions as input 1 PSn pin functions as output Rev. 0.1, 11/98, page 548 of 975 (Initial value) (3) Servo Data Register (SPDR) Bit : 7 -- 6 -- 5 -- 4 SPDR4 3 SPDR3 2 SPDR2 1 SPDR1 0 SPDR0 Initial value : R/W : 1 -- 1 -- 1 -- 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Stores the data of each pins (PS4-PS0) when servo port/general-purpose dual- purpose pin is used as general-purpose port. If the port is accessed to read when SPCR is 1 (output), SPDRn value is read directly. Accordingly, this register is not affected by the state of the pin. If the port is accessed to read when SPCR is 0 (input), the state of the pin is read out. SPDR is a 8-bit read/write register. Bits 7-5 are reserved. No write in it is valid. If a read was attempted, the state of the pin is read out. SPCR is initialized to H'E0 by reset or stand-by. (4) Servo Monitor Control Register (SVMCR) Bit : 7 -- 6 -- Initial value : R/W : 1 -- 1 -- 5 4 3 2 1 0 SVMCR5 SVMCR4 SVMCR3 SVMCR2 SVMCR1 SVMCR0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Selects the monitor signal output to SV1 and SV2 pins when P82/SV1 pin is used as SV1 monitor output pin or when P83/SV2 pin is used as SV2 monitor output pin. SVMCR is an 8-bit read/write register. Bits 7 and 6 are reserved. Writes are disabled. If a read was attempted, an undetermined value is read out. It is initialized to H'C0 by a reset or stand-by. Bit 5 Bit 4 Bit 3 SVMCR5 SVMCR4 SVMCR3 Description 0 0 0 Outputs REF30 signal to SV2 output pin 1 Outputs CAPREF30 signal to SV2 output pin 1 0 Outputs CREF signal to SV2 output pin 1 Outputs CTLMONI signal to SV2 output pin 0 0 Outputs DVCFG signal to SV2 output pin 1 Outputs CFG signal to SV2 output pin 0 Outputs DFG signal to SV2 output pin 1 Outputs DPG signal to SV2 output pin 1 1 (Initial value) Rev. 0.1, 11/98, page 549 of 975 Bit 2 Bit 1 Bit 0 SVMCR2 SVMCR1 SVMCR0 Description 0 0 0 Outputs REF30 signal to SV1 output pin 1 Outputs CAPREF30 signal to SV1 output pin 0 Outputs CREF signal to SV1 output pin 1 Outputs CTLMONI signal to SV1 output pin 0 Outputs DVCFG signal to SV1 output pin 1 Outputs CFG signal to SV1 output pin 0 Outputs DFG signal to SV1 output pin 1 Outputs DPG signal to SV1 output pin 1 1 0 1 (Initial value) (5) CTL Gain Control Register (CTLGR) Bit : 7 -- 6 -- 5 CTLE/A 4 CTLFB 3 CTLGR3 2 CTLGR2 1 CTLGR1 0 CTLGR0 Initial value : R/W : 1 -- 1 -- 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Sets CTLFB switch in CTL amplifier circuit to on/off and CTL amplifier gain. CTLGR is an 8-bit read/write register. Bits 7 and 6 are reserved. No write in it is valid. If a read was attempted, an undetermined value is read out. It is initialized to H'C0 by a reset or stand-by. Bit 7 to 6: Reserved Reserved bits; writes are disabled. If read was attempted, an undetermined value is read out. Bit 5: CTL Selection Bit (CTLE/$) Controls whether the amplifier output or EXCTL is used as the CTLP signal supplied to CTL circuit. Bit 5 CTLE/$ Description 0 AMP output 1 EXCTL Rev. 0.1, 11/98, page 550 of 975 (Initial value) Bit 4: SW Bit of the Feedback Section of CTL Amplifier (CTLFB) Turning on/off the SW of the feedback section allows adjustment of gain. See figure 27.4 CTL Input Circuit. Bit 4 CTLFB Description 0 Turns off CTLFB SW 1 Turns on CTLFB SW (Initial value) Bits 3 to 0: CTL Amplifier Gain Setting Bits (CTLGR3 to 0) Sets the output gain of CTL amplifier. Bit 3 Bit 2 Bit 1 Bit 0 CTLGR3 CTLGR2 CTLGR1 CTLGR0 CTL output gain 0 0 0 0 35.0 dB 1 37.5 dB 0 40.0 dB 1 42.5 dB 0 45.0 dB 1 47.5 dB 0 50.0 dB 1 52.5 dB 0 55.0 dB 1 57.5 dB 0 60.0 dB 1 62.5 dB 0 65.0 dB* 1 67.5 dB* 0 70.0 dB* 1 72.5 dB* 1 1 0 1 1 0 0 1 1 0 1 Note: * (Initial value) With a setting of 65.0 dB or more, the CTLAMP is in a very sensitive status. When configuring the set board, be concerned about countermeasure against noise around the control head signal input port. Also, thoroughly set the filter between the CTLAMP and the CTLSMT. Rev. 0.1, 11/98, page 551 of 975 27.2.6 DFG/DPG Input Signals DFG and DPG signals allows either of separate or overlapped input. If the latter was selected (DPGSW = 1), take care in the input levels of DFG and DPG. Figure 27.5 shows DFG/DPG input signals. DPG DPG Schmitt level 3.45/3.55 VIL/VIH DFG DFG Schmitt level 1.85/1.95 VIL/VIH (1) DPG/DFG separate input (DPGSW=0) DPG Schmitt level DFG Schmitt level DFG/DPG (2) DPG/DFG overlapped input (DPGSW=1) Figure 27.5 DFG/DPG Input Signals 27.3 Reference Signal Generators 27.3.1 Overview The reference signal generators consist of REF30 signal generator and CREF signal generator and create the reference signals (REF30 and CREF signals) used in phase comparison, etc. REF30 signal is used to control the phase of the drum and capstan. CREF signal is used if the reference signal to control the phase of capstan cannot be shared with REF30 signal in REC mode. Each signal generator consists of a 16-bit counter which has the servo clock s/2 (or s/4) as its clock source, a reference period register and a comparator. The value set in the reference period register should be 1/2 of the desired reference signal period. Rev. 0.1, 11/98, page 552 of 975 s = fosc/2 s/4 s/2 RCS W W Reference period buffer 1 (16 bit) Reference period register 1 (16 bit) Comparator (16 bit) Counter (16 bit) REF30 counter register (16 bit) R/W Internal bus External frequency signal (EXTTRG) Field VD detection signal Dummy read Match Mask OD/EV W Internal bus W REX REC/PB ASM PBREC FDS R/W Toggle Clear PB VST W W V noise detection signal REF30 REF30P Video FF W CVS Edge detection VNA Edge detection , VEG W 27.3.2 Block Diagram Figure 27.6 shows the block diagram of REF30 signal generator. Figure 27.7 shows that of CREF signal generator. Figure 27.6 REF30 Signal Generator Rev. 0.1, 11/98, page 553 of 975 PB(ASM) REC@ Q S Counter clear R s/2 DVCFG2 Counter (16 bit) s/4 Clear Match Comparator (16 bit) Edge detection Toggle CREF Reference period register 2 (16 bit) RCS Reference period buffer 2 (16 bit) CRD Dummy read W W W Internal bus s = fosc/2 Figure 27.7 Block Diagram of CREF Signal Generator 27.3.3 Register Configuration Table 27.4 shows the register configuration of the reference signal generators. Table 27.4 Register Configuration Name Abbrev. R/W Size Initial Value Address Reference period mode register RFM W Byte H'00 H'FD096 Reference period register 1 RFD W Word H'FFFF H'FD090 Reference period register 2 CRF W Word H'FFFF H'FD092 REF30 counter register RFC R/W Word H'0000 H'FD094 Reference period mode register 2 RFM2 R/W Byte H'FE H'FD097 Rev. 0.1, 11/98, page 554 of 975 27.3.4 Register Descriptions (1) Reference Period Mode Register (RFM) Bit : Initial value : R/W : 7 RCS 6 VNA 5 CVS 4 REX 3 CRD 2 OD/EV 1 VST 0 VEG 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W RFM is an 8-bit write-only register which determine the operational state of the reference signal generators. If a read is attempted, an undetermined value is read out. It is initialized to H'00 by a reset, stand-by or module stop. RFM is accessible by byte access only. If accessed by a word, its operation is not assured. Bit 7: Clock Source Selection Bit (RCS) Selects the clock source supplied to the counter. (s = fosc/2) Bit 7 RCS Description 0 s/2 1 s/4 (Initial value) Bit 6: Mode Selection Bit (VNA) Selects whether the transition to free-run operation when the REF30 signals are being generated in sync with the VD signals in REC mode is controlled automatically by the V noise detection signal, which has been detected by the sync signal detection circuit, or it is controlled manually by software. Bit 6 VNA Description 0 Manual mode 1 Auto mode (Initial value) Rev. 0.1, 11/98, page 555 of 975 Bit 5: Manual Selection Bit (CVS) Selects whether the REF30 signals are generated in sync with VD or they are operated free-run in the manual mode (VNA = 0). (No selection is not reflected in PB mode.) Bit 5 CVS Description 0 Sync with VD 1 Free-run operation (Initial value) Bit 4: External Signals Sync Selection Bit (REX) Selects whether the REF30 signals are generated in sync with VD or in free-run or in sync with the external signals. (Valid in both PB and REC modes.) Bit 4 REX Description 0 VD signals or free-run 1 Sync with external signals (Initial value) Bit 3: DVCFG2 Sync Selection Bit (CRD) Selects whether the reset timing in the CREF signals generation is immediately after switching over of mode or it is in sync with the DVCFG2 signals immediately after the switching over. Bit 3 CRD Description 0 On switching over of mode 1 In sync with DVCFG2 signals (Initial value) Bit 2: ODD/EVEN Edge Switching Selection Bit (OD/EV) Selects whether REF30P signals are generated by ODD of the field signals or EVEN when in REC. Bit 2 OD/EV Description 0 Generated at the rising edge (EVEN) of the field signals 1 Generated at the falling edge (ODD) of the field signals Rev. 0.1, 11/98, page 556 of 975 (Initial value) Bit 1: Video FF Counter Set (VST) Selects whether the REF30 counter register value is set on or off by the Video FF signal when the drum phase is in FIX on in the PB mode. Bit 1 VST Description 0 Counter set off by Video FF signal 1 Counter set on by Video FF signal (Initial value) Bit 0: Video FF Edge Selection Bit (VEG) Selects the edge at which REF30 counter is set (VST = 1) by the Video FF signal. Bit 0 VEG Description 0 Set at the rising edge of Video FF signal 1 Set at the falling edge of Video FF signal (Initial value) (2) Reference Period Register 1 (RFD) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 REF15 REF14 REF13 REF12 REF11 REF10 REF9 REF8 REF7 REF6 REF5 REF4 REF3 REF2 REF1 REF0 Initial value : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : W W W W W W W W W W W W W W W W The reference period register 1 (RFD) is a buffer register which generates the reference signals for playback (REF30), VD compensation for recording and the reference signals for freerunning. It is an 16-bit write-only register accessible by a word only. If a read is attempted, an undetermined value is read out. The value set in RFD should be 1/2 of the desired reference signal period. Care is required when VD is unstable, such as when the field is weak (Synchronization with VD cannot be acquired if a value less than 1/2 is set when in REC). When data is written in RFD, it is stored in the buffer once, and then fetched into RFD by a match signal of the comparator. (The data which generates the reference signal is updated from time to time by the match signal.) An enforced write, such as initial setting, etc., should be done by a dummy read of RFD. If a byte-write in RFD is attempted, no operation is assured. RFD is initialized to H'FFFF by a reset, stand-by, or module stop. Use bit 7 (ASM) and bit 6 (REC/PB) in the CTL mode register (CTLM) in the CTL circuit to switch between record and playback modes. Use bit 4 (CR/RF bit) in the capstan phase error detection control register (CPGCR) to switch between REF30 and CREF for capstan phase control. Rev. 0.1, 11/98, page 557 of 975 (3) Reference Period Register 2 (CRF) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 REF15 REF14 REF13 REF12 REF11 REF10 REF9 REF8 REF7 REF6 REF5 REF4 REF3 REF2 REF1 REF0 Initial value : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : W W W W W W W W W W W W W W W W The reference period register 2 (CRF) is an 16-bit write-only buffer register which generates the reference signals to control the capstan phase (CREF). CRF is accessibly by a word only; If a read is attempted, an undetermined value is read out. The value set in CRF should be 1/2 of the desired reference signal period. When data is written in CRF, it is stored in the buffer once, and then fetched into CRF by a match signal of the comparator. (The data which generates the reference signal is updated from time to time by the match signal.) An enforced write, such as initial setting, etc., should be done by a dummy read of CRF. If a byte-write in CRF is attempted, no operation is assured. CRF is initialized to H'FFFF by a reset, stand-by, or module stop. Use bit 4 (CR/RF bit) in the capstan phase error detection control register (CPGCR) to switch between REF30 and CREF for capstan phase control. (See section 27.9, Capstan Phase Error Detector) (4) REF30 Counter Register (RFC) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFC15 RFC14 RFC13 RFC12 RFC11 RFC10 RFC9 RFC8 RFC7 RFC6 RFC5 RFC4 RFC3 RFC2 RFC1 RFC0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The REF30 counter register (RFC) is a register which determines the initial value of the free-run counter when it generates REF30 signals when in playback. When data is written in RFC, its value is written in the counter by a match signal of the comparator. If the bit 1 (VST) of RFM is set to 1, the counter is set by the Video FF signal when the drum phase is in FIX ON. The counter setting by the Video FF signal should be done by setting RFM's bit 1 (VST) and bit 0 (VEG). Don't set the RFC value at a value greater than 1/2 of the reference period register 1 (RFD). RFC is a read/write register. If a read is attempted, the value of the counter is read out. If a byte-access is attempted, no operation is assured. RFC is initialized to H'0000 by a reset, standby, or module stop. Rev. 0.1, 11/98, page 558 of 975 (5) Reference Period Mode Register 2 (RFM2) Bit : 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 FDS Initial value : R/W : 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 0 R/W The REM2 is an 8-bit read/write register which determines the operational state of the reference signal generators. Bits 7 to 1 are reserved. If a read is attempted, an undetermined value is read out. It is initialized to H'FE by a reset, stand-by or module stop. RFM2 is a byte access-only register; if accessed by a word, no operation is secured. Bits 7 to 1: Reserved Bits 7 to 1 are reserved; no write is valid. If a read is attempted, an undetermined value is read out. Bit 0: Field Selection Bit (FDS) Determines whether selection between ODD or EVEN is made for the field signals when PB mode was switched over to REC mode, or these signals are synchronized with VD signals within phase error of 90 immediately after the switching over. Bit 0 FDS Description 0 Generated by the VD signal of ODD or EVEN selected 1 Generated by the VD signal within mode transition phase error of 90 (Initial value) Rev. 0.1, 11/98, page 559 of 975 27.3.5 Description of Operation (1) Operation of REF30 Signal Generators The REF30 signal generators generate the reference signals required to control the phase of the drum and capstan. To generate REF30 signals, set the half-period value to the reference period register 1 (RFD) corresponding to the 50% duty cycle. When in playback, REF30 signals are generated by operating REF30 signal generator in free-run. The generator has the external signals synchronization function built-in, and if the bit 4 (REX) of the reference period mode register (RFM) is set to 1, it generates REF30 signals from external signals (EXTTGR). In record mode, the reference signals are generated from the VD signal generated in the sync detector. Any VD drop-out caused by weak field intensity, etc., is compensated by a set value of RFD. To cope with the VD noises, the generator performs automatically the VD masking for a time period about 75% of the RFD setting after REF30 signal was changed due to VD. In record mode, the generation of the reference signals either by VD or free-run operation can be controlled automatically or by software, using the V noise detection signal detected in the sync signal detection circuit. Select which is used by setting bit 6 (VNA) or 5 (CVS) of RFM. The phase of the toggle output of the REF30 signal is cleared to L level when the signal mode transits from PB to REC (ASM). Also the frame servo function can be set, allowing to control the phase of REF30 signals with the field signal detected in the sync signals detection circuit. Use bit 2 (OD/EV) of RFM for such control. See section 27.13.5(2), CTL Mode Register (CTLM) as for switching over between PB, ASM and REC. (2) Operation of the Mask Circuit The REF30 signal generators have toggle mask circuit and counter mask (counter set signal mask) circuit built-in. Each mask circuit masks irregular VD signals which may occur when the VD signal is unstable because of weak field intensity, etc., in record mode. The toggle mask and counter mask circuits mask the VD automatically for about 75% of double the time period set in the reference period register 1 (RFD) after VD signal was detected (see figure 27.9). If a VD signal dropped out and V was compensated, the toggle mask circuit begins masking. The counter mask circuit does not do so for about 25% of time period. If VD signal was detected during such time period, it does masking for about 75% of the time period. If not detected, it does for the same time period after V was compensated (see figures 27.10 and 27.11). Rev. 0.1, 11/98, page 560 of 975 (3) Timing of the REF30 Signal Generation Figures 27.8, 27.9, 27.10, 27.11 and 27.12 show the timing of the generation of REF30 and REF30P signals. Counter set Counter set Counter set Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) REF30 REF30P Figure 27.8 REF30 Signals in Playback Mode Rev. 0.1, 11/98, page 561 of 975 Field signal VD Selected VD (OD/EV=0) Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Toggle mask Masking period Counter mask (clear signal mask) Masking period About 75% REF30 REF30P HSW Drum phase counter Sampling T Sampling Sampling Figure 27.9 Generation of Reference Signal in Record Mode (Normal Operation) Rev. 0.1, 11/98, page 562 of 975 Field signal Drop-out of V VD Selected VD (OD/EV=0) Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Toggle mask Cleared Cleared Masking period About 75% Counter mask (clear signal mask) Cleared About 75% About 75% Masking period About 75% About 25% REF30 REF30P HSW Drum phase counter T Sampling Sampling Sampling Figure 27.10 Generation of the Reference Signal when in REC (V Dropped Out) Rev. 0.1, 11/98, page 563 of 975 Field signal Dislocation of V VD Selected VD (OD/EV=0) Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Toggle mask Cleared Cleared Masking period About 75% Counter mask (clear signal mask) Cleared About 75% Masking period About 75% About 75% REF30 REF30P HSW Drum phase counter Sampling T Sampling Sampling Figure 27.11 Generation of the Reference Signal when in REC (V Dislocated) Rev. 0.1, 11/98, page 564 of 975 External sync signal Cleared Cleared Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Reset REF30 REF30P Figure 27.12 Generation of REF30 Signal by the External Sync Signal (4) CREF Signal Generator CREF signal generator generates CREF signal which is the reference signal to control the phase of capstan. To generate CREF signals, set the half-period value to the reference period register 2 (CRF). If the set value match to the counter value, a toggle waveform is generated corresponding to the 50% duty cycle, and a one-shot pulse signal is output at the rising edge of the waveform. The counter of CREF signal generator is initialized to H'0000 and the phase of the toggle is cleared to L level at the mode transition of PB (ASM) to REC. The timing of clearing is selectable between immediately after the transition from PB (ASM) to REC and the timing of DVCFG2 after the transition. Use bit 3 (CRD) of the reference period mode register (RFM) for the selection. In the capstan phase error detection circuit, either REF30 signal or CREF signal can be selected for the reference signal. Use either of them according to the use of the system. Use CREF signal to control the phase of the capstan at a period which is different from the period used to control the phase of the drum. As for the switching between REF30 and CREF in the capstan phase control, see section 27.9.4(3) Capstan Phase Error Detection Control Register (CPGCR). Rev. 0.1, 11/98, page 565 of 975 (5) Timing chart of the CREF signal generation Figures 27.13, 27.14 and 27.15 show the generation of CREF signal. Cleared Cleared Cleared Value set in reference period register 2 (CRF) Counter Toggle signal CREF Figure 27.13 Generation of CREF Signal Cleared Cleared Cleared Value set in reference period register 2 (CRF) Counter REC/PB Toggle signal Time period when CRF is set CREF PB(ASM) REC Figure 27.14 CREF Signal when PB REC (when CRD Bit = 0) Rev. 0.1, 11/98, page 566 of 975 Cleared Cleared Cleared Value set in reference period register 2 (CRF) Counter REC/PB DVCFG2 Toggle signal Time period when CRF is set CREF PB(ASM) REC Figure 27.15 CREF Signal when PB is Switched to REC (when CRD Bit = 1) Rev. 0.1, 11/98, page 567 of 975 Figures 27.16 and 27.17 show REF30 (REF30P) when PB is switched to REC. PB REC(ASM) Field signal VD (except in PB) Selected VD* (OD/EV=0) REC/PB Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Cleared Cleared Toggle mask Masking period Counter mask (Clear signal mask) Masking period Cleared Cleared About 75% Cleared REF30 REF30P * When in the field discrimination mode Figure 27.16 Generation of the Reference Signal when PB is Switched to REC (1) Rev. 0.1, 11/98, page 568 of 975 PB REC(ASM) Field signal VD (except in PB) Selected VD (OD/EV=0) REC/PB Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Cleared Cleared Cleared Toggle mask Masking period Counter mask (Clear signal mask) Masking period About 50% Cleared REF30 REF30P Figure 27.17 Generation of the Reference Signal when PB is Switched to REC (2) Rev. 0.1, 11/98, page 569 of 975 Figures 27.18, 27.19, 27.20 and 27.21 show REF30 (REF30P) when PB is switched to REC (where FDS bit = 1). PB REC(ASM) REC/PB VD (except in PB) Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Cleared Toggle mask Masking period Counter mask (Clear signal mask) Masking period Cleared Cleared REF30 REF30P FDS bit = "1" Figure 27.18 Generation of the Reference Signal when PB is Switched to REC where RFD Bit is 1 (1) Rev. 0.1, 11/98, page 570 of 975 PB REC(ASM) REC/PB VD (except in PB) Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Toggle mask Masking period Counter mask (Clear signal mask) Masking period 25% 25% 25% REF30 REF30P FDS bit = "1" Figure 27.19 Generation of the Reference Signal when PB is Switched to REC where RFD Bit is 1 (when VD Signal is Not Detected) (2) Rev. 0.1, 11/98, page 571 of 975 PB REC(ASM) REC/PB VD (except in PB) Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Cleared Toggle mask Masking period Counter mask (Clear signal mask) Masking period Cleared Max. 25% REF30 REF30P FDS bit = "1" Figure 27.20 Generation of the Reference Signal when PB is Switched to REC where RFD Bit is 1 (3) Rev. 0.1, 11/98, page 572 of 975 PB REC(ASM) REC/PB VD (except in PB) Value set in reference period register 1 (RFD) Counter Value set in REF30 counter register (RFC) Cleared Toggle mask Masking period Counter mask (Clear signal mask) Masking period Cleared Max. 25% REF30 REF30P FDS bit = "1" Figure 27.21 Generation of the Reference Signal when PB is Switched to REC where RFD Bit is 1 (4) Rev. 0.1, 11/98, page 573 of 975 27.4 HSW (Head-switch) Timing Generator 27.4.1 Overview The HSW timing generator consists of one 5-bit counter and one 16-bit counter, matching circuit, and two 31-bit 10-stage FIFOs. The 5-bit counter counts the DFG pulses following a DPG pulse. Each of them determines the timing to reset the 16-bit timer for each field. The matching circuit compares the timing data in the most significant 16 bits of FIFO with the 16-bit timer, and controls the output of pattern data set in the least significant 15 bits of FIFO. The 16-bit timer is a timer clocked by a s/4 clock source, and can be used as a PPG (Programmable Pattern Generator) as well as a free-running counter. If used as a free-running counter, it is cleared by overflow of the 19-bit FRC. Accordingly, two FRCs operate in sync. Rev. 0.1, 11/98, page 574 of 975 DPG FRCOVF NCDFG EDG R/W , Edge detector R R/W * HSM1 R/W R W CCLR * DFCRA Cleared R/W FGR20FF * HSM2 R/W FRT Comparator (5 bits) Comparator (5 bits) Counter (5 bits) DFG reference register 2 * DFCRB FLA,B EMPA,B OVWA,B CLRA,B R DFG reference register 1 * DFCRA W W * DFCTR HSW loop stage number setting register * HSLP R/W R/W W CKSL * DFCRA 15 bits Cleared R FTCTR (16 bits) Timer counter (16 bits) R/W ISEL1 * HSM2 STRIG R/W VFF/NFF * HSM2 VD PB Capture FIFO output selector & output buffer 16 bits FIFO 1 (31 bits x 10 stages) W 15 bits FIFO output pattern register 2 * FPDRB * DFCRA W ISEL2 AudioFF IRRHSW2 VideoFF IRRHSW1 ADTRG Vpulse Mlevel NHSW HSW P77 to 70 (PPG output) FIFO2 (31 bits x 10 stages)@ 16 bits 15 bits * FTPRB W FIFO timing pattern register 2 Compare circuit (16 bits) Internal bus W FIFO output pattern register 1 * FPDRA 16 bits W FIFO timing pattern register 1 * FTPRA s/8 s/4 CLK HSM2 R Internal bus LOP SOFG OFG R/W Control circuit 27.4.2 Block Diagram Figure 27.22 show a block diagram of the HSW timing generator. Figure 27.22 Composition of the HSW Timing Generator Rev. 0.1, 11/98, page 575 of 975 The HSW timing generator is composed of the elements shown in table 27.5. Table 27.5 Composition of the HSW Timing Generator Element Function HSW mode register 1 (HSM1) Confirmation/determination of this circuits' operating status HSW mode register 2 (HSM2) Confirmation/determination of this circuits' operating status HSW loop stage number setting register (HSLP) Setting of number of loop stages in loop mode FIFO output pattern register 1 (FPDRA) Output pattern register of FIFO1 FIFO output pattern register 2 (FPDRB) Output pattern register of FIFO2 FIFO timing pattern register 1 (FTPRA) Output timing register of FIFO1 FIFO timing pattern register 2 (FTPRB) Output timing register of FIFO2 DFG reference register 1 (DFCRA) Setting of reference DFG edge for FIFO1 DFG reference register 2 (DFCRB) Setting of reference DFG edge for FIFO2 FIFO timer capture register (FTCTR) Capture register of timer counter DFG reference count register (DFCTR) DFG edge count FIFO control circuit Controls FIFO status DFG count compare circuit (x2) Detection of match between DFCR and DFG counters 16-bit timer counter 16-bit free-run timer counter 31-bit x 20 stage FIFO First In First Out data buffer 31-bit FIFO data buffer Data storing buffer for the first stage of FIFO 16-bit compare circuit Detection of match between timer counter and FIFO data buffer FPDRA and FPDRB are intermediate buffers; an FTPRA and FTPRB write results in simultaneous writing of all 31 bits to the FIFO. The FIFO has two 31-bit x 10-stage data buffers, its operating status being controlled by HSM1 and HSM2. Data is stored in the 31-bit data buffer. The values of FTPRA, FTPRB and the timer counter are compared, and if they match, the 15-bit pattern data is output to each function. AudioFF, VideoFF and PPG (P70 to P77) are pin outputs, ADTRG is the A/D converter hardware start signal, Vpulse and Mlevel signals are the signals to generate the additional V pulses, and HSW and NHSW signals are the same with VideoFF signals used for the phase control of the drum. The 16-bit timer counter is initialized by the overflow in the free-run mode (FRC 19-bit free-run timer when FRT bit of HSWM = 1), or by a signal indicating a match between DFCRA, DFCRB and the DFG counter in DFG reference mode. Rev. 0.1, 11/98, page 576 of 975 27.4.3 Register Configuration Table 27.6 shows the register configuration of the HSW timing generator. Table 27.6 Register Configuration Name Abbrev. R/W Size Initial Value Address HSW mode register 1 HSM1 R/W Byte H'30 H'FD060 HSW mode register 2 HSM2 R/W Byte H'00 H'FD061 HSW loop stage number setting register HSLP R/W Byte Undetermined H'FD062 FIFO output pattern register 1 FPDRA W Word Undetermined H'FD064 FIFO timing pattern register 1* FTPRA W Word H'FFFF H'FD066 FIFO output pattern register 2 FPDRB W Word Undetermined H'FD068 FIFO timing pattern register 2 FTPRB W Word H'FFFF H'FD06A DFG reference register 1* DFCRA W Byte Undetermined H'FD06C DFG reference register 2 DFCRB W Byte Undetermined H'FD06D FIFO timer capture register* FTCTR R Word H'0000 H'FD066 DFG reference count register* DFCTR R Byte H'E0 H'FD06C Note: 27.4.4 * FTPRA and FTCTR, as well as DFCRA and DFCTR, are allocated to the same addresses. Register Descriptions (1) HSW Mode Register 1 (HSM1) Bit : Initial value : R/W : 7 FLB 6 FLA 5 EMPB 4 EMPA 3 OVWB 2 OVWA 1 CLRB 0 CLRA 0 R 0 R 1 R 1 R 0 R/(W)* 0 R/(W)* 0 R/W 0 R/W Note: * Only 0 can be written HSM1 is a register which confirms and determines the operational state of the HSW timing generator. HSM1 is an 8-bit register. Bits 7 to 4 are read-only bits, and write is disabled. All the other bits accept both read and write. It is initialized to H'30 by a reset or stand-by. Rev. 0.1, 11/98, page 577 of 975 Bit 7: FIFO2 Full Flag (FLB) When the FLB bit is 1, it indicates that the timing pattern data and the output pattern data of FIFO2 are full. If a write is attempted in this state, the write operation becomes invalid, an interrupt is generated, the OVWB flag (bit 3) is set to 1, and the write data is lost. Wait until space becomes available in the FIFO2, then write again. Bit 7 FLB Description 0 FIFO2 is not full, and can accept data input 1 FIFO2 is full (Initial value) Bit 6: FIFO1 Full Flag (FLA) When the FLA bit is 1, it indicates that the timing pattern data and the output pattern data of FIFO1 are full. If a write is attempted in this state, the write operation becomes invalid, an interrupt is generated, the OVWA flag (bit 2) is set to 1, and the write data is lost. Wait until space becomes available in the FIFO1, then write again. Bit 6 FLA Description 0 FIFO1 is not full, and can accept data input 1 FIFO1 is full (Initial value) Bit 5: FIFO2 Empty Flag (EMPB) Indicates that FIFO2 has no data, or that all the data has been output in single mode. Bit 5 EMPB Description 0 FIFO2 contains data 1 FIFO2 contains no data (Initial value) Bit 4: FIFO1 Empty Flag (EMPA) Indicates that FIFO1 has no data, or that all the data has been output in single mode. Bit 4 EMPA Description 0 FIFO1 contains data 1 FIFO1 contains no data Rev. 0.1, 11/98, page 578 of 975 (Initial value) Bit 3: FIFO2 Overwrite Flag (OVWB) If a write is attempted when the timing pattern data and the output pattern data of FIFO2 are full (FLB bit = 1), the write operation becomes invalid, an interrupt is generated, the OVWB flag is set to 1, and the write data is lost. Wait until space becomes available in the FIFO2, then write again. Write 0 to clear the OVWB flag, because it is not cleared automatically. Bit 3 OVWB Description 0 Normal operation 1 Indicates that a write in FIFO2 was attempted when FIFO2 was full. Clear this flag by 0 writing (Initial value) Bit 2: FIFO1 Overwrite Flag (OVWA) If a write is attempted when the timing pattern data and the output pattern data of FIFO1 are full (FLA bit = 1), the write operation becomes invalid, an interrupt is generated, the OVWA flag is set to 1, and the write data is lost. Wait until space becomes available in the FIFO1, then write again. Write 0 to clear the OVWA flag, because it is not cleared automatically. Bit 2 OVWA Description 0 Normal operation 1 Indicates that a write in FIFO1 was attempted when FIFO1 was full. Clear this flag by 0 writing (Initial value) Bit 1: FIFO2 Pointer Clear (CLRB) Clears the FIFO2 write position pointer. After 1 is written, the bit immediately reverts to 0. Writing 0 in this bit has no effect. Bit 1 CLRB Description 0 Normal operation 1 Clears the FIFO2 pointer (Initial value) Rev. 0.1, 11/98, page 579 of 975 Bit 0: FIFO1 Pointer Clear (CLRA) Clears the FIFO1 write position pointer. After 1 is written, the bit immediately reverts to 0. Writing 0 in this bit has no effect. Bit 0 CLRA Description 0 Normal operation 1 Clears the FIFO1 pointer (Initial value) (2) HSW Mode Register 2 (HSM2) Bit : 7 FRT 6 FGR20FF 5 LOP 4 EDG 3 ISEL1 2 SOFG 1 OFG 0 VFF/NFF Initial value : R/W : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R/W HSM2 is a register which confirms and determines the operational state of the HSW timing generator. HSM2 is an 8-bit register. Bits 6 and 1 are read-only bits, and write is disabled. Bit 0 is a writeonly bit, and if a read is attempted, an undetermined value is read out. All the other bits accept both read and write. It is initialized to H'00 by a reset or stand-by. Bit 7: Free-run Bit (FRT) Selects whether timing is matched to the DPG counter and timer, or to FRC. Bit 7 FRT Description 0 5-bit DFG counter + 16-bit timer 1 16-bit FRC (Initial value) Bit 6: FRG2 Clear Stop Bit (FGR2OFF) Nullifies the clearing of the counter by the DFG register 2. The FIFO group, including both FIFO1 and FIFO2, is available. Bit 6 FGR2OFF Description 0 Validates the clearing of the16-bit counter by DFG register 2 1 Nullifies the clearing of the16-bit counter by DFG register 2 Rev. 0.1, 11/98, page 580 of 975 (Initial value) Bit 5: Mode Selection Bit (LOP) Selects the output mode of FIFO. If the loop mode is selected, LOB3 to LOB0 bits and LOA3 to LOA0 bits become valid. If the LOP bit is rewritten, the pointer which counts the writing position of FIFO is cleared. In this case, the ultimate output date is kept. Bit 5 LOP Description 0 Single mode 1 Loop mode (Initial value) Bit 4: DFG Edge Selection Bit (EDG) Selects the edge by which to count DFG. Bit 4 EDG Description 0 Counts by the rising edge of DFG 1 Counts by the falling edge of DFG (Initial value) Bit 3: Interrupt Selection Bit (ISEL1) Selects the factor which causes an interrupt. (IRRHSW1) Bit 3 ISEL1 Description 0 Generates an interrupt request by the rising edge of the STRIG signal of FIFO (Initial value) 1 Generates an interrupt request by the matching signal of FIFO Rev. 0.1, 11/98, page 581 of 975 Bit 2: FIFO Output Group Selection Bit (SOFG) Selects whether 20 stages of FIFO1 + FIFO2 or only 10 stages of FIFO1 are used. If 20-stage output mode is used in single mode, data write in FIFO1 and FIFO2 is required. Monitor the output FIFO group flag (OFG) and control it by software. Output all the data of FIFO2 after all the data of FIFO1 was output. Repeat this step again. If 10-stage output mode is used, the data of FIFO2 is not reflected. Rewriting the SOFG bit 0 1 0 initializes the control signal of the FIFO output stage to the FIFO1 side. Bit 2 SOFG Description 0 20-stage output of FIFO1 + FIFO2 1 10-stage output of FIFO1 only (Initial value) Bit 1: Output FIFO Group Flag (OFG) Indicates the FIFO group which is outputting. Bit 1 OFG Description 0 Pattern is being output by FIFO1 1 Pattern is being output by FIFO2 (Initial value) Bit 0: Output Switching Bit Between VideoFF and NallowFF (VFF/NFF) Switches the signal output to VideoFF pin. Bit 0 VFF/NFF Description 0 VideoFF output 1 NallowFF output (Initial value) (3) HSW Loop Stage Number Setting Register (HSLP) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 LOB3 LOB2 LOB1 LOB0 LOA3 LOA2 LOA1 LOA0 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W Rev. 0.1, 11/98, page 582 of 975 HSLP sets the number of the loop stages when the HSW timing generator is in loop mode. It is valid if bit 5 (LOP) of HSM2 is 1. Bits 7 to 4 set the number of FIFO2 stages. Bits 3 to 0 set the number of FIFO1 stages. HSLP is an 8-bit read/write register. It is not initialized by a reset, stand-by or module stop, accordingly be sure to set the number of the stages when the loop mode is used. Bits 7 to 4: FIFO2 Stage Number Setting Bits (LOB3 to LOB0) Set the number of FIFO2's stages in loop mode. They are valid only if the loop mode is set (LOP bit of HSM2 is 1). HSM2 HSLP Bit 5 Bit 7 Bit 6 Bit 5 Bit 4 LOP LOB3 LOB2 LOB1 LOB0 Description 0 * * * * Single mode 1 0 0 0 0 Only 0th stage of FIFO2 is output 1 0th and 1st stages of FIFO2 are output 0 0th to 2nd stages of FIFO2 are output 1 0th to 3rd stages of FIFO2 are output 0 0th to 4th stages of FIFO2 are output 1 0th to 5th stages of FIFO2 are output 0 0th to 6th stages of FIFO2 are output 1 0th to 7th stages of FIFO2 are output 0 0th to 8th stages of FIFO2 are output 1 0th to 9th stages of FIFO2 are output 0 Setting prohibited 1 1 0 1 1 0 0 1 (Initial value) 1 1 0 0 1 1 0 1 Note: * Don't care. Rev. 0.1, 11/98, page 583 of 975 Bits 3 to 0: FIFO1 Stage Number Setting Bits (LOA3 to LOA0) Set the number of FIFO1's stages in loop mode. They are valid only if the loop mode is set (LOP bit of HSM2 is 1). HSM2 HSLP Bit 5 Bit 3 Bit 2 Bit 1 Bit 0 LOP LOA3 LOA2 LOA1 LOA0 Description 0 * * * * Single mode 1 0 0 0 0 Only 0th stage of FIFO1 is output 1 0th and 1st stages of FIFO1 are output 0 0th to 2nd stages of FIFO1 are output 1 0th to 3rd stages of FIFO1 are output 0 0th to 4th stages of FIFO1 are output 1 0th to 5th stages of FIFO1 are output 0 0th to 6th stages of FIFO1 are output 1 0th to 7th stages of FIFO1 are output 0 0th to 8th stages of FIFO1 are output 1 0th to 9th stages of FIFO1 are output 0 Setting prohibited 1 1 0 1 1 0 0 1 1 1 0 0 1 1 0 1 Note: * Don't care. Rev. 0.1, 11/98, page 584 of 975 (Initial value) (4) FIFO Output Pattern Register 1 (FPDRA) Bit : 15 -- 14 ADTRGA Initial value : R/W : 1 -- * W * W 7 PPGA7 6 PPGA6 * W * W Bit : Initial value : R/W : 13 12 STRIGA NallowFFA 11 VFFA 10 AFFA 9 VpulseA 8 MlevelA * W * W * W * W * W 5 PPGA5 4 PPGA4 3 PPGA3 2 PPGA2 1 PPGA1 0 PPGA0 * W * W * W * W * W * W FPDRA is a buffer register for the output patter register of FIFO1. The output pattern data written in FPDRA is written at the same time to the position pointed by the buffer pointer of FIFO1. Be sure to write the output pattern data in FPDRA before writing it in FTPRA. FPDRA is an 16-bit write-only register. Only a word access is valid. If a byte access is attempted, resulting operation is not assured. No read is valid. If a read is attempted, an undetermined value is read out. It is not initialized by a reset, stand-by or module stop, accordingly be sure to write data before use. (5) FIFO Output Pattern Register 2 (FPDRB) Bit : 15 -- 14 ADTRGB Initial value : R/W : 1 -- * W * W 7 PPGB7 6 PPGB6 * W * W Bit : Initial value : R/W : 13 12 STRIGB NallowFFB 11 VFFB 10 AFFB 9 VpulseB 8 MlevelB * W * W * W * W * W 5 PPGB5 4 PPGB4 3 PPGB3 2 PPGB2 1 PPGB1 0 PPGB0 * W * W * W * W * W * W FPDRB is a buffer register for the output patter register of FIFO2. The output pattern data written in FPDRB is written at the same time to the position pointed by the buffer pointer of FIFO2. Be sure to write the output pattern data in FPDRB before writing it in FTPRB. FPDRB is an 16-bit write-only register. Only a word access is valid. If a byte access is attempted, resulting operation is not assured. No read is valid. If a read is attempted, an undetermined value is read out. It is not initialized by a reset, stand-by or module stop, accordingly be sure to write data before use. Rev. 0.1, 11/98, page 585 of 975 (6) FIFO Timing Pattern Register 1 (FTPRA) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : * * * * * * * * * * * * * * * * R/W : W W W W W W W W W W W W W W W W FTPRA is a register to write the timing pattern data of FIFO1. The timing data written in FPDRA is written at the same time to the position pointed by the buffer pointer of FIFO1 together with the buffer data of FPDRA. FTPRA is an 16-bit write-only register. Only a word access is valid. If a byte access is attempted, resulting operation is not assured. It is not initialized by a reset, stand-by or module stop, accordingly be sure to write data before use. Note: Its address is shared with the FIFO timer capture register (FTCTR). Accordingly, the value of FTCTR is read out if a read is attempted. (7) FIFO Timing Pattern Register 2 (FTPRB) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : * * * * * * * * * * * * * * * * R/W : W W W W W W W W W W W W W W W W FTPRB is a register to write the timing pattern data of FIFO2. The timing data written in FPDRB is written at the same time to the position pointed by the buffer pointer of FIFO2 together with the buffer data of FPDRB. FTPRB is an 16-bit write-only register. Only a word access is valid. If a byte access is attempted, resulting operation is not assured. It is not initialized by a reset, stand-by or module stop, accordingly be sure to write data before use. (8) DFG Reference Register 1 (DFCRA) Bit : Initial value : R/W : 7 ISEL2 6 CCLR 5 CKSL 4 DFCRA4 3 DFCRA3 0 W 0 W 0 W * W * W 2 1 DFCRA2 DFCRA1 * W * W 0 DFCRA0 * W DFCRA is a register which determines the operation of the HSW timing generator as well as the starting point of the timing of FIFO1. DFCRA is an 8-bit write-only register. It is not initialized by a reset, stand-by or module stop, accordingly be sure to write data before use. Rev. 0.1, 11/98, page 586 of 975 Note: Its address is shared with the DFG reference counter register (DFCTR). Accordingly, the value of DFCTR is read out in the low-order five bits if a read is attempted. Bit 7: Interrupt Selection Bit (ISEL2) Selects the factor which causes an interrupt. (IRRHSW2) Bit 7 ISEL2 Description 0 Generates an interrupt request by the clear signal of the 16-bit timer counter (Initial value) 1 Generates an interrupt request by the VD signal in PB mode Bit 6: DFG Counter Clear Bit (CCLR) Enforces clearing of the counter which counts DFG by software. Writing 1 returns 0 immediately. Writing 0 causes no effect on operation. Bit 6 CCLR Description 0 Normal operation 1 Clears the DFG counter (Initial value) Bit 5: 16-bit Counter Clock Source Selection Bit (CKSL) Selects the clock source of the 16-bit counter. Bit 5 CKSL Description 0 s/4 1 s/8 (Initial value) Bits 4 to 0: FIFO1 Output Timing Setting Bits (DFCRA4 to DFCRA0) Determines the starting point of the timing of FIFO1. The initial value is undetermined. Be sure to set a value after a reset or stand-by. It is valid only if bit 7 (FRT bit) of HSM2 is 0. Rev. 0.1, 11/98, page 587 of 975 (9) DFG Reference Register 2 (DFCRB) Bit : 7 -- 6 -- 5 -- 4 DFCRB4 3 DFCRB3 Initial value : R/W : 1 -- 1 -- 1 -- * W * W 2 1 DFCRB2 DFCRB1 * W 0 DFCRB0 * W * W DFCRB is a register which determines the starting point of the timing of FIFO2. DFCRB is an 8-bit write-only register. If a read is attempted, an undetermined value is read out. Bits 7 to 5 are reserved. No write is valid. If a read is attempted, an undetermined value is read out. It is not initialized by a reset, stand-by or module stop, accordingly be sure to write data before use. It is valid only if bit 7 (FRT bit) of HSM2 is 0. (10) FIFO Timer Capture Register (FTCTR) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : R R R R R R R R R R R R R R R R FTCRT is a register to display the count of the 16-bit timer. FTCRT is an 16-bit read-only register. It stores the counter value if VD signal was detected in PB mode. Only a word access is accepted. If a byte access is attempted, resulting operation is not assured. It is initialized to H'0000 by a reset or stand-by. Note: Its address is shared with the FIFO timing pattern register 1 (FTPRA). Accordingly, if a write is attempted, the value is written in FTPRA. (11) DFG Reference Count Register (DFCTR) Bit : 7 -- 6 -- 5 -- 4 DFCTR4 3 DFCTR3 2 DFCTR2 1 DFCTR1 0 DFCTR0 Initial value : R/W : 1 -- 1 -- 1 -- * R * R * R * R * R DFCTR is a register to count the DFG pulses. DFCTR is an 8-bit read-only register. Bits 7 to 5 are reserved. If a read is attempted, an undetermined value is read out. It is initialized to H'E0 by a reset or stand-by. Note: Its address is shared with the DFG reference register 1 (DFCRA). Accordingly, if a write is attempted, the value is written in DFCRA. Rev. 0.1, 11/98, page 588 of 975 27.4.5 Description of Operation The 5-bit DFG counter takes counts by the edges of DFG. The 16-bit timer operates with s/4 or s/8 (s = fosc/2) as clock source. The DFG counter is cleared by the DPG's rise or when 1 was written in the CCLR bit. If the FRT bit of HSM2 is 1, clearing of the 16-bit timer by the DFG counter is invalid. The matching circuit compares the timing pattern value of FIFO with the counter value, and if they match, it generates the pattern data for the next stage as its output signal. At this time, the information of the output pattern is sent to VIDEO FF, AUDIO FF, port and A/D converter. The port data of FIFO can be used as the head-switching signal of Audio Head, Video Head, and Flying Erase Head. ADTRG signal is a hardware trigger signal of A/D converter. If ADTRG was changed from 0 to 1, AD conversion is started. See section 25, A/D Converter for more information. Vpulse and Mlevel signals are for additional V signals. See section 27.12, Additional V Signals for more information. HSW and NHSW signals are used to control the phases of drum. Switching of the drum head is available in the normal mode and slow mode. STRIG signal generates an interrupt by pattern data. If STRIG is selected by ISEL1, it generates an interrupt by changing the pattern data from 0 to 1. FIFO has two modes, i.e. single mode and loop mode. It can operates in 20 stages in total in FIFO1 and FIFO2. In the single mode, the output pattern data is output as the timing data matches. The data, once output, is lost, and the internal pointer is decremented by 1. When the last data was output, it stops operation until data is written again. When it is used in the 20-stage output mode, total output of FIFO1 and FIFO2 is repeated in turn. Accordingly, in the control of data writing, writing in FIFO1 and FIFO2 has to be controlled by software. If 10-stage output mode is used, only FIFO1 is operated. In loop mode, the output pattern cycles repeatedly from stage 0 through the final stage selected in the HSW loop number setting register. As in single mode, the output pattern data is output each time the timing data matches. In loop mode the FIFO data is retained, but when the loop mode is active, data can be rewritten for each FIFO group. Write data after clearing the FIFO group which is outputting no data. Writing has to be completed before the rewritten FIFO group starts operation. Partial rewriting in the loop is not possible, because the write pointer is outside the loop stages. If the timing of generation is based on DFG, the counter of FIFO1 is reset at the timing given by the DFG reference register 1, and the counter reset of FIFO2 is done by the DFG reference register 2. However, if the 16-bit counter is reset only by the DFG reference register 1, set 1 as the output stop bit (FGR2OFF) of FIFO2.In this case, continuous values should be set as the timing patterns for FIFO1 and FIFO2. The first stage of FIFO2 is output after the last stage of FIFO1 has been output. Figures 27.23 and 27.24 show examples of the timing waveform and its operation of the HSW timing generator. Rev. 0.1, 11/98, page 589 of 975 Figure 27.23 Example of Timing Waveform of HSW (when DFG is 12 Shots) Rev. 0.1, 11/98, page 590 of 975 0 1 2 tA2 tA1 3 4 5 6 Example of setting: DFCR=H'02, DFCR=H'08, HSLP=H'21, DFG falling edge Clear B Clear A A.FF V.FF DFG DPG 7 8 tB1 tA3 9 10 11 0 1 2 tA1 Internal bus W W W FPDRA FPDRB FTPRB FTPRA FIFO1 W tA0 PA9 tB0 PB9 tA5 tA4 tA3 tA2 tA1 PA4 PA3 PA2 PA1 PA0 tB5 tB4 tB3 tB2 tB1 PB4 PB3 PB2 PB1 PB0 FIFO2 Output select buffer Output select @@ buffer Comparator s/4 Timer counter Output pattern data Figure 27.24 Example of Operation of the HSW Timing Generator Rev. 0.1, 11/98, page 591 of 975 (1) Example of operation in single mode (20 stages of FIFO used) (a) Set to single mode (LOP = 0) (b) Write the output pattern data (PA0) to FPDRA. (c) Write the output timing (tA1) to RA. tA1 is written in FIFO1 together with PA0. This initializes the output pattern data to PA0. (d) Repeat the steps in the same way, until PA1, PA2, etc., are set. (e) Write the output pattern data (PB0) to FPDRB. (f) Write the output timing (tB1) to RB. tB1 is written in FIFO2 together with PB0. This initializes the output pattern data to PB0. (g) Repeat these steps in the same way, until PB1, PB2, etc., are set. From (c), the pattern data of PA0 is output. If tA1 matches with the timer counter, the pattern data of PA1 is output. If tA2 matches with the timer counter, the pattern data of PA2 is output. . . . After this sequence is repeated and all the pattern data set in FIFO1 is output, the pattern data of FIFO2 is output. After the pattern data is output the pointer is decremented by 1. Care is required, however, because matching of tA0 is not detected until data is written in FIFO2. Matching of tB0 also is not detected until data is written FIFO1 again. (2) Example of the operation in loop mode (a) Set the number of loop stages in HSLP register (e.g. HSLP = H'44) (b) Write the output pattern data (PA0) to FPDRA. (c) Write the output timing (tA1) to FTPRA. tA1 is written in FIFO1 together with PA0. This initializes the output pattern data to PA0. (d) Repeat the steps in the same way, until PA1, PA2, etc., are set. (e) Write the output pattern data (PB0) to FPDRB. (f) Write the output timing (tB1) to FTPDB. tB1 is written in FIFO2 together with PB0. This initializes the output pattern data to PB0. (g) Repeat the steps in the same way, until PB1, PB2, etc., are set. From (c), the pattern data PA0 is output. If tA1 matches the timer counter, the pattern data PA1 is output. If tA2 matches the timer counter, the pattern data PA2 is output. . . . Rev. 0.1, 11/98, page 592 of 975 If tA4 matches the timer counter, the pattern data PA4 is output. If tA5 matches the timer counter, the pattern data PB0 is output. If tB1 matches the timer counter, the pattern data PB1 is output. . . . If tB4 matches the timer counter, the pattern data PB4 is output. If tB5 matches the timer counter, the pattern data PA0 is output. . . . 27.4.6 Interruption The HSW timing generator generates an interrupt under the following conditions. (1) IRRHSW1 occurred when pattern data was written (OVWA, OVWB = 1) and FIFO was full (FULL). (2) IRRHSW1 occurred when matching was detected and the STRIG bit of FIFO was 1. (3) IRRHSW1 occurred when the values of the 16-bit timer counter and 16-bit timing pattern register matched. (4) IRRHSW2 occurred when the 16-bit timer counter was cleared. (5) IRRHSW2 occurred when a VD signal (capture signal of the timer capture register) was received in PB mode. (2) and (3), as well as (4) and (5), are switched over by ISEL1 and ISEL2. Rev. 0.1, 11/98, page 593 of 975 27.4.7 Cautions (1) When both DFG counter and 16-bit timer counter are operating, the latter is not cleared if input of DPG and DFG signals is stopped. This leads to free-running of the 16-bit timer counter, and periodical detection of matching by the 16-bit timer. In such a case, the period of the output from the HSW timing generator is independent from DPG or DFG. (2) Specify the mode setting bit (LOP) of the HSW mode register 2 (HSM2) immediately before writing the FIFO data. (3) Input the rising edge of DPG and DFG count edge at different timings. If the same timing was input, counting up of DFG and clearing of the DFG counter occurs simultaneously. In this case, the latter will take precedence. This leads to the DFG counter's lag by 1. Figure 27.25 shows the input timing of DPG and DFG. (4) If stop of the drum system is required when FIFO output is being used in the 20-stage output mode, rewrite the SOFG bit of HSM2 register 0 1 0 by software, and initialize the FIFO output stage to the FIFO1 side without fail. Also clear and rewrite the data of FIFO1 and FIFO2. I TP * FG I >(1 state) DPG DFG TP * FG Note: When DFG counter takes count at the rising edges of DFG Figure 27.25 Input Timing of DPG and DFG Rev. 0.1, 11/98, page 594 of 975 27.5 Four-head High-speed Switching Circuit for Special Playback 27.5.1 Overview This four-head high-speed switching circuit generates a color rotary signal (C.Rotary) and headamplifier switching signal (H.Amp SW) for use in four-head special playback. A pre-amplifier output comparison result signal is input from the COMP pin. The signal output to the C,.Rotary pin is a Chroma signal processing control signal. The signal output at the H.Amp SW pin is a pre-amplifier output select signal. To reduce the width of noise bars, the C,.Rotary and H.Amp SW signals are synchronized to the horizontal sync signal (OSCH). OSCH is made by adding supplemented H, which has been separated from Csync signal in the sync signal detector circuit. For more details of OSCH, see section 27.15, Sync Signal Detector. If C.rotary, H.Amp SW or COMP pin does not require this circuit to configure a VCR system, it can be used as an I/O port. 27.5.2 Block Diagram Figure 27.26 shows the block diagram of this circuit. Internal bus W W CRH HAH W * CHCR SIG3 to 0 * CHCR OSCH (Synchronization) Synchronization control C.Rotary Decoding circuit H.Amp SW COMP Narrow.FF RTP0 Video.FF V/N * CHCR HSWPOL * CHCR W W Internal bus Figure 27.26 Four-Head High-Speed Switching Circuit for Special Playback Rev. 0.1, 11/98, page 595 of 975 27.5.3 Pin Configuration Table 27.7 summarizes the pin configuration of the high-speed switching circuit used in fourhead special playback. They can also be used as I/O port when not in use. See section 27.2, Servo Port. Table 27.7 Pin Configuration Name Abbrev. I/O Function Compare input pin COMP Input Input of pre-amplifier output result signal Color rotary signal output pin C.Rotary Output Output of chroma processing control signal Head amplifier switch pin H.Amp SW Output Output of pre-amplifier output select signal 27.5.4 Register Description (1) Register Configuration Table 27.8 shows the register configuration of the high-speed switching circuit used in fourhead special playback. Table 27.8 Register Configuration Name Abbrev. R/W Size Initial Value Address Special playback control register CHCR W Byte H'00 H'FD06E (2) Special Playback Control Register (CHCR) Bit : Initial value : R/W : 7 V/N 6 HSWPOL 5 CRH 4 HAH 3 SIG3 2 SIG2 1 SIG1 0 SIG0 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W The special-effects control register (CHCR) is a 8-bit write-only register. It cannot be read. It is initialized to H'00 by if resetting, standby or module stop is implemented. Rev. 0.1, 11/98, page 596 of 975 Bits 7: HSW Signal Select Bit (V/N) Selects HSW signal to be used at special playback. Bit 7 V/N Description 0 Video FF signal output 1 Narrow FF signal output (Initial value) Bit 6: COMP Polarity Select Bit (HSWPOL) Selects polarity of COMP signal. Bit 6 HSWPOL Description 0 Positive 1 Negative (Initial value) Bit 5: C.Rotary Synchronization Control Bit (CRH) Synchronize C.Rotary signal with OSCH signal. Bit 5 CRH Description 0 Synchronous 1 Asynchronous (Initial value) Rev. 0.1, 11/98, page 597 of 975 Bit 4: H.AmpSW Synchronization Control Bit (HAH) Synchronize H.AmpSW signal with OSCH signal. Bit 4 HAH Description 0 Synchronous 1 Asynchronous (Initial value) Bits 3 to 0: Signal Control (SIG3 to SIG0) These bits, combined with the state of the COMP input pin, control the outputs at the C.Rotary and H.AmpSW pins. Bit 3 Bit 2 Bit 1 Bit 0 Output pins SIG3 SIG2 SIG1 SIG0 C.Rotary H.Amp SW 0 0 * * L L 1 0 0 HSW L 1 HSW H 0 L HSW 1 H +6: * HSW EX-OR COMP COMP 1 1 0 1 Note: * 0 1 HSW EX-NOR COMP COMP 0 HSW E-OR RTP0 RTP0 1 HSW EX-NOR RTP0 RTP0 Don't care. Rev. 0.1, 11/98, page 598 of 975 (Initial value) 27.6 Drum Speed Error Detector 27.6.1 Overview Drum speed error control operates so as to hold the drum at a constant revolution speed, by measuring the period of the DFG signal. A digital counter detects the speed deviation from a preset value. The speed error data is processed and added to phase error data in a digital filter. This filter controls a pulse-width modulated (PWM) output, which controls the revolution speed and phase of the drum. The DFG input signal from the drum motor is a sine wave with a small amplitude. The DFG input signal is amplified by an input amplifier, then reshaped into a square wave by a reshaping circuit, and sent to the speed error detector as the DFG signal. The speed error detector uses the system clock to measure the period of the DFG signal, and detects the deviation from a preset data value. The preset data is the value that would result from measuring the DFG signal period with the clock signal if the drum motor were running at the correct speed. The error detector operates by latching a counter value when it detects an edge of the DFG signal. The latched count provides 16 bits of speed error data for the digital filter to operate on. The digital filter processes and adds the speed error data to phase error data from the drum phase control system, then sends the result to the pulse-width modulator as drum error data. Rev. 0.1, 11/98, page 599 of 975 Rev. 0.1, 11/98, page 600 of 975 Error data (16 bits) To DFU ADDFGN NCDFG s s/2 s/4 s/8 DFCS1,0 W DRF R F/F Q S * DFPR Preset data (16 bits) W R/W * DFVCR R/W R/W DFESS * DFUCR * DFRLOR Lock range detector * DFRUDR Lock range data 2 (16 bits) W Internal bus * DFVCR R/W Internal bus W Lock range data 1 (16bit) DFEFON Error data limitter control circuit DFOVF OVF * DFER Error data (16bit) Latch Counter (16bit) Preset * FGCR Edge detector , * DFVCR R/W Rock 2 up Rock 1 up S R Clear Q F/F * DFVCR Lock counter (2 bits) R/W UDF DF-R/UNR IRRDRM2 IRRDRM1 * DFVCR R To DROCKON DFU DFRCS1,0 * DFRVCR DPCNT S F/F Q R (R)/W 27.6.2 Block Diagram Figure 27.27 shows a block diagram of the dram speed error detector. Figure 27.27 Block Diagram Of The Dram Speed Error Detector 27.6.3 Register Configuration Table 27.9 shows the register configuration of the drum speed error detector. Table 27.9 Register Configuration Name Abbrev. R/W Size Initial Value Address Specified DFG speed preset data register DFPR W Word H'0000 H'FD030 DFG speed error data register DFER R/W Word H'0000 H'FD032 DFG lock UPPER data register DFRUDR W Word H'7FFF H'FD034 DFG lock LOWER data register DFRLDR W Word H'8000 H'FD036 Drum speed error detection control register DFVCR R/W Byte H'00 H'FD038 27.6.4 Register Descriptions (1) Specified DFG Speed Preset Data Register (DFPR) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : W W W W W W W W W W W W W W W W The specified DFG speed preset data is set in DFPR. When the data is written, a 16-bit preset data is sent to the preset circuit. The preset data is referenced to H'8000*, and can be calculated from the following equation. Specified DFG speed preset data =H'8000- ( s/n DFG frequency -2) s: Servo clock frequency (fosc/2) in Hz DFG frequency: In Hz The constant 2 is the presetting interval (see Figure 27.28). s/n Clock source of selected counter DFPR is a 16-bit write-only register, and is accessible by word access only. Byte access gives unassured results. Reads are disabled. DFPR is initialized to H'0000 by a reset, and in standby mode and module stop mode. Rev. 0.1, 11/98, page 601 of 975 Note: * The preset data value is calculated so that the counter will reach H'8000 when the error is zero. When the counter value is latched as error data in the DFG speed error data register (DFER), however, it is converted to a value referenced to H'0000. (2) DFG Speed Error Data Register (DFER) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W Note: * Note that only detected error data can be read. DFER is a register that stores 16-bit DFG speed error data. When the drum motor speed is correct, the data is latched in DFER is H'0000. Negative data will be latched if the speed is too fast, and positive data if the speed is too slow. The DFER value is sent to the digital filter either automatically or by software. DFER is a 16-bit readable/writable register. DFER is accessible by word access only. Byte access gives unassured results. DFER is initialized to H'0000 by a reset, and in standby mode and module stop mode. Refer to the Note in 27.6.4 (1) Specified DFG Speed Preset Data Register (DFPR). (3) DFG Lock UPPER Data Register (DFRUDR) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : W W W W W W W W W W W W W W W W DFRUDR is a register used to set the lock range on the UPPER side when drum speed lock is detected, and to set the limit value on the UPPER side when limiter function is in use. Set a signed data to DFRUDR (bit 15 is a sign-setting bit). When lock is being detected, if the drum speed is detected within the lock range, the lock counter which has been set by DFRCS 1 and 0 bits of DFVCR register counts down. If the set value of DFRCS 1 and 0 matches the number of times of occurrence of locking, the computation of the digital filter in the drum phase system can be controlled automatically. Also, if the DFG speed error data is beyond the DFRUDR value within the limiter function is in use, the DFRUDR value can be used as the data for computation by the digital filter. DFRUDR is an 16-bit write-only register. Only a word access is valid. If a byte access is attempted, operation is not assured. No read is valid. If a read is attempted, an undetermined value is read out. It is initialized to H'7FFF by a reset, stand-by or module-stop. Rev. 0.1, 11/98, page 602 of 975 (4) DFG Lock LOWER Data Register (DFRLDR) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : W W W W W W W W W W W W W W W W DFRLDR is a register used to set the lock range on the LOWER side when drum speed lock is detected, and to set the limit value on LOWER side when limiter function is in use. Set a signed data to DFRLDR (bit 15 is a sign-setting bit). When lock is being detected, if the drum speed is detected within the lock range, the lock counter which has been set by DFRCS 1 and 0 bits of DFVCR register counts down. If the set value of DFRCS 1 and 0 matches the number of times of occurrence of locking, the computation of the digital filter in the drum phase system can be controlled automatically. Also, if the DFG speed error data is under the DFRLDR value when the limiter function is in use, the DFRLDR value can be used as the data for computation by the digital filter. DFRLDR is an 16-bit write-only register. Only a word access is valid. If a byte access is attempted, operation is not assured. No read is valid. If a read is attempted, an undetermined value is read out. It is initialized to H'8000 by a reset, stand-by or module-stop. (5) Drum Speed Error Detection Control Register (DFVCR) Bit : Initial value : R/W : 7 DFCS1 6 DFCS0 5 DFOVF 0 R/W 0 R/W 0 R/(W)*1 4 3 DFRFON DF-R/UNR 0 R/W 0 R 2 DPCNT 1 DFRCS1 0 DFRCS0 0 R/W 0 (R)*2/W 0 (R)*2/W Notes: 1. Only 0 can be written. 2. If read-accessed, the counter value is read out. DFVCR control the operation of drum speed error detection. DFVCR is a read/write 8-bit register. Bit 3 accepts only read, and bit 5 accepts only read and 0 write. It is initialized to H'00 by a reset, stand-by or module-stop. Rev. 0.1, 11/98, page 603 of 975 Bits 7 and 6: Clock Source Selection Bits (DFCS1, DFCS0) DFCS1 and DFCS0 select the clock to be supplied to the counter. (s = fosc/2) Bit 7 Bit 6 DFCS1 DFCS0 Description 0 0 s 1 s/2 0 s/4 1 s/8 1 (Initial value) Bit 5: Counter Overflow Flag (DFOVF) DFOVF flag indicates the overflow of the 16-bit counter. It is cleared by writing 0. Write 0 after reading 1. Also, setting has the highest priority in this flag. If a flag set and 0 write occurs simultaneously, the latter is nullified. Bit 5 DFOVF Description 0 Normal state 1 Indicates that overflow has occurred in the counter (Initial value) Bit 4: Error Data Limit Function Selection Bit (DFRFON) Makes the error data limit function valid. (Limit values are the values set in the lock range data register (DFRUDR, DFRLDR)). Bit 4 DFRFON Description 0 Limit function off 1 Limit function on (Initial value) Bit 3: Drum Lock Flag (DF-R/UNR) Sets a flag if an underflow occurred in the drum lock counter. Bit 3 DF-R/UNR Description 0 Indicates that the drum speed system is not locked 1 Indicates that the drum speed system is locked Rev. 0.1, 11/98, page 604 of 975 (Initial value) Bit 2: Drum Phase System Filter Computation Automatic Start Bit (DPCNT) Sets on the filter computation of the phase system if an underflow occurred in the drum lock counter. Bit 2 DPCNT Description 0 Does not perform the filter computation by detection of the drum lock (Initial value) 1 Set on the filter computation of the phase system when drum lock is detected Bits 1 and 0: Drum Lock Counter Setting Bits (DFRCS1, DFRCS0) Sets the number of times where drum lock has been determined (DFG has been detected in the rage set by the lock range data register). It sets the drum lock flag if it detected the set number of times of occurrence of drum lock. If data is written in DFRCS1 and 0, it is stored in the lock counter. Note: If DFRCS1 or DFRCS0 is read-accessed, the counter value is read out. If bit 3 (drum lock flag) is 1 and the drum lock counter's value is 3, it indicates that the drum speed system is locked. The drum look counter stops until lock is released after underflow. Bit 1 Bit 0 DFRCS1 DFRCS0 Description 0 0 Underflow after lock was detected once 1 Underflow after lock was detected twice 0 Underflow after lock was detected three times 1 Underflow after lock was detected four times 1 (Initial value) Rev. 0.1, 11/98, page 605 of 975 27.6.5 Description of Operation The drum speed error detector detects the speed error based on the reference value set in the DFG specified speed preset register (DFPR). The reference value set in DFPR is preset in the counter by NCDFG signal, and counts down by the selected clock. The timing of the counter presetting and the error data latching can be selected between the rising or falling edge of NCDFG signal. See section 27.14.4, FG Control Register (FGCR). The error data detected is sent to digital filter circuit. The error data is signed binaries. It takes a positive number (+) if the speed is slower than the specified speed, a negative number (-) if the speed is faster, or 0 if it had no error (revolving at the specified speed). Figure 27.28 shows an example of operation to detect the drum speed. (a) Setting the error data limit A limit can be set to the error data sent to the digital filter circuit using the DFG lock data register (DFRUDR, DFRLDR). Set the upper limit of the error data in DFRUDR and the lower limit in DFRLDR, and write 1 in DFRFON bit. If the error data is beyond the limit range, the DFRLDR value is sent if a negative number is latched, or the DFRUDR value is sent if a positive one is latched, as a limit value. Be sure to turn off the limit setting (DERFON = 0) when you set the limit value. If the limit was set with the limit setting on (DERFON = 1), result of computation is not assured. (b) Lock detection If an error data was detected within the lock range set in the lock data register, the drum lock flag (DF-R/UNR) is set by the number of the times of occurrence of locking set by DFRCS1 and 0 bits, and an interrupt is requested (IRRDRM2) at the same time. The number of the occurrence of locking (once to 4 times) can be specified when setting the flag. Use DFRCS1 and 0 bits for this purpose. Also, if bit 5 (DPHA bit) of the drum system digital filter control register (DFIC) is 0 (phased system digital filter computation off) and DPCNT bit is 1, turning on/off of the phase system digital filter computation can be controlled automatically by the status of lock detection. (c) Drum system speed error detection counter The drum system speed error detection counter stops the counter and set the overflow flag (DFOVF) when overflow occurred. At the same time, it generates an interrupt request (IRRDRM1). Clear DFOVF by writing 0 after reading 1. If setting the flag and writing 0 take place simultaneously, the latter is nullified. Rev. 0.1, 11/98, page 606 of 975 (d) Interrupt request IRRDRM1 is generated by the NCDFG signal latch and the overflow of the error detection counter. IRRDRM2 is generated by detection of lock (after the detection of the number of times of setting). NCDFG signal Error data latch signal (DFG ) Preset data load Preset period (2 counts) Specified speed value -value+value Counter Preset value Latch data 0 (no error) Figure 27.28 Example of the Operation of the Drum Speed Error Detection (Selection of the Rising Edge of DFG) Rev. 0.1, 11/98, page 607 of 975 27.6.6 fH Correction in Trick Play Mode In trick play mode, the tape speed changes relative to the video head. This change alters the horizontal sync signal (fH), causing skew. To correct the skew, the drum motor speed must be shifted to a different speed in each trick play mode, so as to obtain the normal horizontal sync frequency. To shift the drum motor speed, software should modify the value written in the DFG preset data register in the speed error detector. This fH correction can be expressed in terms of the basic frequency fF of the drum as follows. fF = N0 x fF0 N0+H (1-n) Legend: n: H: N0: fF0: Speed multiplier (FWD = positive, REV = negative) H alignment (1.5H in standard mode, 0.75H in 2x mode, and 0.5H in 3x mode for VHS and systems; 1H for an 8-mm VCR) Standard H numbers within field Field frequency NTSC: N0 = 262.5, fF0 = 59.94 PAL: N0 = 312.5, fF0 = 50.00 Rev. 0.1, 11/98, page 608 of 975 27.7 Drum Phase Error Detector 27.7.1 Overview Drum phase control must start operating after the drum motor is brought to the correct revolution speed by the speed control system. Drum phase control works as follows in record and playback. Record: Phase is controlled so that the vertical blanking intervals of the recorded video signal will line up along the bottom edge of the tape. Playback: Phase is controlled so as to trace the recorded tracks accurately. A digital counter detects the phase deviation from a preset value. The phase error data is processed and added to speed error data in a digital filter. This filter controls a pulse-width modulated (PWM) output, which controls the rotational phase and speed of the drum. When the error is zero, the PWM circuit outputs a waveform with a 50% duty cycle. The DPG signal from the drum motor is reshaped into a rectangular pulse waveform by a reshaping circuit, and sent to the phase error detector. The phase error detector compares the phase of the DPG pulse (tach pulse), which contains video head phase information, with a reference signal. In the actual circuit, the comparison is carried out by comparing the head-switching (HSW) signal, which is delayed by a counter that is reset by DPG, with a reference signal value. The reference signal is the REF30 signal, which differs between record and playback as follows. Record: Vsync signal extracted from the video signal to be recorded (frame rate signal, actually 1/2 Vsync) Playback: 30 Hz or 25 Hz signal divided from the system clock Rev. 0.1, 11/98, page 609 of 975 Rev. 0.1, 11/98, page 610 of 975 R/W N/V * DPGCR NHSW (Narrow FF) HSW (Video FF) s s/2 s/4 s/8 REF30P DPCS1,0 * DPGCR R/W R/W HSWES * DPGCR , Edge detector S F/F Q R Figure 27.29 Block Diagram of Drum Phase Error Detector R/W Internal bus MSB Error data (4bit) * DPER1 Sequence controller R/W LSB * DPGCR R/(W) R/W DFEPS * DFUCR DPOVF OVF LSB * DPER2 Error data (16bit) Latch Counter (20bit) Preset (16bit) MSB (4bit) * DPPR2 W Preset data W Preset data * DPPR1 Internal bus Error data (20 bits) To DFU IRRDRM3 s = fosc/2 27.7.2 Block Diagram Figure 27.29 shows a block diagram of the drim phse error detector. 27.7.3 Register Configuration Table 27.10 shows the register configuration of the drum phase error detector. Table 27.10 Register Configuration Name Abbrev. R/W Size Initial Value Address Specified drum phase preset data register 1 DPPR1 W Byte H'F0 H'FD03C Specified drum phase preset data register 2 DPPR2 W Word H'0000 H'FD03A Drum phase error data register 1 DPER1 R/W Byte H'F0 H'FD03D Drum phase error data register 2 DPER2 R/W Word H'0000 H'FD03E Drum phase error detection control register DPGCR R/W Byte H'07 H'FD039 27.7.4 Register Descriptions (1) Drum Phase Preset Data Registers (DPPR1, DPPR2) DPPR1 Bit : 7 -- 6 -- 5 -- 4 -- 3 2 1 0 Initial value : R/W : 1 -- 1 -- 1 -- 1 -- 0 W 0 W 0 W 0 W DPPR2 Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : W W W W W W W W W W W W W W W W The 20-bit preset data that defines the specified drum phase is set in DPPR1 and DPPR2. The 20 bits are weighted as follows. Bit 3 of DPPR1 is the MSB, and bit 0 of DPPR2 is the LSB. When data is written to DPPR2, the 20-bit preset data, including DPPR1, is loaded into the preset circuit. Write to DPPR1 first, and DPPR2 next. The preset data is referenced to H'80000*, and can be calculated from the following equation. Rev. 0.1, 11/98, page 611 of 975 Target phase difference = (reference signal frequency/2) - 6.5H DPG phase preset data = H'80000 - (s/n x target phase difference) s: s/n: Servo clock frequency in Hz (fosc/2) Clock source of selected counter DPPR2 is accessible by word access only. Byte access gives unassured results. Reads are disabled. DPPR1 and DPPR2 are initialized to H'F0 and H'0000 by a reset, and in standby mode. Note: * The preset data value is calculated so that the counter will reach H'80000 when the error value is zero. When the counter value is latched as error data in the drum phase error data registers (DPER1 and DPER2), however, it is converted to a value referenced to H'00000. (2) Drum Phase Error Data Registers (DPER1, DPER2) DPER1 Bit : 7 -- 6 -- 5 -- 4 -- 3 2 1 0 Initial value : R/W : 1 -- 1 -- 1 -- 1 -- 0 R*/W 0 R*/W 0 R*/W 0 R*/W DPER2 Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W Note: * Note that only detected error data can be read. DPER1 and DPER2 consist of a 20-bit DPG phase error data register. When the rotational phase is correct, the data H'00000 is latched. Negative data will be latched if the drum leads the correct phase, and positive data if it lags. Values in DPER1 and DPER 2 are transferred to the digital filter circuit. DPER1 and DPER are 20-bit readable/writable registers. When writing data to DPER 1 and DPER2, write to DPER1 first, and then write to DPER2. DPER2 is accessible by word access only. Byte access gives unassured results. DPER1 and DPER2 are initialized to H'F0 and H'0000 by a reset, and in standby mode. See the note on the drum phase preset data registers (DPPR1 and DPPR2) in section 27.7.4 (1). Rev. 0.1, 11/98, page 612 of 975 (3) Drum Phase Error Detection Control Register (DPGCR) Bit : 7 DPCS1 6 DPCS0 5 DPOVF 4 N/V 3 HSWES 2 -- 1 -- 0 -- 0 R/W 0 R/W 0 R/(W)* 0 R/W 0 R/W 1 -- 1 -- 1 -- Initial value : R/W : Note: * Only 0 can be written DPGCR controls the operation of drum phase error detection. DPGCR is an 8-bit read/write register. Bits 2-0 are reserved, bit 5 accepts only read and 0 write. It is initialized to H'07 by a reset or stand-by. Bits 7, 6: Clock Source Selection Bit (DPCS1, DPCS0) Select the clock supplied to the counter. (s = fosc/2) Bit 7 Bit 6 DPCS1 DPCS0 Description 0 0 s 1 1 s/2 0 s/3 1 s/4 (Initial value) Bit 5: Counter Overflow Flag (DPOVF) DPOVF flag indicates the overflow of the 20-bit counter. It is cleared by writing 0. Write 0 after reading 1. Also, setting has the highest priority in this flag. If a flag set and 0 write occurs simultaneously, the latter is nullified. Bit 5 DPOVF Description 0 Normal state 1 Indicates that a overflow has occurred in the counter (Initial value) Bit 4: Error Data Latch signal Selection Bit (N/V) Selects the latch signal of error data. Bit 4 N/V Description 0 HSW (VideoFF) signal 1 NHSW (NallowFF) signal (Initial value) Rev. 0.1, 11/98, page 613 of 975 Bit 3: Edge Selection Bit (HSWES) Selects the edge of the error data latch signal (HSW or NHSW). Bit 3 HSWES Description 0 Latches at the rising edge 1 Latches at the falling edge (Initial value) Bits 2 to 0: Reserved Bits 2 to 0 are reserved. No read or write is valid. 27.7.5 Description of Operation The drum phase error detector detects the phase error based on the reference value set in the Drum specified phase preset data register 1 and 2 (DPPR1, DPPR2). The reference values set in DPPR1 and 2 are preset in the counter by REF30P signal, and counted up by the clock selected. The latch of the error data can be selected between the rising or falling edge of HSW (NHSW). The error data detected in the error data automatic transmission mode (DFEPS bit of DFUCR = 0) is sent to the digital filter circuits automatically. In soft transmission mode (DFEPS bit of DFUCR = 1), the data written in DPER1 and 2 is sent to the digital filter circuit. The error data is signed binary. It takes a positive number (+) if the phase is behind the specified phase, a negative number (-) if in advance of the specified phase, or 0 if it had no phase error (revolving at the specified phase). Figures 27.30 and 27.31 show examples of operation to detect a drum phase error. (a) Drum phase error detection counter The drum phase error detection counter stops the counter when overflow or latch occurred. At the same time, it generates an interrupt request (IRRDRM3), setting the overflow flag (DPOVF) if overflow occurred. Clear DPOVF by writing 0 after reading 1. If setting the flag and writing 0 take place simultaneously, the latter is nullified. (b) Interrupt request IRRDRM3 is generated by the HSW (NHSW) signal latch and the overflow of the error detection counter. Rev. 0.1, 11/98, page 614 of 975 REF30P HSW (NHSW)* Preset Counter Preset Latch Preset value Latch Preset value Note: * Edge selectable Figure 27.30 Drum Phase Control in Playback Mode (HSW Rising Edge Selected) VD Reset Reset Preset Preset REF30P HSW (NHSW)* Counter Latch Preset value Latch Preset value Note: * Edge selectable Figure 27.31 Drum Phase Control in Record Mode (HSW Rising Edge Selected) Rev. 0.1, 11/98, page 615 of 975 27.7.6 Phase Comparison The phase comparison circuit takes measures of the difference of time between the reference signal and the comparing signal with a digital counter. REF30 signal is used for the reference signal, and HSW signal (VIDEOFF) or HHSW signal (NALLOWFF) from the HSW timing generator is used for the comparing signal. In record mode, however, the phase of REF30 signal is the same of that of the vertical sync signal (Vsync) because the reference signal generator (REF30 generator) is reset by the vertical sync signal (Vsync) in the video signals. The error detection counter performs the data latching operation at the rising or falling edge of HSW signal. The digital filter circuit performs computation using this data as 20-bit phase error data. After processing and adding the phase error data and the speed error data from the drum speed control system, the digital filter circuit send the data as the error data of the drum system to the PWM modulation circuit. 27.8 Capstan Speed Error Detector 27.8.1 Overview Capstan speed control operates so as to hold the capstan motor at a constant revolution speed, by measuring the period of the CFG signal. A digital counter detects the speed deviation from a preset value. The speed error data is added to phase error data in a digital filter. This filter controls a pulse-width modulated (PWM) output, which controls the revolution speed and phase of the capstan motor. The CFG input signal is downloaded by the comparator circuit, then reshaped into a square wave by a reshaping circuit, divided by the CFG divider, and sent to the speed error detector as the DVCFG signal. The speed error detector uses the system clock to measure the period of the DVCFG signal, and detects the deviation from a preset data value. The preset data is the value that would result from measuring the DVCFG signal period with the clock signal if the capstan motor were running at the correct speed. The error detector operates by latching a counter value when it detects an edge of the DVCFG signal. The latched count provides 16 bits of speed error data for the digital filter to operate on. The digital filter adds the speed error data to phase error data from the capstan phase control system, then sends the result to the pulse-width modulator as capstan error data. Rev. 0.1, 11/98, page 616 of 975 Error data (16 bits) To DFU DVCFG s s/2 s/4 s/8 CFCS1,0 * CFVCR R/W R F/F Q S * CFVCR R/W R/W CFESS * CFUCR R/W Internal bus W Lock range data (16 bits) * CFRLDR Lock range detector Lock range data (16 bits) * CFRUDR W Internal bus * CFVCR CFRFON Error data limitter control circuit CFOVF OVF * CFER Error data (16 bits) R/W Latch Counter (16 bits) Preset Preset data (16bit) * CFPR W Lock 2 up Lock 1 up S R Clear Q F/F Lock counter (2 bits) * CFVCR R/W CPCNT S F/F Q R CFRCS1,0 * CFRVCR CROCKON To DFU IRRCAP2 IRRCAP1 * CFVCR R CF-R/UNR UDF (R)/W 27.8.2 Block Diagram Figure 27.32 shows a block diagram of the capstan speed error detector. Figure 27.32 Block Diagram of Capstan Speed Error Detector Rev. 0.1, 11/98, page 617 of 975 27.8.3 Register Configuration Table 27.11 shows the register configuration of the capstan speed error detector. Table 27.11 Register Configuration Name Abbrev. R/W Size Initial Value Address Specified CFG speed preset data register CFPR W Word H'0000 H'FD050 CFG speed error data register CFER R/W Word H'0000 H'FD052 CFG lock UPPER data register CFRUDR W Word H'7FFF H'FD054 CFG lock LOWER data register CFRLDR W Word H'8000 H'FD056 Capstan speed error detection control register CFVCR R/W Byte H'00 H'FD058 Rev. 0.1, 11/98, page 618 of 975 27.8.4 Register Descriptions (1) Specified CFG Speed Preset Data Register (CFPR) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : W W W W W W W W W W W W W W W W The 16-bit preset data that defines the specified CFG speed is set in CFPR. The preset data is referenced to H'8000*, and can be calculated from the following equation. CFG speed preset data =H'8000 - ( s/n - 2) DVCFG frequency s: Servo clock frequency in Hz (fOSC/2) DVCFG frequency: In Hz The constant 2 is the preset interval (see figure 27.33). s/n: Clock source of the selected counter CFPR is a 16-bit write-only register. When CFPR is written to, the 16-bit preset data is also loaded into the counter. CFPR is accessible by word access only. Byte access gives unassured results. CFPR is initialized to H'0000 by a reset. Note: * The preset data value is calculated so that the counter will reach H'8000 when the error is zero. When the counter value is latched as error data in the CFG speed error data register (CFER), however, it is converted to a value referenced to H'0000. Rev. 0.1, 11/98, page 619 of 975 (2) CFG Speed Error Data Register (CFER) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W Note: * Note that only detected error data can be read. CFER is a 16-bit data register. When the speed of the capstan motor is correct, the data latched in CFER is H'0000. Negative data will be latched if the speed is too fast, and positive data if the speed is too slow. The CFER value is sent to the digital filter either automatically or by software. CFER is a 16-bit readable/writable register. The CFER value is stored until the next CFG edge. CFER is accessible by word access only. Byte access gives unassured results. CFER is initialized to H'0000 by a reset, and in module stop mode and standby mode. See the note on the specified CFG speed preset data register (CFPR) in section 27.8.4 (1). (3) CFG Lock UPPER Data Register (CFRUDR) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : W W W W W W W W W W W W W W W W CFRUDR is a register used to set the lock range on the UPPER side when capstan speed lock is detected, and to set the limit value on the UPPER side when limiter function is in use. Set a signed data to DFRUDR (bit 15 is a sign-setting bit). When lock is being detected, if the capstan speed is detected within the lock range, the lock counter which has been set by CFRCS 1 and 0 bits of CFVCR register counts down. If the set value of CFRCS 1 and 0 matches the number of times of occurrence of locking, the computation of the digital filter in the capstan phase system can be controlled automatically. Also, if the CFG speed error data is beyond the CFRUDR value when the limiter function is in use, the DFRUDR value can be used as the data for computation by the digital filter. CFRUDR is an 16-bit write-only register. Only a word access is valid. If a byte access is attempted, operation is not assured. A read is invalid. If a read is attempted, an undetermined value is read out. It is initialized to H'7FFF by a reset, stand-by or module-stop. Rev. 0.1, 11/98, page 620 of 975 (4) CFG Lock LOWER Data Register (CFRLDR) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : W W W W W W W W W W W W W W W W CFRLDR is a register used to set the lock range on the LOWER side when capstan speed lock is detected, and to set the limit value on LOWER side when limiter function is in use. When lock is being detected, if the drum speed is detected within the lock range, the lock counter which has been set by CFRCS 1 and 0 bits of CFVCR register counts down. If the set value of CFRCS 1 and 0 matches the number of times of occurrence of locking, the computation of the digital filter in the drum phase system can be controlled automatically. Also, if the CFG speed error data is under the CFRLDR value when the limiter function is in use, the CFRLDR value can be used as the data for computation by the digital filter. CFRLDR is an 16-bit write-only register. Only a word access is valid. If a byte access is attempted, operation is not assured. No read is valid. If a read is attempted, an undetermined value is read out. It is initialized to H'8000 by a reset, stand-by or module-stop. (5) Capstan Speed Error Detection Control Register (CFVCR) Bit : 7 CFCS1 6 CFCS0 5 CFOVF 0 R/W 0 R/W 0 R/(W)*1 Initial value : R/W : 4 3 2 CFRFON CF-R/UNR CPCNT 0 R/W 0 R 0 R/W 1 CFRCS1 0 CFRCS0 0 (R)*2/W 0 (R)*2/W Notes: 1. Only 0 can be written. 2. If read-accessed, the counter value is read out. CFVCR control the operation of capstan speed error detection. CFVCR is a read/write 8-bit register. Bit 3 accepts only read, and bit 5 accepts only read and 0 write. It is initialized to H'00 by a reset, stand-by or module-stop. Bits 7 and 6: Clock Source Selection Bits (CFCS1, CFCS0) CFCS1 and CFCS0 select the clock to be supplied to the counter. (s = fosc/2) Bit 7 Bit 6 CFCS1 CFCS0 Description 0 0 s 1 s/2 0 s/4 1 s/8 1 (Initial value) Rev. 0.1, 11/98, page 621 of 975 Bit 5: Counter Overflow Flag (CFOVF) CFOVF flag indicates overflow of the 16-bit counter. It is cleared by writing 0. Write 0 after reading 1. Also, setting has the highest priority in this flag. If a flag set and 0 write occurs simultaneously, the latter is nullified. Bit 5 CFOVF Description 0 Normal state 1 Indicates that a overflow has occurred in the counter (Initial value) Bit 4: Error Data Limit Function Selection Bit (CFRFON) Makes the error data limit function valid. (Limit values are the values set in the lock range data register (CFRUDR, CFRLDR)). Bit 4 CFRFON Description 0 Limit function off 1 Limit function on (Initial value) Bit 3: Capstan Lock Flag (CF-R/UNR) Sets a flag if an underflow occurred in the capstan lock counter. Bit 3 CF-R/UNR Description 0 Indicates that the capstan speed system is not locked 1 Indicates that the capstan speed system is locked (Initial value) Bit 2: Capstan Phase System Filter Computation Automatic Start Bit (CPCNT) Sets on the filter computation of the phase system if an underflow occurred in the capstan lock counter. Bit 2 CPCNT Description 0 Does not perform the filter computation by detection of the capstan lock (Initial value) 1 Set on the filter computation of the phase system when capstan lock is detected Rev. 0.1, 11/98, page 622 of 975 Bits 1 and 0: Capstan Lock Counter Setting Bits (CFRCS1, CFRCS0) Sets the number of times where drum lock has been determined (DEVCFG has been detected in the rage set by the lock range data register). It sets the capstan lock flag if it detected the set number of times of occurrence of capstan lock. If data is written in CFRCS1 and 0, it is stored in the lock counter. Note: If CFRCS1 or CFRCS0 is read-accessed, the counter value is read out. If bit 3 (capstan lock flag) is 1 and the capstan lock counter's value is 3, it indicates that the capstan speed system is locked. The capstan look counter stops until lock is released after underflow. Bit 1 Bit 0 CFRCS1 CFRCS0 Description 0 0 Underflow after lock was detected once 1 Underflow after lock was detected twice 0 Underflow after lock was detected three times 1 Underflow after lock was detected four times 1 27.8.5 (Initial value) Description of Operation The capstan speed error detector detects the speed error based on the reference value set in the CFG specified speed preset register (CFPR). The reference value set in CFPR is preset in the counter by the DVCFG signal, and counts down by the selected clock. The timing of the counter presetting and the error data latching can be selected between the rising or falling edge of DVCFG signal. See section 27.14.3, DVCFG Control Register (CDVC). The error data detected is sent to digital filter circuit. The error data is signed binaries. It takes a positive number (+) if the speed is slower than the specified speed, a negative number (-) if the speed is faster, or 0 if it had no error (revolving at the specified speed). Figure 27.33 shows an example of operation to detect the capstan speed. (a) Setting the error data limit A limit can be set to the error data sent to the digital filter circuit using the CFG lock data register (CFRUDR, CFRLDR). Set the upper limit of the error data in CFRUDR and the lower limit in CFRLDR, and write 1 in CFRFON bit. If the error data is beyond the limit range, the CFRLDR value is sent if a negative number is latched, or the CFRUDR value is sent if a positive one is latched, as a limit value. Be sure to turn off the limit setting (CERFON = 0) when you set the limit value. If the limit was set with the limit setting on (CERFON = 1), result of computation is not assured. Rev. 0.1, 11/98, page 623 of 975 (b) Lock detection If an error data was detected within the lock range set in the lock data register, the capstan lock flag (CF-R/UNR) is set by the number of the times of occurrence of locking set by CFRCS1 and 0 bits, and an interrupt is requested (IRRCAP2) at the same time. The number of the occurrence of locking (once to 4 times) can be specified when setting the flag. Use CFRCS1 and 0 bits for this purpose. Also, if bit 5 (CPHA bit) of the capstan system digital filter control register (CFIC) is 0 (phased system digital filter computation off) and DPCNT bit is 1, turning on/off of the phase system digital filter computation can be controlled automatically by the status of lock detection. (c) Capstan system speed error detection counter The capstan system speed error detection counter stops the counter and set the overflow flag (CFOVF) when overflow occurred. At the same time, it generates an interrupt request (IRRCAP1). Clear CFOVF by writing 0 after reading 1. If setting the flag and writing 0 take place simultaneously, the latter is nullified. (d) Interrupt request IRRCAP1 is generated by the DVCFG signal latch and the overflow of the error detection counter. IRRCAP2 is generated by detection of lock (after the detection of the number of times of setting). Error data latch signal (DVCFG) Preset data load Preset period (2 counts) Specified speed value Counter -value +value Preset value Latch data 0 (no error) Figure 27.33 Example of the Operation of the Capstan Speed Error Detection Rev. 0.1, 11/98, page 624 of 975 27.9 Capstan Phase Error Detector 27.9.1 Overview The capstan phase control system is required to start operation after the capstan motor has arrived at the specified speed under the control of the speed control system. The capstan phase control system operates in the following way in record/playback mode. In record mode: Controls the tape running so that it may run at a specified speed together with the speed control system. In playback mode: Control the tape running so that the recorded track may be traced correctly. Any error deviated from the reference phase is detected by the digital counter. This phase error data and the speed error data is processed and added by the digital filter circuit to control the PWM output. The phase and speed of the capstan, in turn, is control this PWM output. The control signal of the capstan phase control in the REC mode differ from that in PB mode. In REC mode, the control is performed by the DVCFG2 signal which is generated by dividing the frequencies of the reference signal (REF30P or CREF) and the CFG signal. In PB mode, it is performed by divided rising signal (DVCTL) of the reference signal (CAPREF30) and the playback control pulse (PB-CTL). The reference signal in record and playback modes are as follows. In record mode: 1/2Vsync signal extracted from the video signal to be recorded In playback mode: Signal generated by dividing the PB-CTL signal (DVCTL) at its rising edge Rev. 0.1, 11/98, page 625 of 975 Rev. 0.1, 11/98, page 626 of 975 R/W * CTLM R/W R/P ASM s s/2 s/4 s/8 R/W SELCFG2 * CPGCR DVCTL DVCFG2 RECREF CAPREF30 CREF REF30P * CPGCR R/W CR/RF CPCS1,0 R/W Internal bus S F/F Q R W MSB R/W Error data (4 bit) * CPER1 Preset R/W LSB * CPER2 Error data (16 bit) Latch * DFUCR R/W CFEPS s = fosc/2 Error data (20 bits) To DFU IRRCAP3 Latch PB : DVCTL REC : DVCFG2 Preset PB: X value + TRK value = CAPREF30 REC: REF30P or CREF * CPGCR R/(W) CPOVF OVF LSB * CPPR2 Preset data (16 bit) W Counter (20 bits) Sequence controller MSB (4 bit) Preset data * CPPR1 Internal bus 27.9.2 Block Diagram Figure 27.34 shows the block diagram of the capstan phase error detector. Figure 27.34 Block Diagram of Capstan Phase Error Detector 27.9.3 Register Configuration Table 27.12 shows the register configuration of the capstan phase error detector. Table 27.12 Register Configuration Name Abbrev. R/W Size Initial Value Address* Specified Capstan phase preset data register 1 CPPR1 W Byte H'F0 H'FD05C Specified Capstan phase preset data register 2 CPPR2 W Word H'0000 H'FD05A Capstan phase error data register 1 CPER1 R/W Byte H'F0 H'FD05D Capstan phase error data register 2 CPER2 R/W Word H'0000 H'FD05E Capstan phase error detection control register CPGCR R/W Byte H'07 H'FD059 Rev. 0.1, 11/98, page 627 of 975 27.9.4 Register Descriptions (1) Specified Capstan Phase Preset Data Registers (CPPR1, CPPR2) CPPR1 Bit : 7 -- 6 -- 5 -- 4 -- 3 2 1 0 Initial value : R/W : 1 -- 1 -- 1 -- 1 -- 0 W 0 W 0 W 0 W CPPR2 Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : W W W W W W W W W W W W W W W W The 20-bit preset data that defines the specified capstan phase is set in CPPR1 and CPPR2. The 20 bits are weighted as follows. Bit 3 of CPPR1 is the MSB. Bit 0 of CPPR2 is the LSB. When CPPR2 is written to, the 20-bit preset data, including CPPR1, is loaded into the preset circuit. Write to CPPR1 first, and CPPR2 next. The preset data is referenced to H'80000*, and can be calculated from the following equation. Target phase difference = Rreference signal frequency/2 Capstan phase preset data = H'80000 - (s/n x target phase difference) s: s/n: Servo clock frequency in Hz (fosc/2) Clock source of selected counter DFPR2 is accessible by word access only. Byte access gives unassured results. Reads are disabled. DPPR1 and DPPR2 are initialized to H'F0 and H'0000 by a reset, and in standby mode. Note: * The preset data value is calculated so that the counter will reach H'80000 when the error is zero. When the counter value is latched as error data in the capstan phase error data registers (CPER1 and CPER2), however, it is converted to a value referenced to H'00000. Rev. 0.1, 11/98, page 628 of 975 (2) Capstan Phase Error Data Registers (CPER1, CPER2) Bit : 7 -- 6 -- 5 -- 4 -- 3 2 1 0 Initial value : R/W : 1 -- 1 -- 1 -- 1 -- 0 R*/W 0 R*/W 0 R*/W 0 R*/W Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W Note: * Note that only detected error data can be read. CPER1 and CPER2 constitute a 20-bit capstan phase error data register. The 20 bits are weighted as follows. Bit 3 of CPER1 is the MSB. Bit 0 of CPER2 is the LSB. When the rotational phase is correct, the data H'00000 is latched. Negative data will be latched if the phase leads the correct phase, and positive data if it lags. Values in CPER1 and CPER 2 are transferred to the digital filter circuit. CPER1 and CPER are 20-bit readable/writable registers. When writing data to CPER 1 and CPER2, write to CPER1 first, and then write to CPER2. CPER2 is accessible by word access only. Byte access gives unassured results. CPER1 and CPER2 are initialized to H'F0 and H'0000 by a reset, and in standby mode. See the note on the capstan phase preset data registers (CPPR1 and CPPR2) in section 27.9.4 (1). Rev. 0.1, 11/98, page 629 of 975 (3) Capstan Phase Error Detection Control Register (CPGCR) Bit : Initial value : R/W : 7 CPCS1 6 CPCS0 5 CPOVF 4 CR/RF 3 SELCFG2 2 -- 1 -- 0 -- 0 R/W 0 R/W 0 R/(W)* 0 R/W 0 R/W 1 -- 1 -- 1 -- Note: * Only 0 can be written CPGCR controls the operation of capstan phase error detection. CPGCR is an 8-bit read/write register. Bits 2-0 are reserved, bit 5 accepts only read and 0 write. It is initialized to H'07 by a reset or stand-by. Bits 7, 6: Clock Source Selection Bit (CPCS1, CPCS0) Select the clock supplied to the counter. (s = fosc/2) Bit 7 Bit 6 CPCS1 CPCS0 Description 0 0 s 1 s/2 0 s/4 1 s/8 1 (Initial value) Bit 5: Counter Overflow Flag (CPOVF) CPOVF flag indicates the overflow of the 20-bit counter. It is cleared by writing 0. Write 0 after reading 1. Also, setting has the highest priority in this flag. If a flag set and 0 write occurs simultaneously, the latter is nullified. Bit 5 CPOVF Description 0 Normal state 1 Indicates that a overflow has occurred in the counter (Initial value) Bit 4: Preset Signal Selection Bit (CR/RF) Selects the preset signal. Bit 4 CR/RF Description 0 Presets REF30P 1 Presets CREF signal Rev. 0.1, 11/98, page 630 of 975 (Initial value) Bit 3: Latch Signal Selection Bit (SELCFG2) Selects the counter preset signal and the error data latch signal data in PB (ASM) mode. Bit 3 SELCFG2 Description 0 Presets CAPREF30 signal; latches DVCTL signal 1 Presets REF30P (CREF) signal; latches DVCFG2 signal (Initial value) Bits 2 to 0: Reserved Bits 2 to 0 are reserved. No read or write is valid. 27.9.5 Description of Operation The capstan phase error detector detects the phase error based on the reference value set in the capstan specified phase preset data register 1 and 2 (CPPR1, CPPR2). The reference values set in CPPR1 and 2 are preset in the counter by REF30P (CREF) signal or CAPREF signal, and counted up by the clock selected. The latching of the error data is performed by DVCTL or DVCFG2. The error data detected in the error data automatic transmission mode (CFEPS bit of DFUCR = 0) is sent to the digital filter circuit automatically. In soft transmission mode (CFEPS bit of DFUCR = 1), the data written in CPER1 and 2 is sent to the digital filter circuit. The error data is signed binary. It takes a positive number (+) if the phase is behind the specified phase, a negative number (-) if in advance of the specified phase, or 0 if it had no phase error (revolving at the specified phase). Figures 27.35 and 27.36 show examples of operation to detect a capstan phase error. (a) Capstan phase error detection counter The capstan phase error detection counter stops the counter when overflow or latch occurred. At the same time, it generates an interrupt request (IRRCAP3), setting the overflow flag (DPOVF) if overflow occurred. Clear CPOVF by writing 0 after reading 1. If setting the flag and writing 0 take place simultaneously, the latter is nullified. (b) Interrupt request IRRCAP3 is generated by the DVCTL or DVCFG2 signal latch and the overflow of the error detection counter. Rev. 0.1, 11/98, page 631 of 975 CAPREF30 PB-CTL DVCTL or DVCFG2 Preset Preset Counter Latch Latch Preset value Figure 27.35 Capstan Phase Control in Playback Mode REF30P or CREF DVCFG2 Preset Counter Preset Latch Preset value Figure 27.36 Capstan Phase Control in Record Mode Rev. 0.1, 11/98, page 632 of 975 Latch 27.10 X-Value and Tracking Adjustment Circuit 27.10.1 Overview To maintain compatibility with other VCRs, an on-chip adjustment circuit adjusts the phase of the reference signal (internal reference signal (REF30) or external reference signal (EXCAP)) during playback. Because of manufacturing tolerances, the physical distance between the video head and control head (the X-value: 79.244 mm) may vary from set to set, so when a tape that was recorded on a different set is played back, the phase of the reference signal may need to be adjusted. The adjustment can be made by a register setting. The same setting can adjust the rotational phase of the capstan motor to maintain positional alignment (tracking alignment) of the video head with the recorded tracks in autotracking, or when tracks that were recorded with an EP head are traced by a wider head. These tracking adjustments can be made by acquisition of the envelope signal by A/D converter. 27.10.2 Block Diagram The adjustment circuit consists of a 10-bit counter clocked by the system clock (s or s/2), and two down-counters with load register. Individual setting of X-value adjustment can be made by X-value data register (XDR) and tracking adjustment by TRK data register (TRDR). The reference signal clears the 10-bit counter and sets the load register value in the down-counter with two load registers. After the adjusted reference signal is generated, clock supply stops and the circuit halts until the next reference signal is input. REF30 signal can be divided (by 2 to 4) as necessary. Figure 27.37 shows a block diagram. Rev. 0.1, 11/98, page 633 of 975 Figure 27.37 Block Diagram of X-Value Adjustment Circuit Rev. 0.1, 11/98, page 634 of 975 W CAPRF R*/W DVREF1, 0 * XTCR (2bit) Down counter Edge selection W EXC/REF * XTCR R Q S Internal bus Counter (10bit) AT/MU W (12bit) X-value data register * XDR (12bit) Down counter * XTCR W ASM R S Q REC/PB * XTCR W TRK/X Internal bus Note: * When DVREF1 and DVREF0 are read, values in the down counter (2 bits) are readout. s = fosc/2 REF30P EXCAP s s /2 XCS * XTCR W (12bit) Down counter (12bit) TRK value data register * TRDR W REF30X CAPREF30 27.10.3 Description of Registers (1) Register Configuration Table 27.13 shows the register configuration of X-value correction and tracking correction circuits. Table 27.13 Register Configuration Name Abbrev. R/W Size Initial Value Address* X-value and TRK-value control register XTCR R/W Byte H'80 H'FD074 X-value data register XDR W Word H'F000 H'FD070 TRK-value data register TRDR W Word H'F000 H'FD072 (2) X-value and TRK-value Control Register (XTCR) Bit : 7 -- 6 CAPRF 5 AT/MU 4 TRK/X 3 EXC/REF 2 XCS 1 DVREF1 0 DVREF0 Initial value : R/W : 1 -- 0 W 0 W 0 W 0 W 0 W 0 R*/W 0 R*/W XTCR is an 8-bit register to determine the X-value and TRK-value correction circuits. Bits 6-2 are write-only bits. No read is valid. If a read is attempted, an undetermined value is read out. Bits 1 and 0 are read/write bits. XTCR accepts only a byte access. If a word access is attempted, operation is unassured. It is initialized to H'80 by a reset, stand-by or module stop. Note: If read-accessed, the counter value is read out. Bit 7: Reserved Bit 7 is reserved. No write is valid. If a read is attempted, an undetermined value is read out. Bit 6: External Sync Signal Edge Selection Bit (CAPRF) Selects the EXCAP edge when a selection is made to generate external sync signals. Bit 6 CAPRF Description 0 Signal generated at the rising edge of EXCAP 1 Signal generated at both edges of EXCAP (Initial value) Rev. 0.1, 11/98, page 635 of 975 Bit 5: Capstan Phase Correction Auto/Manual Selection Bit (AT/08) Selects whether the generation of the correction reference signal (CAPREF30) for capstan phase control is controlled automatically or manually depending on the status of the ASM and REC/3% bits of CTL mode register. Bit 5 AT/08 Description 0 Manual mode 1 Auto mode (Initial value) Bit 4: Capstan Phase Correction Register Selection Bit (TRK/;) Determines the method to generate the CAPREF30 signal when AT/08 bit is 0. Bit 4 TRK/; Description 0 Generates CAPREF30 only by the set value of XDR 1 Generates CAPREF30 by the set value of XDR and TRDR (Initial value) Bit 3: Reference Signal Selection Bit (EXC/REF) Selects the reference signal to generate the correction reference signal (CAPREF30). Bit 3 EXC/REF Description 0 Generates the signal based on REF30P 1 Generates the signal based on the external reference signal (Initial value) Bit 2: Clock Source Selection Bit (XCS) Selects the clock source to be supplied to the 10-bit counter. Bit 2 XCS Description 0 s 1 s/2 Rev. 0.1, 11/98, page 636 of 975 (Initial value) Bits 1 and 0: REF30P Division Ratio Selection Bit (DVREF1, DVREF0) Selects the division value of REF30P. If it is read-accessed, the counter value is read out. (The selected division value is set by the UDF of the counter.) Bit 1 Bit 0 DVREF1 DVREF0 Description 0 0 Division in 1 1 Division in 2 0 Division in 3 1 Division in 4 1 (Initial value) (3) X-value Data Register (XDR) Bit : Initial value : R/W : 15 14 13 12 -- -- -- -- 1 -- 1 -- 1 -- 1 -- 11 10 9 8 7 6 5 4 3 2 1 0 XD11 XD10 XD9 XD8 XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0 0 0 0 0 0 0 0 0 0 0 0 0 W W W W W W W W W W W W The X-value data register (XDR) is an 16-bit write-only register. No readis valid. If a read is attempted, an undefined value is read out. XDR accepts only a word-access. If a byte access is attempted, operation is not assured. Set an X-value correction data to XDR, except a value which is beyond the cycle of the CTL pulse. If AT/08 = 0, TRK/; = 0 was set, CAPREF30 can be generated only by the setting of SDR. Set an X-value and TRK correction value in PB mode, and X- value in REC mode. It is initialized to H'F000 by a reset, stand-by or module stop. (4) TRK-value Data Register (TRDR) Bit : 15 14 13 12 -- -- -- -- TRD11 TRD10 TRD9 TRD8 TRD7 TRD6 TRD5 TRD4 TRD3 TRD2 TRD1 TRD0 1 R/W : -- 1 -- 1 -- 1 -- Initial value : 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 W W W W W W W W W W W W The TRK-value data register (TRDR) is an 16-bit write-only register. No read is valid. If a read is attempted, an undefined value is read out. TRDR accepts only a word-access. If a byte access is attempted, operation is not assured. Set an TRK-value correction data to TRDR, except a value which is beyond the cycle of the CTL pulse. It is initialized to H'F000 by a reset, stand-by or module stop. Rev. 0.1, 11/98, page 637 of 975 27.11 Digital Filters 27.11.1 Overview The digital filters required in servo control make extensive use of multiply-accumulate operations on signed integers (error data) and coefficients. A filter computation circuit (digital filter computation circuit) is provided in on-chip hardware to reduce the load on software, and to improve processing efficiency. Figure 27.38 shows a block diagram of the filter circuit configuration. The filter circuit includes a high-speed 24-bit x 16-bit multiplier-accumulator, an arithmetic buffer, and an I/O processor. The digital filter computations are carried out by the high-speed multiplier-accumulator. The arithmetic buffer stores coefficients and gain constants needed in the filter computations, which are referenced by the high-speed multiplier-accumulator. The I/O processor is activated by a frequency generator signal, and determines what operation is carried out. When activated, it reads the speed error and phase error from the speed and phase error detectors and sends them to the accumulator. When the filter computation is completed, the I/O processor reads the result from the accumulator and sends it to a 12-bit PWM. At this time, the accumulation result gain can be controlled. Rev. 0.1, 11/98, page 638 of 975 27.11.2 Block Diagram Error latch signal Accumulation controller End Start Sign controller Buffer/ register select & R/W A, B, G, etc. Write-only Calculation register Coefficient register Constant register UA (32 bits), upper accumulator Accumulator Data shifter LA (16 bits), lower accumulator Accumulation sequence circuit Data bus Error check Address bus Accumulator MD (32 bits), multiplied data Read-only Buffer circuit Error data (from the error detector) Motor control data (to PWM circuit) Figure 27.38 Block Diagram of Digital Filter Circuit Rev. 0.1, 11/98, page 639 of 975 Figure 27.39 Digital Filter Representation Rev. 0.1, 11/98, page 640 of 975 Phase system Speed system 16 DAs15 to 0 CAs15 to 0 + As 24 XAs 8 + DAp15 to 0 CAp15 to 0 16 AP 24 XAp 8 - + 8 VBp 24 8 BP 8 8 VSn 24 + 24 DZs11 to 0 CZs11 to 0 8 KP DGKp15 to 0 CGKp15 to 0 DBp15 to 0 CBp15 to 0 16 8 Bs 8 8 GKp 16 GP VBs 24 Usn * + Usn-1 24 Z -1 8 - DZp11 to 0 CZp11 to 0 24 * Upn-1 24 Upn Z -1 + * Add the same 8-bit value as MSB * Add 0s to 8 bits after the decimal point Ep VPn 24 24 8 + Error detector DPER19 to 0 CPER19 to 0 20 Ep Error detector DFER15 to 0 CFER15 to 0 16 Es * Add the same 8-bit value as MSB * Add 0s to 8 bits after the decimal point Es XSn 24 8 + 24 Tp 24 DBs15 to 0 CBs15 to 0 16 KS 16 OfP - Ofs Y 24 14 8 DOfp15 to 0 COfp15 to 0 Ws 24 - 8 Right-bit shift of the decimal point along with Go 12 PWM Go Note 2 12 PION CP/DP * DFUCR PWM Note: Go = x64, x32 are optional. Go = x64, x32, x16, x8,x4, x2 8 Phase direct test output 4 DOfs15 to 0 COfs15 to 0 DFUout 24 DFIC CFIC * OPTION PWM PWM * : See figure 27.42, Z-1 initialization circuit. Notes: 1. Overflows during accumulation are ignored, and values below the decimal point are always omitted. 2. Gain control is disabled during phase output. 8 + DGKs15 to 0 CGKs15 to 0 GKs 16 GS + Digital filter control register 27.11.3 Arithmetic Buffer This buffer stores computational data used in the digital filters. See table 27.14. Write access is -1 limited to the gain and coefficient data (Z ). The other data is used by hardware. None of the data can be read. Table 27.14 Arithmetic Buffer Register Configuration Buffer Data Length Arithmetic Data Phase system Gain or Coefficient Processing Data 16 bits 16 bits 16 bits Ep Upn -1 Upn-1 (Zp ) Vpn Tp Y Ap Bp GKp Ofp Ap x Epn Bp x Vpn Speed system Es Xsn Usn -1 Usn-1 (Z s) Vsn Ws As Bs GKs Ofs As x Xsn Bs x Vsn Error output Legend: PWM Valid bits Non-existent bits Decimal point Rev. 0.1, 11/98, page 641 of 975 27.11.4 Register Configuration Table 27.15 shows the register configuration of the digital circuit. Table 27.15 Register Configuration Name Abbrev. R/W Size Initial Value Address Capstan phase gain constant CGKp W Word Undetermined H'FD010 Capstan speed gain constant CGKs W Word Undetermined H'FD012 Capstan phase coefficient A CAp W Word Undetermined H'FD014 Capstan phase coefficient B CBp W Word Undetermined H'FD016 Capstan speed coefficient A CAs W Word Undetermined H'FD018 Capstan speed coefficient B CBs W Word Undetermined H'FD01A Capstan phase offset COfp W Word Undetermined H'FD01C Capstan speed offset COfs W Word Undetermined H'FD01E Drum phase gain constant DGKp W Word Undetermined H'FD000 Drum speed gain constant DGKs W Word Undetermined H'FD002 Drum phase coefficient A DAp W Word Undetermined H'FD004 Drum phase coefficient B DBp W Word Undetermined H'FD006 Drum speed coefficient A DAs W Word Undetermined H'FD008 Drum speed coefficient B DBs W Word Undetermined H'FD00A Drum phase offset DOfp W Word Undetermined H'FD00C Drum speed offset DOfs W Word Undetermined H'FD00E Drum system speed delay initialization register DZs W Word H'F000 H'FD020 Drum system phase delay initialization register DZp W Word H'F000 H'FD022 Capstan system speed delay initialization register CZs W Word H'F000 H'FD024 Capstan system phase delay initialization register CZp W Word H'F000 H'FD026 Drum system digital filter control register DFIC R/W Byte H'80 H'FD028 Capstan system digital filter control register CFIC R/W Byte H'80 H'FD029 Digital filter control register DFUCR R/W Byte H'C0 H'FD02A Rev. 0.1, 11/98, page 642 of 975 27.11.5 Register Description (1) Gain Constants (DGKp, DGKs, CGKp, CGKs) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : * * * * * * * * * * * * * * * * R/W : W W W W W W W W W W W W W W W W Note: * Initial value is uncertain. These registers are 16-bit write-only buffers that set accumulation gain of the digital filter. They cannot be read. They can be accessed by word access only. Accumulation gain can be set to gain 1 value as maximum value. Byte access gives unassured results. These registers are not initialized by a reset or in standby mode. Be sure to write data in them before processing starts. In the digital filter, output gain and accumulation gain can be adjusted separately. Take output gain into account when setting accumulation gain. (2) Coefficients (DAp, DBp, DAs, DBs, CAp, CBp, CAs, CBs) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : * * * * * * * * * * * * * * * * R/W : W W W W W W W W W W W W W W W W Note: * Initial value is uncertain. These registers are 16-bit write-only buffers that determine the cutoff frequency f1 and f2.. They cannot be read. They can be accessed by word access only. Byte access gives unassured results. These registers are not initialized by a reset or in standby mode. Be sure to write data in them before processing starts. In the digital filter, output gain and accumulation gain can be adjusted separately. Take output gain into account when setting accumulation gain. Rev. 0.1, 11/98, page 643 of 975 (3) Offset (DOfp, DOfs, COfp, COfs) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : * * * * * * * * * * * * * * * * R/W : W W W W W W W W W W W W W W W W Note: * Initial value is uncertain. These registers are 16-bit write-only buffers that set offset level of digital filter output. They cannot be read. They can be accessed by word access only. Byte access gives unassured results. These registers are not initialized by a reset or in standby mode. Be sure to write data in them before processing starts. In this digital filter, output gain adjustment (x1, 2, 4, 8 ,16, 32, 64) after offset adding is enabled. Take output gain into account when setting accumulation gain. (4) Delay Initialization Register (CZp, CZs, DZp, DZs) Bit : 15 14 13 12 Initial value : 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 -- W W W W W W W W W W W W R/W : -- -- -- 11 10 9 8 7 6 5 4 3 2 1 0 The delay initialization register is an 16-bit write-only register. It accepts only a word-access. If a byte access is attempted, operation is not assured. If a read is attempted, an undefined value is read out. Bits 12 to 15 are reserved, and no write in them is valid. It is initialized to H'F000 by a reset, stand-by or module stop. The MSB of 12-bit data (bit 11) is a sign bit. -1 Loading to Z is performed automatically by bits 4 and 3 of CFIC and DFIC (CZPON, CZSON, -1 DZPON, DZSON). Writing in register is always available, but loading in Z is not possible when the digital filter is performing calculation processing in relation to such register. In such a -1 case, loading to Z will be done the next time computation began. (5) Drum System Digital Filter Control Register (DFIC) Bit : Initial value : R/W : -- 7 6 DROV 5 DPHA 4 DZPON 3 DZSON 2 DSG2 1 DSG1 0 DSG0 1 -- 0 R/(W)* 0 R/(W) 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Note: * Only 0 can be written DFIC is a 8-bit readable/writable register that controls the status of the drum digital filter and operating mode. They can be accessed by byte access only. Word access gives unassured results. Rev. 0.1, 11/98, page 644 of 975 Bit 7 is a reserved bit. Writes are disabled. DFIC is initialized to H'80 by a reset, and in standby mode and module stop mode. Bit 7: Reserved This bit is reserved. Reads and writes are both disabled. Bit 6: Drum System Range Over Flag (DROV) This flag is set to 1 when the result of a filter computation exceeds 12 bits in width. To clear this flag, write 0. Bit 6 DROV Description 0 Indicates that the filter computation result did not exceed 12 bits 1 Indicates that the filter computation result exceeded 12 bits (Initial value) Bit 5: Drum Phase System Filter Computation Start Bit (DPHA) Starts or stops filter processing for drum phase system. Bit 5 DPHA Description 0 Phase system filter computations are disabled Phase computation result (Y) is not added to Es (see figure 27.34) 1 (Initial value) Phase system filter computations are enabled Rev. 0.1, 11/98, page 645 of 975 -1 Bit 4: Drum Phase System Z Initialization Bit (DZPON) -1 Reflects the DZp value on Z of the phase system when computation processing of the drum phase system began. If 1 was written, it is reflected on the computation, and then cleared to 0. Set this bit after writing data to DZp. Bit 4 DZPON Description 0 DZp value is not reflected on Z of the phase system -1 (Initial value) -1 1 DZp value is reflected on Z of the phase system -1 Bit 3: Drum Speed System Z Initialization Bit (DZSON) -1 Reflects the DZs value on Z of the speed system when computation processing of the drum speed system begins. If 1 was written, it is reflected on the computation, and then cleared to 0. Set this bit after writing data to DZs. Bit 3 DZSON Description 0 DZs value is not reflected on Z of the speed system -1 (Initial value) -1 1 DZs value is reflected on Z of the speed system Bits 2 to 0: Drum System Output Gain Control Bits (DSG2, DSG1, DSG0) Control the gain output to DRMPWM. Bit 2 Bit 1 Bit 0 DSG2 DSG1 DSG0 Description 0 0 0 x1 1 x2 0 x4 1 x8 0 x 16 1 (x 32)* 0 (x 64)* 1 Invalid (Do not set) 1 1 0 1 Note: * Setting optional Rev. 0.1, 11/98, page 646 of 975 (Initial value) (6) Capstan Digital Filter Control Register (CFIC) Bit : 7 -- 6 DROV 5 DPHA 4 DZPON 3 DZSON 2 DSG2 1 DSG1 0 DSG0 Initial value : R/W : 1 -- 0 R/(W)* 0 R/(W) 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Note: * Only 0 can be written CFIC is a 7-bit readable/writable register that controls the status of the capstan digital filter and operating mode. They can be accessed by byte access only. Word access gives unassured results. Bit 7 is a reserved bit. Writes are disabled. CFIC is initialized to H'80 by a reset, and in standby mode and module stop mode. Bit 7: Reserved This bit is reserved. Reads and writes are both disabled. Bit 6: Capstan System Range Over Flag (CROV) This flag is set to 1 when the result of a filter computation exceeds 12 bits in width. To clear this flag, write 0. Bit 6 CROV Description 0 Indicates that the filter computation result did not exceed 12 bits 1 Indicates that the filter computation result exceeded 12 bits (Initial value) Bit 5: Capstan Phase System Filter Start (CPHA) Starts or stops filter processing for capstan phase system. Bit 5 CROV Description 0 Phase filter computations are disabled Phase computation result (Y) is not added to Es (see figure 27.38) 1 Phase filter computations are enabled (Initial value) Rev. 0.1, 11/98, page 647 of 975 -1 Bit 4: Capstan Phase System Z Initialization Bit (CZPON) -1 Reflects the CZp value on Z of the capstan phase system when computation processing of the phase system began. If 1 was written, it is reflected on the computation, and then cleared to 0. Set this bit after writing data to CZp. Bit 4 CZPON Description 0 CZp value is not reflected on Z of the phase system -1 (Initial value) -1 1 CZp value is reflected on Z of the phase system -1 Bit 3: Capstan Speed System Z Initialization Bit (CZSON) -1 Reflects the CZs value on Z of the capstan speed system when computation processing of the speed system began. If 1 was written, it is reflected on the computation, and then cleared to 0. Set this bit after writing data to CZs. Bit 3 CZSON Description 0 CZs value is not reflected on Z of the speed system -1 (Initial value) -1 1 CZs value is reflected on Z of the speed system Bits 2 to 0: Capstan System Gain Control Bits (CSG2, CSG1, CSG0) Control the gain output to CAPPWM. Bit 1 Bit 2 Bit 0 CSG2 CSG1 CSG0 Description 0 0 0 x1 1 x2 0 x4 1 x8 0 x 16 1 (x 32)* 0 (x 64)* 1 Invalid (Do not set) 1 1 0 1 Note: * Setting optional Rev. 0.1, 11/98, page 648 of 975 (Initial value) (7) Digital Filter Control Register (DFUCR) Bit : 7 -- 6 -- 5 PTON 4 CP/DP 3 CFEPS 2 DFEPS 1 CFESS 0 DFESS Initial value : R/W : 1 -- 1 -- 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W DFUCR is an 8-bit read/write register which controls the operation of the digital filter. It accepts a byte-access only. If it was word-accessed, operation is not assured. Bits 7 and 6 are reserved. No write in them is valid. It is initialized to H'00 by a reset, stand-by or module stop. Bits 7 and 6: Reserved Bits 7 and 6 are reserved. No read or write is valid. If a read is attempted, an undefined value is read out. Bit 5: Phase System Computation Result PWM Output Bit (PTON) Outputs the computation results of only the phase system to PWM. (The computation results of the drum phase system is output to CAPPWM pin, and that of the capstan phase system is output to DRMPWM pin.) Bit 5 PTON Description 0 Outputs the results of ordinary computation of the filter to PWM pin 1 Outputs the computation results of only the phase system to PWM pin (Initial value) Bit 4: PWM Output Selection Bit (CP/'3) Selects whether the phase system computation results when PTON was set to 1 is output to the drum or capstan. The PWM of the selected side outputs ordinary filter computation results (speed system of MIX). Bit 4 CP/'3 Description 0 Outputs the drum phase system computation results (CAPPWM) 1 Outputs the capstan phase system computation results (DRMPWM) (Initial value) Rev. 0.1, 11/98, page 649 of 975 Bit 3: Capstan Phase System Error Data Transfer Bit (CFEPS) Transfers the capstan phase system error data to the digital filter when the data write is enforced. Bit 3 CFEPS Description 0 Error data is transferred by DVCFG2 signal latching 1 Error data is transferred when the data is written (Initial value) Bit 2: Drum Phase System Error Data Transfer Bit (DFEPS) Transfers the drum phase system error data to the digital filter when the data write is enforced. Bit 2 DFEPS Description 0 Error data is transferred by HSW (NHSW) signal latching 1 Error data is transferred when the data is written (Initial value) Bit 1: Capstan Speed System Error Data Transfer Bit (CFESS) Transfers the capstan phase system error data to the digital filter when the data write is enforced. Bit 1 CFESS Description 0 Error data is transferred by DVDFG signal latching 1 Error data is transferred when the data is written (Initial value) Bit 0: Drum Speed System Error Data Transfer Bit (DFESS) Transfers the drum speed system error data to the digital filter when the data write is enforced. Bit 0 DFESS Description 0 Error data is transferred by NCDFG signal latching 1 Error data is transferred when the data is written Rev. 0.1, 11/98, page 650 of 975 (Initial value) 27.11.6 Filter Characteristics (1) Lag-Lead Filter A filter required for a servo loop is built in the hardware. This filter uses IIR (Infinite Impulse Response) type digital filter (another type of the digital filter is FIR, i.e. Finite Impulse Response type). This digital filter circuit implements a lag-lead filter, as shown in figure 27.40. R1 INPUT OUTPUT R2 + C Figure 27.40 Lag-lead Filter The transfer function is expressed by the following equation. S 2f2 Transfer function G (S) = S 1+ 2f1 1+ f1=1/2C (R1+R2) f2=1/2CR2 Rev. 0.1, 11/98, page 651 of 975 (2) Frequency Characteristics The computation circuit repeats computation of the function, which is obtained by s-z conversion according to bi-linear approximation of the transfer function on the s-plane. Figure 27.41 shows the frequency characteristics of the lag-lead filter. gain(dB) 20log(f1/f2) f1 f2 phase(deg) Frequency (Hz) 0 Figure 27.41 Frequency Characteristics of the Lag-Lead Filter The pulse transfer function G(Z) is obtained by the bi-linear approximation of the transfer G (S). In the transfer G (S), S= 2 1-Z-1 Ts 1+Z-1 Where, assumed that Z = e-jTs, -1 G (Z) = G 2 1+AZ-1 Ts 1+BZ-1 1 f2 G (Z) = 1 Ts+ f1 Ts - Ts+ Ts: A= Ts+ Sampling cycle (sec) Rev. 0.1, 11/98, page 652 of 975 1 f2 1 f2 Ts - B= Ts+ 1 f1 1 f1 27.11.7 Operations in Case of Transient Response In case of transient response when the motor is activated, the digital filter computation circuit must prevent computation due to a large error. The convergence of the computations becomes slow and servo retraction becomes deteriorating if a large error is input to the filter circuit when it is performing repeated computations. To prevent them from occurring, operate the filter (set constants A and B) after pulling in the speed and phase within a certain range of error, initialize -1 -1 the Z (set initial values in CZp, CZs, DZp, DZs)(see section 27.11.8, Initialization of Z ), or use the error data limit function (see section regarding the error detector). 27.11.8 Initialization of Z -1 -1 -1 Z can be initialized by its delay initialization register (CZp, CZs, DZp, DZs). Loading to Z is performed automatically by bits 4 and 3 of CFIC and DFIC (CZPON, CZSON, DZPON, -1 DZSON). Writing in register is always available, but loading in Z is not possible when the digital filter is performing calculation processing in relation to such register. In such a case, -1 loading to Z will be done the next time computation began. Figure 27.42 shows the -1 initialization circuit of Z . -1 The delay initialization register sets 12-bit data. The MSB (bit 11) is a signed bit. Z has 24 bits for integrals and 8 bits for decimals. Accordingly, the same value as the signed bits should be -1 set in the 13 bits on the MSB side of Z , and 0 in the entire decimal section. Example: Value set for the delay initialization register MSB 1 0 0 0 0 0 0 0 0 0 0 0 Value set for Z -1 MSB 111111111111100000000000 Set here the value in the signed bits 00000000 Fixed Rev. 0.1, 11/98, page 653 of 975 Xn Vn + + Usn-1 24 Res Z 8 Delay initialization register -1 12 USn - + A DAs15 to 0 DAp15 to 0 CAs15 to 0 CAp15 to 0 DZs11 to 0 DZp11 to 0 CZs11 to 0 CZp11 to 0 B 16 DBs15 to 0 DBp15 to 0 CBs15 to 0 CBp15 to 0 16 Z -1initialization bit DZSON DZPON CZSON CZSON W W W W Internal bus Note: MSB of 12-bit data to be written in the delay initialization register is a sign bit. -1 Figure 27.42 Z Initialization Circuit 27.12 Additional V Signal 27.12.1 Overview The circuit described in this section outputs an additional vertical sync signal to take the place of Vsync in special playback. It is activated at both edges of the HSW signal output by the headswitch timing generator. The head-switch timing generator also outputs a Vpulse signal containing the additional vertical sync pulse itself, and an Mlevel signal that defines the width of the additional vertical sync signal including the equalizing pulses. The additional V signal is output at a three-level output pin (Vpulse). Figure 27.43 shows the additional V signal control circuit. Rev. 0.1, 11/98, page 654 of 975 HSW timing generator Mlevel signal Vpulse signal Csync Sync detector OSCH Additional V pulse generator Additional V pulse Figure 27.43 Additional V Pulse Control Circuit (a) HSW timing generator This circuit generates signals that are synchronized with head switching. It should be programmed to generate the Mlevel and Vpulse signals at edges of the HSW signal (VideoFF). For details, see section 27.4, HSW (Head-switch) Timing Generator. (b) Sync detector This circuit detects pulses of the width specified by VTR or HTR from the signal input at the Csync pin and generates an internal horizontal sync signal (OSCH). The sync detector has an interpolation function, so OSCH has a regular period even if there are horizontal sync dropouts in the signal received at the pin. For details, see section 27.15, Sync Signal Detector. 27.12.2 Pin Configuration Table 27.16 summarizes the pin configuration of the additional V signal. Table 27.16 Pin Configuration Name Abbrev. I/O Function Additional V pulse pin Vpulse Output Output of additional V signal synchronized to Video FF Rev. 0.1, 11/98, page 655 of 975 27.12.3 Register Configuration Table 27.17 summarizes the register that controls the additional V signal. Table 27.17 Register Configuration Name Abbrev. R/W Size Initial Value Address Additional V control register ADDVR R/W Byte H'E0 H'FD06F 27.12.4 Register Description Additional V Register (ADDVR) Bit : Initial value : R/W : 7 6 5 -- -- -- 4 HMSK 3 HiZ 2 CUT 1 VPOM 0 POL 1 -- 1 -- 1 -- 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W ADDVR is a 8-bit readable/writrable register. It is initialized to H'E0 by a reset, and in standby mode. Bits 7 to 5: Reserved These bits are reserved. Reads and writes are both disabled. If a read is attempted, an undefined value is readout. Rev. 0.1, 11/98, page 656 of 975 Bit 4: OSCH Mask (HMSK) Masks the OSCH signal in the additional V signal. Bit 4 HMSK Description 0 OSCH is added in 1 OSCH is not added in (Initial value) Bit 3: High Impedance (HiZ) Set to 1 when the intermediate level is generated by an external circuit. Bit 3 HiZ Description 0 Vpulse is a three-level output pin 1 Vpulse is a three-state output pin (high, low, or high-impedance) (Initial value) Bits 2 to 0: Additional V Output Control (CUT, VPON, POL) These bits control the output at the additional V pin. Bit 2 Bit 1 Bit 0 CUT VPON POL Description 0 0 * Low level 1 0 Negative polarity (see figure 27.46) 1 Positive polarity (see figure 27.45) 0 Intermediate level (high impedance if HiZ bit = 1) 1 High level 1 Note: * * (Initial value) Don't care. Rev. 0.1, 11/98, page 657 of 975 27.12.5 Additional V Pulse Signal Figure 27.44 shows the additional V pulse signal. The Mlevel and Vpulse signals are generated by the head-switch timing generator. The OSCH signal is combined with these to produce equalizing pulses. The polarity can be selected by the POL bit in the additional V register (ADDVR). Vpulse pin outputs a low level by a reset, and in standby mode and module stop mode. Internal bus R/W R/W R/W * ADDVR VPON CUT HMSK R/W POL R/W * ADDVR HiZ STBY VCC VCC OSCH Rs Vpulse Vpulse pin Rs Mlevel [Legend] STBY : Power-down mode other than sleep mode Vpulse, Mlevel : Signal from the HSW timing generator Rs : Voltage division resistance (20 k: Reference value) Figure 27.44 Additional V Pin Rev. 0.1, 11/98, page 658 of 975 VSS VSS (a) Additional V pulses when sync signal is not detected With additional V pulses, the pulse signal (OSCH) detected by the sync detector is superimposed on the V pulse and Mlevel signals generated by the head-switch timing generator. If there is a lot of noise in the input sync signal (Csync), or a pulse is missing, OSCH will be a complementary pulse, and therefore an H pulse of the period set in HRTR and HPWR will be superimposed. In this case, there may be slight timing drift compared with the normal sync signal, depending on the HRTR and FPWR setting, with resultant discontinuity. If no sync signal is input, the additional V pulse is generated as a complementary pulse. Set the sync detector registers and activate the sync detector by manipulating the SYCT bit in the sync signal control register (SYNCR). See section 27.15.7, Sync Detector Activation. Figures 27.45 and 27.46 show the additional V pulse timing charts. HSW signal edge Mlevel signal Vpulse signal OSCH Additional V pulse VPON=1, CUT=0, POL=1 Figure 27.45 Additional V Pulse When Positive Polarity is Specified Rev. 0.1, 11/98, page 659 of 975 HSW signal edge Mlevel signal Vpulse signal OSCH Additional V pulse VPON=1, CUT=0, POL=1 Figure 27.46 Additional V Pulse When Negative Polarity is Specified 27.13 CTL Circuit 27.13.1 Overview The CTL circuit includes a Schmitt amplifier that amplifies and reshapes the CTL input, then outputs it as the PB-CTL signal to the servo, linear time counter, and other circuits. The PB-CTL signal is also sent to a duty discriminator in the CTL circuit that detects and records VISS, ASM, and VASS marks. A REC-CTL amplifier is included in the record circuits. Detection and recording whether the CTL pulse pattern is long or short can also be enabled to correspond to the wide-aspect. The following operating modes can be selected by settings in the CTL mode register: * Duty discrimination VISS detect, ASM detect, VASS detect, L/S bit pattern detect * CTL record VISS record, ASM record, VASS record, L/S bit pattern detect * Rewrite Trapezoid waveform generator Rev. 0.1, 11/98, page 660 of 975 27.13.2 Block Diagram Figure 27.47 shows a block diagram of the CTL circuit. PB-CTL CTL mode IRRCTL FW/RV Duty descriminator CTL detector VISS detect VISS control circuit Bit pattern register Write control circuit Schmitt amplifier + - CTL(+) VISS write Duty I/O flag REF30X Internal bus RECCTL amplifier CTL(-) Figure 27.47 Block Diagram of CTL Circuit Rev. 0.1, 11/98, page 661 of 975 27.13.3 Pin Configuration Table 27.18 summarizes the pin configuration of the CTL circuit. Table 27.18 Pin Configuration Name Abbrev. I/O Function CTL (+) I/O pin CTL (+) I/O CTL signal input/output CTL (-) I/O pin CTL (-) I/O CTL signal input/output CTL bias input pin CTL Bias Input CTL primary amplifier bias supply CTL Amp (O) output pin CTLAmp (O) Output CTL amplifier output CTL SMT (i) input pin CTLSMT (i) Input CTL Schmitt amplifier input CTL FB input pin CTL FB Input CTL amplifier high-range characteristics control CTL REF output pin CTL REF Output CTL amplifier reference voltage output 27.13.4 Register Configuration Table 27.19 shows the register configuration of the CTL circuit. Table 27.19 Register Configuration Name Abbrev. R/W Size Initial Value Address CTL control register CTCR R/W Byte H'30 H'FD080 CTL mode register CTLM R/W Byte H'00 H'FD081 REC-CTL duty data register 1 RCDR1 W Word H'F000 H'FD082 REC-CTL duty data register 2 RCDR2 W Word H'F000 H'FD084 REC-CTL duty data register 3 RCDR3 W Word H'F000 H'FD086 REC-CTL duty data register 4 RCDR4 W Word H'F000 H'FD088 REC-CTL duty data register 5 RCDR5 W Word H'F000 H'FD08A Duty I/O register DI/O R/W Byte H'F1 H'FD08C Bit pattern register BTPR R/W Byte H'FF H'FD08D Rev. 0.1, 11/98, page 662 of 975 27.13.5 Register Descriptions (1) CTL Control Register (CTCR) Bit : 7 6 5 4 3 2 1 0 NT/PL FSLC FSLB FSLA CCS LCTL UNCTL SLWM Initial value : 0 0 1 1 0 0 0 0 R/W : W W W W W W R W The CTL control register (CTCR) controls PB-CTL rewrite and sets the slow mode. When CTL pulse cannot be detected with the input amplifier gain set at the CTL gain control register (CTLGR) in PB-CTL circuit, the bit 1 (UNCTL) of CTCR is set to 1. It is automatically cleared to 0 when CTL pulse is detected. CTCR is an 8-bit readable/writable register. However, bit 1 is read-only, and the rest is writeonly. CTCR is initialized to H'30 by a reset, and in standby and module stop mode. Bit 7: NTSC/PAL Select (NT/PL) Selects the period of the rewrite circuit. Bit 7 NT/PL Description 0 NTSC mode (frame rate: 30 Hz) 1 PAL mode (frame rate: 25 Hz) (Initial value) Bits 6 to 4: Frequency Select (FSLA, FSLB, FSLC) These bits select the operating frequency of the CTL write circuit. They should be set according to fOSC. Bit 1 Bit 0 Bit 0 FSLC FSLB FSLA Description 0 0 0 Reserved (do not set) 1 Reserved (do not set) 0 fosc = 8 MHz 1 fosc = 10 MHz * Reserved (do not set) 1 1 Note: * * (Initial value) Don't care. Rev. 0.1, 11/98, page 663 of 975 Bits 3: Clock Source Select Bit (CCS) Selects clock source of CTL. Bit 3 CCS Description 0 s 1 s/2 (Initial value) Bit 2: Long CTL Bit (LCTL) Sets the long CTL detection mode. Bit 2 LCTL Description 0 Clock source (CCS) operates at the setting value 1 Clock source (CCS) operates for further 8-division after operating at the setting value (Initial value) Bit 1: CTL Undetected Bit (UNCTL) Indicates the CTL pulse detection status at the CTL input amplifier sensitivity set at the CTL gain control register. Bit 1 UNCTL Description 0 Detected 1 Undetected (Initial value) Bit 0: Mode Select Bit (SLWM) Selects CTL mode. Bit 0 SLWM Description 0 Normal mode 1 Slow mode Rev. 0.1, 11/98, page 664 of 975 (Initial value) (2) CTL Mode Register (CTLM) Bit : 7 6 5 4 3 2 1 0 ASM REC/PB FW/RV MD4 MD3 MD2 MD1 MD0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : R/W : The CTL mode register (CTLM) is an 8-bit read/write register that controls the operating state of the CTL circuit. If 1 is written in bits MD3 and MD2, they will be cleared to 0 one cycle () later. CTLM is initialized to H'00 by a reset, and in standby mode and module stop mode. When CTL is being stopped, only bits 7, 6 and 5 operate. Note: Do not set any value other than the setting value for each mode (see table 27.20, CTL Mode Functions). Bits 7 and 6: Record/Playback Mode Bits (ASM, REC/PB) These bits switch between record and playback. Combined with bits 4 to 0 (MD4 to MD0), they support the VISS, VASS, and ASM mark functions. Bit 7 Bit 6 ASM REC/3% Description 0 0 Playback mode 1 Record mode 0 Assemble mode 1 Invalid (do not set) 1 (Initial value) Bit 5: Direction (FW/RV) Selects the direction in playback. Clear this bit to 0 during record. Figure 27.48 shows the PBCTL signal. Bit 5 FW/RV Description 0 FORWARD 1 REVERSE (Initial value) Rev. 0.1, 11/98, page 665 of 975 CTL input FWD PB-CTL REV Figure 27.48 Internal PB-CTL Signal in Forward and Reverse Bits 4 to 0: CTL Mode Select (MD4 to MD0) These bits select the detect, record, and rewrite modes for VISS, VASS, and ASM marks. If 1 is written in bits MD3 and MD2, they will be cleared to 0 one cycle () later. The 5 bits from MD4 to MD0 are used in combination with bits 7 and 6 (ASM and REC/3%). Table 27.20 describes the modes. Table 27.20 CTL Mode Functions (1) Bit ASM R/3 F/R MD4 MD3 MD2 MD1 MD0 Mode Description 0 0/1 0 0 0 0 0 VASS detect (duty detect) PB-CTL duty discrimination (Initial value) 0 * Duty I/O flag is set to 1 if duty 44% is detected * Duty I/O flag is cleared to 0 if duty < 44% is detected * Interrupt request is generated when one CTL pulse has been detected 0 1 0 0 0 0 0 0 VASS record * If 0 is written in the duty I/O flag, REC-CTL is generated and recorded with the duty cycle set by register RCDR2 or RCDR3 * If 1 is written in the duty I/O flag, REC-CTL is generated and recorded with the duty cycle set by register RCDR4 or RCDR5 0 0 0 1 0 Rev. 0.1, 11/98, page 666 of 975 0 1 0 VASS rewrite Same as above (VASS record); trapezoid waveform circuit operation Table 27.20 CTL Mode Functions (2) Bit ASM R/3 F/R MD4 MD3 MD2 MD1 MD0 Mode Description 0 0/1 0 1 0 0 1 VISS detect (index detect) * The duty I/O flag is set to 1 at the point of write access to register CTLM 0 * The 1 pulses recognized by the duty discrimination circuit are counted in the VISS control circuit * The duty I/O flag is cleared to 0, indicating VISS detection, when the value set at VCTR register is repeatedly detected * An interrupt request is generated when VISS is detected 0 1 0 0 0 1 0 1 VISS record (index record) * 64 pulse data with 0 pulse data at both edge are written (index record) * The index bit string is written through the duty I/O flag * An interrupt request is generated at the end of VISS recording 0 0 0 0 0 1 0 1 VISS rewrite Same as above (VISS record; trapezoid waveform circuit operation) 0 0 0 1 0 0 0 0 VISS initialize VISS write is forcibly aborted 1 0 0/1 0 0 0 0 0 ASM mark ASM mark detection detect * The duty I/O flag is cleared to 0 when PB-CTL duty 66% is detected * An interrupt request is generated when an ASM mark is detected 0 1 0 1 0 0 0 0 ASM mark * An ASM mark is recorded by record writing 0 in the duty I/O flag * An interrupts is requested for every one CTL pulse * REC-CTL is generated and recorded with the duty cycle set by register RCDR3 Rev. 0.1, 11/98, page 667 of 975 (3) REC-CTL Duty Data Register 1 (RCDR1) Bit : Initial value : R/W : 15 14 13 12 -- -- -- -- 1 -- 1 -- 1 -- 1 -- 11 10 9 8 7 6 5 4 3 2 1 0 CMT1B CMT1A CMT19 CMT18 CMT17 CMT16 CMT15 CMT14 CMT13 CMT12 CMT11 CMT10 0 0 0 0 0 0 0 0 0 0 0 0 W W W W W W W W W W W W RCDR1 is a register that sets the REC-CTL rising timing. This setting is valid only for recording and rewriting, and is not used in detection. RCDR1 is a 12-bit write-only register, and can be accessed by word access only. Byte access gives unassured results. Bits 15 to 12 are reserved and are not affected by write access. RCDR1 is initialized to H'F000 by a reset, and in standby mode, module stop mode and CTL stop mode. The value to set in RCDR1 can be calculated from the transition timing T1 and the servo clock frequency s by the equation given below. See figure 27.60, REC-CTL Signal Generation Timing. Any transition timing can be set. The timing should be selected with attention to playback tracking compensation and the latch timing for phase control. RCDR1 = T1 x s/64 s is the servo clock frequency (= fOSC/2) in Hz, and T1 is the set timing (s). Note: 0 cannot be set to RCDR1. Set a value 1 or above. Rev. 0.1, 11/98, page 668 of 975 (4) REC-CTL Duty Data Register 2 (RCDR2) Bit : Initial value : R/W : 15 14 13 12 -- -- -- -- 1 -- 1 -- 1 -- 1 -- 11 10 9 8 7 6 5 4 3 2 1 0 CMT2B CMT2A CMT29 CMT28 CMT27 CMT26 CMT25 CMT24 CMT23 CMT22 CMT21 CMT20 0 0 0 0 0 0 0 0 0 0 0 0 W W W W W W W W W W W W RCDR2 is a register that sets 1 pulse (short) falling timing of REC-CTL at recording and rewriting, and detects long/short pulses at detecting. RCDR2 is a 12-bit write-only register, and can be accessed by word access only. Byte access gives unassured results. Bits 15 to 12 are reserved and are not affected by write access. RCDR2 is initialized to H'F000 by a reset, and in standby mode, module stop mode, and CTL stop mode. At recording, the value to set in RCDR2 can be calculated from the transition timing T2 and the servo clock frequency s by the equation given below, and the set value should be 25% of the duty obtained by the equation. See figure 27.60, REC-CTL Signal Generation Timing. RCDR2 = T2 x s/64 s is the servo clock frequency (= fOSC/2) in Hz, and T2 is the set timing (s). At bit pattern detection, set the 1 pulse long/short threshold value at FWD. See figure 27.56, Duty Discriminator. RCDR2 = T2' x s/64 s is the servo clock frequency (= fOSC/2) in Hz, and T2' is the 1 pulse long/short threshold value at FWD (s). Rev. 0.1, 11/98, page 669 of 975 (5) REC-CTL Duty Data Register 3 (RCDR3) Bit : 15 14 13 12 -- -- -- -- 1 R/W : -- 1 -- 1 -- 1 -- Initial value : 11 10 9 8 7 6 5 4 3 2 1 0 CMT3B CMT3A CMT39 CMT38 CMT37 CMT36 CMT35 CMT34 CMT33 CMT32 CMT31 CMT30 0 0 0 0 0 0 0 0 0 0 0 0 W W W W W W W W W W W W RCDR3 is a register that sets 1 pulse (long) and assemble mark falling timing of REC-CTL at recording and rewriting, and detects long/short pulses at detecting. RCDR3 is a 12-bit write-only register, and can be accessed by word access only. Byte access gives unassured results. Bits 15 to 12 are reserved and are not affected by write access. RCDR3 is initialized to H'F000 by a reset, and in standby mode, module stop mode, and CTL stop mode. At recording, the value to set in RCDR3 can be calculated from the transition timing T3 and the servo clock frequency s by the equation given below. The set value should be 30% of the duty when the RCDR3 is used for REC-CTL 1 pulse, and 67 to 70% when used for assemble mark. The set value must not exceed the value of REF30X. See figure 27.60, REC-CTL Signal Generation Timing. RCDR3 = T3 x s/64 s is the servo clock frequency (= fOSC/2) in Hz, and T3 is the set timing (s). At bit pattern detection, set the 0 pulse long/short threshold value at FWD. See figure 27.56, Duty Discriminator. RCDR3 = T3' x s/64 s is the servo clock frequency (= fOSC/2) in Hz, and T3' is the 0 pulse long/short threshold value at FWD (s). Rev. 0.1, 11/98, page 670 of 975 (6) REC-CTL Duty Data Register 4 (RCDR4) Bit : 15 14 13 12 -- -- -- -- 1 R/W : -- 1 -- 1 -- 1 -- Initial value : 11 10 9 8 7 6 5 4 3 2 1 0 CMT4B CMT4A CMT49 CMT48 CMT47 CMT46 CMT45 CMT44 CMT43 CMT42 CMT41 CMT40 0 0 0 0 0 0 0 0 0 0 0 0 W W W W W W W W W W W W RCDR4 sets the timing of falling edge of the 0 pulse (Short) of REC-CTL in record or rewrite mode. In detection mode, it is used to detect the Long/Short pulse. RCDR4 is a 12-bit write-only register. It accepts only a word-access. If a byte access is attempted, operation is not assured. If a read is attempted, an undefined value is read out. Bits 15 to 12 are reserved, and no write in them is valid. It is initialized to H'F000 by a reset, stand-by or module stop. In record mode, set a value with the 57.5% duty cycle obtained from the set time T4 corresponding to the frequency s according to the following equation. See figure 27.60, RECCTL Signal Generation Timing. RCDR4 = T4 x s/64 is the servo clock frequency (= fOSC/2) in Hz, and T4 is the set timing (s). At bit pattern detection, set the 0 pulse long/short threshold value at REV. See figure 27.56, Duty Discriminator. RCDR4 = H'FFF - (T4' x s/80) s is the servo clock frequency (= fOSC/2) in Hz, and T4' is the 0 pulse long/short threshold value at REV (s). Rev. 0.1, 11/98, page 671 of 975 (7) REC-CTL Duty Data Register 5 (RCDR5) 15 14 13 12 -- -- -- -- 1 R/W : -- 1 -- 1 -- 1 -- Bit : Initial value : 11 10 9 8 7 6 5 4 3 2 1 0 CMT5B CMT5A CMT59 CMT58 CMT57 CMT56 CMT55 CMT54 CMT53 CMT52 CMT51 CMT50 0 0 0 0 0 0 0 0 0 0 0 0 W W W W W W W W W W W W RCDR5 sets the timing of falling edge of the 0 pulse (Short) of REC-CTL in record or rewrite mode. In detection mode, it is used to detect the Long/Short pulse. RCDR5 is a 12-bit write-only register. It accepts only a word-access. If a byte access is attempted, operation is not assured. If a read is attempted, an undefined value is read out. Bits 15 to 12 are reserved, and no write in them is valid. It is initialized to H'F000 by a reset, stand-by or module stop. In record mode, set a value with the 62.5% duty cycle obtained from the set time T5 corresponding to the frequency s according to the following equation. See figure 27.60, RECCTL Signal Generation Timing. RCDR5 = T5 x s/64 is the servo clock frequency (= fOSC/2) in Hz, and T5 is the set timing (s). At bit pattern detection, set the 1 pulse long/short threshold value at REV. See figure 27.56, Duty Discriminator. RCDR5 = H'FFF - (T5' x s/80) s is the servo clock frequency (= fOSC/2) in Hz, and T5' is the 1 pulse long/short threshold value at REV (s). Rev. 0.1, 11/98, page 672 of 975 (8) Duty I/O Register (DI/O) Bit : Initial value : R/W : 7 VCTR2 6 VCTR1 5 VCTR0 4 -- 3 BPON 2 BPS 1 BPF 0 DI/O 1 W 1 W 1 W 1 -- 0 W 0 W 0 R/(W)* 1 R/W Note: * Only 0 can be written The duty I/O register is an 8-bit register that confirms and determines the operating status of the CTL circuit. It is initialized to H'F1 by a reset, and in standby mode, module stop mode, and CTL stop mode. Bits 7, 6, and 5: VISS Interrupt Setting Bit (VCTR2, VCTR1, VCTR0) Combination of VCTR2, VCTR1 and VCTR0 sets number of 1 pulse detection in VISS detection mode. Detecting the set number of pulse detection is considered as VISS detection, and an interrupt request is generated. Note: When changing the detection pulse number during VISS detection, initialize VISS first, then resume the VISS detection setting. Bit 7 Bit 6 Bit 5 VCTR2 VCTR1 VCTR0 Number of 1-pulse for detection 0 0 0 2 1 4 (SYNC mark) 0 6 1 8 (mark A, short) 0 12 (mark A, long) 1 16 0 24 (mark B) 1 32 1 1 0 1 Bit 4: Reserved This bit is reserved. Writes are disabled. When read, undefined values are obtained. Rev. 0.1, 11/98, page 673 of 975 Bit 3: Bit Pattern Detection ON/OFF Bit (BPON) Determines ON or OFF of bit pattern detection. Note: When writing 1 to BPON bit, be sure to set appropriate data to RCDR 2 to 5 beforehand. Bit 3 BPON Description 0 Bit pattern detection OFF 1 Bit pattern detection ON (Initial value) Bit 2: Bit Pattern Detection Start Bit (BPS) Starts 8-bit bit pattern detection. When 1 is written to this bit, it returns to 0 after one cycle. Writing 0 to this bit does not affect operation. Bit 2 BPS Description 0 Normal status 1 Starts 8-bit bit pattern detection (Initial value) Bit 1: Bit Pattern Detection Flag (BPF) Sets flag every time 8-bit PB-CTL is detected in PB or ASM mode. To clear flag, write 0 after reading 1. Bit 1 BPF Description 0 Bit pattern (8-bit) is not detected 1 Bit pattern (8-bit) is detected (Initial value) Bit 0: Duty I/O Register (DI/O) This flag has different functions for record and playback. In VISS detect mode, VASS detect mode, and ASM mark detect mode, this flag indicates the detection result. In VISS record or rewrite mode, this flag controls the write control circuit so as to write an index code, operating according to a control signal from the VISS control circuit. In VASS record or rewrite mode and ASM mark record mode, this flag is used for write control, one CTL pulse at a time. This bit can always be written to, but this does not affect the write control circuit in modes other than VISS record, rewrite, and ASM record. Rev. 0.1, 11/98, page 674 of 975 VISS Detect Mode and VASS Detect Mode The duty I/O flag indicates the result of duty discrimination. The duty I/O flag is 1 when the duty cycle of the PB-CTL signal is above 44% (a 0 pulse in the CTL signal). The duty I/O flag is 0 when the duty cycle of the PB-CTL signal is below 44% (a 1 pulse in the CTL signal). ASM Mark Detect Mode The duty I/O flag indicates the result of duty discrimination. The duty I/O flag is 0 when the duty cycle of the PB-CTL signal is above 66% (when an ASM mark is detected). VISS Record Mode and VISS Rewrite Mode The duty I/O flag operates according to a control signal from the VISS control circuit, and controls the write control circuit so as to write an index code. The write timing is set in the REC-CTL duty data registers (RCDR1 to RCDR5). For VISS recording, registers RCDR1 to RCDR5 are set with reference to REF30X. For VISS rewrite, RCDR2 to RCDR5 are set with reference to the low-to-high transition of the previously recorded CTL signal, and the write is carried out through the trapezoid waveform generator. Set the duty timing for a 1 pulse (short) in RCDR2, for a 1 pulse (long) in RCDR3, for a 0 pulse (short) in RCDR4, and for a 0 pulse (long) in RCDR5. While an index code is being written, the value of the bit being written can be read by reading the duty I/O flag. If the CTL signal currently being written is a 0 pulse, the duty I/O flag will read 1. If the CTL signal currently being written is a 1 pulse, the duty I/O flag will read 0. VASS Record Mode and VASS Rewrite Mode The duty I/O flag is used for write control, one CTL pulse at a time. The write timing is set in the REC-CTL duty data registers (RCDR1 to RCDR5). For VASS recording, registers RCDR1 to RCDR5 are set with reference to REF30X. For VASS rewrite, RCDR2 to RCDR5 are set with reference to the low-to-high transition of the previously recorded CTL signal, and the write is carried out through the trapezoid waveform generator. Set the duty timing for a 1 pulse (short) in RCDR2, for a 1 pulse (long) in RCDR3, for a 0 pulse (short) in RCDR4, and for 0 pulse (long) in RCDR5. If 0 is written in the duty I/O flag, a CTL pulse will be written with a duty cycle set in RCDR2 and RCDR3, referenced to the immediately following REF30X. If 1 is written in the duty I/O flag, a CTL pulse will be written with a duty cycle set in RCDR4 and RCDR5, referenced to the immediately following REF30X. ASM Record Mode The duty I/O flag is used for write control, one CTL pulse at a time. The write timing is set in the REC-CTL duty data registers (RCDR1 and RCDR3). If 0 is written in the duty I/O flag, a CTL pulse will be written with a duty cycle of 67% to 70% as set in RCDR3, referenced to the immediately following REF30X. Rev. 0.1, 11/98, page 675 of 975 (9) Bit Pattern Register (BTPR) Bit : 7 LSP7 6 LSP6 5 LSP5 4 LSP4 3 LSP3 2 LSP2 1 LSP1 0 LSP0 Initial value : R/W : 1 R/W* 1 R/W* 1 R/W* 1 R/W* 1 R/W* 1 R/W* 1 R/W* 1 R/W* Note: * Write is prohibited when bit pattern detection is selected. The bit pattern register (BTPR) is an 3-bit shift register which detects and records the bit pattern of the CTL pulses. If a CTL pulse is detected in PB or ASM mode, the register is shifted leftward at the rising edge of PB-CTL, and reflects the determined result of Long/Short on the bit 0 (Long pulse = 1, Short pulse = 0). If BPON bit is set to 1 in PB mode, the register starts detection of bit pattern immediately after the CTL pulse. To exit the bit pattern detection, set the BPON bit at 0. If 1 was written in the BPS bit when the bit pattern is being detected, the BPF bit is set at 1 when an 3-bit bit pattern was detected. If continuous detection of 8-bits is required, write 0 in the BPF bit, and then write 1 in BPS bit. At the time of VISS detection, the bit pattern detection is disabled. Set the BPON bit to 0 at the time of VISS detection. In REC mode, the register record the Long/Shorts in the bit pattern set in BTPR. The pulse in record mode is determined always by bit 7 (LSP7) of BTPR. BTPR records one pulse, shifts leftward, and stores the data of bit 7 to bit 0. BTPR is initialized to H'FF by a reset, stand-by, module stop, or CTL stop. Rev. 0.1, 11/98, page 676 of 975 27.13.6 Operation (a) CTL circuit operation As shown in figure 27.49, the CTL discrimination/record circuit is composed of a 16-bit up/down counter and 12-bit registers (x5). In playback (PB) mode, the 16-bit up/down counter counts on a s/4 clock when the PB-CTL pulse is high, and on a s/5 clock when low. In record or slow mode, this counter counts up on a s/8 clock when the pulse is high, and on a s/4 clock when low. This counter always counts up in record and slow modes. In playback or slow mode, it is cleared on the rise of PB-CTL signal. In record mode, it is cleared on the rise of REF30X signal. UP/DOWN control signal REC: UP PB, ASM: UP when PB-CTL is high Down when PB-CTL is low Counter clear signal REF30X (REC) PB-CTL (PB, ASM) UP s/4 (s/8) s/5 (s/4) UP/DOWN counter (16 bits) UDF Duty detection Upper 12 bits DOWN UDF: Underflows when PB-CTL duty is 44% or less RCDR1 Match detection REC-CTL RCDR2 Match detection REC-CTL(S1) RCDR3 Match detection REC-CTL(L1and ASM) RCDR4 Match detection REC-CTL(S0) RCDR5 Match detection REC-CTL(L0) 12-bit register Figure 27.49 CTL Circuit (b) CTL mode register (CTLM) switchover timing CTLM is enabled immediately after data is written to the register. Care must be taken with changes in the operating state. Capstan phase control is performed by the VD sync REF30X (X-value + tracking value) and PB-CTL in ASM mode, and by the REF30X or CREF and CFG division signal (DVCFG2) in REC mode. If CAPREF30 signal to be used for capstan phase control is always generated by XDR, the value of XDR must be overwritten when switching between PB and REC modes. Figures 27.50 and 27.51 show examples of switch timing of CTLM and XDR. Rev. 0.1, 11/98, page 677 of 975 The X-value is updated by REF30P. Modification of XDR must be performed before REF30P in the cycle in which the X-value is changed. X-value (XDR) is rewritten in this cycle VD REF30P HSW X-value after change X-value Latch Preset Capstan phase control ASM mode, PB mode : REF30X-PB-CTL REC mode : REF30P-DVCFG2 Tx REF30X PB-CTL REC-CTL CTL Ta 16bit UP/DOWN counter Tb /5 /4 /4 RCDR1 RCDR3 RCDR1 RCDR2 UDF 0 pulse 1 pulse 0 pulse 1 pulse DVCFG2 CDIVR2 Register write Ta is the interval calculated from RDCR3. Tb is the interval in which switchover is performed from ASM mode to REC mode. Tx is the cycle in which the REF30X period is shortened due to the change of XDR. Figure 27.50 Example of CTLM Switchover Timing (When Phase Control Is Performed by REF30P and DVCFG2 in REC Mode) Rev. 0.1, 11/98, page 678 of 975 The X-value is updated by REF30P. Modification of XDR must be performed before REF30P in the cycle in which the X-value is changed. X-value (XDR) is rewritten in this cycle VD REF30P HSW X-value after change X value Tx Capstan phase control ASM mode, PB mode: REF30X-PB-CTL REF30X REC-CTL PB-CTL CTL Ta 16bit UP/DOWN counter Tb /5 /4 /4 RCDR1 RCDR3 RCDR1 RCDR2 UDF 0 pulse 1 pulse 0 pulse 1 pulse DVCFG2 CDIVR2 Register write CREF ASM-REC switchover Latch Preset Capstan phase control REC mode : REF30P-DVCFG2 Ta is the interval calculated from RDCR3. Tb is the interval in which switchover is performed from ASM mode to REC mode. Tx is the cycle in which the REF30X period is shortened due to the change of XDR. With CREF and DVCFG2 phase alignment, the frequency need not be 25 Hz or 30 Hz. Figure 27.51 Example of CTLM Switchover Timing (When Phase Control Is Performed by CREF and DVCFG2 in REC Mode) Rev. 0.1, 11/98, page 679 of 975 27.13.7 CTL Input Section The CTL input section consists of a Schmitt amplifier, a CTL detector, and a redetector. Figure 27.52 shows a block diagram of the CTL input section. Trivial CTL pulse signal is received from the CTL head, amplified by the input amplifier, reshaped into a square wave by the Schmitt amplifier, and sent to the servo circuits, and the Timer L as the PB-CTL signal. Control the CTL input amplifier gain by bits 3 to 0 in CTL gain control register (CTLGR) of the servo port. AMPON (PB-CTL) AMPSHORT (REC-CTL) CTLGR3 to 1 CTLFB CTLGR0 - + + - - + PB-CTL(+) PB-CTL(-) CTL(-) CTL(+) CTLREF CTLBias CTLFB CTLAmp(o) CTLSMT(i) Note Note : Be sure to set a capacitor between CTLAmp (o) and CTLSMT (i). Figure 27.52 Block Diagram of CTL Input Amplifier Rev. 0.1, 11/98, page 680 of 975 (1) CTL Detector If the CTL detector fails to detect a CTL pulse, it sets the CTL control register (CTCR) bit 1 to high indicating that the pulse has not been detected. If a CTL pulse is detected after that, the bit is automatically cleared to 0. Duration used for determining detection or nondetection of the pulse depends on magnitude of phase shift of the last detected pulse from the reference phase (phase difference between REF30 and CTL signal). Typically, detection or non-detection is determined within 3 to 4 cycles of the reference period. If settings of the CTL gain control register are maintained in a table format, you can refer to it when the CTL detector failed to detect CTL pulses. From the table, you can control input gain of the CTL according to state of UNCTL bit, thereby selecting an optimum CTL amplifier gain depending on state of the pulse recorded. Figure 27.53 illustrates concept of gain control for detecting the CTL input pulse. * V+TH (fixed) V-TH (fixed) * Note: * CTL input sensitivity is variable depending on CTL gain control register (CTLGR) setting. Figure 27.53 CTL Input Pulse Gain Control Rev. 0.1, 11/98, page 681 of 975 (2) PB-CTL Waveform Shaper in Slow Mode Operation If bit 0 in CTL control register (CTCR) is set to slow mode, slow reset function is activated. In slow mode, if falling edge is not detected within the specified time from rising edge detection, PB-CTL is forcibly shut down (slow reset). The time TFS (s) until the signal falls is the following interval after the rising edge of the internal CTL signal is detected: (s = fOSC/2) TFS = 16384 x 4 s When fOSC = 10 MHz, TFS = 13.1 ms. Figure 27.54 shows the PB-CTL waveform in slow mode. 1 frame 1 frame 1 frame CTL waveform Slow reset Internal CTL signal CTLP Acceleration CTLP Deceleration Slow tracking delay Stop Acceleration CTLP Deceleration Slow tracking delay Acceleration Stop Figure 27.54 PB-CTL Waveform in Slow Mode Operation Rev. 0.1, 11/98, page 682 of 975 Slow tracking delay 27.13.8 Duty Discriminator The duty discriminator circuit measures the period of the control signal recorded on the tape (PB-CTL signal) and discriminates its duty cycle. In VISS or VASS detection, the duty I/O flag is set or cleared according to the result of duty discrimination. The duty I/O flag is set to 1 when the duty cycle of the PB-CTL signal is above 44%, and is cleared to 0 when the duty cycle is below 44%. In ASM detection, an ASM mark is recognized (and the duty I/O flag is cleared to 0) when the duty cycle is above 66%. When the duty cycle is below 66%, no ASM mark is recognized and the duty I/O flag is set to 1. The detection direction can be switched between forward and reverse by bit 5 (FW/RV) in the CTL mode register. Long or short pulse can be detected by comparing REC-CTL duty data register (RCDR2 to RCDR5) and UP/DOWN counter. Long or short pulse id discriminated at PB-CTL signal falling. Discrimination result is stored in bit 0 of bit pattern register (BTPR). At the same time, BTPR is shifted to the left. LSP0 indicates 0 when short pulse is detected, and 1 when long pulse is detected. Set the threshold value of long/short pulse in RCDR2 to RCDR5. See (4), Detection of the Long/Short Pulse. Figure 27.55 shows the duty cycle of the PB-CTL signal. Rev. 0.1, 11/98, page 683 of 975 Input signal Short 1 pulse PB-CTL 250.5% Input signal Long 1 pulse PB-CTL 300.5% Input signal Short 0 pulse PB-CTL 57.50.5% Input signal Long 0 pulse PB-CTL 62.50.5% Input signal ASM Mark PB-CTL 67 to 70% Figure 27.55 PB-CTL Signal Duty Cycle Rev. 0.1, 11/98, page 684 of 975 Figure 27.56 shows the duty discrimination circuit. A 44% duty cycle is discriminated by counting with the 16-bit up/down counter, using a s/4 clock for the up-count and a s/5 clock for the down-count. An up-count is performed when the PB-CTL signal is high, and a downcount when low. Long or short pulse is discriminated by comparing with RCDR2 to RCDR5. PB-CTL UP/DOWN s/4 UDF UP/DOWN counter (16 bits) 0/1 discrimina tion s/5 Comparison of upper 12-bit S * RCDR2or4 (12bit) L/S discrimina tion Q R * RCDR3or5 (12bit) Clear PB-CTL * FWD : Discriminated by RCDR2 and RCDR3 REV : Discriminated by RCDR4 and RCDR5 s/4 s/5 Counter PB-CTL 1 pulse s/5 Counter s/4 PB-CTL 0 pulse 0 pulse L/S threshold value RCDR3 Counter FWD s/5 RCDR2 1 pulse L/S threshold value s/4 PB-CTL Short pulse (0 pulse) s/5 REV RCDR4 Counter 0 pulse L/S threshold value s/4 RCDR5 1 pulse L/S threshold value PB-CTL Long pulse (1 pulse) Figure 27.56 Duty Discriminator Rev. 0.1, 11/98, page 685 of 975 (1) VISS (Index) Detect Mode VISS detection is carried out by the VISS control circuit, which counts 1 pulses in the PBCTL signal. If the pulse count detects any value set in the VISS interrupt setting bits (bits 5, 6 or 7 in the duty I/O register), an interrupt request is generated and the duty I/O flag is cleared to 0. At VISS record or rewrite, INDEX code is automatically written. INDEX code is composed of 0 continuous 62-bit data with 0 pulse data at both edge. Examples of bit strings and the duty I/O flag at VISS detection/record is illustrated in figure 27.57. IRRCTL Thirty-two 1 pulses detected Tape direction 1 0 1 1 1 1 1 1 1 0 613 bits 633 bits Start Duty I/O flag (a) VISS detection (INDEX: Thirty-two 1 pulse setting) IRRCTL 1 2 3 Tape direction 62 63 64 1 0 1 1 1 1 1 1 1 0 62 bits 64 bits Start Duty I/O flag (b) VISS record Figure 27.57 Examples of VISS Bit Strings and Duty I/O Flag Rev. 0.1, 11/98, page 686 of 975 (2) Duty Detection Mode (VASS) VASS detection is carried out by the duty discriminator. Software can detect index sequences by reading the duty I/O flag at each CTL pulse. At each CTL pulse, the duty discriminator sends the result of duty discrimination to the duty I/O flag, and simultaneously generates an interrupt request. The duty I/O flag is cleared to 0 if the CTL pulse is a 1 (duty cycle below 44%), and is set to 1 if the CTL pulse is a 0 (duty cycle above 44%). The duty I/O flag is modified at each CTL pulse. It should be read by the interrupt-handling routine within the period of the PB-CTL signal. VASS detection format is illustrated in figure 27.58. Tape direction Written three times M B 1 1 1 1 1 1 1 1 1 1 1 S Header (11 bits) L M S S B B Thousands L M S S B B Hundreds L M S S B B Tens L S B Ones Data (16 bits: 4 digits of 4-bit BCD) Figure 27.58 VASS (Index) Format (3) Assemble (ASM) Mark Detect Mode ASM mark detection is carried out by the duty discriminator. If the duty discriminator detects that the duty cycle of the PB-CTL signal is 66% or higher, it generates an interrupt request, and simultaneously clears the duty I/O flag to 0. The duty I/O flag is updated at every CTL pulse. It should be read by the interrupt-handling routine within the period of the PB-CTL signal. Rev. 0.1, 11/98, page 687 of 975 (4) Detection of the Long/Short Pulse The Long/Short pulse is detected in PB mode by the L/S determination based on the comparison of the REC-CTL duty register (RCDR2 to RCDR5) with the up/down counter and the results of the duty I/O flag. The results of the determination is stored in bit 0 (LSP0) of the bit pattern register (BTPR) at the rising edge of PB-CTL, shifting at the same time BTPR leftward. RCDR2-5 set the L/S thresholds for each of FWD/REV. Set to RCDR2 a threshold of 1 pulse L/S for FWD, to RCDR3 a threshold of 0 pulse L/S for FWD, to RCDR4 a threshold of 0 pulse L/S for REV, and to RCDR5 a threshold of 1 pulse L/S for REV. Figure 27.59 shows the detection of Long/Short pulse. Also, the bit pattern of 8-bit can be detected by BTPR. Check that an 8-bit detection has been done by bit 1 (BPF bit) of the duty I/O register, and then read BTPR. Internal bus R BTPR Shift leftrward Bit patter register (8-bit) LSB RCDR2 (12bit) S RCDR3 (12bit) Q R RCDR4 (12bit) S RCDR5 (12bit) Q R FW/RV DI/O High-order 12-bit data s/4 UP/DOWN counter (16-bit) L/S is determined at the rising edge of PB-CTL. After the determination, bit pattern register is shifted leftward, and the results of the determination is stored in the LSB. Figure 27.59 Detection of Long/Short Pulse Rev. 0.1, 11/98, page 688 of 975 27.13.9 CTL Output Section An on-chip control head amplifier is provided for writing the REC-CTL signal generated by the write control circuit onto the tape. The write control circuit controls the duty cycle of the REC-CTL signal in the writing of VISS and VASS sequences and ASM marks and the rewriting of VISS and VASS sequences. The duty cycle of the REC-CTL signal is set in REC-CTL duty data registers 1 to 5 (RCDR1 to RCDR5). Times calculated in terms of s (= fOSC/2) should be converted to appropriate data to be set in these registers. In VISS or VASS mode, set RCDR2 for a duty cycle of 25%0.5%, RCDR3 for a duty cycle of 30%0.5%, RCDR4 for a duty cycle of 57.50.5%, and RCDR5 for a duty cycle of 62.50.5%. When 1 is written in the duty I/O flag, the REC-CTL signal will be written on the tape with a 25%0.5% duty cycle when 0 is written in bit 7 (LSP7) in the bit pattern register (BTPR) and with a 300.5% duty cycle when 1 is written. Table 27.21 shows the relationship between the REC-CTL duty register and CTL outputs. In ASM mark write mode, set RCDR3 for a duty cycle of 67% to 70%. An ASM mark will be written when 0 is written in the duty I/O flag. An interrupt request is generated at the rise of the reference signal after one CTL pulse has been written. The reference signal is derived from the output signal (REF30X) of the X-value adjustment circuit, and has a period of one frame. Figure 27.60 shows the timings that generate the REC-CTL signal. Table 27.21 REC-CTL Duty Register and CTL Outputs MODE D/IO LSP7 Pulse RCDR Duty VISS, VASS modes 0 0 S1 RCDR2 250.5% 1 L1 RCDR3 300.5% 0 S0 RCDR4 57.50.5% 1 L0 RCDR5 65.50.5% * RCDR3 60 to 70% 1 ASM mode Note: * 0 Don't care. Rev. 0.1, 11/98, page 689 of 975 Internal bus RESET REF30X W W W Clear s/4 RCDR1 (12bit) UP/DOWN counter (12 bits) RCDR2or4 (12bit) RCDR3or5 (12bit) Compare Compare Upper 12 bits Compare REC-CTL rise timing REC-CTL1 pulse, ASM fall timing REC-CTL 0 pulse fall timing End of writing of one CTL pulse (except VISS) IRRCTL REF30X Counter reset Match detection Counter Match detection REC-CTL RCDR1 RCDR2 (VISS/VASS S1 p pulse) RCDR3 (VISS/VASS L1 pulse, or ASM) RCDR4 (VISS/VASS S0 pulse) RCDR5 (VISS/VASS L0 pulse) Figure 27.60 REC-CTL Signal Generation Timing Rev. 0.1, 11/98, page 690 of 975 The 16-bit counter in the REC-CTL circuit continues counting on a clock derived by dividing the system clock s (= fOSC/2) by 4. The counter is cleared on the rise of REF30X in record mode, and on the rise of PB-CTL in rewrite mode. REC-CTL match detection is carried out by comparing the counter value with each RCDR value. RCDR1 to RCDR5 can be written to by software at all times. If RCDR is changed before the respective match detection is performed, match detection is performed using the new value. The value changed after match detection becomes valid on the rise of REF30X following the change. Figure 27.61 shows examples of RCDR change timing. REF30X RCDR4 Counter RCDR2 RCDR1 REC-CTL RCDR1 RCDR2 1 pulse (Short) RCDR1 RCDR4 RCDR1 RCDR4 RCDR4 Interval in which RCDR4 can be written to 0 pulse (Short) RCDR1 Rewritten 0 pulse (Short) Figure 27.61 Example of RCDR Change Timing (Example Showing RCDR4) Rev. 0.1, 11/98, page 691 of 975 27.13.10 Trapezoid Waveform Circuit In rewriting, the trapezoid waveform circuit leaves the rising edge of the already-recorded PBCTL signal intact, but changes the duty cycle. In rewriting, the CTL pulse is written with reference to the rise of PB-CTL. The CTL duty cycle for a rewrite is set in the REC-CTL duty data registers (RCDR2 to RCDR5). Time values T2 to T5 are referenced to the rise of PB-CTL. Figure 27.62 shows the rewrite waveform. RESET PB-CTL Internal bus W W W Clear s/4 UP/DOWN counter (16 bits) RCDR2or4 (12bit) RCDR3or5 (12bit) RCDR1 (12bit) Not used when rewriting Upper 12 bits Compare Compare REC-CTL 1 pulse fall timing REC-CTL 0 pulse fall timing End of writing of one CTL pulse (except VISS) IRRCTL PB-CTL Eliminated pulse New pulse High-impedance interval REC-CTL when rewriting T2 to T5 RCDR2 (BISS/VASS S1 pulse) RCDR3 (VISS/VASS L1 pulse) RCDR4 (VISS/VASS S0 pulse) RCDR5 (VISS/VASS L0 pulse) Figure 27.62 Relationship between REC-CTL and RCDR2 to RCDR5 when Rewriting Rev. 0.1, 11/98, page 692 of 975 27.13.11 Note on CTL Interrupt Following a reset, the CTL circuit is in the VISS discrimination input mode. Depending on the CTL pin states, a false PB-CTL input pulse may be recognized and an interrupt request generated. If the interrupt request will be enabled, first clear the CTL interrupt request flag. 27.14 Frequency Dividers 27.14.1 Overview On-chip frequency dividers are provided for the pulse signal picked up from the control track during playback (the PB-CTL signal), and the pulse signal received from the capstan motor (CFG signal). The CTL frequency divider generates a CTL divided control signal (DVCTL) from the PB-CTL signal, for use in capstan phase control during high-speed search, for example. The CFG frequency divider generates two divided CFG signals (DVCFG for speed control and DVCFG2 for phase control) from the CFG signal, which is first reshaped into a rectangular waveform by a reshaping circuit. The DFG noise canceller is a circuit which considers signal less than 2 as noise and mask it. 27.14.2 CTL Frequency Divider (1) Block Diagram Figure 27.63 shows a block diagram of the CTL frequency divider. Internal bus R/W * DVCTL CEG R/W * DVCTL CEX W * CTLR CTL division register (8bit) EXCTL Edge detector , Down counter (8 bits) UDF DVCTL PB-CTL Figure 27.63 CTL Frequency Divider Rev. 0.1, 11/98, page 693 of 975 (2) Register Configuration Register configuration Table 27.22 shows the register configuration of the CTL dividers. Table 27.22 Register Configuration Name Abbrev. R/W Size Initial Value Address DVCTL control register CTVC R/W Byte Undefined H'FD098 CTL division register CTLR W Byte H'00 H'FD099 DVCTL control register (CTVC) Bit : Initial value : R/W : 7 CEX 6 CEG 5 N 4 N 3 N 2 CFG 1 HSW 0 CTL 0 W 0 W 1 N 1 N 1 N * R * R * R Note: * Initial value is uncertain. The DVCTL control register (CTVC) is a register consisting of the external input signal selection bit and the flags which show the CFG, HSW and CTL levels. Note: It has an undetermined value by a reset or stand-by. Bit 7: DVCTL Signal Generation Selection Bit (CEX) Selects which of the PB-CTL signal or the external input signal is used to generate the DVCTL signal. Bit 7 CEX Description 0 Generates DVCTL signal with PB-CTL signal 1 Generates DVCTL signal with external input signal (Initial value) Bit 6: External Sync Signal Edge Selection Bit (CEG) Selects the edge of the external signal at which the frequency division is made when the external signal was selected to generate DVCTL signal. Bit 6 CEG Description 0 Rising edge 1 Falling edge Rev. 0.1, 11/98, page 694 of 975 (Initial value) Bits 5 to 3: Reserved Bits 5 to 3 are reserved. No write in them is valid. If a read is attempted, an undetermined value is read out. Bit 2: CFG Flag (CFG) Shows the CFG level. Bit 2 CFG Description 0 CFG is at Low level 1 CFG is at High level (Initial value) Bit 1: HSW Flag (HSW) Shows the level of the HSW signal selected by the VFF/NFF bit of the HSW mode register 2 (HSM2). Bit 1 HSW Description 0 HSW is at Low level 1 HSW is at High level (Initial value) Bit 0: CTL Flag (CTL) Shows the CTL level. Bit 0 CTL Description 0 REC or PB-CTL is at Low level 1 REC or PB = CTL is at High level (Initial value) CTL frequency division register (CTLR) Bit : Initial value : R/W : 7 CTL7 6 CTL6 5 CTL5 4 CTL4 3 CTL3 2 CTL2 1 CTL1 0 CTL0 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Rev. 0.1, 11/98, page 695 of 975 The CTL frequency division register (CTLR) is an 8-bit write-only register to set the frequency dividing value (N-1 if divided by N) for PB-CTL. If a read is attempted, an undetermined value is read out. PB-CTL is divided by N at its rising edge. If the register value was 0, no division operation is performed, and the DVCTL signal with the same cycle with PB-CTL is output. It is initialized by a reset or stand-by. (3) Operation During playback, control pulses recorded on the tape are picked up by the control head and input to the CTL pin. The control pulse signal is amplified by a Schmitt amplifier, reshaped, then input to the CTL frequency divider as the PB-CTL signal. This circuit is employed when the control pulse (PB-CTL signal) is used for phase control of the capstan motor. The divided signal is sent as the DVCTL signal to the capstan phase in the servo circuits, system and the Timer R. The CTL frequency divider is a 8-bit reload timer consisting of a reload register and a downcounter. Frequency division is obtained by setting frequency-division data in bits 7 to 0 in the CTL frequency-division data register (CTLR), which is the reload register. When a frequency-division value is written in this reload register, it is also written into the downcounter. The down-counter is decremented on rising edges of the PB-CTL signal. Figure 27.64 shows examples of the PB-CTL and DVCTL waveforms. CTL input signal PB-CTL or external sync signal CTLR=00 CTLR=01 CTLR=02 CTLR : CTL frequency-division data register Figure 27.64 CTL Frequency Division Waveforms Rev. 0.1, 11/98, page 696 of 975 27.14.3 CFG Frequency Divider (1) Block Diagram Figure 27.65 shows a block diagram of the 7-bit CFG frequency divider and its mask timer. Internal bus W R/W R/W W * CDVC CRF CDIVR(7bit) * CDVC MCGin CFG Edge select Down counter (7 bits) DVCFG UDF , * CDVC CMN UDF DVCFG2 Down counter (7 bits) S CMK R PB(ASM)REC * CDVC CDIVR2(7bit) s/1024 s/512 s/256 s/128 Down counter (6 bits) UDF * CDVC DVTRG W CFG clock select CTMR(6bit) R/W W W R Internal bus s = fosc/2 Figure 27.65 CFG Frequency Divider Rev. 0.1, 11/98, page 697 of 975 (2) Register Descriptions Register configuration Table 27.23 shows the register configuration of the CFG frequency division circuit. Table 27.23 Register Configuration Name Abbrev. R/W Size Initial Value Address DVCFG control register CDVC R/W Byte H'60 F'FD09A CFG frequency division register 1 CDIVR1 W Byte H'80 H'FD09B CFG frequency division register 2 CDIVR2 W Byte H'80 H'FD09C DVCFG mask period register CTMR W Byte H'FF H'FD09D DVCFG control register (CDVC) Bit : Initial value : R/W : 7 MCGin 6 -- 5 CMK 4 CMN 3 DVTRG 2 CRF 1 CPS1 0 CPS0 0 R/W* 1 -- 1 R 0 W 0 W 0 W 0 W 0 W Note: * Only 0 can be written CDVC is a 8-bit register to control the capstan frequency division circuit. It is initialized to H'60 by a reset, stand-by or module stop. Bit 7: Mask CFG Flag (MCGin) MCGin is a flag to indicate occurrence of a frequency division signal during the mask timer's mask period. To clear it, write 0. To clear it by software, write 0 after reading 1. Also, setting has the highest priority in this flag. If a condition setting the flag and 0 write occurs simultaneously, the latter is nullified. Bit 7 MCGin Description 0 CFG is in normal operation 1 Shows that DVCFG was detected during masking (runaway detected) Bit 6: Reserved Bit 6 is reserved. No write in it is valid. If a read is attempted, 1 is read out. Rev. 0.1, 11/98, page 698 of 975 (Initial value) Bit 5: CFG Mask Status Bit (CMK) Indicates the status of the mask. It is initialized to 1 by a reset, stand-by or module stop. Bit 5 CMK Description 0 Indicates that the capstan mask timer has released masking 1 Indicates that the capstan mask timer is currently masking (Initial value) Bit 4: CFG Mask Selection Bit (CMN) Selects the turning ON/OFF of the mask function. Bit 4 CMN Description 0 Capstan mask timer function ON 1 Capstan mask timer function OFF (Initial value) Bit 3: PB (ASM) REC Transition Timing Sync ON/OFF Selection Bit (DVTRG) Selects the ON/OFF of the timing sync of the transition from PB (ASM) to REC when the DVCFG2 signal is generated. Bit 3 DVTRG Description 0 PB (ASM) REC transition timing sync ON 1 PB (ASM) REC transition timing sync OFF (Initial value) Bit 2: CFG Frequency Division Edge Selection Bit (CRF) Selects the edge of the CFG signal to be divided. Bit 2 CRF Description 0 Performs frequency division at the rising edge of CFG 1 Performs frequency division at both edges of CFG (Initial value) Rev. 0.1, 11/98, page 699 of 975 Bits 1 and 0: CFG Mask Timer Clock Selection Bit (CPS1, CPS0) Selects the clock source for the CFG mask timer. (s = fosc/2) Bit 1 Bit 0 CPS1 CPS0 Description 0 0 s/1024 1 s/512 0 s/256 1 s/128 1 (Initial value) CFG frequency division register 1 (CDIVR1) Bit : 7 -- 6 CDV16 5 CDV15 4 CDV14 3 CDV13 2 CDV12 1 CDV11 0 CDV10 Initial value : R/W : 1 -- 0 W 0 W 0 W 0 W 0 W 0 W 0 W The CFG frequency division register 1 (CDIVR1) is an 8-bit write-only register to set the division value. If a read is attempted, an undetermined value is read out. Bit 7 is reserved. The frequency division value is written in the reload register and the down counter at the same time. CFG's frequency is divided by N at its rising edge or both edges If the register value was 0, no division operation is performed, and the DVCFG signal with the same input cycle with CFG signal is output. The DVCFG signal is sent to the capstan speed error detector. It is initialized to H'80 by a reset or stand-by together with the capstan frequency division register and the down counter. CFG frequency division register 2 (CDIVR2) Bit : 7 -- 6 CDV26 5 CDV25 4 CDV24 3 CDV23 2 CDV22 1 CDV21 0 CDV20 Initial value : R/W : 1 -- 0 W 0 W 0 W 0 W 0 W 0 W 0 W The CFG frequency division register 2 (CDIVR2) is an 8-bit write-only register to set the division value. If a read is attempted, an undetermined value is read out. Bit 7 is reserved. The frequency division value is written in the reload register and the down counter at the same time. Rev. 0.1, 11/98, page 700 of 975 CFG's frequency is divided by N at its rising edge or both edges If the register value was 0, no division operation is performed, and the DVCFG signal with the same input cycle with CFG is output. The DVCFG2 signal is sent to the capstan speed error detector and the Timer L. The DVCFG2 circuit has no mask timer function. The frequency division counter starts its division operation at the point data was written in CDIVR2. If synchronization is required for phase matching, for example, do it by writing in CDIVR2. If the DVTRG bit of the CDVC register was 0, the register synchronizes with the switching timing from PB (ASM) to REC. It is initialized to H'80 by a reset or stand-by together with the capstan frequency division register and the down counter. DVCFG mask period register (CTMR) Bit : 7 -- 6 -- 5 CPM5 4 CPM4 3 CPM3 2 CPM2 1 CPM1 0 CPM0 Initial value : R/W : 1 -- 1 -- 1 W 1 W 1 W 1 W 1 W 1 W The DVCFG mask period register (CTMR) is an 8-bit write-only register. If a read is attempted, an undetermined value is read out. CTMR is a reload register for the mask timer (down counter). Set in it the mask period of CFG. The mask period is determined by the clock specified by the bits 1 and 0 of CDVC and the set value (N-1). If data is written in CTMR, it is written also in the mask timer at the same time. It is initialized to H'FF by a reset, stand-by or module stop. Mask period = N x clock cycle (3) Operation Frequency divider The CFG pulses output from the capstan motor are sent to internal circuitry as the CFG signal via the zero-cross type comparator. The CFG signal, shaped into a rectangular waveform by a reshaping circuit, is divided by the CFG frequency dividers, and used in servo control. The rising edge or both edges of the CFG signal can be selected for the frequency divider. The CFG frequency dividers comprises a 7-bit frequency divider with a mask timer for capstan speed control (DVCFG signal generator) and a 7-bit frequency divider for capstan phase control (DVCFG2 signal generator). The DVCFG frequency divider consists of a 7-bit reload register (CFG frequency division register1: CDIVR1), a 7-bit down-counter, and a 6-bit mask timer (with settable mask interval). Frequency division is performed by setting the frequency-division value in 7bit CDIVR1. When the frequency- division value is written in CDIVR1, it is also written in the down-counter. After frequency division of a CFG signal for which the edge has been selected, the signal is sent via the mask timer to the capstan speed error detector as the DVCFG signal. Rev. 0.1, 11/98, page 701 of 975 The DVCFG frequency divider consists of a 7-bit reload register (CFG frequency division register 2: CDIVR2) and a 7-bit down-counter. The 7-bit frequency divider does not have a mask timer. Frequency division is performed by setting the frequency-division value in CDIVR2. When the frequency- division value is written in CDVIR2, it is also written in the down-counter. After frequency division of a CFG signal for which the edge has been selected, the signal is sent to the capstan speed error detector and the Timer L as the DVCFG2 signal. Frequency division starts when the frequency-division value is written. When CVTRG bit in CDVC register is set to 0, reloading is executed with the switchiover timing from PB (ASM) mode to REC mode. To switch from REF30 to CREF, change the settings of bit 4 (CR/RF bit) in the capstan phase error detection control register (CPGCR). If synchronization is necessary for phase control, this can be provided by writing the frequency-division value in CDIVR2. The down-counters are decremented on rising edges of the CFG signal when the CRF bit is 0 in the DVCFG control register (CDVC), and on both edges when the CRF bit is 1. Figure 27.66 shows examples of CFG frequency division waveforms. CFG CRF bit=0 CDIVR=00 CRF bit=0 CDIVR=00 CRF bit=0 CDIVR=01 CRF bit=0 CDIVR=02 Figure 27.66 Frequency Division Waveforms Rev. 0.1, 11/98, page 702 of 975 Mask timer The capstan mask timer is a 6-bit reload timer that uses a prescaled clock as a clock source. The mask timer is used for masking DVCFG signal intended for controlling the capstan speeds. The capstan mask timer prevents edge detection to be carried out for an unnecessarily long duration by masking the edge detection for a certain period. The above trouble can result from abnormal revolution (runout) of the capstan motor because its revolution has to cover a wide range speeds from the low/still up to the high speed search. The capstan mask timer is started by output of a pulse edge in the divided CFG signal (DVCFG). While the timer is running, a mask signal disables the output of further DVCFG pulses. The mask signal is shown in Figure 27.67. The mask timer status can be recognized by reading the CMK flag in the DVCFG control register (CDVC). DVCFG Mask Mask timer underflow Figure 27.67 Mask Signal Rev. 0.1, 11/98, page 703 of 975 Figures 27.68 and 27.69 show examples of CFG mask timer operations. CFG (racing) Edge detect Capstan motor mask timer Mask interval Mask interval DVCFG Cleared by wiring 0 after reading 1 MCGin flag Figure 27.68 CFG Mask Timer Operation (When Capstan Motor is Racing) CFG Edge detect Capstan motor mask timer Mask interval Mask interval Figure 27.69 CFG Mask Timer Operation (When Capstan Motor is Operating Normally) Rev. 0.1, 11/98, page 704 of 975 27.14.4 DFG Noise Removal Circuit (1) Block Diagram Figure 27.70 shows the block diagram of the DFG noise removal circuit. DFG Delay circuit Edge detection S Edge detection R Q NCDFG delay = 2 Figure 27.70 DFG Noise Removal Circuit (2) Register Descriptions Register configuration Table 27.24 shows the register configuration of the DFG mask circuit. Table 27.24 Register Configuration Name Abbrev. R/W Size Initial Value Address FG control register FGCR W Byte H'FE H'FD09E FG Control Register (FGCR) Bit : 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- DRF Initial value : 1 1 1 1 1 1 1 0 R/W : -- -- -- -- -- -- -- W Selects the edge of the DFG noise removal signal (NCDFG) to be sent to the drum speed error detector. If a read is attempted, an undetermined value is read out. Bits 7 to 1 are reserved. No write in them is valid. It is initialized to H'FE by a reset, stand-by or module stop. The edge selection circuit is located in the drum speed error detector, and outputs the register output to the drum speed error detector. Bits 7 to 1: Reserved Bits 7 to 1 are reserved. No write in them is valid. If a read is attempted, an undetermined value is read out. Rev. 0.1, 11/98, page 705 of 975 Bit 0: DFG Edge Selection Bit (DRF) Selects the edge of the NCDFG signal used in the drum speed error detector. Bit 0 DRF Description 0 Selects the rising edge of NCDFG signal 1 Selects the falling edge of NCDFG signal (Initial value) (3) Description of Operation The DFG noise removal circuits generates a signal (NCDFG signal) as a result of removing noise (signal fluctuation smaller than 2 ) from the DFG signal. The resulted NCDFG signal is behind the time when the DFG signal was detected by 2 . Figure 27.71 shows the NCDFG signal. Noise DFG NCDFG 2 2 Figure 27.71 NCDFG signal Rev. 0.1, 11/98, page 706 of 975 2 = fosc 27.15 Sync Signal Detector 27.15.1 Overview This block performs detection of the horizontal sync signal (Hsync) and vertical sync signal (Vsync) from the composite sync signal (Csync), noise counting, and field detection. It detects the horizontal and vertical sync signals by setting threshold in the register and based on the servo clock (s = fosc/2). Noise masking is possible during the detection of the horizontal sync signals, and if any Hsync is missing, it can be supplemented. Also, if total volume of the noise detected in one frame of Csync amounted over a specified volume, the detector generates a noise detection interrupt. Note: This circuit detects a pulse with a specific width set by the threshold register. It does not classify or restore the sync signal to a formal one. Rev. 0.1, 11/98, page 707 of 975 Csync W Rev. 0.1, 11/98, page 708 of 975 s/2 Selection of polarity (6bit) V threshold register * VTR W W W Up/Down counter (6-bit) Sync signal detector SEPH (4bit) (8bit) H reload counter (8-bit) H counter (8-bit) W Noise detector (8bit) Noise counter (10-bit) NOIS R/(W) * NDR Noise detection register Noise detection window Supplement control & nozzle mask control circuit (4bit) (6bit) * HTR * HRTR * HPWR * NWR H supplement Supplemented Noise detection H threshold H pulse width start time window register register register register W Internal bus Clear R/W Toggle circuit VD interrupt s = fosc/2 OSCH VD(SEPV) FILED NOISE IRRSNC Noise detection interrupt * SYNCR R/W SYCT NIS/VD Field detector FLD R 27.15.2 Block Diagram Figure 27.72 shows the block diagram of the sync signal detector. Figure 27.72 Block Diagram of the Sync Signal Detector 27.15.3 Pin Configuration Table 27.25 shows the pin configuration of the sync signal detector. Table 27.25 Pin Configuration Name Abbrev. I/O Function Composite sync signal input pin Csync Input Composite sync signal input 27.15.4 Register Configuration Table 27.26 shows the register configuration of the sync signal detector. Table 27.26 Register Configuration Name Abbrev. R/W Size Initial Value Address Vertical sync signal threshold register VTR W Byte H'C0 H'FD0B0 Horizontal sync signal threshold register HTR W Byte H'F0 H'FD0B1 H supplement start time setting register HRTR W Byte H'00 H'FD0B2 Supplemented H pulse width setting register HPWR W Byte H'F0 H'FD0B3 Noise detection window setting register NWR W Byte H'C0 H'FD0B4 Noise detector NDR W Byte H'00 H'FD0B5 R/W Byte H'F8 H'FD0B6 Sync signal control register SYNCR Rev. 0.1, 11/98, page 709 of 975 27.15.5 Register Descriptions (1) Vertical Sync Signal Threshold Register (VTR) Bit : 7 -- 6 -- 5 VTR5 4 VTR4 3 VTR3 2 VTR2 1 VTR1 0 VTR0 Initial value : R/ W : 1 -- 1 -- 0 W 0 W 0 W 0 W 0 W 0 W Sets the threshold for the vertical sync signal when the signal is detected from the composite sync signal. The threshold is set by bits 5 to 0 (VTR5 to VTR0). Bits 7 and 6 are reserved. VTR is an 8-bit write-only register to set the division value. If a read is attempted, an undetermined value is read out. It is initialized to H'C0 by a reset, stand-by or module stop. Rev. 0.1, 11/98, page 710 of 975 (2) Horizontal Sync Signal Threshold Register (HTR) Bit : Initial value : R/W : 7 6 5 4 -- -- -- -- 3 HTR3 2 HTR2 1 HTR1 0 HTR0 1 -- 1 -- 1 -- 1 -- 0 W 0 W 0 W 0 W Sets the threshold for the horizontal sync signal when the signal is detected from the composite sync signal. The threshold is set by bits 3 to 0 (HTR3 to HTR0). Bits 7 and 4 are reserved. HTR is an 8-bit write-only register to set the division value. If a read is attempted, an undetermined value is read out. It is initialized to H'F0 by a reset, stand-by or module stop. Figure 27.73 shows threshold and separated sync signals. Hpuls 1/2*Hpuls Hpuls Csync TH TH Counter value VVTH HVTH H'00 SEPH SEPV VD interrupt [Legend] TH : Cycle of the horizontal sync signal Hpuls : Pulse width of the horizontal sync signal VVTH : Value set as the threshold of the vertical sync signal HVTH : Value set as the threshold of the horizontal sync signal SEPV : Detected vertical sync signal SEPH : Detected horizontal sync signal (before supplement) Figure 27.73 Threshold and Separated Sync Signals Rev. 0.1, 11/98, page 711 of 975 Example The set values to detect the vertical and horizontal sync signals (SEPV, SEPH) from Csync are required to meet the following conditions. Assumed that the set values in VTHR register were VVTH and HVTH, (VVTH-1) x 2/s > Hpuls (HVTH-2) x 2/s Hpuls/2 < (HVTH-1) ) x 2/s Where, Hpuls is pulse width (s) of the horizontal sync signal, and s is servo clock (fosc/2). Thus, if s = 5 MHz, NTSC system is used, (VVTH-1) x 0.4s > 4.7s symbol 92 \f "Symbol" \s 10}VVTH symbol 179 \f "Symbol" \s 10 H'D (VVTH-2) symbol 180 \f "Symbol" \s 10x 0.4symbol 109 \f "Symbol" \s 10s symbol 163 \f "Symbol" \s 10 2.35symbol 109 \f "Symbol" \s 10s < (HVTH-1) symbol 180 \f "Symbol" \s 10x 0.4symbol 109 \f "Symbol" \s 10s symbol 92 \f "Symbol" \s 10}VVTH symbol 179 \f "Symbol" \s 10 H'7 Note: This circuits detects the pulse with the width set in VTHR register. If a noise pulse with the width greater than the set value was input, the circuit regards that it detected a sync signal. Rev. 0.1, 11/98, page 712 of 975 (3) H Supplement Start Time Setting Register (HRTR) Bit : Initial value : R/W : 7 HRTR7 6 HRTR6 5 HRTR5 4 HRTR4 3 HRTR3 2 HRTR2 1 HRTR1 0 HRTR0 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Sets the timing to generate a supplementary pulse if a drop-out of a pulse of the horizontal sync signal occurred. HRTR is an 8-bit write-only register. If a read is attempted, an undetermined value is read out. It is initialized to H'00 by a reset, stand-by or module stop. ((Value of HRTR7-0) + 1) symbol 180 \f "Symbol" \s 10x 2/symbol 102 \f "Symbol" \s 10s = TH where, TH is the cycle of the horizontal sync signal (symbol 109 \f "Symbol" \s 10s), and symbol 102 \f "Symbol" \s 10s is the servo clock (fosc/2). Whether the horizontal sync signal exists or not is determined one clock before the supplementary pulse is generated. Accordingly, set to HRTR7 to HRTR0 a value obtained from the equation shown above plus one. Also, HRTR7-HRTR0 sets the noise mask period. If the horizontal sync signal had the normal pulses, it is masked in the mask period. The start and the end of the mask period are computed frm the rising edge of OSCH and SEPH, respectively. See figure 27.75. (4) Complementary H Pulse Width Setting Register (HPWR) Bit : 7 -- 6 -- 5 -- 4 -- 3 HPWR3 2 HPWR2 1 HPWR1 0 HPWR0 Initial value : R/W : 1 -- 1 -- 1 -- 1 -- 0 W 0 W 0 W 0 W HPWR sets the pulse width of the complementary pulse which is generated if a drop-out of a pulse of the horizontal sync signal occurs. Bits 7 to 4 are reserved. HRWR is an 8-bit write-only register. If a read is attempted, an undetermined value is read out. It is initialized to H'F0 by a reset or stand-by. ((Value of HPWR3-0) + 1) symbol 180 \f "Symbol" \s 10x 2/symbol 102 \f "Symbol" \s 10s = Hpulse Where, Hpuls is the pulse width of the horizontal sync signal (symbol 109 \f "Symbol" \s 10s), and symbol 102 \f "Symbol" \s 10s is the servo clock (fosc/2). Rev. 0.1, 11/98, page 713 of 975 (5) Noise Detection Window Setting Register (NWR) Bit : 7 -- 6 -- 5 NWR5 4 NWR4 3 NWR3 2 NWR2 1 NWR1 0 NWR0 Initial value : R/W : 1 -- 1 -- 0 W 0 W 0 W 0 W 0 W 0 W NWR sets the period (window) when the drop-out of the pulse of the horizontal sync signal is detected and the noise is counted. Set the timing of the noise detection window in bits 5 to 0. Bits 7 and 6 are reserved. NWR is an 8-bit write-only register. If a read is attempted, an undetermined value is read out. It is initialized to H'C0 by a reset, stand-by or module stop. Set the value of the noise detection window timing according to the following equation. ((Value of NWR5-0) + 1) symbol 180 \f "Symbol" \s 10x 2/symbol 102 \f "Symbol" \s 10s = 1/4 symbol 180 \f "Symbol" \s 10x TH Where, TH is the pulse width of the horizontal sync signal (symbol 109 \f "Symbol" \s 10s), and symbol 102 \f "Symbol" \s 10s is the servo clock (fosc/2). It is recommended that this timing value is set at about 1/4 of the cycle of the horizontal sync signal. (6) Noise Detection Register (NDR) Bit : Initial value : R/W : 7 NDR7 6 NDR6 5 NDR5 4 NDR4 3 NDR3 2 NDR2 1 NDR1 0 NDR0 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W NDR sets the noise detection level when the noise of the horizontal sync signal is detected (when NWR is set). Set the noise detection level in bits 7 to 0. NDR is an 8-bit write-only register. No read is valid. If a read is attempted, an undetermined value is read out. It is initialized to H'00 by a reset, stand-by or module stop. The noise detector takes counts of the drop-outs of the horizontal sync signals and the noises within the pulses, and if they amount to a count greater than four times of the value set in NDR7-0, the detector sets the NOIS flag in the sync signal control register (SYNCR). Set the noise detection level at 1/4 of the noise counts in one frame. The noise counter is cleared whenever Vsync was detected twice. See section 27.15.6, Noise Detection for the details of the noise detection window and the noise detection level. Rev. 0.1, 11/98, page 714 of 975 (7) Sync Signal Control Register (SYNCR) Bit : 7 -- 6 -- 5 -- 4 -- 3 NIS/VD 2 NOIS 1 FLD 0 SYCT Initial value : R/W : 1 -- 1 -- 1 -- 1 -- 1 R/W 0 R/(W)* 0 R 0 R/W Note: * Only 0 can be written SYNCR controls the noise detection, field detection, polarity of the sync signal input, etc. SYNCR is an 8-bit register. It is initialized to H'F8 by a reset, stand-by or module stop. Bits 7 to 4 are reserved. No write is valid. Bit 1 is valid for read only. Bits 7 to 4: Reserved Bits 7 to 4 are reserved. Writes are disabled. If a read is attempted, an undetermined value is read out. Bit 3: Interrupt Selection Bit (NIS/VD) Selects whether an interrupt request is generated when a noise level was detected or when the VD signal was detected. Bit 3 NIS/VD Description 0 Interrupt at the noise level 1 Interrupt at VD (Initial value) Bit 2: Noise Detection Flag (NOIS) NOIS is a status flag indicating that the noise counts reached at more than four times of the value set in NDR. The flag is cleared only by writing 0 after reading 1. Care is required because it is not cleared automatically. Bit 2 NOIS Description 0 Noise count is smaller than four times of the value set in NDR 1 Noise count is greater than four times of the value set in NDR (Initial value) Rev. 0.1, 11/98, page 715 of 975 Bit 1: Field Detection Flag (FLD) Indicates whether the field currently being scanned is even or odd. See figure 27.74. Bit 1 FLD Description 0 Odd field 1 Even field (Initial value) Bit 0: Sync Signal Polarity Selection Bit (SYCT) Selects the polarity of the sync signal (Csync) to be input. Bit 0 SYCT Polarity symbol Description 0 Positive (Initial value) 1 Rev. 0.1, 11/98, page 716 of 975 Negative Composite sync signal SEPV Noise detection window Field detection flag (FLD) Even Field (a) Even field (EVEN) Composite sync signal SEPV Noise detection window Field detection flag (FLD) Odd field (b) Odd field (ODD) Figure 27.74 Field Detection Rev. 0.1, 11/98, page 717 of 975 27.15.6 Noise Detection If drop-out of a pulse of the horizontal sync signal occurred, set a complementary pulse at the timing set in HPWR and with the set pulse width. Set the noise detection window with HWR of about 1/4 of the horizontal sync signal, and the pulse with equal High and Low periods will be obtained. (1) Example of Setting Assumed that a complementary pulse is set when fosc = 10MHz under the conditions symbol 102 \f "Symbol" \s 10s = 5MHz, NTSC:TH = 63.6 (symbol 109 \f "Symbol" \s 10s) and Hpuls = 4.7 (symbol 109 \f "Symbol" \s 10s), the set values of the complementary pulse timing (HRTR7-0), complementary pulse width (HPWR3-0) and noise detection window timing (NWR5-0) are expressed by the following equations. (Value of HRTR7-0) symbol 180 \f "Symbol" \s 10x 2/symbol 102 \f "Symbol" \s 10s = TH ((Value of HPWR3-0) + 1) symbol 180 \f "Symbol" \s 10x 2/symbol 102 \f "Symbol" \s 10s = Hpuls ((Value of NWR5-0) + 1) symbol 180 \f "Symbol" \s 10x 2/symbol 102 \f "Symbol" \s 10s = 1/4 symbol 180 \f "Symbol" \s 10x TH Where, TH is the cycle of the horizontal sync signal (symbol 109 \f "Symbol" \s 10s), Hpuls is the pulse width of the horizontal sync signal (symbol 109 \f "Symbol" \s 10s) and symbol 102 \f "Symbol" \s 10s is the servo clock (Hz) (fosc/2). Accordingly, (Value of HRTR7-0) symbol 180 \f "Symbol" \s 10x 0.4 (symbol 109 \f "Symbol" \s 10s) = 63.6 (symbol 109 \f "Symbol" \s 10s) symbol 92 \f "Symbol" \s 10}HRTR7-0=H'9F ((Value of HPWR3-0) + 1) symbol 180 \f "Symbol" \s 10x 0.4 (symbol 109 \f "Symbol" \s 10s) = 4.7 (symbol 109 \f "Symbol" \s 10s) symbol 92 \f "Symbol" \s 10}HRTR3-0=H'B ((Value of NWR5-0) + 1) symbol 180 \f "Symbol" \s 10x 0.4 (symbol 109 \f "Symbol" \s 10s) = 16 (symbol 109 \f "Symbol" \s 10s) symbol 92 \f "Symbol" \s 10}NWR5-0=H'27 Also, the noise mask period is computed as follows. ((Value of HRTR7-0) + 1) symbol 45 \f "Symbol" \s 10- 24) symbol 180 \f "Symbol" \s 10x 2/symbol 102 \f "Symbol" \s 10s = 54 (symbol 109 \f "Symbol" \s 10s) Where, 24 is a constant required for a structural reason. Figure 27.75 shows the set period for HRTR, HPWR and NWR. Rev. 0.1, 11/98, page 718 of 975 Set period for HRTR, HPWR and NWR Drop-out of the horizontal sync signal TH TH SEPH c H counter a b H'00 OVF H'E8 a H reload counter c Mask period Mask period Don't mask immediately after complement. Mask period Mask period Noise mask for H counter TM OSCH Mask period Mask period Noise mask for OSCH Mask period Do mask also immediately after complement. Mask period Noise detection window Period determined by NWR5 to NWR0 period determined by a and a [Legend] SEPH OSCH a b c a, b, c H'E8 TH TM Period determined by HRTR7 to HRTR0 period determined by c and H'E8 Period determined by HPWR3 to HPER0 period determined by b : Horizontal sync signal after detection : Horizontal sync signal after complement : Value set for the noise detection window (NWR5 to NWR0) : Value set for the pulse width of the horizontal sync signal (NPWR3 to NPWR0) : Value set for complement timing (HRTR7 to HRTR0) : Complements of 1 of a,b,c, respectively :Complement of 2 of multiplier 24 in the equation for the noise mask period (The noise mask period ends 24 counts before the overflow of H reload counter.) : Cycle of the horizontal sync signal (NTSC:63.6 [ms], PAL:64[ms]) : Timing at which the noise mask period ends. Figure 27.75 Set Period for HRTR, HPWR and NWR Rev. 0.1, 11/98, page 719 of 975 (2) Operation to Detect Noise The noise detector considers an irregular pulse of the composite sync signal (Csync) and a chip of a pulse of the horizontal sync signal within a frame as noise. The noise counter takes counts of the irregular pulses during the High period of the noise detection window and the chips and drop-outs of the horizontal sync signal pulses during the Low period. Also, it counts more than one irregular pulses as one. The noise counter is cleared at every frame (Vsync is detected twice). The equivalent pulse contained in 9H of the vertical sync signal is counted also as an irregular pulse. It sets the noise detection flag (NOIS) in the sync signal control register (SYNCR) at 1 if the count of the irregular pulses + the count of the pulse chips and drop-outs of the horizontal sync signal > 4 symbol 180 \f "Symbol" \s 10x (value of NDR7 to 0). See section 27.15.5 (7), Sync Signal Control Register (SYNCR) for the NOIS bit. Figure 27.76 shows the operation of the noise detection. Noise Csync Noise detection window Noise detection level Noise counter Noise detection flag is set. Noise detection flag (NOIS) NOIS : Bit 3 of the sync signal control register (SYNCR) Figure 27.76 Operation of the Noise Detection Rev. 0.1, 11/98, page 720 of 975 27.15.7 Activation of the Sync Signal Detector The sync signal detector starts operation by release of reset, or by accepting input of a sync signal after its transition from the power down mode to the active mode and release of module stop. The signal given to the detector is the polarity pulse assigned by the SYCT bit of the sync signal control register (SYNCR). The detector starts operation even if this pulse was a noise pulse with a width short of the regular width. The minimum pulse width which can activate the detector is not constant depending on the internal operation of the input circuit. Accordingly, if the assured activation of the detector is required, input a pulse with a width greater than 4/symbol 102 \f "Symbol" \s 10s (symbol 102 \f "Symbol" \s 10s = fosc/2 (Hz)). In such a case, care is required to noise, etc., because even a pulse with a width smaller than 4symbol 102 \f "Symbol" \s 10/s may cause activation. Rev. 0.1, 11/98, page 721 of 975 27.16 Servo Interrupt 27.16.1 Overview The interrupt exception processing of the servo module is started by one of ten factors, i.e. the drum speed error detector (symbol 180 \f "Symbol" \s 10x2), drum phase error detector, capstan speed error detector (symbol 180 \f "Symbol" \s 10x2), capstan phase error detector, HSW timing generator (symbol 180 \f "Symbol" \s 10x2), sync detector and CTL circuit. For these interrupt factors, see each of their circuit sections of the manual. Also, see section 5. Exception Handling. 27.16.2 Register Configuration Table 27.27 shows the list of the registers which control the interrupt of the servo section. Table 27.27 Registers which Control the Interrupt of the Servo Section Name Abbrev. R/W Size Initial Value Address Servo interrupt permission SIENR1 register 1 R/W Byte H'00 H'FD0B8 Servo interrupt permission SIENR2 register 2 R/W Byte H'FC H'FD0B9 Servo interrupt request register 1 SIRQR1 R/W Byte H'00 H'FD0BA Servo interrupt request register 2 SIRQR2 R/W Byte H'FC H'FD0BB 27.16.3 Register Description (1) Servo Interrupt Permission Register 1 (SIENR1) Bit : Initial value : R/W : 7 IEDRM3 6 IEDRM2 5 IEDRM1 4 IECAP3 3 IECAP2 2 IECAP1 1 IEHSW2 0 IEHSW1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W SIENR1 controls the permission and prohibition of the interrupt of the servo section. SIENR1 is an 8-bit read/write register. It is initialized to H'00 by a reset, stand-by or module stop. Rev. 0.1, 11/98, page 722 of 975 Bit 7: Drum Phase Error Detection Interrupt Permission Bit (IEDRM3) Bit 7 IEDRM3 Description 0 Prohibits the interrupt to the request through IRRDRM3 1 Permits the interrupt to the request through IRRDRM3 (Initial value) Bit 6: Drum Speed Error Detection (lock detection) Interrupt Permission Bit (IEDRM2) Bit 6 IEDRM2 Description 0 Prohibits the interrupt to the request through IRRDRM2 1 Permits the interrupt to the request through IRRDRM2 (Initial value) Bit 5: Drum Speed Error Detection (OVF, latch) Interrupt Permission Bit (IEDRM1) Bit 5 IEDRM1 Description 0 Prohibits the interrupt to the request through IRRDRM1 1 Permits the interrupt to the request through IRRDRM1 (Initial value) Bit 4: Capstan Phase Error Detection Interrupt Permission Bit (IECAP3) Bit 4 IECAP3 Description 0 Prohibits the interrupt to the request through IRRCAP3 1 Permits the interrupt to the request through IRRCAP3 (Initial value) Bit 3: Capstan Speed Error Detection (lock detection) Interrupt Permission Bit (IECAP2) Bit 3 IECAP2 Description 0 Prohibits the interrupt to the request through IRRCAP2 1 Permits the interrupt to the request through IRRCAP2 (Initial value) Rev. 0.1, 11/98, page 723 of 975 Bit 2: Capstan Speed Error Detection (OVF, latch) Interrupt Permission Bit (IECAP1) Bit 2 IECAP1 Description 0 Prohibits the interrupt to the request through IRRCAP1 1 Permits the interrupt to the request through IRRCAP1 (Initial value) Bit 1: HSW Timing Generation (counter clear, capture) Interrupt Permission bit (IEHSW2) Bit 1 IEHSW2 Description 0 Prohibits the interrupt to the request through IRRHSW2 1 Permits the interrupt to the request through IRRHSW2 (Initial value) Bit 0: HSW Timing Generation (OVW, matching, STRIG) Interrupt Permission bit (IEHSW1) Bit 0 IEHSW1 Description 0 Prohibits the interrupt to the request through IRRHSW1 1 Permits the interrupt to the request through IRRHSW1 Rev. 0.1, 11/98, page 724 of 975 (Initial value) (2) Servo Interrupt Permission Register 2 (SIENR2) Bit : 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 IESNC 0 IECTL Initial value : R/W : 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 0 R/W 0 R/W SIENR2 controls the permission and prohibition of the interrupt of the servo section. SIENR2 is an 8-bit read/write register. It is initialized to H'FC by a reset, stand-by or module stop. Bits 7 to 2: Reserved Bits 7 to 2 are reserved. No read or write is valid. If a read is attempted, an undetermined value is read out. Bit 1: Vertical Sync Signal Interrupt Permission Bit (IESNC) Bit 1 IESNC Description 0 Prohibits the interrupt (interrupt to the vertical sync signal) to the request through IRRSNC (Initial value) 1 Permits the interrupt to the request through IRRSNC Bit 0: CTL Interrupt Permission Bit (IECTL) Bit 0 IECTL Description 0 Prohibits the interrupt to the request through IRRCTL 1 Permits the interrupt to the request through IRRCTL (Initial value) Rev. 0.1, 11/98, page 725 of 975 (3) Servo Interrupt Request Register 1 (SIRQR1) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 IRRDRM3 IRRDRM2 IRRDRM1 IRRCAP3 IRRCAP2 IRRCAP1 IRRHSW2 IRRHSW1 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* Note: * Only 0 can be written to clear the flag. SIRQR1 displays an occurrence of an interrupt request of the servo section. If the interrupt request occurred, the corresponding bit is set to 1. SIRQR1 is an 8-bit read/write register. Writing is allowed only in the case of writing 0 to clear the flag. It is initialized to H'00 by a reset, stand-by or module stop. Bit 7: Drum Phase Error Detector Interrupt Request Bit (IRRDRM3) Bit 7 IRRDRM3 Description 0 No interrupt request from the drum phase error detector 1 Interrupt requested from the drum phase error detector (Initial value) Bit 6: Drum Speed Error Detector (lock detection) Interrupt Request Bit (IRRDRM2) Bit 6 IRRDRM2 Description 0 No interrupt request from the drum speed error detector (lock detection) (Initial value) 1 Interrupt requested from the drum speed error detector (lock detection) Rev. 0.1, 11/98, page 726 of 975 Bit 5: Drum Speed Error Detector (OVF, latch) Interrupt Request Bit (IRRDRM1) Bit 5 IRRDRM1 Description 0 No interrupt request from the drum speed error detector (OVF, latch) (Initial value) 1 Interrupt requested from the drum speed error detector (OVF, latch) Bit 4: Capstan Phase Error Detector Interrupt Request Bit (IRRCAP3) Bit 4 IRRCAP3 Description 0 No interrupt request from the capstan phase error detector 1 Interrupt requested from the capstan phase error detector (Initial value) Bit 3: Capstan Speed Error Detector (lock detection) Interrupt Request Bit (IRRCAP2) Bit 3 IRRCAP2 Description 0 No interrupt request from the capstan speed error detector (lock detection) (Initial value) 1 Interrupt requested from the drum speed error detector (lock detection) Bit 2: Drum Speed Error Detector (OVF, latch) Interrupt Request Bit (IRRCAP1) Bit 2 IRRCAP1 Description 0 No interrupt request from the capstan speed error detector (OVF, latch)(Initial value) 1 Interrupt requested from the capstan speed error detector (OVF, latch) Bit 1: HSW Timing Generator (counter clear, capture) Interrupt Permission Bit (IRRHSW2) Bit 1 IRRHSW2 Description 0 No interrupt request from the HSW timing generator (counter clear, capture) (Initial value) 1 Interrupt requested from the HSW timing generator (counter clear, capture) Rev. 0.1, 11/98, page 727 of 975 Bit 0: HSW Timing Generator (OVW, matching, STRIG) Interrupt Permission Bit (IRRHSW1) Bit 0 IRRHSW1 Description 0 No interrupt request from the HSW timing generator (OVW, matching, STRIG) (Initial value) 1 Interrupt requested from the HSW timing generator (OVW, matching, STRIG) (4) Servo Interrupt Request Register 2 (SIRQR2) Bit : Initial value : R/W : 7 6 5 4 3 2 -- -- -- -- -- -- 1 IRRSNC 0 IRRCTL 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 0 R/(W)* 0 R/(W)* Note: * Only 0 can be written to clear the flag. SIRQR2 displays an occurrence of an interrupt request of the servo section. If the interrupt request occurred, the corresponding bit is set to 1. SIRQR2 is an 8-bit read/write register. Writing 0 after reading 1 is allowed; no other writing is allowed. It is initialized to H'FC by a reset, stand-by or module stop. Bits 7 to 2: Reserved Bits 7 to 2 are reserved. No read or write is valid. If a read is attempted, an undetermined value is read out. Rev. 0.1, 11/98, page 728 of 975 Bit 1: Vertical Sync Signal Interrupt Request Bit (IRRSNC) Bit 1 IRRSNC Description 0 No interrupt request from the sync signal detector (VD, noise) 1 Interrupt requested from the sync signal detector (VD, noise) (Initial value) Bit 0: CTL Signal Interrupt Request Bit (IRRCTL) Bit 0 IRRCTL Description 0 No interrupt request from CTL 1 Interrupt requested from CTL (Initial value) Rev. 0.1, 11/98, page 729 of 975 Rev. 0.1, 11/98, page 730 of 975 Section 28 Electrical Characteristics 28.1 Absolute Maximum Ratings Table 28.1 lists the absolute maximum ratings. Table 28.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage Vcc -0.3 to +0.7 V Input voltage (ports other than port 0) Vin -0.3 to Vcc+0.3 V Input voltage (port 0) Vin -0.3 to AVcc+0.3 V A/D converter power supply voltage AVcc -0.3 to +7.0 V A/D converter input voltage AVin -0.3 to AVcc+0.3 V Servo power supply voltage SVcc -0.3 to +7.0 V Servo amplifier input voltage Vin -0.3 to SVcc + 0.3 V Operating temperature Topr -20 to +75 C Operating temperature (At Flash memory program/erase) Topr 0 to +75 C Storage temperature Tstr -55 to +125 C Notes: 1. Permanent damage may occur to the chip if absolute maximum ratings are exceeded. Normal operation should be under the conditions specified in Electrical Characteristics. Exceeding these values can result in incorrect operation and reduced reliability. 2. All voltages are relative to Vss = SVss = AVss = 0.0 V. Rev. 0.1, 11/98, page 731 of 975 28.2 Electrical Characteristics of HD64F2194 28.2.1 DC Characteristics of HD64F2194 Table 28.2 (1) DC Characteristics of HD64F2194 (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Values Item Symbol Applicable Pins Test Conditions Min Typ Max Unit Input high voltage VIH Vcc=2.7 to 5.5V 0.9 Vcc Vcc+0.3 V 0.8 Vcc Vcc+0.3 0.9 Vcc Vcc+0.3 0.8 Vcc Vcc+0.3 Vcc-0.5 Vcc+0.3 Vcc-0.3 Vcc+0.3 0.7 Vcc Vcc+0.3 0.8 Vcc Vcc+0.3 0.7 Vcc Vcc+0.3 MD0 5(6, 10,, FWE, ,&, ,54 to ,54 Vcc=2.7 to 5.5V SCK1, SCK2, SI1, SI2, &6, FTIA, FTIB, FTIC, FTID, TRIG, TMBI, $'75* OSC1, X1 Vcc=2.7 to 5.5V P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PS0 to PS4 Vcc=2.7 to 5.5V Csync Note: Do not open the AVcc and AVss pin even when the A/D converter is not in use. Rev. 0.1, 11/98, page 732 of 975 Notes Table 28.2 (2) DC Characteristics of HD64F2194 (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Values Item Symbol Applicable Pins Test Conditions Min Typ Max Unit Input low voltage VIL Vcc=2.7 to 5.5 -0.3 0.1 Vcc V -0.3 0.2 Vcc -0.3 0.1 Vcc -0.3 0.2 Vcc -0.3 0.5 -0.3 0.3 -0.3 0.3 Vcc -0.3 0.2 Vcc -0.3 0.2 Vcc MD0 5(6, 10,, FWE, ,&, ,54 to ,54 Vcc=2.7 to 5.5 SCK1, SCK2, SI1, SI2, &6, FTIA, FTIB, FTIC, FTID, TRIG, TMBI, Notes $'75* OSC1, X1 Vcc=2.7 to 5.5 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PS0 to PS4 Vcc=2.7 to 5.5 Csync Note: Do not open the AVcc and AVss pin even when the A/D converter is not in use. Rev. 0.1, 11/98, page 733 of 975 Table 28.2 (3) DC Characteristics of HD64F2194 (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Values Item Symbol Applicable Pins Output high VOH voltage Output low VOL voltage Test Conditions Min Typ Max Unit Vcc-1.0 V -IOH=0.5mA Vcc- 0.5 V -IOH=0.1mA Vcc=2.7 to 5.5V Vcc-0.5 V 0.6 V IOL=0.4mA Vcc=2.7 to 5.5V 0.4 V IOL=20mA 1.5 V IOL=1.6mA 0.6 V IOL=0.4mA Vcc=2.7 to 5.5V 0.4 V SO1, SO2, SCK1, -IOH=1.0mA SCK2, PWM1, PWM2, PWM3, PWM4, PWM14, STRB, BUZZ, TMO, TMOW, FTOA, FTOB, PPG70 to PPG77, RP0 to RP7, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PS0 to PS4 IOL=1.6mA SO1, SO2, SCK1, SCK2, PWM1, PWM2, PWM3, PWM4, PWM14, STRB, BUZZ, TMO, TMOW, FTOA, FTOB, PPG70 to PPG77, RP0 to RP7, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, PS0 to PS4 P80 to P87, Rev. 0.1, 11/98, page 734 of 975 Notes Reference value Table 28.2 (4) DC Characteristics of HD64F2194 (Conditions: Vcc = AVcc = 2.7 to 5.5 V, Vss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Values Item Symbol Applicable Pins Input /output leakage current IIL Test Conditions Min Typ Max Unit 1.0 A 5(6, 10,, FWE, ,54 to Vin=0.5 to Vcc- 0.5V ,54, ,& 1.0 Vin=0.5 to Vcc- 0.5V 1.0 P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P53, P60 to P67, P70 to P77, P80 to P87, Vin=0.5 to Vcc- 0.5V 1.0 P00 to P07, AN8 to ANB Vin=0.5 to AVcc-0.5V 1.0 MD0, OSC1 SCK1, SCK2, SI1, SI2, &6, FTIA, FTIB, FTIC, FTID, TRIG, TMBI, Vin=0.5 to Vcc- 0.5V Notes $'75* Pull-up MOS current -Ip P10 to P17, P20 to P27, P30 to P37, Vcc=5.0V, Vin=0V 50 300 A Input capacity Cin All input pins except power supply, P13, P23, P24 and analog system pins fin=1 MHz, Vin=0V, Ta=25 C 15 pF P13, P23, P24 fin=1 MHz, Vin=0V, Ta=25 C 20 pF Note: Note 3 3. Current value when the relevant bit of the pull-up MOS select register (PUR1 to PUR3) is set to 1. Rev. 0.1, 11/98, page 735 of 975 Table 28.2 (5) DC Characteristics of HD64F2194 (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Values Item Applicabl Test Symbol e Pins Conditions Active IOPE mode current dissipa-tion (CPU operating) Vcc Min Typ Max Unit Notes Vcc=5V, fOSC=10 MHz, High-speed mode 50 70 mA Note 4 Vcc=5V, fOSC=10 MHz, Medium-speed mode (1/64) 35 mA Reference value V-active IRESP mode current dissipa-tion (reset) Vcc Vcc=5V, fOSC=10 MHz -- 30 45 mA Note 4 Sleep mode ISLEEP current dissipa-tion Vcc Vcc=5V, fOSC=10 MHz High-speed mode 20 30 mA Note 4 Subactive ISUB mode current dissipa-tion Vcc Vcc=2.7V, 32kHz With crystal oscillator ( sub=w/2) 90 150 A Note 4 Vcc=2.7V, 32kHz With crystal oscillator ( sub=w/8) 40 Vcc=2.7V, 32kHz With crystal oscillator ( sub=w/2) 15 30 Vcc=2.7V, 32kHz With crystal oscillator ( sub=w/8) 10 Subsleep ISUBSLP mode current dissipa-tion Note: Vcc Reference value, Note 4 A 4. The current on the pull-up MOS or the output buffer excluded. Rev. 0.1, 11/98, page 736 of 975 Note 4 Reference value, Note 4 Table 28.2 (6) DC Characteristics of HD64F2194 (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Values Applicable Symbol Pins Item Watch IWATCH mode current dissipa-tion Vcc Standby ISTBY mode current dissipa-tion Vcc RAM data retaining voltage in standby mode Vcc Note: VSTBY Test Conditions Min Typ Max Unit Notes Vcc=2.5V, 32kHz With crystal oscillator 5 10 A Note 4 Vcc=5.0V, 32kHz With crystal oscillator 10 A Reference value Note 4 X1=Vcc, 32kHz Without crystal oscillator 5 A Note 4 2.0 V 4. The current on the pull-up MOS or the output buffer excluded. Rev. 0.1, 11/98, page 737 of 975 Table 28.2 (7) Pin Status at Current Dissipation Measurement Mode RES pin Internal State Pin Oscillator Pin Active mode High-speed, mediumspeed Vcc Operating Vcc Main clock: Crystal oscillator Sub clock: X1 pin = Vcc Sleep mode High-speed, mediumspeed Vcc CPU and servo circuits stopped. Vcc Reset Vss Reset Vcc Standby mode Vcc All stopped Vcc Subactive mode Vcc CPU and timer A operating Vcc Subsleep mode Vcc Timer A operating Vcc Watch mode Vcc Timer A operating Vcc Rev. 0.1, 11/98, page 738 of 975 Main clock: Crystal oscillator Sub clock: Crystal oscillator Table 28.2 (8) Bus Drive Characteristics of HD64F2194 (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Applicable pin: SCL, SDA Values Item Schmitt trigger input Applicable Symbol Pins VT- Test Conditions SCL, SDA + VT + T V -VT- Min Typ Max Unit 0.2Vcc V 0.7Vcc V 0.05Vcc V Input High level voltage VIH SCL, SDA 0.7Vcc Vcc+0.5 V Input Low level voltage VIL SCL, SDA -0.5 0.2Vcc V Output Low VOL level voltage SCL, SDA IOL=8mA 0.5 V IOL=3mA 0.4 20+ 0.1Cb 250 SCL and tof SDA output fall time SCL, SDA Notes ns Rev. 0.1, 11/98, page 739 of 975 28.2.2 Allowable Output Currents of HD64F2194 The specifications for the digital pins are shown below. Table 28.3 Allowable Output Currents (Conditions: Vcc = 2.7 to 5.5 V, Vss = 0.0 V, Ta = -20 to +75C) Item Symbol Value Unit Notes Allowable input current (to chip) IO 2 mA 1 Allowable input current (to chip) IO 22 mA 2 Allowable input current (to chip) IO 10 mA 3 Allowable output current (from chip) -IO 2 mA 4 Total allowable input current (to chip) IO 80 mA 5 Total allowable output current (from chip) -IO 50 mA 6 Notes: 1. The allowable input current is the maximum value of the current flowing from each I/O pin to VSS (except for port 8, SCL and SDA). 2. The allowable input current is the maximum value of the current flowing from each I/O pin to VSS. This applies to port 8. 3. The allowable input current is the maximum value of the current flowing from each I/O pin to VSS. This applies to SCL and SDA. 4. The allowable output current is the maximum value of the current flowing from VCC to each I/O pin. 5. The total allowable input current is the sum of the currents flowing from all I/O pins to VSS simultaneously. 6. The total allowable output current is the sum of the currents flowing from VCC to all I/O pins. Rev. 0.1, 11/98, page 740 of 975 28.2.3 AC Characteristics of HD64F2194 Table 28.4 (1) AC Characteristics of HD64F2194 (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Values Item Symbol Applicable Pins Clock oscillation frequency fOSC OSC1, OSC2 Clock cycle time tcyc OSC1, OSC2 Test Conditions Min Typ Max Unit 8 10 MHz 100 125 ns Subclock oscillation fX frequency X1, X2 Vcc=2.7 to 5.5V 32.768 kHz Subclock cycle time tsubcyc X1, X2 Vcc=2.7 to 5.5V 30.518 s Oscillation stabilization time OSC1, OSC2 Crystal oscillator 10 ms X1, X2 32kHz crystal oscillator Vcc=2.7 to 5.5V 2 s trc Notes Figure 28.1 Figure 28.2 External clock high width tCPH OSC1 40 ns External clock low width tCPL OSC1 40 ns External clock rise time tCPr OSC1 10 ns External clock fall time tCPf OSC1 10 ns External clock stabilization delay time tDEXT OSC1 500 s Figure 28.3 Subclock input low level pulse width tEXCLL X1 Vcc=2.7 to 5.5V 15.26 s Figure 28.2 Subclock input high tEXCLH level pulse width X1 Vcc=2.7 to 5.5V 15.26 s Subclock input rise time tEXCLr X1 Vcc=2.7 to 5.5V 10 ns Subclock input fall time tECXLf X1 Vcc=2.7 to 5.5V 10 ns Figure 28.1 Rev. 0.1, 11/98, page 741 of 975 Table 28.4 (2) AC Characteristics of HD64F2194 (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Values Item Applicable Symbol Pins Test Conditions 5(6 pin low level tREL 5(6 tIH ,54 to ,54, Vcc=2.7V to 5.5V 2 10,, ,& , $'75*, TMBI, Min Vcc=2.7V to 5.5V 20 Typ Max Unit Figure tcyc Figure 28.4 tcyc tsubcyc Figure 28.5 tcyc tsubcyc width Input pin high level width FTIA, FTIB, FTIC, FTID, TRIG Input pin low level width tIL ,54 to ,54, Vcc=2.7V to 5.5V 2 10,, ,& , $'75*, TMBI, FTIA, FTIB, FTIC, FTID, TRIG tcyc OSC1 VIH VIL tCPL tCPH tCPr tCPf Figure 28.1 System Clock Timing tsubcyc tEXCLH tEXCLL VIH X1 Vcc x 0.5 VIL tEXCLr tEXCLf Figure 28.2 Subclock Input Timing Rev. 0.1, 11/98, page 742 of 975 4.0V Vcc OSC1 (Internal) RES tDEXT* Note: * The tDEXT includes the RES pin Low level width 20 tcyc. Figure 28.3 External Clock Stabilization Delay Timing RES VIL tREL Figure 28.4 Reset Input Timing IRQ0 to IRQ5, NMI, IC, ADTRG, TMBI, FTIA, FTIB, FTIC, FTID, TRIG VIH VIL tIL tIH Figure 28.5 Input Timing Rev. 0.1, 11/98, page 743 of 975 28.2.4 Serial Interface Timing of HD64F2194 Table 28.5 Serial Interface Timing of HD64F2194 (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Values Item Applicabl Test Symbol e Pins Conditions Input clock cycle tscyc Typ Max Unit Figure Asynchroniza-tion 4 tcyc Figure 28.6 Clock synchronization 6 SCK2 2 Input clock pulse width tSCKW SCK1, SCK2 0.4 0.6 tscyc Input clock rise time SCK1 1.5 tcyc SCK2 60 ns SCK1 1.5 tcyc SCK2 60 ns Input clock fall time tSCKr tSCKf SCK1 Min Transmit data delay time (clock sync) tTXD SO1 100 ns Receive data setup time (clock sync) tRXS SI1 100 ns Receive data hold time tRXH (clock sync) SI1 100 ns Transmit data output delay time tTXD SO2 200 ns Receive data setup time (clock sync) tRXS SI2 180 ns Receive data hold time tRXH (clock sync) SI2 180 ns &6 setup time tCSS &6 1 tscyc &6 hold time tCSH &6 1 tscyc Rev. 0.1, 11/98, page 744 of 975 Figure 28.7 Figure 28.7 Figure 28.8 tSCKW tscyc VIH or VOH SCK1 VIL or VOL tSCKr tSCKf Figure 28.6 SCK1 Clock Timing VIH SCK1, SCK2 VIL tTXD VOH SO1, SO2 VOL tRXS tRXH SI1, SI2 Figure 28.7 SCI I/O Timing/Clock Synchronization Mode VIH CS tCSH tCSS SCK2 VIH VIL Figure 28.8 SCI2 Chip Select Timing Rev. 0.1, 11/98, page 745 of 975 Vcc 2.4k LSI output pin 30pF 12k Timing reference level VOH: 2.0V VOL: 0.8V Figure 28.9 Output Load Conditions Rev. 0.1, 11/98, page 746 of 975 2 Table 28.6 I C Bus Interface Timing of HD64F2194 (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Values Item Test Symbol Conditions Min Typ Max Unit Figure SCL input cycle time tSCL 12 tcyc Figure 28.10 SCL input high pulse width tSCLH 3 tcyc SCL input low pulse width tSCLL 5 SCL, SDA input rise time tsr 7.5 tcyc SCL, SDA input fall time tsf 300 ns SCL, SDA input spike pulse removal time tsp 1 tcyc SDA input bus free time tBUF 5 tcyc Start condition input hold time tSTAH 3 tcyc Re-transmit start condition input tSTAS setup time 3 tcyc Stop condition input setup time tSTOS 3 tcyc Data input setup time tSDAS 0.5 tcyc Data input hold time tSDAH 0 ns SCL, SDA capacity load Cb 400 pF Note: tcyc *1 2 1. Can also be set to 17.5 tcyc depending on the selection of clock to be used by the I C module. Rev. 0.1, 11/98, page 747 of 975 VIH SDA tBUF VIL tSTAH tSCLH tSTAS tSP tSTOS SCL P* S* tSf Sr* tSCLL tSCL tSDAH Note: * S, P and Sr denote the following: S : Start conditions P : Stop conditions Sr: Re-transmit start conditions 2 Figure 28.10 I C Bus Interface I/O Timing Rev. 0.1, 11/98, page 748 of 975 P* tSDAS tSr 28.2.5 A/D Converter Characteristics of HD64F2194 Table 28.7 A/D Converter Characteristics of HD64F2194 (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = AVss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Values Item Analog power supply voltage Applicable Symbol Pins Test Conditions Min Typ Max AVcc Unit AVcc Vcc0.3 Vcc Vcc+0 V .3 Analog input voltage AVIN AN0 to AN7, AN8 to ANB AVss AVcc V Analog power supply current AICC AVcc AVcc=5.0V 2.0 mA AISTOP AVcc Vcc=2.7 to 5.5V At reset and in power-down mode 10 A Analog input capacitance CAIN AN0 to AN7, AN8 to ANB 30 pF Allowable signal source impedance RAIN AN0 to AN7, AN8 to ANB 10 k Resolution 10 Bit Absolute accuracy 4 LSB Conversion time 13.4 26.6 s Note Note: Do not open the AVcc and AVss pin even when the A/D converter is not in use. Set AVcc = Vcc and AVss = Vss. 28.2.6 Servo Section Electrical Characteristics of HD64F2194 Rev. 0.1, 11/98, page 749 of 975 Table 28.8 (1) Servo Section Electrical Characteristics of HD64F2194 (reference values) (Conditions: Vcc = SVcc = 5.0 V, Vss = SVss = 0.0 V, Ta = 25C unless otherwise specified.) Reference Values Applicable Item Symbol PB-CTL input amplifier voltage gain PB-CTL V+TH Schmitt input Pins Test Conditions Min Typ Max Unit CTL (+) CTLGR3=0, CTLRG2=0, CTLRG1=0, CTLRG0=0, f=10kHz 32.0 34.0 36.0 dB CTLGR3=0, CTLRG2=0, CTLRG1=0, CTLRG0=1, f=10kHz 34.5 36.5 38.5 CTLGR3=0, CTLRG2=0, CTLRG1=1, CTLRG0=0, f=10kHz 37.0 39.0 41.0 CTLGR3=0, CTLRG2=0, CTLRG1=1, CTLRG0=1, f=10kHz 39.5 41.5 43.5 CTLGR3=0, CTLRG2=1, CTLRG1=0, CTLRG0=0, f=10kHz 42.0 44.0 46.0 CTLGR3=0, CTLRG2=1, CTLRG1=0, CTLRG0=1, f=10kHz 44.5 46.5 48.5 CTLGR3=0, CTLRG2=1, CTLRG1=1, CTLRG0=0, f=10kHz 47.0 49.0 51.0 CTLGR3=0, CTLRG2=1, CTLRG1=1, CTLRG0=1, f=10kHz 49.5 51.5 53.5 CTLGR3=1, CTLRG2=0, CTLRG1=0, CTLRG0=0, f=10kHz 52.0 54.0 56.0 CTLGR3=1, CTLRG2=0, CTLRG1=0, CTLRG0=1, f=10kHz 54.5 56.5 58.5 CTLGR3=1, CTLRG2=0, CTLRG1=1, CTLRG0=0, f=10kHz 57.0 59.0 61.0 CTLGR3=1, CTLRG2=0, CTLRG1=1, CTLRG0=1, f=10kHz 59.5 61.5 63.5 CTLGR3=1, CTLRG2=1, CTLRG1=0, CTLRG0=0, f=10kHz 62.0 64.0 66.0 CTLGR3=1, CTLRG2=1, CTLRG1=0, CTLRG0=1, f=10kHz 64.5 66.5 68.5 CTLGR3=1, CTLRG2=1, CTLRG1=1, CTLRG0=0, f=10kHz 67.0 69.0 71.0 CTLGR3=1, CTLRG2=1, CTLRG1=1, CTLRG0=1, f=10kHz 69.5 71.5 73.5 AC combination, C=0.1F Typ (non pol) 250 AC combination, C=0.1F Typ (non pol) -250 150 8 mA CTLSMT (i) V-TH Analog switch ON resistance REB REC-CTL output voltage ICTL REC-CTL pin-to-pin resistance RCTL CTL (+) CTL (-) CTL reference output voltage CTLREF Rev. 0.1, 11/98, page 750 of 975 Series resistance = 0 mVp 8 10 k 1/2 SVcc V Note Table 28.8 (2) Servo Section Electrical Characteristics of HD64F2194 (reference values) (Conditions: Vcc = SVcc = 5.0 V, Vss = SVss = 0.0 V, Ta = 25C unless otherwise specified.) Reference Values Item Applicable Symbol Pins Test Conditions Min Typ Max Unit 1/2 SVCC V Vpp 10 k Rise threshold level 2.25 V Fall threshold level 2.75 Rising edge Schmitt level 1.95 Falling edge Schmitt level 1.85 Rising edge Schmitt level 3.55 Falling edge Schmitt level 3.45 -IOH=0.1mA 4.0 VOM No load, Hiz=1 2.5 VOL IOL=0.1mA 1.0 15 k AC coupling, 48 C=1F Typ, f=1kHz 52 % CFG pin bias voltage CFG CFG input level CFG CFG input impedance CFG CFG input threshold V+THCF value CFG V-THCF DFG Schmitt input V+THDF DFG V-THDF DPG Schmitt input V+THDP DPG V-THDP 3-level output voltage VOH Vpulse 3-level output pin divided voltage resistance Vpulse CFG Duty CFG AC coupling, 1.0 C=1F Typ, f=1kHz Note V V V Rev. 0.1, 11/98, page 751 of 975 Table 28.8 (3) Servo Section Electrical Characteristics of HD64F2194 (Conditions: Vcc = SVcc = 5.0 V, Vss = SVss = 0.0 V, Ta = 25C unless otherwise specified.) Values Applicable Symbol Pins Test Conditions Min Typ Max Digital input high level VIH 0.8 Vcc Vcc+0 V .3 Digital input low level VIL -0.3 0.2 Vcc Digital output high level VOH -IOH=1mA Vcc -1.0 Digital output low level VOL IOL=1.6mA 0.6 Current consumption ICCSV At no load 5 10 Item COMP, EXCTL, EXCAP, EXTTRG H.AmpSW, C.Rotary, VIDEOFF, AUDIOFF, DRMPWM, CAPPWM, SV1, SV2 SVcc Rev. 0.1, 11/98, page 752 of 975 Unit V mA Note 28.2.7 FLASH Memory Characteristics Table 28.9 shows the FLASH memory characteristics. Table 28.9 FLASH Memory Characteristics (Preliminary) Conditions: Vcc = 5.0 V 10%, AVcc = 5.0 V 10%, Vss = AVss = 0 V, Ta = 0 to +75C (operating temperature range at programming/erasing) Test Symbol conditions Min Item *1*2*4 Programming time *1*3*5 Erasing time No. of reprogramming At programming *1 Wait time after SWE-bit setting Unit 10 200 ms/ 32 bytes tE 100 1200 ms/ block NWEC 100 Times x 10 s y 50 s z 150 200 s *1 10 s 10 s 4 s 2 s 4 s 1000 Times x 10 s Wait time after P-bit setting Wait time after P-bit clearing *1 Wait time after PSU-bit clearing *1 Wait time after PV-bit setting Wait time after dummy write *1 *1 Wait time after PV-bit clearing *1*4*5 Maximum No. of programmings *1 Wait time after SWE-bit setting N When tZ = 200 s y 200 s *1*6 z 5 10 ms *1 10 s 10 s 20 s 2 s 5 s N 120 240 Times *1 Wait time after ESU-bit setting Wait time after E-bit setting Wait time after E-bit clearing *1 Wait time after ESU-bit clearing *1 Wait time after EV-bit setting Wait time after dummy write *1 *1 Wait time after EV-bit clearing *1*6 Maximum No. of erasings Max *1*4 *1 Wait time after PSU-bit setting At erasing Typ tP Notes: 1. Perform each time setting according to the programming/erasing algorithm. 2. Programming time per 32 bytes (total time of setting P-bit of the FLASH memory control register. Programming verify time is not included). Rev. 0.1, 11/98, page 753 of 975 3. Time to erase 1 block (total time of setting E-bit of the FLASH memory control register. Erasing verify time is not included). 4. Maximum programming time (tP (max.)) = Wait time after P-bit setting (z) x Maximum No. of programming (N) 5. No. of times when wait time after P-bit setting (z) = 200 s. Set maximum No. of programming shall be set less than maximum programming time (tP (max.)) according to the actual setting (z). 6. Relationship between wait time after E-bit setting (z) and maximum No. of erasing (N) for maximum erasing time (tE (max.)) is as follows: tE (max.) = Wait time after E-bit setting x Maximum No. of erasing (N) Set the (z) and (N) values so that they satisfy the above equation. (Ex.) When z = 5 [ms], N = 240 times (Ex.) When z = 10 [ms], N = 120 times 28.2.8 Usage Note The F-ZTAT version and the Mask ROM version satisfy the electrical characteristics indicated in this manual, but the actual power value, operating margin, and noise margin may differ from those in this manual, due to the difference of production process, on-chip ROM, layout pattern, etc. When executing the system examination using the F-ZTAT version, be sure to execute the same system examination using the Mask ROM version when changing to the Mask ROM version. Rev. 0.1, 11/98, page 754 of 975 28.3 Electrical Characteristics of HD6432194, HD6432193, HD6432192 and HD6432191 28.3.1 DC Characteristics of HD6432194, HD6432193, HD6432192 and HD6432191 Table 28.10 (1) DC Characteristics of HD6432194, HD6432193, HD6432192 and HD6432191 (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Values Item Symbol Applicable Pins Test Conditions Min Typ Max Unit Input high voltage VIH Vcc=2.5 to 5.5V 0.9 Vcc Vcc+0.3 V 0.8 Vcc Vcc+0.3 0.9 Vcc Vcc+0.3 0.8 Vcc Vcc+0.3 Vcc-0.5 Vcc+0.3 Vcc-0.3 Vcc+0.3 0.7 Vcc Vcc+0.3 0.8 Vcc Vcc+0.3 0.7 Vcc Vcc+0.3 MD0 5(6, 10,, ,&, ,54 to ,54 Vcc=2.5 to 5.5V SCK1, SCK2, SI1, SI2, &6, FTIA, FTIB, FTIC, FTID, TRIG, TMBI, Notes $'75* OSC1, X1 Vcc=2.5 to 5.5V P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PS0 to PS4 Vcc=2.5 to 5.5V Csync Note: Do not open the AVcc and AVss pin even when the A/D converter is not in use. Rev. 0.1, 11/98, page 755 of 975 Table 28.10 (2) DC Characteristics of HD6432194, HD6432193, HD6432192 and HD6432191 (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Values Item Symbol Applicable Pins Test Conditions Min Typ Max Unit Input low voltage VIL Vcc=2.5 to 5.5V -0.3 0.1 Vcc V -0.3 0.2 Vcc -0.3 0.1 Vcc -0.3 0.2 Vcc -0.3 0.5 -0.3 0.3 -0.3 0.3 Vcc -0.3 0.2 Vcc -0.3 0.2 Vcc MD0 5(6, 10,, ,&, ,54 to ,54 Vcc=2.5 to 5.5V SCK1, SCK2, SI1, SI2, &6, FTIA, FTIB, FTIC, FTID, TRIG, TMBI, $'75* OSC1, X1 Vcc=2.5 to 5.5V P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PS0 to PS4 Vcc=2.5 to 5.5V Csync Note: Do not open the AVcc and AVss pin even when the A/D converter is not in use. Rev. 0.1, 11/98, page 756 of 975 Notes Table 28.10 (3) DC Characteristics of HD6432194, HD6432193, HD6432192 and HD6432191 (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Values Item Symbol Applicable Pins Output high VOH voltage Test Conditions Min Typ Max Unit Vcc-1.0 V Vcc- 0.5 V V 0.6 V IOL=0.4mA Vcc=2.5 to 5.5V 0.4 V IOL=20mA 1.5 V IOL=1.6mA 0.6 V IOL=0.4mA Vcc=2.5 to 5.5V 0.4 V SO1, SO2, SCK1, SCK2, -IOH=1.0mA PWM1, PWM2, PWM3, PWM4, PWM14, STRB, BUZZ, TMO, TMOW, FTOA, FTOB, PPG70 to PPG77, RP0 to RP7, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PS0 to PS4 -IOH=0.5mA Vcc-0.5 -IOH=0.1mA Vcc=2.5 to 5.5V Output low VOL voltage SO1, SO2, SCK1, SCK2, IOL=1.6mA PWM1, PWM2, PWM3, PWM4, PWM14, STRB, BUZZ, TMO, TMOW, FTOA, FTOB, PPG70 to PPG77, RP0 to RP7, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, PS0 to PS4 P80 to P87 Notes Reference value Rev. 0.1, 11/98, page 757 of 975 Table 28.10 (4) DC Characteristics of HD6432194, HD6432193, HD6432192 and HD6432191 (Conditions: Vcc = AVcc = 2.5 to 5.5 V, Vss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Values Item Symbol Applicable Pins Input /output leakage current IIL Test Conditions Min Typ Max Unit Notes 1.0 A 5(6, 10,, ,54 to ,54, Vin=0.5 to Vcc- 0.5V ,& 1.0 SCK1, SCK2, SI1, SI2, SDA, SCL, &6, FTIA, FTIB, FTIC, FTID, TRIG, TMBI, $'75* Vin=0.5 to Vcc- 0.5V 1.0 P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87 Vin=0.5 to Vcc- 0.5V 1.0 P00 to P07, AN8 to ANB Vin=0.5 to AVcc-0.5V 1.0 MD0, OSC1 Vin=0.5 to Vcc- 0.5V Pull-up MOS current -Ip P10 to P17, P20 to P27, P30 to P37 Vcc=5.0V, Vin=0V 50 300 A Input capacity Cin All input pins except power supply, P23, P24 and analog system pins fin=1 MHz, Vin=0V, Ta=25 C 15 pF P23, P24 fin=1 MHz, Vin=0V, Ta=25 C 20 pF Note: Note 3 3. Current value when the relevant bit of the pull-up MOS select register (PUR1 to PUR3) is set to 1. Rev. 0.1, 11/98, page 758 of 975 Table 28.10 (5) DC Characteristics of HD6432194, HD6432193, HD6432192 and HD6432191 (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Values Item Applicabl Test Symbol e Pins Conditions Active IOPE mode current dissipa-tion (CPU operating) Vcc Min Typ Max Unit Notes Vcc=5V, fOSC=10 MHz High-speed mode 50 70 mA Note 4 Vcc=5V, fOSC=10 MHz Medium-speed mode (1/64) 35 mA Reference value V-active IRESP mode current dissipa-tion (reset) Vcc Vcc=5V, fOSC=10 MHz 25 45 mA Note 4 Sleep mode ISLEEP current dissipa-tion Vcc Vcc=5V, fOSC=10 MHz High-speed mode 20 30 mA Note 4 Subactive ISUB mode current dissipa-tion Vcc Vcc=2.5V, 32kHz With crystal oscillator ( sub=w/2) 40 100 A Note 4 Vcc=2.5V, 32kHz With crystal oscillator ( sub=w/8) 20 Vcc=2.5V, 32kHz With crystal oscillator ( sub=w/2) 15 30 Vcc=2.5V, 32kHz With crystal oscillator ( sub=w/8) 10 Subsleep ISUBSLP mode current dissipa-tion Note: Vcc Reference value, Note 4 A Note 4 Reference value, Note 4 4. The current on the pull-up MOS or the output buffer excluded. Rev. 0.1, 11/98, page 759 of 975 Table 28.10 (6) DC Characteristics of HD6432194, HD6432193, HD6432192 and HD6432191 (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Values Applicable Symbol Pins Item Watch IWATCH mode current dissipa-tion Vcc Standby ISTBY mode current dissipa-tion Vcc RAM data retaining voltage in standby mode Vcc Note: VSTBY Test Conditions Min Typ Max Unit Notes Vcc=2.5V, 32kHz With crystal oscillator 5 10 A Note 4 Vcc=5.0V, 32kHz With crystal oscillator 10 A Reference value Note 4 X1=Vcc, 32kHz Without crystal oscillator 5 A Note 4 2.0 4. The current on the pull-up MOS or the output buffer excluded. Rev. 0.1, 11/98, page 760 of 975 V Table 28.10 (7) Pin Status at Current Dissipation Measurement Mode RES Pin Internal State Pin Oscillator Pin Active mode High-speed, mediumspeed Vcc Operating Vcc Main clock: Crystal oscillator Sub clock: X1 pin = Vcc Sleep mode High-speed, mediumspeed Vcc CPU and servo circuits stopped Vcc Reset Vss Reset Vcc Standby mode Vcc All stopped Vcc Subactive mode Vcc CPU and timer A operating Vcc Subsleep mode Vcc Timer A operating Vcc Watch mode Vcc Timer A operating Vcc Main clock: Crystal oscillator Sub clock: Crystal oscillator Rev. 0.1, 11/98, page 761 of 975 Table 28.10 (8) Bus Drive Characteristics of HD6432194, HD6432193, HD6432192 and HD6432191 (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Applicable pin: SCL, SDA Values Item Schmitt trigger input Applicable Symbol Pins VT- Test Conditions SCL, SDA + VT + T V -VT- Min Typ Max Unit 0.2 Vcc V 0.7 Vcc V 0.05 Vcc V Input High level voltage VIH SCL, SDA 0.7 Vcc Vcc+0.5 V Input Low level voltage VIL SCL, SDA -0.5 0.2 Vcc V Output Low VOL level voltage SCL, SDA IOL=8mA 0.5 V IOL=3mA 0.4 20+ 0.1Cb 250 SCL and tof SDA output fall time SCL, SDA Rev. 0.1, 11/98, page 762 of 975 ns Notes 28.3.2 Allowable Output Currents of HD6432194, HD6432193, HD6432192 and HD6432191 The specifications for the digital pins are shown below. Table 28.11 Allowable Output Currents of HD6432194, HD6432193, HD6432192 and HD6432191 (Conditions: Vcc = 2.5 to 5.5 V, Vss = 0.0 V, Ta = -20 to +75C) Item Symbol Value Unit Notes Allowable input current (to chip) IO 2 mA 1 Allowable input current (to chip) IO 22 mA 2 Allowable input current (to chip) IO 10 mA 3 Allowable output current (from chip) -IO 2 mA 4 Total allowable input current (to chip) IO 80 mA 5 Total allowable output current (from chip) -IO 50 mA 6 Notes: 1. The allowable input current is the maximum value of the current flowing from each I/O pin to VSS (except for port 8, SCL and SDA). 2. The allowable input current is the maximum value of the current flowing from each I/O pin to VSS. This applies to port 8. 3. The allowable input current is the maximum value of the current flowing from each I/O pin to VSS. This applies to SCL and SDA. 4. The allowable output current is the maximum value of the current flowing from VCC to each I/O pin. 5. The total allowable input current is the sum of the currents flowing from all I/O pins to VSS simultaneously. 6. The total allowable output current is the sum of the currents flowing from VCC to all I/O pins. Rev. 0.1, 11/98, page 763 of 975 28.3.3 AC Characteristics of HD6432194, HD6432193, HD6432192 and HD6432191 Table 28.12 (1) AC Characteristics of HD6432194, HD6432193, HD6432192 and HD6432191 (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Values Item Applicable Symbol Pins Test Conditions Min Typ Max Unit Clock oscillation frequency fOSC OSC1, OSC2 8 10 MHz Clock cycle time tcyc OSC1, OSC2 100 125 ns Subclock oscillation fX frequency X1, X2 Vcc=2.5 to 5.5V 32.768 kHz Subclock cycle time tsubcyc X1, X2 Vcc=2.5 to 5.5V 30.518 s Oscillation stabilization time OSC1, OSC2 Crystal oscillator 10 ms X1, X2 32kHz crystal oscillator Vcc=2.5 to 5.5V 2 s trc Notes Figure 28.11 Figure 28.12 External clock high width tCPH OSC1 40 ns External clock low width tCPL OSC1 40 ns External clock rise time tCPr OSC1 10 ns External clock fall time tCPf OSC1 10 ns External clock stabilization delay time tDEXT OSC1 500 s Figure 28.13 Subclock input low level pulse width tEXCLL X1 Vcc=2.5 to 5.5V 15.26 s Figure 28.12 Subclock input high tEXCLH level pulse width X1 Vcc=2.5 to 5.5V 15.26 s Subclock input rise time X1 Vcc=2.5 to 5.5V 10 ns tEXCLr Rev. 0.1, 11/98, page 764 of 975 Figure 28.11 Table 28.12 (2) AC Characteristics of HD6432194, HD6432193, HD6432192 and HD6432191 (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Values Applicable Symbol Pins Test Conditions Min Typ Max Unit Figure Subclock input fall time tEXCLf X1 Vcc=2.5 to 5.5V 10 ns Figure 28.12 5(6 pin low level tREL 5(6 Vcc=2.5V to 5.5V 20 tcyc Figure 28.14 tIH ,54 to ,54, Vcc=2.5V to 5.5V 2 10,, ,&, $'75*, TMBI, tcyc tsubcyc Figure 28.15 tcyc tsubcyc Item width Input pin high level width FTIA, FTIB, FTIC, FTID, TRIG Input pin low level width tIL ,54 to ,54, Vcc=2.5V to 5.5V 2 10,, ,&, $'75*, TMBI, FTIA, FTIB, FTIC, FTID, TRIG tcyc OSC1 VIH VIL tCPH tCPr tCPL tCPf Figure 28.11 System Clock Timing Rev. 0.1, 11/98, page 765 of 975 tsubcyc tEXCLH tEXCLL VIH X1 Vcc x 0.5 VIL tEXCLr tEXCLf Figure 28.12 Subclock Input Timing 4.0V Vcc OSC1 (Internal) RES tDEXT* Note: * The tDEXT includes the RES pin Low level width 20 tcyc. Figure 28.13 External Clock Stabilization Delay Timing Rev. 0.1, 11/98, page 766 of 975 RES VIL tREL Figure 28.14 Reset Input Timing IRQ0 to IRQ5, NMI, IC, ADTRG, TMBI, FTIA, FTIB, FTIC, FTID, TRIG VIH VIL tIL tIH Figure 28.15 Input Timing Rev. 0.1, 11/98, page 767 of 975 28.3.4 Serial Interface Timing of HD6432194, HD6432193, HD6432192 and HD6432191 Table 28.13 Serial Interface Timing of HD6432194, HD6432193, HD6432192 and HD6432191 (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Values Item Applicabl Test Symbol e Pins Conditions Input clock cycle tscyc Typ Max Unit Figure Asynchroniza-tion 4 tcyc Figure 28.16 Clock synchronization 6 SCK2 2 Input clock pulse width tSCKW SCK1, SCK2 0.4 0.6 tscyc Input clock rise time SCK1 1.5 tcyc SCK2 60 ns SCK1 1.5 tcyc SCK2 60 ns Input clock fall time tSCKr tSCKf SCK1 Min Transmit data delay time (clock sync) tTXD SO1 100 ns Receive data setup time (clock sync) tRXS SI1 100 ns Receive data hold time tRXH (clock sync) SI1 100 ns Transmit data output delay time tTXD SO2 200 ns Receive data setup time (clock sync) tRXS SI2 180 ns Receive data hold time tRXH (clock sync) SI2 180 ns &6 setup time tCSS &6 1 tscyc &6 hold time tCSH &6 1 tscyc Rev. 0.1, 11/98, page 768 of 975 Figure 28.17 Figure 28.17 Figure 28.18 tSCKW tscyc VIH or VOH SCK1 VIL or VOL tSCKr tSCKf Figure 28.16 SCK1 Clock Timing VIH SCK1, SCK2 VIL tTXD VOH SO1, SO2 VOL tRXS tRXH SI1, SI2 Figure 28.17 SCI I/O Timing/Clock Synchronization Mode VIH CS tCSH tCSS SCK2 VIH VIL Figure 28.18 SCI2 Chip Select Timing Rev. 0.1, 11/98, page 769 of 975 Vcc 2.4k LSI output pin 30 pF 12k Timing reference level VOH: 2.0 V VOL: 0.8 V Figure 28.19 Output Load Conditions Rev. 0.1, 11/98, page 770 of 975 2 Table 28.14 I C Bus Interface Timing of HD6432194, HD6432193, HD6432192 and HD6432191 (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Values Item Symbol SCL input cycle time Test Conditions Min Typ Max Unit Figure tSCL 12 tcyc Figure 28.10 SCL input high pulse width tSCLH 3 tcyc SCL input low pulse width tSCLL 5 SCL, SDA input rise time tsr 7.5 tcyc SCL, SDA input fall time tsf 300 ns SCL, SDA input spike pulse removal time tsp 1 tcyc SDA input bus free time tBUF 5 tcyc Start condition input hold time tSTAH 3 tcyc Re-transmit start condition input tSTAS setup time 3 tcyc Stop condition input setup time tSTOS 3 tcyc Data input setup time tSDAS 0.5 tcyc Data input hold time tSDAH 0 ns SCL, SDA capacity load Cb 400 pF Note: tcyc *1 2 1. Can also be set to 17.5 tcyc depending on the selection of clock to be used by the I C module. Rev. 0.1, 11/98, page 771 of 975 VIH SDA tBUF VIL tSTAH tSCLH tSTAS tSP tSTOS SCL P* S* tSf Sr* tSCLL tSCL tSDAH Note: * S, P and Sr denote the following: S : Start conditions P : Stop conditions Sr: Re-transmit start conditions 2 Figure 28.20 I C Bus Interface I/O Timing Rev. 0.1, 11/98, page 772 of 975 P* tSDAS tSr 28.3.5 A/D Converter Characteristics of HD6432194, HD6432193, HD6432192 and HD6432191 Table 28.15 A/D Converter Characteristics of HD6432194, HD6432193, HD6432192 and HD6432191 (Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = AVss = 0.0 V, Ta = -20 to +75C unless otherwise specified.) Values Item Analog power supply voltage Applicable Symbol Pins Test Conditions Min Typ Max AVcc Unit AVcc Vcc- 0.3 Vcc Vcc+0 V .3 Analog input voltage AVIN AN0 to AN7, AN8 to ANB AVss AVcc V Analog power supply current AICC AVcc AVcc=5.0V 2.0 mA AISTOP Avcc Vcc=2.5 to 5.5V At reset and in power-down mode 10 A Analog input capacitance CAIN AN0 to AN7, AN8 to ANB 30 pF Allowable signal source impedance RAIN AN0 to AN7, AN8 to ANB 10 k Resolution 10 Bit Absolute accuracy 4 LSB Conversion time 13.4 26.6 s Note Note: Do not open the AVcc and AVss pin even when the A/D converter is not in use. Set AVcc = Vcc and AVss = Vss. 28.3.6 Servo Section Electrical Characteristics of HD6432194, HD6432193, HD6432192 and HD6432191 Rev. 0.1, 11/98, page 773 of 975 Table 28.16 (1) Servo Section Electrical Characteristics of HD6432194, HD6432193, HD6432192 and HD6432191 (reference values) (Conditions: Vcc = SVcc = 5.0 V, Vss = SVss = 0.0 V, Ta = 25C unless otherwise specified.) Reference Values Item Applicabl Symbol e Pins Test Conditions PB-CTL input amplifier voltage gain CTL (+) PB-CTL V+TH Schmitt input CTLSMT (i) V-TH Analog switch ON resistance REB REC-CTL output voltage ICTL REC-CTL pin-to-pin resistance RCTL CTL (+) CTL (-) CTL reference output voltage CTLREF Rev. 0.1, 11/98, page 774 of 975 Min Typ Max Unit CTLGR3=0, CTLRG2=0, CTLRG1=0, CTLRG0=0, f=10kHz 32.0 34.0 36.0 dB CTLGR3=0, CTLRG2=0, CTLRG1=0, CTLRG0=1, f=10kHz 34.5 36.5 38.5 CTLGR3=0, CTLRG2=0, CTLRG1=1, CTLRG0=0, f=10kHz 37.0 39.0 41.0 CTLGR3=0, CTLRG2=0, CTLRG1=1, CTLRG0=1, f=10kHz 39.5 41.5 43.5 CTLGR3=0, CTLRG2=1, CTLRG1=0, CTLRG0=0, f=10kHz 42.0 44.0 46.0 CTLGR3=0, CTLRG2=1, CTLRG1=0, CTLRG0=1, f=10kHz 44.5 46.5 48.5 CTLGR3=0, CTLRG2=1, CTLRG1=1, CTLRG0=0, f=10kHz 47.0 49.0 51.0 CTLGR3=0, CTLRG2=1, CTLRG1=1, CTLRG0=1, f=10kHz 49.5 51.5 53.5 CTLGR3=1, CTLRG2=0, CTLRG1=0, CTLRG0=0, f=10kHz 52.0 54.0 56.0 CTLGR3=1, CTLRG2=0, CTLRG1=0, CTLRG0=1, f=10kHz 54.5 56.5 58.5 CTLGR3=1, CTLRG2=0, CTLRG1=1, CTLRG0=0, f=10kHz 57.0 59.0 61.0 CTLGR3=1, CTLRG2=0, CTLRG1=1, CTLRG0=1, f=10kHz 59.5 61.5 63.5 CTLGR3=1, CTLRG2=1, CTLRG1=0, CTLRG0=0, f=10kHz 62.0 64.0 66.0 CTLGR3=1, CTLRG2=1, CTLRG1=0, CTLRG0=1, f=10kHz 64.5 66.5 68.5 CTLGR3=1, CTLRG2=1, CTLRG1=1, CTLRG0=0, f=10kHz 67.0 69.0 71.0 CTLGR3=1, CTLRG2=1, CTLRG1=1, CTLRG0=1, f=10kHz 69.5 71.5 73.5 AC combination, C=0.1F Typ (non pol) 250 AC combination, C=0.1F Typ (non pol) -250 150 8 mA Series resistance = 0 mVp 8 10 k 1/2 SVcc V Note Table 28.16 (2) Servo Section Electrical Characteristics of HD6432194, HD6432193, HD6432192 and HD6432191 (reference values) (Conditions: Vcc = SVcc = 5.0 V, Vss = SVss = 0.0 V, Ta = 25C unless otherwise specified.) Reference Values Item Applicable Symbol Pins Test Conditions Min CFG pin bias voltage CFG CFG input level CFG CFG input impedance CFG CFG input threshold V+THCF value CFG 1/2 SVCC V Vpp AC coupling, C=1F 1.0 Typ, f=1kHz k Rise threshold level 2.25 V Fall threshold level 2.75 Rising edge Schmitt level 1.95 Falling edge Schmitt level 1.85 Rising edge Schmitt level 3.55 Falling edge Schmitt level 3.45 -IOH=0.1mA 4.0 VOM No load, Hiz=1 2.5 VOL IOL=0.1mA V+THDF DFG V+THDP DPG V-THDP 3-level output voltage Unit 10 V-THDF DPG Schmitt input Max V-THCF DFG Schmitt input Typ VOH Vpulse 3-level output pin divided voltage resistance Vpulse CFG Duty CFG Note V V V 1.0 15 k AC coupling, C=1F 48 Typ, f=1kHz 52 % Rev. 0.1, 11/98, page 775 of 975 Table 28.16 (3) Servo Section Electrical Characteristics of HD6432194, HD6432193, HD6432192 and HD6432191 (Conditions: Vcc = SVcc = 5.0 V, Vss = SVss = 0.0 V, Ta = 25C unless otherwise specified.) Values Applicable Symbol Pins Test Conditions Min Typ Max Digital input high level VIH 0.8 Vcc Vcc+0 V .3 Digital input low level VIL -0.3 0.2 Vcc Digital output high level VOH -IOH=1mA Vcc- 1.0 Digital output low level VOL IOL=1.6mA 0.6 Current consumption ICCSV At no load 5 10 Item COMP, EXCTL, EXCAP, EXTTRG H.AmpSW, C.Rotary, VIDEOFF, AUDIOFF, DRMPWM, CAPPWM, SV1, SV2 SVcc Rev. 0.1, 11/98, page 776 of 975 Unit V mA Note Rev. 0.1, 11/98, page 777 of 975 Appendix A Instruction Set A.1 Instructions [Operation Notation] *1 Rd Rs General register (destination) *1 General register (source) Rn General register ERn MAC General register (32-bit register) *2 Multiplication-Addition register (32-bit register) *1 (EAd) Destination operand (EAs) EXR Source operand Extend register CCR N Z V C PC Condition code register N (negative flag) in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter SP #IMM disp + Stack pointer Immediate data Displacement Addition - Subtraction x / ~ ( ) <> Multiplication Division Logical AND Logical OR Exclusive logical OR Move from the left to the right Logical complement Contents of operand :8/:16/:24/:32 8/16/24/32 bit length Notes: 1. General register is 8-bit (R0H to R7H, R0L to R7L), 16-bit (R0 to R7) or 32-bit (ER0 to ER7). 2. MAC register cannot be used in this LSI. Rev. 0.1, 11/98, page 778 of 975 [Condition Code Notation] Symbol Description Modified according to the instruction result * Not fixed (value not guaranteed) 0 Always cleared to 0 1 Always set to 1 - Not affected by the instruction execution result Rev. 0.1, 11/98, page 779 of 975 Table A.1 List of Instruction Set (1) Data Transfer Instruction MOV LDM MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 POP.W Rn POP.L ERn PUSH.W Rn PUSH.L ERn LDM @SP+,(ERm-ERn) B B B B B B B B B B B B B B B B W W W W W W W W W W W W W W L L L L L L L L L L L L L L W L W L L STM STM (ERm-ERn),@-SP L POP PUSH MOVFPE MOVFPE @aa:16,Rd MOVTPE MOVTPE Rs,@aa:16 -- @@aa @(d,PC) 2 2 2 4 8 2 2 4 6 2 4 8 2 2 4 6 4 2 2 4 8 2 4 6 2 4 8 2 4 6 6 2 4 6 10 4 6 8 4 6 10 Cannot be used in this LSI Rev. 0.1, 11/98, page 780 of 975 4 6 8 2 4 2 4 4 4 I #xx:8Rd8 Rs8Rd8 @ERsRd8 @(d:16,ERs)Rd8 @(d:32,ERs)Rd8 @ERsRd8,ERs32+1ERs32 @aa:8Rd8 @aa:16Rd8 @aa:32Rd8 Rs8@ERd Rs8@(d:16,ERd) Rs8@(d:32,ERd) ERd32-1ERd32,Rs8@ERd Rs8@aa:8 Rs8@aa:16 Rs8@aa:32 #xx:16Rd16 Rs16Rd16 @ERsRd16 @(d:16,ERs)Rd16 @(d:32,ERs)Rd16 @ERsRd16,ERs32+2ERs32 @aa:16Rd16 @aa:32Rd16 Rs16@ERd Rs16@(d:16,ERd) Rs16@(d:32,ERd) ERd32-2ERd32,Rs16@ERd Rs16@aa:16 Rs16@aa:32 #xx:32ERd32 ERs32ERd32 @ERsERd32 @(d:16,ERs)ERd32 @(d:32,ERs)ERd32 @ERsERd32,ERs32+4ERs32 @aa:16ERd32 @aa:32ERd32 ERs32@ERd ERs32@(d:16,ERd) ERs32@(d:32,ERd) ERd32-4ERd32,ERs32@ERd ERs32@aa:16 ERs32@aa:32 @SPRn16,SP+2SP @SPERn32,SP+4SP SP-2SP,Rn16@SP SP-4SP,ERn32@SP (@SPERn32,SP+4SP) Repeat for the number of returns (SP-4SP,ERn32@SP) Repeat for the number of returns No of Execution States *1 Condition Code Operation @aa @-ERn/@ERn+ @ERn Rn Size #xx Mnemonic @(d,ERn) Addressing Mode and Instruction Length (Bytes) H N Z V C Advanced Mode -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 2 3 5 3 2 3 4 2 3 5 3 2 3 4 2 1 2 3 5 3 3 4 2 3 5 3 3 4 3 1 4 5 7 5 5 6 4 5 7 5 5 6 3 5 3 5 7/9/11 [1] -- -- -- -- -- -- 7/9/11 [1] -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -- [2] [2] (2) Arithmetic Instructions ADD ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDX ADDX #xx:8,Rd ADDX Rs,Rd ADDS ADDS #1,ERd ADDS #2,ERd ADDS #4,ERd INC INC.B Rd INC.W #1,Rd INC.W #2,Rd INC.L #1,ERd INC.L #2,ERd DAA DAA Rd SUB SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBX SUBX #xx:8,Rd SUBX Rs,Rd SUBS SUBS #1,ERd SUBS #2,ERd SUBS #4,ERd DEC DEC.B Rd DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DEC.L #2,ERd DAS DAS Rd MULXU MULXU.B Rs,Rd MULXU.W Rs,ERd MULXS MULXS.B Rs,Rd MULXS.W Rs,ERd DIVXU DIVXU.B Rs,Rd DIVXU.W Rs,ERd DIVXS CMP NEG EXTU EXTS TAS B B W W L L B B L L L B W W L L B B W W L L B B L L L B W W L L B B W B W B 2 2 6 2 2 2 2 2 2 2 2 2 2 2 2 2 4 2 6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 4 2 2 B 4 DIVXS.W Rs,ERd W 4 CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd NEG.B Rd NEG.W Rd NEG.L ERd EXTU.W Rd EXTU.L ERd EXTS.W Rd B B W W L L B W L W L W EXTS.L ERd L TAS @ERd B -- @@aa @(d,PC) @aa I 2 2 4 2 6 2 2 2 2 2 2 2 2 4 Quatient)(Division w/o sign) ERd32/Rs16ERd32 (Ed:Remainder, Rd: Quatient)(Division with sign) Rd16/Rs8Rd16(RdH: Rmainder, RdL: Quatient)(Division w/o sign) ERd32/Rs16ERd32 (Ed:Remainder, Rd: Quatient)(Division with sign) Rd8-#xx:8 Rd8-Rs8 Rd16-#xx:16 Rd16-Rs16 ERd32-#xx:32 ERd32-ERs32 0-Rd8Rd8 0-Rd16Rd16 0-ERd32ERd32 0(<Bits 15 to 8> of Rd16) 0(<Bits 31 to 16> of ERd32) (<Bit7> of Rd16) (<Bits 15 to 8> of Rd16) (<Bit15> of ERd32) (<Bits31 to 16> of ERd32) @ERd-0CCR set, (1) (<Bit7> of @ERd) H N Z V C No of Execution States *1 Advanced Mode [5] [5] -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- * -- * -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- [6] [7] -- -- 1 1 2 1 3 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 3 1 1 1 1 1 1 1 1 1 1 1 1 12 20 13 21 12 -- -- [6] [7] -- -- 20 -- -- [8] [7] -- -- 13 -- -- [8] [7] -- -- 21 -- -- -- -- -- -- -- -- -- -- -- -- 0 -- 0 -- 0 -- 1 1 2 1 3 1 1 1 1 1 1 1 -- -- 0 -- 1 -- -- 0 -- 4 Rd8+#xx:8Rd8 Rd8+Rs8Rd8 Rd16+#xx:16Rd16 Rd16+Rs16Rd16 ERd32+#xx:32ERd32 ERd32+ERs32ERd32 Rd8+#xx:8+CRd8 Rd8+Rs8+CRd8 ERd32+1ERd32 ERd32+2ERd32 ERd32+4ERd32 Rd8+1Rd8 Rd16+1Rd16 Rd16+2Rd16 ERd32+1ERd32 ERd32+2ERd32 Rd8 10 Decimal adjust Rd8 Rd8-Rs8Rd8 Rd16-#xx:16Rd16 Rd16-Rs16Rd16 ERd32-#xx:32ERd32 ERd32-ERs32ERd32 Rd8-#xx:8-CRd8 Rd8-Rs8-CRd8 ERd32-1ERd32 ERd32-2ERd32 ERd32-4ERd32 Rd8-1Rd8 Rd16-1Rd16 Rd16-2Rd16 ERd32-1ERd32 ERd32-2ERd32 Rd8 10 Decimal adjust Rd8 Rd8xRs8Rd16(Multiplication w/o sign) Rd16xRs16ERd32(Multiplication w/o sign) Rd8xRs8Rd16(Multiplication w/o sign) Rd16xRs16ERd32(Multiplication w/o sign) 4 DIVXS.B Rs,Rd Condition Code Operation -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Rd16/Rs8Rd16 (RdH: Rmainder, RdL: -- 2 W @-ERn/@ERn+ @ERn Rn Size #xx Mnemonic @(d,ERn) Addressing Mode and Instruction Length (Bytes) [3] [3] [4] [4] [5] [5] -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- * * [3] [3] [4] [4] [3] [3] [4] [4] -- 0 -- 0 -- MAC MAC @ERn+,@ERm+ CLRMAC CLRMAC LDMAC LDMAC ERs,MACH LDMAC ERs,MACL STMAC STMAC MACH,ERd STMAC MACL,ERd Cannot be used in this LSI [2] Rev. 0.1, 11/98, page 781 of 975 (3) Logic Operations Instructions AND OR XOR NOT AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd NOT.B Rd NOT.W Rd NOT.L ERd B B W W L L B B W W L L B B W W L L B W L 2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2 Rev. 0.1, 11/98, page 782 of 975 @@aa @(d,PC) --- Rd8#xx:8Rd8 Rd8Rs8Rd8 Rd16#xx:16Rd16 Rd16Rs16Rd16 ERd32#xx:32ERd32 ERd32ERs32ERd32 Rd8#xx:8Rd8 Rd8Rs8Rd8 Rd16#xx:16Rd16 Rd16Rs16Rd16 ERd32#xx:32ERd32 ERd32ERs32ERd32 Rd8#xx:8Rd8 Rd8Rs8Rd8 Rd16#xx:16Rd16 Rd16Rs16Rd16 ERd32#xx:32ERd32 ERd32ERs32ERd32 ~Rd8Rd8 ~Rd16Rd16 ~ERd32ERd32 No of Execution States *1 Condition Code Operation @aa @-ERn/@ERn+ @ERn Rn Size #xx Mnemonic @(d,ERn) Addressing Mode and Instruction Length (Bytes) I H N Z V C N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N N N N N N N N N N N N N N N N N N N N N Advanced Mode 1 1 2 1 3 2 1 1 2 1 3 2 1 1 2 1 3 2 1 1 1 (4) Shift Instructions SHAL SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHLR SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd ROTXL ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd ROTXR ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd ROTL ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd B B W W L L B B W W L L B B W W L L B B W W L L B B W W L L B B W W L L B B W W L L B B W W L L 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Condition Code -- @@aa @(d,PC) Operation @aa @-ERn/@ERn+ @ERn Rn Size #xx Mnemonic @(d,ERn) Addressing Mode and Instruction Length (Bytes) I 0 C MSB LSB MSB LSB C C MSB LSB 0 0 MSB C MSB MSB C MSB MSB LSB C LSB LSB C LSB LSB C -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- H N Z V C -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 No of Execution States *1 Advanced Mode 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Rev. 0.1, 11/98, page 783 of 975 (5) Bit Manipulation Instructions BSET BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BCLR BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BNOT BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BTST BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BLD BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BILD BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BST BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BIST BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BAND BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 Rev. 0.1, 11/98, page 784 of 975 4 6 8 -- @@aa @(d,PC) I (#xx:3 of Rd8)1 (#xx:3 of @ERd)1 (#xx:3 of @aa:8)1 (#xx:3 of @aa:16)1 (#xx:3 of @aa:32)1 (Rn8 of Rd8)1 (Rn8 of @ERd)1 (Rn8 of @aa:8)1 (Rn8 of @aa:16)1 (Rn8 of @aa:32)1 (#xx:3 of Rd8)0 (#xx:3 of @ERd)0 (#xx:3 of @aa:8)0 (#xx:3 of @aa:16)0 (#xx:3 of @aa:32)0 (Rn8 of Rd8)0 (Rn8 of @ERd)0 (Rn8 of @aa:8)0 (Rn8 of @aa:16)0 (Rn8 of @aa:32)0 (#xx:3 of Rd8)[~(#xx:3 of Rd8)] (#xx:3 of @ERd)[~(#xx:3 of @ERd)] (#xx:3 of @aa:8)[~(#xx:3 of @aa:8)] (#xx:3 of @aa:16)[~(#xx:3 of @aa:16)] (#xx:3 of @aa:32)[~(#xx:3 of @aa:32)] (Rn8 of Rd8)[~(Rn8 of Rd8)] (Rn8 of @ERd)[~(Rn8 of @ERd)] (Rn8 of @aa:8)[~(Rn8 of @aa:8)] (Rn8 of @aa:16)[~(Rn8 of @aa:16)] (Rn8 of @aa:32)[~(Rn8 of @aa:32)] ~(#xx:3 of Rd8)Z ~(#xx:3 of @ERd)Z ~(#xx:3 of @aa:8)Z ~(#xx:3 of @aa:16)Z ~(#xx:3 of @aa:32)Z ~(Rn8 of Rd8)Z ~(Rn8 of @ERd)Z ~(Rn8 of @aa:8)Z ~(Rn8 of @aa:16)Z ~(Rn8 of @aa:32)Z (#xx:3 of Rd8)C (#xx:3 of @ERd)C (#xx:3 of @aa:8)C (#xx:3 of @aa:16)C (#xx:3 of @aa:32)C ~(#xx:3 of Rd8)C ~(#xx:3 of @ERd)C ~(#xx:3 of @aa:8)C ~(#xx:3 of @aa:16)C ~(#xx:3 of @aa:32)C C(#xx:3 of Rd8) C(#xx:3 of @ERd) C(#xx:3 of @aa:8) C(#xx:3 of @aa:16) C(#xx:3 of @aa:32) ~C(#xx:3 of Rd8) ~C(#xx:3 of @ERd) ~C(#xx:3 of @aa:8) ~C(#xx:3 of @aa:16) ~C(#xx:3 of @aa:32) C(#xx:3 of Rd8)C C(#xx:3 of @ERd)C C(#xx:3 of @aa:8)C C(#xx:3 of @aa:16)C C(#xx:3 of @aa:32)C No of Execution States *1 Condition Code Operation @aa @-ERn/@ERn+ @ERn Rn Size #xx Mnemonic @(d,ERn) Addressing Mode and Instruction Length (Bytes) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- H N Z V C -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Advanced Mode 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 1 4 4 5 6 1 4 4 5 6 1 3 3 4 5 (5) Bit Manipulation Instructions BIAND BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BOR BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BIOR BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 BIXOR BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 B B B B B B B B B B B B B B B B B B B B B B B B B Condition Code 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 6 8 -- @@aa @(d,PC) Operation @aa @-ERn/@ERn+ @ERn Rn Size #xx Mnemonic @(d,ERn) Addressing Mode and Instruction Length (Bytes) I C [~(#xx:3 of Rd8)]C C [~(#xx:3 of @ERd)]C C [~(#xx:3 of @aa:8)]C C [~(#xx:3 of @aa:16)]C C [~(#xx:3 of @aa:32)]C C(#xx:3 of Rd8)C C(#xx:3 of @ERd)C C(#xx:3 of @aa:8)C C(#xx:3 of @aa:16)C C(#xx:3 of @aa:32)C C [~(#xx:3 of Rd8)]C C [~(#xx:3 of @ERd)]C C [~(#xx:3 of @aa:8)]C C [~(#xx:3 of @aa:16)]C C [~(#xx:3 of @aa:32)]C C (#xx:3 of Rd8)C C (#xx:3 of @ERd)C C (#xx:3 of @aa:8)C C (#xx:3 of @aa:16)C C (#xx:3 of @aa:32)C C [~(#xx:3 of Rd8)]C C [~(#xx:3 of @ERd)]C C [~(#xx:3 of @aa:8)]C C [~(#xx:3 of @aa:16)]C C [~(#xx:3 of @aa:32)]C -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- No of Execution States *1 H N Z V C Advanced Mode -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Rev. 0.1, 11/98, page 785 of 975 (6) Branch Instructions Bcc JMP BSR JSR RTS -- @@aa @(d,PC) 2 4 2 2 4 2 Rev. 0.1, 11/98, page 786 of 975 Branch Condition 4 2 2 I -- -- -- Never -- CZ=0 -- -- CZ=1 -- -- -- C=0 -- -- C=1 -- -- Z=0 -- -- Z=1 -- -- V=0 -- -- V=1 -- -- N=0 -- -- N=1 -- NV=0 -- -- NV=1 -- -- Z(NV)=0 -- -- Z(NV)=1 -- -- -- PCERn -- PCaa:24 -- PC@aa:8 -- PC@-SP,PCPC+d:8 -- PC@-SP,PCPC+d:16 -- PC@-SP,PCERn -- PC@-SP,PCaa:24 -- PC@-SP,PC@aa:8 -- PC@SP+ if condition is true then PCPC+d else next; 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 No of Execution States *1 Operation Code Operation @aa @-ERn/@ERn+ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- @(d,ERn) BRA d:8(BT d:8) BRA d:16(BT d:16) BRN d:8(BF d:8) BRN d:16(BF d:16) BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8(BHS d:8) BCC d:16(BHS d:16) BCS d:8(BLO d:8) BCS d:16(BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 JMP @ERn JMP @aa:24 JMP @@aa:8 BSR d:8 BSR d:16 JSR @ERn JSR @aa:24 JSR @@aa:8 RTS @ERn Size #xx Mnemonic Rn Addressing Mode and Instruction Length (Bytes) Always H N Z V C Advanced Mode -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 5 4 5 4 5 6 5 (7) System Control Instructions TRAPA TRAPA #xx:2 -- RTE -- RTE SLEEP SLEEP LDC LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR STC STC CCR,Rd STC EXR,Rd STC CCR,@ERd STC EXR,@ERd STC CCR,@(d:16,ERd) STC EXR,@(d:16,ERd) STC CCR,@(d:32,ERd) STC EXR,@(d:32,ERd) STC CCR,@-ERd STC EXR,@-ERd STC CCR,@aa:16 STC EXR,@aa:16 STC CCR,@aa:32 STC EXR,@aa:32 ANDC ANDC #xx:8,CCR ANDC #xx:8,EXR ORC ORC #xx:8,CCR ORC #xx:8,EXR XORC XORC #xx:8,CCR XORC #xx:8,EXR NOP NOP -- B B B B W W W W W W W W W W W W B B W W W W W W W W W W W W B B B B B B -- -- @@aa @(d,PC) 2 4 2 2 4 4 6 6 10 10 4 4 6 6 8 8 2 2 4 4 6 6 10 10 4 4 6 6 8 8 2 4 2 4 2 4 2 No of Execution States *1 Condition Code Operation @aa @-ERn/@ERn+ @ERn Rn Size #xx Mnemonic @(d,ERn) Addressing Mode and Instruction Length (Bytes) I PC@-SP,CCR@-SP, EXR@-SP,<Vector>PC EXR@SP+,CCR@SP+, PC@SP+ Transition to power-down state #xx:8CCR #xx:8EXR Rs8CCR Rs8EXR @ERsCCR @ERsEXR @(d:16,ERs)CCR @(d:16,ERs)EXR @(d:32,ERs)CCR @(d:32,ERs)EXR @ERsCCR,ERs32+2ERs32 @ERsEXR,ERs32+2ERs32 @aa:16CCR @aa:16EXR @aa:32CCR @aa:32EXR CCRRd8 EXRRd8 CCR@ERd EXR@ERd CCR@(d:16,ERd) EXR@(d:16,ERd) CCR@(d:32,ERd) EXR@(d:32,ERd) ERd32-2ERd32,CCR@ERd ERd32-2ERd32,EXR@ERd CCR@aa:16 EXR@aa:16 CCR@aa:32 EXR@aa:32 CCR#xx:8CCR EXR #xx:8EXR CCR#xx:8CCR EXR#xx:8EXR CCR#xx:8CCR EXR#xx:8EXR PCPC+2 H N Z V C 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Advanced Mode 8 [9] 5 [9] 2 1 2 1 1 3 3 4 4 6 6 4 4 4 4 5 5 1 1 3 3 4 4 6 6 4 4 4 4 5 5 1 2 1 2 1 2 1 Rev. 0.1, 11/98, page 787 of 975 (8) Block Transfer Instructions Condition Code -- @@aa @(d,PC) Operation @aa @-ERn/@ERn+ @ERn Rn Size #xx Mnemonic @(d,ERn) Addressing Mode and Instruction Length (Bytes) EEPMOV EEPMOV.B -- 4 EEPMOV.W -- 4 I if R4L0 Repeat @ER5@ER6 ER5+1ER5 ER6+1ER6 R4L-1R4L Until R4L=0 else next; if R40 Repeat @ER5@ER6 ER5+1ER5 ER6+1ER6 R4-1R4 Until R4=0 else next; H N Z V C No of Execution States *1 Advanced Mode -- -- -- -- -- -- 4+2n *2 -- -- -- -- -- -- 4+2n *2 Notes: 1. The values indicated in the column of number of execution states apply when instruction code and operand exist in the on-chip memory. 2. n is the initial setting value of R4L or R4. [1] 7 states when the number of return/retract registers is 2, 9 states when the number of registers is 3, and 11 states when the number of registers is 4. [2] Cannot be used in this LSI. [3] Set to 1 when a carry or borrow occurs at bit 11, otherwise cleared to 0. [4] Set to 1 when a carry or borrow occurs at bit 27, otherwise cleared to 0. [5] Retains the value before computation when the computation result is 0, otherwise cleared to 0. [6] Set to 1 when the divisor is negative, otherwise cleared to 0. [7] Set to 1 when the divisor is 0, otherwise cleared to 0. [8] Set to 1 when the quotient is negative, otherwise cleared to 0. [9] 1 is added to the number of execution states when EXR is valid. Rev. 0.1, 11/98, page 788 of 975 Bcc BAND ANDC AND ADDX ADDS ADD Instruction ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS #1,ERd ADDS #2,ERd ADDS #4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC #xx:8,CCR ANDC #xx:8,EXR BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BRA d:8 (BT d:8) BRA d:16 (BT d:16) BRN d:8 (BF d:8) BRN d:16 (BF d:16) BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8 (BHS d:8) BCC d:16 (BHS d:16) BCS d:8 (BLO d:8) BCS d:16 (BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 Mnemonic A.2 Instruction Codes (1) Size B B W W L L L L L B B B B W W L L B B B B B B B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1st byte 8 rd 0 8 7 9 0 9 7 A 0 A 0 B 0 B 0 B 9 rd 0 E E rd 1 6 7 9 6 6 7 A 0 1 0 6 0 1 7 6 7 C 7 E 6 A 6 A 4 0 5 8 4 1 5 8 4 2 5 8 4 3 5 8 4 4 5 8 4 5 5 8 4 6 5 8 4 7 5 8 4 8 5 8 4 9 5 8 rs 1 rs 0 1 1 ers 0 0 0 0 8 0 9 IMM rs IMM rs 6 rs 0 6 F IMM 4 0 IMM 0 erd abs 1 3 disp 0 disp 1 disp 2 disp 3 disp 4 disp 5 disp 6 disp 7 disp 8 disp 9 IMM 4th byte IMM IMM disp disp disp disp disp disp disp disp disp 0 0 0 0 0 0 0 0 0 IMM 0 IMM abs IMM 0 0 abs 0 ers 0 erd 0 6 6 6 6 IMM IMM disp 7 7 0 6 3rd byte 0 0 0 1 rd 0 rd rd rd erd 0 rd rd rd rd erd erd erd erd erd 2nd byte 7 6 0 IMM 0 6th byte Instruction Format 5th byte 7 6 7the byte 0 IMM 0 8th byte 9th byte 10th byte A.2 Instruction Codes Rev. 0.1, 11/98, page 789 of 975 Rev. 0.1, 11/98, page 790 of 975 BIST BIOR BILD BIAND BCLR Bcc (Cont.) Instruction BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 Mnemonic A.2 Instruction Code (2) -- -- -- -- -- -- -- -- -- -- -- -- B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B Size 1st byte 4 A 5 8 4 B 5 8 4 C 5 8 4 D 5 8 4 E 5 8 4 F 5 8 7 2 7 D 7 F 6 A 6 A 6 2 7 D 7 F 6 A 6 A 7 6 7 C 7 E 6 A 6 A 7 7 7 C 7 E 6 A 6 A 7 4 7 C 7 E 6 A 6 A 6 7 7 D 7 F 6 A 6 A 2nd byte disp A 0 disp B 0 disp 0 C disp D 0 disp E 0 disp F 0 0 IMM rd 0 erd 0 abs 1 8 3 8 rn rd 0 erd 0 abs 1 8 3 8 1 IMM rd 0 erd 0 abs 1 0 3 0 1 IMM rd 0 erd 0 abs 1 0 3 0 1 IMM rd 0 erd 0 abs 1 0 3 0 1 IMM rd 0 erd 0 abs 1 8 3 8 6 6 7 7 7 7 7 7 4 4 7 7 6 6 2 2 6 6 7 7 2 2 7 7 3rd byte 1 IMM 1 IMM abs 1 IMM 1 IMM abs 1 IMM 1 IMM abs 1 IMM 1 IMM abs abs rn rn 0 IMM 0 IMM abs disp disp disp disp disp disp 0 0 0 0 0 0 0 0 0 0 0 0 4th byte abs abs abs abs abs abs 6 7 7 7 6 7 7 4 7 6 2 2 1 IMM 1 IMM 1 IMM 1 IMM rn 0 IMM 0 0 0 0 0 0 6th byte Instruction Format 5th byte 6 7 7 7 6 7 7 4 7 6 2 2 7th byte 1 IMM 1 IMM 1 IMM 1 IMM rn 0 IMM 0 0 0 0 0 0 8th byte 9th byte 10th byte Rev. 0.1, 11/98, page 791 of 975 BST BSR BSET BOR BNOT BLD BIXOR Instruction BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR d:8 BSR d:16 BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 Mnemonic A.2 Instruction Code (3) B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B -- -- B B B B B Size 1st byte 7 5 7 C 7 E 6 A 6 A 7 7 7 C 7 E 6 A 6 A 7 1 7 D 7 F 6 A 6 A 6 1 7 D 7 F 6 A 6 A 7 4 7 C 7 E 6 A 6 A 7 0 7 D 7 F 6 A 6 A 6 0 7 D 7 F 6 A 6 A 5 5 5 C 6 7 7 D 7 F 6 A 6 A 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2nd byte IMM rd erd 0 abs 1 0 3 0 IMM rd erd 0 abs 1 0 3 0 IMM rd erd 0 abs 1 8 3 8 rn rd erd 0 abs 1 8 3 8 IMM rd erd 0 abs 1 0 3 0 IMM rd erd 0 abs 1 8 3 8 rn rd erd 0 abs 1 8 3 8 disp 0 0 IMM rd erd 0 abs 1 8 3 8 7 7 0 0 6 6 6 6 0 0 7 7 4 4 1 1 6 6 7 7 1 1 7 7 5 5 7 7 7 7 7 7 3rd byte 0 IMM 0 IMM abs disp abs rn rn 0 IMM 0 IMM abs 0 IMM 0 IMM abs abs rn rn 0 IMM 0 IMM abs 0 IMM 0 IMM abs 1 IMM 1 IMM abs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4th byte abs abs abs abs abs abs abs abs 6 6 7 7 6 7 7 7 7 0 0 4 1 1 7 5 0 IMM rn 0 IMM 0 IMM rn 0 IMM 0 IMM 1 IMM 0 0 0 0 0 0 0 0 6th byte Instruction Format 5th byte 6 6 7 7 6 7 7 7 7 0 0 4 1 1 7 5 7th byte 0 IMM rn 0 IMM 0 IMM rn 0 IMM 0 IMM 1 IMM 0 0 0 0 0 0 0 0 8th byte 9th byte 10th byte Rev. 0.1, 11/98, page 792 of 975 EXTU EXTS EEPMOV DIVXU DIVXS DAA DAS DEC CLRMAC CMP BXOR BTST Instruction BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA Rd DAS Rd DEC.B Rd DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DEC.L #2,ERd DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV.B EEPMOV.W EXTS.W Rd EXTS.L ERd EXTU.W Rd EXTU.L ERd Mnemonic A.2 Instruction Code (4) B B B B B B B B B B B B B B B -- B B W W L L B B B W W L L B W B W -- -- W L W L Size A 1 7 1 7 1 0 1 1 1 1 1 1 0 0 5 5 7 7 1 1 1 1 rd C 9 D A F F F A B B B B 1 1 1 3 B B 7 7 7 7 rs 2 rs 2 1 ers 0 0 0 5 D 7 F D D rs rs 5 D D F 5 7 IMM rd rd rd 0 erd 0 erd rd rd rd rd rd 0 erd 0 erd 0 0 rd 0 erd C 4 rd 0 erd rd 0 erd 5 5 5 5 9 9 1 3 IMM 8 8 rs rs F F rd 0 erd IMM 1st byte 2nd byte 3rd byte 4th byte 7 3 0 IMM rd 7 3 0 IMM 7 0 C 0 erd 0 7 3 0 IMM 7 0 E abs abs 6 A 1 0 6 abs A 3 0 6 3 rn rd 6 3 rn 7 0 C 0 erd 0 6 3 rn 7 0 E abs abs 6 A 1 0 abs 6 A 3 0 7 5 0 IMM rd 7 5 0 IMM 0 7 C 0 erd 0 7 5 0 IMM 0 7 E abs abs 6 A 1 0 abs 6 A 3 0 Cannot be used in the H8S/2194 Series 5 0 IMM rn 3 6 7 0 IMM 3 7 0 0 0 6th byte Instruction Format 5th byte 7 6 7 5 3 3 7th byte 0 IMM rn 0 IMM 0 0 0 8th byte 9th byte 10th byte Rev. 0.1, 11/98, page 793 of 975 MAC MOV LDMAC LDM LDC JSR JMP INC Instruction INC.B Rd INC.W #1,Rd INC.W #2,Rd INC.L #1,ERd INC.L #2,ERd JMP @ERn JMP @aa:24 JMP @@aa:8 JSR @ERn JSR @aa:24 JSR @@aa:8 LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR LDM.L @SP+, (ERn-ERn+1) LDM.L @SP+, (ERn-ERn+2) LDM.L @SP+, (ERn-ERn+3) LDMAC ERs,MACH LDMAC ERs,MACL MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) Mnemonic A.2 Instruction Code (5) B W W L L -- -- -- -- -- -- B B B B W W W W W W W W W W W W L L L L L -- B B B B B B B B B B B B Size 0 4 0 1 4 4 4 4 4 4 4 4 4 4 4 4 1 2 3 1 rs rs 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 abs IMM abs ern 0 2nd byte 0 rd 5 rd D rd 7 0 erd F 0 erd 0 ern 0 9 9 F F 8 8 D D B B B B D D D 6 6 6 6 7 7 6 6 6 6 6 6 6 6 6 F 0 6 6 7 6 2 6 6 6 6 7 rd C 8 E 8 C rd A A 8 E 8 1 1 0 0 0 0 0 IMM rs rd ers rd ers rd ers 0 ers rd abs 0 rd 2 rd erd rs erd rs erd 0 6 6 A A 7 0 abs abs 3rd byte Cannot be used in the H8S/2194 Series 1st byte 0 A 0 B 0 B 0 B 0 B 5 9 5 A 5 B 5 D 5 E 5 F 0 7 0 1 0 3 0 3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 disp abs disp 0 0 0 0 0 0 0 0 A 2 rs rd abs ers 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 0 0 0 0 0 2 0 2 0 7 0 ern+1 7 0 ern+2 7 0 ern+3 IMM 4th byte 6 6 B B abs abs disp disp 2 2 0 0 6th byte Instruction Format 5th byte disp disp abs abs 7th byte 8th byte disp disp 9th byte 10 byte Rev. 0.1, 11/98, page 794 of 975 MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa :16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,Rd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16 ,ERd MOV.L @aa:32 ,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) * MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE @aa:16,Rd MOVTPE Rs,@aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU.B Rs,Rd MULXU.W Rs,ERd NEG.B Rd NEG.W Rd NEG.L ERd NOP MOV (Cont.) NOP NEG MULXU MOVFPE MOVTPE MULXS Mnemonic Instruction A.2 Instruction Code (6) B B B B W W W W W W W W W W W W W W W L L L L L L L L L L L L L B B B W B W B W L -- Size 1 1 1 0 1 0 0 0 0 1 2nd byte erd rs abs 8 rs A rs 0 rd rs rd ers rd ers rd ers 0 ers rd 0 rd 2 rd erd rs erd rs erd 0 erd rs 8 rs A rs 0 0 erd ers 0 erd 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 6 7 6 6 6 6 6 7 6 6 6 6 6 0 0 5 5 1 1 1 0 1 1 0 2 7 7 7 0 C C rs rs 8 9 B 0 0 0 rd 0 erd rd rd 0 erd 0 5 5 0 2 9 F 8 D B B 9 F 8 D B B B B 3rd byte Cannot be used in the H8S/2194 Series 1st byte 6 C 3 rs 6 A 6 A 7 9 0 D 6 9 6 F 7 8 6 D 6 B 6 B 6 9 6 F 7 8 6 D 6 B 6 B 7 A 0 F 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 0 abs disp abs disp IMM abs rs rs ers ers ers ers 0 2 erd erd erd erd 8 A A 2 erd erd 0 erd erd erd ers ers 0 ers ers ers abs IMM abs abs rd 0 erd 0 0 0 0 0 0 0 0 0 0 rs rd 4th byte 6 6 B B abs disp abs disp A 2 disp disp abs 0 ers abs 0 erd 6th byte Instruction Format 5th byte 7th byte 8th byte disp disp 9th byte 10th byte Rev. 0.1, 11/98, page 795 of 975 RTE RTS ROTXR ROTXL ROTR ROTL PUSH POP ORC OR NOT Instruction B W L B B W W L L B B W L W L B B W W L L B B W W L L B B W W L L B B W W L L -- -- Mnemonic NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn POP.L ERn PUSH.W Rn PUSH.L ERn ROTL.B Rd ROTL.B #2, Rd ROTL.W Rd ROTL.W #2, Rd ROTL.L ERd ROTL.L #2, ERd ROTR.B Rd ROTR.B #2, Rd ROTR.W Rd ROTR.W #2, Rd ROTR.L ERd ROTR.L #2, ERd ROTXL.B Rd ROTXL.B #2, Rd ROTXL.W Rd ROTXL.W #2, Rd ROTXL.L ERd ROTXL.L #2, ERd ROTXR.B Rd ROTXR.B #2, Rd ROTXR.W Rd ROTXR.W #2, Rd ROTXR.L ERd ROTXR.L #2, ERd RTE RTS A.2 Instruction Code (7) Size 1st byte 1 7 1 7 1 7 C rd 1 4 7 9 6 4 7 A 0 1 0 4 0 1 6 D 0 1 6 D 0 1 1 2 1 2 1 2 1 2 1 2 1 2 1 3 1 3 1 3 1 3 1 3 1 3 1 2 1 2 1 2 1 2 1 2 1 2 1 3 1 3 1 3 1 3 1 3 1 3 5 6 5 4 2nd byte 0 rd 1 rd 3 0 erd IMM rs rd 4 rd rs rd 4 0 erd F 0 IMM 4 1 7 rn 0 0 F rn 0 0 8 rd C rd 9 rd D rd B 0 erd F 0 erd 8 rd C rd 9 rd D rd B 0 erd F 0 erd 0 rd 4 rd 1 rd 5 rd 3 0 erd 7 0 erd 0 rd 4 rd 1 rd 5 rd 3 0 erd 7 0 erd 7 0 7 0 6 6 0 6 D D 4 4 3rd byte 0 IMM F 7 0 ern 0 ern IMM ers 0 erd 4th byte IMM 6th byte Instruction Format 5th byte 7th byte 8th byte 9th byte 10th byte Rev. 0.1, 11/98, page 796 of 975 STMAC STM SLEEP STC SHLR SHLL SHAR SHAL Instruction SHAL.B Rd SHAL.B #2, Rd SHAL.W Rd SHAL.W #2, Rd SHAL.L ERd SHAL.L #2, ERd SHAR.B Rd SHAR.B #2, Rd SHAR.W Rd SHAR.W #2, Rd SHAR.L ERd SHAR.L #2, ERd SHLL.B Rd SHLL.B #2, Rd SHLL.W Rd SHLL.W #2, Rd SHLL.L ERd SHLL.L #2, ERd SHLR.B Rd SHLR.B #2, Rd SHLR.W Rd SHLR.W #2, Rd SHLR.L ERd SHLR.L #2, ERd SLEEP STC.B CCR,Rd STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd STC.W CCR,@(d:16,ERd) STC.W EXR,@(d:16,ERd) STC.W CCR,@(d:32,ERd) STC.W EXR,@(d:32,ERd) STC.W CCR,@-ERd STC.W EXR,@-ERd STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32 STC.W EXR,@aa:32 STM.L(ERn-ERn+1) , @-SP STM.L (ERn-ERn+2) , @-SP STM.L (ERn-ERn+3) , @-SP STMAC MACH,ERd STMAC MACL,ERd Mnemonic A.2 Instruction Code (8) B B W W L L B B W W L L B B W W L L B B W W L L -- B B W W W W W W W W W W W W L L L L L Size 2nd byte 8 rd C rd 9 rd D rd B 0 erd F 0 erd 8 rd C rd 9 rd D rd B 0 erd F 0 erd 0 rd 4 rd 1 rd 5 rd 3 0 erd 7 0 erd 0 rd 4 rd 1 rd 5 rd 3 0 erd 7 0 erd 8 0 0 rd 1 rd 4 0 4 1 4 0 4 1 4 0 4 1 4 0 4 1 4 0 4 1 4 0 4 1 1 0 2 0 3 0 Cannot be used in this LSI 1st byte 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 2 0 2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 6 6 6 6 7 7 6 6 6 6 6 6 6 6 6 9 9 F F 8 8 D D B B B B D D D 3rd byte 1 1 1 1 0 0 1 1 erd 0 erd 0 erd 0 erd 0 erd 0 erd 0 erd 0 erd 0 8 0 8 0 A 0 A 0 F 0 ern F 0 ern F 0 ern 4th byte 6 6 B B abs abs disp disp A A 0 0 6th byte Instruction Format 5th byte abs abs 7th byte 8th byte disp disp 9th byte 10th byte Rev. 0.1, 11/98, page 797 of 975 SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS #1,ERd SUBS #2,ERd SUBS #4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS @ERd TRAPA #x:2 XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XORC #xx:8,CCR XORC #xx:8,EXR Mnemonic B W W L L L L L B B B -- B B W W L L B B 1st byte 1 8 7 9 1 9 7 A 1 A 1 B 1 B 1 B B rd 1 E 0 1 5 7 D rd 1 5 7 9 6 5 7 A 0 1 0 5 0 1 IMM rd rs 0 E 0 00 IMM IMM rs rd 5 rd rs rd 5 0 erd F 0 IMM 4 1 2nd byte rd rs rd 3 rd rs 0 erd 3 1 ers 0 erd 0 erd 0 0 erd 8 0 erd 9 5 5 6 0 B 7 3rd byte C IMM IMM IMM 0 ers 0 erd IMM 0 erd IMM 4th byte 6th byte Instruction Format 5th byte Note: * Either 1 or 0 can be set to bit 7 in 4th byte of MOV.L Ers, @(d: 32, Erd) instruction. XORC TAS TRAPA XOR SUBX SUBS SUB Instruction A.2 Instruction Code (9) Size 7th byte 8th byte 9th byte 10th byte [Legend] IMM: Immediate data (2, 3, 8, 16, 32 bits) abs: Absolute address (8, 16, 24, 32 bits) disp: Displacement (8, 16, 32 bits) rs, rd, rn: Register fields (8-bit register or 16-bit register is selected in 4 bits. rs, rd and rn correspond to the operand type Rs, Rd, and Rn respectively.) ers, erd, ern, erm: Register fields (address register or 32-bit register is selected in 3 bits. ers, erd ern and erm correspond to the operand type ERs, ERd, ERn and Rm respectively.) The following table shows the correspondence between the register field and the general register. Address Register, 32-bit Register 16-bit Register 8-bit Register General Register Field Register General Register Field Register General Register Field Register 000 ER0 0000 R0 0000 R0H 001 ER1 0001 R1 0001 R1H : : : : : : : : : : : : : : : : : : : : : : : : 111 ER7 0111 R7 0111 R7H 1000 E0 1000 R0L 1001 E1 1001 R1L : : : : : : : : : : : : : : : : 1111 E7 1111 R7L Rev. 0.1, 11/98, page 798 of 975 AL 3 BL BSR BCS XOR XORC RTE BNE AND ANDC TRAPA BEQ ADD MOV OR XOR AND MOV C D E F SUB ADD BVS 9 Table A.3(2) MOV Table A.3(2) SUBX Note: * Cannot be used in this LSI 8 BVC MOV.B Table A.3(2) LDC 7 BST OR AND XOR BIST BXOR BAND BOR BLD BIXOR BIAND BIOR BILD RTS BCC OR ORC 6 B BTST DIVXU BLS Table A.3(2) 5 CMP BCLR MULXU BHI Table A.3(2) 4 BH highest bit is set to 1 BH highest bit is set to 0. ADDX BNOT 2 BH LDC STC * * STMAC LDMAC AL 2nd byte 9 BSET DIVXU BRN Table A.3(2) Table A.3(2) 1 AH 1st byte A 8 7 6 BRA MULXU 5 NOP 0 4 3 2 1 0 AH Instruction code: Table A.3 Operation Code Map (1) A Table A.3(2) Table A.3(2) JMP BPL Table A.3(2) Table A.3(2) B EEPMOV BMI Table A.3(2) Table A.3(2) BSR BGE C CMP BLT JSR BGT SUBX ADDX E Table A.3(3) MOV MOV D F BLE Table A.3(2) Table A.3(2) A.3 Operation Code Map Table A.3 shows an operation code map. Rev. 0.1, 11/98, page 799 of 975 Rev. 0.1, 11/98, page 800 of 975 1 MOV 01 13 SUBS DAS BRA MOV MOV MOV 1B 1F 58 6A 79 7A ADD CMP CMP MOV Table A.3(4) ADD BHI 2 SUB SUB Table A.3(4) BLS NOT STM 3 BL 2nd byte BH BRN AL Note: * Cannot be used in this LSI DEC 1A NOT ROTXL ROTXR 12 17 SHLR 11 0F SHLL DAA 0B 10 INC ADDS 0A AH AL LDM AH 1st byte 0 BH Instruction code: Table A.3 Operation Code Map (2) OR OR * MOVFPE BCC ROTXR ROTXL SHLR SHLL STC 4 LDC XOR XOR BCS DEC EXTU INC 5 AND AND BNE MAC* 6 BEQ DEC EXTU ROTXR ROTXL SHLR SHLL INC 7 MOV BVC 9 BVS SUBS NEG ROTR ROTL SHAR SHAL ADDS SLEEP 8 MOV BPL CLRMAC* A BMI NEG B C BGE * MOVTPE CMP SUB ROTR ROTL SHAR SHAL MOV ADD Table A.3(3) D BLT DEC EXTS INC Table A.3(3) BGT TAS E F BLE DEC EXTS ROTR ROTL SHAR SHAL INC Table A.3(3) Rev. 0.1, 11/98, page 801 of 975 0 2 BCLR MULXS 3 BNOT BNOT BCLR BCLR r is the register specification section. Absolute address is set at aa. BSET Notes: 1. 2. 7Faa7 BSET *2 BTST 7Eaa7 7Faa6 *2 BTST BCLR *2 BNOT 7Eaa6 BSET 7Dr07 *1 *2 BSET 7Dr06 *1 XOR 5 DH AND 6 DL 4th byte 7 BXOR BAND BLD BOR BIXOR BIAND BILD BIOR BST BIST BXOR BAND BLD BOR BIXOR BIAND BILD BIOR BST BIST OR 4 CL 3rd byte CH DIVXS BL BTST BNOT DIVXS 1 BH 7Cr07 *1 MULXS AL 2nd byte BTST CL AH 1st byte 7Cr06 *1 01F06 01D05 01C05 AH AL BH BL CH Instruction code: Table A.3 Operation Code Map (3) 8 9 A B C D DH highest bit is set to 0. DH highest bit is set to 1. E F Rev. 0.1, 11/98, page 802 of 975 BSET 0 AH BNOT 1 AL 1st byte BNOT 1 0 BSET AL AH 1st byte Note: * Absolute address is set at aa. 6A38aaaaaaaa7* 6A38aaaaaaaa6* 6A30aaaaaaaa7* 6A30aaaaaaaa6* AHALBHBL ... FHFLGH GL Instruction code: 6A18aaaa7* 6A18aaaa6* 6A10aaaa7* 6A10aaaa6* AHALBHBLCHCLDHDLEH EL Instruction code: BCLR 2 BH 3 3 6 DL 7 EH EL 5th byte 5 DH 6 DL 4th byte 7 EH EL 5th byte BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 4 CL 3rd byte CH BTST BL 5 DH 4th byte BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 4 CL 3th byte CH BTST BL 2nd byte BCLR 2 BH 2nd byte Table A.3 Operation Code Map (4) 8 8 9 FL FH 9 FL 6th byte FH 6th byte A B HH HL 8th byte C D B C D HH highest bit is set to 0. HH highest bit is set to 1. GL 7th byte GH A FH highest bit is set to 0. FH highest bit is set to 1. E E F F A.4 Number of Execution States This section explains execution state and how to calculate the number of execution states for each instruction of the H8S/2194 CPU. Table A.5 indicates number of cycles of instruction fetch and data read/write during instruction execution, and table A.4 indicates number of states required for each instruction size. The number of execution states can be obtained from the equation below. Number of execution states = I SI + J SJ + K SK + L SL + M SM + N SN (1) Examples of execution state number calculation The conditions are as follows: In advanced mode, program and stack areas are set in the onchip memory, a wait is inserted every 2 states in the on-chip supporting module access with 8-bit bus width. 1. BSET #0, @FFFFC7:8 From Table A.5, I = L = 2, J = K = M = N = 0 From Table A.4, SI = 1, SL = 2 Number of execution states = 2 x 1 + 2 x 2 = 6 2. JSR @@30 From Table A.5, I = J = K = 2, L = M = N = 0 From Table A.4, SI = SJ = SK = 1 Number of execution states = 2 x 1 + 2 x 1 + 2 x 1 = 6 Rev. 0.1, 11/98, page 803 of 975 Table A.4 Number of States Required for Each Execution Status (Cycle) Target of Access On-Chip Supporting Module Execution Status (Cycle) On-Chip Memory 8-bit bus 16-bit bus Instruction fetch SI 1 -- -- Byte data access SL 2 2 Word data access SM 4 Branch address read SJ Stack operation SK Internal operation SN 1 Rev. 0.1, 11/98, page 804 of 975 Table A.5 Instruction Execution Status (No. of Cycles) (1) Instruction Fetch Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation Instruction Mnemonic I J K L M N ADD ADD.B #xx:8,Rd ADD.B Rs, Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD L #xx:32,ERd ADD.L ERs,ERd 1 1 2 1 3 1 ADDS ADDS #1/2/4,ERd 1 ADDX ADDX #xx:8,Rd ADDX Rs,Rd 1 1 AND AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx.16,Rd AND.W Rs,Rd AND L #xx:32,ERd AND.L ERs,ERd 1 1 2 1 3 2 ANDC ANDC #xx:8,CCR ANDC #xx:8,EXR 1 2 BAND BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3@aa:8 BAND #xx:3@aa:16 BAND #xx:3@aa:32 1 2 2 3 4 BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Bcc 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Rev. 0.1, 11/98, page 805 of 975 Table A.5 Instruction Execution Status (No. of Cycles) (2) Instruction Fetch Branch Address Read Stack Operation Byte Data Access Word Data Access Instruction Mnemonic I J K L M Bcc BGT d:16 BLE d:16 2 2 BCLR BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 1 2 2 3 4 1 2 2 3 4 BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 1 2 2 3 4 1 1 1 1 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 1 2 2 3 4 1 1 1 1 BIOR #xx:8,Rd BIOR #xx:8,@ERd BIOR #xx:8,@aa:8 BIOR #xx:8,@aa:16 BIOR #xx:8,@aa:32 1 2 2 3 4 1 1 1 1 BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 1 2 2 3 4 2 2 2 2 BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 1 2 2 3 4 1 1 1 1 BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 1 2 2 3 4 1 1 1 1 BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 1 2 2 3 4 1 2 2 3 BIAND BILD BIOR BIST BIXOR BLD BNOT Rev. 0.1, 11/98, page 806 of 975 Internal Operation N 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Table A.5 Instruction Execution Status (No. of Cycles) (3) Instruction Fetch Branch Address Read Stack Operation Instruction Mnemonic I J K BNOT BNOT Rn,@aa:32 4 2 BOR BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 1 2 2 3 4 1 1 1 1 BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 1 2 2 3 4 1 2 2 3 4 BSET BSR 2 2 2 2 BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 1 2 2 3 4 BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 1 2 2 3 4 1 2 2 3 4 BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 1 2 2 3 4 CLRMAC CLRMAC Cannot be used in this LSI. CMP CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd 1 1 2 1 3 1 DAA DAA Rd 1 DAS DAS Rd 1 BXOR Internal Operation L M N 2 2 2 2 BSR d:8 BTST Word Data Access 2 2 2 2 BSR d:16 BST Byte Data Access 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 Rev. 0.1, 11/98, page 807 of 975 Table A.5 Instruction Execution Status (No. of Cycles) (4) Instruction Fetch Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation Instruction Mnemonic I J K L M N DEC DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2 ERd 1 1 1 DIVXS DIVXS.B Rs,Rd DIVXS.W Rs,ERd 2 2 11 19 DIVXU DIVXU.B Rs,Rd DIVXU.W Rs,ERd 1 1 11 19 EEPMOV EEPMOV.B EEPMOV.W 2 2 EXTS EXTS.W Rd EXTS.L ERd 1 1 EXTU EXTU.W Rd EXTU.L ERd 1 1 INC INC.B Rd INC.W #1/2,Rd INC.L #1/2,ERd 1 1 1 JMP JMP @ERN JMP @aa:24 2 2 JMP @@aa:8 2 JSR *2 2n+2 *2 2n+2 1 2 1 JSR @ERn 2 2 JSR @aa:24 2 2 JSR @@aa:8 2 LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR 1 2 1 1 2 2 3 3 5 5 2 2 3 3 4 4 LDM.L @SP+,(ERn- ERn+1) LDM.L @SP+,(ERn- ERn+2) LDM.L @SP+,(ERn- ERn+3) 2 4 1 2 6 1 2 8 1 LDMAC LDMAC ERs,MACH LDMAC ERs,MACL Cannot be used in this LSI. MAC MAC @ERn+,@ERm+ LCD LDM Rev. 0.1, 11/98, page 808 of 975 2 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Table A.5 Instruction Execution Status (No. of Cycles) (5) Instruction Fetch Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation Instruction Mnemonic I J K L M N MOV MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 1 1 1 2 4 1 1 2 3 1 2 4 1 1 2 3 2 1 1 2 4 1 2 3 1 2 4 1 2 3 3 1 2 3 5 2 3 4 2 3 5 2 3 4 MOVFPE MOVFPE @:aa:16,Rd Cannot be used in this LSI. MOVTPE MOVTPE Rs,@:aa:16 MULXS MULXU 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 MULXS.B Rs,Rd 2 11 MULXS.W Rs,ERd 2 19 MULXU.B Rs,Rd 1 11 MULXU.W Rs,ERd 1 19 Rev. 0.1, 11/98, page 809 of 975 Table A.5 Instruction Execution Status (No. of Cycles) (6) Instruction Fetch Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation Instruction Mnemonic I J K L M N NEG 1 1 1 NEG.B Rd NEG.W Rd NEG.L ERd NOP NOP 1 NOT NOT.B Rd NOT.W Rd NOT.L ERd 1 1 1 OR OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd 1 1 2 1 3 2 ORC ORC #xx:8,CCR ORC #xx:8,EXR 1 2 POP POP.W Rn POP.L ERn 1 2 1 2 1 1 PUSH PUSH.W Rn PUSH.L ERn 1 2 1 2 1 1 ROTL ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd 1 1 1 1 1 1 ROTR ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd 1 1 1 1 1 1 ROTXL ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd 1 1 1 1 1 1 ROTXR ROTXR.B Rd RPTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd 1 1 1 1 1 1 RTE RTE 2 2/3 1 RTS RTS 2 2 1 Rev. 0.1, 11/98, page 810 of 975 *1 Table A.5 Instruction Execution Status (No. of Cycles) (7) Instruction Fetch Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation Instruction Mnemonic I J K L M N SHAL SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd 1 1 1 1 1 1 SHAR SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd 1 1 1 1 1 1 SHLL SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd 1 1 1 1 1 1 SHLR SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd 1 1 1 1 1 1 SLEEP SLEEP 1 STC STC.B CCR.Rd STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd STC.W CCR,@(d:16,ERd) STC.W EXR,@(d:16,ERd) STC.W CCR,@(d:32,ERd) STC.W EXR,@(d:32,ERd) STC.W CCR,@-ERd STC.W EXR,@-ERd STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32 STC.W EXR,@aa:32 1 1 2 2 3 3 5 5 2 2 3 3 4 4 STM.L (ERn-ERn+1), @-Sp STM.L (ERn-ERn+2), @-Sp STM.L (ERn-ERn+3), @-Sp 2 4 1 2 6 1 2 8 1 STMAC STMAC MACH,ERd STMAC MACL,ERd Cannot be used in this LSI. SUB SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd 1 2 1 3 1 SUBS SUBS #1/2/4,ERd 1 STM 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Rev. 0.1, 11/98, page 811 of 975 Table A.5 Instruction Execution Status (No. of Cycles) (8) Instruction Fetch Branch Address Read Stack Operation Byte Data Access Word Data Access Internal Operation Instruction Mnemonic I J K L M N SUBX SUBX #xx:8,Rd SUBX Rs,Rd 1 1 TAS TAS @ERd 2 TRAPA TRAPA #x:2 2 2 2/3 XOR XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd 1 1 2 1 3 2 XORC XORC #xx:8,CCR XORC #xx:8,EXR 1 2 2 *1 Notes: 1. 3 applies when EXR is valid, and 2 applies when invalid. 2. Applies when the transfer data is n bytes. Rev. 0.1, 11/98, page 812 of 975 2 A.5 Bus Status During Instruction Execution Table A.6 indicates execution status of each instruction available in this LSI. For the number of states required for each execution status, see table A.4, Number of States Required for Each Execution Status (Cycle). [How to see the table] Order of execution Instruction JMP@aa:24 1 R:W 2nd 2 Internal operation 1 state 3 4 5 6 7 8 R:W EA End of instruction Effective address is read by word. Read/write not executed The 2nd word of the instruction currently being executed is read by word. [Legend] R:B Read by byte R:W Read by word W:B Write by byte W:W Write by word :M Bus not transferred immediately after this cycle 2nd Address of the 2nd word (3rd and 4th bytes) 3rd Address of the 3rd word (5th and 6th bytes) 4th Address of the 4th word (7th and 8th bytes) 5th Address of the 5th word (9th and 10th bytes) NEXT The head address of the instruction immediately after the instruction currently being executed EA Execution address VEC Vector address Rev. 0.1, 11/98, page 813 of 975 Table A.6 Instruction ADD.B #xx:8,Rd Instruction Execution Status (1) 1 R:W NEXT ADD.B Rs,Rd R:W NEXT ADD.W #xx:16,Rd R:W 2nd ADD.W Rs,Rd R:W NEXT ADD.L #xx:32,ERd R:W 2nd ADD.L ERs,ERd R:W NEXT ADDS #1/2/4,ERd R:W NEXT ADDX #xx:8,Rd R:W NEXT ADDX Rs,Rd R:W NEXT AND.B #xx:8,Rd R:W NEXT 2 3 R:W NEXT R:W 3rd AND.B Rs,Rd R:W NEXT AND.W #xx:16,Rd R:W 2nd AND.W Rs,Rd R:W NEXT AND.L #xx:32,ERd R:W 2nd R:W 3rd AND.L ERs,ERd R:W 2nd R:W NEXT ANDC #xx:8,CCR R:W NEXT R:W NEXT R:W NEXT R:W NEXT ANDC #xx:8,EXR R:W 2nd BAND #xx:3,Rd R:W NEXT BAND #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT BAND #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT BAND #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA BAND #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:W NEXT BRA d:8 (BT d:8) R:W NEXT R:W EA BRN d:8 (BT d:8) R:W NEXT R:W EA BHI d:8 R:W NEXT R:W EA BLS d:8 R:W NEXT R:W EA R:W NEXT R:W EA BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 4 R:W NEXT R:W EA R:W NEXT R:W EA R:W NEXT R:W EA BVC d:8 R:W NEXT R:W EA BVS d:8 R:W NEXT R:W EA BPL d:8 R:W NEXT R:W EA BMI d:8 R:W NEXT R:W EA BGE d:8 R:W NEXT R:W EA BLT d:8 R:W NEXT R:W EA BGT d:8 R:W NEXT R:W EA BLE d:8 R:W NEXT R:W EA BRA d:16 (BT d:16) R:W 2nd Internal operation 1 state R:W EA BRN d:16 (BF d:16) R:W 2nd Internal operation 1 state R:W EA BHI d:16 R:W 2nd Internal operation 1 state R:W EA BLS d:16 R:W 2nd Internal operation 1 state R:W EA BCC d:16 d:16) (BHS R:W 2nd Internal operation 1 state R:W EA BCS d:16 (BLO d:16) R:W 2nd Internal operation 1 state R:W EA BNE d:16 R:W 2nd Internal operation 1 state R:W EA BEQ d:16 R:W 2nd Internal operation 1 state R:W EA BVC d:16 R:W 2nd Internal operation 1 state R:W EA BVS d:16 R:W 2nd Internal operation 1 state R:W EA BPL d:16 R:W 2nd Internal operation 1 state R:W EA BMI d:16 R:W 2nd Internal operation 1 state R:W EA BGE d:16 R:W 2nd Internal operation 1 state R:W EA Rev. 0.1, 11/98, page 814 of 975 R:W:M NEXT 5 6 7 8 9 Table A.6 Instruction Execution Status (2) Instruction 1 2 3 BLT d:16 R:W 2nd Internal operation 1 state R:W EA BGT d:16 R:W 2nd Internal operation 1 state R:W EA BLE d:16 R:W 2nd Internal operation 1 state R:W EA 4 5 BCLR #xx:3,Rd R:W NEXT BCLR #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA BCLR #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA BCLR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA BCLR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT BCLR Rn,Rd R:W NEXT BCLR Rn,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA BCLR Rn,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA BCLR Rn,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA BCLR Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT BIAND #xx:3,Rd R:W NEXT BIAND #xx:3,ERd R:W 2nd R:B EA R:W:M NEXT BIAND #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT BIAND #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT BIAND #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA BILD #xx:3,Rd R:W NEXT BILD #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT BILD #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT BILD #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT BILD #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA BIOR #xx:3,Rd R:W NEXT R:W 2nd R:B EA R:W:M NEXT R:W 2nd R:B EA R:W:M NEXT BOIR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT BOIR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA BIST #xx:3,Rd R:W NEXT BIST #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA BIST #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA BIST #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA BIST #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT BIXOR #xx:3,Rd R:W NEXT R:W 2nd R:B EA R:W:M NEXT R:W 2nd R:B EA R:W:M NEXT BIXOR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT BIXOR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA BLD #xx:3,Rd R:W NEXT BLD #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT BLD #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT BLD #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT BLD #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA BNOT #xx:3,Rd R:W NEXT R:W 2nd R:B:M EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA BNOT #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA BNOT #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT BNOT Rn,Rd R:W NEXT R:W 2nd R:B:M EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA W:B EA W:B EA R:W:M NEXT R:W 2nd R:W 2nd W:B EA R:W:M NEXT BNOT #xx:3,@aa:8 BNOT Rn @aa:8 9 R:W:M NEXT BNOT #xx:3,ERd BNOT Rn,@ERd 8 R:W:M NEXT BOIR #xx:3,@aa:8 BIXOR #xx:3,@aa:8 7 R:W:M NEXT BIOR #xx:3,@ERd BIXOR #xx:3,@ERd 6 W:B EA Rev. 0.1, 11/98, page 815 of 975 Table A.6 Instruction Execution Status (3) Instruction 1 2 3 4 5 BNOT Rn @aa:16 R:W 2nd R:W 3rd R:B:W EA R:W:M NEXT W:B EA BNOT Rn @aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT BOR #xx:3,Rd R:W NEXT R:W:M NEXT BOR #xx:3,ERd R:W 2nd R:B EA BOR #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT BOR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT BOR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA BSET #xx:3,Rd R:W NEXT R:W 2nd R:B:M EA R:W:M NEXT W:B EA BSET #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA BSET #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA BSET #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT BSET Rn,Rd R:W NEXT BSET Rn,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA BSET Rn,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA BSET Rn,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA BSET Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT BSR d:8 R:W NEXT R:W EA W:W:M stack(H) W:W stack(L) BSR d:16 R:W 2nd Internal operation 1 state R:W EA W:W:M stack(H) W:B EA R:W NEXT BST #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT BST #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA BST #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA BST #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT BTST #xx:3,Rd R:W NEXT R:W 2nd R:B EA R:W:M NEXT R:W 2nd R:B EA R:W:M NEXT BTST #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT BTST #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA BTST Rn,Rd R:W NEXT BTST Rn,@ERd R:W 2nd R:B EA R:W:M NEXT BTST Rn,@aa:8 R:W 2nd R:B EA R:W:M NEXT BTST Rn,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT BTST Rn,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA BOXR #xx:3,Rd R:W NEXT BOXR #xx:3,@ERd R:W 2nd R:B EA R:W:M NEXT BOXR #xx:3,@aa:8 R:W 2nd R:B EA R:W:M NEXT BOXR #xx:3,@aa:16 R:W 2nd R:W 3rd R:B EA R:W:M NEXT BOXR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA CLRMAC Cannot be used in this LSI. CMP.B #xx:8,Rd R:W NEXT CMP.B Rs,Rd R:W NEXT CMP.W #xx:16,Rd R:W 2nd CMP.W Rs,Rd R:W NEXT CMP.L #xx:32,ERd R:W 2nd CMP.L ERs,ERd R:W NEXT DAA Rd R:W NEXT DAS Rd R:W NEXT DEC.B Rd R:W NEXT R:W NEXT R:W 3rd R:W NEXT Rev. 0.1, 11/98, page 816 of 975 W:B EA W:B EA W:W stack(L) BST #xx:3,Rd BTST #xx:3,@aa:8 W:B EA R:W NEXT BSET #xx:3,@ERd BTST #xx:3,@ERd 6 R:W:M NEXT R:W:M NEXT R:W:M NEXT W:B EA 7 8 9 Table A.6 Instruction Execution Status (4) Instruction 1 DEC.W #1/2,Rd R:W NEXT 2 3 DEC.W #1/2,ERd R:W NEXT DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU.B Rs,Rd 4 R:W 2nd R:W NEXT Internal operation 11 state R:W 2nd R:W NEXT Internal operation 19 state R:W NEXT Internal operation 11 state DIVXU.W Rs,ERd R:W NEXT Internal operation 19 state EEPMOV.B R:W 2nd R:B EAs EEPMOV.W R:W 2nd R:B EAs EXTS.W Rd R:W NEXT EXTS.L ERd R:W NEXT EXTU.W Rd R:W NEXT EXTU.L ERd R:W NEXT *1 *1 R:B EAd R:B EAd *1 *1 5 R:B EAs R:B EAs *2 *2 6 W:B EAd W:B EAd Repeat n times *2 8 9 R:W NEXT *2 *2 7 R:W NEXT INC.B Rd R:W NEXT INC.W #1/2,Rd R:W NEXT INC.L #1/2,ERd R:W NEXT JMP @ERn R:W NEXT R:W EA JMP @aa:24 R:W 2nd Internal operation 1 state R:W EA JMP @@aa:8 R:W NEXT R:W:M aa:8 R:W:M aa:8 Internal operation 1 state JSR @ERn R:W NEXT R:W EA W:W:M stack(H) W:W stack (L) JSR @aa:24 R:W 2nd Internal operation 1 state R:W EA W:W:M stack(H) W:W stack (L) JSR @@aa:8 R:W NEXT R:W:M aa:8 R:W aa:8 W:W:M stack(H) W:W stack (L) R:W EA LCD #xx.8,CCR R:W NEXT LCD #xx.8,EXR R:W 2nd LCD Rs,CCR R:W NEXT LCD Rs,EXR R:W NEXT R:W EA R:W NEXT LCD @ERs,CCR R:W 2nd R:W NEXT R:W EA LCD @ERs,EXR R:W 2nd R:W NEXT R:W EA LCD @(d:16,ERs),CCR R:W 2nd R:W 3rd R:W NEXT LCD @(d:16,ERs),EXR R:W 2nd R:W 3rd R:W NEXT R:W EA LCD @(d:32,ERs),CCR R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT R:W EA LCD @(d:32,ERs),EXR R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT R:W EA LCD @ERs+,CCR R:W 2nd R:W NEXT Internal operation 1 state R:W EA LCD @ERs+,EXR R:W 2nd R:W NEXT Internal operation 1 state R:W EA LCD @aa:16,CCR R:W 2nd R:W 3rd R:W NEXT R:W EA LCD @aa:16,EXR R:W 2nd R:W 3rd R:W NEXT R:W EA LCD @aa:32,CCR R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA LCD @aa:32,EXR R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W EA LDM.L @SP+, (ERn-ERn+1) R:W 2nd R:W:M NEXT Internal operation 1 state R:W:M *3 stack(H) R:W stack(L) *3 LDM.L @SP+, (ERn-ERn+2) R:W 2nd R:W:M NEXT Internal operation 1 state R:W:M *3 stack(H) R:W stack(L) *3 LDM.L @SP+, (ERn-ERn+3) R:W 2nd R:W:M NEXT Internal operation 1 state R:W:M *3 stack(H) R:W stack(L) *3 LDMAC ERs,MACH Cannot be used in this LSI. R:W EA LDMAC ERs,MACL MAC @ERn+,@ERm+ Rev. 0.1, 11/98, page 817 of 975 Table A.6 Instruction Execution Status (5) Instruction 1 MOV.B #xx:8,Rd R:W NEXT 2 3 MOV.B Rs,Rd R:W NEXT MOV.B @ERs,Rd R:W NEXT R:B EA MOV.B @(d:16,ERs),Rd R:W 2nd R:W NEXT MOV.B @(d:32,ERs),Rd R:W 2nd R:W 3rd R:W 4th MOV.B @ERs+,Rd R:W NEXT Internal operation 1 state R:B EA MOV.B @aa:8,Rd R:W NEXT R:B EA MOV.B @aa:16,Rd R:W 2nd R:W NEXT R:B EA MOV.B @aa:32,Rd R:W 2nd R:W 3rd R:W NEXT MOV.B Rs,@ERd R:W NEXT W:B EA MOV.B Rs,@(d:16,ERd) R:W 2nd R:W NEXT MOV.B Rs,@(d:32,ERd) R:W 2nd R:W 3rd R:W 4th MOV.B Rs,@-ERd R:W NEXT Internal operation 1 state W:B EA MOV.B Rs,@aa:8 R:W NEXT W:B EA MOV.B Rs,@aa:16 R:W 2nd R:W NEXT W:B EA MOV.B Rs,@aa:32 R:W 2nd R:W 3rd R:W NEXT MOV.W #xx:16,Rd R:W 2nd R:W NEXT MOV.W Rs,Rd R:W NEXT MOV.W @ERs,Rd R:W NEXT R:W EA MOV.W @(d:16,ERs),Rd R:W 2nd R:W NEXT MOV.W @(d:32,ERs),Rd R:W 2nd R:W 3rd R:W 4th MOV.W @ERs+,Rd R:W NEXT Internal operation 1 state R:W EA MOV.W @aa:16,Rd R:W 2nd R:W NEXT R:W EA MOV.W @aa:32,Rd R:W 2nd R:W 3rd R:W NEXT MOV.W Rs,@ERd R:W NEXT W:W EA MOV.W Rs,@(d:16,ERd) R:W 2nd R:W NEXT MOV.W Rs,@(d:32,ERd) R:W 2nd R:W 3rd R:W 4th MOV.W Rs,@-ERd R:W NEXT Internal operation 1 state W:W EA MOV.W Rs,@aa:16 R:W 2nd R:W NEXT W:W EA MOV.W Rs,@aa:32 R:W 2nd R:W 3rd R:W NEXT MOV.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT MOV.L ERs,ERd R:W NEXT 4 5 R:W NEXT R:B EA 6 7 R:W:M EA R:W EA+2 R:B EA R:B EA W:B EA R:W NEXT W:B EA W:B EA R:W EA R:W NEXT R:W EA R:B EA W:W EA R:W NEXT W:W EA W:W EA MOV.L @ERs,ERd R:W 2nd R:W:M NEXT R:W:M EA R:W EA+2 MOV.L @(d:16,ERs),ERd R:W 2nd R:W:M 3rd R:W NEXT R:W:M EA R:W EA+2 MOV.L @(d:32,ERs),ERd R:W 2nd R:W:M 3rd R:W:M 4th R:W 5th R:W NEXT MOV.L @ERs+,ERd R:W 2nd R:W:M NEXT Internal operation 1 state R:W:M EA R:W EA+2 MOV.L @aa:16,ERd R:W 2nd R:W:M 3rd R:W NEXT R:W:M EA R:W EA+2 MOV.L @aa:32,ERd R:W 2nd R:W:M 3rd R:W 4th R:W NEXT R:W:M EA MOV.L ERs,@ERd R:W 2nd R:W:M NEXT W:W:M EA W:W EA+2 MOV.L ERs,@(d:16,ERd) R:W 2nd R:W:M 3rd R:W NEXT W:W:M EA W:W EA+2 MOV.L ERs,@(d:32,ERd) R:W 2nd R:W:W 3rd R:W:M 4th R:W 5th R:W NEXT MOV.L ERs,@-ERd R:W 2nd R:W:M NEXT Internal operation 1 state W:W:M EA W:W EA+2 Rev. 0.1, 11/98, page 818 of 975 R:W EA+2 W:W:M EA W:W EA+2 8 9 Table A.6 Instruction Execution Status (6) Instruction 1 2 3 4 5 MOV.L ERs,@aa:16 R:W 2nd R:W:M 3rd R:W NEXT W:W:M EA W:W EA+2 MOV.L ERs,@aa:32 R:W 2nd R:W:M 3rd R:W 4th R:W NEXT W:W:M EA MOVFPE @aa:16,Rd Cannot be used in this LSI. 6 7 8 9 W:W EA+2 MOVTPE Rs,@aa:16 MULXS.B Rs,Rd R:W 2nd R:W NEXT Internal operation 11 state MULXS.W Rs,Rd R:W 2nd R:W NEXT Internal operation 19 state MULXU.B Rs,Rd R:W NEXT Internal operation 11 state MULXU.W Rs,Rd R:W NEXT Internal operation 19 state NEG.B Rd R:W NEXT NEG.W Rd R:W NEXT NEG.L ERd R:W NEXT NOP R:W NEXT NOT.B Rd R:W NEXT NOT.W Rd R:W NEXT NOT.L ERd R:W NEXT OR.B #xx:8,Rd R:W NEXT OR.B Rs,Rd R:W NEXT OR.W #xx:16,Rd R:W 2nd OR.W Rs,Rd R:W NEXT OR.L #xx:32,ERd R:W 2nd R:W 3rd OR.L ERs,ERd R:W 2nd R:W NEXT ORC #xx:8,CCR R:W NEXT ORC #xx:8,EXR R:W 2nd R:W NEXT POP.W Rn R:W NEXT Internal operation 1 state R:W EA POP.L ERn R:W 2nd R:W:M NEXT Internal operation 1 state PUSH.W Rn R:W NEXT Internal operation 1 state W:W EA PUSH.L ERn R:W 2nd R:W:M NEXT Internal operation 1 state ROTL.B Rd R:W NEXT ROTL.B #2,Rd R:W NEXT ROTL.W Rd R:W NEXT ROTL.W #2,Rd R:W NEXT ROTL.L ERd R:W NEXT ROTL.L #2, ERd R:W NEXT ROTR.B Rd R:W NEXT ROTR.B #2,Rd R:W NEXT ROTR.W Rd R:W NEXT ROTR.W #2,Rd R:W NEXT ROTR.L ERd R:W NEXT ROTR.L #2,ERd R:W NEXT ROTXL.B Rd R:W NEXT ROTXL.B #2.Rd R:W NEXT ROTXL.W Rd R:W NEXT ROTXL.W #2,Rd R:W NEXT ROTXL.L ERd R:W NEXT ROTXL.L #2,ERd R:W NEXT ROTXR.B Rd R:W NEXT ROTXR.B #2,Rd R:W NEXT ROTXR.W Rd R:W NEXT ROTXR.W #2,Rd R:W NEXT R:W NEXT R:W NEXT R:W:M EA R:W EA+2 W:W:M EA W:W EA+2 Rev. 0.1, 11/98, page 819 of 975 Table A.6 Instruction Execution Status (7) Instruction 1 ROTXR.L ERd R:W NEXT 2 3 ROTXR.L #2.ERd R:W NEXT RTE R:W NEXT R:W stack(EXR) RTS R:W NEXT R:W:M stack(H) SHAL.B Rd R:W NEXT SHAL B #2,Rd R:W NEXT SHAL.W Rd R:W NEXT SHAL.W #2,Rd R:W NEXT SHAL.L ERd R:W NEXT SHAL.L #2,ERd R:W NEXT SHAR.B Rd R:W NEXT SHAR.B #2,Rd R:W NEXT SHAR.W Rd R:W NEXT SHAR.W #2,Rd R:W NEXT SHAR.L ERd R:W NEXT SHAR.L #2,ERd R:W NEXT SHLL.B Rd R:W NEXT SHLL.B #2,Rd R:W NEXT SHLL.W Rd R:W NEXT SHLL.W #2,Rd R:W NEXT SHLL.L ERd R:W NEXT SHLL.L #2,ERd R:W NEXT SHLR.B Rd R:W NEXT SHLR.B #2,Rd R:W NEXT SHLR.W Rd R:W NEXT SHLR.W #2,Rd R:W NEXT SHLR.L ERd R:W NEXT SHLR.L #2,ERd R:W NEXT SLEEP R:W NEXT STC CCR,Rd R:W NEXT STC EXR,Rd R:W NEXT 4 5 6 R:W stack(H) R:W stack(L) Internal operation 1 state R:W R:W stack(L) R:W Internal operation 1 state 7 *4 *4 Internal operation: M STC CCR,@ERd R:W 2nd R:W NEXT W:W EA STC EXR,@ERd R:W 2nd R:W NEXT W:W EA STC CCR,@(d:16,ERd) R:W 2nd R:W 3rd R:W NEXT STC EXR,@(d:16,ERd) R:W 2nd R:W 3rd R:W NEXT W:W EA STC CCR,@(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT W:W EA STC EXR,@(d:32,ERd) R:W 2nd R:W 3rd R:W 4th R:W 5th R:W NEXT W:W EA STC CCR,@-ERd R:W 2nd R:W NEXT Internal operation 1 state W:W EA STC EXR,@-ERd R:W 2nd R:W NEXT Internal operation 1 state W:W EA W:W EA STC CCR,@aa:16 R:W 2nd R:W 3rd R:W NEXT W:W EA STC EXR,@aa:16 R:W 2nd R:W 3rd R:W NEXT W:W EA STC CCR,@aa:32 R:W 2nd R:W 3rd R:W 4th R:W NEXT STC EXR,@aa:32 R:W 2nd R:W 3rd R:W 4th R:W NEXT W:W EA STM.L (ERnERn+1),@-SP R:W 2nd R:W:M NEXT Internal operation 1 state W:W:M stack (H) *3 W:W stack (L) *3 STM.L (ERnERn+2),@-SP R:W 2nd R:W:M NEXT Internal operation 1 state W:W:M stack (H) *3 W:W stack (L) *3 STM.L (ERnERn+3),@-SP R:W 2nd R:W:M NEXT Internal operation 1 state W:W:M stack (H) *3 W:W stack (L) *3 Rev. 0.1, 11/98, page 820 of 975 W:W EA 8 9 Table A.6 Instruction Execution Status (8) Instruction 1 STMAC MACH,ERd Cannot be used in this LSI. 2 3 4 5 6 7 8 9 W:W stack(EXR) R:W:M VEC R:W VEC+2 Internal operation 1 state R:W W:W stack(EXR) R:W:M VEC R:W VEC+2 Internal operation 1 state R:W STMAC MACL,ERd SUB.B Rs,Rd R:W NEXT SUB.W #xx:16,Rd R:W 2nd SUB.W Rs,Rd R:W NEXT SUB.L #xx:32,ERd R:W 2nd SUB.L ERs,ERd R:W NEXT SUB #1/2/4,ERd R:W NEXT SUBX #xx:8,Rd R:W NEXT SUBX Rs,Rd R:W NEXT R:W NEXT R:W 3nd R:W NEXT TAS @ERd R:W 2nd R:W NEXT R:B:M EA W:B EA TRAPA #x:2 R:W NEXT Internal operation 1 state W:W stack(L) W:W stack(H) XOR.B #xx:8,Rd R:W NEXT XOR.B Rs,Rd R:W NEXT XOR.W #xx:16,Rd R:W 2nd XOR.W Rs,Rd R:W NEXT XOR.L #xx:32,ERd R:W 2nd R:W 3rd XOR.L ERs,ERd R:W 2nd R:W NEXT XORC #xx:8,CCR R:W NEXT R:W NEXT R:W NEXT XORC #xx:8,EXR R:W 2nd R:W NEXT Reset exception handling R:W:M VEC R:W VEC+2 Internal operation 1 state R:W Interrupt exception handling R:W Internal operation 1 state W:W stack(L) W:W stack(H) *6 *7 *5 *7 Notes: 1. EAs is the contents of ER5, and EAd is the contents of ER6. 2. 1 is added to EAs and EAd after execution. n is the initial value of R4L or R4. When 0 is set to n, R4L or R4 is not executed. 3. Repeated twice for 2-unit retract/return, three times for 3-unit retract/return, and four times for 4-retract/return. 4. Head address after return. 5. Start address of the program. 6. Pre-fetch address obtained by adding 2 to the PC to be retracted. When returning from sleep mode, standby mode or watch mode, internal operation is executed instead of read operation. 7. Head address of the interrupt process routine. Rev. 0.1, 11/98, page 821 of 975 A.6 Change of Condition Codes This section explains change of condition codes after instruction execution of the CPU. Legend of the following tables is as follows. m = 31: Longword size m = 15: Word size m = 7: Byte size Si: Bit i of source operand Di: Bit i of destination operand Ri: Bit i of result Dn: Specified bit of destination operand -: No affection : Changes depending on execution result 0: Always cleared to 0 1: Always set to 1 *: Value undetermined Z': Z flag before execution C': C flag before execution Rev. 0.1, 11/98, page 822 of 975 Table A.7 Change of Condition Code (1) Instruction H N Z V C ADD ADDS H=Sm-4Dm-4+Dm-45P+Sm-45P N=Rm Z=5P5P 5 V=SmDm5P+6P'PRm C=SmDm+Dm5P+Sm5P - - - - - ADDX AND Definition H=Sm-4Dm-4+Dm-45P+Sm-45P N=Rm Z=Z'5P 5 V=SmDm5P+6P'PRm C=SmDm+Dm5P+Sm5P - 0 - ANDC N=Rm Z=5P5P 5 Value in the bit corresponding to execution result is stored. No flag change when EXR. BAND - - - - Bcc - - - - - BCLR - - - - - BIAND - - - - C=C''Q BILD - - - - C='Q BIOR - - - - C=C'+'Q BIST - - - - BIXOR - - - - C=C'Dn+& 'Q BLD - - - - C=Dn BNOT - - - - BOR - - - - BSET - - - - - BSR - - - - - BST - - - - - BTST - - - - BXOR - - CLRMAC Cannot be used in this LSI. - - C=C'Dn - - C=C'+Dn Z='Q C=C''Q+& Dn Rev. 0.1, 11/98, page 823 of 975 Table A.7 Change of Condition Code (2) Instruction H N Z V C Definition H=Sm-4'P+'PRm-4+Sm-4Rm-4 N=Rm Z=5P5P 5 V=6PDm5P+Sm'PRm C=Sm'P+'PRm+SmRm CMP DAA * * N=Rm Z=5P5P 5 C: Decimal addition carry DAS * * N=Rm Z=5P5P 5 C: Decimal subtraction borrow DEC - - N=Rm Z=5P5P V=Dm5P 5 DIVXS - - - N=Sm'P+6PDm Z=6P6P 6 DIVXU - - - N=Sm Z=6P6P 6 N=Rm Z=5P5P 5 - Z=5P5P 5 - N=Rm Z=5P5P V='P5P 5 EEPMOV - EXTS - EXTU - INC - - - 0 - - 0 - 0 JMP - - - - - JSR - - - - - LDC Value in the bit corresponding to execution result is stored. No flag change when EXR. LDM - - - - LDMAC Cannot be used in this LSI. - MAC MOV - Rev. 0.1, 11/98, page 824 of 975 0 - N=Rm Z=5P5P 5 Table A.7 Change of Condition Code (3) Instruction H MOVFPE N Z V C Definition - N=R2m Z=5P5P Cannot be used in this LSI. MOVTPE MULXS MULXU - - - - - - H=Dm-4+Rm-4 N=Rm Z=5P5P 5 V=DmRm C=Dm+Rm NOP - NOT - - - - - - 0 - 0 - ORC POP 5 - NEG OR N=Rm Z=5P5P 5 N=Rm Z=5P5P 5 Value in the bit corresponding to execution result is stored. No flag change when EXR. - 0 - - N=Rm Z=5P5P 5 N=Rm Z=5P5P 5 PUSH - 0 ROTL - 0 N=Rm Z=5P5P 5 C=Dm(In case of 1 bit), C=Dm-1(In case of 2 bits) ROTR - 0 N=Rm Z=5P5P 5 C=D0(In case of 1 bit), C=D-1(In case of 2 bits) ROTXL - 0 N=Rm Z=5P5P 5 C=Dm(In case of 1 bit), C=Dm-1(In case of 2 bits) ROTXR - 0 N=Rm Z=5P5P 5 C=D0(In case of 1 bit), C=D1(In case of 2 bits) RTE RTS Value in the bit corresponding to execution result is stored. - - - - - Rev. 0.1, 11/98, page 825 of 975 Table A.7 Change of Condition Code (4) Instruction H SHAL N Z V C - Definition N=Rm Z=5P5P 5 V=DmDm-1+'P'P(In case of 1 bit) V=DmDm-1Dm-2'P'P'P (In case of 2bits) C=Dm(In case of 1 bit), C=Dm-1(In case of 2 bits) SHAR - 0 N=Rm Z=5P5P 5 C=D0(In case of 1 bit), C=D1(In case of 2 bits) SHLL - 0 N=Rm Z=5P5P 5 C=Dm(In case of 1 bit), C=Dm-1(In case of 2 bits) SHLR - 0 0 N=Rm Z=5P5P 5 C=D0(In case of 1 bit), C=D1(In case of 2 bits) SLEEP - - - - - STC - - - - - STM - - - - - STMAC Cannot be used in this LSI. H=Sm-4'P+'PRm-4+Sm-4Rm-4 N=Rm Z=5P5P 5 V=6PDm5P+Sm'PRm C=Sm'P+'PRm+SmRm SUB SUBS - - - - - H=Sm-4'P+'PRm-4+Sm-4Rm-4 N=Rm Z=Z'5P 5 V=6PDm5P+Sm'PRm C=Sm'P+'PRm+SmRm SUBX TAS - TRAPA - XOR - 0 - - XORC Rev. 0.1, 11/98, page 826 of 975 - - - 0 - N=Dm Z='P'P ' N=Rm Z=5P5P 5 Value in the bit corresponding to execution result is stored. No flag change when EXR. Appendix B Internal I/O Registers B.1 Addresses Register Bus Module Address* Name R/W Access Width 7 6 5 4 3 2 1 0 Name H'D000 DGKp W 16 16 DGKp15 DGKp14 DGKp13 DGKp12 DGKp11 DGKp10 DGKp9 DGKp8 Drum digital filter DGKp7 DGKp6 DGKp5 DGKp4 DGKp3 DGKp2 DGKp1 DGKp0 DGKs W 16 16 DGKs15 DGKs14 DGKs13 DGKs12 DGKs11 DGKs10 DGKs9 DGKs8 DGKs7 DGKs6 DGKs5 DGKs4 DGKs3 DGKs2 DGKs1 DGKs0 DAp W 16 16 DAp15 DAp14 DAp13 DAp12 DAp11 DAp10 DAp9 DAp8 DAp7 DAp6 DAp5 DAp4 DAp3 DAp2 DAp1 DAp0 DBp15 DBp14 DBp13 DBp12 DBp11 DBp10 DBp9 DBp8 DBp7 DBp6 DBp5 DBp4 DBp3 DBp2 DBp1 DBp0 DAs15 DAs14 DAs13 DAs12 DAs11 DAs10 DAs9 DAs8 DAs7 DAs6 DAs5 DAs4 DAs3 DAs2 DAs1 DAs0 DBs15 DBs14 DBs13 DBs12 DBs11 DBs10 DBs9 DBs8 DBs7 DBs6 DBs5 DBs4 DBs3 DBs2 DBs1 DBs0 DOfp15 DOfp14 DOfp13 DOfp12 DOfp11 DOfp10 DOfp9 DOfp8 DOfp7 DOfp6 DOfp5 DOfp4 DOfp3 DOfp2 DOfp1 DOfp0 DOfs15 DOfs14 DOfs13 DOfs12 DOfs11 DOfs10 DOfs9 DOfs8 DOfs7 DOfs6 DOfs5 DOfs4 DOfs3 DOfs2 DOfs1 DOfs0 CGKp15 CGKp14 CGKp13 CGKp12 CGKp11 CGKp10 CGKp9 CGKp8 CGKp7 CGKp6 CGKp5 CGKp4 CGKp3 CGKp2 CGKp1 CGKp0 CGKs15 CGKs14 CGKs13 CGKs12 CGKs11 CGKs10 CGKs9 CGKs8 CGKs7 CGKs6 CGKs5 CGKs4 CGKs3 CGKs2 CGKs1 CGKs0 CAp15 CAp14 CAp13 CAp12 CAp11 CAp10 CAp9 CAp8 CAp7 CAp6 CAp5 CAp4 CAp3 CAp2 CAp1 CAp0 CBp15 CBp14 CBp13 CBp12 CBp11 CBp10 CBp9 CBp8 CBp7 CBp6 CBp5 CBp4 CBp3 CBp2 CBp1 CBp0 CAs15 CAs14 CAs13 CAs12 CAs11 CAs10 CAs9 CAs8 CAs7 CAs6 CAs5 CAs4 CAs3 CAs2 CAs1 CAs0 CBs15 CBs14 CBs13 CBs12 CBs11 CBs10 CBs9 CBs8 CBs7 CBs6 CBs5 CBs4 CBs3 CBs2 CBs1 CBs0 COfp15 COfp14 COfp13 COfp12 COfp11 COfp10 COfp9 COfp8 COfp7 COfp6 COfp5 COfp4 COfp3 COfp2 COfp1 COfp0 COfs15 COfs14 COfs13 COfs12 COfs11 COfs10 COfs9 COfs8 COfs7 COfs6 COfs5 COfs4 COfs3 COfs2 COfs1 COfs0 - - - - DZs11 DZs10 DZs9 DZs8 DZs7 DZs6 DZs5 DZs4 DZs3 DZs2 DZs1 DZs0 - - - - DZp11 DZp10 DZp9 DZp8 DZp7 DZp6 DZp5 DZp4 DZp3 DZp2 DZp1 DZp0 - - - CZs11 CZs10 CZs9 CZs8 H'D001 H'D002 H'D003 H'D004 H'D005 H'D006 DBp W 16 16 DAs W 16 16 DBs W 16 16 DOfp W 16 16 DOfs W 16 16 H'D007 H'D008 H'D009 H'D00A H'D00B H'D00C H'D00D H'D00E H'D00F H'D010 CGKp W 16 16 CGKs W 16 16 CAp W 16 16 H'D011 H'D012 H'D013 H'D014 H'D015 H'D016 CBp W 16 16 CAs W 16 16 CBs W 16 16 COfp W 16 16 COfs W 16 16 H'D017 H'D018 H'D019 H'D01A H'D01B H'D01C H'D01D H'D01E H'D01F H'D020 DZs W 16 16 H'D021 H'D022 DZp W 16 16 H'D023 H'D024 CZs W 16 16 - CZs7 CZs6 CZs5 CZs4 CZs3 CZs2 CZs1 CZs0 CZp W 16 16 - - - - CZp11 CZp10 CZp9 CZp8 CZp7 CZp6 CZp5 CZp4 CZp3 CZp2 CZp1 CZp0 - DROV DPHA DZPON DZSON DSG2 DSG1 DSC0 - CROV CPHA CZPON CZSON CSG2 CSG1 CSG0 - - PTON CP/'3 CFEPS DFEPS CFESS DFESS H'D025 H'D026 H'D027 H'D028 DFIC R/W 8 H'D029 CFIC R/W 8 H'D02A DFUCR R/W 8 16 16 Capstan digital filter Digital filter Note: * Lower 16 bits of the address. Rev. 0.1, 11/98, page 827 of 975 Address* Register Name R/W Access Bus Width H'D030 DFPR W 16 16 H'D031 H'D032 DFER R/W 16 16 H'D033 H'D034 DFRUDR W 16 16 DFRLDR W 16 16 H'D035 H'D036 7 6 5 4 3 2 1 0 DFPR15 DFPR14 DFPR13 DFPR12 DFPR11 DFPR10 DFPR9 DFPR8 DFPR7 DFPR6 DFPR5 DFPR4 DFPR3 DFPR2 DFPR1 DFPR0 DFER15 DFER14 DFER13 DFER12 DFER11 DFER10 DFER9 DFER8 DFER7 DFER6 DFER5 DFER4 DFER3 DFER2 DFER1 DFER0 DFRUDR1 5 DFRUDR1 DFRUDR1 DFRUDR1 DFRUDR1 DFRUDR1 DFRUDR9 DFRUDR8 4 3 2 1 0 DFRLDR1 5 DFRLDR1 4 DFRLDR1 3 DFRLDR1 2 DFRLDR1 1 DFRLDR1 0 DFRLDR9 DFRLDR8 DFRLDR7 DFRLDR6 DFRLDR5 DFRLDR4 DFRLDR3 DFRLDR2 DFRLDR1 DFRLDR0 DFRCS1 DFRCS0 H'D038 DFVCR R/W 8 16 DFCS1 DFCS0 DFOVF DFRFON DF-R/UNR OPCNT H'D039 DPGCR R/W 8 16 DPCS1 DPCS0 DPOVF N/V HSWES - - - H'D03A DPPR2 W 16 16 DPPR15 DPPR14 DPPR13 DPPR12 DPPR11 DPPR10 DPPR9 DPPR8 DPPR7 DPPR6 DPPR5 DPPR4 DPPR3 DPPR2 DPPR1 DPPR0 H'D03C DPPR1 W 8 16 - - - - DPPR19 DPPR18 DPPR17 DPPR16 H'D03D DPER1 W 8 16 - - - - DPER19 DPER18 DPER17 DPER16 H'D03E DPER2 W 16 16 DPER15 DPER14 DPER13 DPER12 DPER11 DPER10 DPER9 DPER8 DPER7 DPER6 DPER5 DPER4 DPER3 DPER2 DPER1 DPER0 CFPR15 CFPR14 CFPR13 CFPR12 CFPR11 CFPR10 CFPR9 CFPR8 H'D03B H'D03F CFPR W 16 16 CFER W 16 16 CFRUDR W 16 16 CFRLDR W 16 16 CFRLDR7 H'D058 CFVCR R/W 8 16 CFCS1 H'D059 CPGCR R/W 8 16 CPCS1 CPCS0 H'D05A CPPR2 W 16 16 H'D051 H'D052 H'D053 H'D054 H'D055 H'D056 CFPR7 CFPR6 CFPR5 CFPR4 CFPR3 CFPR2 CFPR1 CFPR0 CFER15 CFER14 CFER13 CFER12 CFER11 CFER10 CFER9 CFER8 CFER7 CFER6 CFER5 CFER4 CFER3 CFER2 CFER1 CFER0 CFRUDR1 5 CFRUDR1 CFRUDR1 CFRUDR1 CFRUDR1 CFRUDR1 CFRUDR9 CFRUDR8 4 3 2 1 0 H'D05B CFRLDR1 5 CFRLDR1 4 CFRLDR1 3 CFRLDR1 2 CFRLDR1 1 CFRLDR1 0 CFRLDR9 CFRLDR8 CFRLDR6 CFRLDR5 CFRLDR4 CFRLDR3 CFRLDR2 CFRLDR1 CFRLDR0 CFCS0 CFOVF CFRFON CF-R/UNR CPCNT CPOVF CR/RF SELCFG2 CFRCS1 CFRCS0 - - - CPH15 CPH14 CPH13 CPH12 CPH11 CPH10 CPH9 CPH8 CPH7 CPH6 CPH5 CPH4 CPH3 CPH2 CPH1 CPH0 H'D05C CPPR1 W 8 16 - - - - CPH19 CPH18 CPH17 CPH16 H'D05D CPER1 W 8 16 - - - - CPER19 CPER18 CPER17 CPER16 H'D05E CPER2 W 16 16 CPER15 CPER14 CPER13 CPER12 CPER11 CPER10 CPER9 CPER7 CPER6 CPER5 CPER4 CPER3 CPER2 CPER1 CPER0 H'D060 HSM1 R/W 8 16 FLB FLA EMPB EMPA OVWB OVWA CLRB CLRA H'D061 HSM2 R/W 8 FRT FRGR2OF LOP F EDG ISEL SOFG OFG VFF/NFF H'D05F CPER8 H'D062 HSLP W 8 16 LOB3 LOB2 LOB1 LOB0 LOA3 LOA2 LOA1 LOA0 H'D064 FPDRA W 16 16 - ADTRGA STRIGA NallowFFA VFFA AFFA VpulseA MlevelA PPGA7 PPGA6 PPGA5 PPGA4 PPGA3 PPGA2 PPGA1 PPGA0 FTPRA* W 16 16 FTPRA15 FTRPA14 FTRPA13 FTRPA12 FTRPA11 FTRPA10 FTRPA9 FTRPA8 FTCTR13 FTCTR12 FTCTR11 FTCTR10 FTCTR9 FTCTR8 H'D065 H'D066 FTCTR* H'D067 FTPRA* W 16 H'D067 FTCTR* R 16 H'D068 FPDRB W 16 16 R 16 FTCTR15 FTPRB W 16 16 H'D06C DFCTR* W 8 16 H'D06C DFCRB R 8 H'D06D DFCRB W 8 H'D06E CHCR W 8 H'D06F ADDVR R/W 8 16 H'D069 H'D06A Capstan error detector CFRUDR7 CFRUDR6 CFRUDR5 CFRUDR4 CFRUDR3 CFRUDR2 CFRUDR1 CFRUDR0 H'D057 H'D066 Drum error detector DFRUDR7 DFRUDR6 DFRUDR5 DFRUDR4 DFRUDR3 DFRUDR2 DFRUDR1 DFRUDR0 H'D037 H'D050 Module Name H'D06B FTCTR14 FTPRA7 FTPRA6 FTPRA5 FTPRA4 FTPRA3 FTPRA2 FTPRA1 FTCTR7 FTCTR6 FTCTR5 FTCTR4 FTCTR3 FTCTR2 FTCTR1 FTCTR0 - ADTRGB STRIGB NallowFFB VFFB AFFB VpulseB MlevelB PPGB7 PPGB6 PPGB5 PPGB4 PPGB3 PPGB2 PPGB1 PPGB0 FTPRB15 FTPRB14 FTPRB13 FTPRB12 FTPRB11 FTPRB10 FTPRB9 FTPRB8 FPTRB0 HSW timing generator * Assign to the same address. FTPRA0 FTPRB7 FTPRB6 FTPRB5 FTPRB4 FPTRB3 FPTRB2 FPTRB1 ISEL2 CCLR CKSL DFCRA4 DFCRA3 DFCRA2 DFCRA1 DFCRA0 - - - DFCTR4 DFCTR3 DFCTR2 DFCTR1 DFCTR0 16 - - - DFCRB4 DFCRB3 DFCRB2 DFCRB1 DFCRB0 16 V/N HSWPOL CRH HAH SIG3 SIG2 SIG1 SIG0 4-head specialeffects playback - - - HMSK HIZ CUT VPON POL Additional V Note: * Lower 16 bits of the address. Rev. 0.1, 11/98, page 828 of 975 Register Bus Module Address* Name R/W Access Width 7 6 5 4 3 2 1 0 Name H'D070 XDR W 16 16 - - - - XR11 XR10 XR9 XR8 X-value, TRK-value XR7 XR6 XR5 XR4 XR3 XR2 XR1 XR0 TRDR W 16 16 - - - - TRD11 TRD10 TRD9 TRD8 TRD7 TRD6 TRD5 TRD4 TRD3 TRD2 TRD1 TRD0 XCS DVRER1 DVREF0 H'D071 H'D072 H'D073 H'D074 XTCR R/W 8 16 - CAPRF AT/08 TRK/; EXC/REF H'D078 DPWDR R/W 16 16 - - - - DPWDR11 DPWDR10 DPWDR9 DPWDR7 DPWDR6 DPWDR5 DPWDR4 DPWDR3 DPWDR2 DPWDR1 DPWDR0 H'D07A DPWCR W 8 16 DPOL DDC DHIZ DH/L DSFDF DCK2 DCK1 DCK0 H'D07B CPWCR W 8 CPOL CDC CHIZ CH/L CSF/DF CCK2 CCK1 CCK0 H'D07C CPWDR R/W 16 H'D079 16 H'D07D H'D080 CTCR W 8 H'D081 CTLM R/W 8 H'D082 RCDR1 W 16 16 16 H'D083 H'D084 RCDR2 W 16 16 H'D085 H'D086 RCDR3 W 16 16 H'D087 H'D088 RCDR4 W 16 16 H'D089 H'D08A RCDR5 W 16 16 H'D08B H'D08C DI/O R/W 8 H'D08D BTPR R/W 8 16 H'D090 RFD W 16 16 CRF W 16 16 RFC R/W 16 16 H'D091 H'D092 H'D093 H'D094 H'D095 H'D096 RFM R/W 8 H'D097 RFM2 R/W 8 H'D098 CTVC R/W 8 H'D099 CTLR W 8 H'D09A CDVC R/W 8 H'D09B CDIVR1 W 8 16 16 16 16 DPWDR8 - - - - CPWDR11 CPWDR10 CPWDR9 CPWDR8 CPWDR7 CPWDR6 CPWDR5 CPWDR4 CPWDR3 CPWDR2 CPWDR1 CPWDR0 NT/PAL FLSC FLSB FSLA CCS LCTL UNCTL SLWM ASM REC/3% FW/RV MD4 MD3 MD3 MD1 MD0 - - - - CMT1B CMT1A CMT19 CMT18 CMT17 CMT16 CMT15 CMT14 CMT13 CMT12 CMT11 CMT10 - - - - CMT2B CMT2A CMT29 CMT28 CMT27 CMT26 CMT25 CMT24 CMT23 CMT22 CMT21 CMT20 - - - - CMT3B CMT3A CMT39 CMT38 CMT37 CMT36 CMT35 CMT34 CMT33 CMT32 CMT31 CMT30 - - - - CMT4B CMT4A CMT49 CMT48 CMT47 CMT46 CMT45 CMT44 CMT43 CMT42 CMT41 CMT40 - - - - CMT5B CMT5A CMT59 CMT58 CMT57 CMT56 CMT55 CMT54 CMT53 CMT52 CMT51 CMT50 VCTR2 VCTR1 VCTR0 - BPON BPS BPF DI/O LSP7 LSP6 LSP5 LSP4 LSP3 LSP2 LSP1 LSP0 REF15 REF14 REF13 REF12 REF11 REF10 REF9 REF8 REF7 REF6 REF5 REF4 REF3 REF2 REF1 REF0 CRF15 CRF14 CRF13 CRF12 CRF11 CRF10 CRF9 CRF8 CRF7 CRF6 CRF5 CRF4 CRF3 CRF2 CRF1 CRF0 RFC15 RFC14 RFC13 RFC12 RFC11 RFC10 RFC9 RFC8 RFC7 RFC6 RFC5 RFC4 RFC3 RFC2 RFC1 RFC0 RCF VNA CVS REX CRD OD/EV VST VEG - - - - - - - FDS CEX CEG - - - CFG HSW CTL CTL7 CTL6 CTL5 CTL4 CTL3 CTL2 CTL1 CTL0 CMK CMN DVTRG CRF CPS1 CPS0 - CDV16 CDV15 CDV14 CDV13 CDV12 CDV11 CDV10 - CDV26 CDV25 CDV24 CDV23 CDV22 CDV21 CDV20 - - CPM5 CPM4 CPM3 CPM2 CPM1 CPM0 - - - - DRF MCGain H'D09C CDIVR2 W 8 H'D09D CTMR W 8 H'D09E FGCR W 8 16 - - - H'D0A0 SPMR R/W 8 8 CTLSTOP - CFGCOMP EXCELON DPGSW COMP H.Amp.SW C.Rot H'D0A1 SPCR R/W 8 8 - - - SPCR4 SPCR3 SPCR2 SPCR1 SPCR0 H'D0A2 SPDR R/W 8 8 - - - SPDR4 SPDR3 SPDR2 SPDR1 SPDR0 H'D0A3 SVMCR R/W 8 8 - - SVMCR5 SVMCR4 SVMCR3 SVMCR2 SVMCR1 SVMCR0 H'D0A4 CTLGR R/W 8 8 - - - CTLFB CTLGR3 CTLGR2 CTLGR1 CTLGR0 Drum 12-bit PWM Capstan 12bit PWM CTL circuit Reference signal generator Frequency divider Servo port control Note: * Lower 16 bits of the address. Rev. 0.1, 11/98, page 829 of 975 Register Bus Module Address* Name R/W Access Width 7 6 5 4 3 2 1 0 Name H'D0B0 VTR W 8 16 - - VTR5 VTR4 VTR3 VTR2 VTR1 VTR0 Sync detector H'D0B1 HTR W 8 16 - - - - HTR3 HTR2 HTR1 HTR0 H'D0B2 HRTR W 8 16 HRTR7 HRTR6 HRTR5 HRTR4 HRTR3 HRTR2 HRTR1 HRTR0 H'D0B3 HPWR W 8 16 - - - - HPWR3 HPWR2 HPWR1 HPWR0 H'D0B4 NWR W 8 16 - - NWR5 NWR4 NWR3 NWR2 NWR1 NWR0 H'D0B5 NDR W 8 16 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 H'D0B6 SYNCR R/W 8 16 - - - - NID/VD NOIS FLD SYCT H'D0B8 SIENR1 R/W 8 16 IEDR3 IEDR2 IEDR1 IECAP3 IECAP2 IECAP1 IEHSW2 IEHSW1 IESTL H'D0B9 SIENR2 R/W 8 16 - - - - - - IESNC H'D0BA SIRQR1 R/W 8 16 IRRDRM3 IRRDRM2 IRRDRM1 IRRCAP3 IRRCAP2 IRRCAP1 IRRHSW2 IRRHSW1 H'D0BB SIRQR2 R/W 8 16 - - - - - - IRRSNC IRRCTL H'D0C0 32 byte Data Buffer R/W 8 8 H'D0C1 R/W 8 8 H'D0C2 R/W 8 8 H'D0C3 R/W 8 8 H'D0C4 R/W 8 8 H'D0C5 R/W 8 8 H'D0C6 R/W 8 8 H'D0C7 R/W 8 8 H'D0C8 R/W 8 8 H'D0C9 R/W 8 8 H'D0CA R/W 8 8 H'D0CB R/W 8 8 H'D0CC R/W 8 8 H'D0CD R/W 8 8 H'D0CE R/W 8 8 H'D0CF R/W 8 8 R/W 8 8 H'D0D1 R/W 8 8 H'D0D2 R/W 8 8 H'D0D3 R/W 8 8 H'D0D4 R/W 8 8 H'D0D5 R/W 8 8 H'D0D6 R/W 8 8 H'D0D7 R/W 8 8 H'D0D8 R/W 8 8 H'D0D9 R/W 8 8 H'D0DA R/W 8 8 H'D0D0 32 byte Data Buffer H'D0DB R/W 8 8 H'D0DC R/W 8 8 H'D0DD R/W 8 8 H'D0DE R/W 8 8 H'D0DF R/W 8 8 Servo interrupt control 32-byte buffer SCI2 32-byte buffer SCI2 H'D0E0 STAR R/W 8 8 - - - STA4 STA3 STA2 STA1 STA0 H'D0E1 EDAR R/W 8 8 - - - EDA4 EDA3 EDA2 EDA1 EDA0 H'D0E2 SCR2 R/W 8 8 TEIE ABTIE - GAP1 GAP0 CKS2 CKS1 CKS0 H'D0E3 SCSR2 R/W 8 8 TEI - - SOL ORER WT ABT STF Note: * Lower 16 bits of the address. Rev. 0.1, 11/98, page 830 of 975 32-byte buffer SCI2 Register Bus Module Address* Name R/W Access Width 7 6 5 4 3 2 1 0 Name H'D100 TIER R/W 8 16 ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE ICSA Timer X1 * OCRA and OCRB addresses are the same. Switched by OCSR bit in IOCR. H'D101 TCSRX R/W 8 16 ICFA ICFB ICFC ICFD OCFA OCFB OVF CCLRA H'D102 FRCH R/W 8/16 16 FRCH7 FRCH6 FRCH5 FRCH4 FRCH3 FRCH2 FRCH1 FRCH0 H'D103 FRCL FRCL7 FRCL6 FRCL5 FRCL4 FRCL3 FRCL2 FRCL1 FRCL0 H'D104 OXRAH* OCRAH7 OCRAH6 OCRAH5 OCRAH4 OCRAH3 OCRAH2 OCRAH1 OCRAH0 H'D105 OCRAL* OCRAL7 OCRAL6 OCRAL5 OCRAL4 OCRAL3 OCRAL2 OCRAL1 OCRAL0 H'D104 OCRBH* OCRBH7 CORBH6 OCRBH5 OCRBH4 OCRBH3 OCRBH2 OCRBH1 OCRBH0 H'D105 OCRBL* OCRBL7 OCRBL6 OCRBL5 CORBL4 CORBL3 CORBL2 CORBL1 CORBL0 H'D106 TCRX R/W 8 16 IEDGA IEDGB IEDGC IEDGD BUFEA FUFEB CKS1 CKS0 H'D107 TOCR R/W 8 16 ICSB ICSC ICSD OCRS OEA OEB OLVLA OLVLB H'D108 ICRAH R 8/16 16 ICRAH7 ICRAH6 ICRAH5 ICRAH4 ICRAH3 ICRAH2 ICRAH1 ICRAH0 H'D109 ICRAL ICRAL7 ICRAL6 ICRAL5 ICRAL4 ICRAL3 ICRAL2 ICRAL1 ICRAL0 H'D10A ICRBH ICRBH6 ICRBH5 ICRBH4 ICRBH3 ICRBH2 ICRBH1 ICRBH0 H'D10B ICRBL H'D10C ICRCH H'D10D ICRCL H'D10E ICRDH R/W 8/16 16 R/W 8/16 16 R 8/16 16 ICRBH7 ICRBL7 ICRBL6 ICRBL5 ICRBL4 ICRBL3 ICRBL2 ICRBL1 ICRBL0 R 8/16 16 ICRCH7 ICRCH6 ICRCH5 ICRCH4 ICRCH3 ICRCH2 ICRCH1 ICRCH0 ICRCL7 ICRCL6 ICRCL5 ICRCL4 ICRCL3 ICRCL2 ICRCL1 ICRCL0 R 8/16 16 ICRDH7 ICRDH6 ICRDH5 ICRDH4 ICRDH3 ICRDH2 ICRDH1 ICRDH0 H'D10F ICRDL ICRDL7 ICRDL6 ICRDL5 ICRDL4 ICRDL3 ICRDL2 ICRDL1 ICRDL0 H'D110 TMB R/W 8 8 TMB17 TMBIF TMPIE - - TMP12 TMP11 TCB10 H'D111 TCB R 8 8 TCB17 TCB16 TCB15 TCB14 TCB13 TCB12 TCB11 TCB10 TLB10 H'D111 TLB W 8 8 TLB17 TLB16 TLB15 TLB14 TLB13 TLB12 TLB11 H'D112 LMR R/W 8 8 LMIF LMIE - - LMR3 LMR2 LMR1 LMR0 H'D113 LTC R 8 8 LTC7 LTC6 LTC5 LTC4 LTC3 LTC2 LTC1 LTC0 H'D113 RCR W 8 8 RCR7 RCR6 RCR5 RCR4 RCR3 RCR2 RCR1 RCR0 H'D118 TMRM1 R/W 8 8 CLR2 AC/BR RLD RLCK PS21 PC20 RLD/CAP CPS H'D119 TMRM2 R/W 8 8 LAT RS11 PS10 PS31 PS30 CP/SLM CAPF SLW H'D11A TMRCP1 R 8 8 TMRC17 TMRC16 TMRC15 TMRC14 TMRC13 TMRC12 TMRC11 TMRC10 H'D11B TMRCP2 R 8 8 TMRC27 TMRC26 TMRC25 TMRC24 TMRC23 TMRC22 TMRC21 TMRC20 H'D11C TMRL1 W 8 8 TMR17 TMR16 TMR15 TMR14 TMR13 TMR12 TMR11 TMR10 H'D11D TMRL2 W 8 8 TMR27 TMR26 TMR25 TMR24 TMR23 TMR22 TMR21 TMR20 H'D11E TMRL3 W 8 8 TMR37 TMR36 TMR35 TMR34 TMR33 TMR32 TMR31 TMR30 H'D11F TMRCS R/W 8 8 TMRI3E TMRI2E TMRI1E TMRI3 TMRI2 TMRI1 - - H'D120 PWDRL W 8 8 PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 H'D121 PWDRU W 8 8 - - PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0 H'D122 PWCR R/W 8 8 - - - - - - - PWMCR0 H'D126 PWR0 W 8 8 PW07 PW06 PW05 PW04 PW03 PW02 PW01 PW00 H'D127 PWR1 W 8 8 PW17 PW16 PW15 PW14 PW13 PW12 PW11 PW10 H'D128 PWR2 W 8 8 PW27 PW26 PW25 PW24 PW23 PW22 PW21 PW20 H'D129 PWR3 W 8 8 PW37 PW36 PW35 PW34 PW33 PW32 PW31 PW30 H'D12A PW8CR R/W 8 8 - - - - PWC3 PWC2 PWC1 PWC0 H'D12C ICR1 R 8 8 ICR17 ICR16 ICR15 ICR14 ICR13 ICR12 ICR11 CIR10 H'D12D PCSR R/W 8 8 ICIF ICIE ICEG NCon/off - DCS2 DCS1 DCS0 Timer B Timer L Timer R 14-bit PWM 8-bit PWM PSU Note: * Lower 16 bits of the address. Rev. 0.1, 11/98, page 831 of 975 Register Bus Module Address* Name R/W Access Width 7 6 5 4 3 2 1 0 Name H'D130 ADRH R 16 8 ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 A/D H'D131 ADRL ADR1 ADR0 H'D132 AHRH R 16 8 AHR9 AHR8 AHR7 AHR6 AHR5 AHR4 AHR3 AHR2 H'D133 AHRL AHR1 AHR0 H'D134 ADCR R/W 8 8 CK HCH1 HCH0 SCH3 SCH2 SCH1 SCH0 H'D135 ADCSR R/W 8 8 SEND HEND ADIE SST HST BUSY SCNL H'D136 ADTSR R/W 8 8 TRGS1 TRGS0 H'D138 TLK W 8/16 16 TLR27 TLR26 TLR25 TLR24 TLR23 TLR22 TLR21 TLR20 H'D138 TCK R 8/16 16 TLR17 TLR16 TLR15 TLR14 TLR13 TLR12 TLR11 TLR10 H'D139 TLJ W 8/16 16 TDR27 TDR26 TDR25 TDR24 TDR23 TDR22 TDR21 TDR20 H'D139 TCJ R 8/16 16 TDR17 TDR16 TDR15 TDR14 TDR13 TDR12 TDR11 TDR10 H'D13A TMJ R/W 8/16 16 PS11 PS10 ST 8/16 PS21 PS20 TGL T/R H'D13B TMJC R/W 8/16 16 BUZZ1 BUZZ0 MON1 MON0 TMJ2IE TMJ1IE H'D13C TMJS R/W 8/16 16 TMJ2I TMJ1I H'D148 SMR1 R/W 8 8 C/A CHR PE O/( STOP MP CKS1 CKS0 H'D149 BRR1 R/W 8 8 H'D14A SCR1 R/W 8 8 TEI RIE TE RE MPIE TEIE CKE1 CKE0 H'D14B TDR1 R/W 8 8 H'D14C SSR1 R/W 8 8 TDRE RDRF ORER FER PER TEMD MPB MPBT H'D14D RDR1 R 8 8 H'D14E SCMR1 R/W 8 8 SDIR SINV SMIF H'D158 ICCR R/W 8 8 ICE IEIC MST TRS ACKE BBSY IRIC SCP H'D159 ICSR R/W 8 8 ESTP STOP IRTR AASX AL AAS ADZ ACKB H'D15E ICDR* R/W 8 8 ICDR7 ICDR6 ICDR5 ICDR4 ICDR3 ICDR2 ICDR1 ICDR0 H'D15E SARX* R/W 8 8 SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 FSX H'D15F ICMR* R/W 8 8 MLS WAIT CKS2 CKS1 CKS0 BC2 BC1 BC0 H'D15F SAR* R/W 8 8 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS H'FFB0 TAR0 R/W 8 8 TA023 TA022 TA021 TA020 TA019 TA018 TA017 TA016 TA015 TA014 TA013 TA012 TA011 TA010 TA009 TA008 TA007 TA006 TA005 TA004 TA003 TA002 TA001 TA123 TA122 TA121 TA120 TA119 TA118 TA117 TA116 H'FFB4 TA115 TA114 TA113 TA112 TA111 TA110 TA109 TA108 H'FFB5 TA107 TA106 TA105 TA104 TA103 TA102 TA101 H'FFB1 H'FFB2 H'FFB3 TAR1 H'FFB6 TAR2 R/W R/W 8 8 8 TA223 TA222 TA221 TA220 TA219 TA218 TA217 TA216 H'FFB7 8 TA215 TA214 TA213 TA212 TA211 TA210 TA209 TA208 H'FFB8 TA207 TA206 TA205 TA204 TA203 TA202 TA201 Timer J Clock synchronizati on/start-stop sync SCI IIC interface * Access varies depending on ICE bit. ATC H'FFB9 TRCR R/W 8 8 TRC2 TRC1 H'FFBA TMA R/W 8 8 TMAOV TMAIE TMA3 TMA2 TMA1 TMA0 H'FFBB TCA R 8 8 TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 H'FFBC WTCSR R/W 8/16 16 OVF WT/,7 TME RSTS RS/10, CKS2 CKS1 CKS0 WDT H'FFBD WTCNT R/W 8/16 16 H'FFC0 PDR0 R 8 8 PDR07 PDR06 PDR05 PDR04 PDR03 PDR02 PDR01 PDR00 Port data register H'FFC1 PDR1 R/W 8 8 PDR17 PDR16 PDR15 PDR14 PDR13 PDR12 PDR11 PDR10 H'FFC2 PDR2 R/W 8 8 PDR27 PDR26 PDR25 PDR24 PDR23 PDR22 PDR21 PDR20 H'FFC3 PDR3 R/W 8 8 PDR37 PDR36 PDR35 PDR34 PDR33 PDR32 PDR31 PDR30 H'FFC4 PDR4 R/W 8 8 PDR47 PDR46 PDR45 PDR44 PDR43 PDR42 PDR41 PDR40 H'FFC5 PDR5 R/W 8 8 PDR53 PDR52 PDR51 PDR50 H'FFC6 PDR6 R/W 8 8 PDR67 PDR66 PDR65 PDR64 PDR63 PDR62 PDR61 PDR60 H'FFC7 PDR7 R/W 8 8 PDR77 PDR76 PDR75 PDR74 PDR73 PDR72 PDR71 PDR70 H'FFC8 PDR8 R/W 8 8 PDR87 PDR86 PDR85 PDR84 PDR83 PDR82 PDR81 PDR80 H'FFCD PMR0 R/W 8 8 PMR07 PMR06 PMR05 PMR04 PMR03 PMR02 PMR01 PMR00 H'FFCE PMR1 R/W 8 8 PMR17 PMR16 PMR15 PMR14 PMR13 PMR12 PMR11 PMR10 H'FFCF PMR2 R/W 8 8 PMR27 PMR26 PMR25 PMR20 Note: * Lower 16 bits of the address. Rev. 0.1, 11/98, page 832 of 975 TRC0 Timer A Port mode register Register Bus Module Address* Name R/W Access Width 7 6 5 4 3 2 1 0 Name H'FFD0 PMR3 R/W 8 8 PMR37 PMR36 PMR35 PMR34 PMR33 PMR32 PMR31 PMR30 Port mode register H'FFD1 PCR1 W 8 8 PCR17 PCR16 PCR15 PCR14 PCR13 PCR12 PCR11 PCR10 Port control register H'FFD2 PCR2 W 8 8 PCR27 PCR26 PCR25 PCR24 PCR23 PCR22 PCR21 PCR20 H'FFD3 PCR3 W 8 8 PCR37 PCR36 PCR35 PCR34 PCR33 PCR32 PCR31 PCR30 H'FFD4 PCR4 W 8 8 PCR47 PCR46 PCR45 PCR44 PCR43 PCR42 PCR41 PCR40 H'FFD5 PCR5 W 8 8 PCR53 PCR52 PCR51 PCR50 H'FFD6 PCR6 W 8 8 PCR67 PCR66 PCR65 PCR64 PCR63 PCR62 PCR61 PCR60 H'FFD7 PCR7 W 8 8 PCR77 PCR76 PCR75 PCR74 PCR73 PCR72 PCR71 PCR70 H'FFD8 PCR8 W 8 8 PCR87 PCR86 PCR85 PCR84 PCR83 PCR82 PCR81 PCR380 H'FFDB PMR4 R/W 8 8 PMR40 H'FFDC PMR5 R/W 8 8 PMR53 PMR52 PMR51 PMR50 H'FFDD PMR6 R/W 8 8 PMR67 PMR66 PMR65 PMR64 PMR63 PMR62 PMR61 PMR60 H'FFDE PMR7 R/W 8 8 PMR77 PMR76 PMR75 PMR74 PMR73 PMR72 PMR71 PMR70 H'FFDF PMR8 R/W 8 8 PMR83 PMR82 PMR81 PMR80 H'FFE1 PUR1 R/W 8 8 PUR17 PUR16 PUR15 PUR14 PUR13 PUR12 PUR11 PUR10 H'FFE2 PUR2 R/W 8 8 PUR27 PUR26 PUR25 PUR24 PUR23 PUR22 PUR21 PUR20 H'FFE3 PUR3 R/W 8 8 PUR37 PUR36 PUR35 PUR34 PUR33 PUR32 PUR31 PUR30 H'FFE4 RTPEGR R/W 8 8 RTPEGR1 RTPEGR0 H'FFE5 RTPSR R/W 8 8 RTPSR7 RTPSR6 RTPSR5 RTPSR4 RTPSR3 RTPSR2 RTPSR1 RTPSR0 H'FFE8 SYSCR R/W 8 8 INTM1 INTM0 XRST NMIEG1 NMIEG0 H'FFE9 MDCR R/W 8 8 MDS0 H'FFEA SBYCR R/W 8 8 SSBY STS2 STS1 STS0 SCK1 SCK0 H'FFEB LPWRCR R/W 8 8 DTON LSON NESEL SA1 SA0 H'FFEC MSTPCRH R/W 8 8 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 H'FFED MSTPCRL R/W 8 8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 H'FFEE STCR R/W 8 8 IICX IICRST FLASHE Port mode register Port pull-up select register RTP TRG select System control register H'FFF0 IEGR R/W 8 8 IRQ5EG IRQ4EG IRQ3EG IRQ2EG IRQ1EG IRQ0EG1 IRQ0EG0 IRQ edge H'FFF1 IENR R/W 8 8 IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E IRQ enable H'FFF2 IRQR R/W 8 8 IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F IRQ status H'FFF3 ICRA R/W 8 8 ICRA7 ICRA6 ICRA5 ICRA4 ICRA3 ICRA2 ICRA1 ICRA0 IRQ priority control H'FFF4 ICRB R/W 8 8 ICRB7 ICRB6 ICRB5 ICRB4 ICRB3 ICRB2 ICRB1 ICRB0 H'FFF5 ICRC R/W 8 8 ICRC7 ICRC6 ICRC5 ICRC4 ICRC3 ICRC2 ICRC1 ICRC0 H'FFF6 ICRD R/W 8 8 ICRD7 ICRD6 ICRD5 ICRD4 ICRD3 ICRD2 ICRD1 ICRD0 H'FFF8 FLMCR1 R/W 8 8 FWE SWE EV PV E P H'FFF9 FLMCR2 R/W 8 8 FLER ESU PSU H'FFFA EBR1 R/W 8 8 EB9 EB8 H'FFFB EBR2 R/W 8 8 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Only for FLASH version. Note: * Lower 16 bits of the address. Rev. 0.1, 11/98, page 833 of 975 B.2 Function List H'D000: Gain Constant DGKp: Drum Digital Filter H'D001: Gain Constant DGKp: Drum Digital Filter H'D002: Gain Constant DGKs: Drum Digital Filter H'D003: Gain Constant DGKs: Drum Digital Filter Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : * * * * * * * * * * * * * * * * R/W : W W W W W W W W W W W W W W W W H'D004: Coefficient DAp: Drum Digital Filter H'D005: Coefficient DAp: Drum Digital Filter H'D006: Coefficient DBp: Drum Digital Filter H'D007: Coefficient DBp: Drum Digital Filter H'D008: Coefficient DAs: Drum Digital Filter H'D009: Coefficient DAs: Drum Digital Filter H'D00A: Coefficient DBs: Drum Digital Filter H'D00B: Coefficient DBs: Drum Digital Filter Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : * * * * * * * * * * * * * * * * R/W : W W W W W W W W W W W W W W W W Rev. 0.1, 11/98, page 834 of 975 H'D00C: Offset DOfp: Drum Digital Filter H'D00D: Offset DOfp: Drum Digital Filter H'D00E: Offset DOfs: Drum Digital Filter H'D00F: Offset DOfs: Drum Digital Filter Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : * * * * * * * * * * * * * * * * R/W : W W W W W W W W W W W W W W W W 6 5 4 3 2 1 0 H'D010: Gain Constant CGKp: Capstan Digital Filter H'D011: Gain Constant CGKp: Capstan Digital Filter H'D012: Gain Constant CGKs: Capstan Digital Filter H'D013: Gain Constant CGKs: Capstan Digital Filter Bit : 15 14 13 12 11 10 9 8 7 Initial value : * * * * * * * * * * * * * * * * R/W : W W W W W W W W W W W W W W W W Rev. 0.1, 11/98, page 835 of 975 H'D014: Coefficient CAp: Capstan Digital Filter H'D015: Coefficient CAp: Capstan Digital Filter H'D016: Coefficient CBp: Capstan Digital Filter H'D017: Coefficient CBp: Capstan Digital Filter H'D018: Coefficient CAs: Capstan Digital Filter H'D019: Coefficient CAs: Capstan Digital Filter H'D01A: Coefficient CBs: Capstan Digital Filter H'D01B: Coefficient CBs: Capstan Digital Filter Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : * * * * * * * * * * * * * * * * R/W : W W W W W W W W W W W W W W W W 7 6 5 4 3 2 1 0 H'D01C: Offset COfp: Capstan Digital Filter H'D01D: Offset COfp: Capstan Digital Filter H'D01E: Offset COfs: Capstan Digital Filter H'D01F: Offset COfs: Capstan Digital Filter Bit : 15 14 13 12 11 10 9 8 Initial value : * * * * * * * * * * * * * * * * R/W : W W W W W W W W W W W W W W W W Rev. 0.1, 11/98, page 836 of 975 H'D020: Delay Initialization Register DZs: Digital filter H'D021: Delay Initialization Register DZs: Digital filter H'D022: Delay Initialization Register DZp: Digital filter H'D023: Delay Initialization Register DZp: Digital filter H'D024: Delay Initialization Register CZs: Digital filter H'D025: Delay Initialization Register CZs: Digital filter H'D026: Delay Initialization Register CZp: Digital filter H'D027: Delay Initialization Register CZp: Digital filter Bit : 15 14 13 12 Initial value : 1 1 1 1 R/W : 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 W W W W W W W W W W W W Rev. 0.1, 11/98, page 837 of 975 H'D028: Drum System Digital Filter Control Register DFIC: Digital Filter Bit : 7 -- 6 DROV 5 DPHA 4 DZPON 3 DZSON 2 DSG2 1 DSG1 0 DSG0 Initial value : R/W : 1 -- 0 R/(W)* 0 R/(W) 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Drum system gain control bit DSG2 0 1 DSG1 DSG0 Description 0 0 x1 1 x2 1 0 x4 1 x8 0 0 x 16 1 (x 32)* 1 0 (x 64)* 1 Invalid (do not set) Note: * Optional Drum speed system Z-1 initialization bit 0 1 Speed system Z-1 reflects DZs value. Speed system Z-1 does not relect DZs value. Drum phase system Z-1 initialization bit 0 1 Phase system Z-1 reflects DZp value. Phase system Z-1 does not relect DZp value. Drum phase system filter computation start bit 0 1 Phase system filter computation is OFF. Phase system computation result Y is not added to Es. Phase system filter computation is ON. Drum system range over flag 0 1 Filter computation result does not exceed 12 bits. Filter computation result exceeds 12 bits. Note: * Only 0 can be written. Rev. 0.1, 11/98, page 838 of 975 H'D029: Capstan System Digital Filter Control Register CFIC: Digital Filter Bit : 7 -- 6 CROV 5 CPHA 4 CZPON 3 CZSON 2 CSG2 1 CSG1 0 CSG0 Initial value : R/W : 1 -- 0 R/(W)* 0 R/(W) 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Capstan system gain control bit CSG2 0 1 CSG1 CSG0 Description 0 0 x1 1 x2 1 0 x4 1 x8 0 0 x 16 1 (x 32)* 1 0 (x 64)* 1 Invalid (do not set) Capstan speed system Z-1 initialization bit 0 1 Speed system Z-1 reflects CZs value. Speed system Z-1 does not relect CZs value. Capstan phase system Z-1 initialization bit 0 1 Phase system Z-1 reflects CZp value. Phase system Z-1 does not relect CZp value. Capstan phase system filter computation start bit 0 1 Phase system filter computation is OFF. Phase system computation result Y is not added to Es. Phase system filter computation is ON. Capstan system range over flag 0 1 Filter computation result does not exceed 12 bits. Filter computation result exceeds 12 bits. Note: * Only 0 can be written. Rev. 0.1, 11/98, page 839 of 975 H'D02A: Digital Filter Control Register DFUCR: Digital Filter Bit : 7 -- 6 -- 5 PTON 4 CP/DP 3 CFEPS 2 DFEPS 1 CFESS 0 DFESS Initial value : R/W : 1 -- 1 -- 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Drum speed system error data transfer bit 0 Transfer data by NCDFG signal latch. 1 Transfer data at the time of error data write. Capstan speed system error data transfer bit 0 Transfer data by DVCFG signal latch. 1 Transfer data at the time of error data write. Drum phase system error data transfer bit 0 Transfer data by HSW (NHSW) signal latch. 1 Transfer data at the time of error data write. Capstan phase system error data transfer bit 0 Transfer data by DVCFG2 signal latch. 1 Transfer data at the time of error data write. PWM output select bit 0 Output drum phase system computation result (CAPPWM) 1 Output capstan phase system computation result (DRMPWM) Phase system computation result PWM output bit 0 Output normal filter computation result to PWM pin. 1 Output only phase system computation result to PWM pin. Rev. 0.1, 11/98, page 840 of 975 H'D030: Specified DFG Speed Preset Data Register DFPR: Drum Error Detector H'D031: Specified DFG Speed Preset Data Register DFPR: Drum Error Detector Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : W W W W W W W W W W W W W W W W H'D032: DFG Speed Error Data Register DFER: Drum Error Detector H'D033: DFG Speed Error Data Register DFER: Drum Error Detector Bit : Initial value : R/W : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W Rev. 0.1, 11/98, page 841 of 975 H'D034: DFG Lock Upper Data Register DFRUDR: Drum Error Detector H'D035: DFG Lock Upper Data Register DFRUDR: Drum Error Detector Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : W W W W W W W W W W W W W W W W H'D036: DFG Lock Lower Data Register DFRLDR: Drum Error Detector H'D037: DFG Lock Lower Data Register DFRLDR: Drum Error Detector Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : W W W W W W W W W W W W W W W W Rev. 0.1, 11/98, page 842 of 975 H'D038: Drum Speed Error Detection Control Register DFVCR: Drum Error Detector Bit : Initial value : R/W : 7 DFCS1 6 DFCS0 5 DFOVF 0 R/W 0 R/W 0 R/(W)*1 4 3 DFRFON DF-R/UNR 0 R/W 2 DPCNT 1 DFRCS1 0 DFRCS0 0 R/W 0 (R)/W*2 0 (R)/W*2 0 R Drum lock counter setting bit DFRCS1 DFRCS0 Description 0 0 Underflow by 1 lock detection 1 Underflow by 2 lock detections 1 0 Underflow by 3 lock detections 1 Underflow by 4 lock detections Drum phase system filter computation auto start bit 0 1 Filter computation by drum lock detection is not excuted. Filter computation of phase system is executed at the time of drum lock detection. Drum lock flag 0 1 Drum speed system is not locked. Drum speed system is locked. Error data limit function select bit 0 1 Limit function OFF Limit function ON Counter overflow flag 0 1 Normal status Counter overflows. Clock source select bit DFCS1 DFCS0 Description 0 0 s 1 s/2 1 0 s/4 1 s/8 Notes: 1. Only 0 can be written. 2. When read, counter value is read. Rev. 0.1, 11/98, page 843 of 975 H'D039: Drum Phase Error Detection Control Register DPGCR: Drum Error Detector Bit : Initial value : R/W : 7 DPCS1 6 DPCS0 5 DPOVF 4 N/V 3 HSWES 2 -- 1 -- 0 -- 0 R/W 0 R/W 0 R/(W)* 0 R/W 0 R/W 1 -- 1 -- 1 -- Edge select bit 0 1 Latch at rising edge Latch at falling edge Error data latch signal select bit 0 1 HSW (VideFF) signal NHSW (NallowFF) signal Counter overflow flag 0 1 Normal status Counter overflows. Clock source select bit DPCS1 DPCS0 Description 0 0 s 1 s/2 1 0 s/3 1 s/4 Note: * Only 0 can be written. Rev. 0.1, 11/98, page 844 of 975 H'D03A: Specified Drum Phase Preset Data Register 2 DPPR2: Drum Error Detector H'D03B: Specified Drum Phase Preset Data Register 2 DPPR2: Drum Error Detector Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : W W W W W W W W W W W W W W W W H'D03C: Specified Drum Phase Preset Data Register 1 DPPR1: Drum Error Detector Bit : 7 -- 6 -- 5 -- 4 -- 3 2 1 0 Initial value : R/W : 1 -- 1 -- 1 -- 1 -- 0 W 0 W 0 W 0 W Rev. 0.1, 11/98, page 845 of 975 H'D03D: Drum Phase Error Data Register 1 DPER1: Drum Error Detector Bit : 7 -- 6 -- 5 -- 4 -- 3 2 1 0 Initial value : R/W : 1 -- 1 -- 1 -- 1 -- 0 R*/W 0 R*/W 0 R*/W 0 R*/W H'D03E: Drum Phase Error Data Register 2 DPER2: Drum Error Detector H'D03F: Drum Phase Error Data Register 2 DPER2: Drum Error Detector Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W H'D050: Specified CFG Speed Preset Data Register CFPR: Capstan Error Detector H'D051: Specified CFG Speed Preset Data Register CFPR: Capstan Error Detector Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : W W W W W W W W W W W W W W W W Rev. 0.1, 11/98, page 846 of 975 H'D052: CFG Speed Error Data Register CFER: Capstan Error Detector H'D053: CFG Speed Error Data Register CFER: Capstan Error Detector Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W H'D054: CFG Lock Upper Data Register CFRUDR: Capstan Error Detector H'D055: CFG Lock Upper Data Register CFRUDR: Capstan Error Detector Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : W W W W W W W W W W W W W W W W 1 0 H'D056: CFG Lock Lower Data Register CFRLDR: Capstan Error Detector H'D057: CFG Lock Lower Data Register CFRLDR: Capstan Error Detector Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Initial value : 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : W W W W W W W W W W W W W W W W Rev. 0.1, 11/98, page 847 of 975 H'D058: Capstan Speed Error Detection Control Register CFVCR: Capstan Error Detector Bit : Initial value : R/W : 7 CFCS1 6 CFCS0 5 CFOVF 0 R/W 0 R/W 0 R/(W)*1 4 3 2 CFRFON CF-R/UNR CPCNT 0 R/W 0 R 0 R/W 1 CFRCS1 0 CFRCS0 0 (R)/W*2 0 (R)/W*2 Capstan lock counter setting bit CFRCS1 CFRCS0 Description 0 0 Underflow by 1 lock detection 1 Underflow by 2 lock detections 1 0 Underflow by 3 lock detections 1 Underflow by 4 lock detections Capstan phase system filter computation auto start bit 0 1 Filter computation by capstan lock detection is not excuted. Filter computation of phase system is executed at the time of drum lock detection. Capstan lock flag 0 1 Capstan speed system is not locked. Capstan speed system is locked. Error data limit function select bit 0 1 Limit function OFF Limit function ON Counter overflow flag 0 1 Normal status Counter overflows. Clock source select bit CFCS1 CFCS0 Description 0 0 s 1 s/2 1 0 s/4 1 s/8 Notes: 1. Only 0 can be written. 2. When read, counter value is read. Rev. 0.1, 11/98, page 848 of 975 H'D059: Capstan Phase Error Detection Control Register CPGCR: Capstan Error Detector Bit : Initial value : R/W : 7 CPCS1 6 CPCS0 5 CPOVF 4 CR/RF 3 SELCFG2 2 -- 1 -- 0 -- 0 R/W 0 R/W 0 R/(W)* 0 R/W 0 R/W 1 -- 1 -- 1 -- Preset, latch signal select bit 0 1 Preset by CAPREF30 signal and latch by DVCTL signal Preset by REF30P signal and latch by DVCFG2 signal Preset signal select bit 0 1 Preset by REF30P signal Preset by CRRF signal Counter overflow flag 0 1 Normal status Counter overflows. Clock source select bit CPCS1 CPCS0 Description 0 0 s 1 s/2 1 0 s/4 1 s/8 Note: * Only 0 can be written. Rev. 0.1, 11/98, page 849 of 975 H'D05A: Specified Capstan Phase Preset Data Register 2 CPPR2: Capstan Error Detector H'D05B: Specified Capstan Phase Preset Data Register 2 CPPR2: Capstan Error Detector Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : W W W W W W W W W W W W W W W W H'D05C: Specified Capstan Phase Preset Data Register 1 CPPR1: Capstan Error Detector Bit : 7 -- 6 -- 5 -- 4 -- 3 2 1 0 Initial value : R/W : 1 -- 1 -- 1 -- 1 -- 0 W 0 W 0 W 0 W Rev. 0.1, 11/98, page 850 of 975 H'D05D: Capstan Phase Error Data Register 1 CPER1: Capstan Error Detector Bit : 7 -- 6 -- 5 -- 4 -- 3 2 1 0 Initial value : R/W : 1 -- 1 -- 1 -- 1 -- 0 R*/W 0 R*/W 0 R*/W 0 R*/W H'D05E: Capstan Phase Error Data Register 2 CPER2: Capstan Error Detector H'D05F: Capstan Phase Error Data Register 2 CPER2: Capstan Error Detector Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W R*/W Rev. 0.1, 11/98, page 851 of 975 H'D060: HSW Mode Register 1 HSM1: HSW Timing Generator Bit : Initial value : R/W : 7 FLB 6 FLA 5 EMPB 4 EMPA 3 OVWB 2 OVWA 1 CLRB 0 CLRA 0 R 0 R 1 R 1 R 0 R/(W)* 0 R/(W)* 0 R/W 0 R/W FIFO1 pointer clear 0 1 Normal operation Clear FIFO1 pointer FIFO2 pointer clear 0 1 Normal operation Clear FIFO2 pointer FIFO1 overwrite flag 0 Noram operation 1 Data is written to FIFO1 while it is full. Write 0 to clear the flag. FIFO2 overwrite flag 0 Noram operation 1 Data is written to FIFO1 while it is full. Write 0 to clear the flag. FIFO1 empty flag 0 1 Data remains in FIFO1 FIFO1 is empty FIFO2 empty flag 0 1 Data remains in FIFO2 FIFO2 is empty FIFO1 full flag 0 1 FIFO1 is not full FIFO1 is full FIFO2 full flag 0 1 FIFO2 is not full FIFO2 is full Note: * Only 0 can be written. Rev. 0.1, 11/98, page 852 of 975 H'D061: HSW Mode Register 2 HSM2: HSW Timing Generator Bit : 7 FRT 6 FGR20FF 5 LOP 4 EDG 3 ISEL1 2 SOFG 1 OFG 0 VFF/NFF Initial value : R/W : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R/W VideoFF/NallowFF output switchover bit 0 1 VideoFF output NallowFF output Output FIFO group flag 0 1 Outputting pattern by FIFO1 Outputting pattern by FIFO2 FIFO output group select bit 0 1 20-level output by FIFO1 and FIFO2 10-level output by FIFO1 only Interrupt select bit 0 1 Interrupt request is generated by rising of FIFO STRIG signal Interrupt request is generated by FIFO match signal DFG edge select bit 0 1 Calculated by DFG rising edge Calculated by DFG falling edge Mode select bit 0 1 Signal mode Loop mode FRG2 clear stop bit 0 1 16-bit counter clear by DFG reference register 2 is enabled 16-bit counter clear by DFG reference register 2 is disabled Free-run bit 0 1 5-bit DFG counter and 16-bit timer 16-bit FRC Rev. 0.1, 11/98, page 853 of 975 H'D062: HSW Loop Stage Setting Register HSLP: HSW Timing Generator 7 6 5 4 3 2 1 0 LOB3 LOB2 LOB1 LOB0 LOA3 LOA2 LOA1 LOA0 Bit : Initial value : R/W : * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W FIFO1 stage setting bit HSM2 Bit 5 LOP 0 1 Bit 3 LOA3 * 0 HSLP Bit 2 Bit 1 LOA2 LOA1 * * 0 0 1 1 0 1 1 0 0 1 1 0 1 Note: * Don't care. FIFO2 stage setting bit HSM2 Bit 5 LOP 0 1 Bit 7 LOB3 * 0 HSLP Bit 6 Bit 5 LOB2 LOB1 * * 0 0 1 1 0 1 1 0 0 1 1 0 1 Description Bit 4 LOB0 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Note: * Don't care. Rev. 0.1, 11/98, page 854 of 975 Single mode Output stage 0 of FIFO2 Output stage 0 and 1 of FIFO2 Output stage 0 to 2 of FIFO2 Output stage 0 to 3 of FIFO2 Output stage 0 to 4 of FIFO2 Output stage 0 to 5 of FIFO2 Output stage 0 to 6 of FIFO2 Output stage 0 to 7 of FIFO2 Output stage 0 to 8 of FIFO2 Output stage 0 to 9 of FIFO2 Setting disabled Description Bit 0 LOA0 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Single mode Output stage 0 of FIFO1 Output stage 0 and 1 of FIFO1 Output stage 0 to 2 of FIFO1 Output stage 0 to 3 of FIFO1 Output stage 0 to 4 of FIFO1 Output stage 0 to 5 of FIFO1 Output stage 0 to 6 of FIFO1 Output stage 0 to 7 of FIFO1 Output stage 0 to 8 of FIFO1 Output stage 0 to 9 of FIFO1 Setting disabled H'D064: FIFO Output Pattern Register 1 FPDRA: HSW Timing Generator H'D065: FIFO Output Pattern Register 1 FPDRA: HSW Timing Generator Bit : 15 -- 14 ADTRGA Initial value : R/W : 1 -- * W * W 7 PPGA7 6 PPGA6 * W * W Bit : Initial value : R/W : 11 VFFA 10 AFFA 9 VpulseA 8 MlevelA * W * W * W * W * W 5 PPGA5 4 PPGA4 3 PPGA3 2 PPGA2 1 PPGA1 0 PPGA0 * W * W * W * W * W * W 12 13 STRIGA NallowFFA H'D066: FIFO Timing Pattern Register 1 FTPRA: HSW Timing Generator H'D067: FIFO Timing Pattern Register 1 FTPRA: HSW Timing Generator Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : * * * * * * * * * * * * * * * * R/W : W W W W W W W W W W W W W W W W Rev. 0.1, 11/98, page 855 of 975 H'D066: FIFO Timer Capture Register 1 FTCTR: HSW Timing Generator H'D067: FIFO Timer Capture Register 1 FTCTR: HSW Timing Generator Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : R R R R R R R R R R R R R R R R H'D068: FIFO Output Pattern Register 2 FPDRB: HSW Timing Generator H'D069: FIFO Output Pattern Register 2 FPDRB: HSW Timing Generator Bit : 15 -- 14 ADTRGB Initial value : R/W : 1 -- * W * W 7 PPGB7 6 PPGB6 * W * W Bit : Initial value : R/W : 13 12 STRIGB NallowFFB 11 VFFB 10 AFFB 9 VpulseB 8 MlevelB * W * W * W * W * W 5 PPGB5 4 PPGB4 3 PPGB3 2 PPGB2 1 PPGB1 0 PPGB0 * W * W * W * W * W * W Rev. 0.1, 11/98, page 856 of 975 H'D06A: FIFO Timing Pattern Register 2 FTPRB: HSW Timing Generator H'D06B: FIFO Timing Pattern Register 2 FTPRB: HSW Timing Generator Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : * * * * * * * * * * * * * * * * R/W : W W W W W W W W W W W W W W W W H'D06C: DFG Reference Register 1 DFCRA: HSW Timing Generator Bit : Initial value : R/W : 7 ISEL2 6 CCLR 5 CKSL 4 DFCRA4 3 DFCRA3 0 W 0 W 0 W * W * W 2 1 DFCRA2 DFCRA1 * W * W 0 DFCRA0 * W 16-bit counter clock source select bit 0 1 s/4 s/8 DFG counter clear bit 0 Normal operation 1 Clear DFG counter Interrupt select bit 0 Interrupt request is generated by clear signal of 16-bit timer counter 1 Interrupt request is generated by VD signal in PB mode Rev. 0.1, 11/98, page 857 of 975 H'D06C: DFG Reference Count Register DFCTR: HSW Timing Generator Bit : Initial value : R/W : 7 6 5 -- -- -- 1 1 1 -- -- -- 4 DFCTR4 3 DFCTR3 2 DFCTR2 1 DFCTR1 0 DFCTR0 * R * R * R * R * R H'D06D: DFG Reference Register 2 DFCRB: HSW Timing Generator Bit : 7 -- 6 -- 5 -- 4 DFCRB4 3 DFCRB3 Initial value : R/W : 1 -- 1 -- 1 -- * W * W Rev. 0.1, 11/98, page 858 of 975 1 2 DFCRB2 DFCRB1 * W * W 0 DFCRB0 * W H'D06E: Special Effect Playback Control Register CHCR: 4-head Special Effect Playback Circuit Bit : Initial value : R/W : 7 V/N 6 HSWPOL 5 CRH 4 HAH 3 SIG3 2 SIG2 1 SIG1 0 SIG0 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Signal control bits SIG3 SIG2 SIG1 SIG0 0 0 1 * 0 * 0 1 0 1 * 1 1 0 1 0 1 0 1 Output pin C.Rotary H.Amp SW L L HSW L HSW H L HSW H HSW HSW EX-OR COMP COMP HSW EX-NOR COMP COMP HSW EX-OR RTP0 RTP0 HSW EX-NOR RTP0 RTP0 Note: * Don't care. H.AmpSW synchronization control bit 0 Synchronous 1 Asynchronous C.Rotary synchronization control bit 0 Synchronous 1 Asynchronous COMP polarity select bit 0 Positive 1 Negative HSW output signal select bit 0 VideoFF signal output 1 Nallow FF signal output Rev. 0.1, 11/98, page 859 of 975 H'D06F: Additional V Control Register ADDVR: Additional V Signal Generator Bit : 7 -- 6 -- 5 -- 4 HMSK 3 HiZ 2 CUT 1 VPOM 0 POL Initial value : R/W : 1 -- 1 -- 1 -- 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Additional V output control bits CUT VPON POL Description 0 0 * Low level 1 0 Negative polarity (Figure 27.42) 1 Positive polarity (Figure 27.41) 1 * 0 Immediate level (high-impedance when HiZ bit = 1) 1 High level Note: * Don't care. High impedance bit 0 3-level output from Vpulse pin 1 Vpulse pin is set as 3-state (H/L/HiZ) pin OSCH mask bit 0 OSCH added 1 OSCH not added Rev. 0.1, 11/98, page 860 of 975 H'D070: X-Value Data Register XDR: X-Value, TRK-Value H'D071: X-Value Data Register XDR: X-Value, TRK-Value Bit : Initial value : R/W : 15 14 13 12 -- -- -- -- 1 -- 1 -- 1 -- 1 -- 11 10 9 8 7 6 5 4 3 2 1 0 XD11 XD10 XD9 XD8 XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0 0 0 0 0 0 0 0 0 0 0 0 0 W W W W W W W W W W W W 4 3 2 1 0 H'D072: TRK-Value Data Register TRDR: X-Value, TRK-Value H'D073: TRK-Value Data Register TRDR: X-Value, TRK-Value Bit : 15 14 13 12 -- -- -- -- 11 10 9 8 7 6 5 TRD11 TRD10 TRD9 TRD8 TRD7 TRD6 TRD5 TRD4 TRD3 TRD2 TRD1 TRD0 Initial value : 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 R/W : -- -- -- -- W W W W W W W W W W W W Rev. 0.1, 11/98, page 861 of 975 H'D074: X-Value/TRK-Value Control Register XTCR: X-Value, TRK-Value Adjustment Circuit Bit : 7 -- 6 CAPRF 5 AT/MU 4 TRK/X 3 EXC/REF 2 XCS 1 DVREF1 0 DVREF0 Initial value : R/W : 1 -- 0 W 0 W 0 W 0 W 0 W 0 R/W 0 R/W REF30P frequency division rate select bit DVREF1 DVREF0 Description 0 0 1-division 1 2-division 1 0 3-division 1 4-division Clock source select bit 0 s 1 s/2 Reference signal select bit 0 Generated by REF30P signal 1 Generated by external referece signal Capstan phase adjustment register select bit 0 CAPREF30 is generated only by XDR setting value 1 CAPREF30 is generated by XDR and TRDR setting values Capstan phase adjustment auto/manual select bit 0 1 Manual mode Auto mode External sync signal edge select bit 0 Generated at EXCAP rising edge 1 Generated at EXCAP rising and falling edge Rev. 0.1, 11/98, page 862 of 975 H'D078: Drum 12-bit PWM Data Register DPWDR: Drum 12-Bit PWM Bit : 15 14 13 12 -- -- -- -- 11 10 9 8 7 6 5 4 3 2 1 0 DPWDR11 DPWDR10 DPWDR9 DPWDR8 DPWDR7 DPWDR6 DPWDR5 DPWDR4 DPWDR3 DPWDR2 DPWDR1 DPWDR0 Initial value : 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 R/W : -- -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 0.1, 11/98, page 863 of 975 H'D07A: Drum 12-Bit PWM Control Registor DPWCR: Drum 12-Bit PWM Bit : Initial value : R/W : 7 DPOL 6 DDC 5 DHiZ 4 DH/L 3 DSF/DF 2 DCK2 1 DCK1 0 DCK0 0 W 1 W 0 W 0 W 0 W 0 W 1 W 0 W Carrier frequency select bits CK2 CK1 CK0 0 0 0 /2 1 /4 0 /8 1 /16 0 /32 1 /64 0 /128 1 (Do not set) 1 1 0 1 Carrier frequency select bits Output data select bit 0 Modulate error data from digital filter circuit 1 Modulate data written in data register Note: When PWMs output data from the digital filter circuit, the data consisting of the speed and phase filtering results are modulated by PWMs and output from the CAPPWM and DRMPWM pins. However, it is possible to output only drum phase filter results from CAPPWM pin and only capstan phase filter result from DRMPWM pin, by DFUCR settings of the digital filter circuit. See the section explaining the digital filter computation circuit. Fixed output bit, PWM pin output bit DC HiZ H/L 1 0 0 0 Fixed output bit, PWM pin output bit Low level output from PWM pin 1 High level output form PWM pin 1 * High impedance from PWM pin * * PWM modulated signal output Note: * Don't care. Polarity switchover bit 0 Positive polarity 1 Negative polarity output Rev. 0.1, 11/98, page 864 of 975 H'D07B: Capstan 12-Bit PWM Control Register CPWCR: Capstan 12-Bit PWM Bit : Initial value : R/W : 7 CPOL 6 CDC 5 CHiZ 4 CH/L 3 CSF/DF 2 CCK2 1 CCK1 0 CCK0 0 W 1 W 0 W 0 W 0 W 0 W 1 W 0 W H'D07C: Capstan 12-Bit PWM Data Register CPWDR: Capstan 12-Bit PWM Bit : 15 14 13 12 -- -- -- -- 11 10 9 8 7 6 5 4 3 2 1 0 CPWDR11 CPWDR10 CPWDR9 CPWDR8 CPWDR7 CPWDR6 CPWDR5 CPWDR4 CPWDR3 CPWDR2 CPWDR1 CPWDR0 Initial value : 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 R/W : -- -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 0.1, 11/98, page 865 of 975 H'D080: CTL Control Register CTCR: CTL Circuit Bit : 7 6 5 4 3 2 1 0 NT/PL FSLC FSLB FSLA CCS LCTL UNCTL SLWM Initial value : 0 0 1 1 0 0 0 0 R/W : W W W W W W R W Mode select bit 0 Normal mode 1 Slow mode CTL undetected bit 0 Detected 1 Undetected Long CTL bit 0 Clock source (CCS) operates at the setting value 1 Clock source (CCS) operates for further 8-division after operating at the setting value Clock source select bit 0 s 1 s/2 Operating frequency select bits FSLC FSLB FSLA Description 0 0 0 Reserved (do not set) 1 Reserved (do not set) 1 0 fosc = 8 MHz 1 fosc = 10 MHz (Initial value) 1 * * Reserved (do not set) Note: * Don't care. NTSC/PAL select bit 0 NTSC mode (frame rate: 30 Hz) 1 PAL mode (frame rate: 25 Hz) Rev. 0.1, 11/98, page 866 of 975 H'D081: CTL Mode Register CTLM: CTL Circuit 7 6 5 4 3 2 1 0 ASM REC/PB FW/RV MD4 MD3 MD2 MD1 MD0 Bit : Initial value : R/W : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W CTL mode select bits Direction bit 0 FORWARD 1 REVERSE Record/playback mode bits ASM REC/PB Description 0 0 Playback mode (PLAYBACK) 1 Record mode (RECORD) 1 0 Assemble mode 1 Invalid (do not set) H'D082: REC-CTL Duty Data Register 1 RCDR1: CTL Circuit H'D083: REC-CTL Duty Data Register 1 RCDR1: CTL Circuit Bit : Initial value : R/W : 15 14 13 12 -- -- -- -- 1 -- 1 -- 1 -- 1 -- 11 10 9 8 7 6 5 4 3 2 1 0 CMT1B CMT1A CMT19 CMT18 CMT17 CMT16 CMT15 CMT14 CMT13 CMT12 CMT11 CMT10 0 0 0 0 0 0 0 0 0 0 0 0 W W W W W W W W W W W W Rev. 0.1, 11/98, page 867 of 975 H'D084: REC-CTL Duty Data Register 2 RCDR2: CTL Circuit H'D085: REC-CTL Duty Data Register 2 RCDR2: CTL Circuit Bit : Initial value : R/W : 15 14 13 12 -- -- -- -- 1 -- 1 -- 1 -- 1 -- 11 10 9 8 7 6 5 4 3 2 1 0 CMT2B CMT2A CMT29 CMT28 CMT27 CMT26 CMT25 CMT24 CMT23 CMT22 CMT21 CMT20 0 0 0 0 0 0 0 0 0 0 0 0 W W W W W W W W W W W W 3 2 1 0 H'D086: REC-CTL Duty Data Register 3 RCDR3: CTL Circuit H'D087: REC-CTL Duty Data Register 3 RCDR3: CTL Circuit Bit : Initial value : R/W : 15 14 13 12 -- -- -- -- 1 -- 1 -- 1 -- 1 -- 11 10 9 8 7 6 5 4 CMT3B CMT3A CMT39 CMT38 CMT37 CMT36 CMT35 CMT34 CMT33 CMT32 CMT31 CMT30 0 0 0 0 0 0 0 0 0 0 0 0 W W W W W W W W W W W W 3 2 1 0 H'D088: REC-CTL Duty Data Register 4 RCDR4: CTL Circuit H'D089: REC-CTL Duty Data Register 4 RCDR4: CTL Circuit Bit : Initial value : R/W : 15 14 13 12 -- -- -- -- 1 -- 1 -- 1 -- 1 -- 11 10 9 8 7 6 5 4 CMT4B CMT4A CMT49 CMT48 CMT47 CMT46 CMT45 CMT44 CMT43 CMT42 CMT41 CMT40 0 0 0 0 0 0 0 0 0 0 0 0 W W W W W W W W W W W W 3 2 1 0 H'D08A: REC-CTL Duty Data Register 5 RCDR5: CTL Circuit H'D08B: REC-CTL Duty Data Register 5 RCDR5: CTL Circuit Bit : Initial value : R/W: 15 14 13 12 -- -- -- -- 1 -- 1 -- 1 -- 1 -- 11 10 9 8 7 6 5 4 CMT5B CMT5A CMT59 CMT58 CMT57 CMT56 CMT55 CMT54 CMT53 CMT52 CMT51 CMT50 0 0 0 0 0 0 0 0 0 0 0 0 W W W W W W W W W W W W Rev. 0.1, 11/98, page 868 of 975 H'D08C: Duty I/O Register DI/O: CTL Circuit Bit : Initial value : R/W : 7 VCTR2 6 VCTR1 5 VCTR0 4 -- 3 BPON 2 BPS 1 BPF 0 DI/O 1 W 1 W 1 W 1 -- 0 W 0 W 0 R/(W)* 1 R/W Duty I/O register Bit pattern detection flag 0 Bit pattern (8-bit) is not detected 1 Bit pattern (8-bit) is detected Bit pattern detection start bit 0 Normal status 1 Starts 8-bit bit pattern detection Bit pattern detection ON/OFF bit 0 Bit pattern detection OFF 1 Bit pattern detection ON VISS interrupt setting bits VCTR2 VCTR1 VCTR0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Number of 1-pulse for detection 2 4 (SYNC mark) 6 8 (mark A, short) 12 (mark A, long) 16 24 (mark B) 32 Note: * Only 0 can be written. Rev. 0.1, 11/98, page 869 of 975 H'D08D: Bit Pattern Register BTPR: CTL Circuit Bit : 7 LSP7 6 LSP6 5 LSP5 4 LSP4 3 LSP3 2 LSP2 1 LSP1 0 LSP0 Initial value : R/W : 1 R*/W 1 R*/W 1 R*/W 1 R*/W 1 R*/W 1 R*/W 1 R*/W 1 R*/W Note: * Writes are disabled during bit pattern detection. H'D090: Reference Frequency Register 1 RFD: Reference Signal Generator H'D091: Reference Frequency Register 1 RFD: Reference Signal Generator Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 REF15 REF14 REF13 REF12 REF11 REF10 REF9 REF8 REF7 REF6 REF5 REF4 REF3 REF2 REF1 REF0 Initial value : R/W : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 W W W W W W W W W W W W W W W W 1 0 H'D092: Reference Frequency Register 2 CRF: Reference Signal Generator H'D093: Reference Frequency Register 2 CRF: Reference Signal Generator Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 CRF15 CRF14 CRF13 CRF12 CRF11 CRF10 CRF9 CRF8 CRF7 CRF6 CRF5 CRF4 CRF3 CRF2 CRF1 CRF0 Initial value : R/W : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 W W W W W W W W W W W W W W W W 2 1 0 H'D094: REF30 Counter Register RFC: Reference Signal Generator H'D095: REF30 Counter Register RFC: Reference Signal Generator Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 RFC15 RFC14 RFC13 RFC12 RFC11 RFC10 RFC9 RFC8 RFC7 RFC6 RFC5 RFC4 RFC3 RFC2 RFC1 RFC0 Initial value : R/W : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. 0.1, 11/98, page 870 of 975 H'D096: Reference Frequency Mode Register RFM: Reference Signal Generator Bit : Initial value : R/W : 7 RCS 6 VNA 5 CVS 4 REX 3 CRD 2 OD/EV 1 VST 0 VEG 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W VideoFF edge select bit 0 Set at VideoFF signal rising 1 Set at VideoFF signal falling VideoFF counter set 0 VideoFF signal turns counter set OFF 1 VideoFF signal turns counter set OFF ODD/EVEN edge switchoverselect bit 0 Generated at field signal rising (EVEN) 1 Generated at field signal rising (ODD) DVCFG2 synchronization select bit 0 At mode switching 1 DVCFG2 signal synchronized External signal synchronization select bit 0 VD signal or free-run 1 External signal sync Manual select bit 0 VD sync 1 Free-run Mode select bit 0 Manual mode 1 Auto mode Clock source select bit 0 s/2 1 s/4 Rev. 0.1, 11/98, page 871 of 975 H'D097: Reference Frequency Mode Register 2 RFM2: Reference Signal Generator Bit : 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 FDS Initial value : R/W : 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 0 R/W Field select bit 0 Generated by selected ODD or EVEN VD signal 1 Generated by VD signal immediately after mode transition Rev. 0.1, 11/98, page 872 of 975 H'D098: DVCTL Control Register CTVC: Frequency Divider Bit : Initial value : R/W : 7 CEX 6 CEG 5 -- 4 -- 3 -- 2 CFG 1 HSW 0 CTL 0 W 0 W 1 -- 1 -- 1 -- * R * R * R CTL flag 0 REC or PB-CTL level is low 1 REC or PB-CTL level is high HSW flag 0 HSW level is low 1 HSW level is high CFG flag 0 CFG level is low 1 CFG level is high External sync signal edge select bit 0 Rising edge 1 Falling edge DVCTL signal generation select bit 0 Generated by PB-CTL signal 1 Generated by external input signal Rev. 0.1, 11/98, page 873 of 975 H'D099: CTL Frequency Division Register CTLR: Frequency Divider Bit : Initial value : R/W : 7 CTL7 6 CTL6 5 CTL5 4 CTL4 3 CTL3 2 CTL2 1 CTL1 0 CTL0 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W H'D09A: DVCFG Control Register CDVC: Frequency Divider Bit : Initial value : R/W : 7 MCGin 6 -- 5 CMK 4 CMN 3 DVTRG 2 CRF 1 CPS1 0 CPS0 0 R/W* 1 -- 1 R 0 W 0 W 0 W 0 W 0 W CFG mask timer clock select bit CPS1 0 1 CPS0 0 1 0 1 Description s/1024 s/512 s/256 s/128 CFG frequency division edge select bit 0 Execute frequency division operation at CFG rising edge 1 Execute frequency division operation at CFG rising and falling edges PB (ASM)-to-REC transition timing sync ON/OFF select bit 0 PB (ASM)-to-REC transition timing sync ON 1 PB (ASM)-to-REC transition timing sync OFF CFG mask select bit 0 Capstan mask timing function ON 1 Capstan mask timing function OFF CFG mask status bit 0 Mask is released by capstan mask timer 1 Mask is set by capstan mask timer Mask CFG flag 0 CFG normal operation 1 DVCFG is detected while mask is set (race detection) Note: * Only 0 can be written Rev. 0.1, 11/98, page 874 of 975 H'D09B: CFG Frequency Division Register 1 CDIVR1: Frequency Divider Bit : 7 -- 6 CDV16 5 CDV15 4 CDV14 3 CDV13 2 CDV12 1 CDV11 0 CDV10 Initial value : R/W : 1 -- 0 W 0 W 0 W 0 W 0 W 0 W 0 W H'D09C: CFG Frequency Division Register 2 CDIVR2: Frequency Divider Bit : 7 -- 6 CDV26 5 CDV25 4 CDV24 3 CDV23 2 CDV22 1 CDV21 0 CDV20 Initial value : R/W : 1 -- 0 W 0 W 0 W 0 W 0 W 0 W 0 W H'D09D: DVCFG Mask Interval Register CTMR: Frequency Divider Bit : 7 -- 6 -- 5 CPM5 4 CPM4 3 CPM3 2 CPM2 1 CPM1 0 CPM0 Initial value : R/W : 1 -- 1 -- 1 W 1 W 1 W 1 W 1 W 1 W Rev. 0.1, 11/98, page 875 of 975 H'D09E: FG Control Register FGCR: Frequency Divider Bit : 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- DRF Initial value : 1 1 1 1 1 1 1 0 R/W : -- -- -- -- -- -- -- W DFG edge select bit 0 NCDFG signal rising edge is selected 1 NCDFG signal falling edge is selected H'D0A0: Servo Port Mode Register SPMR: Servo Port Bit : Initial value : R/W : 7 CTLSTOP 6 -- 0 R/W 1 -- 4 3 5 CFGCOMP EXCTLON DPGSW 0 R/W 0 R/W 0 R/W 2 COMP 1 H.Amp.SW 0 C.Rot 0 R/W 0 R/W 0 R/W C.Rotary pin function switch bit 0 C.Rotary/PS0 pin functions as C.Rotary output pin 1 C.Rotary/PS0 pin functions as PS0 I/O pin H.AmpSW pin function switch bit 0 H.AmpSW/PS1 pin functions as H.AmpSW output pin 1 H.AmpSW/PS1 pin functions as PS1 I/O pin COMP pin function switch bit 0 COMP/PS2 pin functions as COMP input pin 1 COMP/PS2 pin functions as PS2 I/O pin DPG pin functionswitch bit 0 Separate input for drum control system input (DPG/PS3 pin functions as DPG input pin) 1 Weight input for drum control system input (DPG/PS3 pin functions as PS3 I/O pin) EXCTL pin function switch bit 0 EXCTL/PS4 pin functions as EXCEL input pin 1 EXCTL/PS4 pin functions as PS4 I/O pin CFG input method switch bit 0 Zero cross type comparator method for CFG signal input 1 Digital signal input method for CFG signal input CTLSTOP bit 0 CTL circuit operates 1 CTL circuit does not operate Rev. 0.1, 11/98, page 876 of 975 H'D0A1: Servo Control Register SPCR: Servo Port Bit : 7 -- 6 -- 5 -- 4 SPCR4 3 SPCR3 2 SPCR2 1 SPCR1 0 SPCR0 Initial value : R/W : 1 -- 1 -- 1 -- 0 W 0 W 0 W 0 W 0 W SPCRn Description 0 PSn pin functions as input pin 1 PSn pin functions as output pin H'D0A2: Servo Data Register SPDR: Servo Port Controller Bit : 7 -- 6 -- 5 -- 4 SPDR4 3 SPDR3 2 SPDR2 1 SPDR1 0 SPDR0 Initial value : R/W : 1 -- 1 -- 1 -- 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 0.1, 11/98, page 877 of 975 H'D0A3: Servo Monitor Control Register SVMCR: Servo Port Bit : 7 -- 6 -- Initial value : R/W : 1 -- 1 -- 5 4 3 2 1 0 SVMCR5 SVMCR4 SVMCR3 SVMCR2 SVMCR1 SVMCR0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W SVMCR2 SVMCR1 SVMCR0 Description 0 0 0 REF30 signal is output from SV1 output pin 1 CAPREF30 signal is output from SV1 output pin 1 0 CREF signal is output from SV1 output pin 1 CTLMONI signal is output from SV1 output pin 1 0 0 DVCFG signal is output from SV1 output pin 1 CFG signal is output from SV1 output pin 1 0 DFG signal is output from SV1 output pin 1 DPG signal is output from SV1 output pin SVMCR5 SVMCR4 SVMCR3 Description 0 0 0 REF30 signal is output from SV2 output pin 1 CAPREF30 signal is output from SV2 output pin 1 0 CREF signal is output from SV2 output pin 1 CTLMONI signal is output from SV2 output pin 1 0 0 DVCFG signal is output from SV2 output pin 1 CFG signal is output from SV2 output pin 1 0 DFG signal is output from SV2 output pin 1 DPG signal is output from SV2 output pin Rev. 0.1, 11/98, page 878 of 975 H'D0A4: CTL Gain Control Register CTLGR: Servo Port Bit : 7 -- 6 -- 5 CTLE/A 4 CTLFB 3 CTLGR3 2 CTLGR2 1 CTLGR1 0 CTLGR0 Initial value : R/W : 1 -- 1 -- 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W CTL amp gain setting bit CTLGR3 CTLGR2 CTLGR1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 CTLGR0 CTL outpu gain 0 35.0 dB 1 37.5 dB 0 40.0 dB 1 42.5 dB 0 45.0 dB 1 47.5 dB 0 50.0 dB 1 52.5 dB 0 55.0 dB 1 57.5 dB 0 60.0 dB 1 62.5 dB 0 65.0 dB 1 67.5 dB 0 70.0 dB 1 72.5 dB CTL amp feedback SW bit 0 CTLFB SW is OFF 1 CTLFB SW is ON CTL select bit 0 AMP output 1 EXCTL Rev. 0.1, 11/98, page 879 of 975 H'D0B0: Vertical Sync Signal Threshold Value Register VTR: Sync Detector (Servo) Bit : 7 -- 6 -- 5 VTR5 4 VTR4 3 VTR3 2 VTR2 1 VTR1 0 VTR0 Initial value : R/W : 1 -- 1 -- 0 W 0 W 0 W 0 W 0 W 0 W H'D0B1: Horizontal Sync Signal Threshold Value Register HTR: Sync Detector (Servo) Bit : 7 -- 6 -- 5 -- 4 -- 3 HTR3 2 HTR2 1 HTR1 0 HTR0 Initial value : R/W : 1 -- 1 -- 1 -- 1 -- 0 W 0 W 0 W 0 W H'D0B2: H Pulse Adjustment Start Time Setting Register HRTR: Sync Detector (Servo) Bit : Initial value : R/W : 7 HRTR7 6 HRTR6 5 HRTR5 4 HRTR4 3 HRTR3 2 HRTR2 1 HRTR1 0 HRTR0 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Rev. 0.1, 11/98, page 880 of 975 H'D0B3: H Pulse Width Setting Register HPWR: Sync Detector (Servo) Bit : 7 -- 6 -- 5 -- 4 -- 3 HPWR3 2 HPWR2 1 HPWR1 0 HPWR0 Initial value : R/W : 1 -- 1 -- 1 -- 1 -- 0 W 0 W 0 W 0 W H'D0B4: Noise Detection Window Setting Register NWR: Sync Detector (Servo) Bit : 7 -- 6 -- 5 NWR5 4 NWR4 3 NWR3 2 NWR2 1 NWR1 0 NWR0 Initial value : R/W : 1 -- 1 -- 0 W 0 W 0 W 0 W 0 W 0 W H'D0B5: Noise Detection Register NDR: Sync Detector (Servo) Bit : Initial value : R/W : 7 NDR7 6 NDR6 5 NDR5 4 NDR4 3 NDR3 2 NDR2 1 NDR1 0 NDR0 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Rev. 0.1, 11/98, page 881 of 975 H'D0B6: Sync Signal Control Register SYNCR: Sync Detector (Servo) Bit : 7 -- 6 -- 5 -- 4 -- 3 NIS/VD 2 NOIS 1 FLD 0 SYCT Initial value : R/W : 1 -- 1 -- 1 -- 1 -- 1 R/W 0 R/(W)* 0 R 0 R/W Sync signal polarity select bit SYCT 0 Description 1 Field detection flag 0 Odd field 1 Even field Noise detection flag 0 Noise count is less than four times of NDR setting value 1 Noise count is over four times of NDR setting value Interrupt select bit 0 Noise level interrupt 1 VD interrupt Note: * Only 0 can be written. Rev. 0.1, 11/98, page 882 of 975 Polarity Positive Negative H'D0B8: Servo Interrupt Enable Register 1 SIENR1: Servo Interrupt Bit : Initial value : R/W : 7 IEDRM3 6 IEDRM2 5 IEDRM1 4 IECAP3 3 IECAP2 2 IECAP1 1 IEHSW2 0 IEHSW1 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W HSW timing generator (OVW, match, STRIG) interrupt enable bit 0 Interrupt request is disabled by IRRHSW1 1 Interrupt request is enabled by IRRHSW1 HSW timing generation (counter clear, capture) interrupt enable bit 0 Interrupt request is disabled by IRRHSW2 1 Interrupt request is enabled by IRRHSW2 Capstan speed error detection (OVF, latch) interrupt enable bit 0 Interrupt request is disabled by IRRCAP1 1 Interrupt request is enabled by IRRCAP1 Capstan speed error detection (lock detection) interrupt enable bit 0 Interrupt request is disabled by IRRCAP2 1 Interrupt request is enabled by IRRCAP2 Capstan phase error detection interrupt enable bit 0 Interrupt request is disabled by IRRCAP3 1 Interrupt request is enabled by IRRCAP3 Drum speed error detection (OVF, latch) interrupt enable bit 0 Interrupt request is disabled by IRRDRM1 1 Interrupt request is enabled by IRRDRM1 Drum speed error detection (lock detection) interrupt enable bit 0 Interrupt request is disabled by IRRDRM2 1 Interrupt request is enabled by IRRDRM2 Drum phase error detection interrupt enable bit 0 Interrupt request is disabled by IRRDRM3 1 Interrupt request is enabled by IRRDRM3 Rev. 0.1, 11/98, page 883 of 975 H'D0B9: Servo Interrupt Enable Register 2 SIENR2: Servo Interrupt Bit : Initial value : R/W : 7 6 5 4 3 2 -- -- -- -- -- -- 1 1 1 1 1 1 -- -- -- -- -- -- 1 IESNC 0 IECTL 0 R/W 0 R/W CTL interrupt enable bit 0 Interrupt request is disabled by IRRCTL 1 Interrupt request is enabled by IRRCTL Vertical sync signal interrupt enable bit 0 Interrupt (vertical sync signal interrupt) request is disabled by IRRSNC 1 Interrupt (vertical sync signal interrupt) request is enabled by IRRSNC Rev. 0.1, 11/98, page 884 of 975 H'D0BA: Servo Interrupt Request Register 1 SIRQR1: Servo Interrupt Bit : Initial value : R/W : 1 0 2 4 3 7 6 5 IRRDRM3 IRRDRM2 IRRDRM1 IRRCAP3 IRRCAP2 IRRCAP1 IRRHSW2 IRRHSW1 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* HSW timing generator (OVW, match, STRIG) interrupt request bit 0 HSW timing generator (OVM, match, STRIG) interrupt request is not generated 1 HSW timing generator (OVM, match, STRIG) interrupt request is generated HSW timing generator (counter clear, capture) interrupt request bit 0 HSW timing generator (counter clear, capture) interrupt request is not generated 0 HSW timing generator (counter clear, capture) interrupt request is generated Capstan speed error detector (OVF, latch) interrupt request bit 0 Capstan speed error detector (OVF, latch) interrupt request in not generated 1 Capstan speed error detector (OVF, latch) interrupt request in generated Capstan speed error detector (lock detection) intrerrupt request bit 0 Capstan speed error detector (lock detection) interrupt request is not generated 1 Capstan speed error detector (lock detection) interrupt request is generated Capstan phase error detector (OVF, latch) interrupt request bit 0 Capstan phase error detector (OVF, latch) interrupt request is not generated 1 Capstan phase error detector (OVF, latch) interrupt request is generated Drum speed error detector (OVF, latch) interrupt request bit 0 Drum speed error detector (OVF, latch) interrupt request is not generated 1 Drum speed error detector (OVF, latch) interrupt request is generated Drum speed error detector (lock detection) interrupt request bit 0 Drum speed error detector (lock detection) interrupt request is not generated 1 Drum speed error detector (lock detection) interrupt request is generated Drum phase error detector interrupt request bit 0 Drum phase error detector interrupt request is not generated 1 Drum phase error detector interrupt request is generated Note: * Only 0 can be written to clear the flag. Rev. 0.1, 11/98, page 885 of 975 H'D0BB: Servo Interrupt Request Register 2 SIRQR2: Servo Interrupt Bit : Initial value : R/W : 7 6 5 4 3 2 -- -- -- -- -- -- 1 1 1 1 1 1 -- -- -- -- -- -- 1 IRRSNC 0 IRRCTL 0 R/(W)* 0 R/(W)* CTL interrupt request bit 0 CTL interrupt request is not generated 1 CTL interrupt request is generated Vertical sync signal interrupt request bit 0 Sync signal detector (VD, noise) interrupt request is not generated 1 Sync signal detector (VD, noise) interrupt request is generated Note: * Only 0 can be written to clear the flag. Rev. 0.1, 11/98, page 886 of 975 H'D0E0: Start Address Register STAR: 32-Byte Buffer SCI2 Bit : Initial value : R/W : 7 6 5 -- -- -- 1 1 1 -- -- -- 4 STA4 3 STA3 2 STA2 1 STA1 0 STA0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W H'D0E1: End Address Register EDAR: 32-Byte Buffer SCI2 Bit : Initial value : R/W : 7 6 5 -- -- -- 1 1 1 -- -- -- 4 EDA4 3 EDA3 2 EDA2 1 EDA1 0 EDA0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 0.1, 11/98, page 887 of 975 H'D0E2: Serial Control Register 2 SCR2: 32-Byte Buffer SCI2 Bit : 7 TEIE 6 ABTIE 5 -- 4 GAP1 3 GAP0 2 CKS2 1 CKS1 0 CKS0 Initial value : R/W : 0 R/W 0 R/W 1 -- 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Transfer clock select bits CKS2 CKS1 CKS0 SCK2 pin 0 0 0 0 0 /64 6.4 s 12.8 s 0 0 0 /32 3.2 s 6.4 s 0 0 0 0 0 0 /16 /8 1.6 s 0.8 s 3.2 s 1.6 s SCK2 output Sprescaler S Prescaler frequency Transfer clock frequency division rate = 10 MHz = 5 MHz /256 25.6 s 51.2 s 0 0 0 0 /4 0.4 s 0.8 s 0 0 0 0 0 0 /2 -- -- 0.4 s -- SCK2 input Transfer data interval select bits GAP1 GAP0 Transfer data interval 0 0 No interval 0 1 8-clock interval 1 0 24-clock interval 0 1 56-clock interval Transfer interrupt enable bit 0 Transfer interrupt request is disabled 1 Transfer interrupt request is enabled Transfer end interrupt enable bit 0 Transfer-end interrupt request is disabled 1 Transfer-end interrupt request is enabled Rev. 0.1, 11/98, page 888 of 975 Clock source External clock -- H'D0E3: Serial Control Status Register 2 SCSR2: 32-Byte Buffer SCI2 Bit : Initial value : R/W : 7 TEI 6 -- 5 -- 4 SOL 3 ORER 2 WT 1 ABT 0 STF 0 R/(W)* 1 -- 1 -- 0 R/W 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/W Start flag 0 Read: Write: 1 Read: Write: Transfer stops Transfer aborted and SCI2 initialized Transfer in progress, or CS input standby Transfer starts Abort flag 0 [Clear conditions] When 0 is written after reading 1 1 [Setting conditions] When CS pin output level becomes high during transfer Wait flag 0 [Clear conditions] When 0 is written after reading 1 1 [Setting conditions] When read/write instruction to serial data buffer (32-bit) is generated while transfer is in progress or during CS input standby Overrun error flag 0 [Clear conditions] When 0 is written after reading 1 1 [Setting conditions] When extra pulse is over-applied to correct transfer clock or clock input is generated after transfer end, when using external clock Extension data bit 0 Read: SO2 pin output level is low Write: SO2 pin output level is changed to low 1 Read: SO2 pin output level is high Write: SO2 pin output level is changed to high Transfer end interrupt request flag 0 [Clear conditions] When 0 is written after reading 1 1 [Setting conditions] When transmission or reception ends Note: * Only 0 can be written to clear the flag. Rev. 0.1, 11/98, page 889 of 975 H'D100: Timer Interrupt Enable Register ITER: Timer X1 Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE ICSA 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Input capture input select A bit 0 FTIA pin input is selected for input capture A input 1 HSW is selected for input capture A input Output compare interrupt enable bit 0 1 OCFC interrupt request (OCIC) is disabled OCFC interrupt request (OCIC) is enabled Output compare interrupt B enable bit 0 OCFB interrupt request (OCIB) is disabled 1 OCFB interrupt request (OCIB) is enabled Output compare interrupt A enable bit 0 OCFA interrupt request (OCIA) is disabled 1 OCFA interrupt request (OCIA) is enabled Input capture D interrupt enable bit 0 ICFD interrupt request (ICID) is disabled 1 ICFD interrupt request (ICID) is enabled Input capture C interrupt enable bit 0 ICFC interrupt request (ICIC) is disabled 1 ICFC interrupt request (ICIC) is enabled Input capture B interrupt enable bit 0 ICFB interrupt request (ICIB) is disabled 1 ICFB interrupt request (ICIB) is enabled Input capture A interrupt enable bit 0 ICFA interrupt request (ICIA) is disabled 1 ICFA interrupt request (ICIA) is enabled Rev. 0.1, 11/98, page 890 of 975 H'D101: Timer Control/Status Register X TCSRX: Timer X1 7 6 5 4 3 2 1 0 ICFA ICFB ICFC ICFD OCFA OCFB OVF CCLRA Bit : Initial value : R/W : 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/ W Counter clear 0 FRC clearing is disabled 1 FRC clearing is enabled Timer overflow 0 1 [Clearing conditions] When 0 is written to OVF after reading OVF = 1 [Setting conditions] When FRC changes from H'FFFF to H'0000 Output compare flag B 0 1 [Clearing conditions] When 0 is written to OCFB after reading OCFB = 1 [Setting conditions] When FRC = OCRB Output compare flag A 0 1 [Clearing conditions] When 0 is written to OCFA after reading OCFA = 1 [Setting conditions] When FRC = OCRA Input capture flag D 0 1 [Clearing conditions] When 0 is written to ICFD after reading ICFD = 1 [Setting conditions] When input capture signal is generated Input capture flag C 0 1 [Clearing conditions] When 0 is written to ICFC after reading ICFC = 1 [Setting conditions] When input capture signal is generated Input capture flag B 0 1 [Clearing conditions] When 0 is written to ICFB after reading ICFB = 1 [Setting conditions] When FRC value is transferred to ICRB by input capture signal Input capture flag A 0 1 [Clearing conditions] When 0 is written to ICFA after reading ICFA = 1 [Setting conditions] When FRC value is transferred to ICRA by input capture signal Note: * Only 0 can be written to bits 7 to 1 to clear the flags. Rev. 0.1, 11/98, page 891 of 975 H'D102: Free Running Counter H FRCH: Timer X1 H'D103: Free Running Counter L FRCL: Timer X1 FRC Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W FRCH FRCL H'D104: Output Compare Register AH, BH OCRAH, OCRBH: Timer X1 H'D105: Output Compare Register AL, BL OCRAL, OCRBL: Timer X1 OCRA, OCRB Bit : Initial value : R/W : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W OCRAH, OCRBH Rev. 0.1, 11/98, page 892 of 975 OCRAL, OCRBL H'D106: Timer Control Register X TCRX: Timer X1 Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Clock selct bit CKS1 CKS0 Clock select 0 0 Internal clock: count at /4 0 1 Internal clock: count at /16 1 0 Internal clock: count at /64 1 1 DVCFG: Edge detection p ulse selected by CFG frequency division timer Buffer enable B 0 ICRC is not used as buffer register for ICRB 1 ICRC is used as buffer register for ICRB Buffer enable A 0 ICRC is not used as buffer register for ICRA 1 ICRC is used as buffer register for ICRA Input capture edge select D 0 Capture at falling edge of input capture input D 1 Capture at rising edge of input capture input D Input capture edge select C 0 Capture at falling edge of input capture input C 1 Capture at rising edge of input capture input C Input capture edge select B 0 Capture at falling edge of input capture input B 1 Capture at rising edge of input capture input B Input capture edge select A 0 Capture at falling edge of input capture input A 1 Capture at rising edge of input capture input A Rev. 0.1, 11/98, page 893 of 975 H'D107: Timer Output Compare Control Register TOCR: Timer X1 Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 ICSB ICSC ICSD OSRS OEA OEB OLVLA OLVLB 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Output level B 0 Low level 1 High level Output level A 0 Low level 1 High level Output enable B 0 1 Output compare B output is disabled Output compare B output is enabled Output enable A 0 1 Output compare A output is disabled Output compare A output is enabled Output compare register select 0 OCRA register is selected 1 OCRB register is selected Input capture input select D 0 FTID pin is selected for input capture D input 1 NHSW is selected for input capture D input Input capture input select C 0 FTIC pin is selected for input capture C input 1 DVCTL is selected for input capture C input Input capture input select B 0 FTIB pin is selected for input capture B input 1 VD is selected for input capture B input Rev. 0.1, 11/98, page 894 of 975 H'D108: Input Capture Register AH ICRAH: Timer X1 H'D109: Input Capture Register AL ICRAL: Timer X1 H'D10A: Input Capture Register BH ICRBH: Timer X1 H'D10B: Input Capture Register BL ICRBL: Timer X1 H'D10C: Input Capture Register CH ICRCH: Timer X1 H'D10D: Input Capture Register CL ICRCL: Timer X1 H'D10E: Input Capture Register DH ICRDH: Timer X1 H'D10F: Input Capture Register DL ICRDL: Timer X1 ICRA, ICRB, ICRC, ICRD Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : R R R R R R R R R R R R R R R R ICRAH, ICRBH, ICRCH, ICRDH ICRAL, ICRBL, ICRCL, ICRDL Rev. 0.1, 11/98, page 895 of 975 H'D110: Timer Mode Register B TMB: Timer B Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 TMB17 TMBIF TMBIE -- -- TMB12 TMB11 TMB10 0 0 0 1 1 0 0 0 R/W -- -- R/W R/W R/W R/W R/(W)* Clock select bit Clock select TMB12 TMB11 TMB10 0 0 0 Internal clock: Count at /16384 0 0 1 Internal clock: Count at /4096 0 1 0 Internal clock: Count at /1024 0 1 1 Internal clock: Count at /512 1 0 0 Internal clock: Count at /128 1 0 1 Internal clock: Count at /32 1 1 0 Internal clock: Count at /8 1 1 1 Count at rising/falling edge of external event (TMBI) Note: * External event edge selection is set at PMR51 in port mode register 5 (PMR5). See section 12.2.4, Port Register 5 (PMR5). Timer B interrupt enable bit 0 Timer B interrupt request is disabled 1 Timer B interrupt request is enabled Timer B interrupt request flag 0 [Clearing conditions] When 0 is written after reading 1 1 [Setting conditions] When TCB overflows Auto reload function select bit 0 Interval function is selected 1 Auto reload function is selected Note: * Only 0 can be written to clear the flag. Rev. 0.1, 11/98, page 896 of 975 H'D111: Timer Counter B TCB: Timer B Bit : 7 6 5 4 3 2 1 0 TCB17 TCB16 TCB15 TCB14 TCB13 TCB12 TCB11 TCB10 Initial value : 0 0 0 0 0 0 0 0 R/W : R R R R R R R R H'D111: Timer Load RegisterB TLB: TimerB Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 TLB17 TLB16 TLB15 TLB14 TLB13 TLB12 TLB11 TLB10 0 0 0 0 0 0 0 0 W W W W W W W W Rev. 0.1, 11/98, page 897 of 975 H'D112: Timer L Mode Register LMR: Timer L Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 LMIF LMIE -- -- IMR3 IMR2 IMR1 IMR0 0 0 1 1 0 0 0 0 R/(W)* R/W -- -- R/W R/W R/W R/W Clock select bit R2 LMR1 LMR0 0 0 0 1 1 Count at falling edge of PB and REC-CTL 1 * Count DVCFG2 0 * Internal clock: Count at /128 1 * Internal clock: Count at /64 Note: * Don't care. Up/down count control 0 Up count control 1 Down count control Timer L interrupt enable bit 0 Timer L interrupt request is disabled 1 Timer L interrupt request is enabled Timer L interrupt request flag 0 [Clearing conditions] When 0 is written after reading 1 1 [Setting conditions] When LTC overflow, underflow or compare match clear occurs Note: * Only 0 can be written to clear the flag. Rev. 0.1, 11/98, page 898 of 975 Clock select Count at rising edge of PB and REC-CTL H'D113: Linear Time Counter LTC: Timer L Bit : 7 6 5 4 3 2 1 0 LTC7 LTC6 LTC5 LTC4 LTC3 LTC2 LTC1 LTC0 Initial value : 0 0 0 0 0 0 0 0 R/W : R R R R R R R R H'D113: Reload/Compare Match Register RCR: Timer L Bit : 7 6 5 4 3 2 1 0 RCR7 RCR6 RCR5 RCR4 RCR3 RCR2 RCR1 RCR0 Initial value : 0 0 0 0 0 0 0 0 R/W : W W W W W W W W Rev. 0.1, 11/98, page 899 of 975 H'D118: Timer R Mode Register 1 TMRM1: Timer R Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 CLR2 AC/BR RLD RLCK PS21 PS20 RLD/CAP CPS 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W TMRU-1 capture signal select bit 0 Capture signal at CFG rising edge 1 Capture signal at IRQ3 edge TMRU-1 operation mode select bit 0 TMRU-1 functions as reload timer 1 TMRU-1 functions as capture timer TMRU-2 clock source select bits PS21 PS20 0 0 Count at TMRU-1 underflow 1 PSS, count at /256 0 PSS, count at /128 PSS, count at /64 1 1 TMRU-2 clock source select TMRU-2 reload timing select bit 0 Reload at CFG rising edge 1 Reload at TMRU underflow Execution/non-execution of reload by TMRU-2 0 TMRU-2 is not used as reload timer 1 TMRU-2 is used as reload timer Acceleration/deceleration select bit 0 Deceleration 1 Acceleration TMRU-2 clear select bit 0 TMRU-2 is not cleard at the time of capture 1 TMRU-2 is cleard at the time of capture Rev. 0.1, 11/98, page 900 of 975 H'D119: Timer R Mode Register TMRM2: Timer R Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 LAT PS11 PS10 PS31 PS30 CP/SLM CAPF SLW 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/(W)* R/(W)* Slow tracking mono-multi flag 0 [Clearing conditions] When 0 is written after reading 1 1 [Setting conditions] When slow tracking mono-multi ends while CP/SLM bit = 1 Capture signal flag 0 [Clearing conditions] When 0 is written after reading 1 1 [Setting conditions] When TMRU-2 capture signal is generated while CP/SLM bit = 0 Interrupt select bit 0 Interrupt request by TMRU-2 capture signal is enabled 1 Interrupt request by slow tracking mono-multi end is enabled TMRU-3 clock source select bits PS31 PS30 0 0 1 TMRU-3 clock source select Count at rising edge of DVCTL from frequency divider 1 PSS, count at /4096 0 PSS, count at /2048 1 PSS, count at /1024 TMRU-1 clock source select bits PS11 PS10 0 0 Count at CFG rising edge 1 PSS, count at o/4 0 PSS, count at o/256 1 PSS, count at o/512 1 TMRU-1 clock source select TMRU-2 captrue signal select bits LAT CPS 0 * Capture at TMRU-3 underflow 1 0 Capture at CFG rising edge 1 Capture at IRQ3 edge TMRU-2 capture signal select Note: * Don't care. Note: * Only 0 can be written to clear the flag. Rev. 0.1, 11/98, page 901 of 975 H'D11A: Timer R Capture Register 1 TMRCP1: Time R Bit : 7 6 5 4 3 2 1 0 TMRC17 TMRC16 TMRC15 TMRC14 TMRC13 TMRC12 TMRC11 TMRC10 Initial value : 1 1 1 1 1 1 1 1 R/W : R R R R R R R R 2 1 0 H'D11B: Timer R Capture Register 2 TMRCP2: Time R Bit : 7 6 5 4 3 TMRC27 TMRC26 TMRC25 TMRC24 TMRC23 TMRC22 TMRC21 TMRC20 Initial value : 1 1 1 1 1 1 1 1 R/W : R R R R R R R R H'D11C: Timer R Load Register 1 TMRL1: Timer R 7 6 5 4 3 2 1 0 TMR17 TMR16 TMR15 TMR14 TMR13 TMR12 TMR11 TMR10 Initial value : 1 1 1 1 1 1 1 1 R/W : W W W W W W W W Bit : Rev. 0.1, 11/98, page 902 of 975 H'D11D: Timer R Load Register 2 TMRL2: Timer R Bit : 7 6 5 4 3 2 1 0 TMR27 TMR26 TMR25 TMR24 TMR23 TMR22 TMR21 TMR20 Initial value : 1 1 1 1 1 1 1 1 R/W : W W W W W W W W H'D11E: Timer R Load Register 3 TMRL3: Timer R Bit : 7 6 5 4 3 2 1 0 TMR37 TMR36 TMR35 TMR34 TMR33 TMR32 TMR31 TMR30 Initial value : 1 1 1 1 1 1 1 1 R/W : W W W W W W W W Rev. 0.1, 11/98, page 903 of 975 H'D11F: Timer R Control/Status Register TMRCS: Timer R Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 TMRI3E TMRI2E TMRI1E TMRI3 TMRI2 TMRI1 -- -- 0 0 0 0 0 0 1 1 R/W R/W R/W R/(W)* R/(W)* R/(W)* -- -- TMRI1 interrupt request flag 0 [Clearing conditions] When 0 is written after reading 1 1 [Setting conditions] When TMRU-1 underflows TMRI2 interrupt request flag 0 [Clearing conditions] When 0 is written after reading 1 1 [Setting conditions] When TMRU-2 underflows or when capstan motor acceleration/deceleration operation ends TMRI3 interrupt request flag 0 [Clearing conditions] When 0 is written after reading 1 1 [Setting conditions] When interrupt source selected at CP/SLM bit in TMRM2 is generated TMRI1 interrupt enable bit 0 TMRI1 interrupt request is disabled 1 TMRI1 interrupt request is enabled TMRI2 interrupt enable bit 0 TMRI2 interrupt request is disabled 1 TMRI2 interrupt request is enabled TMRI3 interrupt enable bit 0 TMRI3 interrupt request is disabled 1 TMRI3 interrupt request is enabled Note: * Only 0 can be written to clear the flag. Rev. 0.1, 11/98, page 904 of 975 H'D120: PWM Data Register L PWDRL: 14-Bit PWM Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W H'D121: PWM Data Register U PWDRU: 14-Bit PWM Bit : 7 -- 6 -- Initial value : R/W : 1 -- 1 -- 5 4 3 2 1 0 PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0 0 W 0 W 0 W 0 W 0 W 0 W Rev. 0.1, 11/98, page 905 of 975 H'D122: PWM Control Register PWCR: 14-Bit PWM Bit : 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 PWCR0 Initial value : R/W : 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 0 R/W Clock select bit 0 1 Input clock is /2 (t = 2/) Generate PWM waveform with conversion frequency of 16384/ and minimum pulse width of 1/ Input clock is /4 (t = 4/) Generate PWM waveform with conversion frequency of 32768/ and minimum pulse width of 2/ Note: * t: PWM input clock frequency H'D126: 8-Bit PWM Data Register 0 PWR0: 8-Bit PWM Bit : Initial value : R/W : 7 PW07 6 PW06 5 PW05 4 PW04 3 PW03 2 PW02 1 PW01 0 PW00 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Rev. 0.1, 11/98, page 906 of 975 H'D127: 8-Bit PWM Data Register 1 PWR1: 8-Bit PWM Bit : Initial value : R/W : 7 PW17 6 PW16 5 PW15 4 PW14 3 PW13 2 PW12 1 PW11 0 PW10 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W H'D128: 8-Bit PWM Data Register 2 PWR2: 8-Bit PWM Bit : Initial value : R/W : 7 PW27 6 PW26 5 PW25 4 PW24 3 PW23 2 PW22 1 PW21 0 PW20 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W H'D129: 8-Bit PWM Data Register 3 PWR3: 8-Bit PWM Bit : Initial value : R/W : 7 PW37 6 PW36 5 PW35 4 PW34 3 PW33 2 PW32 1 PW31 0 PW30 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Rev. 0.1, 11/98, page 907 of 975 H'D12A: 8-Bit PWM Control Register PW8CR: 8-Bit PWM Bit : 7 -- 6 -- 5 -- 4 -- 3 PWC3 2 PWC2 1 PWC1 0 PWC0 Initial value : R/W : 1 -- 1 -- 1 -- 1 -- 0 R/W 0 R/W 0 R/W 0 R/W Output polarity select bits 0 Positive polarity 1 Negative polarity (n = 3 to 0) H'D12C: Input Capture Register 1 ICR1: PSU Bit : Initial value : R/W : 7 ICR17 6 ICR16 5 ICR15 4 ICR14 3 ICR13 2 ICR12 1 ICR11 0 ICR10 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Rev. 0.1, 11/98, page 908 of 975 H'D12D: Prescaler Unit Control/Status Register PCSR: PSU Bit : Initial value : R/W : 7 ICIF 6 ICIE 5 ICEG 4 NCon/off 3 -- 2 DCS2 1 DCS1 0 DCS0 0 R/(W)* 0 R/W 0 R/W 0 R/W 1 -- 0 R/W 0 R/W 0 R/W Frequency division clock output select bits Frequency division clodk output select PSS, output /32 DCS2 DCS1 DCS0 0 0 0 1 PSS, output /16 1 0 PSS, output /8 1 PSS, output /4 0 0 PSW, output W/32 1 PSW, output W/16 1 0 PSW, output W/8 1 PSW, output W/4 1 Noise cancel ON/OFF bit 0 Noise cancel function of IC pin is disabled 1 Noise cancel function of IC pin is enabled IC pin edge select bit 0 Falling edge of IC pin input is detected 1 Rising edge of IC pin input is detected Input capture interrupt enable bit 0 Interrupt request by input capture is disabled 1 Interrupt request by input capture is enabled Input capture interrupt flag 0 [Clearing conditions] When 0 is written after reading 1 1 [Setting conditions] When input capture is executed at IC pin edge Note: * Only 0 can be written to clear the flag. Rev. 0.1, 11/98, page 909 of 975 H'D130: Software Trigger A/D Result Register H ADRH: A/D Converter H'D131: Software Trigger A/D Result Register L ADRL: A/D Converter ADRH Bit : 15 14 13 12 11 ADRL 10 9 8 7 6 ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 Initial value : R/W : 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R 5 -- 4 -- 3 -- 2 -- 1 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- H'D132: Hardware Trigger A/D Result Register H AHRH: A/D Converter H'D133: Hardware Trigger A/D Result Register L AHRL: A/D Converter AHRH Bit : 15 14 13 12 11 AHRL 10 9 8 7 6 AHR9 AHR8 AHR7 AHR6 AHR5 AHR4 AHR3 AHR2 AHR1 AHR0 Initial value : R/W : 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R Rev. 0.1, 11/98, page 910 of 975 5 -- 4 -- 3 -- 2 -- 1 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- H'D134: A/D Control Register ADCR: A/D Converter Bit : Initial value : R/W : 7 CK -- 6 5 HCH1 4 HCH0 3 SCH3 2 SCH2 1 SCH1 0 SCH0 0 R/W 1 -- 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Software channel select bits SCH3 SCH2 SCH1 SCH0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 * * Analog input channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 ANA ANB Software-triggered conversion channel is not selected Notes: 1. If conversion is started by software when SCH3 to SCH0 are set to 11xx, the conversion result is undetermined. Hardware- or external-triggered conversion, however, will be performed on the channel selected by HCH1 and HCH0. 2. * Don't care. Hardware channel select bits HCH1 HCH2 Analog input channel 0 0 AN8 1 AN9 1 0 ANA 1 ANB Clock select 0 Conversion frequency = 266 states 1 Conversion frequency = 134 states Rev. 0.1, 11/98, page 911 of 975 H'D135: A/D Control/Status Register ADCSR: A/D Converter Bit : 7 SEND 6 HEND 5 ADIE 4 SST 3 HST 2 BUSY 1 SCNL 0 -- Initial value : R/W : 0 R/(W)* 0 R//(W)* 0 R/W 0 R/W 0 R 0 R 0 R 1 -- Software-triggered A/D conversion cancel flag 0 No contention for A/D conversion 1 Indicates that software-triggered A/D conversion was canceled by the start of hardware-triggered A/D conversion. Busy flag 0 No contention for A/D conversion 1 Indicates an attempt to execute software-triggerd A/D conversion was canceled by the start of hardwaretriggered A/D conversion. Hardware A/D status flag 0 Read: Hardware- or external -triggered A/D conversion is not in progress Write: Hardware- or external-triggered A/D conversion is aborted 1 Hardware- or external-triggered A/D conversion has ended or been stopped Software A/D start flag 0 Read: Indicates that software-triggered A/D conversion has ended or been stopped Write: Software-triggered A/D conversion is aborted 1 Read: Indicates that software-triggered A/D conversion is in progress Write: Starts software-triggered A/D conversion A/D interrupt enable bit 0 Interrupt (ADI) upon A/D conversion end is disabled 1 Interrupt (ADI) upon A/D conversion end is enabled Hardware A/D end flag 0 [Clearing conditions] When 0 is written after reading 1 1 [Setting conditions] When hardware- or external-triggered A/D conversion has ended Software A/D end flag 0 [Clearing conditions] When 0 is written after reading 1 1 [Setting conditions] When software-triggered A/D conversion has ended Note: * Only 0 can be written to clear the flag. Rev. 0.1, 11/98, page 912 of 975 H'D136: A/D Trigger Select Register ADTSR: A/D Converter Bit : 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 TRGS1 0 TRGS0 Initial value : R/W : 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 0 R/W 0 R/W Trigger select bits TRGS1 TRGS0 0 0 Hardware- or external-triggered A/D conversion is disabled 1 Hardware-triggered (ADTRG) A/D conversion is selected 1 0 Hardware-triggered (DFG) A/D conversion is selected 1 External-triggered (ADTRG) A/D conversion is selected Rev. 0.1, 11/98, page 913 of 975 H'D138: Timer Load Register K TLK: Timer J Bit : 7 6 5 4 3 2 1 0 TLR27 TLR26 TLR25 TLR24 TLR23 TLR22 TLR21 TLR20 Initial value : 1 1 1 1 1 1 1 1 R/W : W W W W W W W W H'D138: Timer Counter K TCK: Timer J Bit : 7 6 5 4 3 2 1 0 TDR27 TDR26 TDR25 TDR24 TDR23 TDR22 TDR21 TDR20 Initial value : 1 1 1 1 1 1 1 1 R/W : R R R R R R R R H'D139: Timer Load Register J TLJ: Timer J Bit : 7 6 5 4 3 2 1 0 TLR17 TLR16 TLR15 TLR14 TLR13 TLR12 TLR11 TLR10 Initial value : 1 1 1 1 1 1 1 1 R/W : W W W W W W W W H'D139: Timer Counter J TCJ: Timer J Bit : 7 6 5 4 3 2 1 0 TDR17 TDR16 TDR15 TDR14 TDR13 TDR12 TDR11 TDR10 Initial value : 1 1 1 1 1 1 1 1 R/W : R R R R R R R R Rev. 0.1, 11/98, page 914 of 975 H'D13A: Timer Mode Register J TMJ: Timer J Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PS11 PS10 ST 8/16 PS21 PS20 TGL T/R 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R R/W Timer output/remote-controller output select bit TMJ-1 timer output 0 1 TMJ-1 toggle output (data transmitted from remote controller) TMJ-2 toggle flag 0 TMJ-2 toggle output is 0 1 TMJ-2 input clock select bits PS21 PS20 0 0 1 TMJ-2 toggle output is 1 TMJ-2 input clock select PSS, count at /16384 1 PSS, count at /2048 0 Count at TMJ-1 underflow 1 Count at rising/falling edge of external clock (IRQ2) * Note: * External clock edge selection is set in edge select register (IEGR). See section explaining edge select register (IEGR). 8-bit/16-bit operation select bit 0 TMJ-1 and TMJ-2 operate separately 1 TMJ-1 and TMJ-2 operate together as 16-bit Remote-controlled operation start bit 0 Stop TMJ-1 clock supply in remote control mode 1 Start TMJ-1 clock supply in remote control mode TMJ-1 input clock select bits PS11 PS10 0 0 1 TMJ-1 input clock select PSS, count at /512 1 PSS, count at /256 0 PSS, count at /4 1 Count at rising/falling edge of external clock (IRQ1) Note: * External clock edge selection is set in edge select register (IEGR). See section explaining edge select register (IEGR). When using external clock in remote control mode, set opposite edges for IRQ1 and IRQ2 edges (eg. When falling edge is set for IRQ1, set rising edge for IRQ2). Rev. 0.1, 11/98, page 915 of 975 H'D13B: Timer J Control Register TMJC: Timer J Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 BUZZ1 BUZZ0 MON1 MON0 -- TMJ2IE TMJ1IE -- 0 0 0 0 1 0 0 1 R/W R/W R/W R/W -- R/W R/W -- TMJ1I interrupt enable bit 0 TMJ1I interrupt request is disabled 1 TMJ1I interrupt request is enabled TMJ2I interrupt enable bit 0 TMJ2I interrupt request is disabled 1 TMJ2I interrupt request is enabled Monitor output select bits MON1 MON0 0 0 PB or REC-CTL 1 DVCTL * Output TCA7 1 Monitor output select Note: * Don't care. Buzzer output select bits BUZZ0 0 0 /4096 1 /8192 0 Output monitor signal 1 Output Timer J BUZZ signal 1 Output signal Frequency when = 10 MHz BUZZ1 Rev. 0.1, 11/98, page 916 of 975 2.44 kHz 1.22 kHz H'D13C: Timer J Status Register TMJS: Timer J Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 TMJ2I TMJ1I -- -- -- -- -- -- 0 0 1 1 1 1 1 1 R/(W)* R/(W)* -- -- -- -- -- -- TMJ1I interrupt request flag 0 [Clearing conditions] When 0 is written after reading 1 1 [Setting conditions] When TMJ-1 underflows TMJ2I interrupt request flag 0 [Clearing conditions] When 0 is written after reading 1 1 [Setting conditions] When TMJ-2 underflows Note: * Only 0 can be written to clear the flag. Rev. 0.1, 11/98, page 917 of 975 H'D148: Serial Mode Register SMR1: SCI1 Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Clock select CKS1 CKS0 0 0 clock 1 /4 clock 0 /16 clock 1 /64 clock 1 Clock select Multiprocessor mode 0 Multiprocessor function is disabled 1 Multiprocessor format is selected Stop bit length 0 Stop bit*1 1 Stop bit*2 Notes: 1. In transmission, a single 1 bit (stop bit) is added to the end of a transmit character before it is sent. 2. In transmission, two 1 bits (stop bits) are added to the end of a transmit character before it is sent. Parity mode 0 Even parity*1 1 Odd parity*2 Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. Parity enable 0 Parity bit addition and checking disabled 1 Parity bit addition and checking enabled* Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. Character length 0 8-bit data 1 7-bit data Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and LSB-first/MSB-first selection is not available. Communication mode 0 Start-stop synchronous mode 1 Clock synchronouns mode Rev. 0.1, 11/98, page 918 of 975 H'D149: Bit Rate Register BRR1: SCI1 Bit : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W : Rev. 0.1, 11/98, page 919 of 975 H'D14A: Serial Control Register SCR1: SCI1 Bit : 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : R/W : Clock enable bits CKE1 CKE0 0 0 1 1 0 1 Clock select Start-stop synchronous mode Internal clock/SCK pin function as I/O port*1 Clock synchronous mode Internal clock/SCK pin function as serial clock output *1 Start-stop synchronous mode Internal clock/SCK pin function as clock output*2 Clock synchronous mode Internal clock/SCK pin function as serial clock output Start-stop synchronous mode External clock/SCK pin function as clock input*3 Clock synchronous mode External clock/SCK pin function as serial clock input Start-stop synchronous mode External clock/SCK pin function as clock input*3 Clock synchronous mode External clock/SCK pin function as serial clock input Notes: 1. Initial value 2. Outputs a clock of the same frequency as the bit rate. 3. Inputs a clock with a frequency 16 times the bit rate. Transmit end interrupt enable bit 0 Transmit-end interrupt (TEI) request is disabled* 1 Transmit-end interrupt (TEI) request is enabled* Note: * TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0. Multiprocessor interrupt enable bit 0 Multiprocessor interrupts are disabled (normal reception performed) [Clearing conditions] (1) When the MPIE bit is cleared to 0 (2) When data with MPB = 1 is received 1 Multiprocessor interrupt are enabled* Receive interrupt (RXI) requests, receive-error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received. Note: * When receive data including MPB = 0 is reveived, receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR, is not performed. When receive data with MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled. Receive enable bit 0 Reception is disabled*1 1 Reception is enabled*2 Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. 2. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. SMR setting must be performed to decide the reception format before setting the RE bit to 1. Transmit enable bit 0 Transmission is disabled*1 1 Transmission is enabled*2 Notes: 1. The TDRE flag in SSR is fixed at 1. 2. In this state, serial transmission is started when transmit data is written to TDR and TDRE flag in SSR is cleared to 0. SMR setting must be performed to decide the transmission format before setting the TE bit to 1. Receive interrupt enable bit 0 Reveive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request is disabled* 1 Reveive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request is enabled Note: * RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF, FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to 0. Transmit interrupt enable bit 0 Transmit-data-empty interrupt (TXI) request is disabled* 1 Transmit-data-empty interrupt (TXI) request is enabled Note: * TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or clearing the TIE bit to 0. Rev. 0.1, 11/98, page 920 of 975 H'D14B: Transmit Data Register TDR1: SCI1 Bit : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W : Rev. 0.1, 11/98, page 921 of 975 H'D14C: Serial Status Register SSR1: SCI1 Bit : 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT 1 0 0 0 0 1 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Initial value : R/W : Multiprocessor bit transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor bit 0 [Clearing conditions]* When data with a 0 multiprocessor bit is received 1 [Setting conditions] When data with a 1 multiprocessor bit is reveived Note: * Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor format. Transmit end 0 [Clearing conditions] (1) When 0 is written in TDRE after reading TDRE = 1 1 [Setting conditions] (1) When the TE bit in SCR is 0 (2) When TDRE = 1 at trasmission of the last bit of a 1-byte serial transmit character Parity error 0 [Clearing conditions]*1 When 0 is written in PER after reading PER = 1 1 [Setting conditions] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR *2 Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In synchronous mode, serial transmission cannot be continued, either. Framing error 0 [Clearing conditions]*1 When 0 is written in FER after reading FER = 1 1 [Setting conditions] When the SCI checks the stop bit at the end of the receive data when reception ends, and the stop bit is 0.*2 Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the FER flag is set to 1. In synchronous mode, serial transmission cannot be continued, either. Overrun errro 0 [Clearing conditions]*1 When 0 is written in ORER after reading ORER = 1 1 [Setting conditions] When the next serial reception is completed while RDRF = 1 *2 Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1. In synchronous mode, serial transmission cannot be continued, either. Receive data register full 0 [Clearing conditions] When 0 is written in RDRF after reading RDRF = 1 1 [Setting conditions] When serial reception ends normally adn receive data is transferred from RSR to RDR Note: RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCR is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost. Transmit data register empty 0 [Clearing conditions] (1) When 0 is written in TDRE after reading TDRE = 1 (2) When the DTC is activated by a TXI interrupt and writes data to TDR 1 [Setting conditions] (1) When the TE bit in SCR is 0 (2) When data is transferred from TDR to TSR and data can be written to TDR Note: * Only 0 can be written to clear the flag. Rev. 0.1, 11/98, page 922 of 975 H'D14D: Receive Data Register RDR1: SCI1 Bit : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 R/W : R R R R R R R R H'D14E: Serial Interface Mode Register SCMR1: SCI1 Bit : 7 6 5 4 3 2 1 0 -- -- -- -- SDIR SINV -- SMIF Initial value : 1 1 1 1 0 0 1 0 R/W : -- -- -- -- R/W R/W -- R/W Serial communication inteface mode select 0 Normal SCI mode 1 Reserved mode Data invert 0 1 TDR contents are transmitted without modification Receive data is stored in RDR without modification TDR contents are onverted before being transmitted Receive data is stored in RDR in inverted form Data transfer direction 0 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first 1 TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first Rev. 0.1, 11/98, page 923 of 975 2 H'D158: I C Bus Control Register ICCR: IIC Bus Interface Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 ICE IEIC MST TRS ACKE BBSY IRIC SCP 0 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/(W)* W Start condition/stop condition prohibit 0 Writing 0 issues a start or stop condition, in combination with the BBSY flag 1 Reading always returns a value of 1 Writing is ignored I2C bus interface interrupt request flag 0 1 Waiting for transfer, or transfer in progress [Clearing conditions] (1) When 0 is written in IRIC after reading IRIC = 1 Interrupt requested [Setting conditions] 2 I C bus format master mode (1) When a start condition is detected in the bus line state after a start condition is issued (when the TDRE flag is set to 1 because of first frame transmission) (2) When a wait is inserted between the data and acknowledge bit when WAIT = 1 (3) At the end of data transfer (when the TDRE or RDRF flag is set to 1) (4) When a slave address is received after bus arbitration is lost (when the AL flag is set to 1) (5) When 1 is reveived as teh acknowledge bit when the ACKE bit is 1 (when the ACKB bit is set to 1) 2 I C bus format slave mode (1) When the slave address (SVA, SVAX) matches (when the AAS and AASX flags are set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the TDRE or RDRF flag is set to 1) (2) When the general call address is detected (when the ADZ flag is set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the TDRE or RDRF flag is set to 1) (3) When 1 is received as the acknowledge bit when the ACKE bit is 1 (when the ACKB bit is set to 1) (4) When a stop condition is detected (when the STOP or ESTP flag is set to 1) Synchronous serial format (1) At the end of data transfer (when the TDRE or RDRF flag is set to 1) (2) When a start condition is detected with serial format selected Bus busy 0 Bus is free [Clearing conditions] 1 Bus is busy [Setting conditions] When a stop condition is detected When a start condition is detected Acknowledge bit judgment selection 0 The value of the acknowledge bit is ignored, and continuous transfer is performed 1 If the acknowledge bit is 1, continuous transfer is interrupted Master/slave select Transmit/receive select MST 0 1 TRS 0 1 0 1 Slave reveive mode Slave transmit mode Master receive mode Master transmit mode I2C bus interface interrupt enable 0 Interrupt request is disabled 1 Interrupt request is enabled I2C bus interface enable 0 I2C bus interface module disabled, with SCL and SDA signal pins set to port function SAR and SARX can be accessed 2 1 I C bus interface module enabled for transfer operation (pins SCL and SCA are driving the bus) Note: * Only 0 can be written to clear the falg. Rev. 0.1, 11/98, page 924 of 975 2 H'D159: I C Bus Status Register ICSR: IIC Bus Interface Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 ESTP STOP IRTR AASX AL AAS ADZ ACKB 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/W Acknowledge bit 0 Receive mode: 0 is output at acknowledge output timing Transmit mode: Indicates that the receiving device has acknowldeged the data (signal is 0) 1 Receive mode; 1 is output at acknowledge output timing Transmit mode: Indicates that the receiving device has not acknowldeged the data (signal is 1) General call address recognition flag 0 General call address not recognized [Clearing conditions] (1) When ICDR data is written (transmit mode) or read (receive mode) (2) When 0 is written in ADZ after reading ADZ = 1 (3) In master mode 1 General call address recognized [Setting conditions] * When the general call address is detected in slave receive mode Slave address recognition flag 0 Slave address or general call address not recognized [Clearing conditions] (1) When ICDR data is written (transmit mode) or read (receive mode) (2) When 0 is written in AAS after reading AAS = 1 (3) In master mode 1 Slave address or general call address recognized [Setting conditions] * When the slave address or general call address is detected in slave receive mode Arbitration lost flag 0 Bus arbitration won [Clearing conditions] (1) When ICDR data is written (transmit mode) or read (receive mode) (2) When 0 is written in AL after reading AL = 1 1 Arbitration lost [Setting conditions] (1) If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode (2) If the internal SCL line is high at the fall of SCL in master transmit mode Second slave address recognition flag 0 Second slave address not recognized [Clearing conditions] (1) When 0 is written in AASX after reading AASX = 1 (2) When a start condition is detected (3) In master mode 1 Second slave address recognized [Setting conditions] * When the second slave address is detected in slave receive mode I2C bus interface continuous transmission/reception interrupt request flag 0 Waiting for transfer, or transfer in progress [Clearing conditions] (1) When 0 is written in IRTR after reading IRTR = 1 (2) When the IRIC flag is cleared to 0 1 Continuous transfer state [Setting conditions] In I2C bus interface slave mode * When the TDRE or RDRF flag is set to 1 when AASX = 1 In other mode * When the TDRE or RDRF flag is set to 1 Normal stop condition detection flag 0 No normal stop condition [Clearing conditions] (1) When 0 is written in STOP after reading STOP = 1 (2) When the IRIC flag is cleared to 0 2 1 In I C bus format slave mode Normal stop condition detected [Setting conditions] * When a stop condition is detected after completion of frame transfer In other mode No meaning Error stop condition detection flage 0 No error stop condition [Clearing conditions] (1) When 0 is written in ESTP after reading ESTP = 1 (2) When the IRIC flag is cleared to 0 2 1 In I C bus format slave mode Error stop condition detected [Setting conditions] * When a stop condition is detected during frame transfer In other mode No meaning Note: * Only 0 can be written to clear the flag. Rev. 0.1, 11/98, page 925 of 975 2 H'D15E: I C Bus Data Register ICDR: IIC Bus Interface 7 6 5 4 3 2 1 0 ICDR7 ICDR6 ICDR5 ICDR4 ICDR3 ICDR2 ICDR1 ICDR0 -- -- -- -- -- -- -- -- R/W R/W R/W R/W R/W R/W R/W R/W Bit : Initial value : R/W : H'D15E: Second Slave Address Register SARX: IIC Bus Interface Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 FSX 0 0 0 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W R/W Format select Used combined with SAR FS bit. Rev. 0.1, 11/98, page 926 of 975 2 H'D15F: I C Bus Mode Register ICMR: IIC Bus Interface Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 MLS WAIT CKS2 CKS1 CKS0 BC2 BC1 BC0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit counter BC2 BC1 BC0 0 0 1 0 0 1 0 1 0 1 0 1 0 1 Transfer clock select bits IICX* CKS2 CKS1 CKS0 Clock 0 0 0 1 1 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 /28 /40 /48 /64 /80 /100 /112 /128 /56 /80 /96 /128 /160 /200 /224 /256 Bit/frame Clock sync I2C bus format serial format 8 1 2 3 4 5 6 7 9 2 3 4 5 6 7 8 Transfer rate =5 MHz =8 MHz =10 MHz 179 kHz 286 kHz 357 kHz 125 kHz 200 kHz 250 kHz 104 kHz 167 kHz 208 kHz 78.1 kHz 125 kHz 156 kHz 62.5 kHz 100 kHz 125 kHz 50.0 kHz 80.0 kHz 100 kHz 44.6 kHz 71.4 kHz 89.3 kHz 39.1 kHz 62.5 kHz 78.1 kHz 89.3 kHz 143 kHz 179 kHz 62.5 kHz 100 kHz 125 kHz 52.1 kHz 83.3 kHz 104 kHz 39.1 kHz 62.5 kHz 78.1 kHz 31.3 kHz 50.0 kHz 62.5 kHz 25.0 kHz 40.0 kHz 50.0 kHz 22.3 kHz 35.7 kHz 44.6 kHz 19.5 kHz 31.3 kHz 39.1 kHz Wait insertion bit 0 Data and acknowledge bits transferred consecutively 1 Wait inserted between data and acknowledge bits MSB-first/LSB-first select 0 MSB-first 1 LSB-first Note: * See STCR Bit 6. Rev. 0.1, 11/98, page 927 of 975 H'D15F: Slave Address Register SAR: IIC Bus Interface Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Format select bit SAR SARX Bit 0 Bit 0 FS FX 0 0 1 1 0 1 Rev. 0.1, 11/98, page 928 of 975 Format select 2 I C bus format * SAR and SARX slave addresses recognized 2 I C bus format * SAR slave address recognized * SARX slave address ignored I2C bus format * SAR slave address ignored * SARX slave address recognized 2 I C bus format * SAR and SARX slave addresses ignored H'FFB0: Trap Address Register 0 TAR0: ATC H'FFB1: Trap Address Register 0 TAR0: ATC H'FFB2: Trap Address Register 0 TAR0: ATC H'FFB3: Trap Address Register 1 TAR1: ATC H'FFB4: Trap Address Register 1 TAR1: ATC H'FFB5: Trap Address Register 1 TAR1: ATC H'FFB6: Trap Address Register 2 TAR2: ATC H'FFB7: Trap Address Register 2 TAR2: ATC H'FFB8: Trap Address Register 2 TAR2: ATC Bit : Initial value : R/W : Bit : Initial value : R/W : Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 A23 A22 A21 A20 A19 A18 A17 A16 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 A15 A14 A13 A12 A11 A10 A9 A8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 A7 A6 A5 A4 A3 A2 A1 -- 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W -- Rev. 0.1, 11/98, page 929 of 975 H'FFB9: Address Trap Control Register ATCR: ATC Bit : 7 6 5 4 3 2 1 0 -- -- -- -- -- TRC2 TRC1 TRC0 Initial value : 1 1 1 1 1 0 0 0 R/W : -- -- -- -- -- R/W R/W R/W Trap control 0 0 Address trap function 0 is disabled 1 Address trap function 0 is enabled Trap control 1 0 Address trap function 1 is disabled 1 Address trap function 1 is enabled Trap control 2 0 Address trap function 2 is disabled 1 Address trap function 2 is enabled Rev. 0.1, 11/98, page 930 of 975 H'FFBA: Timer Mode Register A TMA: Timer A Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 TMAOV TMAIE -- -- TMA3 TMA2 TMA1 TMA0 0 0 1 1 0 0 0 0 R/(W)* R/W -- -- R/W R/W R/W R/W Clock select bits TMA3 TMA2 TMA1 TMA0 0 0 0 1 1 0 1 1 0 0 1 1 0 Prescaler frequency division rate (interval timer) Operation mode or overflow frequency (time-base) 0 PSS, /16384 1 PSS, /8192 0 PSS, /4096 1 PSS, /1024 0 PSS, /512 1 PSS, /256 0 PSS, /64 1 PSS, /16 0 1s 1 0.5 s 0 0.25 s 1 0.03125 s 0 Clear PSW and TCA to H'00 Interval timer mode Clock time base mode 1 1 0 1 Note: = f osc Clock source, prescaler select bit 0 Timer A clock source is PSS 1 Timer A clock source is PSW Timer A interrupt enable bit 0 Interrupt request by Timer A (TMAI) is disabled 1 Interrupt request by Timer A (TMAI) is enabled Timer A overflow flag 0 [Clearing conditions] When 0 is written to TMAOV after reading TMAOV = 1 1 [Setting conditions] When TCA overflows Note: * Only 0 can be written to clear the flag. Rev. 0.1, 11/98, page 931 of 975 H'FFBB: Timer Counter A TCA: TimerA Bit : 7 6 5 4 3 2 1 0 TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 Initial value : 0 0 0 0 0 0 0 0 R/W : R R R R R R R R H'FFBC: Watchdog Timer Control/Status Register WTCSR: WDT Bit : Initial value : R/W : 7 6 5 OVF WT/IT TME 0 0 0 0 0 R/(W)* R/W R/W R/W R/W 4 3 RSTS RST/NMI 2 1 0 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Reset or NMI 0 NMI interrupt request is disabled 1 Internal reset request is generated Timer enable bit 0 WTCNT is initialized to H'00 and halted 1 WTCNT counts Timer mode select bit 0 Interval timer mode: Sends the CPU an interval timer interrupt request (WOVI) when WTCNT overflows 1 Watchdog timer mode: Sends the CPU a reset or NMI interrupt request when WTCNT overflows Overflow flag 0 [Clearing conditions] (1) Write 0 in the TME bit (2) Read WTCSR when OVF = 1, then write 0 in OVF 1 [Setting conditions] When WTCNT overflows (changes from H'FF to H'00) (When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset.) Note: * Only 0 can be written to clear the flag. Rev. 0.1, 11/98, page 932 of 975 H'FFBD: Watchdog Timer Counter WTCNT: WDT Bit : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W : H'FFC0: Port Data Register 0 PDR0: I/O Port Bit : Initial value : R/W : 7 PDR07 6 PDR06 5 PDR05 4 PDR04 3 PDR03 2 PDR02 1 PDR01 0 PDR00 -- R -- R -- R -- R -- R -- R -- R -- R H'FFC1: Port Data Register 1 PDR1: I/O Port Bit : Initial value : R/W : 7 PDR17 6 PDR16 5 PDR15 4 PDR14 3 PDR13 2 PDR12 1 PDR11 0 PDR10 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W H'FFC2: Port Data Register 2 PDR2: I/O Port Bit : Initial value : R/W : 7 PDR27 6 PDR26 5 PDR25 4 PDR24 3 PDR23 2 PDR22 1 PDR21 0 PDR20 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W H'FFC3: Port Data Register 3 PDR3: I/O Port Bit : Initial value : R/W : 7 PDR37 6 PDR36 5 PDR35 4 PDR34 3 PDR33 2 PDR32 1 PDR31 0 PDR30 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 0.1, 11/98, page 933 of 975 H'FFC4: Port Data Register 4 PDR4: I/O Port Bit : Initial value : R/W : 7 PDR47 6 PDR46 5 PDR45 4 PDR44 3 PDR43 2 PDR42 1 PDR41 0 PDR40 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W H'FFC5: Port Data Register 5 PDR5: I/O Port Bit : 7 -- 6 -- 5 -- 4 -- 3 PDR53 2 PDR52 1 PDR51 0 PDR50 Initial value : R/W : 1 -- 1 -- 1 -- 1 -- 0 R/W 0 R/W 0 R/W 0 R/W H'FFC6: Port Data Register 6 PDR6: I/O Port Bit : Initial value : R/W : 7 PDR67 6 PDR66 5 PDR65 4 PDR64 3 PDR63 2 PDR62 1 PDR61 0 PDR60 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W H'FFC7: Port Data Register 7 PDR7: I/O Port Bit : Initial value : R/W : 7 PDR77 6 PDR76 5 PDR75 4 PDR74 3 PDR73 2 PDR72 1 PDR71 0 PDR70 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W H'FFC8: Port Data Register 8 PDR8: I/O Port Bit : Initial value : R/W : 7 PDR87 6 PDR86 5 PDR85 4 PDR84 3 PDR83 2 PDR82 1 PDR81 0 PDR80 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Rev. 0.1, 11/98, page 934 of 975 H'FFCD: Port Mode Register 0 PMR0: I/O Port Bit : Initial value : R/W : 7 PMR07 6 PMR06 5 PMR05 4 PMR04 3 PMR03 2 PMR02 1 PMR01 0 PMR00 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W P07/AN7 to P00/IRQ0 rin function select bits 0 P0n/ANn pin functions as P0n input port 1 P0n/ANn pin functions as ANn input port (n = 7 to 0) H'FFCE: Port Mode Register 1 PMR1: I/O Port Bit : Initial value : R/W : 7 PMR17 6 PMR16 5 PMR15 4 PMR14 3 PMR13 2 PMR12 1 PMR11 0 PMR10 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W P15/IRQ5 to P10/IRQ0 pin function select bits 0 P1n/IRQn pin functions as P1n I/O port 1 P1n/IRQn pin functions as IRQn input port (n = 5 to 0) P16/IC pin function select bit 0 P16/IC pin functions as P16 I/O port 1 P16/IC pin functions as IC input port P17/TMOW pin function select bit 0 P17/TMOW pin functions as P17 I/O port 1 P17/TMOW pin functions as TMOW output port Rev. 0.1, 11/98, page 935 of 975 H'FFCF: Port Mode Register 2 PMR2: I/O Port Bit : Initial value : R/W : 7 PMR27 6 PMR26 5 PMR25 4 -- 3 -- 2 -- 1 -- 0 PMR20 0 R/W 0 R/W 0 R/W 1 -- 1 -- 1 -- 1 -- 0 R/W P26/SO2 pin PMOS control bit 0 P26/SO2 pin functions as CMOS output 1 P26/SO2 pin functions as NMOS open drain output P25/SI2 pin function select bit 0 P25/SI2 pin functions as P25 I/O port 1 P25/SI2 pin functions as S12 input port P26/SO2 pin function select bit 0 P26/SO2 pin functions as P26 I/O port 1 P26/SO2 pin functions as SO2 output port P27/SCK2 pin function select bit 0 P27/SCK2 pin functions as P27 I/O port 1 P27/SCK2 pin functions as SCK2 I/O port H'FFD0: Port Mode Register 3 PMR3: I/O Port Bit : Initial value : R/W : 7 PMR37 6 PMR36 5 PMR35 4 PMR34 3 PMR33 2 PMR32 1 PMR31 0 PMR30 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W P30/CS pin function select bit 0 P30/CS pin functions as P30 I/o port 1 P30/CS pin functions as CS input port P31/STRB pin function select bit 0 P31/STRB pin functions as P31 I/O port 1 P31/STRB pin functions as STRB output port P35/PWM3 to P32/PWM0 pin function select bit 0 P3n/PWMm pin functions as P3n I/O port 1 P3n/PWMm pin functions as PWMm output port P36/BUZZ pin function select bit 0 P36/BUZZ pin functions as P36 I/O port 1 P36/BUZZ pin functions as BUZZ output port (n = 5 to 2, m = 3 to 0) P37/TMO pin function select bit 0 P37/TMO pin functions as P37 I/O port 1 P37/TMO pin functions as TMO output port Notes: If the TMO pin is used for remote control sending, a careless timer output pulse may be output when the remote control mode is set after the output has been switched to the TMO output. Perform the switching and setting in the following order. [1] Set the remote control mode. [2] Set the TMJ-1 and 2 counter data of the timer J. [3] Switch the P37/TMO pin to the TMO output pin. [4] Set the ST bit to 1. Rev. 0.1, 11/98, page 936 of 975 H'FFD1: Port Control Register 1 PCR1: I/O Port Bit : Initial value : R/W : 7 PCR17 6 PCR16 5 PCR15 4 PCR14 3 PCR13 2 PCR12 1 PCR11 0 PCR10 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 P1n pin functions as input port 1 P1n pin functions as output port (n = 7 to 0) H'FFD2: Port Control Register 2 PCR2: I/O Port Bit : Initial value : R/W : 7 PCR27 6 PCR26 5 PCR25 4 PCR24 3 PCR23 2 PCR22 1 PCR21 0 PCR20 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 P2n pin functions as input port 1 P2n pin functions as output port (n = 7 to 0) H'FFD3: Port Control Register 3 PCR3: I/O Port Bit : Initial value : R/W : 7 PCR37 6 PCR36 5 PCR35 4 PCR34 3 PCR33 2 PCR32 1 PCR31 0 PCR30 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 P3n pin functions as input port 1 P3n pin functions as output port (n = 7 to 0) Rev. 0.1, 11/98, page 937 of 975 H'FFD4: Port Control Register 4 PCR4: I/O Port Bit : Initial value : R/W : 7 PCR47 6 PCR46 5 PCR45 4 PCR44 3 PCR43 2 PCR42 1 PCR41 0 PCR40 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 P4n pin functions as input port 1 P4n pin functions as output port (n = 7 to 0) H'FFD5: Port Control Register 5 PCR5: I/O Port Bit : Initial value : R/W : 7 -- 6 -- 5 -- 4 -- 3 PCR53 2 PCR52 1 PCR51 0 PCR50 1 -- 1 -- 1 -- 1 -- 0 W 0 W 0 W 0 W 0 P5n pin functions as input port 1 P5n pin functions as output port (n = 3 to 0) H'FFD6: Port Control Register 6 PCR6: I/O Port Bit : Initial value : R/W : 7 PCR67 6 PCR66 5 PCR65 4 PCR64 3 PCR63 2 PCR62 1 PCR61 0 PCR60 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W PMR6n PCR6n 0 0 P6n/RPn pin functions as P6n general purpose input port 1 P6n/RPn pin functions as P6n general purpose output port * P6n/RPn pin functions as RPn realtime output port 1 Port Control Register 6 Note: * Don't care. (n = 7 to 0) Rev. 0.1, 11/98, page 938 of 975 H'FFD7: Port Control Register 7 PCR7: I/O Port Bit : Initial value : R/W : 7 PCR77 6 PCR76 5 PCR75 4 PCR74 3 PCR73 2 PCR72 1 PCR71 0 PCR70 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 P7n pin functions as input port 1 P7n pin functions as output port (n = 7 to 0) H'FFD8: Port Control Register 8 PCR8: I/O Port Bit : Initial value : R/W : 7 PCR87 6 PCR86 5 PCR85 4 PCR84 3 PCR83 2 PCR82 1 PCR81 0 PCR80 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 P8n pin functions as input port 1 P8n pin functions as output port (n = 7 to 0) H'FFDB: Port Mode Register 4 PMR4: I/O Port Bit : 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 PMR40 Initial value : R/W : 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 0 R/W P40/PWM14 pin function select bit 0 P40/PWM14 pin functions as P40 I/O port 1 P40/PWM14 pin functions as PWM14 output port Rev. 0.1, 11/98, page 939 of 975 H'FFDC: Port Mode Register 5: PMR5: I/O Port Bit : 7 -- 6 -- 5 -- 4 -- 3 PMR53 2 PMR52 1 PMR51 0 -- Initial value : R/W : 1 -- 1 -- 1 -- 1 -- 0 R/W 0 R/W 0 R/W 1 -- Timer B event input edge select 0 The timer B event input detects the falling edge 1 The timer B event input detects the rising edge P52/TMBI pin function select bit 0 P52/TMBI pin function as P52 I/O port 1 P52/TMBI pin functions as TMB input port P53/TRIG pin function select bit 0 P53/TRIG pin function as P53 I/O port 1 P53/TRIG pin function as TRIG input port H'FFDD: Port Mode Register 6 PMR6: I/O Port Bit : Initial value : R/W : 7 PMR67 6 PMR66 5 PMR65 4 PMR64 3 PMR63 2 PMR62 1 PMR61 0 PMR60 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W P67/RP7 to P60/RP0 pin function select bit 0 P6n/RPn pin functions as P6n I/O port 1 P6n/RPn pin functions as RPn output port (n = 7 to 0) H'FFDE: Port Mode Register 7 PMR7: I/O Port Bit : Initial value : R/W : 7 PMR77 6 PMR76 5 PMR75 4 PMR74 3 PMR73 2 PMR72 1 PMR71 0 PMR70 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W P77/PPG7 to P70/PPG0 pin function select bit 0 P7n/PPGn pin functions as P7n I/O port 1 P7n/PPGn pin functions as PPGn output port (n = 7 to 0) Rev. 0.1, 11/98, page 940 of 975 H'FFDF: Port Mode Register 8 PMR8: I/O Port Bit : 7 -- 6 -- 5 -- 4 -- 3 PMR83 2 PMR82 1 PMR81 0 PMR80 Initial value : R/W : 1 -- 1 -- 1 -- 1 -- 0 R/W 0 R/W 0 R/W 0 R/W P80/EXTTRG pin function select bit 0 P80/EXTTRG pin functions as P80 I/O port 1 P80/EXTTRG pin functions as EXTTRG input port P81/EXCAP pin function select bit 0 P81/EXCAP pin functions as P81 I/O port 1 P81/EXCAP pin functions as EXCAP input port P82/SV1 pin function select bit 0 P82/SV1 pin functions as P82 I/O port 1 P82/SV1 pin functions as SV1 output port P83/SV2 pin function select bit 0 P83/SV2 pin functions as P83 I/O port 1 P83/SV2 pin functions as SV2 output port H'FFE1: Pull-Up MOS Select Register 1 PUR1: I/O Port Bit : Initial value : R/W : 7 PUR17 6 PUR16 5 PUR15 4 PUR14 3 PUR13 2 PUR12 1 PUR11 0 PUR10 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 P1n pin has no pull-up MOS transistor 1 P1n pin has pull-up MOS transistor (n = 7 to 0) Rev. 0.1, 11/98, page 941 of 975 H'FFE2: Pull-Up MOS Select Register 2 PUR2: I/O Port Bit : Initial value : R/W : 7 PUR27 6 PUR26 5 PUR25 4 PUR24 3 PUR23 2 PUR22 1 PUR21 0 PUR20 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 P2n pin has no pull-up MOS transistor 1 P2n pin has pull-up MOS transistor (n = 7 to 0) H'FFE3: Pull-Up MOS Select Register 3 PUR3: I/O Port Bit : Initial value : R/W : 7 PUR37 6 PUR36 5 PUR35 4 PUR34 3 PUR33 2 PUR32 1 PUR31 0 PUR30 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 P3n pin has no pull-up MOS transistor 1 P3n pin has pull-up MOS transistor (n = 7 to 0) H'FFE4: Realtime Output Trigger Edge Select Register RTPEGR: I/O Port Bit : 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- Initial value : R/W : 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 1 0 RTPEGR1 RTPEGR0 0 R/W 0 R/W Realtime output trigger edge select bit RTPEGR1 RTPEGR0 0 1 Rev. 0.1, 11/98, page 942 of 975 Realtime output trigger edge select 0 Trigger input is disabled 1 Rising edge of trigger input is selected 0 Falling edge of trigger input is selected 1 Rising and falling edges of trigger input is selected H'FFE5: Realtime Output Trigger Select Register RTPSR: I/O Port Bit : Initial value : R/W : 7 RTPSR7 6 RTPSR6 5 RTPSR5 4 RTPSR4 3 RTPSR3 2 RTPSR2 1 RTPSR1 0 RTPSR0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 External trigger (TRIG pin) input is selected 1 Internal triggfer (HSW) input is selected (n = 7 to 0) H'FFE8: System Control Register SYSCR: System Control Bit : Initial value : R/W : 7 6 5 4 3 2 1 -- -- INTM1 INTM0 XRST 0 -- 0 -- 0 0 1 0 0 R R/W R R/W R/W NMIEG1 NMIEG0 0 -- 1 -- NMI edge select bits NMIEG1 NMIEG0 0 0 Interrupt request is generated at falling edge of NMI input 1 Interrupt request is generated at rising edge of NMI input * Interrupt request is generated at rising or falling edge of NMI input 1 NMI edge select Note: * Don't care. External reset 0 Reset is generated by watchdog timer overflow 1 Reset is generaed by external reset input Interrupt control mode INTM1 INTM0 Interrupt control mode 0 0 0 Interrupt is controlled by I bit 1 1 Interrupt is controlled by I and UI bits and ICR 0 2 Cannot be used in the H8S/2194 Series 1 3 Cannot be used in the H8S/2194 Series 1 Interrupt control Rev. 0.1, 11/98, page 943 of 975 H'FFE9: Mode Control Register MDCR: System Control Bit : 7 6 5 4 3 2 1 0 -- -- -- -- -- -- -- MDS0 Initial value : 0 0 0 0 0 0 0 --* R/W: -- -- -- -- -- -- -- R Mode select 0 Note: * Determined by MD0 pin. H'FFEA: Standby Control Register SBYCR: System Control Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 -- -- SCK1 SCK0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W -- -- R/W R/W System clock select SCK1 SCK0 0 0 Bus master is in high-speed mode 0 1 Medium-speed clock is /16 1 0 Medium-speed clock is /32 1 1 Medium-speed clock is /64 System clock select Standby timer select bits STS2 STS1 STS0 0 0 0 8192 states 0 0 1 16384 states 0 1 0 32768 states 0 1 1 65536 states 1 0 0 131072 states 1 0 1 262144 states Standby time *1 16 states *2 1 1 Notes: 1. Don't care. 2. The standby time is 32 states when transited to medium-speed mode /32 (SCK = 1, SCK = 0). Do not select 16 states for Flash ROM version. Software standby 0 Transition to sleep mode after execution of SLEEP instruction in high-speed mode or medium-speed mode Transition to subsleep mode after execution of SLEEP instruction in subactive mode 1 Transition to stadby mode, subactive mode, or watch mode after execution of SLEEP instruction in high-speed mode or mediumspeed mode Transition to watch mode or high-speed mode after execution of SLEEP instruction in subactive mode Rev. 0.1, 11/98, page 944 of 975 H'FFEB: Low-Power Control Register LPWRCR: System Control Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 DTON LSON NESEL -- -- -- SA1 SA0 0 0 0 0 0 0 0 0 R/W R/W R/W -- -- -- R/W R/W Subactive mode clock select SA1 SA0 0 0 Operating clock of CPU is w/8 0 1 Operating clock of CPU is w/4 1 * Operating clock of CPU is w/2 Subactive mode clock select Note: * Don't care. Noise elimination sampling frequency select 0 Sampling at divided by 16 1 Sampling at divided by 4 Low-speed on flag 0 * When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, standby mode, or watch mode * When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode, or directly to high-speed mode * After watch mode is cleared, a transition is made to high-speed mode 1 * When a SLEEP instruction is executed in high-speed mode a transition is made to watch mode, subactive mode, sleep mode or standby mode. * When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode or watch mode. * After watch mode is cleared, a transition is made to subactive mode Direct transfer on flag 0 * When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, standby mode, or watch mode * When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode, or directly to high-speed mode 1 * When a SLEEP instruction is executed in high-speed mode or medium-speed mode, a transition is made directly to subactive mode*, or a transition is made to sleep mode or standby mode * When a SLEEP instruction is executed in subactive mode, a transition is made directily to high-speed mode, or a transition is made to subsleep mode Rev. 0.1, 11/98, page 945 of 975 H'FFEC: Module Stop Control Register MSTPCRH: System Control H'FFED: Module Stop Control Register MSTPCRL: System Control MSTPCRH Bit : 7 6 5 4 3 MSTPCRL 2 1 0 7 6 5 4 3 2 1 0 MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Initial value : R/W : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Module stop 0 Module stop mode is released 1 Module stop mode is set H'FFEE: Serial Timer Control Register STCR: System Control Bit : 7 6 5 4 3 2 1 0 -- IICX IICRST -- FLSHE -- -- -- Initial value : 0 0 0 0 0 0 0 0 R/W : -- R/W R/W -- R/W -- -- -- Flash memory control register enable bit 0 Flash memory control register is not selected 1 Flash memory control register is selected I2C controller reset bit 0 IIC controller is not reset 1 IIC controller is reset I2C transfer clock select Used combined with ICMR CKS2 to CKS0 Rev. 0.1, 11/98, page 946 of 975 H'FFF0: IRQ Edge Select Register IEGR: Interrupt Controller Bit : Initial value : R/W : 2 1 0 7 6 5 4 3 -- IRQ5EG IRQ4EG IRQ3EG IRQ2EG 0 0 0 0 0 0 0 0 -- R/W R/W R/W R/W R/W R/W R/W IRQ1EG IRQ0EG1 IRQ0EG2 IRQ0 pin detected dege select bits IRQ0EG1 IRQ0EG0 0 0 IRQ0 pin detected edge select 0 1 Interrupt request generaed at rising edge of IRQ0 pin input 1 * Interrupt request generaed at bath falling and rising edge of IRQ0 pin input Interrupt request generaed at falling edge of IRQ0 pin input Note: * Don't care. IRQ5 to IRQ1 pins detected edge select bits 0 Interrupt request generated at falling edge of IRQn pin input 1 Interrupt request generated at rising edge of IRQn pin input (n = 5 to 1) H'FFF1: IRQ Enable Register IENR: Interrupt Controller Bit : Initial value : R/W : 7 6 -- -- 0 0 -- -- 5 IRQ5E 4 IRQ4E 3 IRQ3E 2 IRQ2E 1 IRQ1E 0 IRQ0E 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W IRQ5 to IRQ0 enable bits 0 1 IRQn interrupt is disabled IRQn interrupt is enabled (n = 5 to 0) Rev. 0.1, 11/98, page 947 of 975 H'FFF2: IRQ Status Register IRQR: Interrupt Controller Bit : 7 -- 6 -- 5 IRQ5F 4 IRQ4F 3 IRQ3F 2 IRQ2F 1 IRQ1F 0 IRQ0F Initial value : R/W : 0 -- 0 -- 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* 0 R/(W)* IRQ5 to IRQ0 flag 0 [Clearing conditions] Cleared by reading IRQnF set to 1, then writing 0 in IRQnF When IRQn interrupt exception handling is executed 1 [Setting conditions] (1) When a falling edge occurs in IRQn input while falling edge detection is set (IRQnEG = 0) (2) When a rising edge occurs in IRQn input while rising edge detection is set (IRQnEG = 0) (3) When a falling or rising edge occurs in IRQ0 input while both-edge detection is set (IRQ0EG1 = 1) (n = 5 to 0) Note: * Only 0 can be written to clear the flag. H'FFF3: Interrupt Control Register A ICRA: Interrupt Controller H'FFF4: Interrupt Control Register B ICRB: Interrupt Controller H'FFF5: Interrupt Control Register C ICRC: Interrupt Controller H'FFF6: Interrupt Control Register D ICRD: Interrupt Controller Bit : 7 ICR7 6 ICR6 5 ICR5 4 ICR4 3 ICR3 2 ICR2 1 ICR1 0 ICR0 Initial value : R/W : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Interrupt control level 0 Corresponding interrupt source is control level 0 (non-priority) 1 Corresponding interrupt source is control level 1 (priority) (n = 7 to 0) Rev. 0.1, 11/98, page 948 of 975 H'FFF8: Flash Memory Control Register 1 FLMCR1: FLASH ROM (FLASH Version Only) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 FWE SWE -- -- EV PV E P --* 0 0 0 0 0 0 0 R R/W -- -- R/W R/W R/W R/W Program 0 Program mode cleared 1 Transition to program mode [Setting condition] When FWE = 1, SWE = 1, and PSU = 1 Erase 0 Erase mode cleared 1 Transition to erase mode [Setting condition] When FWE = 1, SWE = 1, and ESU = 1 Program-verify 0 Program-verify mode cleared 1 Transition to program-verufy mode [Setting condition] When FWE = 1 and SWE = 1 Erase-verify 0 Erase-verify mode cleared 1 Transition to erase-verify mode [Setting condition] When FWE = 1 and SWE = 1 Software write enable 0 Writes are disabled 1 Writes are enabled [Setting condition] When FWE = 1 Flash write enable 0 When a low level is input to the FWE pin (hardware-protected state) 1 When a high level is input to the FWE pin Note: * Determined by the state of the FWE pin. Rev. 0.1, 11/98, page 949 of 975 H'FFF9: Flash Memory Control Register 2 FLMCR2: FLASH ROM (FLASH Version Only) 7 6 5 4 3 2 1 0 FLER -- -- -- -- -- ESU PSU Initial value : 0 0 0 0 0 0 0 0 R/W : R -- -- -- -- -- R/W R/W Bit : Program setup 0 Program setup cleared 1 Program setup [Setting condition] When FWE = 1, and SWE = 1 Erase setup 0 Erase setup cleared 1 Erase setup [Setting condition] When FWE = 1, and SWE = 1 Flash memory error 0 Flash memory is operating normally Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode 1 An error has occurred during flash memeory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 7.8.3, Error Protection H'FFFA: Erase Block Select Register 1 EBR1: FLASH ROM (FLASH Version Only) Bit : EBR1 7 6 5 4 3 2 1 0 -- -- -- -- -- -- EB9 EB8 Initial value : 0 0 0 0 0 0 0 0 R/W : -- -- -- -- -- -- R/W R/W Rev. 0.1, 11/98, page 950 of 975 H'FFFB: Erase Block Select Register 2 EBR2: FLASH ROM (FLASH Version Only) Bit : EBR2 Initial value : R/W : 7 6 5 4 3 2 1 0 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Division of Erase Block Block (size) 128-k byte version EB0 (1k bytes) EB1 (1k bytes) EB2 (1k bytes) EB3 (1k bytes) EB4 (28k bytes) EB5 (16k bytes) EB6 (8k bytes) EB7 (8k bytes) EB8 (32k bytes) EB9 (32k bytes) Address H'000000 to H'0003FF H'000400 to H'0007FF H'000800 to H'000BFF H'000500 to H'000FFF H'001000 to H'007FFF H'008000 to H'00BFFF H'00C000 to H'00DFFF H'00E000 to H'00FFFF H'010000 to H'017FFF H'018000 to H'01FFFF Rev. 0.1, 11/98, page 951 of 975 Rev. 0.1, 11/98, page 952 of 975 Appendix C Pin Circuit Diagrams C.1 Pin Circuit Diagrams Circuit diagrams for all pins except power supply pins are shown in table C.1. Legend G OUT PMOS NMOS G IN OUT Clocked gate signal transmitted when G = 1 IN Signal transmitted when G = 0 [Symbols] RD: Read signal RST: Reset signal LPM: Power-down mode signal (1 in standby, watch, and subactive modes) Hi-Z: High impedance SLEEP: Sleep mode signal Note: Numbers given for resistance values, etc., are reference values. Rev. 0.1, 11/98, page 953 of 975 Table C.1 Pin Circuit Diagrams (1) Pin States Pin Names P00/AN0 to P07/AN7 Sleep At Reset Mode Circuit Diagram PMR0n*RD Power-Down Modes Other Than Sleep Mode Hi-Z Retained Hi-Z Hi-Z Retained Hi-Z Hi-Z Retained Pull-up MOS: OFF Subactive mode: Functions Other modes: Hi-Z SCH3 to SCH0 AN8 to ANB HCH1, HCH0 P10/,54 to P15/,54 P16/,& PUR1n*PCR1n PDR1n PMR1n PCR1n RD*PCR1n INT PMR1n INT = IRQ0 to IRQ5, IC n = 0 to 6 When ,54 to ,54 and ,& are selected, pin input should be fixed high or low. Rev. 0.1, 11/98, page 954 of 975 Table C.1 Pin Circuit Diagrams (2) Pin States Pin Names P17/TMOW Sleep At Reset Mode Circuit Diagram PUR17*PCR17 Power-Down Modes Other Than Sleep Mode Hi-Z Retained Pull-up MOS: OFF Subactive mode: Functions Other modes: Hi-Z Hi-Z Retained Pull-up MOS: OFF Subactive mode: Functions Other modes: Hi-Z TMOW PDR17 PMR17 PCR17 RD*PCR17 P20/SI1 PUR20*PCR20 PDR20 RXE PCR20 RD*PCR20 SI1 RXE RXE: Input control signal determined by SCR and SMR. When SI1 is selected, pin input should be fixed high or low. Rev. 0.1, 11/98, page 955 of 975 Table C.1 Pin Circuit Diagrams (3) Pin States Pin Names Sleep At Reset Mode Circuit Diagram P21/SO1 PUR21*PCR21 Power-Down Modes Other Than Sleep Mode Hi-Z Retained Pull-up MOS: OFF Subactive mode: Functions Other modes: Hi-Z Hi-Z Retained Pull-up MOS: OFF Subactive mode: Functions Other modes: Hi-Z SO1 PDR21 TXE PCR21 RD*PCR21 TXE: Output control signal determined by SCR and SMR. P22/SCK1 PUR22*PCR22 SCKO PDR22 CKOE PCR22 RD*PCR22 SCKI CKIE SCKO: Transfer clock output SCKI: Transfer clock input CKOE: Transfer clock output control signal determined by SMR CKIE: Transfer clock input control signal determined by SMR and SCR When SCK1 is selected, pin input should be fixed high or low. Rev. 0.1, 11/98, page 956 of 975 Table C.1 Pin Circuit Diagrams (4) Pin States Pin Names Sleep At Reset Mode Circuit Diagram P23/SDA P24/SCL PUR2n*PCR2n Power-Down Modes Other Than Sleep Mode Hi-Z Retained Pull-up MOS: OFF Subactive mode: Functions Other modes: Hi-Z Hi-Z Retained Pull-up MOS: OFF Subactive mode: Functions Other modes: Hi-Z PDR2n IICE PCR2n RD*PCR2n IICE SDA/SCL SDA/SCL IICE n = 3, 4 IICE: I2C bus enable signal P26/SO2 PUR26*PCR26 SO2 PDR26 PDR26 PCR26 RD*PCR26 Rev. 0.1, 11/98, page 957 of 975 Table C.1 Pin Circuit Diagrams (5) Pin States Pin Names Sleep At Reset Mode Circuit Diagram P25/SI2 PUR25*PCR25 Hi-Z PDR25 PMR25 PCR25 Power-Down Modes Other Than Sleep Mode Retained Pull-up MOS: OFF Subactive mode: Functions Other modes: Hi-Z RD*PCR25 SI2 PMR25 When SI2 is selected, pin input should be fixed high or low. P27/SCK2 Hi-Z PUR27*PCR27 SCKO PDR27 PMR27 EXCK PCR27 Retained Pull-up MOS: OFF Subactive mode: Functions Other modes: Hi-Z SCKI RD*PCRn n = 3, 6 SCKO: Transfer clock output SCKI: Transfer clock input EXCK: External clock input control signal determined by SMR1 or SMR2 When SCK2 is set to input, pin input should be fixed high or low. Rev. 0.1, 11/98, page 958 of 975 Table C.1 Pin Circuit Diagrams (6) Pin States Pin Names Sleep At Reset Mode Circuit Diagram P30/&6 PUR30*PCR30 Hi-Z PDR30 PMR30 PCR30 Power-Down Modes Other Than Sleep Mode Retained Pull-up MOS: OFF Subactive mode: Functions Other modes: Hi-Z RD*PCR30 CS PMR30 When ,54 to ,54, 10, and ,& are selected, pin input should be fixed high or low. P31/STRB P32/PWM0 P33/PWM1 P34/PWM2 P35/PWM3 P36/BUZZ P37/TMO PUR3n*PCR3n OUT PDR3n PMR3n PCR3n Hi-Z Retained Pull-up MOS: OFF Subactive mode: Functions Other modes: Hi-Z n = 1 to 7 RD*RCR3n OUR: P31/STRB: SC12 strobe output P32/PWM0: 8-bit PWM0 output P33/PWM1: 8-bit PWM1 output P34/PWM2: 8-bit PWM2 output P35/PWM3: 8-bit PWM3 output P36/BUZZ: Timer J buzzer output P37/TMO: Timer J timer output Rev. 0.1, 11/98, page 959 of 975 Table C.1 Pin Circuit Diagrams (7) Pin States Pin Names Sleep At Reset Mode Circuit Diagram P40/PWM14 OUT Hi-Z PDR40 Retained Subactive mode: Functions Other modes: Hi-Z PMR40 PCR40 RD*PCR40 Power-Down Modes Other Than Sleep Mode OUT PWM14 P41/FTIA P42/PTIB P43/FTIC P44/FTID PDR4n Hi-Z PCR4n Retained Subactive mode: Functions Other modes: Hi-Z RD*PCR4n IN IN = FTIA, FTIB, FTIC, FTID n = 1 to 4 P45/FTOA P46/PTOB OUT PDR4n TOE PCR4n RD*PCR4n n = 5, 6 OUT: P45/FTOA: Timer X1 output compare output FTOA P46/FTOB: Timer X1 output compare output FTOB TOE: Output control signal determined by TOCR Rev. 0.1, 11/98, page 960 of 975 Hi-Z Retained Subactive mode: Functions Other modes: Hi-Z Table C.1 Pin Circuit Diagrams (8) Pin States Pin Names Sleep At Reset Mode Circuit Diagram P47 PDR47 Hi-Z PCR47 Power-Down Modes Other Than Sleep Mode Retained Subactive mode: Functions Other modes: Hi-Z RD*PCR47 P50/$'75* PDR50 Hi-Z TRGE PCR50 Retained Subactive mode: Functions Other modes: Hi-Z RD*PCR50 ADTRG TRGE TRGE: A/D trigger input control signal When $'75* is selected, pin input should be fixed high or low. P51 PDR51 PCR51 Hi-Z Retained Subactive mode: Functions Other modes: Hi-Z RD*PCR51 Rev. 0.1, 11/98, page 961 of 975 Table C.1 Pin Circuit Diagrams (9) Pin States Pin Names Sleep At Reset Mode Circuit Diagram P52/TMBI P53/TRIG PDR5n Hi-Z PMR5n PCR5n Power-Down Modes Other Than Sleep Mode Retained Subactive mode: Functions Other modes: Hi-Z RD*PCR5n IN PMR5n n = 2, 3 IN = TMBI, TRIG When TMBI and TRIG are selected, pin input should be fixed high or low. P60/RP0 to P67/RP7 PDRS6n Hi-Z PCRS6n Retained Subactive mode: Functions Other modes: Hi-Z n = 0 to 7 RD*PCRRS6n P70/PPG0 to P77/PPG7 PPGn PDR7n PMR7n PCR7n RD*PCR7n Rev. 0.1, 11/98, page 962 of 975 n = 0 to 7 Hi-Z Retained Subactive mode: Functions Other modes: Hi-Z Table C.1 Pin Circuit Diagrams (10) Pin States Pin Names Sleep At Reset Mode Circuit Diagram P80/ EXTTRG P81/EXCAP PDR8n Hi-Z PMR8n PCR8n RD*PCR8n Power-Down Modes Other Than Sleep Mode Retained Subactive mode: Functions Other modes: Hi-Z IN n = 0, 1 PMR8n IN = EXTTRG, EXCAP When EXTTRG and EXCAP are selected, pin input should be fixed high or low. P82/SV1 P83/SV2 OUT Hi-Z Retained Subactive mode: Functions Other modes: Hi-Z Hi-Z Retained Subactive mode: Functions Other modes: Hi-Z PDR8n PMR8n PCR8n RD*PCR8n n = 2, 3 OUT = SV1, SV2 P84 to P87 PDR8n PCR8n RD*PCR8n Csync n = 4 to 7 Pin input should be fixed high or low. Module STOP Rev. 0.1, 11/98, page 963 of 975 Table C.1 Pin Circuit Diagrams (11) Pin States Pin Names Circuit Diagram COMP/PS2 Sleep At Reset Mode Power-Down Modes Other Than Sleep Mode Fixed Fixed Fixed Hi-Z Hi-Z Hi-Z Low output Low output Low output Low output Low output Low output RST + LPM + SLEEP AUDIOFF VIDEOFF OUT LPM CAPPWM DRMPWM Vpulse LPM 15 k Typ Threelevel control circuit 15 k Typ Note: Resistance values are reference value 5(6 MD0 Rev. 0.1, 11/98, page 964 of 975 RST Low input (High) (High) Table C.1 Pin Circuit Diagrams (12) Pin States Pin Names Circuit Diagram C.Rotary/PS0 H.Ampsw/ PS1 OUT Sleep At Reset Mode Power-Down Modes Other Than Sleep Mode Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z SPDRn SPMRn SPCRn RD*SPCRn n = 0, 1 OUT = C.Rotary, H.Ampsw EXCTL/PS4 SPDR4 SPMR4 SPCR4 RD*PCRn EXCTL SPMRn When EXCTL is selected, pin input should be fixed high or low. CFG BIAS + P250 VREF REF CFGCOMP - M250 F/F S CFGCOMP O R stp CFG + VREF + - Res+ModuleSTOP Rev. 0.1, 11/98, page 965 of 975 Table C.1 Pin Circuit Diagrams (13) Pin States Pin Names DFG DPG Sleep At Reset Mode Circuit Diagram DPG SW DFG Power-Down Modes Other Than Sleep Mode Hi-Z Hi-Z Oscillation Oscillation Oscillation Oscillation Oscillation High output DFG DPG DPG Pes+LPM DPG SW PDRn PMRn PCRn RD*PCRn CTL (+) CTL (-) CTLREF CTLBias CTLFB CTLAmp (O) CTLSMT (I) AMPON (PB-CTL) AMPSHORT (REC-CTL) CTLGR3 to 1 CTLFB CTLGR0 + - + - + PB-CTL (+) PB-CTL (-) CTL (-) CTL (+) CTLREF CTLBias CTLFB CTLAmp (o) CTLSMT (i) Note Note: Be sure to set a capacitor between CTLAmp (o) and CTLSMT (i). X2 1 M Typ Note: Resistance values are reference values. X1 OSC2 LPM OSC1 Rev. 0.1, 11/98, page 966 of 975 Appendix D Port States in the Difference Processing States D.1 Pin Circuit Diagrams Table D.1 Port States Overview Port Reset Active Sleep Standby Watch Subactive Subsleep P07 to P00 High impedance High impedance High impedance High impedance High impedance High impedance High impedance P17 to P10 High impedance Functions Retained High impedance High impedance Functions Retained P27 to P20 High impedance Functions Retained High impedance High impedance Functions Retained P37 to P30 High impedance Functions Retained High impedance High impedance Functions Retained P47 to P40 High impedance Functions Retained High impedance High impedance Functions Retained P53 to P50 High impedance Functions Retained High impedance High impedance Functions Retained P67 to P60 High impedance Functions Retained High impedance High impedance Functions Retained P77 to P70 High impedance Functions Retained High impedance High impedance Functions Retained P87 to P80 High impedance Functions Retained High impedance High impedance Functions Retained Rev. 0.1, 11/98, page 967 of 975 Rev. 0.1, 11/98, page 968 of 975 Appendix E Usage Notes E.1 Power Supply Rise and Fall Order Figure E.1 shows the order in which the power supply pins rise when the chip is powered on, and the order in which they fall when the chip is powered down. If the power supply voltages cannot rise and fall simultaneously, power supply operations should be carried out in this order. At power-on, wait until the microcomputer section power supply (VCC) has risen to the prescribed voltage, then raise the other analog power supplies. At power-down, drop the analog power supplies first, followed by the microcomputer section power supply (VCC). When powering up and down, ensure that the voltage applied to the pins does not exceed the respective power supply voltage. VCC, AVCC VCC, AVCC SVCC Vin VCC AVCC SVCC Vin SVCC Vin : Microcomputer section power supply voltage : A/D converter power supply voltage : Servo section power supply voltage : Pin applied voltage Figure E.1 Power Supply Rise and Fall Order In power-down modes (except sleep mode), the analog power supplies can be turned off to reduce current dissipation. When the microcomputer section power supply (VCC) is dropped to the backup voltage in a power-down mode, the order shown in figure E.2 should be followed. Make sure that the voltage applied to the pins does not exceed the respective power supply voltage. The A/D converter power supply (AVCC) should be set to the same potential as the microcomputer section power supply (VCC). In all power-down modes except sleep mode, AVCC is turned off inside the device. At this time, the AVCC current dissipation is defined as AISTOP. Rev. 0.1, 11/98, page 969 of 975 VCC, AVCC SVCC 5V 2.7 V Vin VCC : Microcomputer section power supply voltage AVCC : A/D converter power supply voltage SVCC : Servo section power supply voltage Vin : Pin applied voltage Figure E.2 Power Supply Control in Power-Down Modes E.2 Pin Handling When the High-Speed Switching Circuit for FourHead Special Playback Is Not Used Table E.1 shows how the C.Rotary, H.AmpSW, and COMP pins should be handled when the switching circuit for four-head special-effects playback is not used. COMP is an input pin, and the other two are output pins. When the switching circuit for four-head special-effects playback is not used, the related pins should be handled as shown below. Table E.1 Pin Handling When the High-Speed Switching Circuit for Four-Head Special Playback Is Not Used Pin No. Pin Name Connection 103 C.Rotary OPEN (output pin)* 104 H.AMP SW OPEN (output pin)* 105 COMP VSS Note: * Output depends on the special-effects control register (CHCR) value. If the initial value is used, the output is low-level. Rev. 0.1, 11/98, page 970 of 975 E.3 Sample External Circuits Examples of external circuits for the servo section, and sync signal detection circuit are shown in figures E.3, E.4. (1) Servo Section An example of the external circuit for the DRMPWM output and CAPPWM output pins is shown in figure E.3. DRMPWM (pin 26) CAPPWN (pin 25) R1 C1 Figure E.3 Sample External Circuit for Servo Section (2) Sync Signal Detection Circuit Section Figure E.4 shows an example of the external circuit for the sync signal detection circuit section. Csync 33 k 10 pF Note: The figures shown are reference values. Careful consideration should be given to board floating capacitance and wiring characteristics when deciding on the constants. Figure E.4 Example of External Circuit for Sync Signal Detection Circuit Section Rev. 0.1, 11/98, page 971 of 975 Rev. 0.1, 11/98, page 972 of 975 Appendix F List of Product Codes Table F.1 Product Codes List of H8S/2194 Series Product Code Product Type H8S/2194 Series H8S/2194 Mark Code Package (Hitachi Package Code) Mask ROM version HD6432194 HD6432194 (***)F 112-pin FP (FP-112) F-ZTAT version HD64F2194 HD64F2194F 112-pin FP (FP-112) H8S/2193 Mask ROM version HD6432193 HD6432193 (***)F 112-pin FP (FP-112) H8S/2192 Mask ROM version HD6432192 HD6432192 (***)F 112-pin FP (FP-112) H8S/2191 Mask ROM version HD6432191 HD6432191 (***)F 112-pin FP (FP-112) Note: (***) is the ROM code. Rev. 0.1, 11/98, page 973 of 975 Rev. 0.1, 11/98, page 974 of 975 Appendix G External Dimensions Unit: mm 23.2 0.3 20 84 57 56 112 29 0.65 23.2 0.3 85 0.10 *0.17 0.05 0.15 0.04 1.23 2.70 0.13 M 3.05 Max 28 1.6 0 -8 0.10 +0.15 -0.10 1 *0.32 0.08 0.30 0.06 0.8 0.3 *Dimension including the plating thickness Base material dimension Figure G.1 Extermal Dimensions (FP-112) Rev. 0.1, 11/98, page 975 of 975