October 2015
DocID028258 Rev 2
1/13
This is information on a product in full production.
www.st.com
STL8N6F7
N-channel 60 V, 0.019 Ω typ., 8 A STripFET™ F7
Power MOSFET in a PowerFLAT™ 3.3x3.3 package
Datasheet - production data
Figure 1: Internal schematic diagram
Features
Order code
VDS
RDS(on) max
ID
STL8N6F7
60 V
0.023 Ω
8 A
Among the lowest RDS(on) on the market
Excellent figure of merit (FoM)
Low Crss/Ciss ratio for EMI immunity
High avalanche ruggedness
Applications
Switching applications
Description
This N-channel Power MOSFET utilizes
STripFET™ F7 technology with an enhanced
trench gate structure that results in very low on-
state resistance, while also reducing internal
capacitance and gate charge for faster and more
efficient switching.
Table 1: Device summary
Order code
Marking
Package
Packing
STL8N6F7
8N6F7
PowerFLAT™ 3.3x3.3
Tape and reel
1234
PowerFLAT™ 3.3x3.3
D(5, 6, 7, 8)
G(4)
S(1, 2, 3)
8
1 2 3 4
765
AM15810v1
Contents
STL8N6F7
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DocID028258 Rev 2
Contents
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1 Electrical characteristics (curves) ...................................................... 5
3 Test circuits ..................................................................................... 7
4 Package information ....................................................................... 8
4.1 PowerFLAT 3.3x3.3 package information ......................................... 9
5 Revision history ............................................................................ 12
STL8N6F7
Electrical ratings
DocID028258 Rev 2
3/13
1 Electrical ratings
Table 2: Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDS
Drain-source voltage
60
V
VGS
Gate-source voltage
± 20
V
ID(1)
Drain current (continuous) at TC = 25 °C
36
A
ID(1)
Drain current (continuous) at TC = 100 °C
22
A
IDM(1)(2)
Drain current (pulsed)
144
A
ID(3)
Drain current (continuous) at Tpcb = 25 °C
8
A
ID(3)
Drain current (continuous) at Tpcb = 100 °C
5
A
IDM(2)(3)
Drain current (pulsed)
32
A
PTOT(1)
Total dissipation at TC = 25 °C
60
W
PTOT(3)
Total dissipation at Tpcb = 25 °C
3
W
Tstg
Storage temperature
-55 to 150
°C
Tj
Operating junction temperature
Notes:
(1)This value is rated according to Rthj-c.
(2)Pulse width limited by safe operating area.
(3)This value is rated according to Rthj-pcb.
Table 3: Thermal data
Symbol
Parameter
Value
Unit
Rthj-pcb(1)
Thermal resistance junction-pcb max.
42.8
°C/W
Rthj-case
Thermal resistance junction-case max.
2.1
°C/W
Notes:
(1)When mounted on FR-4 board of 1 inch², 2oz Cu, t < 10 sec.
Electrical characteristics
STL8N6F7
4/13
DocID028258 Rev 2
2 Electrical characteristics
(TC = 25 °C unless otherwise specified)
Table 4: On /off states
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
V(BR)DSS
Drain-source breakdown voltage
ID = 1 mA, VGS = 0 V
60
V
IDSS
Zero gate voltage
drain current
VGS = 0 V
VDS = 60 V
1
µA
IGSS
Gate-body leakage
current
VGS = 20 V, VDS = 0 V
100
nA
VGS(th)
Gate threshold voltage
VDS = VGS, ID = 250 μA
2
4
V
RDS(on)
Static drain-source
on-resistance
VGS = 10 V, ID = 4 A
0.019
0.023
Ω
Table 5: Dynamic
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Ciss
Input capacitance
VDS = 30 V, f = 1 MHz,
VGS = 0 V
-
420
-
pF
Coss
Output capacitance
-
215
-
pF
Crss
Reverse transfer
capacitance
-
16
-
pF
Qg
Total gate charge
VDD = 30 V, ID = 8 A,
VGS = 10 V (see Figure 14:
"Test circuit for gate charge
behavior")
-
8
-
nC
Qgs
Gate-source charge
-
2.3
-
nC
Qgd
Gate-drain charge
-
2.1
-
nC
Table 6: Switching times
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
td(on)
Turn-on delay time
VDD = 30 V, ID = 4 A,
RG = 4.7 Ω, VGS = 10 V (see
Figure 13: "Test circuit for
resistive load switching times")
-
7.85
-
ns
tr
Rise time
-
3.25
-
ns
td(off)
Turn-off delay time
-
12.1
-
ns
tf
Fall time
-
3.95
-
ns
Table 7: Source-drain diode
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VSD(1)
Forward on voltage
ISD = 8 A, VGS = 0 V
-
1.2
V
trr
Reverse recovery time
ID = 8 A, di/dt = 100 A/µs
VDD = 48 V (see Figure 15:
"Test circuit for inductive load
switching and diode recovery
times"
-
17.1
ns
Qrr
Reverse recovery charge
-
6.67
nC
IRRM
Reverse recovery current
-
0.8
A
Notes:
(1)Pulsed: pulse duration = 300 µs, duty cycle 1.5%
STL8N6F7
Electrical characteristics
DocID028258 Rev 2
5/13
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area
Figure 3: Thermal impedance
Figure 4: Output characteristics
Figure 5: Transfer characteristics
Figure 6: Gate charge vs gate-source voltage
Figure 7: Static drain-source on-resistance
Electrical characteristics
STL8N6F7
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DocID028258 Rev 2
Figure 8: Capacitance variations
Figure 9: Normalized gate threshold voltage
vs temperature
Figure 10: Normalized on-resistance vs
temperature
Figure 11: Normalized V(BR)DSS vs
temperature
Figure 12: Source-drain diode forward characteristics
STL8N6F7
Test circuits
DocID028258 Rev 2
7/13
3 Test circuits
Figure 13: Test circuit for resistive load
switching times
Figure 14: Test circuit for gate charge
behavior
Figure 15: Test circuit for inductive load
switching and diode recovery times
Figure 16: Unclamped inductive load test
circuit
Figure 17: Unclamped inductive waveform
Figure 18: Switching time waveform
Package information
STL8N6F7
8/13
DocID028258 Rev 2
4 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
STL8N6F7
Package information
DocID028258 Rev 2
9/13
4.1 PowerFLAT 3.3x3.3 package information
Figure 19: PowerFLAT™ 3.3x3.3 package outline
BOTTOM VIEW
SIDE VIEW
TOP VIEW
8465286_A
Package information
STL8N6F7
10/13
DocID028258 Rev 2
Table 8: PowerFLAT™ 3.3x3.3 package mechanical data
Dim.
mm
Min.
Typ.
Max.
A
0.70
0.80
0.90
b
0.25
0.30
0.39
c
0.14
0.15
0.20
D
3.10
3.30
3.50
D1
3.05
3.15
3.25
D2
2.15
2.25
2.35
e
0.55
0.65
0.75
E
3.10
3.30
3.50
E1
2.90
3.00
3.10
E2
1.60
1.70
1.80
H
0.25
0.40
0.55
K
0.65
0.75
0.85
L
030
0.45
0.60
L1
0.05
0.15
0.25
L2
0.15
θ
8°
10°
12°
STL8N6F7
Package information
DocID028258 Rev 2
11/13
Figure 20: PowerFLAT™ 3.3x3.3 recommended footprint
8465286_footprint
Revision history
STL8N6F7
12/13
DocID028258 Rev 2
5 Revision history
Table 9: Document revision history
Date
Revision
Changes
20-Aug-2015
1
First release.
22-Oct-2015
2
Updated title and features in cover page.
Updated Table 4: "On /off states", Table 5: "Dynamic", Table 6:
"Switching times" and Table 7: "Source-drain diode".
Added Section 3.1: "Electrical characteristics (curves)".
Document status promoted from preliminary di production data.
STL8N6F7
DocID028258 Rev 2
13/13
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