Product Brief SmartFusion2 System-on-Chip FPGAs Product Brief Microsemi's SmartFusion(R)2 SoC FPGAs integrate fourth generation flash-based FPGA fabric, an ARM(R) Cortex(R)-M3 processor, and high-performance communications interfaces on a single chip. The SmartFusion2 family is the industry's lowest power, most reliable and highest security programmable logic solution. SmartFusion2 FPGAs offer up to 3.6X the gate density, up to 2X the performance of previous flash-based FPGA families, and includes multiple memory blocks and multiply accumulate blocks for DSP processing. The 166 MHz ARM Cortex-M3 processor is enhanced with an embedded trace macrocell (ETM), memory protection unit (MPU), 8 kbyte instruction cache, and additional peripherals, including controller area network (CAN), Gigabit Ethernet, and high speed universal serial bus (USB). High speed serial interfaces include PCI EXPRESS(R) (PCIe(R)), 10 Gbps attachment unit interface (XAUI) / XGMII extended sublayer (XGXS) plus native serialization/deserialization (SERDES) communication, while double data rate 2 (DDR2)/DDR3 memory controllers provide high speed memory interfaces. SmartFusion2 Family Reliability * Single Event Upset (SEU) Immune * Junction Temperature: 125C - Military Temperature, 100C - Industrial Temperature, 85C - Commercial Temperature - * * Zero FIT FPGA Configuration Cells Single Error Correct Double Error Detect (SECDED) Protection on the Following: - Ethernet Buffers - CAN Message Buffers - Cortex-M3 (eSRAMs) Embedded Intellectual Property (IP) Protection Through Unique Security Features and Use Models New to the PLD Industry - Encrypted User Key and Bitstream Loading, Enabling Programming in Less-Trusted Locations - Supply-Chain Assurance Device Certificate - Enhanced Anti-Tamper Features - Zeroization Low Power Scratch Pad * Low Static and Dynamic Power * Power as low as 13 mW/Gbps per lane for SERDES devices * Up to 50% lower total power than competing SoC devices Memory - USB Buffers - PCIe Buffer - DDR Memory Controllers with Optional SECDED Modes - Flash*Freeze Mode for Fabric High-Performance FPGA Buffers Implemented with SEU Resistant Latches on the Following: * Efficient 4-Input LUTs with Carry Chains for HighPerformance and Low Power - DDR Bridges (MSS, MDDR, FDDR) * - Instruction Cache - MMUART FIFOs - SPI FIFOs Up to 236 Blocks of Dual-Port 18 Kbit SRAM (Large SRAM) with 400 MHz Synchronous Performance (512 x 36, 512 x 32, 1 kbit x 18, 1 kbit x 16, 2 kbit x 9, 2 kbit x 8, 4 kbit x 4, 8 kbit x 2, or 16 kbit x 1) * Up to 240 Blocks of Three-Port 1 Kbit SRAM with 2 Read Ports and 1 Write Port (micro SRAM) * High-Performance DSP Signal Processing * NVM Integrity Check at Power-Up and On-Demand * No External Configuration Memory Required--InstantOn, Retains Configuration When Powered Off Security * - Design Security Features (Available on all Devices) October 2014 (c) 2014 Microsemi Corporation - Up to 240 Fast Mathblocks with 18 x 18 Signed Multiplication, 17 x 17 Unsigned Multiplication and 44-Bit Accumulator I SmartFusion2 System-on-Chip FPGAs Product Brief Microcontroller Subsystem (MSS) * High Speed Serial Interfaces Hard 166 MHz 32-Bit ARM Cortex-M3 Processor * - 1.25 DMIPS/MHz - 8 Kbyte Instruction Cache - Embedded Trace Macrocell (ETM) - Memory Protection Unit (MPU) - Single Cycle Multiplication, Hardware Divide - JTAG Debug (4 wires), Serial Wire Debug (SWD, 2 Wires), and Serial Wire Viewer (SWV) Interfaces Up to 16 SERDES Lanes, Each Supporting: - XGXS/XAUI Extension (To Implement a 10 Gbps (XGMII) Ethernet PHY Interface) - Native SERDES Interface Facilitates Implementation of Serial RapidIO in Fabric or an SGMII Interface to the Ethernet MAC in MSS - PCI Express (PCIe) Endpoint Controller x1, x2, x4 Lane PCI Express Core Up to 2 Kbytes Maximum Payload Size * 64 KB Embedded SRAM (eSRAM) * Up to 512 KB Embedded Nonvolatile Memory (eNVM) * Triple Speed Ethernet (TSE) 10/100/1000 Mbps MAC * USB 2.0 High Speed On-The-Go (OTG) Controller with ULPI Interface * CAN Controller, 2.0B Compliant, Conforms to ISO11898-1, 32 Transmit and 32 Receive Buffers - MSS DDR Controllers * Two Each: SPI, I2C, Multi-Mode UARTs (MMUART) Peripherals - Supports LPDDR/DDR2/DDR3 - Maximum 333 MHz DDR Clock Rate * Hardware Based Watchdog Timer - SECDED Enable/Disable Feature * 1 General Purpose 64-Bit (or two 32-bit) Timer(s) - * Real-Time Calendar/Counter (RTC) Supports Various DRAM Bus Width Modes, x8, x9, x16, x18, x32, x36 * DDR Bridge (4 Port Data R/W Buffering Bridge to DDR Memory) with 64-Bit AXI Interface - Supports Command Reordering to Optimize Memory Efficiency * Non-Blocking, Multi-Layer AHB Bus Matrix Allowing MultiMaster Scheme Supporting 10 Masters and 7 Slaves - Supports Data Reordering, Returning Critical Word First for Each Command * Two AHB-Lite/APB3 Interfaces (Master/Slave Capable) * Two DMA Controllers to Offload Data Transactions from the Cortex-M3 Processor to FPGA Fabric - 8-Channel Peripheral DMA (PDMA) for Data Transfer Between MSS Peripherals and Memory - High-Performance DMA (HPDMA) for Data Transfer Between eSRAM and DDR Memories 64-Bit/32-Bit AXI and 64-Bit/32-Bit AHB Master and Slave Interfaces to the Application Layer High Speed Memory Interfaces * * * 1 MHz Embedded RC Oscillator 1.2 V Core Voltage * Multi-Standard User I/Os (MSIO/MSIOD) - 50 MHz Embedded RC Oscillator * Up to 8 Clock Conditioning Circuits (CCCs) with Up to 8 Integrated Analog PLLs II - Output Clock with 8 Output Phases and 45 Phase Difference (Multiply/Divide, and Delay Capabilities) - Frequency: Input 1 MHz to 200 MHz, Output 20 MHz to 400 MHz Fabric * Up to Two High Precision 32 KHz to 20 MHz Main Crystal Oscillator - and DDR (FDDR) SDRAM Support through the SMC_FIC and Additional Soft SDRAM Memory Controller - LVTTL/LVCMOS 3.3 V (MSIO Only) - LVCMOS 1.2 V, 1.5 V, 1.8 V, 2.5 V - DDR (SSTL2_1, SSTL2_2) - LVDS, MLVDS, Standards - PCI - LVPECL (receiver only) Clock Sources - (MDDR) Operating Voltage and I/Os Clocking Resources * Up to 2 High Speed DDRx Memory Controllers * Mini-LVDS, RSDS Differential DDR I/Os (DDRIO) - DDR2, DDR3, LPDDR, SSTL2, SSTL18, HSTL - LVCMOS 1.2 V, 1.5 V, 1.8 V, 2.5 V Market Leading Number of User I/Os with 5G SERDES P r o d u ct B r i ef Re vi s i o n 18 SmartFusion2 System-on-Chip FPGAs Product Brief SmartFusion2 SoC FPGA Block Diagram Acronyms AES AHB APB AXI COMM_BLK DDR DPA ECC EDAC ETM FDDR FIC FIIC HS USB OTG IAP MACC MDDR Advanced Encryption Standard Advanced High-Performance Bus Advanced Peripheral Bus Advanced eXtensible Interface Communication Block Double Data Rate Differential Power Analysis Elliptic Curve Cryptography Error Detection and Correction Embedded Trace Macrocell DDR2/3 Controller in FPGA Fabric Fabric Interface Controller Fabric Interface Interrupt Controller High Speed USB 2.0 On-The-Go In-Application Programming Multiply-Accumulate DDR2/3 Controller in MSS MMUART MPU MSIO MSS PUF SECDED SEU SHA SMC_FIC TSE ULPI UTMI WDT XAUI XGMII XGXS Multi-Mode UART Memory Protection Unit Multi-Standard I/O Microcontroller Subsystem Physically Unclonable Function Single Error Correct Double Error Detect Single Event Upset Secure Hashing Algorithm Soft Memory Controller Triple Speed Ethernet (10/100/1000 Mbps) UTMI + Low Pin Interface USB 2.0 Transceiver Macrocell Interface Watchdog Timer 10 Gbps Attachment Unit Interface 10 Gigabit Media Independent Interface XGMII Extended Sublayer P r o du c t B r i e f R ev i si o n 1 8 III SmartFusion2 System-on-Chip FPGAs Product Brief Table 1 * SmartFusion2 SoC FPGA Product Family Logic/DSP Features Maximum Logic Elements (4LUT + DFF)* Mathblocks (18x18) M2S005 M2S010(T) M2S025(T) M2S050(T) M2S090(T) M2S100(T) M2S150(T) 6,060 12,084 27,696 56,340 86,316 99,512 146,124 11 22 34 72 84 160 240 2 1 Fabric Interface Controllers (FICs) 1 PLLs and CCCs 2 6 Cortex-M3 + Instruction cache Grades User I/Os High Speed Fabric Memory MSS eNVM (kbytes) 2 8 Yes 128 256 512 eSRAM (kbytes) 64 eSRAM (kbytes) Non-SECDED 80 CAN, 10/100/1000 Ethernet, HS USB 1 each Multi-Mode UART, SPI, I2C, Timer 2 each LSRAM 18K Blocks 10 21 31 69 109 160 236 uSRAM1K Blocks 11 22 34 72 112 160 240 Total RAM (kbits) 191 400 592 1314 2074 3040 4488 2x36 1x18 8 4 DDR Controllers (Count x Width) 1x18 SERDES Lanes (T) 0 4 PCIe Endpoints 0 1 2x36 8 2 16 4 MSIO (3.3 V) 115 123 157 139 309 292 292 MSIOD (2.5 V) 28 40 40 62 40 106 106 DDRIO (2.5 V) 66 70 70 176 76 176 176 Total User I/O 209 233 267 377 425 574 574 Commercial (C), Industrial (I), Military (M) C,I C,I,M Note: *Total logic may vary based on utilization of DSP and memories in your design. Refer to the SmartFusion FPGA Fabric UG for details. *Feature availability is package dependent, refer to Table 3. IV P r o d u ct B r i ef Re vi s i o n 18 SmartFusion2 System-on-Chip FPGAs Product Brief I/Os Per Package Table 2 * I/Os per Package and Package Options Package Options Type FCS325 VF256 FCS536 VF400 FCV484 VQ144 FG484 FG676 FG896 FC1152 Pitch (mm) 0.5 0.8 0.5 0.8 0.8 0.5 1.0 1.0 1.0 1.0 Length x Width (mm) 11x11 14x14 16x16 17x17 19x19 20x20 23x23 27x27 31x31 35x35 Device I/O Lanes I/O Lanes I/O Lanes M2S005 M2S010 (T)3 M2S025 (T) 3 180 2 M2S050 (T) 3 200 2 M2S090 (T) 2,3 180 4 M2S100 (T) 4 4 M2S150 (T) I/O Lanes I/O Lanes I/O Lanes I/O Lanes I/O Lanes I/O 161 - 171 - 84 - 209 - 138 2 195 4 84 - 233 4 138 2 207 4 267 4 207 4 267 4 267 4 293 4 273 4 377 425 Lanes I/O Lanes 8 4 574 8 574 16 Notes: 1. Preliminary 2. 090 FCS325 is 11x13.5 package dimension 3. Mil Temp 010/025/050/090 are only available in the FG484 package 4. Mil Temp 100/150 devices are only available in the FC1152 package Pin compatible to other devices in the same package. 5. The M2S090(T) device in the FCS/FCSG325 package is available with an ordering code of XZ48. The XZ48 ordering code pre-configures the device for Auto Update mode. Minimum Order quantities apply, contact your local Microsemi sales office for details. P r o du c t B r i e f R ev i si o n 1 8 V SmartFusion2 System-on-Chip FPGAs Product Brief Features per Device/Package Combination Table 3 * Features per Device/Package Combination Features Package VQ1445 VF256 FCS325 VF400 FCV484 FG484 FCS536 FG676 FG896 FC1152 5 Devices MDDR 5G6 Crystal SERDES FDDR Oscillators Lanes PCIe Endpoints MSIOD (2.5 V Max) DDRIO (2.5 V Max) Total User I/O M2S005 - - 2 - - 1 52 9 23 84 M2S010 - - 2 - - 1 50 11 23 84 M2S005 - - 2 - - 1 119 12 30 161 M2S010 (T) x181 - 2 2 1 1 66 8 64 138 M2S025 (T) x181 - 2 2 1 1 66 8 64 138 M2S025 (T) 1 - 2 2 1 1 94 22 64 180 M2S050 (T) 2 x18 - 1 2 1 0 90 22 88 200 M2S090 (T) x181 - 2 4 2 1 104 12 64 180 M2S005 x181 - 2 - - 1 79 28 64 171 M2S010 (T) x181 - 2 4 1 1 99 32 64 195 M2S025 (T) x181 - 2 4 1 1 111 32 64 207 M2S050 (T) x182 - 1 4 1 0 87 32 88 207 M2S150 (T) x181 x181 2 4 4 1 TBD TBD TBD 273 M2S005 1 x18 - 2 - - 1 115 28 66 209 M2S010 (T) x181 - 2 4 1 1 123 40 70 233 M2S025 (T) x181 - 2 4 1 1 157 40 70 267 M2S050 (T) x182 - 1 4 1 0 105 40 122 267 M2S090 (T) x181 - 2 4 2 1 157 40 70 267 M2S150 (T) x181 x181 2 4 4 1 151 16 126 293 M2S090 (T) x181 - 2 4 2 1 309 40 76 425 M2S050 (T) 4 x36 x364 1 8 2 1 139 62 176 377 M2S100 (T) x363 x363 2 8 2 1 292 106 176 574 M2S150 (T) x363 x363 2 16 4 1 292 106 176 574 x18 Notes: 1. DDR supports x18, x16, x9, and x8 modes 2. DDR supports x18 and x16 modes 3. DDR supports x36, x32, x18, x16, x9, and x8 modes 4. DDR supports x36, x32, x18, and x16 modes 5. Preliminary 6. Maximum SERDES rate for Mil temp devices is 3.125 Gbps VI USB MSIO (3.3 V Max) P r o d u ct B r i ef Re vi s i o n 18 SmartFusion2 System-on-Chip FPGAs Product Brief Table 4 * Programming Interfaces Available Package Devices JTAG SPI_0 Flash_GOLDEN_N System Controller SPI Port VQ144 M2S005 Yes Yes No No M2S010 Yes Yes No No M2S005 Yes Yes Yes Yes M2S010 (T) Yes Yes Yes No M2S025 (T) Yes Yes Yes No M2S025 (T) Yes Yes No No M2S050 (T) Yes Yes No No M2S090 (T) Yes Yes No No M2S005 Yes Yes Yes Yes M2S010 (T) Yes Yes Yes Yes M2S025 (T) Yes Yes Yes Yes M2S050 (T) Yes No Yes Yes M2S150 (T) Yes Yes Yes Yes M2S005 Yes Yes Yes Yes M2S010 (T) Yes Yes Yes Yes M2S025 (T) Yes Yes Yes Yes M2S050 (T) Yes No Yes Yes M2S090 (T) Yes Yes Yes Yes FCS536 M2S150 (T) Yes Yes Yes Yes FG676 M2S090 (T) Yes Yes Yes Yes FG896 M2S050 (T) Yes No Yes Yes FC1152 M2S100 (T) Yes Yes Yes Yes M2S150 (T) Yes Yes Yes Yes VF256 FCS325 VF400 FCV484 FG484 P r o du c t B r i e f R ev i si o n 1 8 VII SmartFusion2 System-on-Chip FPGAs Product Brief SmartFusion2 Ordering Information M2S050 T _ 1 G FG 896 I Application (Temperature Range) Blank = Commercial (0C to +85C Junction Temperature) I = Industrial (-40C to +100C Junction Temperature) M = Military (-55C to +125C Junction Temperature) Package Lead Count Lead-Free Packaging Blank = Standard Packaging G = RoHS-Compliant Package Type FG = Fine Pitch Ball Grid Array (1.0 mm pitch) VF = Very Fine Pitch Ball Grid Array (0.8 mm pitch) FC = Flip Chip Ball Grid Array (1.0 mm pitch) FCS = Flip Chip Ball Grid Array (0.5 mm pitch) FCV = Very Fine Pitch Flip Chip Ball Grid Array (0.8 mm pitch) VQ = Plastic Quad Flat Pack Rectangular Package (0.5 mm pitch) Speed Grade Blank = PCIe Gen 1 Support Only 1 = 15 % Faster than STD, PCIe Gen 1 and Gen 2 Prefix T = With Transceiver Blank = No Transceiver Part Number (Digits Indicate Thousands of LUTs) M2S005 * M2S010 M2S025 M2S050 M2S090 M2S100 M2S150 Note: *M2S005 devices are not available with Transceivers or in the Military temperature grade SmartFusion2 Military Temperature Devices Table 5 * SmartFusion2 Design Security Military Temperature Device Offering M2S010T-1FG484M M2S010T-1FGG484M M2S025T-1FG484M M2S025T-1FGG484M M2S050T-1FG484M M2S050T-1FGG484M M2S090T-1FG484M M2S090T-1FGG484M M2S100T-1FC1152M M2S100T-1FCG1152M M2S150T-1FC1152M M2S150T-1FCG1152M Note: Gold Wire bonds are available for the FG484 package by appending X399 to the part number when ordering, for example: M2S090T-1FG484MX399 VIII P r o d u ct B r i ef Re vi s i o n 18 SmartFusion2 System-on-Chip FPGAs Product Brief SmartFusion2 Device Status Refer to the SmartFusion2 Datasheet for device status. SmartFusion2 Datasheet and Pin Descriptions The datasheet and pin descriptions are published separately: SmartFusion2 Datasheet SmartFusion2 Pin Descriptions Marking Specification Details Microsemi normally topside marks the full ordering part number on each device. The figure below provides the details for each character code present on Microsemi's SmartFusion2 SoC FPGA devices. Device Name Date Code Package Customer Type Number Wafer Lot # Part Number Prefix Speed Grade Country of Origin Product Grade Description: * Device Name (M2XXXX): M2S for SmartFusion2 Devices Example: M2S050 * Package (PK###): Available Package as below PK: Package code: FG(G): Fine Pitch BGA, 1.00 mm pitch FC(G): Flip Chip Fine Pitch BGA with Metal LID on top, 1.00 mm pitch FCV(G): Flip Chip Very Fine Pitch BGA with Metal LID on top, 0.8 mm pitch FCS(G): Flip Chip Ultra Fine Pitch BGA with Metal LID on top, 0.5 mm pitch VF(G): Very Fine Pitch BGA, 0.8 mm pitch VQ(G): Ultra Fine Pitch Thin Quad Flat Pack, 0.5 mm pitch ###: Number of Pins: Can be three or four digits. For example,144, 256, or 1152 * Wafer Lot (AAAAAAXX): Microsemi Wafer lot # AAAAAA: Wafer lot number XX: One or two characters revision code * Speed Grade (-##): Speed Binning Number Blank: Standard speed grade -1: -1 Speed grade P r o du c t B r i e f R ev i si o n 1 8 IX SmartFusion2 System-on-Chip FPGAs Product Brief * Product grade (Z): Product Grade; assigned as follows C: Commercial ES: Engineering Samples I: Industrial M: Military Temperature PP: Pre Production * Date Code (YYWW): Assembly Date Code YY: Last two digits for seal year WW: Work week the part was sealed SS: Two blank spaces %: Can be digital number or character for new product * Customer Type Number: As specified on lot traveler * Part number Prefix: Part number prefix, assigned as below GW: Gold Wire bond Blank: Non Transceivers T: Transceivers * Country of Origin (CCD): Assembly house country location Country name: Country Code China: CHN Hong Kong: HKG Japan: JPN Korea, South: KOR Philippines: PHL Taiwan: TWN Singapore: SGP United States: USA Malaysia: MYS X P r o d u ct B r i ef Re vi s i o n 18 1 - SmartFusion2 Device Family Overview Microsemi's SmartFusion2 SoC FPGAs integrate fourth generation flash-based FPGA fabric, an ARM Cortex-M3 processor, and high-performance communications interfaces on a single chip. The SmartFusion2 FPGA is the industry's lowest power, the most secure, and has the highest reliability of any programmable logic solution. SmartFusion2 FPGAs offer up to 3.6X the gate density and up to 2X the performance of previous flash-based FPGA families and includes multiple memory blocks and multiply accumulate blocks for DSP processing. The 166 MHz ARM Cortex-M3 processor is enhanced with ETM and 8 kbyte instruction cache, and additional peripherals including CAN, Gigabit Ethernet, and high speed USB. High speed serial interfaces enable PCIe, XAUI / XGXS plus native SERDES communication while DDR2/DDR3 memory controllers provide high speed memory interfaces. SmartFusion2 Chip Layout PLLs PLLs SERDES MSS and DDR uSRAM (1 Kb) East I/Os West I/Os FPGA Fabric eNVM Math Blocks LSRAM (18 Kb) Oscillators System Controller Fabric DDR SERDES Crystal PLLs Figure 1-1 * SmartFusion2 Chip Layout R ev i si o n 1 8 1-1 SmartFusion2 Device Family Overview Reliability SmartFusion2 flash-based fabric has zero FIT configuration rate due to its single event upset (SEU) immunity, which is critical in reliability applications. The flash fabric also has the advantage that no external configuration memory is required, making the device instant-on; it retains configuration when powered off. To complement this unique FPGA capability, SmartFusion2 devices add reliability to many other aspects of the device. Single Error Correct Double Error Detect (SECDED) protection is implemented on the Cortex-M3 embedded scratch pad memory, Ethernet, CAN and USB buffers, and is optional on the DDR memory controllers. This means that if a one-bit error is detected, it will be corrected. Errors of more than one bit are detected only and not corrected. SECDED error signals are brought to the FPGA fabric to allow the user to monitor the status of these protected internal memories. Other areas of the architecture are implemented with latches, which are more resistant to SEUs. Therefore, no correction is needed in these locations: DDR bridges (MSS, MDDR, FDDR), instruction cache and MMUART, SPI, and PCIe FIFOs. Highest Security Devices Building further on the intrinsic security benefits of flash nonvolatile memory technology, the SmartFusion2 family incorporates essentially all the legacy security features that made the original SmartFusion(R), Fusion(R), IGLOO(R), and ProASIC(R)3 third-generation flash FPGAs and cSoCs the gold standard for secure devices in the PLD industry. In addition, the fourth-generation flash-based SmartFusion2 SoC FPGAs add many unique design and data security features and use models new to the PLD industry. Design Security Design security is protecting the intent of the owner of the design, such as keeping the design and associated bitstream keys confidential, preventing design changes (insertion of Trojan Horses, for example), and controlling the number of copies made throughout the device life cycle. Design security may also be known as intellectual property (IP) protection. It is one aspect of anti-tamper (AT) protection. Design security applies to the device from initial production, includes any updates such as in-the-field upgrades, and can include decommissioning of the device at the end of its life, if desired. Good design security is a prerequisite for good data security. The following are the main design security features supported: Table 1-1 * Design Security Features Features M2S005 M2S090 M2S010 M2S100 M2S025 M2S150 M2S050 Software Memory Protection Unit (MPU) x x FlashLockTM Passcode Security (256-bit) x x Flexible security settings using flash lock-bits x x Encrypted/Authenticated Design Key Loading x x Symmetric Key Design Security (256-bit) x x Design Key Verification Protocol x x Encrypted/Authenticated Configuration Loading x x Certificate-of-Conformance (C-of-C) x x Back-Tracking Prevention (also known as, Versioning) x x Device Certificate(s) (Anti-Counterfeiting) x x 1- 2 R ev isio n 1 8 SmartFusion2 System-on-Chip FPGAs Product Brief Table 1-1 * Design Security Features (continued) Features M2S005 M2S090 M2S010 M2S100 M2S025 M2S150 M2S050 Support for Configuration Variations x x Fabric NVM and eNVM Integrity Tests x x Information Services (S/N, Cert., USERCODE, and others) x x Tamper Detection x x Tamper Response (includes Zeroization) x x ECC Public Key Design Security (384-bit) x Hardware Intrinsic Design Key (SRAM-PUF) x Low Power Microsemi's flash-based FPGA fabric results in extremely low power design implementation with static power as low as 7 mW. Flash*Freeze (F*F) technology provides an ultra-low power static mode (Flash*Freeze mode) for SmartFusion2 devices, with power less than 7 mW for the largest device. F*F mode entry retains all the SRAM and register information and the exit from F*F mode achieves rapid recovery to active mode. High-Performance FPGA Fabric Built on 65 nm process technology, the SmartFusion2 FPGA fabric is composed of 4 building blocks: the logic module, the large SRAM, the micro SRAM and the mathblock. The logic module is the basic logic element and has advanced features: * A fully permutable 4-input LUT (look-up table) optimized for lowest power * A dedicated carry chain based on carry look-ahead technique * A separate flip-flop which can be used independently from the LUT The 4-input look-up table can be configured either to implement any 4-input combinatorial function or to implement an arithmetic function where the LUT output is XORed with carry input to generate the sum output. Dual-Port Large SRAM (LSRAM) Large SRAM (RAM1Kx18) is targeted for storing large memory for use with various operations. Each LSRAM block can store up to 18,432 bits. Each RAM1Kx18 block contains two independent data ports: Port A and Port B. The LSRAM is synchronous for both Read and Write operations. Operations are triggered on the rising edge of the clock. The data output ports of the LSRAM have pipeline registers which have control signals that are independent of the SRAM's control signals. Three-Port Micro SRAM (uSRAM) Micro SRAM (RAM64x18) is the second type of SRAM which is embedded in the fabric of SmartFusion2 devices. RAM64x18 uSRAM is a 3-port SRAM; it has two read ports (Port A and Port B) and one write port (Port C). The two read ports are independent of each other and can perform Read operations in both synchronous and asynchronous modes. The write port is always synchronous. The uSRAM block is approximately 1 KB (1,152 bits) in size. These uSRAM blocks are primarily targeted for building embedded FIFOs to be used by any embedded fabric masters. R ev i si o n 1 8 1-3 SmartFusion2 Device Family Overview Mathblocks for DSP Applications The fundamental building block in any digital signal processing algorithm is the multiply-accumulate function. SmartFusion2 FPGAs implement a custom 18 x18 Multiply-Accumulate (18 x18 MACC) block for efficient implementation of complex DSP algorithms such as finite impulse response (FIR) filters, infinite impulse response (IIR) filters, and fast Fourier transform (FFT) for filtering and image processing applications. Each mathblock has the following capabilities: * Supports 18x18 signed multiplications natively (A[17:0] x B[17:0]) * Supports dot product; the multiplier computes: (A[8:0] x B[17:9] + A[17:9] x B[8:0]) x 29 * Built-in addition, subtraction, and accumulation units to combine multiplication results efficiently In addition to the basic MACC function, DSP algorithms typically need small amounts of RAM for coefficients and larger RAMs for data storage. SmartFusion2 micro RAMs are ideally suited to serve the needs of coefficient storage while the large RAMs are used for data storage. Microcontroller Subsystem (MSS) The microcontroller subsystem (MSS) contains a high-performance integrated Cortex-M3 processor, running at up to 166 MHz. The MSS contains an 8 Kbyte instruction cache to provide low latency access to internal eNVM and external DDR memory. The MSS provides multiple interfacing options to the FPGA fabric in order to facilitate tight integration between the MSS and user logic in the fabric. ARM Cortex-M3 Processor The MSS uses the latest revision (r2p1) of the ARM Cortex-M3 processor. Microsemi's implementation includes the optional embedded trace macrocell (ETM) features for easier development and debug and the memory protection unit (MPU) for real-time operating system support. Cache Controller In order to minimize latency for instruction fetches when executing firmware out of off-chip DDR or on-chip eNVM, an 8 kbyte, 4-way set associative instruction cache is implemented. This provides zero wait state access for cache hits and is shared by both I and D code buses of the Cortex-M3 processor. In the event of cache misses, cache lines are filled, replacing existing cache entries based on a least recently used (LRU) algorithm. There is a configurable option available to operate the cache in a locked mode, whereby a fixed segment of code from either the DDR or eNVM is copied into the cache and locked there, so that it is not replaced when cache misses occur. This would be used for performance-critical code. It is also possible to disable the cache altogether, which is desirable in systems requiring very deterministic execution times. The cache is implemented with SEU tolerant latches. DDR Bridge The DDR bridge is a data bridge between four AHB bus masters and a single AXI bus slave. The DDR bridge accumulates AHB writes into write combining buffers prior to bursting out to external DDR memory. The DDR bridge also includes read combining buffers, allowing AHB masters to efficiently read data from the external DDR memory from a local buffer. The DDR bridge optimizes reads and writes from multiple masters to a single external DDR memory. Data coherency rules between the four masters and the external DDR memory are implemented in hardware. The DDR bridge contains three write combining / read buffers and one read buffer. All buffers within the DDR bridge are implemented with SEU tolerant latches and are not subject to the single event upsets (SEUs) that SRAM exhibits. SmartFusion2 devices implement three DDR bridges in the MSS, FDDR, and MDDR subsystems. 1- 4 R ev isio n 1 8 SmartFusion2 System-on-Chip FPGAs Product Brief AHB Bus Matrix (ABM) The AHB bus matrix (ABM) is a non-blocking, AHB-Lite multi-layer switch, supporting 10 master interfaces and 7 slave interfaces. The switch decodes access attempts by masters to various slaves, according to the memory map and security configurations. When multiple masters are attempting to access a particular slave simultaneously, an arbiter associated with that slave decides which master gains access, according to a configurable set of arbitration rules. These rules can be configured by the user to provide different usage patterns to each slave. For example, a number of consecutive access opportunities to the slave can be allocated to one particular master, to increase the likelihood of same type accesses (all reads or all writes), which makes more efficient usage of the bandwidth to the slave. System Registers The MSS System registers are implemented as an AHB slave on the AHB bus matrix. This means the Cortex-M3 processor or a soft master in the FPGA fabric may access the registers and therefore control the MSS. The System registers can be initialized by user-defined flash configuration bits on power-up. Each register also has a flash bit to enable write protecting the contents of the registers. This allows the MSS system configuration to be reliably fixed for a given application. Fabric Interface Controller (FIC) The FIC block provides two separate interfaces between the MSS and the FPGA fabric: the MSS master (MM) and fabric master (FM). Each of these interfaces can be configured to operate as AHB-Lite or APB3. Depending on device density, there are up to two FIC blocks present in the MSS (FIC_0 and FIC_1). Embedded SRAM (eSRAM) The MSS contains two blocks of 32 KB eSRAM, giving a total of 64 KB. Having the eSRAM arranged as two separate blocks allows the user to take advantage of the Harvard architecture of the Cortex-M3 processor. For example, code could be located in one eSRAM, while data, such as the stack, could be located in the other. The eSRAM is designed for Single Error Correct Double Error Detect (SECDED) protection. When SECDED is disabled, the SRAM usually used to store SECDED data may be reused as an extra 16 KB of eSRAM. Embedded NVM (eNVM) The MSS contains up to 512 KB of eNVM (64 bits wide). Accesses to the eNVM from the Cortex-M3 processor are cacheable. DMA Engines Two DMA engines are present in the MSS: high-performance DMA and peripheral DMA. High-Performance DMA (HPDMA) The high-performance DMA (HPDMA) engine provides efficient memory to memory data transfers between an external DDR memory and internal eSRAM. This engine has two separate AHB-Lite interfaces--one to the MDDR bridge and the other to the AHB bus matrix. All transfers by the HPDMA are full word transfers. Peripheral DMA (PDMA) The peripheral DMA engine (PDMA) is tuned for offloading byte-intensive operations, involving MSS peripherals, to and from the internal eSRAMs. Data transfers can also be targeted to user logic/RAM in the FPGA fabric. R ev i si o n 1 8 1-5 SmartFusion2 Device Family Overview APB Configuration Bus On every SmartFusion2 device, an APB configuration bus is present to allow the user to initialize the SERDES ASIC blocks, the fabric DDR memory controller, and user instantiated peripherals in the FPGA fabric. Peripherals A large number of communications and general purpose peripherals are implemented in the MSS. USB Controller The MSS contains a high speed USB 2.0 On-The-Go (OTG) controller with the following features: * Operates either as the function controller of a high-speed / full-speed USB peripheral or as the host/peripheral in point-to-point or multi-point communications with other USB functions. * Complies with the USB 2.0 standard for high-speed functions and with the On-The-Go supplement to the USB 2.0 specification. * Supports OTG communications with one or more high-speed, full-speed, or low-speed devices. TSE Ethernet MAC The triple speed Ethernet (TSE) MAC supports IEEE 802.3 10/100/1000Mbps Ethernet operation. The following PHY interfaces are directly supported by the MAC: * GMII * MII * TBI The Ethernet MAC hardware implements the following functions: * 4 KB internal transmit FIFO and 8 KB internal receive FIFO * IEEE 802.3X full-duplex flow control * DMA of Ethernet frames between internal FIFOs and system memory (such as eSRAM or DDR) * Cut-through operation * SECDED protection on internal buffers SGMII PHY Interface SGMII mode is implemented by means of configuring the MAC for 10-bit interface (TBI) operation, allocating one of the high-speed serial channels to SGMII, and by implementing custom logic in the fabric. 10 Gbps Ethernet Support for 10 Gbps Ethernet is achieved by programming the SERDES interface to XAUI mode. In this mode, a soft 10G EMAC with XGMII interface can be directly connected to the SERDES interface. Communication Block (COMM_BLK) The COMM block provides a UART-like communications channel between the MSS and the system controller. System services are initiated through the COMM block. SPI The serial peripheral interface controller is compliant with the Motorola SPI, Texas Instruments synchronous serial, and National Semiconductor MICROWIRETM formats. In addition, the SPI supports interfacing to large SPI flash and EEPROM devices by way of the slave protocol engine. The SPI controller supports both Master and Slave modes of operation. The SPI controller embeds two 4x32 (depth x width) FIFOs for receive and transmit. These FIFOs are accessible through Rx data and Tx data registers. Writing to the Tx data register causes the data to be written to the transmit FIFO. This is emptied by transmit logic. Similarly, reading from the Rx data register causes data to be read from the receive FIFO. 1- 6 R ev isio n 1 8 SmartFusion2 System-on-Chip FPGAs Product Brief Multi-Mode UART (MMUART) SmartFusion2 devices contain two identical multi-mode universal asynchronous/synchronous receiver/transmitter (MMUART) peripherals that provide software compatibility with the popular 16550 device. They perform serial-to-parallel conversion on data originating from modems or other serial devices, and perform parallel-to-serial conversion on data from the Cortex-M3 processor to these devices. The following are the main features supported: * Fractional baud rate capability * Asynchronous and synchronous operation * Full programmable serial interface characteristics - * Data width is programmable to 5, 6, 7, or 8 bits - Even, odd, or no-parity bit generation/detection - 1,11/2, and 2 stop bit generation 9-bit address flag capability used for multidrop addressing topologies 2 I C SmartFusion2 devices contain two identical master/slave I2C peripherals that perform serial to-parallel conversion on data originating from serial devices, and perform parallel-to-serial conversion on data from the ARM Cortex-M3 processor, or any other bus master, to these devices. The following are the main features supported: * I2C v2.1 - 100 Kbps - 400 Kbps * Dual-slave addressing * SMBus v2.0 * PMBus v1.1 Clock Sources: On-Chip Oscillators, PLLs, and CCCs SmartFusion2 devices have two on-chip RC oscillators--a 1 MHz RC oscillator and a 50 MHz RC oscillator--and up to two main crystal oscillators (32 KHz-20 MHz). These are available to the user for generating clocks to the on-chip resources and the logic built on the FPGA fabric array. The second crystal oscillator available on the SmartFusion2 devices is dedicated for RTC clocking. These oscillators (except the RTC crystal oscillator) can be used in conjunction with the integrated user phase-locked loops (PLLs) and fabric clock conditioning circuits (FAB_CCC) to generate clocks of varying frequency and phase. In addition to being available to the user, these oscillators are also used by the system controller, power-on reset circuitry, MSS during Flash*Freeze mode, and the RTC. SmartFusion2 devices have up to eight fabric CCC (FAB_CCC) blocks and a dedicated PLL associated with each CCC to provide flexible clocking to the FPGA fabric portion of the device. The user has the freedom to use any of the eight PLLs and CCCs to generate the fabric clocks and the internal MSS clock from the base fabric clock (CLK_BASE). There is also a dedicated CCC block for the MSS (MSS_CCC) and an associated PLL (MPLL) for MSS clocking and de-skewing the CLK_BASE clock. The fabric alignment clock controller (FACC), part of the MSS CCC, is responsible for generating various aligned clocks required by the MSS for correct operation of the MSS blocks and synchronous communication with the user logic in the FPGA fabric. R ev i si o n 1 8 1-7 SmartFusion2 Device Family Overview High Speed Serial Interfaces SERDES Interface SmartFusion2 has up to four 5 Gbps SERDES transceivers, each supporting the following: * 4 SERDES lanes * The native SERDES interface facilitates implementation of Serial RapidIO (SRIO) in fabric or an SGMII interface for the Ethernet MAC in MSS PCI Express (PCIe) PCIe is a high speed, packet-based, point-to-point, low pin count, serial interconnect bus. The SmartFusion2 family has two hard high-speed serial interface blocks. Each SERDES block contains a PCIe system block. The PCIe system is connected to the SERDES block and following are the main features supported: * Supports x1, x2, and x4 lane configuration * Endpoint configuration only * PCI Express Base Specification Revision 2.0 * 2.5 and 5.0 Gbps compliant * Embedded receive (2 KB), transmit (1 KB) and retry (1 KB) buffer dual-port RAM implementation * Up to 2 kbytes maximum payload size * 64-bit AXI or 32-bit AHB-Lite Master and Slave interface to the application layer * 32-bit APB interface to access configuration and status registers of PCIe system * Up to 3 x 64 bit base address registers * 1 virtual channel (VC) XAUI/XGXS Extension The XAUI/XGXS extension allows the user to implement a 10 Gbps (XGMII) Ethernet PHY interface by connecting the Ethernet MAC fabric interface through an appropriate soft IP block in the fabric. High Speed Memory Interfaces: DDRx Memory Controllers There are up to three DDR subsystems, MDDR (MSS DDR) and FDDR (fabric DDR) present in SmartFusion2 devices. Each subsystem consists of a DDR controller, PHY, and a wrapper. The MDDR has an interface from the MSS and fabric, and FDDR provides an interface from the fabric. The following are the main features supported by the FDDR and MDDR: 1- 8 * Support for LPDDR, DDR2, and DDR3 memories * Simplified DDR command interface to standard AMBA AXI/AHB interface * Up to 667 Mbps (333 MHz double data rate) performance * Supports 1, 2, or 4 ranks of memory * Supports different DRAM bus width modes: x8, x9, x16, x18, x32, and x36 * Supports DRAM burst length of 2, 4, or 8 in full bus-width mode; supports DRAM burst length of 2, 4, 8, or 16 in half bus-width mode * Supports memory densities up to 4 GB * Supports a maximum of 8 memory banks * SECDED enable/disable feature * Embedded physical interface (PHY) * Read and Write buffers in fully associative CAMs, configurable in powers of 2, up to 64 Reads plus 64 Writes R ev isio n 1 8 SmartFusion2 System-on-Chip FPGAs Product Brief * Support for dynamically changing clock frequency while in self-refresh * Supports command reordering to optimize memory efficiency * Supports data reordering, returning critical word first for each command MDDR Subsystem The MDDR subsystem has two interfaces to the DDR. One is an AXI 64-bit bus from the DDR bridge within the MSS. The other is a multiplexed interface from the FPGA fabric, which can be configured as either a single AXI 64-bit bus or two 32-bit AHB-Lite buses. There is also a 16-bit APB configuration bus, which is used to initialize the majority of the internal registers within the MDDR subsystem after reset. This APB configuration bus can be mastered by the MSS directly or by a master in the FPGA fabric. Support for 3.3 V Single Data Rate DRAMs (SDRAM) can be obtained by using the SMC_FIC interface in the MDDR subsystem. Users would then instantiate a soft AHB or AXI SDRAM memory controller in the FPGA fabric and connect I/O ports to 3.3 V MSIO. FDDR Subsystem The FDDR subsystem has one interface to the DDR. This is a multiplexed interface from the FPGA fabric, which can be configured as either a single AXI 64-bit bus or two 32-bit AHB-Lite buses. There is also a 16-bit APB configuration bus, which is used to initialize the majority of the internal registers within the FDDR subsystem after reset. This APB configuration bus can be mastered by the MSS or a master in the FPGA fabric. SmartFusion2 Development Tools Design Software System designers can leverage the easy-to-use Libero(R)system-on-chip (SoC) software toolset for designing SmartFusion2 devices. Libero SoC highlights include the following: * System Builder for creation of system level architecture * Synthesis, DS,P and debug support from Synopsys * Simulation from Mentor Graphics * Push-button design flow with power analysis and timing analysis * SmartDebug for access to non-invasive probes within SmartFusion2 devices * Integrated firmware flows for SoftConsole (GNU/Eclipse), IAR(R), and KeilTM * Operating system support includes uClinuxTM from Emcraft Systems, FreeRTOSTM, SAFERTOS(R) and uc/OS-IIITM from Micrium. For more information refer to Libero SoC, Design Hardware SmartFusion2 hardware is now available in a starter kit and development kit format. The starter kit is recommended for initial evaluation and the development kit for full system design and prototyping. R ev i si o n 1 8 1-9 SmartFusion2 Device Family Overview Table 1-2 * SmartFusion2 Kits SmartFusion2 Starter Kit The SmartFusion2 Starter Kit provides a cost effective platform for evaluation and development of a SmartFusion2 SoC FPGA based solution. The kit utilizes a miniature mezzanine form factor system-onmodule, which integrates the SmartFusion2 device with 64 MB LPDDR, 16 MB SPI flash, and Ethernet PHY. The baseboard provides easy to use benchtop access to the SmartFusion2 SoC and interfaces. SmartFusion2 Development Kit The SmartFusion2 full feature development kit provides access to all peripherals of the SmartFusion2 device, including use of the SERDES, DDR, CAN, USB, and other embedded peripherals. Application-specific daughtercards are also in development for use with this kit. The SmartFusion2 Motor Control Kit will support up to 6-axis motor control and is currently in development This is used in conjunction with the SmartFusion2 Development Kit. The SmartFusion2 Micro Power Manager (MPM) Daughtercard will be the next revision in MPM system management platforms. This is used in conjunction with the SmartFusion2 Development Kit. IP Cores SmartFusion2 SoC FPGAs contain an ARM Cortex-M3 processor and multiple peripherals hardcoded into the device. In addition to these, Microsemi offers many soft peripherals that can be placed in the FPGA fabric of the device. These include Core429, Core1553, CoreJESD204BRX/TX, CoreFRI, CoreFFT, and many other DirectCores. Refer to IP Cores for more information. . 1- 10 R ev i sio n 1 8 2 - Product Brief Information List of Changes1-V The following table lists critical changes that were made in each revision of the SmartFusion2 Product Brief. Revision Changes Revision 18 Ordering information added to Table 2 for the M2S090(T) device in the FCS/FCSG325 (October 2014) package. Trademark changed to the Register mark for ARM Cortex-M3. Page 1-V, 1-I Revision 17 (August 2014) Updated Device Packages 005-VF256 and 150-FCS536 in Table 2-Table 4. 1-V-1-VII Revision 16 (June 2014) Updated Table 2, Table 3, and Table 4. 1-V, 1-VI, 1-VII Revision 15 (March 2014) Table 1 to Table 3 and "SmartFusion2 Ordering Information" were updated with 1-IV-1-VI Military device data. Table 4 and Table 5 and the "Marking Specification Details" 1-VIII,1-VII section were added. 1-VIII,1-IX Revision 14 (Dec 2013) Tables 3-6 were combined into Table 3. Fabric Interface Controller features were added to "SmartFusion2 SoC FPGA Product Family" table. Packages VQ144 and FCV484 were added to Table 2 and Table 3. 1-VI,1-IV 1-V,1-VI Revision 13 (Nov 2013) Data Security Feature sections, table and Device Status table were removed. "SmartFusion2 SoC FPGA Block Diagram" was updated. N/A 1-III Revision 12 (Oct 2013) Packages FCS325 and VF256 were added to Table 2. "SmartFusion2 Ordering Information" on page 1-VIII was updated. Typo fixed on "SmartFusion2 SoC FPGA Block Diagram" on page 1-III. 1-V,1-VIII Revision 11 (Sept 2013) LSRAM x32/36 widths added. "SmartFusion2 SoC FPGA Product Family" table note added referring to updates in Table 2 -Table 4 and Table 6. 1-IV "SmartFusion2 Ordering Information" was updated. Part Numbers (tables 7 and 8) were removed. "SmartFusion2 Device Status" table updated. 1-VIII M2S090-FG676 and M2S005-VF400 package pinouts finalized. N/A Revision 10 (June 2013) M2S005-FG484 package pinout I/O count finalized. Typos were corrected. N/A Revision 9 (May 2013) A note regarding total logic was added to Table 1 * SmartFusion2 SoC FPGA Product Family. 1-IV "Design Security Features" and "Additional Security Features" tables were added to show the security features supported. 1-2 R ev i si o n 1 8 2-1 Product Brief Information Revision Changes Page The "SmartFusion2 SoC FPGA Block Diagram" was revised to clarify the connections between the Cortex-M3 processor and cache (SAR 45967). III I/O counts were updated in Table 1 * SmartFusion2 SoC FPGA Product Family (SAR 46000). IV I/O counts and devices were updated. The FG676 package was added to Table 2 * I/Os per Package and Package Options (SAR 46000). V "Features per Device/Package Combination" was divided into four new tables, Table 3 through Table 6 to accommodate new features for package/device combinations for the FG676 package, for T and non-T devices (SAR 46000). VI The status for M2S050T was changed from Advance to Preliminary in the "SmartFusion2 Device Status" section (SAR 46967). IX The SmartFusion2 product brief has been separated from the rest of the SmartFusion2 datasheet. The "SmartFusion2 Development Tools " section has been updated and is now part of the product brief (SAR 45184). 1-9 The M2S090 device is new. The product family tables and ordering information have been updated (SAR 45127). IV Revision 6 (Feb 2013) The number of PLLs and CCCs for MS2025 was corrected from 4 to 6 (SAR 44480). IV Revision 5 (Feb 2013) Table 1 * SmartFusion2 SoC FPGA Product Family and Table 2 * I/Os per Package and Package Options were revised to correct I/O counts for M2S005/M2S025 and the VF400 and FG484 packages (SAR 42618). IV Junction temperature for military, industrial, and commercial SmartFusion2 SoC FPGAs was added to the "Reliability" section. In the "Operating Voltage and I/Os" section, "Market leading number of user I/Os with 5G SERDES" was added to the (SAR 42618). LVTTL/LVCMOS 3.3 V was qualified as MSIO only and DDR was removed from the list under DDRIOs (SAR 44652). I, II Table 3 * Features per Device/Package Combination is new (SARs 42618, 44414). VI RMII was removed from as a supported PHY interface in the "TSE Ethernet MAC" section (SAR 42618). 1-6 Revision 8 (April 2013) Revision 7 (Feb 2013) 2- 2 R ev isio n 1 8 SmartFusion2 System-on-Chip FPGAs Product Brief Revision Changes Revision 4 The "SmartFusion2 Ordering Information" was revised to add Pre-Production as a (January 2013) temperature range. Ambient temperature was corrected to junction temperature in the defined temperature ranges. Speed grades were defined. Table 8 SmartFusion2 Valid Lead-Free Part Numbers for Devices with Design Security is new (SAR 43648). Page VIII, NA The maximum payload size for PCIe was corrected from 256 bytes to "up to 2 kbytes" (SAR 42215). II, 1-8 More information was included on SDRAM Support in the "High Speed Memory Interfaces" section (SAR 42594). II The phrase "with 16-bit PIPE interface (Gen1/Gen2)" was removed from the PCIe bullet in the "High Speed Serial Interfaces" section (SAR 43851). II In Table 1 * SmartFusion2 SoC FPGA Product Family, PCIe Endpoint x4 was corrected to PCIe Endpoint x1, x2, x4 (SAR 43851). IV The number of I/Os for M2S025 in the FG484 package was corrected from 267 to 289 in Table 2 * I/Os per Package and Package Options (SAR 42618). V The Y Security designator was removed from "SmartFusion2 Ordering Information" (SAR 42231). VIII The "SGMII PHY Interface" section was revised to change "allocating one of the highspeed serial channels to SGMII and by implementing custom logic in the fabric" to "allocating one of the high-speed serial channels to and utilizing the CoreTBI soft IP block" (SAR 43851). 1-6 The "PCI Express (PCIe)" section was corrected to state the SmartFusion2 family has up to four high-speed serial interface blocks rather than two. The following bullets were removed (SAR 43851): 1-8 * Intel's PIPE interface (8-bit/16-bit) to interface between the PHY MAC and PHY (SERDES) * Fully compliant PHY PCS sub-layer (125/250 MHz) "Support for SDRAM memories" was removed from the "High Speed Memory Interfaces: DDRx Memory Controllers " section (SAR 42594). The text was corrected to state there are up to three, rather than two, DDR subsystems (SAR 43851). 1-8 The "MDDR Subsystem" section was revised to explain that support for 3.3 V Single Data Rate DRAMs (SDRAM) can be obtained by using the SMC_FIC interface (SAR 42594). 1-9 The "FDDR Subsystem" section was revised to remove the statement that the APB configuration bus can be mastered by the MSS directly (SAR 42594). 1-9 The "SmartFusion2 Development Tools "chapter was revised to indicate that Libero SoC includes SoftConsole (GNU/Eclipse) (SAR 41972). 1-9 Revision 3 The "SmartFusion2 SoC FPGA Block Diagram" was updated. Table 7 SmartFusion2 (October 2012) Valid Part Numbers for Devices with Design Security is new. III, N/A Revision 2 (July 2012) Information was updated based on ongoing development of specifications. N/A Revision 1 (June 2012) Information was reorganized and updated based on ongoing development of specifications. N/A R ev i si o n 1 8 2-3 Product Brief Information Datasheet Categories Categories In order to provide the latest information to designers, some datasheet parameters are published before data has been fully characterized from silicon devices. The data provided for a given device, as highlighted in the "SmartFusion2 Device Status" table on page IX, is designated as either "Product Brief," "Advance," "Preliminary," or "Production." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized. Preliminary The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Production This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Safety Critical, Life Support, and High-Reliability Applications Policy The products described in this advance status document may not have completed the Microsemi qualification process. Products may be amended or enhanced during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult the Microsemi SoC Products Group Terms and Conditions for specific liability exclusions relating to life-support applications. For more information covering all of the SoC Products Group's products refer to the Reliability Report. Microsemi also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local sales office for additional reliability information. Microsemi Corporate Headquarters One Enterprise, Aliso Viejo, CA 92656 USA. Within the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 Sales.Support@Microsemi.com 2- 4 R ev isio n 1 8 Microsemi Corporate Headquarters One Enterprise, Aliso Viejo CA 92656 USA Within the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 E-mail: sales.support@microsemi.com Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for communications, defense & security, aerospace and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; security technologies and scalable anti-tamper products; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif., and has approximately 3,400 employees globally. Learn more at www.microsemi.com. (c) 2014 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. 51700115PB-18/10.14