K3P7V(U)1000B-GC CMOS MASK ROM 64M-Bit (8Mx8 /4Mx16) CMOS MASK ROM FEATURES GENERAL DESCRIPTION * Switchable organization 8,388,608 x 8(byte mode) 4,194,304 x 16(word mode) * Fast access time Random Access Time/Page Access Time 3.3V Operation : 100/30ns(Max.)@CL=50pF, 120/40ns(Max.)@C L=100pF 3.0V Operation : 120/40ns(Max.)@CL=100pF 8 Words / 16 Bytes page access * Supply voltage : single +3.0V/ single +3.3V * Current consumption Operating : 60mA(Max.) Standby : 50A(Max.) * Fully static operation * All inputs and outputs TTL compatible * Three state outputs * Package K3P7V(U)1000B-GC : 44-SOP-600 The K3P7V(U)1000B-GC is a fully static mask programmable ROM fabricated using silicon gate CMOS process technology, and is organized either as 8,388,608 x 8 bit(byte mode) or as 4,194,304 x 16 bit(word mode) depending on BHE voltage level.(See mode selection table) This device includes page read mode function, page read mode allows 8 words (or 16 bytes) of data to read fast in the same page, CE and A 3 ~ A21 should not be changed. This device operates with 3.0V or 3.3V power supply, and all inputs and outputs are TTL compatible. Because of its asynchronous operation, it requires no external clock assuring extremely easy operation. It is suitable for use in program memory of microprocessor, and data memory, character generator. The K3P7V(U)1000B-GC is packaged in a 44-SOP. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION A21 . . . . . . . . A3 A0~A2 A-1 X BUFFERS AND DECODER MEMORY CELL MATRIX (4,194,304x16/ 8,388,608x8) SENSE AMP. Y BUFFERS AND DECODER DATA OUT BUFFERS . . . A21 1 44 A20 A18 2 43 A19 A17 3 42 A8 A7 4 41 A9 A6 5 40 A10 A5 6 39 A11 A4 7 38 A12 A3 8 37 A13 A2 9 36 A14 A1 10 35 A15 A0 11 34 A16 CE 12 VSS 13 CE Q0/Q8 CONTROL LOGIC OE BHE Pin Name Pin Function A0 - A 2 Page Address Inputs A3 - A 21 Address Inputs Q0 - Q14 Data Outputs Q15 /A-1 Output 15(Word mode)/ LSB Address(Byte mode) BHE Word/Byte selection CE Chip Enable OE Output Enable VCC Power VSS Ground Q7/Q15 SOP 33 BHE 32 VSS OE 14 31 Q15/A-1 Q0 15 30 Q7 Q8 16 29 Q14 Q1 17 Q9 18 28 Q6 Q2 19 26 Q5 Q10 20 25 Q12 27 Q13 Q3 21 24 Q4 Q11 22 23 VCC K3P7V(U)1000B-GC K3P7V(U)1000B-GC CMOS MASK ROM ABSOLUTE MAXIMUM RATINGS Item Voltage on Any Pin Relative to VSS Symbol Rating Unit VIN -0.3 to +4.5 V Temperature Under Bias TBIAS -10 to +85 C Storage Temperature TSTG -55 to +150 C NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70C) Symbol Min Typ Max Unit Supply Voltage Item VCC 2.7/3.0 3.0/3.3 3.3/3.6 V Supply Voltage VSS 0 0 0 V DC CHARACTERISTICS Parameter Symbol Test Conditions Min 60 mA mA CE=VIH, all outputs open 500 A CE=VCC, all outputs open 50 A ICC Cycle=5MHZ, all outputs open, CE=OE=VIL, VIN=0.45V to 2.4V (AC Test Condition) Standby Current(TTL) ISB1 Standby Current(CMOS) ISB2 - Unit 50 Operating Current VCC=3.3V0.3V Max VCC=3.0V0.3V Input Leakage Current ILI VIN=0 to V CC - 10 A Output Leakage Current ILO VOUT=0 to VCC - 10 A Input High Voltage, All Inputs VIH 2.0 VCC+0.3 V Input Low Voltage, All Inputs VIL -0.3 0.6 V Output High Voltage Level VOH IOH=-400A 2.4 - V Output Low Voltage Level VOL IOL=2.1mA - 0.4 V NOTE : Minimum DC Voltage(V IL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input pins(VIH) is V CC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. MODE SELECTION CE OE BHE Q15/A-1 Mode Data Power H X X X Standby High-Z Standby L H L L X X Operating High-Z Active H Output Operating Q0~Q15 : Dout Active L Input Operating Q0~Q7 : Dout Q8~Q14 : Hi-Z Active CAPACITANCE(TA=25C, f=1.0MHz) Item Output Capacitance Input Capacitance Symbol Test Conditions Min Max Unit COUT VOUT=0V - 12 pF CIN VIN=0V - 12 pF NOTE : Capacitance is periodically sampled and not 100% tested. K3P7V(U)1000B-GC CMOS MASK ROM AC CHARACTERISTICS(TA=0C to +70C, VCC=3.3V/3.0V0.3V, unless otherwise noted.) TEST CONDITIONS Item Value Input Pulse Levels 0.45V to 2.4V Input Rise and Fall Times 10ns Input and Output timing Levels 1.5V Output Loads 1 TTL Gate and CL=50pF or 100pF READ CYCLE Item Symbol K3P7V1000B-GC10 (C L=50pF) Min Max Min Max Min Unit Max tRC Chip Enable Access Time tACE 100 120 120 ns Address Access Time tAA 100 120 120 ns Page Address Access Time tPA 30 40 40 ns Output Enable Access Time tOE 30 40 40 ns Output or Chip Disable to Output High-Z tDF 20 20 20 ns Output Hold from Address Change tOH 0 120 K3P7U1000B-GC12 (CL=100pF) Read Cycle Time NOTE : Page Address is determined as below. Word mode (BHE=VIH) : A 0, A1, A2 Byte mode (BHE=V IL) : A-1, A0, A1, A2 100 K3P7V1000B-GC12 (CL=100pF) 0 120 0 ns ns K3P7V(U)1000B-GC CMOS MASK ROM TIMING DIAGRAM READ ADD A0~A21 A-1(*1) ADD1 ADD2 tRC tDF(*3) tACE CE tOE tAA OE tOH DOUT D0~D7 D8~D15(*2) VALID DATA VALID DATA PAGE READ CE tDF(*3) OE ADD A3~A21 ADD A0,A1,A2 A -1(*1) 1 st tAA tPA VALID DATA VALID DATA VALID DATA VALID DATA DOUT D0~D7 D8~D15(*2) 3 rd 2 nd NOTES : *1.Byte Mode only. A-1 is Least Significant Bit Address.(BHE = VIL) *2. Word Mode only.(BHE = VIH) *3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.