© Semiconductor Components Industries, LLC, 2010
September, 2010 − Rev. 18
1Publication Order Number:
NCV8664/D
NCV8664
Very Low Iq Low Dropout
Linear Regulator
The NCV8664 is a precision 3.3 V and 5.0 V fixed output, low
dropout integrated voltage regulator with an output current
capability of 150 mA. Careful management of light load current
consumption, combined with a low leakage process, achieve a
typical quiescent current of 22 A.
NCV8664 is pin and functionally compatible with NCV4264 and
NCV4264−2, and it could replace these parts when very low
quiescent current is required.
The output voltage is accurate within 2.0%, and maximum
dropout voltage is 600 mV at full rated load current.
It is internally protected against input supply reversal, output
overcurrent faults, and excess die temperature. No external
components are required to enable these features.
Features
•3.3 V, 5.0 V Fixed Output
•2.0% Output Accuracy, Over Full Temperature Range
•30 A Maximum Quiescent Current at IOUT = 100 A
•600 mV Maximum Dropout Voltage at 150 mA Load Current
•Wide Input Voltage Operating Range of 4.5 V to 45 V
•Internal Fault Protection
♦−42 V Reverse Voltage
♦Short Circuit/Overcurrent
♦Thermal Overload
•NCV Prefix for Automotive and Other Applications Requiring Site
and Control Changes
•AEC−Q100 Qualified
•EMC Compliant
•These are Pb−Free Devices
SOT−223
ST SUFFIX
CASE 318E
PIN CONNECTIONS
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MARKING
DIAGRAMS
xx = Voltage Rating DPAK
(50 = 5.0 V Version)
(33 = 3.3 V Version)
x = Voltage Rating SOT223
(5 = 5.0 V Version)
(3 = 3.3 V Version)
A = Assembly Location
L = Wafer Lot
Y = Year
W, WW = Work Week
G or G = Pb−Free Package
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
ORDERING INFORMATION
123
TAB
12
3
4V664xxG
ALYWW
DPAK
DT SUFFIX
CASE 369C
(SOT−223/DPAK)
PIN FUNCTION
1V
IN
2,TAB GND
3V
OUT
1
1
AYW
V664xG
G
(Note: Microdot may be in either location)
1
8SOIC−8 Fused
CASE 751
V664x
ALYWX
G
1
8
(SOIC−8 Fused)
PIN FUNCTION
1NC
2, VIN
3 GND
4. VOUT
5−8. NC
NCV8664
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2
IN
Bias Current
Generators
1.3 V
Reference +
-
Error
Amp
Thermal
Shutdown
OUT
GND
Figure 1. Block Diagram
PIN FUNCTION DESCRIPTION
Pin No.
Symbol Function
DPAK/SOT−223 SOIC−8
1 2 VIN Unregulated input voltage; 4.5 V to 45 V.
2 3 GND Ground; substrate.
3 4 VOUT Regulated output voltage; collector of the internal PNP pass transistor.
TAB −GND Ground; substrate and best thermal connection to the die.
−1, 5−8 NC No Connection.
OPERATING RANGE
Pin Symbol, Parameter Symbol Min Max Unit
VIN, DC Input Operating Voltage VIN 4.5 +45 V
Junction Temperature Operating Range TJ−40 +150 °C
MAXIMUM RATINGS
Rating Symbol Min Max Unit
VIN, DC Voltage VIN −42 +45 V
VOUT
, DC Voltage VOUT −0.3 +18 V
Storage Temperature Tstg −55 +150 °C
ESD Capability, Human Body Model (Note 1) VESDHB 4000 −V
ESD Capability, Machine Model (Note 1) VESDMIM 200 −V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series incorporates ESD protection and is tested by the following methods:
ESD HBM tested per AEC−Q100−002 (EIA/JESD22−A 114C)
ESD MM tested per AEC−Q100−003 (EIA/JESD22−A 115C)
THERMAL RESISTANCE
Parameter Symbol Condition Min Max Unit
Junction−to−Ambient DPAK
SOT−223
SOIC−8 Fused
RJA −
−
−
101 (Note 2)
99 (Note 2)
145
°C/W
Junction−to−Case DPAK
SOT−223
SOIC−8 Fused
RJC −
−
−
9.0
17
−
°C/W
2. 1 oz., 100 mm2 copper area.
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3
LEAD SOLDERING TEMPERATURE AND MSL
Rating Symbol Min Max Unit
Lead Temperature Soldering
Reflow (SMD Styles Only), Lead Free (Note 3)
Tsld
−265 pk
°C
Moisture Sensitivity Level SOT223
DPAK
SOIC−8 Fused
MSL 3
2
1
−
−
−
−
3. Lead Free, 60 sec – 150 sec above 217°C, 40 sec max at peak.
ELECTRICAL CHARACTERISTICS (VIN = 13.5 V, Tj = −40°C to +150°C, unless otherwise noted.)
Characteristic Symbol Test Conditions Min Typ Max Unit
Output Voltage
5.0 V Version
VOUT 0.1 mA IOUT 150 mA (Note 4)
6.0 V VIN 28 V
4.900 5.000 5.100 V
Output Voltage
5.0 V Version
VOUT 0 mA IOUT 150 mA
5.5 V VIN 28 V
−40°C TJ 125°C
4.900 5.000 5.100 V
Output Voltage
3.3 V Version
VOUT 0.1 mA IOUT 150 mA (Note 4)
4.5 V VIN 28 V
3.234 3.300 3.366 V
Line Regulation
5.0 V Version
VOUT vs. VIN IOUT = 5.0 mA
6.0 V VIN 28 V
−25 5.0 +25 mV
Line Regulation
3.3 V Version
VOUT vs. VIN IOUT = 5.0 mA
4.5 V VIN 28 V
−25 5.0 +25 mV
Load Regulation VOUT vs. IOUT 1.0 mA IOUT 150 mA
(Note 4)
−35 5.0 +35 mV
Dropout Voltage
5.0 V Version
VIN−VOUT IQ = 100 mA (Notes 4 & 5)
IQ = 150 mA (Notes 4 & 5)
−
−
265
315
500
600
mV
Dropout Voltage
3.3 V Version
VIN−VOUT IQ = 100 mA (Notes 4 & 7)
IQ = 150 mA (Notes 4 & 7)
−
−
−
−
1.266
1.266
V
Quiescent Current IqIOUT = 100 A
TJ = 25°C
TJ = −40°C to +85°C
−
−
21
22
29
30
A
Active Ground Current IG(ON) IOUT = 50 mA (Note 4)
IOUT = 150 mA (Note 4)
−
−
1.3
8.0
3
15
mA
Power Supply Rejection PSRR VRIPPLE = 0.5 VP−P
, F = 100 Hz −67 −dB
Output Capacitor for Stability
5.0 V Version
COUT
ESR
IOUT = 0.1 mA to 150 mA
(Note 4)
10
−
−
−
−
9.0
F
Output Capacitor for Stability
3.3 V Version
COUT
ESR
IOUT = 0.1 mA to 150 mA
(Note 4)
22
−
−
−
−
18
F
PROTECTION
Current Limit IOUT(LIM) VOUT = 4.5 V (5.0 V Version) (Note 4)
VOUT = 3.0 V (3.3 V Version) (Note 4)
150
150
−
−
500
500
mA
Short Circuit Current Limit IOUT(SC) VOUT = 0 V (Note 4) 100 −500 mA
Thermal Shutdown Threshold TTSD (Note 6) 150 −200 °C
4. Use pulse loading to limit power dissipation.
5. Dropout voltage = (VIN – VOUT), measured when the output voltage has dropped 100 mV relative to the nominal value obtained with VIN = 13.5 V.
6. Not tested in production. Limits are guaranteed by design.
7. VDO = VIN − VOUT
. For output voltage set to < 4.5 V, VDO will be constrained by the minimum input voltage.
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4
8664
13
2
Vout
COUT
10 F, 5.0 V Version
22 F, 3.3 V Version
CIN
1.0 F
GND
4.5−45 V
Input
Figure 2. Measurement Circuit
Figure 3. Applications Circuit
8664
13
2
Vout
COUT
10 F, 5.0 V Version
22 F, 3.3 V Version
Output
CIN
100 nF
GND
4.5−45 V
Input
RL
Output
Vin
Vin
100 nF
IQ
II
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5
Typical Curves
Iout = 100 mA
−40°C
125°C
25°C
Figure 4. ESR Characterization, 5.0 V Version Figure 5. Output Voltage vs. Input Voltage,
5.0 V Version
LOAD CURRENT (mA) INPUT VOLTAGE (V)
140120100806040200
0.01
10
100
1000
7.06.05.04.03.02.01.00
0
1.0
2.0
3.0
4.0
5.0
6.0
Figure 6. Current Consumption vs. Output
Load, 5.0 V Version
OUTPUT CURRENT (mA)
150100500
0
2.0
4.0
9.0
ESR ()
OUTPUT VOLTAGE (V)
QUIESCENT CURRENT (mA)
180160
Maximum ESR
Cout = 10, 22 F
Stable Region Vin = 13.5 V
6.0
8.0
7.0
200
8.0
Figure 7. Current Consumption vs. Output
Load (Low Load), 5.0 V Version
OUTPUT CURRENT (mA)
15105.00
0
0.05
0.10
0.15
0.30
0.35
0.40
QUIESCENT CURRENT (mA)
0.25
20
−40°C
125°C
25°C
0.20
Figure 8. Quiescent Current vs. Temperature,
5.0 V Version
TEMPERATURE (°C)
10050−50
0
5.0
15
45
QUIESCENT CURRENT (A)
20
30
35
Figure 9. Quiescent Current vs. Temperature,
5.0 V Version
TEMPERATURE (°C)
500−50
0
2.0
4.0
8.0
10
12
QUIESCENT CURRENT (mA)
6.0
10
25
40
0 150
Iout = 150 mA
100 150
Vin = 13.5 V Vin = 13.5 V
Vin = 13.5 V
Vin = 13.5 V
Iout = 100 A
1.0
3.0
5.0
1.0
0.1
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6
Typical Curves
RL = 50
RL = 100
TA = 25°C
TA = 125°C
Figure 10. Dropout Voltage vs. Output Load,
5.0 V Version
Figure 11. Current Consumption vs. Input
Voltage, 5.0 V Version
OUTPUT LOAD (mA) INPUT VOLTAGE (V)
150100500
0
0.15
0.30
0.45
50403020100
0
18
2.0
10
4.0
14
16
Figure 12. Output Current vs. Input Voltage,
5.0 V Version
INPUT VOLTAGE (V)
4030100
0
20
40
160
DROPOUT (V)
CURRENT CONSUMPTION (mA)
OUTPUT CURRENT (mA)
200
125°C
60
80
100
50
Figure 13. Output Voltage vs. Temperature,
5.0 V Version
TEMPERATURE (°C)
100500−50
4.90
4.92
4.94
4.98
5.06
5.08
5.10
OUTPUT VOLTAGE (V)
5.02
150
5.00
Figure 14. Current Limit vs. Temperature,
5.0 V Version
TEMPERATURE (°C)
150100−50
0
50
100
400
OUTPUT CURRENT (mA)
200
250
350
25°C
−40°C
0.05
0.10
0.20
0.25
0.35
0.40
6.0
8.0
12
4.96
5.04
20
140
120
500
150
300
Vin = 13.5 V
Vin = 13.5 V
Load = 10 mA
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Typical Curves
Iout = 100 mA
Iout = 150 mA
−40°C
125°C
25°C
Figure 15. ESR Stability, 3.3 V Version Figure 16. Output Voltage vs. Input Voltage,
3.3 V Version
OUTPUT LOAD (mA) INPUT VOLTAGE (V)
1007550250
0
50
60
100
403020100
0
1.0
1.5
2.0
2.5
3.0
3.5
Figure 17. Current Consumption vs. Output
Load, 3.3 V Version
OUTPUT LOAD (mA)
150100500
0
2.0
4.0
9.0
ESR ()
OUTPUT VOLTAGE (V)
QUIESCENT CURRENT (mA)
150125
Vin = 13.5 V
Cout > 22 F
6.0
8.0
7.0
200
Figure 18. Current Consumption vs. Output
Load (Low Load), 3.3 V Version
OUTPUT LOAD (mA)
2015100
0
0.05
0.10
0.15
0.35
0.45
0.50
QUIESCENT CURRENT (mA)
0.30
25
0.25
TEMPERATURE (°C)
11060−40
0
1
3
10
QUIESCENT CURRENT (A)
4
7
8
2
5
9
10 150
Vin = 13.5 V
1.0
3.0
5.0
30
10
20
40
70
80
90
0.5 Iout = 5 mA
0.20
6
Vin = 13.5 V
Figure 19. Quiescent Current vs. Temperature,
3.3 V Version
TEMPERATURE (°C)
1106010−40
0
5
10
15
35
45
QUIESCENT CURRENT (A)
30
150
25
Vin = 13.5 V
Iout = 100 A
20
Figure 20. Quiescent Current vs. Temperature,
3.3 V Version
−40°C
125°C
25°C
5
0.40
Vin = 13.5 V
40
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8
Typical Curves
TEMPERATURE (°C) TEMPERATURE (°C)
60200−20−40
3.00
3.25
3.30
3.50
1501106010−40
0
100
150
200
250
OUTPUT VOLTAGE (V)
CURRENT LIMIT (mA)
125100
Vin = 14 V
Iout = 5 mA
3.15
3.05
3.10
3.20
3.35
3.40
3.45
50
Vin = 13.5 V
40 80
INPUT VOLTAGE (V)
503020100
0
2
4
6
7
CURRENT CONSUMPTION (mA)
1
RL = 50
40
RL = 100
3
5
Figure 21. Dropout Voltage, 3.3 V Version
OUTPUT LOAD (mA)
100500
0
0.05
0.10
0.30
0.35
0.45
DROPOUT VOLTAGE (V)
0.20
200150
0.15
0.25
0.40
Figure 22. Current Consumption vs. Input
Voltage, 3.3 V Version
Figure 23. Output Voltage vs. Temperature,
3.3 V Version
Figure 24. Short Circuit Current Limit vs.
Temperature, 3.3 V Version
120
−40°C
125°C
25°C
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9
Circuit Description
The NCV8664 is a precision trimmed 3.3 V and 5.0 V
fixed output regulator. Careful management of light load
consumption combined with a low leakage process results
in a typical quiescent current of 22 A. The device has
current capability of 150 mA, with 600 mV of dropout
voltage at full rated load current. The regulation is provided
by a PNP pass transistor controlled by an error amplifier
with a bandgap reference. The regulator is protected by
both current limit and short circuit protection. Thermal
shutdown occurs above 150°C to protect the IC during
overloads and extreme ambient temperatures.
Regulator
The error amplifier compares the reference voltage to a
sample of the output voltage (Vout) and drives the base of
a PNP series pass transistor by a buffer. The reference is a
bandgap design to give it a temperature−stable output.
Saturation control of the PNP is a function of the load
current and input voltage. Over saturation of the output
power device is prevented, and quiescent current in the
ground pin is minimized. The NCV8664 is equipped with
foldback current protection. This protection is designed to
reduce the current limit during an overcurrent situation.
Regulator Stability Considerations
The input capacitor CIN in Figure 2 is necessary for
compensating input line reactance. Possible oscillations
caused by input inductance and input capacitance can be
damped by using a resistor of approximately 1 in series
with CIN. The output or compensation capacitor, COUT
helps determine three main characteristics of a linear
regulator: startup delay, load transient response and loop
stability. The capacitor value and type should be based on
cost, availability, size and temperature constraints.
Tantalum, aluminum electrolytic, film, or ceramic
capacitors are all acceptable solutions, however, attention
must be paid to ESR constraints. The aluminum
electrolytic capacitor is the least expensive solution, but, if
the circuit operates at low temperatures (−25°C to −40°C),
both the value and ESR of the capacitor will vary
considerably. The capacitor manufacturer’s data sheet
usually provides this information. The value for the output
capacitor COUT shown in Figure 2 should work for most
applications; however, it is not necessarily the optimized
solution. Stability is guaranteed at values COUT ≥ 10 F and
ESR ≤ 9 for 5.0 V version, and COUT ≥ 22 F and ESR
≤ 18 for 3.3 V version, within the operating temperature
range. Actual limits are shown in a graph in the Typical
Performance Characteristics section.
Calculating Power Dissipation in a Single Output
Linear Regulator
The maximum power dissipation for a single output
regulator (Figure 3) is:
IQ(max) VI(max) Iq(eq. 1)
PD(max) [VIN(max) VOUT(min)]
Where:
VIN(max) is the maximum input voltage,
VOUT(min) is the minimum output voltage,
IQ(max) is the maximum output current for the
application, and Iq is the quiescent current the regulator
consumes at IQ(max).
Once the value of PD(Max) is known, the maximum
permissible value of RJA can be calculated:
PJA 150oCTA
PD(eq. 2)
The value of RJA can then be compared with those in the
package section of the data sheet. Those packages with
RJA
’s less than the calculated value in Equation 2 will keep
the die temperature below 150°C. In some cases, none of
the packages will be sufficient to dissipate the heat
generated by the IC, and an external heat sink will be
required. The current flow and voltages are shown in the
Measurement Circuit Diagram.
Heat Sinks
For proper heat sinking of the SOIC−8 Lead device,
connect pins 5 − 8 to the heat sink.
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air. Each material in the heat flow path
between the IC and the outside environment will have a
thermal resistance. Like series electrical resistances, these
resistances are summed to determine the value of RJA:
RJA RJC RCS RSA (eq. 3)
Where:
RJC = the junction−to−case thermal resistance,
RCS = the case−to−heat sink thermal resistance, and
RSA = the heat sink−to−ambient thermal resistance.
RJA appears in the package section of the data sheet.
Like RJA, it too is a function of package type. RCS and
RSA are functions of the package type, heat sink and the
interface between them. These values appear in data sheets
of heat sink manufacturers. Thermal, mounting, and heat
sinking are discussed in the ON Semiconductor application
note AN1040/D, available on the ON Semiconductor
Website.
NCV8664
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10
EMC−Characteristics: Conducted Susceptibility
All EMC−Characteristics are based on limited samples
and not part of production testing, according to
47A/658/CD IEC62132−4 (Direct Power Injection)
Test Conditions
Supply Voltage VIN = 12 V
Temperature TA = 23°C ±5°C
Load RL = 35
Direct Power Injection: 33 dBm forward power CW
Acceptance Criteria: Amplitude Dev. max 2% of Output
Voltage
Figure 25. Test Circuit
GND
VIN VOUT
NCV8664U1
10 F10 F
++
C4
C2 C1
47 nF
C3
10 nF
F2
FERRITE
F1
FERRITE
F3
FERRITE
X1
VIN_HF
X2
VIN_MON
X5
GND_HF
X6
GND_MON
X4
VOUT_MON
X3
VOUT_HF
13
2
Figure 26. Typical VIN−pin Susceptibility Figure 27. Typical VOUT−pin Susceptibility
FREQUENCY (MHz)
1000100101
0
10
20
30
40
VIN (dBm)
FREQUENCY (MHz)
1000100101
0
10
20
30
40
VOUT (dBm)
VOUT−pin pass 33 dBmVIN−pin pass 33 dBm
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Figure 28. qJA vs. Copper Spreader Area
Figure 29. Single−Pulse Heating Curves
COPPER AREA (mm2)
JA (°C/W)
PULSE TIME (sec)
R(t) (°C/W)
0 100 200 300 400 500 600 700
0
20
40
60
80
100
120
140
160
SOT223
DPAK
SOIC−8 Fused
0.001
0.01
0.1
1
10
100
1000
0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
SOIC−8 Fused
SOT223
DPAK
ORDERING INFORMATION
Device Marking Package Shipping†
NCV8664D50R2G V6645 SOIC−8 Fused
(Pb−Free)
2500 / Tape & Reel
NCV8664D50G V6645 SOIC−8 Fused
(Pb−Free)
98 Units / Rail
NCV8664DT50RKG V66450G DPAK
(Pb−Free)
2500 / Tape & Reel
NCV8664DT33RKG V66433G DPAK
(Pb−Free)
2500 / Tape & Reel
NCV8664ST50T3G V6645 SOT−223
(Pb−Free)
4000 / Tape & Reel
NCV8664ST33T3G V6643 SOT−223
(Pb−Free)
4000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
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12
PACKAGE DIMENSIONS
SOT−223 (TO−261)
CASE 318E−04
ISSUE M
A1
b1
D
E
b
e
e1
4
123
0.08 (0003)
A
L1
C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
1.5
0.059 mm
inches
SCALE 6:1
3.8
0.15
2.0
0.079
6.3
0.248
2.3
0.091
2.3
0.091
2.0
0.079
SOLDERING FOOTPRINT
HE
DIM
A
MIN NOM MAX MIN
MILLIMETERS
1.50 1.63 1.75 0.060
INCHES
A1 0.02 0.06 0.10 0.001
b0.60 0.75 0.89 0.024
b1 2.90 3.06 3.20 0.115
c0.24 0.29 0.35 0.009
D6.30 6.50 6.70 0.249
E3.30 3.50 3.70 0.130
e2.20 2.30 2.40 0.087
0.85 0.94 1.05 0.033
0.064 0.068
0.002 0.004
0.030 0.035
0.121 0.126
0.012 0.014
0.256 0.263
0.138 0.145
0.091 0.094
0.037 0.041
NOM MAX
L1 1.50 1.75 2.00 0.060
6.70 7.00 7.30 0.264
0.069 0.078
0.276 0.287
HE
− −
e1
0°10°0°10°
qq
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
DT SUFFIX
CASE 369C−01
ISSUE D
b
D
E
b3
L3
L4
b2
eM
0.005 (0.13) C
c2
A
c
C
Z
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
D0.235 0.245 5.97 6.22
E0.250 0.265 6.35 6.73
A0.086 0.094 2.18 2.38
b0.025 0.035 0.63 0.89
c2 0.018 0.024 0.46 0.61
b2 0.030 0.045 0.76 1.14
c0.018 0.024 0.46 0.61
e0.090 BSC 2.29 BSC
b3 0.180 0.215 4.57 5.46
L4 −−− 0.040 −−− 1.01
L0.055 0.070 1.40 1.78
L3 0.035 0.050 0.89 1.27
Z0.155 −−− 3.93 −−−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
12 3
4
5.80
0.228
2.58
0.102
1.60
0.063
6.20
0.244
3.00
0.118
6.17
0.243
mm
inches
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
H0.370 0.410 9.40 10.41
A1 0.000 0.005 0.00 0.13
L1 0.108 REF 2.74 REF
L2 0.020 BSC 0.51 BSC
A1
H
DETAIL A
SEATING
PLANE
A
B
C
L1
L
H
L2 GAUGE
PLANE
DETAIL A
ROTATED 90 CW5
NCV8664
http://onsemi.com
14
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AJ
SEATING
PLANE
1
4
58
N
J
X 45_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
BS
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) ZSXS
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
mm
inches
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
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