i tt san H1a ice eeeuet Semiconductor uuseee Corporation ispLSI 2064VE 3.3V In-System Programmable High Density SuperFAST PLD Features * SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC 2000 PLD Gates 64 and 32 I/O Pin Versions, Four Dedicated Inputs 64 Registers -~ High Speed Global Interconnect - Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size for Random Logic 100% Functional, JEDEC and Pinout Compatible with ispLSI 2064V Devices 3.3V LOW VOLTAGE 2064 ARCHITECTURE ~~ Interfaces with Standard 5V TTL Devices * HIGH-PERFORMANCE E?CMOS TECHNOLOGY fmax = 180MHz Maximum Operating Frequency tpd = 5.0ns Propagation Delay Electrically Erasable and Reprogrammable Non-Volatile 100% Tested at Time of Manufacture ~~ Unused Product Term Shutdown Saves Power IN-SYSTEM PROGRAMMABLE 3.3V In-System Programmability (ISP) Using Boundary Scan Test Access Port (TAP) Open-Drain Output Option for Flexible Bus Interface Capabitity, Allowing Easy implementation of or Bus Arbitration Logic Increased Manufacturing Yields, Reduced Market and Improved Product Quality ~- Reprogram Soldered Devices for F: * 100% IEEE 1149.1 BOUNDARY SC * THE EASE OF USE AND FAST PLDs WITH THE DENSITY ANE Enhanced Pin Locking Three Dedicated Cl - Synchronous and A Programmable Flexibie Pin Optimized Interconne ispEXPERT ting Pool Provides Global OMPILER AND COMPLETE LOG ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING ~- Superior Quality of Results ~- Tightly integrated with Leading CAE Vendor Tools Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER PC and UNIX Platforms Functional Block Diagram Output Routing Pool (ORP) db. Py Global Routing Pool | a Wc (GRP) cll I bg x a Ed me Ol le 8 3 3 7 d & ba 3 2] FE Pl] lic eT ie Ed 3 3 Esl Ea s 3 P) EAI 116 ole a SS 5 z EEE O139A/2064V 2064VE is a High Density Programmable evice available in 64 and 32 |/O-pin versions. The levice contains 64 Registers, four Dedicated Input pins, ree Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLS! 2064VE features in-system programmability through the Boundary Scan Test Ac- cess Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testabie. The ispLS! 2064VE offers non-volatile reprogrammability of the logic, as well as the intercon- nect, to provide truly reconfigurable systems. The basic unit of logic on the isoLS| 2064VE device is the Generic Logic Block (GLB). The GLBs are labeled AO, A1...B7 (see Figure 1). There are a total of 16 GLBs in the ispLS! 2064VE device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. Copyright 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. March 1999 Tel. (603) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http:/Awww.latticesemi.com 2064ve_01Lattice e532 Semiconductor aaa Corporation Specifications ispLS!I 2064VE Functional Block Diagram Figure 1. ispLSI 2064VE Functional Block Diagram (64-I/O and 32-I/O Versions) w 3 6 3 Q Global Routing Pool (GRP) The 64-/O 2064VE contains 64 I/O cells, while 1/O version contains 32 I/O cells. Each I/O cell connected to an I/O pin and can be indivi grammed to be a combinatorial input, out bi-directional /O pin with 3-state con levels are TTL compatible voltages a programmed independently fo rate to minimize overall outge 0 dedicated inputs and gonnected together to make a Megablock (see ). The outputs of the eight GLBs are connected toas 32 or 16 universal 1/O cells by two or one ORPs. Each ispLSI 2064VE device contains two Megablocks. two or one O The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional |/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 2064VE device are selected using the dedicated clock pins. Three dedicated clock pins (YO, Genenc Logic | Blocks (GLBs! Output Routing Pool (ORP) Output Routing Pool (ORP) FOUND TOON? | E or an asynchronous clock can be selected on a asis. The asynchronous or Product Term clock be generated in any GLB for its own clock. Programmable Open-Drain Outputs In addition to the standard output configuration, the outputs of the ispLSI 2064VE are individually program- mable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and pull-up. This output configuration is controlled by a pro- grammable fuse. The default configuration when the device is in bulk erased state is totem-pole configuration. The open-drain/totem-pole option is selectable through the ispEXPERT software tools.Lattice Specifications ispLS!I 2O64VE sanena Corporation Absolute Maximum Ratings Supply Voltage Vo oe ecccccsessscecsesecsecssesseesseesevesssveens -0.5 to +5.4V Input Voltage Applied ............. ccc ccesesseeeecnees -0.5 to +5.6V Off-State Output Voltage Applied ..........00... -0.5 to +5.6V Storage Temperature ..0..... eee cceseeeteeeteees -65 to 150C Case Temp. with Power Applied ................... -55 to 125C Max. Junction Temp. (Ty) with Power Applied ............ 150C 1. Stresses above those listed under the Absolute Maximum Ratings may cause permanent damagifto the device. Functional operation of the device at these or at any other conditions above those indicated in the operatic ns of this specifica tion is not implied (while programming, follow the programming specifications). : SYMBOL PARAMETER MIN. MAX. | UNITS Commercial T 3.0 3.6 Vv Industrial 3.0 3.6 Vv VIL Input Low Voltage ~ 0.5 0.8 Vv VIH Input High Voltage 2.0 5.25 Vv Tabie 2-0005/2064V Vcc Supply Voltage SYMBOL TYPICAL | UNITS TEST CONDITIONS C, Dedicated Input 8 pf Vec= 3.3V, Vin = 2.0V 1/0 Capacitance 6 pf Voec= 3.3V, Vo = 2.0V Clock and Global 10 pf Vec= 3.3V, Vy= 2.0V Table 2-0006/2064VE MINIMUM MAXIMUM UNITS Erase/Reprogram 10000 ~ Cycles Table 2-0008/2064VELattice eeeens Semiconductor saneas Corporation Switching Test Conditions Specifications ispLS!I 2064VE Input Pulse Levels GND to 3.0V Input Rise and Fall Time 10% to 90% <5 ns Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load See Figure 2 3-state levels are measured 0.5V from Table 2-0003/2064V steady-state active level. Output Load Conditions (see Figure 2) TEST CONDITION R1 R2 CL A 3162 | 34892 | 35pF B Active High co 348Q | 35pF Active Low 3162 | 348Q | 35pF Active High to Z Lat Non-0.8V ce | 348Q | SpF Active Low to Z at Vo, +0.5V 3162 | 3482 5pF Table 2-0004/2064V Over SYMBOL PARAMETER VoL Output Low Voltage Vou Output High Voltage he input or VO Low lH Input or /O High IN lit. BSCAN Iiw-Pu =| VO los' Icc? 4 Supply Current . One output at a time mA < Vins Vi.(Max.) HA (Veg 0.2)V S$ Vin S Voc pA <V,, $5.25V OV < Vins Vit OV < Vins Vi Vec= 3.3V, Vour= 0.5V Vii= 0.0V, V,,= 3.0V fovock = 1 MHz a maximum duration of one second. Voy7 = 0.5V was selected to avoid test Figure 2. Test Load + 3.3V Device Output "CL includes Test F, Capacitance. 02 19A/2064V Conditions DITION Vv Vv mA pA pA mA mA Table 2-0007/2064VE problems by tester ground degradation. Characterized but not 100% tested. Measured using four 16-bit counters. Typical values are at Vec= 3.3V and T,= 25C. Bon Maximum Ic varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum I...Lattice Specifications ispLSI 2064VE sseeee Corporation External Timing Parameters Over Recommended Operating Conditions PARAMETER | TEST'| DESCRIPTION 0 7 10 | units COND. MIN. | MAX.| MIN. |MAX.| MIN. |MAX. tod1 A 1 | Data Propagation Delay, 4PT Bypass, ORP Bypass| | 5.0 - 175} | 10.0 ns tod2 A 2 | Data Propagation Delay ~ |75 | |10.0] - |13.0} ns fmax A | 3 | Clock Frequency with Internal Feedback? 180] - | 135/ ~ | 100] | MHz fmax (Ext.) - 4 | Clock Frequency with External Feedback (ja7m01) | 125] - | 100] - | 77 | - | MHz fmax (Tog.) - 5 | Clock Frequency, Max. Toggle 200] - | 143) ~ | 100] ~ | MHz tsu1 - 6 | GLB Reg. Setup Time before Clock, 4 PT Bypass 3.5 - 5.0 | 2a 65 | - ns tcot A 7 | GLB Reg. Clock to Output Delay, ORP Bypass ~ |35] - Oo} | 5.0 ns thi - 8 | GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0} - | 0.0} ns tsu2 - 9 | GLB Reg. Setup Time before Clock 45] 2@ieo0 | siaeo | - ns tco2 A | 10] GLB Reg. Clock to Output Delay 75 | ee 5.0] - | 6.0] ns the ~ |11] GLB Reg. Hold Time after Clock 0.0 |eearo.o- | 00) - | ns tri A 12] Ext. Reset Pin to Output Delay 2p ,| 7.0% 10.0} - |135] ns tw - | 13] Ext. Reset Pulse Duration Ode) 5.0] - | 65) - ns tptoeen B | 14] input to Output Enable ; 10.0] ~ |12.0] - [15.0] ns totoedis C | 15] Input fo Output Disable jie. 110.0; - {120} 115.0] ns tgoeen B | 16] Global OE Output Enable . r- 15.0] ~ | 7.0] - | 9.0] ns tgoedis C |17] Global OE Output Disable d - |50/ - |70] - | 90] ns twh - 18] External Synchronous Clock Pu ti igh 25 ~ 3.5 - 5.0 | - ns twi ~ 19] External Synchronous C _ Low 25) - | 35] - | 50] - ns 1. Unless noted otherwise, all parameters use a GRR& ee TXOR path, ORP and YO clock. Table 2-0030/2064VE 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions sectic bs, aLattice usaue Semiconductor asaees Corporation Specifications ispLS!I 2064VE Internal Timing Parameters! Over Recommended Operating Conditions PARAMETER | # DESCRIPTION 180 5 "0 UNITS MIN. |MAX.| MIN. [MAX.| MIN. [MAX. Inputs tio 20 | Input Buffer Delay ~ - _ Z _ _ ns tdin 21 | Dedicated Input Delay -~-{/-]-]- {1-4} -1 ns GRP tor | 22 | GRP Delay L-[-[-]- 7 -] -/ 1s GLB ae t4ptbpc 23 | 4 Product Term Bypass Path Delay (Combinatorial) - - 4 - ~ ns t4ptbpr 24 | 4 Product Term Bypass Path Delay (Registered) - | ghee | ~ | - | ns tiptxor 25 | 1 Product Term/XOR Path Delay - -~ f- | - 1] ns t20ptxor 26 | 20 Product Term/XOR Path Delay - -~ | - | ns txoradj 27 | XOR Adjacent Path Delay? ite | - ~ | | vs tgbp 28 | GLB Register Bypass Delay = - _ _ ns tgsu 29 | GLB Register Setup Time before Clock s | 4 -~ | - - ~ _ ns tgh 30 | GLB Register Hold Time after Clock Ait, ~ep - _ - _ ~ ns tgco 31 | GLB Register Clock to Output Delay r ~ - - ~ ~ ns | tgro 32 | GLB Register Reset to Output Delay ,#% is. ~{/-]-]-]-4] -4] ns tptre 33 | GLB Product Term Reset to Register Dy = - ~ _ - ~ ~ ns tptoe 34 | GLB Product Term Output Enatsl call Oelay -~|-]-]-]-7] - 4] vs tptck 35 | GLB Product Term Clock D a ~{-]-]- -~ | - | ns ORP iy torp 36 | ORP Delay -|-{-]-]-] - 4 as torpbp 37 | ORP Bypass Di ~ - _ ~ - ~ ns Outputs tob 38 | Output -{-],-] - _ ~ | ns tsi 39 | Out] Delay Adder -~/--]-}-]-4] -1 ns toen 40 put Enabled - ~ - - - - ns todis Output Disabled - _ ~ _ - - ns tgoe | Output Enable ~f|-f| - |] - ~ | | ns Clocks tgyo 43 k Delay, YO to Global GLB Clock Line (Ref. clock) - - - ~ _ - ns tgy1/2 44 | Clock Delay, Y1 or 2 to Global GLB Clock Line ~- - - - ~ _ ns Global Reset tor | 45 | Global Reset to GLB [-[-]-]-]-]- [1 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Table 2-0036/2064VELattice Specifications ispLSI 2O64VE sannue Corporation ispLS! 2064VE Timing Model VO Cell GRP GLB ORP VO Cell atts a fw df Feedback | Ded. In >- 1 Comb 4 PT Bypass #23 _ 10 Pin VO Delay >| GRP Reg 4 PT Bypass | GLB Reg Bypass OFRP Bypass i > > > > #20 | #22 | #24 #28 (Input) 20 PT GLB Reg XOR Delays Delay #25, 26, 27 D Q RST | Reset > #45 | #28, 39. ZN a Control RE PTs OE #33, 34, CK 35 Y0,1,2 > #43. 4 #42 IGOE 0,1 0491/2064 Derivations of tsu, th and tco from the Product Te tsu = Logic + Reg su - Clock (min) = (tio + tgrp + t20ptxor) + (tgsu) - (ti = (#20 + #22 + #26) + (#29) - (#204 th = Clock (max) + Reg h - Logic : " = (tio + tgrp + tptck(max) io #fgrp + t20ptxor) = (#20 + #22 + #35) + tco = Clock (max) + { = (tio + tgrp co) + (torp + tob) = (#20 +4 (#36 + #38) Note: Calculations ing specifications for the ispLSi 2064VE-180L. Table 2-0042/2064VELattice Specifications ispLS!I 20O64VE Power consumption in the ispLS! 2064VE device de- used. Figure 3 shows the relationship between power pends on two primary factors: the speed at which the and operating speed. device is operating and the number of Product Terms Figure 3. Typical Device Power Consumption vs fmax 120 -- ispLS! 2064VE Ioc(mA) = Where: # of PTs = Number of Product Terms ysed in de # of nets = Number of Signals used i ice Max freq = Highest Clock Frequeg@ CC = 3.3V, room temperature) and an assumption of two GLB estimates only. Since the value of icc is sensitive to operating The Icc estimate is based on ty loads on average exists. Th conditions and the prograg 0127/2064VELattice uueen Semiconductor ss2885 Corporation Specifications ispLSI 2064VE 64-1/O Signal Descriptions Signal Name Description RESET Active Low (0) Reset pin resets all the registers in the device. GOE 0, GOE1 Global Output Enable input pins. YO, 1, Y2 Dedicated Clock Input ~ These clock inputs are connected to one of the clock inputs of all the GLBs in the device. BSCAN Input Dedicated in-system programming Boundary Scan enable input pin. This pin is brought low to enable the programming mode. The TMS, TDI, TDO and TCK controls become active. TDI/IN 0 Input This pin performs two functions. When BSCAN is logic low, it functions as a serial data input pin to load programming data into the device. When BSCAN is high, it functions as a dedicated input pin. TCK/IN 3 Input ~ This pin performs two functions. When BSCAN is logic low, it functiongas a clock pin for the ISP/Boundary Scan state machine. When BSCAN is high, it functions as a dedated input pin. TMS/IN 1 Input This pin performs two functions. When BSCAN is logic low, it fu mode control pin for the ISP/Boundary Scan state machine. When BSCAN is high, it functj ed input pin. TDO/IN 2 Output/Input This pin performs two functions. When BSCAN Nis | S as an output pin to read serial shift register data. When BSCAN is high, it functioi ed input pin. GND Ground (GND) vcc Vcc NC* No Connect /O Input/Output Pins These are the general purpos by the logic array. . NC pins are not to be connected to any active signals, VCC or GND. 32-1/O0 Signal Descriptions Signal Name rogrammed to function as a Global Output Enable fecan be programmed to function as a GLobal Output Enable or is connected to one of the clock inputs of all GLBs on the Dedicated clock input. This clock input is brought into the Clock optionally be routed to any GLB and/or 1/O cell on the device. (2) Active ts all of the GLB and i/O registers in the device. Biem programming Boundary Scan Enable input pin. This pin is brought low to g mode. The TMS, TDI, TDO and TCK controls become active. GOE O/IN 3 This pin performs one of two fu pin or a Dedicated Input pin. GOE 1/YO This pin performs one of two furs a Dedicated Clock inpg device. RESET/Y1 BSCAN TDI/IN O orms two functions. When BSCAN is logic low, it functions as an input pin to load data into the device. TDINNO is also used as one of the two control pins for the ISP State n BSCAN is high, it functions as a dedicated input pin. TMS/IN 2 This pin performs two functions. When BSCAN is logic low, it functions as a pin to control the tion of the ISP State Machine. When BSCAN is high, it functions as a dedicated input pin. TDO/IN 1 Output/Input This pin performs two functions. When BSCAN is logic low, it functions as an output pin pin to read serial shift register data. When BSCAN is high, it functions as a dedicated input pin. TCK/Y2 Input ~ This pin performs two functions. When BSCAN is logic fow, it functions as a clock pin for the Serial Shift Register. When BSCAN is high, it functions as a dedicated clock input. This clock input is brought into the Clock Distribution Network and can optionally be routed to any GLB and/or {/O cell on the device. GND Ground (GND) vcc Vec NC! No Connect vO Input/Output pins These are the general purpose I/O pins used by the logic array. 1. NC pins are not to be connected to any active signals, VCC or GND.Lattice saeees oemiconductor anueas Corporation Specifications ispLS!I 2O64VE 64-1/O Signal Locations Signal 100-Ball BGA | 100-Pin TQFP | 84-Pin PLCC RESET D2 11 20 GOE 0, GOE 1 | F9, E1 62, 13 64, 22 YO, Y1, Y2 E3, F6, F8 10, 65, 60 19, 67, 62 BSCAN E5 15 24 TDIAN O F2 16 25 TCK/IN 3 G10 59 61 TMS/IN 1 J5 37 43 TDOAN 2 B6 87 1 GND B7, F1, G9, K6 | 14,39, 61, 86 | 23, 44, 63, 84 vcc AS, E2, F10, J4 | 12, 36, 63,89 | 2,21, 42, 65 NC! A6, A8, C3, 4,9, 21, 25, 66 C4, D1, D6, 31, 38, 44, 50, D8, E7, E9, 54, 64, 66, 71, E10, F4, G3, 75, 81, 88, 94, G5, H7, H8, 100 K3, K5 1. NC pins are not to be connected to any active signals, VCC or 32-1/0 Signal Locations Signal 44-Pin TQFP | 44-Pin PLCC BGA GOE 0/ IN 3 40 2 GOE 1/Y0 5 RESET/Y1 29 D7 BSCAN 7 D1 TDI/IN 0 8 2 TMS/IN 2 30 C TMO/IN 1 24 G4 TCY/Y2 33 E7 GND 1,23 C4, E4 VCC 12, 34 D3, DS NC! Al, A7, D4, G1, G7 1. NC pins are not to be connected to any active signals, VCC or GND. 10Lattice ==8" Semiconductor snaass Corporation Specifications ispLSI 2O64VE LO Movers terelat 100 100 84 49 44 44 Signal BGA TQFP PLCC BGA TQFP- PLCC VO0 Gi 7 26 E1 9 15 VO1 F3 18 27 F2 10 16 /O2 E4 19 28 Fi 11 17 VO3 Hi 20 29 E3 12 18 vO4 G2 22 30 F3 13 19 VO5 Jf 23 31 G2 14 20 VO6 H2 24 32 F4 15 2i VO7 K1 26 33 G3 16 22 /O 8 J2 27 34 F5 19 25 vO9 K2 28 35 G5 20 26 VO 10 H3 29 36 F6 21 27 /O11 J3 30 37 G6 22 28 vO12 G4 32 38 ES 23 29 013 H4 33 39 E6 24 30 VO 14 K4 34 40 F7 25 31 VO 15 H5 35 41 D6 26 32 VO 16 FS 40 45 C7 31 37 VO 17 J6 41 46 B6 32 38 VO 18 K7 42 47 B?7 33 39 VO 19 H6 43 48 C5 34 40 VO 20 K8 45 49 BS 35 Al VO 21 G6 46 50 AG 36 42 VO 22 J7 47 51 B4 37 43 VO 23 K9 48 92 AS 38 44 V0 24 J8 49 53 B3 41 3 VO25 K10 51 54 A3 42 4 VO 26 J9 52 55 B2 43 5 VO27 J10 53 56 A2 44 6 V0 28 H9 55 57 C3 1 7 O29 H10 56 58 C2 2 8 VO30 G7 57 59 B1 3 VO 31 G8 58 60 D2 4, VO32 D10 67 68 _ VO 33 E& 68 69 0 34 F7 O35 C10 VO 36 D9 VO37 B10 _ VO38 C9 _ VO39 A10 ~ VO 40 BS _ VO 41 AQ _ VO 42 C8 VO 43 B& VO 44 D7 _ V/O 45 C7 VO 46 AZT 82 _ _ _ VO47 C6 83 _ _ _ V0 48 E6 3 _ _ _ 0 49 B5 4 _ _ VO50 Ad 92 5 _ _ _ VO 51 C5 93 6 _ _ _ VO 52 AS 95 7 _ _ _ 1/0 53 DS 96 8 _ _ VO 54 B4 97 9 _ _ _ VO 55 A2 98 10 _ _ _ VO 56 B3 99 11 _ _ _ VO57 At 1 12 _ _ V/O 58 B2 2 13 _ _ _ VO 59 B1 3 14 _ _ _ vO60 C2 5 15 _ _ VO 61 C1 6 16 _ _ _ VO 62 D4 7 17 _ _ _ 0 63 D3 8 18 _ _ _ 11=Lattl ce Specifications ispLS! 2064VE s2ene88 Corporation Signal Configuration ispLSI 2064VE 100-Ball BGA Signal Diagram 10 9 8 7 #66 5 4 3 2 1 4s BIREIEEEIEEE | 2} (IE 8 c| EIB c >| EIB D E nc'] | NC E F vec} |SOE F | [&] a G H 38 38 15} | 13] | 10 6 3 H J 27 | | 26 7} lint] [CCH |S | fe | | 8 J K A " GND] | NC "0 NC! "9 "0 K ispLSI 2064VE Bottom View 9 8 7 6 5 4 3 2 1 100-BGA/2064VE INCs are not to be connected to any active signals, VCC or GND. Note: Ball A1 indicator dot on top side of package. 12Lattice sustss Semiconductor enseue Corporation Pin Configuration ispLSI 2064VE 100-Pin TQFP Pinout Diagram Specifications ispLS!I 2064VE N owtran = OO z Mm 0 tt ON sr OM 5 OOOO DDO TIO OOVIIILVITIS AAAARRARAARAAAAAAARARAAE ODOR OWTSTAYAN Yr DOODDKNRONU TYAN - ODAOR GDAIAIWAMHWAI9OAIMAAINMWDADNDMDADADNDDOMOOORRAKRER vos7oO1 = /0 580 2 1/0 38 VO 590-4 3 = /0 37 NCL 4 VO 36 VO 60CC 5 : V/O 614 6 F/O 35 VO 620-4 7 1/0 34 V/O 63-4 8 1/0 33 INCL 9 FT 1/0 32 YO 10 66 FE NCt RESET 11 65 FTI Y1 VCCE 12 ispLSI 2064 64 FT NC! GOE 1074 13 63 EJ VCC GND] 14 Top Vi 62 FJ GOE 0 BSCANCL4 15 61 FT GND TDIV/IN OL 16 60 ET Y2 VO OL 17 59 EI TCK/IN 3 VO 1E4 18 58 FT 0 31 VO 2 19 57 FT VO 30 VO 30 20 56 FT 1/0 29 NCL 21 55 Fo vO 28 VO 4E--] 22 54 FJ NCI VO 5-1] 23 53 FI VO 27 VO 6EL4 24 52 Fr 1/0 26 INCL] 25 51 FT 0 25 OOM ODOrN YT ON ODO HOOnninrtdst este st tds ts Tt wo - Saat oD QTOAEELOSKEIL SD 25 2*G0000*90000% = -- not to be connected to any active signals, VCC or GND. 100 TQFP/2064VE 13Lattice Specifications ispLS!I 2064VE uuanas Corporation Pin Configuration ispLSI 2064VE 84-Pin PLCC Pinout Diagram N SBREBASSISoE oS SVISITSB 2GegeggeegeeeseFReVgeegegeeeee OOO OOo ooo ooo ooo 11109 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 VO 57 CL] 12 a -] VO 38 vo58 0 j TJ 1/0 37 vo59 F T] 0 36 vo6o C rT] VO 35 voei CO T] vO 34 vo62 C r] 0 33 vo63 T T] 0 32 Yoo rT} Y1 RESET (1 TJ Nc} vec 0 Tr] vec GOE1 0 -] GOEO GND T] GND BSCAN [J r] Y2 TOVINO [J ] TCK/IN 3 yoo r} VO 31 vo1 r] VO 30 vo2 CT ] vO 29 vo3 T] VO 28 vo4 0 T} VO 27 vos T T] VO 26 voe [] T] VO 25 44 45 46 47 48 LICTOOLCICICICICI 5 oer eZee AN aR A ar Qeeeeeeegee = 1. NC pins are not to be connected to any active signal, VCC or GND. 84 PLOC/2064VE 14Lattice =35 semiconductor uanaee Corporation Specifications ispLS!I 2064VE Pin Configuration ispLSI 2064VE 44-Pin PLCC Pinout Diagram wm 2 nouodw o ON r On NUN WNW ONAN WN eegoQg 8 6222900 Dono ooo ooo 6 5 4 3 2 1 44 43 42 41 40 vo 28 (7 391] vo 18 vo 29 [18 3810 VO 17 vo 30 C19 3710 VO 16 vo 31 [10 PI TMS/IN 2 GoE1/vo [11 vec [12 ispLSI 2064VE BSCAN [413 Top View TDIIN O [14 voo [15 vo1(Ch16 vo2 (h17 18 19 20 21 Pin Configuration 44 PLCC/2064VE . 337] VO 18 "12 3277 vO 17 320 C3 31] vo 16 vo31 []4 307] TMS/IN 2 5 s GoEvvo TY ispLSI 2064VE [RESET vec (6 Top Vi 28 [7] VCC BSCAN C7 op View 271] tToKv2 TDI/IN Oo [8 26] vO 15 voo Tg 25[] vO 14 vo1 [10 241] vo 13 vo2Ti1 230] vO 12 12 13 14 15 16 17 18 19 20 21 22 DOC OC OO orn onogreoeoaor PQOLQQkKRZLQLGO Oo = 35 Oo Be 44 TOFP/2064VE 15Seat Semicendurton Specifications ispLS!/ 2064VE Signal Configuration ispLS! 2064VE 49-Ball BGA Signal Diagram 7 6 5 4 3 2 1 iN ner] | VO] | vO] fooeol | vO] | VO} |e TA 49-BGA/2064VE 1 @ connected to any active signals, VCC or GND. indicator dot on top side of package. 16Lattice gaee8s Semiconductor aeneee Corporation Specifications ispLS/ 2064VE Part Number Description ispLSI 2064VEXXX X XXX X Device Family ___ Device Number Speed 180 = 180 MHz fmax 135 = 135 MHz fmax 100 = 100 MHz fmax FAMILY fmax (MHz) 180 180 180 135 135 135 100 100 100 FAMILY fmax (MHz 135 tod (ns) 5.0 5.0 5.0 7.5 7.5 7.5 10 10 10 COMMERCIAL ispLSI -180LB100 ~135LJ84 -135LT100 VE-135LB100 2064VE-100LJU84 ispLS! 2064VE-100LT100 ispLSI 2064VE-100LB100 INDUSTRIAL ORDERING NUMBER S| 2064VE-135LT100! tL Grade Blank = Commercial {= Industrial Package T100 = 100-Pin TQFP J84 = 84-Pin PLCC B10 = 100-Ball BGA pe , 0212/2064VE PACKAGE 84-Pin PLCC 100-Pin TQFP 100-Ball BGA 84-Pin PLCC 100-Pin TQFP 100-Ball BGA 84-Pin PLCC 100-Pin TQFP 100-Ball BGA Table 2-0041A/2064VE PACKAGE 100-Pin TQFP Table 2-0041B/2064VE 17