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Copyright ©2008 by Zilog®, Inc. All rights reserved.
www.zilog.com
FEATURES
•Z85C30 Optimized for Non-Multiplexed Bus
Microprocessors. Z80C30 Optimized for Mul-
tiplexed Bus Microprocessors.
•Pin Compatible to NMOS Versions
•Two Independent, 0 to 4.1 Mbit/Second, Full-
Duplex Channels, Each with a Separate Crystal
Oscillator, BaudRate Generator, and Digital
Phase-Locked Loop (DPLL) for Clock Recov-
ery.
•Multi-Protocol Operation under Program Con-
trol; Programmable for NRZ, NRZI, or FM
Data Encoding.
•Asynchronous Mode with Five to Eight Bits
and One, One and One-Half, or Two Stop Bits
Per Character, Programmable Clock Factor,
Break Detection and Generation; Parity, Over-
run, and Framing Error Detection.
•Synchronous Mode with Internal or External
Character Synchronization on One or Two
Synchronous Characters and CRC Generation
and Checking with CRC-16 or CRC-CCITT
Preset to either 1s or 0s.
•SDLC/HDLC Mode with Comprehensive
Frame-Level Control, Automatic Zero Inser-
tion and Deletion, I-Field Residue Handling,
Abort Generation and Detection, CRC Genera-
tion and Checking, and SDLC Loop.
•Software Interrupt Acknowledge Feature (not
with NMOS)
•Local Loopback and Auto Echo Modes
•Supports T1 Digital Trunk
•Enhanced DMA Support (not with NMOS)
–10 x 19-Bit Status FIFO
–14-Bit Byte Counter
•Speeds:
–Z85C30 -8.5, 10, 16.384 MHz
–Z80C30 -8, 10 MHz
Other Features for Z85C30 only:
•New programmable WR7' (write register 7
prime) to enable new features.
•Improvements to support SDLC mode of syn-
chronous communication:
–Improve functionality to ease sending
back-to-back frames.
–Automatic SDLC opening Flag transmis-
sion*
–Automatic Tx Underrun/EOM Latch reset
in SDLC mode*
–Automatic /RTS deactivation*
–TxD pin forced "H" in SDLC NRZI mode
after closing flag*
–Complete CRC reception*
–Improved response to Abort sequence in
status FIFO
–Automatic Tx CRC generator preset/reset
–Extended read for write registers*
–Write data set-up timing improvement
•Improved AC timing
–Three to 3.6 PCLK access recovery time
–Programmable /DTR//REQ timing*
–Write data to falling edge of /WR set-up
time requirement is now eliminated.
–Reduced /INT timing
•Other features include:
–Extended read function to read back the
written value to the write registers. *
–Latching RR0 during read
CMOS Z-BUS® SCC SERIAL COMMUNICATION CONTROLLER
PB005702-0608
Z80C30
Product Brief