LTC3351
1
Rev. A
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TYPICAL APPLICATION
FEATURES DESCRIPTION
Hot Swappable Supercapacitor Charger,
Backup Controller and System Monitor
The LT C
®
3351 is a backup power controller that charges
and monitors a series stack of one to four supercapaci-
tors. The LTC3351’s synchronous step-down controller
drives N-channel MOSFETs for constant current/constant
voltage charging with programmable input current limit.
In addition, the step-down converter runs in reverse as
a step-up converter to deliver power from the superca-
pacitor stack to the backup supply rail. Internal balancers
eliminate the need for external balance resistors and each
capacitor has a shunt regulator for overvoltage protection.
The LTC3351 monitors system voltages, currents, stack
capacitance and ESR which can all be read over the I2C/
SMBus port. The hot swap controller uses N-channel
MOSFETs for inrush control and a low loss path from
the input to the output. The ideal diode controller uses
an N-channel MOSFET for a low loss power path from
the supercapacitors to the output. The LTC3351 is avail-
able in a thermally enhanced low profile 44-lead 4mm ×
7mm×0.75mm QFN surface mount package.
APPLICATIONS
n Integrated Hot Swap Controller with Circuit Breaker
n High Efficiency Synchronous Step-Down CC/CV
Charging of One to Four Series Supercapacitors
n Step-Up Mode in Backup Provides Greater
Utilization of Stored Energy in Supercapacitors
n 16-Bit ADC for Monitoring System Voltages/
Currents, Capacitance and ESR
n Programmable Undervoltage and Overvoltage
Thresholds to 35V
n VIN: 4.5V to 35V, VCAP(n): Up to 5V per Capacitor,
Charge/Backup Current: >10A
n Programmable Input Current Limit Prioritizes System
Load Over Capacitor Charge Current
n All N-FET Charger Controller and PowerPath™ Controller
n Compact 44-Lead 4mm × 7mm QFN Package
n Swappable PCIE Cards with NVM
n High Current 12V Ride-Through UPS
n Servers/Mass Storage/High Availability Systems All registered trademarks and trademarks are the property of their respective owners. Patents
pending.
V
IN
UV
OUTFB
OUTFET
TGATE
SW
BGATE
ICAP
VCAP
CAP4
CAP3
CAP2
CAP1
CAPRTN
CAPFB
HS_GATE
ISNSP_HS/
ISNSM
I
CHG
(STEP-DOWN)
I
BACKUP
V
CAP
< V
OUT
(STEP-UP)
V
CAP
> V
OUT
(DIRECT
CONNECT)
V
OUT
LTC3351
10F
V
CAP
10F
10F
10F
3351 TA01a
I
2
C
OV
ISNSP_CHG
5ms/DIV
3351 TA01
IIN
0.2A/DIV
VOUT
2V/DIV
VIN
2V/DIV
Example Hot Swap from 12V
LTC3351
2
Rev. A
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PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
VIN, VOUT, ISNSP_HS, ISNSP_CHG, ISNSM,
UV, OV, RETRYB, OUTFB ....................... –0.3V to 40V
VCAP .......................................................... –0.3V to 22V
CAP4-CAP3, CAP3-CAP2,
CAP2-CAP1, CAP1-CAPRTN ................. –0.3V to 5.5V
DRVCC, CAPFB, SMBALERT, CAPGD,
VINGD, GPI, SDA, SCL ........... –0.3V to INTVCC + 0.3V
BST ......................................................... –0.3V to 45.5V
CAP_SLC T0, CA P_SLCT1 ......... –0.3V to VCC2P5 + 0.3V
BST to SW ................................................ –0.3V to 5.5V
ISNSP_HS to ISNSM,
ISNSP_CHG to ISNSM, ICAP to VCAP ... –0.3V to 0.3V
IINTVCC .................................................................100mA
ICAP(1,2,3,4), ICAPRTN ............................................ 600mA
ICAPGD, IVINGD , ISMBALERT ......................................10mA
Operating Junction Temperature Range
(Notes 2, 3) ........................................ –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
(Note 1)
16 17
TOP VIEW
45
PGND
UFF PACKAGE
44-LEAD (4mm × 7mm) PLASTIC QFN
18 19 20 21 22
44 43 42 41 40 39 38
CAP_SLCT0
CAP_SLCT1
VINGD
SCL
SDA
SMBALERT
CAPGD
VC
CAPFB
OUTFB
SGND
RT
GPI
ITST
CAPRTN
ISNS_HS
ISNSP_CHG
ISNSM
RETRYB
VOUT
INTVCC
DRVCC
BGATE
BST
TGATE
SW
VCC2P5
ICAP
VCAP
OUTFET
CTIMER
OV
UV
VIN
HS_GATE
SRC
CSS
CAP1
CAP2
CAP3
CAP4
CFP
CFN
VCAPP5
29
28
27
26
25
24
23
30
31
32
33
34
35
36
37
8
9
10
11
12
13
14
15
7
6
5
4
3
2
1
TJMAX = 125°C, θJA = 36.4°C/W, θJC = 2.6°C/W
EXPOSED PAD (PIN 45) IS PGND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3351EUFF#PBF LTC3351EUFF#TRPBF 3351 44-Lead (4mm × 7mm) Plastic QFN –40°C to 125°C
LTC3351IUFF#PBF LTC3351IUFF#TRPBF 3351 44-Lead (4mm × 7mm) Plastic QFN –40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
LTC3351
3
Rev. A
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ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Switching Regulator
VIN Input Supply Voltage l4.5 35 V
IQInput Quiescent Current, IVOUT (Note 4) 2.25 mA
VCAPFBHI Maximum Regulated VCAP Feedback Voltage Full Scale (1111b) l1.188 1.2 1.212 V
VCAPFB_DEF Default VCAPFB_DAC Setting (1010b) l0.997 1.0125 1.028 V
VCAPFBLO Minimum Regulated VCAP Feedback Voltage Zero Scale (0000b) l0.625 0.6375 0.650 V
ICAPFB CAPFB Input Leakage Current VCAPFB = 1.2V l–50 50 nA
VOUTFB Regulated VOUT Feedback Voltage l1.182 1.2 1.218 V
VOUTFB(TH) OUTFET Turn-Off Threshold Falling Threshold 1.27 1.3 1.33 V
IOUTFB OUTFB Input Leakage Current VOUTFB = 1.2V l–50 50 nA
VOUTBST VOUT Voltage in Step-Up Mode VIN = 0V l4.5 35 V
VUVLO INTVCC Undervoltage Lockout Rising Threshold
Falling Threshold
l
l
3.85
4.3
4
4.45 V
V
VDRVUVLO DRVCC Undervoltage Lockout Rising Threshold
Falling Threshold
l
l
3.75
4.2
3.9
4.35 V
V
VDUVLO VOUT – VCAP Differential Undervoltage Lockout Rising Threshold
Falling Threshold
l
l
160
55
200
90
240
125
mV
mV
VOVLO Switcher VIN Overvoltage Lockout Rising Threshold
Falling Threshold
l
l
37.7
36.3
38.6
37.2
39.5
38.1
V
V
VVCAPP5 Charge Pump Output Voltage Relative to VCAP, 0V < VCAP < 20V 5 V
Input Current Sense Amplifier
VSNSI Regulated Input Current Sense Voltage
(ISNSP_CHG – ISNSM)
l31.04 32 32.96 mV
Charge Current Sense Amplifier
VSNSC Regulated Charge Current Sense Voltage
(ICAP–VCAP)
VCAP = 10V, Charge Mode l31.04 32 32.96 mV
VCMC Common Mode Range (ICAP, VCAP) 0 20 V
VPEAK Peak Inductor Current Sense Voltage Active in Both Step-Up/Step-Down
Modes
l51 58 65 mV
IICAP ICAP Pin Current Step-Down Mode, VSNSC = 32mV
Step-Up Mode, VSNSC = 32mV
27
100
µA
µA
Error Amplifier
gMV VCAP Voltage Loop Transconductance 1 mmho
gMC Charge Current Loop Transconductance 64 μmho
gMI Input Current Loop Transconductance 64 μmho
gMO VOUT Voltage Loop Transconductance 350 μmho
Oscillator
fSW Switching Frequency RT = 107k
l
495
490
500
500
505
510
kHz
kHz
Maximum Programmable Frequency RT = 53.6k 1 MHz
Minimum Programmable Frequency RT = 267k 200 kHz
DCMAX Maximum Duty Cycle Step-Down Mode, 53.6k<RT<267k
Step-Up Mode, 53.6k<RT<267k
97
87
98
93
99.5 %
%
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VIN = VOUT = 12V, VDRVCC = VINTVCC unless
otherwise noted.
LTC3351
4
Rev. A
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ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Gate Drivers
RUP-TG TGATE Pull-Up On-Resistance 2 Ω
RDOWN-TG TGATE Pull-Down On-Resistance 0.6 Ω
RUP-BG BGATE Pull-Up On-Resistance 2 Ω
RDOWN-BG BGATE Pull-Down On-Resistance 0.6 Ω
tNO Non-Overlap Time 50 ns
tON(MIN) 85 ns
INTVCC Linear Regulator
VINTVCC Internal VCC Voltage 5.2V < VIN < 35V 5 V
DVINTVCC Load Regulation IINTVCC = 50mA –1.5 –2.5 %
Ideal Diode
VFTO Fast On Threshold Voltage 65 mV
VFR Forward Regulation Voltage 30 mV
VRTO Reverse Turn Off Threshold Voltage –30 mV
UV/OV Comparator
VUV/OVI(TH) UV/OV Input Threshold (Rising Edge) l1.182 1.2 1.218 V
VUV/OVI(HYS) UV/OV Hysteresis 60 mV
IUV/OV UV/OV Input Leakage Current VUV/OV = 0.5V l–50 50 nA
VVINGD VINGD Output Low Voltage ISINK = 5mA 300 mV
IVINGD VINGD High-Z Leakage Current VINGD = 5V l1 μA
UV Falling to VINGD Low Delay 1 µs
CAPGD
VCAPFB(TH) CAPGD Rising Threshold as % of Regulated
VCAP Feedback Voltage
vcapfb_dac = Full Scale (1111b) l90 92 94 %
VCAPFB(HYS) CAPGD Hysteresis at CAPFB as a % of
Regulated VCAP Feedback Voltage
vcapfb_dac = Full Scale (1111b) 2.5 %
VCAPGD CAPGD Output Low Voltage ISINK = 5mA 200 mV
ICAPGD CAPGD High-Z Leakage Current VCAPGD = 5V l1 μA
Analog-to-Digital Converter
VRES Measurement Resolution 16 Bits
VGPI General Purpose Input Voltage Range Unbuffered
Buffered
0
0
5
3.5
V
V
IGPI General Purpose Input Pin Leakage Current Buffered Input 1 μA
RGPI GPI Pin Resistance Buffer Disabled 1.25 MΩ
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VIN = VOUT = 12V, VDRVCC = VINTVCC unless
otherwise noted.
LTC3351
5
Rev. A
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ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Measurement System Error
VERR Measurement Error (Note 5) VIN = 0V
VIN = 30V
100
1.5
mV
%
VOUT = 5V
VOUT = 30V
100
1.5
mV
%
VCAP = 0V
VCAP = 10V
100
1.5
mV
%
VGPI = 0V, Unbuffered
VGPI = 5V, Unbuffered
2
1
mV
%
VCAP1 = 0V
VCAP1 = 2V
2
1
mV
%
VCAP2 = 0V
VCAP2 = 2V
2
1
mV
%
VCAP3 = 0V
VCAP3 = 2V
2
1
mV
%
VCAP4 = 0V
VCAP4 = 2V
2
1
mV
%
VSNSI = 0mV
VSNSI = 32mV
200
2
µV
%
VSNSC = 0mV
VSNSC = 32mV
200
2
µV
%
CAP1 to CAP4
RSHNT Shunt Resistance 0.5 Ω
DVCAPMAX Maximum Shunt Operating Voltage 3.6 V
Programming Pins
VITST ITST Voltage RTST = 20Ω l1.182 1.2 1.209 V
I2C/SMBus – SDA, SCL, SMBALERT
IIL,SDA,SCL Input Leakage Low –1 1 μA
IIH,SDA,SCL Input Leakage High –1 1 μA
VIH Input High Threshold 1.5 V
VIL Input Low Threshold 0.8 V
fSCL SCL Clock Frequency 400 kHz
tLOW Low Period of SCL Clock 1.3 μs
tHIGH High Period of SCL Clock 0.6 μs
tBUF Bus Free Time Between Start and Stop
Conditions
1.3 μs
tHD,STA Hold Time, After (Repeated) Start Condition 0.6 μs
tSU,STA Setup Time After a Repeated Start Condition 0.6 μs
tSU,STO Stop Condition Set-Up Time 0.6 μs
tHD,DATO Output Data Hold Time 0 900 ns
tHD,DATI Input Data Hold Time 0 ns
tSU,DAT Data Set-Up Time 100 ns
tSP Input Spike Suppression Pulse Width 50 ns
VSMBALERT SMBALERT Output Low Voltage ISINK = 5mA 200 mV
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VIN = VOUT = 12V, VDRVCC = VINTVCC unless
otherwise noted.
LTC3351
6
Rev. A
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Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3351 is tested under pulsed load conditions such that
TJ ≈ TA. The LTC3351E is guaranteed to meet specifications from
0°C to 125°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3351I is guaranteed over the –40°C to 125°C operating junction
temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors. The junction temperature (TJ,
in °C) is calculated from the ambient temperature (TA, in °C) and power
dissipation (PD, in Watts) according to the formula:
TJ = TA + (PD • θJA)
where θJA = 36.4°C/W for the UFF package.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ISMBALERT SMBALERT High-Z Leakage Current VSMBALERT = 5V l1 μA
Hot Swap Controller
VIN(UVLO_HS) Hot Swap Input Supply Undervoltage Lockout VIN rising, Hot Swap operation l3.7 3.85 4 V
VILIM(TH) Current Limit Threshold (ISNS_HS-ISNSM) VOUT < VIN – 11V
VOUT = VIN
l
l
7
46
10
48
13
50
mV
mV
I(OV,UV,RETRYB) OV, UV, RETRYB Pin Input Current l–50 0 50 nA
VTH(RETRYB) RETRYB Threshold l185 200 215 mV
VTIMER(TH) CTIMER Pin Threshold Rising
Falling
l1.188 1.2
0.3
1.212 mV
mV
ITIMER(DN) CTIMER Pull-Down Current l1.4 2 2.6 μA
ITIMER(UP) CTIMER Pull-Up Current l320 400 480 μA
ITIMER(RATIO) CTIMER Pull-Down/Pull-Up Current l0.5 0.6 %
IHS_GATE(UP) HS_GATE Pull-Up Current l16 24 30 μA
IHS_GATE(FST) HS_GATE Fast Pull-Down Resistance VHS_GATE = VOUT 25 Ω
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VIN = VOUT = 12V, VDRVCC = VINTVCC unless
otherwise noted.
Note 3: The LTC3351 includes over temperature protection that is intended
to protect the device during momentary overload conditions. When over
temperature protection is active the switcher is shutdown. Junction
temperature will exceed 125˚C when over temperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 4: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See the Applications Information
section.
Note 5: Measurement error is the magnitude of the difference between the
actual measured value and the ideal value. VSNSI is the voltage between
ISNS_CHG and ISNSM, representing input current. VSNSC is the voltage
between ICAP and VCAP, representing charge current. Error for VSNSI and
VSNSC is expressed in μV, a conversion to an equivalent current may be
made by dividing by the sense resistors, RSNSI and RSNSC, respectively.
LTC3351
7
Rev. A
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TYPICAL PERFORMANCE CHARACTERISTICS
Hot Swap Current Limit
Fold-Back Curve Example Hot Swap, 12V Hot Swap and Full Charge Cycle
Hot Swap and Begin Charge
Hot Swap Startup into
Shorted Output Hot Swap Short Detailed
Backup Operation, 1A Backup Operation, 2A Backup Operation, 3.5A
V
IN
– V
OUT
(V)
0
2
5
7
10
12
10
18
26
34
42
50
ISNS_HS – ISNSM (mV)
3351 G01
5ms/DIV
3351 G02
IIN
0.2A/DIV
VOUT
2V/DIV
VIN
2V/DIV
500ms/DIV
3351 G03
IIN
0.5A/DIV
VOUT
2V/DIV
VCAP
2V/DIV
VIN
2V/DIV
10ms/DIV
3351 G04
IIN
0.5A/DIV
VOUT
2.0V/DIV
VCSS
0.5V/DIV
VIN
2.0V/DIV
10ms/DIV
3351 G05
IIN
0.2A/DIV
VCSS
0.5V/DIV
VCTIMER
0.5V/DIV
VIN
2.0V/DIV
500ms/DIV
3351 G08
IIN
0.5A/DIV
VOUT
2.0V/DIV
VCAP
2.0V/DIV
VIN
2.0V/DIV
300ms/DIV
3351 G09
IIN
0.5A/DIV
VOUT
2V/DIV
VCAP
2V/DIV
VIN
2V/DIV
100µs/DIV
3351 G06
IIN
0.2A/DIV
HS_GATE
0.5V/DIV
VCTIMER
0.5V/DIV
1.2s/DIV
3351 G07
IIN
0.5A/DIV
VOUT
2.0V/DIV
VCAP
2.0V/DIV
VIN
2.0V/DIV
TA = 25°C, unless otherwise noted.
LTC3351
8
Rev. A
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TYPICAL PERFORMANCE CHARACTERISTICS
IIN and ICHARGE vs VIN ICHARGE vs VCAP ICHARGE vs VCAP
IIN and ICHARGE vs IOUT Efficiency in Boost Mode VCAP vs vcapfb_dac
VCAP vs Temperature Charger Efficiency vs VCAP Charge Current vs Shunt Voltage
VCAP (V)
0
ICHARGE (A)
2.50
3.75
8
3351 G11
1.25
0246
5.00
VIN = 12V
VIN = 24V
VIN = 35V
IIN(MAX) = 2A
ICHARGE = 4A
IOUT = 0A
VCAP (V)
0
ICHARGE (A)
2.50
3.75
8
3351 G12
1.25
0246
5.00
VIN = 12V
VIN = 24V
VIN = 35V
IIN(MAX) = 2A
ICHARGE = 4A
IOUT = 1A
IOUT (A)
EFFICIENCY (%)
0.001 0.01 0.1 1 10
3351 G14
VCAP = 2V
VCAP = 3V
VCAP = 4V
VOUT = 10V
0
10
20
30
40
50
60
70
80
90
100
vcapfb_dac (CODE)
0
3
6
9
12
15
0.7
0.8
0.9
1.0
1.1
1.2
V
CAP
(V)
3351 G15
vcapfb_dac = 0xF
TEMPERATURE (C)
–40
–10
20
50
80
110
140
1.195
1.196
1.197
1.198
1.199
1.200
VCAPFB (V)
3351 G16
VIN (V)
11
CURRENT (A)
2.9
3.5
36
3351 G10
2.3
1.7 16 21 26 31
IIN
4.1
125°C
25°C
–40°C
IIN(MAX) = 2A, ICHARGE = 4A
IOUT = 1A, VCAP = 6V
ICHARGE
IOUT (A)
0
CURRENT (A)
2.50
3.75
3.00
3351 G13
1.25
00.75 1.50 2.25
IIN
5.00
VIN = 12V
VIN = 24V
VIN = 35V
IIN(MAX) = 2A, ICHARGE = 4A
ICHARGE
IIN(MAX) = 2A
IOUT = 0A
0
1.7
3.4
5.1
6.8
8.5
0
20
40
60
80
100
EFFICIENCY (%)
3351 G17
VIN = 12V
VIN = 24V
VIN = 35V
VCAP (V)
MAXIMUM CAPACITOR VOLTAGE – VSHUNT (mV)
–100
–75
–50
–25
0
25
0
10
20
30
40
50
60
70
80
90
100
CHARGE CURRENT (% OF MAXIMUM)
3351 G18
TA = 25°C, unless otherwise noted.
LTC3351
9
Rev. A
For more information www.analog.com
PIN FUNCTIONS
CAP_SLCT0, CAP_SLCT1 (Pins 1, 2): CAP_SLCT0 and
CAP_SLCT1 set the number of super-capacitors used.
Refer to Table1 in the Applications Information section.
VINGD (Pin 3): Power-Fail Status Output. This open-drain
output is pulled low when VOUT is not powered from VIN.
SCL (Pin 4): Clock Pin for the I2C/SMBus Serial Port.
SDA (Pin 5): Bidirectional Data Pin for the I
2
C/SMBus
Serial Port.
SMBALERT (Pin 6): Interrupt Output. This open-drain
output is pulled low when an alarm threshold is exceeded
and will remain low until the acknowledgement of the
part’s response to an SMBus ARA.
CAPGD (Pin 7): Capacitor Power Good. This open-drain
output is pulled low when CAPFB is below VCAPFB(TH).
VC (PIN 8): Control Voltage Pin. This is the compensation
node for the charge current, input current, supercapacitor
stack voltage and output voltage control loops. An RC
network is needed between VC and SGND. There is an
internal compensation resistor in series with this pin. It
is 1kΩ in buck mode and 2kΩ in boost mode. Nominal
voltage range for this pin is 1V to 3V.
CAPFB (Pin 9): Capacitor Stack Feedback Pin. This pin
closes the feedback loop for constant voltage regulation.
An external resistor divider between VCAP and SGND with
the center tap connected to CAPFB programs the final
supercapacitor stack voltage. This pin is nominally equal
to the output of the VCAP DAC when the synchronous
controller is charging in constant voltage mode.
OUTFB (Pin 10): Step-Up Mode Feedback Pin. This pin
closes the feedback loop for voltage regulation of VOUT
during input power failure using the synchronous control-
ler in step-up mode. An external resistor divider between
VOUT and SGND with the center tap connected to OUTFB
programs the minimum backup supply rail voltage when
input power is unavailable. This pin is nominally 1.2V
when in backup and the synchronous controller is not
in current limit. To disable step-up mode tie OUTFB to
INTVCC.
SGND (Pin 11): Signal Ground. All small-signal and com-
pensation components should be connected to this pin,
which in turn connects to PGND. SGND should connect
to PGND on top metal under the LTC3351. PGND should
be connected to the ground plane with vias under the
exposed pad (pin 45). This should be the only connection
between SGND and the ground plane.
RT (Pin 12): Timing Resistor. The switching frequency of
the synchronous controller is set by placing a resistor, RT,
from this pin to SGND. This resistor is always required.
If not present the synchronous controller will not start.
GPI (Pin 13): General Purpose Input. The voltage on this
pin is digitized directly by the ADC. For high impedance
inputs an internal buffer can be selected and used to drive
the ADC. The GPI pin can be connected to a negative
temperature coefficient (NTC) thermistor to monitor the
temperature of the supercapacitor stack. A low drift bias
resistor is required from INTVCC to GPI and a thermistor
is required from GPI to ground. Connect GPI to SGND
if not used. Read the digitized voltage on this pin in the
meas_gpi register.
ITST (Pin 14): Programming Pin for Capacitance Test
Current. This current partially discharges the capacitor
stack at a precise rate for capacitance measurement. This
pin servos to 1.2V during a capacitor measurement. A
resistor, RTST, from this pin to SGND programs the test
current. The resistor on this pin must be at least 20Ω.
Current flows from VCAP4 to this pin during this test and
must not dissipate more than 300mW in the IC.
CAPRTN (Pin 15): Capacitor Stack Shunt Return Pin.
Connect this pin to the grounded bottom plate of the first
supercapacitor in the stack through a shunt resistor.
CAP1 (Pin 16): First Supercapacitor Pin. The top plate of
the first supercapacitor and the bottom plate of the sec-
ond supercapacitor are connected to this pin through a
shunt resistor. CAP1 and CAPRTN are used to measure the
voltage across the first supercapacitor and shunt current
around the capacitor to provide balancing and prevent
overvoltage. The voltage between this pin and CAPRTN is
digitized and is read in the meas_vcap1 register.
LTC3351
10
Rev. A
For more information www.analog.com
PIN FUNCTIONS
CAP2 (Pin 17): Second Supercapacitor Pin. The top plate
of the second supercapacitor and the bottom plate of the
third supercapacitor are connected to this pin through a
shunt resistor. CAP2 and CAP1 are used to measure the
voltage across the second supercapacitor and to shunt
current around the capacitor to provide balancing and pre-
vent overvoltage. If not used, this pin should be shorted to
CAP1. The voltage between this pin and CAP1 is digitized
and is read in the meas_vcap2 register.
CAP3 (Pin 18): Third Supercapacitor Pin. The top plate of
the third supercapacitor and the bottom plate of the fourth
supercapacitor are connected to this pin through a shunt
resistor. CAP3 and CAP2 are used to measure the voltage
across the third supercapacitor and shunt current around
the capacitor to provide balancing and prevent overvolt-
age. If not used, this pin should be shorted to CAP2. The
voltage between this pin and CAP2 is digitized and is read
in the meas_vcap3 register.
CAP4 (Pin 19): Fourth Supercapacitor Pin. The top plate of
the fourth supercapacitor is connected to this pin through
a shunt resistor. CAP4 and CAP3 are used to measure the
voltage on the capacitor and shunt current around the
supercapacitor to provide balancing and prevent overvolt-
age. If not used, this pin should be shorted to CAP3. The
voltage between this pin and CAP3 is digitized and is read
in the meas_vcap4 register. The capacitance test current
set by the ITST pin is pulled from this pin.
CFP (Pin 20): VCAPP5 Charge Pump Flying Capacitor
Positive Terminal. Place a 6.3V 0.1μF between CFP and CFN.
CFN (Pin 21): VCAPP5 Charge Pump Flying Capacitor
Negative Terminal. Place a 6.3V 0.1μF between CFP and CFN.
VCAPP5 (Pin 22): Charge Pump Output. The internal
charge pump drives this pin to VCAP + INTVCC. It is used
as the high side rail for the OUTFET gate drive and charge
current sense amplifier. Connect a 6.3V 0.1μF capacitor
from VCAPP5 to VCAP.
OUTFET (Pin 23): Output Ideal Diode Gate Drive Output.
This pin controls the gate of an external N-channel
MOSFET used as an ideal diode between VOUT and
VCAP. The gate drive receives power from the internal
charge pump output VCAPP5. Connect the source of the
N-channel MOSFET to VCAP and the drain to VOUT. If the
output ideal diode MOSFET is not used, OUTFET should
be left floating.
VCAP (Pin 24): Supercapacitor Stack Voltage and Charge
Current Sense Amplifier Negative Input. Connect this pin
to the top of the supercapacitor stack. The voltage at this
pin is digitized and is read in the meas_vcap register.
ICAP (Pin 25): Charge Current Sense Amplifier Positive
Input. The ICAP and VCAP pins measure the voltage across
the sense resistor, RSNSC, to provide instantaneous cur-
rent signals for the control loops and ESR measurement
system. The maximum charge current is 32mV/RSNSC.
The voltage between this pin and VCAP is the charging/
discharge current as read in the meas_ichg register.
VCC2P5 (Pin 26): Internal 2.5V Regulator Output. This
regulator provides power to the internal logic circuitry
only. Decouple this pin to SGND with a minimum 1μF low
ESR ceramic capacitor.
SW (Pin 27): Switch Node Connection to the Inductor. The
negative terminal of the boot-strap capacitor, CB, is con-
nected to this pin. The voltage on this pin is also used as
the source reference for the top side N-channel MOSFET
gate drive. In step-down mode, the voltage swing on
this pin is from a diode (external) forward voltage below
ground to VOUT. In step-up mode, the voltage swing is
from ground to a diode forward voltage above VOUT.
TGATE (Pin 28): Top Gate Driver Output. This pin is
the output of a floating gate driver for the top external
N-channel MOSFET. The voltage swing at this pin is
ground to VOUT + DRVCC.
BST (Pin 29): TGATE Driver Supply Input. The positive
terminal of the boot-strap capacitor, CB, is connected to
this pin. This pin swings from a diode voltage drop below
DRVCC up to VOUT + DRVCC.
BGATE (Pin 30): Bottom Gate Driver Output. This pin
drives the bottom external N-channel MOSFET between
PGND and DRVCC.
DRVCC (Pin 31): Power Rail for the Bottom Gate Driver.
Connect to INTVCC or to an external supply. Decouple
this pin to ground with a minimum 6.3V 2.2μF low ESR
ceramic capacitor. Do not exceed 5.5V on this pin.
LTC3351
11
Rev. A
For more information www.analog.com
INTVCC (Pin 32): Internal 5V Regulator Output. The con-
trol circuits and gate drivers (when connected to DRVCC)
are powered from this supply. If not connected to DRVCC,
decouple this pin to ground with a minimum 4.7μF low
ESR ceramic capacitor.
VOUT (Pin 33): Output Voltage Supply. This pin supplies
power to the LTC3351 after the hot swap start-up has
finished. The switching controller charges the capacitor
stack from the voltage at this pin and the LTC3351 backs
up the voltage at this pin if the input voltage goes outside
the OV/UV range or an input current fault occurs.
RETRYB (Pin 34): Retry Comparator Input. The hot swap
controller will not attempt to connect V
IN
and V
OUT
unless
this pin is below 200mV. This high voltage capable pin
may be connected to VOUT if the system needs to be fully
powered down before repowering after a power loss and
backup.
ISNSM (Pin 35): Input Current Sense Pin. This is the neg-
ative input for both the hot swap current sense amplifier
and the switching charger input current sense amplifier.
ISNSP_CHG (Pin 36): Input Current Sense Pin. This is
the positive input for the switching charger input current
sense amplifier. The switching charger will reduce charge
current to keep the voltage between this pin and ISNSM to
32mV. The current is measured using the sense resistor
between this pin and ISNSM and is measured by the ADC
and reported in the meas_iin register.
ISNSP_HS (Pin 37): Input Current Sense Pin. This is the
positive input for the hot swap input current sense ampli-
fier. The hot swap controller will limit the voltage between
this pin and ISNSM to 48mV. This pin is also the input
current sense for the circuit breaker function.
CSS (Pin 38): Soft Start and Delay Capacitor Pin. A capac-
itor from this pin to VOUT determines both the maximum
dV/dt of VOUT during the power up and the debounce
delay from OV and UV becoming good before attempting
to reconnect VIN and VOUT.
SRC (Pin 39): Hot Swap/Input FETs Source Pin. This pin
senses the source voltage of the hot swap and input FETs.
HS_GATE (Pin 40): Hot Swap/Input FETs Gate Pin. This
pin controls the external hot swap/input FETs. This pin is
pulled up to, at most, VINTVCC above the VOUT pin.
VIN (Pin 41): External DC Power Source Input and Sense
Pin. For VIN voltages greater than 8V, a 100Ω resistor in
series with this pin is required. The voltage at this pin is
digitized and is reported in the meas_vin register.
UV (Pin 42): Power-Fail Comparator Input. When the
voltage at this pin drops below VUV(TH), the hot swap
controller is disconnected, the part enters backup mode
and VINGD is pulled low.
OV (Pin 43): Power-Fail Comparator Input. When the volt-
age at this pin exceeds VOV(TH), the hot swap controller is
disconnected, the part enters backup mode and VINGD
is pulled low.
CTIMER (Pin 44): Fault and Retry Timing Capacitor. A
capacitor from this pin to SGND programs the fault and
retry timing. During an over current fault condition this
capacitor is charged with ITIMER(UP) (400µA). Once this
pin voltage exceeds VTIMER(TH) (1.2V) a fault is declared
and VOUT is disconnected from VIN. This pin is continu-
ously discharged with ITIMER(DN) (2µA), and once it dis-
charges to 300mV, and RETRYB is low, the hot swap
controller will again attempt to reconnect VIN and VOUT.
PGND (Exposed Pad Pin 45): Power Ground. For rated
thermal performance connect the exposed pad to a con-
tinuous ground plane on the second layer of the printed
circuit board by several vias directly under the LTC3351.
Connect the exposed pad to the SGND pin on top copper.
PIN FUNCTIONS
LTC3351
12
Rev. A
For more information www.analog.com
BLOCK DIAGRAM
16
+
–
VFR
IN
T
V
CC
V
REF
vcapfb_dac[3:0]
Vcapfb_dac
vcapfb_dac
V
IN
CAPFB
OUTFB
VC
R
T
IN
T
V
CC
V
OUT
+
–
x3
7
.5
I
CHG
5V LDO
D/A
16-BIT
A/D
V
REF
IN
T
V
CC
+
–
x3
7
.5
I
IN
VREF
+
–
V
REF
V
OUT
I
REF
+
–
+
–
+
–
OUTFET
CFN
VCAPP5
CFP
VCAP
ICAP
BST
TG
A
TE
SW
+
–
CHARGE
PUMP
D
R
V
CC
BG
A
TE
CAP4
BIDIRECTIONAL
SWITCHING
CONTROLLER
LOGIC
VCC2P5
I
IN
ICHG
VCAP
V
OUT
V
IN
CAP4
CAP3
CAP2
CAP1
CAP
R
TN
DTEMP
CAPGD
GPI
SGND
BANDGAP
V
REF
OSC
2.5V LDO
START-UP
LDO
SHUNT
CONTROLLER
CAP3
BALANCER
SHUNT
CONTROLLER
CAP2
BALANCER
SHUNT
CONTROLLER
CAP1
BALANCER
SHUNT
CONTROLLER
CAP
R
TN
ITST
BALANCER
+
–
V
REF
3351 BD
GPIBUF
+
–
CAPFB
MU
L
TIPLEXER
CAP_SLCT0
CAP_SLCT1
SMBALERT
SDA
SCL
+
–
41
44
40
35
33
23
20
21
22
24
25
29
28
27
31
30
19
18
17
16
15
14
13
11
PGND
45
4
5
6
2
1
3
7
26
32
12
8
10
9
38
V
REF
43
42
UV
OV
CSS
CTIMER
39
HOT SWAP
CONTROLLER
HS_GATE
SRC
ISNSM
36
ISNSP_CHG
37
ISNSP_HS
RETRYB
34
VINGD
VIN
1k (BUCK)
2k (BOOST)
VPEAK
LTC3351
13
Rev. A
For more information www.analog.com
TIMING DIAGRAM
Definition of Timing for F/S Mode Devices on the I2C Bus
SDA
SCL
S Sr P S
tHD(SDA)
S = START, Sr = REPEATED START, P = STOP
tHD(DAT)
tSU(STA) tSU(STO)
tSU(DAT)
tLOW tHD(SDA) tSP
tBUF
trtftr
tf
tHIGH 3351 TD
I2C/SMBus Legend
S START CONDITION
Sr REPEATED START CONDITION
Rd READ (BIT VALUE OF 1)
Wr WRITE (BIT VALUE OF 0)
A ACKNOWLEDGE
N NACK
P STOP CONDITION
PEC* PACKET ERROR CODE
MASTER TO SLAVE
SLAVE TO MASTER
SMBus WRITE WORD PROTOCOL
S SLAVE ADDRESS Wr A COMMAND CODE A DATA BYTE LOW A DATA BYTE HIGH A P
SMBus WRITE WORD WITH PEC PROTOCOL
S SLAVE ADDRESS Wr A COMMAND CODE A DATA BYTE LOW A DATA BYTE HIGH A PEC* A P
SMBus READ WORD PROTOCOL
S SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A DATA BYTE LOW A DATA BYTE HIGH N P
SMBus READ WORD WITH PEC PROTOCOL
S SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A DATA BYTE LOW A DATA BYTE HIGH A PEC* N P
SMBus ALERT RESPONSE ADDRESS PROTOCOL
S ALERT RESPONSE ADDRESS Rd A DEVICE ADDRESS Rd N P
SMBus ALERT RESPONSE ADDRESS PROTOCOL WITH PEC
S ALERT RESPONSE ADDRESS Rd A DEVICE ADDRESS Rd A PEC* N P
*USE OF PACKET ERROR CHECKING IS OPTIONAL
LTC3351
14
Rev. A
For more information www.analog.com
OPERATION
Introduction
The LTC3351 is a highly integrated backup power control-
ler and system monitor. It features a bidirectional switch-
ing controller, hot swap controller, output ideal diode,
supercapacitor shunts/balancers, under and over voltage
comparators, a 16-bit ADC, and I2C/SMBus programma-
bility with status reporting.
If VIN is within externally programmable UV/OV threshold
voltages, the hot swap controller connects VIN to VOUT
and the synchronous switching controller operates in
step-down mode charging a stack of supercapacitors. A
programmable input current limit ensures that the super-
capacitors will automatically be charged at the highest
possible charge current that the input can support. If VIN
goes outside the UV/OV thresholds, or if the hot swap
controller’s circuit breaker trips, or if a simulated failure
is requested, then the hot swap controller will disconnect
VOUT from VIN and the synchronous controller will run in
reverse as a step-up converter to deliver power from the
supercapacitor stack to VOUT.
An ideal diode controller drives an external MOSFET to
provide a low loss power path from VCAP to VOUT. This
ideal diode works seamlessly with the bidirectional con-
troller to provide power from the supercapacitors to
VOUT. The hot swap controller utilizes two back-to-back
MOSFETs to control inrush, provide a short circuit breaker
function and prevent back driving VIN while in backup
mode.
The LTC3351 provides balancing and overvoltage protec-
tion to a series stack of one to four supercapacitors. The
internal capacitor voltage balancers eliminate the need
for external balance resistors. Overvoltage protection is
provided by shunt regulators that use an internal switch
and an external resistor across each supercapacitor.
The LTC3351 monitors system voltages, currents, and
its own die temperature. A general purpose input (GPI)
pin is provided to measure an additional system param-
eter or implement a thermistor measurement. In addition,
the LTC3351 can measure the capacitance and equiva-
lent series resistance of the supercapacitor stack. This
provides indication of the health of the supercapacitors
and, along with the VCAP voltage measurement, provides
information on the total energy stored and the maximum
power that can be delivered.
Operations Example
The LTC3351 is a highly integrated circuit with many fea-
tures and operating modes. To better explain the opera-
tions of the LTC3351, a simplified example will be used.
This example is graphically shown in Figure1 and will be
referred to throughout. Due to the widely varying time
scales of the events with which the LTC3351 operates,
the time axis of Figure1 is not to scale.
The example begins with V
IN
and V
CAP
at 0V. V
IN
is applied
suddenly at the point labeled “hot plug”. There is a very
small inrush current into the drain capacitance of the
hot swap FET connected to VIN, this is shown as a small
“spike” on the IIN waveform. This “spike” is very small in
either duration or amplitude, depending on the rise rate
of VIN. During the time labeled “debounce”, the LTC3351
qualifies the input as good using the UV and OV compara-
tors and expires an input debounce timer using the CSS
pin. Once this debounce time has passed, the LTC3351
begins turning on the hot swap FETs to charge the capaci-
tance on V
OUT
in a controlled way, during which time both
the input current and rise rate of VOUT are controlled.
This results in a low constant IIN current while the VOUT
capacitance is charged.
Once V
OUT
has been charged to V
IN
, the charger is allowed
to start charging the supercapacitors. For this example; at
the beginning of the charge cycle the supercapacitors are
fully discharged. The charger will begin with constant cur
-
rent charging of the supercapacitors. Since the capacitor
voltage is very low, the power delivered is very low. This
low power delivery results in a low input current despite
high charge current. As the voltage on the supercapaci-
tors rises, the delivered power also rises and thus the
input current also rises. This constant current phase of
charging is labeled “CC Charging.”
In this example IOUT, the downstream system load, turns
on during the constant current phase of charging. When
this happens is outside the control of the LTC3351 and its
timing in this example is arbitrary. Since output current
LTC3351
15
Rev. A
For more information www.analog.com
OPERATION
is supplied from VIN via the hot swap FETs this step in
load current directly causes a step in input current. The
charge current is unaffected by this load step because the
LTC3351 is not in input current limit.
As the supercapacitors charge, their voltage increases and
the input current increases due to the increasing power
being delivered to the supercapacitors. In this example
the increasing input current reaches the input current
limit at the beginning of the time labeled “CP charg-
ing.” With a constant input voltage, input current limit
causes the LTC3351 to effectively have an input power
limit. Depending on the settings of the input current limit,
charge current limit, charge voltage, system load current
and input voltage the charging phase of operation may or
may not reach the input current limit.
During the constant power phase of charging, the charge
current decreases as the charge voltage increases to
maintain constant input power. This results in a slowing
rate of charge as the charger approaches constant volt-
age charging. Once V
CAP
reaches the programmed charge
voltage, the constant voltage phase of charging begins.
This is labeled “CV charging.”
During constant voltage charging, current is being deliv-
ered to the supercapacitors and there is a voltage drop
across their internal ESR (equivalent series resistance).
The LTC3351 holds the VCAP voltage constant during
this phase. Holding the VCAP voltage constant allows the
voltage across this ESR to fall towards zero as the inter-
nal capacitance is charged to VCAP. During this time the
charge current decays toward the leakage current of the
capacitors.
The LTC3351 CV charges forever, waiting for a power
failure, while keeping the capacitors charged, balanced
and ready for backup. While fully charged and standing
by for backup, the LTC3351 can also measure the ESR
and capacitance of the batteries if requested (not shown
in Figure1). This is the condition the LTC3351 is likely to
spend most time in, assuming input power loss is infre-
quent as is typically the case.
When power does fail, as labeled “power failure” in
Figure1, the OV or UV comparators detect the power
failure at the input. The hot swap FET is turned off to
isolate VOUT from VIN. Once the FET is off, VOUT imme-
diately falls to VCAP (or the programmed boost voltage if
Figure1.
VIN
VCAP
VOUT
IIN
ICAP
IOUT
HOT
PLUG
DEBOUNCE CC CHARGING
CP CHARGING
CV CHARGING AND BALANCING
POWER FAILURE
IDEAL DIODE BACKUP
TIME (NOT TO SCALE)
0
0
VOLTAGECURRENT
INRUSH
CONTROL
3351 F01
BOOST BACKUP
LTC3351
16
Rev. A
For more information www.analog.com
OPERATION
+
+
+
+
+
–
INPUT
CURRENT
CONTROLLER
CHARGE
CURRENT
CONTROLLER
BIDIRECTIONAL
SWITCHING
CONTROLLER
STEP-DOWN MODE
V
REF
I
IN
V
IN
V
IN
LTC3351
HS_GATE
ISNSP_CHG
ISNSM
V
OUT
(TO SYSTEM)
TGATE
I
CHG
BGATE
ICAP
VCAP
R
SNSC
R
SNSI
3351 F02
+
–
I
REF
V
REF
CAPACITOR
VOLTAGE
CONTROLLER
+
–
+
–
CAPFB
VC
37.5
D/A
vcapfb_dac[3:0]
+
–
SRC
ISNSP_HS
HOT SWAP
CONTROLLER
37.5
Figure2. Power Path Block Diagram - Power Available from VIN
it is higher, however in this example it is not). The ideal
diode FET between VCAP and VOUT is turned on during
the time labeled “ideal diode backup.” While operating in
ideal diode backup, power is supplied directly from the
capacitors without conversion. V
CAP
is discharged during
this time and VOUT falls along with VCAP.
Once the V
OUT
voltage approaches the programmed boost
voltage, the boost converter is turned on and the ideal
diode turned off. The boost converter then supplies the
output at constant voltage. As the capacitor voltage falls,
the capacitor current must increase to supply the constant
power load at VOUT. This continues until either the boost
reaches its current limit or exhausts the available energy
in the capacitors. This time is labeled “boost backup.”
Bidirectional Switching Controller—Step-Down Mode
The bidirectional switching controller is designed to
charge a series stack of supercapacitors (Figure 2).
Charging proceeds at a constant current until the super-
capacitors reach their maximum charge voltage deter-
mined by the CAPFB servo voltage and the resistor divider
between VCAP and CAPFB. The maximum charge current
is determined by the value of the sense resistor, RSNSC,
connected in series with the inductor. The charge cur-
rent loop servos the voltage across the sense resistor
to 32mV. When charging begins, an internal soft-start
ramp gradually increases the charge current. The VCAP
voltage and charge current are read from the meas_vcap
and meas_ichg registers, respectively.
LTC3351
17
Rev. A
For more information www.analog.com
OPERATION
The LTC3351 provides constant power charging (for
a fixed V
IN
) by limiting the input current drawn by the
switching controller in step-down mode. The charger
input current limit will reduce charge current to limit
the voltage between ISNSP_CHG and ISNSM, typically
across RSNSI, to 32mV. If the combined system load plus
supercapacitor charge current is large enough to cause
the switching controller to reach the programmed input
current limit, the input current limit loop will reduce the
charge current by precisely the amount necessary to
enable the external load to be satisfied. Even if the charge
current is programmed to exceed the allowable input cur-
rent, the input current limit will not be violated; the super-
capacitor charger will reduce its current as needed. The
input current is read from the meas_iin register.
Bidirectional Switching Controller—Step-Up Mode
The bidirectional switching controller acts as a step-up
converter to provide power from the supercapacitors to
VOUT when input power is unavailable (Figure3). VINGD
low enables step-up mode. VOUT regulation is set by a
resistor divider between V
OUT
and OUTFB. To disable step-
up mode tie OUTFB to INTVCC.
Step-up mode is often used with the output ideal diode.
If the VOUT regulation voltage is set below the capacitor
stack voltage, upon removal of input power, power to VOUT
is provided from the supercapacitor stack via the output
ideal diode. VCAP and VOUT will decrease as the load cur-
rent discharges the supercapacitor stack. The output ideal
diode will shut off and VOUT will fall a PN diode (~700mV)
below VCAP when the voltage on OUTFB falls below 1.3V
(VOUTFB(TH)). If OUTFB falls below 1.2V when the output
ideal diode shuts off, the synchronous step-up controller
will turn on immediately to regulate OUTFB to 1.2V by
providing power from the supercapacitor stack. If OUTFB
is above 1.2V when the output ideal diode shuts off, the
load current will flow through the body diode of the output
ideal diode N-channel MOSFET for a period of time until
OUTFB falls to 1.2V.
+
+
+
+
+
–
+
–
VFR
OUTPUT
VOLTAGE
CONTROLLER
BIDIRECTIONAL
SWITCHING
CONTROLLER
STEP-UP MODE
V
REF
LTC3351
V
OUT
V
OUT
(TO SYSTEM)
V
CAP
> V
OUT
V
CAP
< V
OUT
TGATE
OUTFET
OUTFB
BGATE
ICAP
VCAP
R
SNSC
3351 F03
VC
+
–
Figure3. Power Path Block Diagram - Power Backup
LTC3351
18
Rev. A
For more information www.analog.com
OPERATION
The synchronous controller in step-up mode will run non-
synchronously when V
CAP
is less than 90mV (V
DUVLO
fall-
ing) below VOUT. It will run synchronously when VCAP falls
200mV (VDUVLO rising) below VOUT.
Hot Swap Controller
Upon applying power to VIN, the LTC3351 will immediately
turn on a strong pull-down on the HS_GATE pin to pre-
vent the external FETs from conducting current from VIN
to VOUT. During the initial VIN rise the LTC3351 may limit
the rise rate of the voltage at the VIN pin by drawing cur-
rent through the 100Ω resistor in series with the pin. The
LTC3351 will then drive the INTVCC pin to 3.6V using cur-
rent from the VIN pin. Once the INTVCC voltage is greater
than 3.3V the hot swap turn-on sequence will begin.
If both the under voltage (UV) and (OV) comparators are
in range, the CSS pin will begin to source 1μA of current,
charging the C
SS
capacitor. Once the CSS pin reaches
1.2V and the RETRYB pin is below 200mV (VTH(RETRYB))
the LTC3351 will begin the process of connecting V
IN
and
V
OUT
using the external FETs. The LTC3351 will begin pull-
ing up on the HS_GATE pin using 24μA (IHS_GATE(UP)) of
current. As VOUT begins to rise, the capacitor from VOUT
to the CSS pin provides feedback to the LTC3351 about
the rise rate of the output. Therefore, the sizing of the CSS
capacitor determines the maximum slew rate of V
OUT
and
the inrush current.
During the ramp up of HS_GATE and VOUT, both the cur-
rent limit and the circuit breaker are active. VIN to VOUT
differential foldback reduces both the current limit and cir-
cuit breaker threshold while charging the output capaci-
tor; this reduces the required SOA of the hot swap FETs.
If, at any time, the under voltage (UV) or overvoltage
(OV) comparators go out of range, or if the CTIMER pin
reaches 1.2V (VTIMER(TH)), the LTC3351 will declare a
fault and quickly turn off the external FET by grounding
HS_GATE. The FET sources will be kept within a safe volt-
age of the gate by the SRC pin. Once a fault is declared the
LTC3351’s backup controller will begin supplying power to
VOUT from the energy stored in the capacitor stack. This
will continue until either a new turn-on sequence occurs,
the supercapacitor stored energy is depleted, or the boost
is disabled via I2C/SMBus.
The LTC3351 will limit the current from V
IN
to V
OUT
through
the external FETs using the voltage across the current sense
resistor(s) sensed using the ISNSP_HS and ISNSM pins.
When VOUT is within 1V of VIN the LTC3351 will limit the
voltage across the ISNSP_HS and ISNSM pins to 48mV
(VILIM(TH)). To limit power in the external FET this limit
is folded back to 10mV as the voltage from V
IN
to V
OUT
increases from 1V to 10V. Above 10V the limit remains
at 10mV. This current limit is separate from the switching
charger’s input current limit. The switching charger’s input
current limit is unaffected by the above described fold back.
The LTC3351’s CTIMER pin will source current when the
input current is within 1.66% of the input current limit. As
with the input current limit, this threshold is folded back
as the voltage from V
IN
to V
OUT
increases. The current
sourced from the CTIMER pin to the CTIMER capacitor is
about 400µA (ITIMER(UP)). Once the voltage at the CTIMER
pin exceeds 1.2V (VTIMER(TH) rising) a fault is declared
and the turn-off sequence is initiated. The CTIMER pin
has a static 2μA (ITIMER(DN)) load that discharges the
CTIMER capacitor. Once a fault is declared the CTIMER
pin must fall below 300mV before the turn-on sequence
is re-attempted.
RETRYB Pin
The LTC3351’s RETRYB pin determines if the LTC3351
tries to connect VIN and VOUT after a fault. The faults are
UV, OV, circuit breaker (CTIMER), or a simulated fault pro-
grammed via the I
2
C/SMBus port by setting ctl_hotswap_
disable. If the RETRYB pin is low (VTH(RETRYB) below
200mV) the LTC3351 will try to connect VIN and VOUT
using the hot swap controller. The RETRYB pin is high
voltage tolerant and high impedance. A divider from V
OUT
to RETRYB allows a precise threshold to be set. This can
be used to ensure the system completely powers down
following a failure before re-powering.
VINGD Pin
The VINGD pin indicates that the input voltage is within
the OV/UV range and the system is powered from V
IN
. For
VINGD to be high, the voltage at UV must be above 1.2V
(VOV rising) the voltage at OV must be below 1.17V (VUV
falling), the circuit breaker must not be tripped, the hot
LTC3351
19
Rev. A
For more information www.analog.com
OPERATION
swap must not be disabled via I2C/SMBus, and the hot
swap controller must have completed connecting V
IN
and
VOUT. The state of the VINGD pull-down is read from the
vingd bit in the sys_status register.
If UV is set to a level near or less than the charge voltage
of the capacitors, VIN becomes high impedance and the
VOUT load is very low, it is possible for a small amount
of current to flow from VCAP to VIN through VOUT due to
the maximum duty cycle operation. In this condition, the
high duty cycle buck is effectively a reverse low duty cycle
boost. The boost has a small amount of output current
that holds VIN above VCAP and possibly UV, causing the
part to falsely indicate VINGD. Eventually V
CAP
will be dis-
charged below the programmed UV threshold and VINGD
will indicate correctly. This situation can be avoided by
programming the UV threshold at least 3% above the
capacitor charge voltage.
Ideal Diode
The LTC3351 has an ideal diode controller that drives an
external N-channel MOSFET between VCAP and VOUT. The
ideal diode consists of a precision amplifier that drives
the gates of N-channel MOSFETs whenever the voltage at
VOUT is approximately 30mV (VFR) below the voltage at
VCAP. Within the amplifier’s linear range, the small-signal
resistance of the ideal diode will be quite low, keeping the
forward drop near 30mV. At higher current levels, the
MOSFETs will be in full conduction.
The ideal diode provides a path for the supercapacitors
to power VOUT when VIN is unavailable or the hot swap
controller is disconnected. In addition to a Fast-Off com-
parator, the ideal diode also has a Fast-On comparator that
turns on the external MOSFET when V
OUT
drops 65mV
(VFTO) below VCAP. The ideal diode will shut off when
OUTFB is just above regulation allowing the synchronous
controller to power VOUT in step-up mode.
Gate Drive Supply (DRVCC)
The bottom gate driver is powered from the DRVCC pin,
which is normally connected to the INTVCC pin. An exter-
nal LDO can also be used to power the gate drivers to
minimize power dissipation inside the LTC3351. See the
Applications Information section for details.
Switcher/Charger Undervoltage Lockout (UVLO)
Internal undervoltage lockout circuits monitor both the
INTVCC and DRVCC pins. The switching controller is kept
off until INTV
CC
rises above V
UVLO
(4.3V) and DRV
CC
rises
above V
DRVUVLO
(4.2V). The controller is disabled if either
INTVCC falls below 4V or DRVCC falls below 3.9V.
Charging is disabled until VOUT is VDUVLO (200mV) above
the supercapacitor voltage and VINGD is high. Charging
is disabled when VOUT falls to within 90mV of the super-
capacitor voltage or when VINGD is low.
RT Oscillator and Switching Frequency
The RT pin is used to program the switching frequency.
A resistor, RT, from this pin to ground sets the switching
frequency according to:
fSW MHz
( )
=53.5
R
T
kΩ
( )
RT also sets the scale factor for the capacitor measure-
ment value reported in the meas_cap register, described
in the ESR and Capacitance Measurement section of this
data sheet.
Switching Controller Input Overvoltage Protection
Input overvoltage protection turns off both switching
controller switches if VIN exceeds VOVLO (38.6V). The
controller will resume switching if VIN falls below 37.2V.
The hot swap controller is unaffected by this and uses its
own programmable OV threshold.
VCAP DAC
The feedback reference for the CAPFB servo point is pro-
grammed using an internal 4-bit digital-to-analog con-
verter (DAC). The reference voltage is programmable from
0.6375V (VCAPFBLO) to 1.2V (VCAPFBHI) in 37.5mV incre-
ments. The DAC defaults to 0xA (VCAPFB_DEF 1.0125V) and
is programmed via the vcapfb_dac register.
Supercapacitors lose capacitance as they age. By initially
setting the VCAP DAC to a low setting, the final charge
voltage on the supercapacitors can be increased as they
age to maintain a constant level of stored backup energy
throughout the lifetime of the supercapacitors. The
LTC3351
20
Rev. A
For more information www.analog.com
OPERATION
capacitance and ESR measurement system may tempo-
rarily increase this DAC to a value as much as full scale
(1.2V) during the ESR test.
If using the capacitance and ESR test, the highest usable
DAC setting will be determined by the voltage increase
between that setting and 1.2V at the CAPFB pin, wherein
the capacitor stack’s voltage increases by 1.25 times the
voltage specified in cap_delta_v_setting.
Charge Status Indication
The LTC3351 includes a comparator to report the status
of the supercapacitors via an open-drain NMOS tran-
sistor on the CAPGD pin. This pin pulls to ground until
the CAPFB pin voltage rises to within nominally 8% of
the VCAP DAC setting. Once the CAPFB pin is above this
threshold, the CAPGD pin goes high impedance. The out-
put of this comparator may also be read from the cappg
bit in the sys_status register.
Capacitor Voltage Balancer
The LTC3351 has an integrated active stack balancer. This
balancer slowly balances all of the capacitor voltages to
within approximately 10mV of each other. This maximizes
the life of the supercapacitors by keeping the voltage on
each as low as possible to achieve the needed total stack
voltage. When the difference between any two capaci-
tor voltages exceeds approximately 10mV, the capacitor
with the largest voltage is discharged with a resistive bal-
ancer (approximately 75Ω until all capacitor voltages are
within 10mV). The balancers can be disabled by setting
the ctl_disable_balancer bit.
Capacitor Shunt Regulators
During charging, the capacitors are protected from over-
voltage. The capacitors in the stack will not have exactly
the same capacitance due to manufacturing tolerances
or uneven aging. This will cause the capacitor voltages
to increase at different rates with the same charge cur-
rent. If this mismatch is severe enough or if the capaci-
tors are being charged to near their maximum voltage, it
becomes necessary to limit the voltage increase on some
capacitors while still charging the other capacitors. Up
to 500mA of current may be shunted around a capacitor
whose voltage is approaching the programmable shunt
voltage. This shunt current reduces the charge rate of that
capacitor relative to the other capacitors. If a capacitor
continues to approach its shunt voltage, the stack charge
current is reduced. This protects the capacitor from over-
voltage while still charging the other capacitors, although
at a reduced rate of charge. When shunting, the internal
switch may be on more than 96% duty cycle. The shunts
are disabled by setting the ctl_disable_shunt bit. The shunt
voltage is programmable in the vshunt register. Shunt
voltages may be programmed in 183.5µV increments. If
a voltage greater than 3.6V is programmed, the charge
current will be reduced as that voltage is approached but
the shunt will not turn on. The default value is 0x3999,
resulting in a shunt voltage of approximately 2.7V. See
Register Map for more information.
I2C/SMBus and SMBALERT
The LTC3351 contains an I
2
C/SMBus compatible port.
This port allows communication with the LTC3351 for
configuration and reading back telemetry data. The port
supports two SMBus formats, read word and write word.
These may be used with or without the packet error code
(PEC) feature. Refer to the SMBus specification for details
of these formats and PEC. The registers accessible via
this port are organized on an 8-bit address bus and each
register is 16 bits wide. The “command code” (or sub-
address) of the SMBus read/write word formats is the
8-bit address of each of these registers. The address of
the LTC3351 is 0b0001001.
The SMBALERT pin is asserted (pulled low) whenever
an enabled limit is exceeded or when an enabled status
event happens (see the Limit Checking and Alarms and
the Monitor Status Register sections of this data sheet).
The LTC3351 will de-assert the SMBALERT pin only after
responding to a SMBus alert response address (ARA),
an SMBus protocol used to respond to a SMBALERT.
The host will read from the ARA (0b0001100) and each
part asserting SMBALERT will begin to respond with its
address. The responding parts arbitrate in such a way
that only the part with the lowest address responds com-
pletely. Only when a part has responded with its entire
address does it release the SMBALERT signal. If multiple
parts are asserting the SMBALERT signal then multiple
LTC3351
21
Rev. A
For more information www.analog.com
OPERATION
reads from the ARA are needed. For more information
refer to the SMBus specification.
Details on the registers accessible through this interface
are available in the Register Map section of this data sheet.
For I
2
C masters unable to create the repeated start needed
for the read and write word protocols, a stop followed by
a start may be substituted.
Analog-to-Digital Converter
The LTC3351 has an integrated 16-bit sigma-delta analog-
to-digital converter (ADC). This converter is automatically
multiplexed between the measured channels. Its results
are stored in registers accessible via the I2C/SMBus port.
There are 11 channels measured by the ADC, each of
which takes approximately 800µs to measure. In addition
to providing status information about the system voltages
and currents, some of these measurements are used by
the LTC3351 to balance, protect (shunt), and measure the
capacitors in the stack.
The result of each analog-to-digital conversion is stored in
a 16-bit register as a signed, two’s complement number.
To reduce average quiescent current, the effective duty
cycle of the ADC can be reduced by programming adc_
wait_vin and/or adc_wait_backup. Each register inserts a
delay in the ADC’s measurement cycle during its respec-
tive mode of operation. Each LSB of these registers has
a weight of approximately 400µs. At some times, such
as when shunting or making capacitance and ESR mea-
surement, these settings may be temporarily ignored.
Measurements of individual channels may be enabled or
disabled by setting the appropriate bit in adc_backup_ch_
en_reg and adc_vin_ch_en_reg.
The measurements from the ADC are stored to meas_
vcap1, meas_vcap2, meas_vcap3, meas_vcap4, meas_
gpi, meas_vin, meas_vcap, meas_vout, meas_iin, meas_
ichg and meas_dtemp.
ESR and Capacitance Measurement
The LTC3351 monitors the health of a supercapacitor
stack by measuring the capacitance and the ESR. Both
the capacitance and ESR are measured in a single test.
The LTC3351 measures ESR by applying and measuring a
current step with the high efficiency charger and measur-
ing the change in voltage. The capacitance is measured
by discharging a fixed voltage with a known current and
measuring time.
The ESR and capacitance measurement sequence, initi-
ated by setting ctl_start_cap_esr_meas, is:
1. The mon_meas_active and mon_esr_meas_active bits
become high if the capacitors are charged, otherwise,
mon_capesr_pending becomes high.
2. The charger is configured to charge at a pre-set current
up to a full vcapfb_dac setting, this current is set using
an 8 bit DAC controlled either by:
a. An internal algorithm that selects the optimal cur-
rent based on the previous capacitor measurement
(assuming the LTC3351 is not in input current limit)
b. An override setting, programmed in esr_i_override, is
used if non-zero. If it is likely the LTC3351 will operate
in input current limit while charging, then this should
be set low enough to avoid input current limit.
3. The measurement system waits esr_i_on_settling for
the current and capacitor effects to stabilize. Each LSB
of esr_i_on_settling is 1024 switcher periods.
4. A series of measurements of capacitor voltages and
charge currents are made. The charger is then tem-
porarily shut off.
5. The measurement system waits esr_i_off_settling for
the current and capacitor effects to stabilize. Each LSB
of esr_i_off_settling is 1024 switcher periods.
6. A series of measurements of capacitor voltages and
charger currents are made. From these measurements,
and the previous measurements, the ESR is calculated
and stored in meas_esr.
7. The capacitors will be charged to at least 1.25 • cap_
delta_v_setting above their initial voltage (as measured
at step 1).
If the capacitor voltage reaches the maximum charge
voltage (VCAPFB = 1.2V), then the test will stop try-
ing to charge and continue without fully charging. The
test may fail later due to this. If the charger is unable
to reach 1.25•cap_delta_v_setting above the initial
LTC3351
22
Rev. A
For more information www.analog.com
OPERATION
voltage with capfb less than 1.2V, it will continue trying
to charge indefinitely. This may occur if the charger is
limited by the input voltage and maximum duty cycle
of the buck charger. This may also occur if there is no
charge current available due to system load exceed-
ing the input current limit. If either of these conditions
occurs, the test will remain in this condition indefinitely.
8. The charger is temporarily disabled. The mon_cap_
meas_active bit becomes high, the mon_esr_meas_
active bit becomes low and the ITST current is enabled.
After a time set by cap_i_on_settling, a series of volt-
age measurements is made.
9. The capacitor stack is discharged a fixed voltage (set by
cap_delta_v_setting) from the voltage measured in the
previous step using the ITST current (1.2V/RTST, up to
60mA or 300mW). This voltage is measured using the
CAP1-4 pins.
10. The time required to discharge by this fixed voltage
is measured. It is then scaled for cap_delta_v_setting
and stored as meas_cap.
11. The charger stays off and the ITST current stays on
until the stack voltage returns to the voltage set by
vcapfb_dac.
12. The charger is turned back on and the ITST current
is turned off. The mon_meas_active bit goes low.
Figure4 shows this sequence graphically.
This measurement is only initiated when the ctl_start_
cap_esr_meas bit is set. The results of the measurement
can be checked against limits and issue a SMBALERT if
limits are exceeded, see the Limit Checking and Alarms
section of this data sheet.
The measurement of Capacitance and ESR can fail if
power fails during the test or if the capacitor stack is
discharged below the CAPGD threshold. The test will
also fail if ctl_stop_cap_esr_meas is set. If it does fail,
mon_meas_failed will be set.
Monitor Status Register
The LTC3351 has a monitor status register (monitor_
status_reg) containing status bits to indicate the state
of the capacitance and ESR monitoring system. These
bits are set and cleared by the capacitor monitor upon
certain events during a capacitor and ESR measurement,
as described in the ESR and Capacitance Measurement
section.
There is a corresponding monitor status mask register
(monitor_status_mask_reg). Writing a one to any of
these bits will cause the SMBALERT pin to pull low when
the corresponding bit in monitor_status_reg has a ris-
ing edge. This allows reduced polling of the LTC3351
when waiting for a capacitance or ESR measurement to
complete.
Details of monitor_status_reg and monitor_status_
mask_reg can be found in the Register Map section of
this datasheet.
EXTRAPOLATED
MEASUREMENT
VCAP
ICAP
esr_m1, esr_m2
esr_m0
esr_m3
REAL
VOLTAGE
IDEAL
VOLTAGE
1.25 • cap_delta_v_setting
vcapfb_dac VCAP SETTING
chrg_cv INDICATION
meas_capesr_i_off_settlingesr_i_on_settling cap_i_on_settling
ESR MEASUREMENT CAPACITANCE MEASUREMENT
cap_m0
(DIFFERENCE)
CAPACITANCE MEASUREMENT PRECHARGE CURRENT
(1/4 FULL SCALE)
ESR TEST CURRENT
(AUTOMATIC OR
esr_i_override)
SOFTSTART SOFTSTART
0
–ITST 3351 F04
cap_delta_v_setting
Figure4.
LTC3351
23
Rev. A
For more information www.analog.com
OPERATION
System Status Register
The sys_status register contains data about the state of
the charger, switcher and comparators. Details of this
register may be found in the Register Map section of this
data sheet.
Limit Checking and Alarms
The LTC3351 has a limit checking function that will check
each measured value against I2C/SMBus programmable
limits. This feature is optional and all of the limits are dis-
abled by default. The limit checking is designed to simplify
system monitoring, eliminating the need to continuously
poll the LTC3351 for measurement data.
If a measured parameter goes outside of the programmed
level of an enabled limit, the associated bit in the alarm_
reg register is set high and the SMBALERT pin is pulled
low. This informs the I
2
C/SMBus host that a limit has been
exceeded. The alarm_reg may then be read to determine
exactly which programmed limits have been exceeded.
A single ADC is shared between the 11 channels with
about 9ms between consecutive measurements of the
same channel. In a transient condition, it is possible for
these parameters to exceed their programmed levels in
between consecutive ADC measurements without setting
the alarm.
Once the LTC3351 has responded to an SMBus ARA the
SMBALERT pin is released. The LTC3351 will not pull the
pin low again until another limit is exceeded. To reset a
limit that has been exceeded write a zero to the respec-
tive bit in the alarm_reg register. When writing alarm_reg,
zeros will clear their respective bits in the register, ones
will be ignored.
A number of the LTC3351’s registers are used for limit
checking. Individual limits are enabled or disabled in
alarm_mask_reg. Once an enabled alarm’s measured
value exceeds the programmed level for that alarm the
alarm is set. That alarm may only be cleared by writing a
zero to the appropriate bit of alarm_reg. All alarms that
have been set and have not yet been cleared may be read
in the alarm_reg.
All of the individual measured voltages have a correspond-
ing undervoltage (UV) and overvoltage (OV) alarm level.
All of the individual capacitor voltages are compared to
the same alarm levels, set in cap_ov_lvl and cap_uv_lvl.
The input current measurement has an overcurrent (OC)
alarm programmed in iin_oc_lvl. The charge current has
an undercurrent alarm programmed in ichg_uc_lvl.
Die Temperature Sensor
The LTC3351 has an integrated die temperature sensor
monitored by the ADC and digitized to meas_dtemp.
An alarm is configured on die temperature by setting
dtemp_cold_lvl and/or dtemp_hot_lvl and enabling their
respective alarms in alarm_mask_reg. To convert the
code in the meas_dtemp register to degrees Celsius use
the following:
TDIE (°C) = 0.0295 • meas_dtemp – 274°C
General Purpose Input
The general purpose input (GPI) pin is used to measure
an additional system parameter where the voltage on this
pin is digitized by the ADC. For high impedance inputs, an
internal buffer may be selected and used to drive the ADC.
This buffer is enabled by setting the ctl_gpi_buffer_en
bit in the ctl_reg register. With this buffer, the input range
is limited from 0V to 3.5V. If this buffer is not used, the
range is from 0V to 5V, however, the input stage of the
ADC will draw about 0.8µA per volt from this pin. The ADC
input is a switched capacitor amplifier running at about
2MHz, so this current draw will be at that frequency. The
pin current can be eliminated at the cost of reduced range
and increased offset by enabling the buffer.
Alarms are available for this pin voltage with levels pro-
grammed using gpi_uv_lvl and gpi_ov_lvl. These alarms
are enabled using the mask_alarm_gpi_uv and mask_
alarm_gpi_ov bits in alarm_mask_reg.
To monitor the temperature of the supercapacitor stack,
the GPI pin can be connected to a negative temperature
coefficient (NTC) thermistor. A low drift bias resistor is
required from INTVCC to GPI and a thermistor is required
from GPI to ground. Connect GPI to SGND if not used.
LTC3351
24
Rev. A
For more information www.analog.com
OPERATION
Figure5.
VIN
OV
UV
OUTFB
RETRYB
INTVCC
CAPSLCT0
CAP_SLCT1
VINGD
SCL
SDA
SMBALERT
CAPGD
VC
CAPFB
RT
GPI
VCC2P5
CSS
CTIMER
ITST
DRVCC
BGATE
BST
TGATE
SW
ICAP
VCAP
CFN
CFP
VCAPP5
OUTFET
CAPRTN
CAP1
CAP2
CAP3
CAP4
3351 F05
HS_GATE
SRC
ISNSP_HS
ISNSM
VOUT
ISNSP_CHG
LTC3351
INTERNAL DIODES
SUBSTRATE DIODES NOT SHOWN
Internal Diodes
The LTC3351 has numerous internal diodes as part of its
circuits and ESD protection structures. In normal opera-
tion, these diodes are reverse biased. Figure5 shows all
the diodes except the substrate diodes. These substrate
diodes have their anode connect to ground and their cath-
odes connect to every pin except SW.
LTC3351
25
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
Digital Configuration
Although the LTC3351 has extensive digital features,
none are mandatory for basic use. The shunt voltage
is programmed via vshunt, which has a default value of
2.7V. The capacitor voltage feedback reference defaults
to 1.0125V (VCAPFB_DEF) and is set using vcapfb_dac. If
these values are acceptable, no software is required for
basic use.
All other digital features are optional, most for system
monitoring. The ADC automatically runs and stores con-
versions to registers (e.g., meas_vcap). Capacitance and
ESR measurements only run if requested. Each measured
parameter has programmable limits (e.g., vcap_uv_lvl and
vcap_ov_lvl) which may trigger an alarm and SMBALERT
when enabled. All alarms are disabled by default.
Capacitor Configuration
The LTC3351 is used with one to four supercapacitors. If
fewer than four capacitors are used, the capacitors must
be populated from CAPRTN to CAP4, and the unused CAP
pins must be tied to the highest used CAP pin. For exam-
ple, if three capacitors are used, tie CAP4 to CAP3. If only
two capacitors are used, tie both CAP4 and CAP3 to CAP2.
The number of capacitors used must be programmed on
the CAP_SLCT0 and CAP_SLCT1 pins by tying the pins
to VCC2P5 for a one and ground for a zero as shown in
Table1. The value programmed on these pins is read back
from num_caps via I2C/SMBus.
Table1.
Number of
Capacitors
num_caps
register CAP_SLCT1 CAP_SLCT0
1000
2101
3210
4311
Capacitor Shunt Regulator Programming
VSHUNT is programmed via the vshunt register and defaults
to 2.7V at initial power-up. VSHUNT serves to limit the volt-
age on any individual capacitor by turning on a shunt
around that capacitor as the voltage approaches VSHUNT.
CAPRTN, CAP1, CAP2, CAP3 and CAP4 are connected
to the supercapacitors through resistors which serve
as ballasts for the internal shunts. The shunt current is
approximately VSHUNT divided by twice the shunt resis-
tance value. For a VSHUNT of 2.7V, 2.7Ω resistors should
be used for 500mA of shunt current. If the shunts are dis-
abled, the shunt resistors must be populated with 100Ω.
Since the shunt current is less than what the switcher
can supply, the on-chip logic will automatically reduce
the charging current to allow the shunt to protect the
capacitor. This greatly reduces the charge rate once any
shunt is activated. For this reason, program V
SHUNT
as
high as possible to reduce the likelihood of it activating
during a charge cycle. Ideally, VSHUNT is set high enough
so that any likely capacitor mismatches would not cause
the shunts to turn on. This keeps the charger operating
at the highest possible charge current and reduces the
charge time. If the shunts never turn on, the charge cycle
completes quickly and the balancers eventually equalize
the voltage on the capacitors. The shunt setting may also
be used to discharge the capacitors for testing, storage
or other purposes.
Simulated Power Failure
The LTC3351 has the ability to simulate a power fail-
ure by setting ctl_hotswap_disable. This causes the hot
swap controller to disconnect VOUT from VIN and indicate
power has failed exactly as if it would had power actu-
ally failed. In this configuration all power consumption
downstream will be supplied by the supercapacitors
either through the ideal diode or the boost converter.
If, during this test, the stored energy is exhausted, then
VOUT will collapse, just as in a real power failure. At
the end of the simulated failure test, the ctl_hotswap_
disable bit must be cleared to allow the hot swap to
reconnect V
IN
to V
OUT
. The min_vout_hs_disable register
may be used to automatically clear ctl_hotswap_disable
if VOUT falls below the programmed voltage. Clearing
the ctl_hotswap_disable does not force the hot swap to
reconnect, it only allows it to reconnect if its usual condi-
tions are met, mainly that OV, UV and RETRYB voltages
are correct. If the hot swap is re-enabled while there is
system load current, it is considered a hot reconnect
and is discussed in the Hot Reconnects section of this
datasheet.
LTC3351
26
Rev. A
For more information www.analog.com
Hot Swap Component Selection
The hot swap controller will servo the HS_GATE pin to
regulate the voltage across the sense resistor(s) between
ISNSP_HS and ISNSM to be, at most, 48mV (VILIM(TH))
. This current limit is folded back as the voltage between
VIN and VOUT increases to 12V, at which point the regula-
tion voltage drops to 12mV and no further.
The CSS capacitor is used both to set an input qualifica-
tion delay (debounce) and to limit the VOUT dV/dt rate to
limit the inrush current.
dVOUT/dt = 48µA/CSS
tDELAY =1.2V •CSS
1µA
The primary concern when selecting a CSS capacitor
value is to select a value large enough to slow the VOUT
rise rate such that the input current stays below the mini-
mum hot swap current limit due to foldback. The following
equations are for input voltages above 10V and assume
a 12mV minimum current limit voltage. The minimum
CSS capacitor could be reduced further for lower voltage
inputs due to the minimum current limit voltage being
higher due to less foldback. The following equations
assume any VOUT load remain off until after the hot swap
completes, if loads are present on VOUT the CSS capaci-
tor must be further increased to set a VOUT rise rate such
that the dV/dt•COUT current and the load current do not
exceed the folded back current limit at any point.
The maximum dV/dt of the output without reaching cur-
rent limit is
dVOUT
dt =12mV
R
SNS
•C
OUT
Minimum CSS =48µA
12mV •RSNS •COUT
=4mmho •R
SNS
•C
OUT
The CSS capacitance may be increased to any value to
achieve a longer delay, however it must be larger than
the minimum CSS computed above to avoid current limit
and tripping the circuit breaker.
The switcher and hot swap controller both share the
negative terminal for their current sense amplifiers. The
switcher reduces charger current so that there is at most
32mV between ISNSP_CHG and ISNSM and the hot swap
controller will limit the input current to at most 48mV
between ISNSP_HS and ISNSM. This allows a single
sense resistor to be used in many applications, result-
ing in a hot swap circuit breaker that is 50% higher than
the switcher’s input current limit. Any two values may be
selected by using two current sense resistors, see the
Input Sense Resistors Selection section of this data sheet
for more information.
Setting Switcher Input and Charge Currents
The maximum switcher input current is determined by the
resistance across the ISNSP_CHG and ISNSM pins, typi-
cally RSNSI. The maximum charge current is determined
by the value of the sense resistor, RSNSC, connected in
series with the inductor. The input and charge current
loops servo the voltage across their respective sense
resistor to 32mV. Therefore, the maximum input and
charge currents are:
IIN(MAX) =32mV
RSNSI
ICHG(MAX) =32mV
R
SNSC
The peak inductor current limit for both buck and boost
modes, IPEAK, is 80% higher than the maximum charge
current and is equal to:
IPEAK =58mV
R
SNSC
This current limit is active in both charging and backup
modes. In backup mode, it is the only control limitation
on inductor and output current.
Low Current Charging and High Current Backup
The LTC3351 accommodates applications requiring low
charge currents and high backup currents. In these appli-
cations, program the desired charge current using RSNSI.
The higher current needed during backup is set using
APPLICATIONS INFORMATION
LTC3351
27
Rev. A
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R
SNSC
. The input current limit will override the charge cur-
rent limit when the supercapacitors are charging while the
charge current limit provides sufficient current capability
for backup operation.
The charge current will be limited to ICHG(MAX) at low
VCAP (i.e., low duty cycles). As VCAP rises, the switch-
ing controller’s input current will increase until it reaches
IIN(MAX). The input current will be maintained at IIN(MAX)
and the charge current will decrease as V
CAP
rises further.
Some applications may want to use only a portion of the
input current limit to charge the supercapacitors. Two
input current sense resistors placed in series can be used
to accomplish this as shown in Figure6. ISNSP_CHG is
kelvin connected to the positive terminal of RSNSI1 and
ISNSM is kelvin connected to the negative terminal of
RSNSI2. The load current is pulled through RSNSI1 while
the input current to the charger is pulled through RSNSI1
and RSNSI2. The input current limit is:
32mV = RSNSI1 • ILOAD + (RSNSI1 + RSNSI2) • IINCHG
For example, suppose that only 2A of input current is
desired to charge the supercapacitors but the system load
and charger combined can pull a total of up to 4A from
the supply. Setting RSNSI1 = RSNSI2 = 8mΩ will set a 4A
current limit for the load and charger, while setting a 2A
limit for the charger. With no system load, the charger can
pull up to 2A of input current. As the load pulls 0A to 4A
of current, the charger’s input will drop from 2A to 0A.
The following equation can be used to determine charging
input current as a function of system load current:
IINCHG =32mV
R
SNSI1
+R
SNSI2
–RSNSI1
R
SNSI1
+R
SNSI2
•ILOAD
The contact resistance of the negative terminal of RSNSI1
and the positive terminal of RSNSI2 as well as the resis-
tance of the trace connecting them will contribute error to
the input current limit. To minimize the error, place both
input current sense resistors close together with a large
PCB pad area between them as the system load current is
pulled from the trace connecting the two sense resistors.
Note that the backup current will flow through
RSNSI2. Size the RSNSI2 resistor package to handle the
powerdissipation.
Figure6.
V
IN
V
IN
HS_GATE
ISNSP_CHG
R
SNSI1
R
SNSI2
L
TC3351
ISNSM
I
INCHG
I
LOAD
V
OUT
(TO SYSTEM)
TG
A
TE
BG
A
TE
3351 F06
Input Sense Resistors Selection
Any combination of hot swap current limit and switch-
ing charger input current limit can be achieved with two
resistors. In Figure7 below, three resistors are shown,
however, in all configurations at least one will be replaced
with a short.
Figure7.
LTC3351
ISNSP_CHG
R2
R1
R3
ISNSM
VOUT
(TO SYSTEM)
IINCHG
(TO CHARGER)
3351 F07
ISNSP_HS
IHS
If the desired hot swap current limit is 1.5 time the char-
ger input current limit, then only R2 is needed and R1 and
R3 are replaced with shorts.
R2 = 48mV/IHS
If the desired hot swap current limit is greater than 1.5
times the charger input current limit, then R1 is replaced
with a short. This will typically be the case when a higher
backup current than charge current is needed.
R2 = 48mV/IHS
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R3 = 32mV/IINCHG – R2
In this configuration, R3 adds to the output impedance of
the boost. Alternatively, the resistors may be reconfigured
as shown in Figure8.
Figure8.
LTC3351
ISNSP_HS
R2
R3
ISNSM
VOUT
IINCHG
3351 F08
ISNSP_CHG
If the desired charger input current limit is more than 2/3
of the hot swap input current limit R3 is replaced with a
short.
R2 = 32mV/IINCHG
R1 = 48mV/IHS – R2
Note that the circuit breaker timer (the CTIMER pin) may
run as low as 2% below the current limit, setting the char-
ger’s input current limit too close to the hot swap current
limit will trip the circuit breaker. Operation with the char-
ger’s input current set close to the hot swap current limit
requires careful attention to the LTC3351’s tolerance for
both VILIM(HS) and VSNSI, the tolerance of both current
sense resistors, the layout, the worst case switching char-
ger’s input current ripple, and how quickly the switching
charger can reduce its current due to the fastest increase
in downstream VOUT current.
Setting VCAP Voltage
The LTC3351 VCAP voltage is set by an external feedback
resistor divider, as shown in Figure9. The regulated out-
put voltage is determined by:
VCAP =1+RFBC1
RFBC2
⎛
⎝
⎜
⎞
⎠
⎟CAPFBREF
where CAPFBREF is the output of the VCAP DAC, pro-
grammed via vcapfb_dac. Take great care to route the
CAPFB line away from noise sources, such as the SW
line, BST, TGATE or BGATE.
Figure9.
LTC3351
CAPFB
V
CAP
R
FBC1
R
FBC2
3351 F9
Setting VOUT Voltage in Backup Mode
The output voltage for the switching controller in step-
up mode is set by an external feedback resistor divider,
as shown in Figure10. The regulated output voltage is
determined by:
VOUT =1+RFBO1
RFBO2
⎛
⎝
⎜
⎞
⎠
⎟1.2V
Take great care to route the OUTFB line away from noise
sources, such as the SW line, BST or TGATE.
VC
OUTFB
RC_INT
LTC3351
V
REF
R
C
(OPT)
R
FBO1
R
FBO2
R
FO
(OPT)
C
FO
(OPT)
C
FBO1
V
OUT
C
C
+
–
3351 F10
Figure10. VOUT Voltage Divider and Compensation Network
RC_INT in Figure10 is 1kΩ in buck mode and 2kΩ in
boost mode.
Compensation
The input current, charge current, V
CAP
voltage, and V
OUT
voltage loops all require a 1nF to 10nF capacitor from the
VC node to ground. When using the output ideal diode and
backing up to low voltages (<8V), use 8.2nF to 10nF on
VC. When not using the output ideal diode, 4.7nF to 10nF
on VC is recommended. For very high backup voltages
(>15V), 1nF to 4.7nF is recommended.
In addition to the VC node capacitor, the V
OUT
voltage
loop requires a phase-lead capacitor, CFBO1, for stabil-
ity and improved transient response during input power
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failure (Figure10). The product of the top divider resistor
and the phase-lead capacitor is used to create a zero at
approximately 2kHz:
RFBO1 • CFBO1≈1
2π2kHz
( )
Choose RFBO1, such that CFBO1 ≥ 100pF, to minimize the
effects of parasitic pin capacitance. Because the phase-
lead capacitor introduces a larger ripple at the input of the
V
OUT
transconductance amplifier, an additional R
C
low-
pass filter from the VOUT divider to the OUTFB pin may be
needed to eliminate voltage ripple spikes. The filter time
constant should be located at the switching frequency of
the switching controller:
RFO • CFO =1
2πf
SW
with CFO > 10pF to minimize the effects of parasitic pin
capacitance. For backup applications, where the VOUT
regulation voltage is low (~5V to 6V), an additional 1k to
3k resistor, RC, in series with the VC capacitor improves
stability and transient response.
Minimum VCAP Voltage in Backup Mode
In backup mode, power is provided to the output from
the supercapacitors either through the output ideal diode
or the switching controller operating in step-up mode.
The output ideal diode provides a low loss power path
from the supercapacitors to VOUT. The minimum inter-
nal (open-circuit) supercapacitor voltage will be equal to
the minimum VOUT necessary for the system to operate
plus the voltage drops due to the output ideal diode and
equivalent series resistance, RSC, of each supercapacitor
in the stack.
Example: System needs 5V to run and draws 1A during
backup. There are four supercapacitors in the stack, each
with an R
SC
of 45mΩ. The output ideal diode forward
regulation voltage is 30mV (OUTFET RDS(ON) < 30mΩ).
The minimum open-circuit supercapacitor voltage is:
VCAP(MIN) = 5V + 0.030V + (1A • 4 • 45mΩ) = 5.21V
Using the switching controller in step-up mode allows the
supercapacitors to be discharged to a voltage much lower
than the minimum VOUT needed to run the system. The
amount of power that the supercapacitor stack can deliver
at its minimum internal (open-circuit) voltage should be
greater than what is needed to power the output and the
step-up converter.
According to the maximum power transfer rule:
PCAP(MIN) =VCAP(MIN)2
4 •n •R
SC
>PBACKUP
η
In the equation above η is the efficiency of the switching
controller in step-up mode and n is the number of super-
capacitors in the stack.
Example: System needs 5V to run and draws 1A dur-
ing backup. There are four supercapacitors in the stack
(n
=
4), each with an RSC of 45mΩ. The converter effi-
ciency is 90%. The minimum open-circuit supercapacitor
voltage is:
VCAP(MIN) =4 • 4 • 45mΩ• 5V • 1A
0.9 =2.0V
In this case, the voltage seen at the terminals of the
capacitor stack is half this voltage, or 1V, according to
the maximum power transfer rule.
Note the minimum VCAP voltage can also be limited
by the peak inductor current limit (180% of maximum
charge current) and the maximum duty cycle in step-up
mode(~90%).
Optimizing Supercapacitor Energy Storage Capacity
In most systems the supercapacitors will provide backup
power to one or more DC/DC converters. A DC/DC con-
verter presents a constant power load to the superca-
pacitor stack. When the supercapacitors are near their
maximum voltage, the loads will draw little current. As
the capacitors discharge, the current drawn from super-
capacitors will increase to maintain constant power to the
load. The amount of energy required in back up mode is
the product of this constant backup power, PBACKUP, and
the backup time, tBACKUP.
LTC3351
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The energy stored in a stack of n supercapacitors available
for backup is:
1
2
nCSC CELL(MAX)
2
V–CELL(MIN)
2
V
( )
where CSC, VCELL(MAX) and VCELL(MIN) are the capacitance,
maximum voltage and minimum voltage of a single capac
-
itor in the stack, respectively. The maximum voltage on
the stack is VCAP(MAX) = n • VCELL(MAX). The minimum
voltage on the stack is VCAP(MIN) = n • VCELL(MIN).
Some of this energy will be dissipated as conduction loss
in the ESR of the supercapacitor stack. A higher backup
power requirement leads to a higher conduction loss for
a given stack ESR.
The amount of capacitance needed is found by solving
the following equation for CSC:
where:
γMAX =1+1– 4RSC •PBACKUP
nCELL(MAX)
2
Vand,
γMin =1+1– 4RSC •PBACKUP
nCELL(MIN)
2
V
RSC is the equivalent series resistance (ESR) of a single
supercapacitor in the stack. Note that the maximum power
transfer rule limits the minimum cell voltage to:
VCELL(MIN) =VCAP(MIN)
n
≥4RSC •PBACKUP
n
A calculator for this is available on the LTC3350 website.
PBACKUP • tBACKUP =1
4nCSC MAX •CELL(MAX)
2
V–MIN •CELL(MIN)
2
V–4RSC •PBACKUP
nln MAX • VCELL(MAX)
MIN • VCELL(MIN)
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To minimize the size of the capacitance for a given amount
of backup energy, increase the maximum voltage on the
stack, VCELL(MAX). However, the voltage is limited to a
maximum of 2.7V and higher than this may lead to an
unacceptably low capacitor lifetime.
An alternative option is to keep VCELL(MAX) at a voltage
that leads to reasonably long lifetime and increase the
capacitor utilization ratio of the supercapacitor stack. The
capacitor utilization ratio, αB, can be defined as:
αB=CELL(MAX)
2
V–CELL(MIN)
2
V
CELL(MAX)
2
V
If the synchronous controller is used in step-up mode,
then the supercapacitors can be run down to a voltage
set by the maximum power transfer rule to maximize the
utilization ratio. The minimum voltage in this case is:
VCELL(MIN) =4RSC •PBACKUP
nη
where η is the efficiency of the boost converter (~90% to
96%). For the backup equation, γ
MAX
and γ
MIN
, substitute
PBACKUP/η for PBACKUP. In this case the energy needed for
backup is governed by the following equation:
P
BACKUP tBACKUP
1
2nCSC •CELL(MAX)
2
V•
B+B
2–1– B
2ln 1+B
1– B
Once a capacitance is found using the above equation the
maximum ESR allowed needs to be checked:
RSC ≤η1– αB
( )
nCELL(MAX)
2
V
4P
BACKUP
Capacitor Selection Procedure
1. Determine backup requirements P
BACKUP
and t
BACKUP
.
2. Determine maximum cell voltage that provides accept-
able capacitor lifetime.
3. Choose number of capacitors in the stack.
4. Choose a desired utilization ratio, αB, for the superca-
pacitor (e.g., 80%).
5. Solve for capacitance, CSC:
CSC
2P
BACKUP
• t
BACKUP
nCELL(MAX)
2
V•
B+B
2–1– B
2ln 1+B
( )
1– B
–
1
6. Find supercapacitor with sufficient capacitance C
SC
and
minimum RSC:
RSC ≤η1– αB
( )
nCELL(MAX)
2
V
4P
BACKUP
7. If a suitable capacitor is not available, iterate by choos-
ing more capacitance, a higher cell voltage, more
capacitors in the stack and/or a lower utilization ratio.
8. Make sure to take into account the lifetime degrada-
tion of ESR and capacitance, as well as the maximum
discharge current rating of the supercapacitor. A list of
supercapacitor suppliers is provided in Table2.
Table2. Supercapacitor Suppliers
AVX www.avx.com
Bussmann www.cooperbussmann.com
CAP-XX www.cap-xx.com
Illinois Capacitor www.illcap.com
Kemet Corp. www.kemet.com
Maxwell www.maxwell.com
Murata www.murata.com
NESS CAP www.nesscap.com
Tecate Group www.tecategroup.com
LTC3351
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Inductor Selection
The switching frequency and inductor selection are
interrelated. Higher switching frequencies allow the use
of smaller inductor and capacitor values, but generally
results in lower efficiency due to MOSFET switching and
gate charge losses. In addition, the effect of inductor value
on ripple current must also be considered. The inductor
ripple current decreases with higher inductance or higher
frequency and increases with higher V
IN
. Accepting larger
values of ripple current allows the use of low inductances
but results in higher output voltage ripple and greater
core losses.
For the LTC3351, the best overall performance will be
attained if the inductor is chosen to be:
L=VIN(MAX)
ICHG(MAX) • fSW
for VIN(MAX) ≤ 2VCAP and:
L=1– VCAP
VIN(MAX)
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
VCAP
0.25 •ICHG(MAX) • fSW
for V
IN(MAX)
≥ 2VCAP, where V
CAP
is the final supercapaci-
tor stack voltage, VIN(MAX) is the maximum input voltage,
ICHG(MAX) is the maximum regulated charge current, and
f
SW
is the switching frequency. Using these equations, the
inductor ripple will be at most 25% of ICHG(MAX).
Using the above equation, the inductor may be too large to
provide a fast enough transient response to hold up VOUT
when input power goes away. This occurs in cases where
the maximum VIN is high (e.g. 25V) and the backup volt-
age low (e.g. 6V). In these situations it would be best to
choose an inductor that is smaller resulting in maximum
peak-to-peak ripple as high as 40% of ICHG(MAX).
Once the value for L is known, the type of inductor core
is selected. Ferrite cores are recommended for their very
low core loss. Selection criteria should concentrate on
minimizing copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current
is exceeded. This causes an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate. The saturation current
for the inductor should be at least 80% higher than the
maximum regulated current, ICHG(MAX). A list of inductor
suppliers is provided in Table3.
Table3. Inductor Vendors
VENDOR URL
Coilcraft www.coilcraft.com
Murata www.murata.com
Sumida www.sumida.com
TDK www.tdk.com
Toko www.toko.com
Vishay www.vishay.com
Würth Electronic www.we-online.com
COUT and CCAP Capacitance
VOUT serves as the input to the synchronous controller in
step-down mode and as the output in step-up (backup)
mode. If step-up mode is used, place 100µF of bulk (alu-
minum electrolytic, OS-CON, POSCAP) capacitance for
every 2A of backup current desired. For 5V system appli-
cations, 100µF per 1A of backup current is recommended.
In addition, a certain amount of high frequency bypass
capacitance is needed to minimize voltage ripple. The volt-
age ripple in step-up mode is:
V
OUT
=
1– VCAP
V
OUT
1
C
OUT
• f
SW
+VOUT
V
CAP
•RESR IOUT(BACKUP)
Maximum ripple occurs at the lowest VCAP that can supply
IOUT(BACKUP). Multilayer ceramics are recommended for
high frequency filtering.
If step-up mode is unused, then the specification for COUT
will be determined by the desired ripple voltage in step-
down mode:
V
OUT
=
VCAP
V
OUT
1– VCAP
V
OUT
ICHG(MAX)
C
OUT
• f
SW
+ICHG(MAX) •RESR
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In continuous conduction mode, the source current of the
top MOSFET is a square wave of duty cycle VCAP/VOUT.
To prevent large voltage transients, a low ESR capacitor
sized for the maximum RMS current must be used. The
maximum RMS capacitor current is given by:
IRMS ≅ICHG(MAX)
VCAP
VOUT
VOUT
VCAP
– 1
This formula has a maximum at VOUT = 2VCAP, where IRMS
= ICHG(MAX)/2. This simple worst-case condition is com-
monly used for design because even significant deviations
do not offer much relief.
Medium voltage (20V to 35V) ceramic, tantalum, OS-CON
and switcher-rated electrolytic capacitors can be used as
input capacitors. Sanyo OS-CON SVP, SVPD series, Sanyo
POSCAP TQC series, or aluminum electrolytic capacitors
from Panasonic WA series or Cornell Dubilier SPV series
in parallel with a couple of high performance ceramic
capacitors can be used as an effective means of achiev-
ing low ESR and high bulk capacitance.
V
CAP
serves as the input to the switching controller in
step-up mode and as the output in step-down mode. The
purpose of the VCAP capacitor is to filter the inductor cur-
rent ripple. The VCAP ripple (ΔVCAP) is approximated by:
ΔVCAP ≈ ΔIPP
1
8CCAP • fSW
+RESR
⎛
⎝
⎜
⎞
⎠
⎟
where fSW is the switching frequency, CCAP is the capaci-
tance on VCAP and ΔIPP is the ripple current in the induc-
tor. The output ripple is highest at maximum input voltage
since ΔIPP increases with input voltage.
Because supercapacitors have low series resistance, it is
important that CCAP be sized properly so that the bulk of
the inductor current ripple flows through the filter capaci-
tor and not the supercapacitor. It is recommended that:
1
8CCAP • fSW
+RESR
⎛
⎝
⎜
⎞
⎠
⎟≤n •RSC
5
where n is the number of supercapacitors in the stack and
RSC is the ESR of each supercapacitor. The capacitance
on VCAP can be a combination of bulk and high frequency
capacitors. Aluminum electrolytic, OS-CON and POSCAP
capacitors are suitable for bulk capacitance while mul-
tilayer ceramics are recommended for high frequency
filtering.
Power MOSFET Selection
Two external power MOSFETs are selected for the
LTC3351’s synchronous controller: one N-channel
MOSFET for the top switch and one N-channel MOSFET
for the bottom switch. The selection criteria of the exter-
nal N-channel power MOSFETs include maximum drain-
source voltage (VDSS), threshold voltage, on-resistance
(RDS(ON)), reverse transfer capacitance (CRSS), total gate
charge (QG), and maximum continuous drain current.
Select VDSS of both MOSFETs to be higher than the maxi-
mum input supply voltage (including transient). The peak-
to-peak drive levels are set by the DRVCC voltage. Logic-
level threshold MOSFETs should be used because DRVCC
is powered from either INTVCC (5V) or an external LDO
whose output voltage must be less than 5.5V.
MOSFET power losses are determined by RDS(ON), CRSS
and QG. The conduction loss at maximum charge current
for the top and bottom MOSFET switches are:
PCOND(TOP) =VCAP
VOUT
ICHG(MAX)2•RDS(ON) 1+ δΔT
( )
PCOND(BOT) =1– VCAP
VOUT
⎛
⎝
⎜
⎞
⎠
⎟ICHG(MAX)2•RDS(ON) 1+ δΔT
( )
The term (1+ δΔT) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
Both MOSFET switches have conduction loss. However,
transition loss occurs only in the top MOSFET in step-
down mode and only in the bottom MOSFET in step-up
mode. These losses are proportional to VOUT2 and can
be considerably large in high voltage applications (VOUT
> 20V). The maximum transition loss is:
PTRAN ≈k
2
VOUT2•ICHG(MAX) •CRSS • fSW
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where k is related to the drive current during the Miller
plateau and is approximately equal to one.
The synchronous controller can operate in both step-
down and step-up mode with different voltages on VOUT
in each mode. If VOUT is 12V in step-down mode (input
power available) and 10V in step-up mode (backup mode)
then both MOSFETs can be sized to minimize conduction
loss. If VOUT can be as high as 25V while charging and
VOUT is held to 6V in backup mode, then the MOSFETs
should be sized to minimize losses during backup mode.
This may lead to choosing a high side MOSFET with
significant transition loss which may be tolerable when
input power is available so long as thermal issues do
not become a limiting factor. The bottom MOSFET can be
chosen to minimize conduction loss. If step-up mode is
unused, then choosing a high side MOSFET that that has
a higher RDS(ON) device and lower CRSS would minimize
overall losses.
Another power loss related to switching MOSFET selec-
tion is the power lost to driving the gates. The total gate
charge, QG, must be charged and discharged each switch-
ing cycle. The power is lost to the internal LDO and gate
drivers within the LTC3351. The power lost due to charg-
ing the gates is:
PG ≈ (QGTOP + QGBOT) • fSW • VOUT
where Q
GTOP
is the top MOSFET gate charge and Q
GBOT
is
the bottom MOSFET gate charge. Whenever possible, uti-
lize MOSFET switches that minimize the total gate charge
to limit the internal power dissipation of the LTC3351.
Schottky Diode Selection
Optional Schottky diodes can be placed in parallel with the
top and bottom MOSFET switches. These diodes clamp
SW during the non-overlap times between conduction of
the top and bottom MOSFET switches. This prevents the
body diodes of the MOSFET switches from turning on,
storing charge during the non-overlap time and requiring
a reverse recovery period that could cost as much as 3%
in efficiency at high VIN. One or both diodes can be omit-
ted if the efficiency loss can be tolerated. Rate the diode
for about one-third to one-fifth of the full load current
since it is on for only a fraction of the duty cycle. Larger
diodes result in additional switching losses due to their
larger junction capacitance. In order for the diodes to be
effective, the inductance between them and the top and
bottom MOSFETs must be as small as possible. Place
these components next to each other on the same layer
of the PC board.
Top MOSFET Driver Supply (CB, DB)
An external bootstrap capacitor, CB, connected to the BST
pin supplies the gate drive voltage for the top MOSFET.
Capacitor CB, in Figure11, is charged though an external
diode, D
B
, from DRV
CC
when the SW pin is low. The value
of the bootstrap capacitor, CB, needs to be 20 times that
of the total input capacitance of the top MOSFET.
The bottom MOSFET, MN2 in Figure 11, turning on
ensures that the SW pin goes low. If the bottom MOSFET
is on for less than 50µS for eight consecutive switching
cycles, the bottom MOSFET will turn on for 100nS to
250nS at the end of the eighth switching cycle to refresh
the voltage on CB.
With the top MOSFET on, the BST voltage is above the
system supply rail:
VBST = VOUT + VDRVCC
The reverse break down of the external diode, DB, must
be greater than VOUT(MAX) + VDRVCC(MAX).
The step-up converter briefly runs non-synchronously
when used with the output ideal diode. During this time
the BST to SW voltage can pump up to voltages exceeding
5.5V if DB is a Schottky diode. Fast switching PN diodes
are recommended due to their low leakage and junction
capacitance. A Schottky diode can be used if the step-up
converter runs synchronous throughout backup mode.
Figure11.
BST
SW
>2.2µF
3351 F11
D
B
DRV
CC
INTV
CC
LTC3351
C
B
0.1µF
1µF
OPT
APPLICATIONS INFORMATION
LTC3351
35
Rev. A
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INTVCC/DRVCC and IC Power Dissipation
The LTC3351 features a low dropout linear regulator
(LDO) that supplies power to INTVCC from the VOUT sup-
ply. INTVCC powers the gate drivers (when connected to
DRV
CC
) and much of the LTC3351’s internal circuitry. The
LDO regulates the voltage at the INTVCC pin to 5V. The
LDO can supply a maximum current of 50mA and must
be bypassed to ground with a minimum of 1μF when not
connected to DRVCC. DRVCC should have at least a 2.2μF
ceramic or low ESR electrolytic capacitor. No matter what
type of bulk capacitor is used on DRV
CC
, an additional
0.1μF ceramic capacitor placed directly adjacent to the
DRV
CC
pin is highly recommended. Good bypassing is
needed to supply the high transient currents required by
the MOSFET gate drivers.
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC3351 to be
exceeded. The INTV
CC
current, which is dominated by the
gate charge current, is supplied by the 5V LDO.
Power dissipation for the IC in this case is highest and is
approximately equal to (VOUT) • (IQ + IG), where IQ is the
non-switching quiescent current of ~4mA and IG is gate
charge current. The junction temperature is estimated
by using the equations given in Note 2 of the Electrical
Characteristics. For example, the IG supplied by the
INTVCC LDO is limited to less than 42mA from a 35V
supply in the QFN package at a 70°C ambient temperature:
TJ = 70°C + (35V)(4mA + 42mA)(36.4°C/W) = 125°C
To prevent the maximum junction temperature from being
exceeded, the INTV
CC
LDO current must be checked while
operating in continuous conduction mode at maximum
VOUT.
The power dissipation in the IC is drastically reduced if
DRVCC is powered from an external LDO. In this case the
power dissipation in the IC is equal to power dissipation
due to IQ and the power dissipated in the gate drivers,
(V
DRVCC)
• (I
G
). Assuming the external DRV
CC
LDO output
is 5V and is supplying 42mA to the gate drivers, at 70°C
ambient the junction temperature rises to only 80.5°C:
TJ = 70°C + [(35V)(2.25mA)+(5V)(42mA)](36.4°C/W)
= 80.5°C
Power the external LDO from VOUT. It must be enabled
after the INTVCC LDO has powered up and its output must
be less than 5.5V. INTV
CC
should no longer be tied to
DRVCC.
Minimum On-Time Considerations
Minimum on-time, t
ON(MIN)
, is the smallest time dura-
tion that the LTC3351 is capable of turning on the top
MOSFET in step-down mode. It is determined by internal
timing delays and the gate charge required to turn on
the top MOSFET. The minimum on-time for the LTC3351
is approximately 85ns. Low duty cycle applications may
approach this minimum on-time limit and care should be
taken to ensure that:
tON(MIN) <VCAP
V
OUT
• f
SW
If the duty cycle falls below what can be accommodated
by the minimum on-time, the switching controller will
begin to skip cycles. The charge current and V
CAP
voltage
will continue to be regulated, but the ripple voltage and
current will increase.
Ideal Diode MOSFET Selection
An external N-channel MOSFET is required for the output
ideal diode. Important parameters for the selection of this
MOSFET is the maximum drain-source voltage, V
DSS
, gate
threshold voltage and on-resistance (RDS(ON)).
When the supercapacitors are at 0V, the input voltage is
applied across the output ideal diode MOSFET. Therefore,
the V
DSS
of the output ideal diode MOSFET must with-
stand the highest voltage on VIN.
The gate drive for the ideal diode is 5V. Use logic-level
threshold N-channel MOSFET.
As a general rule, select a MOSFET with a low enough
RDS(ON) to obtain the desired VDS while operating at full
load current. The LTC3351 will regulate the forward volt-
age drop across the output ideal diode MOSFET to 30mV
APPLICATIONS INFORMATION
LTC3351
36
Rev. A
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APPLICATIONS INFORMATION
if RDS(ON) is low enough. The required RDS(ON) can be
calculated by dividing 0.030V by the load current in amps.
Achieving forward regulation will minimize power loss
and heat dissipation, but it is not a necessity. If a forward
voltage drop of more than 30mV is acceptable, then a
smaller MOSFET can be used but must be sized compat-
ible with the higher power dissipation. Care should be
taken to ensure that the power dissipated is never allowed
to rise above the manufacturer’s recommended maximum
level.
During backup mode, the output ideal diode shuts off
when the voltage on OUTFB falls below 1.3V. For high
VOUT backup voltages (>8.4V), the output ideal diode will
shut off when VCAP is more than a diode drop (~700mV)
above the VOUT regulation point (i.e., OUTFB > 1.2V). The
body diode of the output ideal diode N-channel MOSFET
will carry the load current until VCAP drops to within a
diode drop of the VOUT regulation voltage at which point
the switching controller takes over. During this period
the power dissipation in the output ideal diode MOSFET
increases significantly. Diode conduction time is small
compared to the overall backup time but can be significant
when discharging very large supercapacitors (>600F).
Care should be taken to properly heat sink the MOSFET
to limit the temperature rise.
Hot Swap Input FET Selection
In addition to RDS(ON) requirements, the hot swap input
FET must be sized for safe operating area (SOA). This is
done by sizing for both the start-up characteristic of the
system and to handle a short circuit of the duration set by
CTIMER. Typically, the FET should be sized for the worst
case startup condition and CTIMER should be set such
that a short circuit will require less SOA than the startup
condition. Logic level gate FETs are required.
The foldback curve reduces the SOA requirement of the
FET. The LTC3351’s foldback curve reduces the effec-
tive current limit as the voltage across the FET (as mea-
sured from VIN to VOUT) increases. The current is linearly
reduced from 100% at 1V to about 20% at 11V, voltages
larger than 11V will remain at 20%.
Simplified SOA Requirement Calculation:
1. Determine the output slew rate (see page 26).
2. Using this slew rate and the output capacitance deter-
mine the inrush current.
3. Add any enabled downstream loads to this inrush cur-
rent to determine the input current.
4. Using the slew rate and maximum input voltage, deter-
mine the output capacitor charge time.
Using the output capacitor charging time, the input cur-
rent and the maximum input voltage, select a FET with an
appropriate SOA. The CTIMER capacitor value should be
set to not exceed the FETs SOA when the output is shorted
with maximum input voltage.
Hot Reconnects
Return of input power when operating in backup mode
must be considered. The RETRYB pin provides a mecha-
nism to prevent returning to input power based on either
the VOUT voltage or digital signal, typically indicating the
backup has completed. The RETRYB pin may also be
grounded causing the LTC3351 to attempt to reconnect
the system to the input once all other reconnect criteria
are met. If the RETRYB pin is grounded, and a handover
from backup operation back to VIN operation is required,
it is essential that the load line of the system remain below
the foldback curve of the hot swap controller. If the system
load exceeds the foldback curve of the hot swap control-
ler, the controller will be unable to support the load and
an over-current fault will occur. After the CTIMER cool
down time has passed, the cycle will repeat indefinitely
until the energy storage is depleted and the load shuts
down, returning the system to conditions resembling an
initial power-up. This may be prevented by keeping the
foldback curve above the systems load line. Boosting to
a voltage near V
IN
will allow the hot swap to start at a
high current point on the foldback curve and may allow
the hot swap controller to reconnect VIN without running
into current limit.
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37
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Alternate Hot Swap Controller Configuration
Typically, the CSS capacitor sets both the debounce time
and the maximum rise rate of VOUT. If the fixed relationship
between the debounce time and the maximum rise rate is not
satisfactory the hot swap controller has an alternate configu-
ration to decouple these two parameters, however this comes
at the expense of reduced current limit speed.
In this alternate configuration, the CSS capacitor is con-
nected from the CSS pin to ground. In this configuration,
the CSS capacitor will only function as a debounce timer.
The rise rate of the output is controlled by IHS_GATE(UP)
into the capacitance of the HS_GATE node. Adding a
capacitor from the HS_GATE pin to ground allows the
output rise rate to be programmed independently of all
other parameters. However, this capacitance represents
a large load that the current limit amplifier must drive,
resulting in a slower current limit. A 1kΩ resistor should
be placed in series with this capacitor. This resistor will
limit current into the HS_GATE when the HS_GATE pin is
pulled to ground due to a fault being detected.
Increased Capacitance Test Current
The LTC3351 can sink up to 60mA of capacitance test
current dissipating up to 300mW. This constant current
sink is capable of testing large capacitors, however the
test time may become unreasonably long. To increase the
test current, a simple circuit using a low Vt (<1.2VVGS)
NMOS and a resistor may be used. The gate of the NMOS
is connected to the ITST pin such that when the ITST
circuit is turned on the NMOS is also turned on. This
circuit allows much higher capacitance test current than
the LTC3351 alone.
Figure12.
VCAP
ITST
LTC3351
RTST
R
V
CAP
3351 F12
Increased Capacitance Test Current
When using this circuit, the test current will be the original
ITST circuit current plus an additional current due to the
capacitor stack voltage across the resistor. This requires
a modified equation for converting meas_cap to capaci-
tance. This equation is:
C=–56 •10
–9
•Rt•meas_cap
R•ln 1– ∆ VCAP
1.2V • R
RTST
+VCAP
Where R is the resistance in the added ITST circuit, VCAP is
the charge voltage at the beginning of the test and ΔVCAP
is the voltage set using the cap_delta_v_setting regis-
ter. R, RTST and Rt are in Ohms, C is in Farads, and VCAP
and ΔVCAP are in volts. The above equation is valid when
ctl_cap_scale is 1 (the small setting); if the large setting
is used, the above equation should be multiplied by 100.
Increased Shunt Current
The LTC3351 can shunt up to 500mA around an indi-
vidual cell that has reached VSHUNT as set by the vshunt
register. This limits the charge rate of the other capacitors
because the charge current is reduced to near the shunt
current while shunting to prevent each cap from exceed-
ing VSHUNT. To enable faster charging while shunting,
higher shunt current is needed.
Figure13.
CAP4
CAP3
CAP2
CAP1
CAPRTN
LTC3351
10Ω
R4
MN4
V
CAP
C4
10Ω
R3
MN3
C3
10Ω
R2
MN2
C2
10Ω
R1
MN1
C1
10Ω
3351 F13
Increased Shunt Current Circuit Addition
LTC3351
38
Rev. A
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Higher shunt current may be accommodated with an
external NMOS and resistor across each capacitor as
shown in Figure13. The shunt current will be V
SHUNT
divided by Rx (assuming the RDS(ON) of MNx is small
compared to Rx). The logic level NMOS must be selected
so that its VGS at the desired shunt current is less than one
half the V
SHUNT
voltage. When using this circuit the shunt
resistors should be increased to 10Ω to minimize the
drop across the LTC3351’s internal shunt FET and thus
maximize the VGS for MNx. Using 10Ω resistors will also
reduce the power dissipation allowing a smaller package
size compared to the typical application’s 2.7Ω. When
using 10Ω resistors the internal shunt FET will turn on the
external NMOS, however the internal balancer’s current
will not create enough voltage across the 10Ω resistors
to turn on the external NMOS. Additionally, increasing the
10Ω resistors to 500Ω will allow the internal balancers
to turn on the external FETs, thus also increasing balance
current.
Input Short Protection
The LTC3351’s input current sense amplifier, ISNSP_HS
to ISNSM and ISNSP_CHG to can have at most 0.3V
between them. This is not typically an issue since the
LTC3351 regulates input current to 48mV (hot swap cur-
rent limit) or 32mV (charger input current limit) using
these pins. The LTC3351 hot swap does not regulate
reverse input current. If the input voltage is rapidly
reduced (the input directly shorted to ground for instance)
large currents will flow from the VOUT capacitance to the
VIN short. Unless external protection is used, these large
currents can quickly produce many volts of drop across
the input sense resistor(s), overstressing the input cur-
rent sense pins. If the input is shorted after it has fallen
below the UV threshold, this is not an issue since the hot
swap FETs have already been turned off. However, if the
input supply can be shorted to ground while the LTC3351
is connected, the input protection circuit in Figure14 is
recommended. Also if the system load is so low that the
LTC3351 circuit can be disconnected from the input and
then shorted to ground before the input falls below UV,
then the same circuit is also recommended.
Figure14.
LTC3351
ISNSP_X
1Ω
ISNSM
VOUT
VIN
3351 F14
ISNSP_X
1Ω
1Ω
Input Short Protection Circuit
Since there are several possible configurations for the
input current sense resistors, not all possible protection
circuits are shown. To construct a circuit for another con-
figuration of input current sense resistors, there should
be one Schottky diode for each current sense amplifier
(ISNSP_HS-ISNSM and ISNSP_CHG-ISNSM). There
should be 1Ω between the current sense resistor and the
current sense pins, and the diode should be connected
such that it can conduct current in the direction from V
OUT
to V
IN
, this means the anodes will be connected to ISNSM.
In this circuit, the Schottky diode is a simple clamp to limit
the voltage across the pins. The 1Ω resistors are needed
to limit the current in each Schottky diode. Clearly, if only
one sense resistor is used, only one protection diode is
needed.
Supercapacitor Settling
The ESR-only supercapacitor model using a capacitor
in series with an equivalent series resistance (ESR) is
over-simplified. Real supercapacitors have an additional
settling time due to their internal physics
To explain the implications of this settling, assume a super
capacitor of infinite capacitance such that any voltage
change due to charging or discharging can be ignored. In
the simple ESR-only model, a pulse of current would simply
result in a step in voltage at its rising edge and a step back
to its initial voltage at its falling edge. A real supercapaci-
tor’s response to the same pulse of current’s rising edge
will be an instantaneous step in voltage due to the high
frequency ESR, followed by a settling to a higher voltage
due to the “DC” ESR. On the falling edge there will be an
LTC3351
39
Rev. A
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instantaneous drop in voltage due to the high frequency
ESR and a slower settling back to the original voltage due
to the “DC” ESR. The following figure illustrates this.
Figure15.
VCAP
ICAP
REAL
ESR ONLY
MODEL
3351 F15
t
t
This results in an ESR measurement dependent on the fre-
quency at which it is measured. There is a high frequency
ESR and a larger “DC” ESR. In energy storage applications
where the capacitors will supply a sustained load, the
“DC” ESR limits the deliverable power. Supercapacitor
manufacturers have various methods for measuring ESR.
Even when specifying a “DC” ESR, the measurement is
often done at a frequency significantly higher than “DC”,
often near 100Hz, thereby reporting an intermediate fre-
quency ESR.
ESR Measurement Timing Adjustments
The LTC3351 default ESR measurement timing is set to
measure between the DC and high frequency ESR, closer
to the high frequency ESR for a wide variety of superca-
pacitors. The timing can be adjusted to measure closer to
the DC ESR, however this must done empirically based on
the exact switching controller configuration and capaci-
tors used. Values appropriate for some capacitors would
result in failed measurements for others and there are
no meaningful defaults preprogrammed in the LTC3351.
Using an DC coupled oscilloscope with a precision offset,
observe the supercapacitor stack voltage (VCAP) during
the ESR test. AC coupling will not work as the signal time
scales are too long to cross the oscilloscope’s AC coupling
high pass filter without distortion. Set the oscilloscope
to trigger on SMBALERT falling and enabling the mon_
meas_active alert using the mask_mon_meas_active bit.
Then set the ctl_start_cap_esr_meas to start the ESR
measurement. The SMBAlert will need to be cleared each
time to re-trigger the oscilloscope. Alternatively, a current
probe can be used to trigger on input current, since the
input current will be high during the ESR test.
The esr_i_override setting is available to prevent the auto-
matic adjustment of the ESR test current. The automati-
cally selected ESR test current is available in the next_
esr_i register. After several measurements have been
completed, next_esr_i may be used as a starting point to
manually set esr_i_override. While adjusting the timing
of the ESR measurement, either set esr_i_override so the
test current won’t change between successive measure-
ments or do each measurement twice for each setting and
ignore the first result.
Referring to Figure4, using the oscilloscope you can now
see the effects of esr_i_on_settling and esr_i_off_settling
on the captured waveform. Begin by adjusting esr_i_off_
settling so that VCAP is no longer decreasing significantly
after esr_i_off_settling time. This time will likely be sig-
nificantly longer than the default time.
The esr_i_on_settling time is a little more complicated
to adjust as the capacitors are being charged during this
time. If the esr_i_on_settling time is too short, the internal
chemistry of the supercapacitor will not have settled and
the ESR measured will be closer to the high frequency
ESR than the DC ESR. If esr_i_on_settling is too long
and esr_i_override is not set, then charge current will be
automatically adjusted downward, resulting in reduced
signal for the ESR measurement. If esr_i_on_settling is
too long while esr_i_override is set, the capacitors will
charge to constant voltage and charge current will fall,
corrupting the measurement. This can be observed in
the input current waveform. During an ESR test, it should
not decrease, it should turn off cleanly. The charge cur-
rent can also be observed by comparing esr_m1_i and
esr_m2_i. They should be about the same, esr_m2_i
should not be significantly less than esr_m1_i. If it is,
esr_i_on_settling is too long.
If esr_i_override is set, monitor the increase in stack volt-
age during the ESR test. Ideally it should be about the
same as the Δv in the capacitance test (as set by cap_
delta_v_setting). If the change in voltage during the ESR
test is less than in the capacitance test, esr_i_override
can be increased to maximize the signal available for
LTC3351
40
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ESR test. If the voltage increase during the ESR test is
more than the voltage set by cap_delta_v_setting, cap_
delta_v_setting can be increased for more resolution in
the capacitance test.
When configuring the test, there must be enough voltage
between the vcapfb_dac setting and 1.2V to perform the
test.
If configuring the ESR test to measure the high frequency
ESR, the only adjustment necessary is to reduce the
esr_i_off_settling to 0. The default setting for esr_i_on_
settling is set to fully allow the switcher to settle under
all normal conditions and should not be further reduced
when measuring the high frequency ESR.
Individual Capacitor ESR and Capacitance Calculation
The LTC3351 reports total stack capacitance and ESR.
From the stored voltage and current measurements, it
is possible to calculate each individual capacitor’s ESR
and capacitance. For the calculation algorithm contact
the factory.
Capacitance Measurement Timing Adjustments
Like the ESR measurement, the capacitance measure-
ment is subject to non-ideal effects of the supercapaci-
tors. The LTC3351 measures capacitance by pre-charging
the capacitor stack by 1.25•cap_delta_v_setting (the
ESR test contributes to this charging), turning on a test
discharge current, waiting the time specified by cap_i_
on_settling, measuring a first voltage, then waiting for
the stack to discharge cap_delta_v_setting from the first
measurement. In this test the capacitors are discharged
by a known voltage with a known current and the time is
proportional to capacitance.
Since the capacitors are charged by 1.25 times the change
in voltage during the capacitance test, there is an “extra”
25 percent of the measurement time. Some of this time
can be used to allow the capacitors to settle into a con-
stant rate of voltage decrease. A starting point would
be to use 15 percent of the expected discharge time as
cap_i_on_settling. In the equation below, C should be the
minimum expected stack capacitance due to aging and
tolerance and Δv is change in voltage.
tDISCHARGE =Δ v •C •RTST
1.2V
Combining the above equation, the equation for switcher
frequency and cap_i_on_settling LSB weight results in:
cap _ i_ on _ settling =Δ v • C • 6.5 • 10
6
•RTST
R
t
The above equation is only a starting point. Adequate
settling can be confirmed by triggering an oscilloscope
on the rising edge of ITST (or alternately on SMBALERT
using the mon_esr_done alarm). Observe the response
of the discharging capacitors. They should have clearly
settled into a linear discharge by the time specified in
cap_i_on_settling after the trigger. If they have not settled
in time, cap_i_on_settling needs to be increased. cap_i_
on_settling cannot be increased beyond 25 percent of the
expected minimum measurement time. If 25 percent of
the expected measurement time is inadequate to settle,
the expected measurement time may be increased by
increasing Δv via cap_delta_v_setting.
PCB Layout Considerations
When laying out the printed circuit board, the following
guidelines should be used to ensure proper operation of
the IC. Check the following in your layout:
1. The VCC2P5 bypass capacitor must return to SGND or
the ground plane. If returning to the ground plane keep
away from the switcher’s high di/dt loop.
2. Referring to Figure16, keep MN1, MN2 and COUT close
together. The high di/dt loop formed by the MOSFETs,
Schottky diodes and the VOUT capacitance should have
short, wide traces to minimize high frequency noise and
voltage stress from inductive ringing. Surface mount
components are preferred to reduce parasitic induc-
tances from component leads. Connect the drain of the
top MOSFET directly to the positive terminal of COUT.
Connect the source of the bottom MOSFET directly to
the negative terminal of COUT. This capacitor provides
the AC current to the MOSFETs.
LTC3351
41
Rev. A
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Figure16.
+
+
+
+
HIGH
FREQUENCY
CIRCULATING
PATH
MN2
MN1
V
OUT
C
CAP
3351 F16
C
OUT
R
SNSC
V
CAP
L1
3. Ground is referenced to the negative terminal of the
VCAP decoupling capacitor in step-down mode and to
the negative terminal of the VOUT decoupling capacitor
in step-up mode. The combined IC SGND pin/PGND
paddle and the ground returns of CINTVCC and CDRVCC
must return to the combined negative terminal of COUT
and CCAP.
4. Effective grounding techniques are critical for success-
ful DC/DC converter layouts. Orient power components
such that switching current paths in the ground plane
do not cross through the SGND pin and exposed pad on
the backside of the LTC3351. Switching path currents
can be controlled by orienting the MOSFET switches,
the inductor, and VOUT and VCAP decoupling capacitors
in close proximity to each other.
It is important to keep SGND and the components
connected to SGND away from interference due to
switching currents. To do this, an island of SGND is
formed on top metal. This SGND island should only
connect to PGND on top metal under the LTC3351,
between the SGND pin and the exposed pad of the
LTC3351. This should be the only connection between
SGND and PGND. This area of top metal is where the
LTC3351’s small signal components such as RT, VC,
feedback dividers and VCC2P5 bypass capacitor should
be connected. Power components and all other bypass
capacitors should not connect to SGND.
5. Locate VCAP and VOUT dividers near the LTC3351 and
away from switching components. Kelvin the top of
resistor dividers to the positive terminals of CCAP and
C
OUT
, respectively. The bottom of the resistive dividers
should return directly to the SGND pin. The feedback
resistor connections should not be run along the high
current feeds from the COUT capacitor.
6. Route ICAP and VCAP sense lines together, keep them
short. Apply this rule to ISNSP_HS, ISNSP_CHG and
ISNSM as well. Filter components should be placed
near the part and not near the sense resistors. Ensure
accurate current sensing with Kelvin connections at the
sense resistors. See Figure17.
Figure17.
3351 F17
DIRECTION OF SENSED CURRENT
RSNSC
OR
RSNSI
TO VCAP
OR
ISNSM
TO ICAP
OR
ISNSP_HS
OR
ISNSP_CHG
7. Locate the DRV
CC
and BST decoupling capacitors in
close proximity to the LTC3351. These capacitors carry
the MOSFET drivers’ high peak currents. An additional
0.1μF ceramic capacitor placed immediately next to
the DRVCC pin can help improve noise performance
substantially.
8. Locate the small-signal components away from high
frequency switching nodes (BST, SW, TG, and BG). All
of these nodes have very large and fast moving signals
and should be kept on the output side of the LTC3351.
9. The output ideal diode senses the voltage between
VOUT and VCAP. VCAP is used for Kelvin sensing the
charge current. Place the output ideal diode MOSFET
near the charge current sense resistor, RSNSC, with a
short, wide trace to minimize resistance between the
source of the ideal diode MOSFET and RSNSC.
10. The OUTFET pin for the external ideal diode controller
has extremely limited drive current. Care must be taken
to minimize leakage to adjacent PC board traces. 100nA
of leakage from this pin will introduce an additional ideal
diode offset of approximately 10mV.
LTC3351
42
Rev. A
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REGISTER MAP
Symbol Name
Command
Code Access
Bit
Range Default Description
ctl_reg 0 R/W [10:0] 0 Control Register: Several independent control bits are grouped into this register.
ctl_start_cap_esr_meas
[0] 0 Begin a capacitance and ESR measurement when possible; this bit clears itself
once a measurement cycle begins or becomes pending.
Enum: start_measurement = 1
ctl_gpi_buffer_en [1] 0 A one in this bit location enables the input buffer on the GPI pin. With a zero in
this location the GPI pin is measured without the buffer.
ctl_stop_cap_esr_meas
[2] 0 Stops an active capacitance/ESR measurement; this bit clears itself once a
measurement cycle has been stopped.
Enum: stop_measurement = 1
ctl_cap_scale [3] 0 Increases capacitor measurement resolution 100 times, this is used when
measuring smaller capacitors.
Enums: large_cap = 0,
small_cap = 1
ctl_disable_shunt [4] 0 Disables the shunt feature.
ctl_hotswap_disable [5] 0 Disables the HotSwap controller. The gate of the hotswap FET is forced low,
disconnecting VIN and VOUT and forcing the switcher into backup mode. This can
be used to simulate a power failure for testing.
ctl_force_boost_off [6] 0 This bit disables the boost.
ctl_force_charger_off [7] 0 This bit disables the charger.
ctl_force_itst_on [8] 0 This bit forces the ITST current on. This can be used to discharge the capacitor
stack or manually measure capacitance. Note that this only enables the test
current, it does not disable the charger. Set ctl_force_charger_off to disable the
charger.
ctl_disable_balancer [10] 0 Disables the balancer.
alarm_mask_reg 1 R/W [15:0] 0 Mask Alarms Register: Writing a one to any bit in this register enables a rising
edge of its respective bit in alarm_reg to trigger an SMBALERT.
mask_alarm_gpi_uv [0] 0 GPI Under Voltage alarm mask
mask_alarm_gpi_ov [1] 0 GPI Over Voltage alarm mask
mask_alarm_vin_uv [2] 0 VIN Under Voltage alarm mask
mask_alarm_vin_ov [3] 0 VIN Over Voltage alarm mask
mask_alarm_vcap_uv [4] 0 VCAP Under Voltage alarm mask
mask_alarm_vcap_ov [5] 0 VCAP Over Voltage alarm mask
mask_alarm_vout_uv [6] 0 VOUT Under Voltage alarm mask
mask_alarm_vout_ov [7] 0 VOUT Over Voltage alarm mask
mask_alarm_dtemp_
cold
[8] 0 Die temperature cold alarm mask
mask_alarm_dtemp_
hot
[9] 0 Die temperature hot alarm mask
mask_alarm_ichg_uc [10] 0 Charge undercurrent alarm mask
mask_alarm_iin_oc [11] 0 Input overcurrent alarm mask
mask_alarm_cap_uv [12] 0 Capacitor Under Voltage alarm mask
mask_alarm_cap_ov [13] 0 Capacitor Over Voltage alarm mask
mask_alarm_cap_lo [14] 0 Capacitance low alarm mask
mask_alarm_esr_hi [15] 0 ESR high alarm mask
LTC3351
43
Rev. A
For more information www.analog.com
REGISTER MAP
Symbol Name
Command
Code Access
Bit
Range Default Description
monitor_status_
mask_reg
2 R/W [14:0] 0 Mask Monitor Status Register: Writing a one to any bit in this register enables a
rising edge of its respective bit in monitor_status_reg to trigger an SMBALERT.
mask_mon_meas_
active
[0] 0 Set the SMBALERT when there is a rising edge on mon_meas_active
mask_mon_capesr_
pending
[2] 0 Set the SMBALERT when there is a rising edge on mon_capesr_pending
mask_mon_cap_done [3] 0 Set the SMBALERT when there is a rising edge on mon_cap_done
mask_mon_esr_done [4] 0 Set the SMBALERT when there is a rising edge on mon_esr_done
mask_mon_meas_
failed
[5] 0 Set the SMBALERT when there is a rising edge on mon_meas_failed
mask_mon_disable_
charger
[7] 0 Set the SMBALERT when there is a rising edge on mon_disable_charger
mask_mon_cap_
meas_active
[8] 0 Set the SMBALERT when there is a rising edge on mon_cap_meas_active
mask_mon_esr_meas_
active
[9] 0 Set the SMBALERT when there is a rising edge on mon_esr_meas_active
mask_mon_power_
failed
[10] 0 Set the SMBALERT when there is a rising edge on mon_power_failed
mask_mon_power_
returned
[11] 0 Set the SMBALERT when there is a rising edge on mon_power_returned
mask_mon_balancing [12] 0 Set the SMBALERT when there is a rising edge on mon_balancing
mask_mon_shunting [13] 0 Set the SMBALERT when there is a rising edge on mon_shunting
mask_mon_cap_
precharge
[14] 0 Set the SMBALERT when there is a rising edge on mon_cap_precharge
vcapfb_dac 3 R/W [3:0] 10 VCAP Regulation Reference: This register is used to program the capacitor
voltage feedback loop's reference voltage. Only bits 3:0 are active. VCAPFB_DAC
= 37.5mV * vcapfb_dac + 637.5mV
vshunt 5 R/W [15:0] 14744 Shunt Voltage Register: This register programs the shunt voltage for each
capacitor in the stack. When set below 3.6V, the charger will limit current and the
active shunts will shunt current to prevent this voltage from being exceeded. As a
capacitor voltage nears this level, the charge current will be reduced. Current will
be shunted when the capacitor voltage is within 25mV of vshunt. Vshunt should
be programmed at least 50mV higher than the intended final balanced individual
capacitor voltage. When programmed above 3.6V no current will be shunted,
however the charge current will be reduced as described. 182.8µV per LSB.
adc_vin_ch_en_reg 6 R/W [11:1] 3842
adc_vin_ichg_en [1] 1 Enables ADC measurement of charge current while in charging mode.
adc_vin_dtemp_en [2] 0 Enables ADC measurement of die temperature while in charging mode.
adc_vin_gpi_en [3] 0 Enables ADC measurement of GPI (general purpose input) while in charging
mode.
adc_vin_iin_en [4] 0 Enables ADC measurement of input current while in charging mode.
adc_vin_vout_en [5] 0 Enables ADC measurement of vout while in charging mode.
adc_vin_vcap_en [6] 0 Enables ADC measurement of vcap while in charging mode.
adc_vin_vin_en [7] 0 Enables ADC measurement of vin while in charging mode.
adc_vin_vcap1_en [8] 1 Enables ADC measurement of vcap1 while in charging mode. This bit must be set
for capacitance and ESR measurement.
LTC3351
44
Rev. A
For more information www.analog.com
REGISTER MAP
Symbol Name
Command
Code Access
Bit
Range Default Description
adc_vin_vcap2_en [9] 1 Enables ADC measurement of vcap2 while in charging mode. This bit must be set
for capacitance and ESR measurement if there are two or more capacitors in the
stack.
adc_vin_vcap3_en [10] 1 Enables ADC measurement of vcap3 while in charging mode. This bit must be set
for capacitance and ESR measurement if there are three or more capacitors in the
stack
adc_vin_vcap4_en [11] 1 Enables ADC measurement of vcap4 while in charging mode. This bit must be set
for capacitance and ESR measurement if there are four capacitors in the stack
adc_backup_ch_en_
reg
7 R/W [11:1] 0
adc_backup_ichg_en [1] 0 Enables ADC measurement of charge current while in backup mode.
adc_backup_dtemp_en [2] 0 Enables ADC measurement of die temperature while in backup mode.
adc_backup_gpi_en [3] 0 Enables ADC measurement of GPI (general purpose input) while in backup mode.
adc_backup_iin_en [4] 0 Enables ADC measurement of input current while in backup mode.
adc_backup_vout_en [5] 0 Enables ADC measurement of vout while in backup mode.
adc_backup_vcap_en [6] 0 Enables ADC measurement of vcap while in backup mode.
adc_backup_vin_en [7] 0 Enables ADC measurement of vin while in backup mode.
adc_backup_vcap1_en [8] 0 Enables ADC measurement of vcap1 while in backup mode.
adc_backup_vcap2_en [9] 0 Enables ADC measurement of vcap2 while in backup mode.
adc_backup_vcap3_en [10] 0 Enables ADC measurement of vcap3 while in backup mode.
adc_backup_vcap4_en [11] 0 Enables ADC measurement of vcap4 while in backup mode.
adc_wait_vin 8 R/W [15:0] 100 Sets the wait time between ADC measurement groups while in charging mode.
The LSB of this register has a weight of 400uS. The ADC measures all enabled
channels then waits this time before measuring all channels again. The ADC data
is used for balancing and shunting, increasing this time reduces the shunt and
balancer update rate and is not typically recommended if shunting or balancing is
enabled. If shunting or measuring capacitance/ESR this time may be ignored by
the ADC. 400uS per LSB
adc_wait_backup 9 R/W [15:0] 100 Sets the wait time between ADC measurement groups while in backup mode.
The LSB of this register has a weight of 400uS. The ADC measures all enabled
channels then waits this time before measuring all channels again. 400uS per LSB
gpi_uv_lvl 10 R/W [15:0] 0 General Purpose Input Under Voltage Level: This is an alarm threshold for the GPI
pin. If enabled, the GPI pin voltage falling below this level will trigger an alarm and
an SMBALERT. 182.8µV per LSB
gpi_ov_lvl 11 R/W [15:0] 0 General Purpose Input Over Voltage Level: This is an alarm threshold for the GPI
pin. If enabled, the GPI pin voltage rising above this level will trigger an alarm and
an SMBALERT. 182.8µV per LSB
vin_uv_lvl 12 R/W [15:0] 0 VIN Under Voltage Level: This is an alarm threshold for the input voltage. If
enabled, the input pin voltage falling below this level will trigger an alarm and an
SMBALERT. 2.19mV per LSB
vin_ov_lvl 13 R/W [15:0] 0 VIN Over Voltage Level: This is an alarm threshold for the input voltage. If
enabled, the input pin voltage rising above this level will trigger an alarm and an
SMBALERT. 2.19mV per LSB
vcap_uv_lvl 14 R/W [15:0] 0 VCAP Under Voltage Level: This is an alarm threshold for the capacitor stack
voltage. If enabled, the VCAP pin voltage falling below this level will trigger an
alarm and an SMBALERT. 1.46mV per LSB
vcap_ov_lvl 15 R/W [15:0] 0 VCAP Over Voltage Level: This is an alarm threshold for the capacitor stack
voltage. If enabled, the VCAP pin voltage rising above this level will trigger an
alarm and an SMBALERT. 1.46mV per LSB
LTC3351
45
Rev. A
For more information www.analog.com
REGISTER MAP
Symbol Name
Command
Code Access
Bit
Range Default Description
vout_uv_lvl 16 R/W [15:0] 0 VOUT Under Voltage Level: This is an alarm threshold for the output voltage. If
enabled, the VOUT pin voltage falling below this level will trigger an alarm and an
SMBALERT. 2.19mV per LSB
vout_ov_lvl 17 R/W [15:0] 0 VOUT Over Voltage Level: This is an alarm threshold for the output voltage. If
enabled, the VOUT pin voltage rising above this level will trigger an alarm and an
SMBALERT. 2.19mV per LSB
dtemp_cold_lvl 18 R/W [15:0] 0 Die Temperature Cold Level: This is an alarm threshold for the die temperature. If
enabled, the die temperature falling below this level will trigger an alarm and an
SMBALERT. Temperature = 0.0295C per LSB - 274C
dtemp_hot_lvl 19 R/W [15:0] 0 Die Temperature Hot Level: This is an alarm threshold for the die temperature. If
enabled, the die temperature rising above this level will trigger an alarm and an
SMBALERT. Temperature = 0.0295C per LSB - 274C
ichg_uc_lvl 20 R/W [15:0] 0 Charge Undercurrent Level: This is an alarm threshold for the charge current. If
enabled, the charge current falling below this level will trigger an alarm and an
SMBALERT. 1.955µV/Rsnsc per LSB
iin_oc_lvl 21 R/W [15:0] 0 Input Overcurrent Level: This is an alarm threshold for the input current. If
enabled, the input current rising above this level will trigger an alarm and an
SMBALERT. 1.955µV/Rsnsi per LSB
cap_uv_lvl 22 R/W [15:0] 0 Capacitor Under Voltage Level: This is an alarm threshold for each individual
capacitor voltage in the stack. If enabled, any capacitor voltage falling below this
level will trigger an alarm and an SMBALERT. 182.8µV per LSB.
cap_ov_lvl 23 R/W [15:0] 0 Capacitor Over Voltage Level: This is an alarm threshold for each individual
capacitor in the stack. If enabled, any capacitor voltage rising above this level will
trigger an alarm and an SMBALERT. 182.8µV per LSB
cap_lo_lvl 24 R/W [15:0] 0 Capacitance Low Level: This is an alarm threshold for the measured stack
capacitance. If the measured stack capacitance is less than this level it will
trigger an alarm and an SMBALERT, if enabled. When ctl_cap_scale is set to 1,
capacitance is 3.36µF * RT/RTST per LSB. When ctl_cap_scale is set to 0 it is
336µF * RT/RTST per LSB.
esr_hi_lvl 25 R/W [15:0] 0 ESR High Level: This is an alarm threshold for the measured stack ESR. If
enabled, a measurement of stack ESR exceeding this level will trigger an alarm
and an SMBALERT. Rsnsc/64 per LSB.
esr_i_on_settling 26 R/W [15:0] 2 Time to allow the charging current to settle before measuring the charge voltage
and current for ESR. Each LSB is 1024 switcher periods.
esr_i_off_settling 27 R/W [15:0] 8 Time to wait after turning the charge current off before measuring the charge
voltage and current for ESR. Each LSB is 1024 switcher periods.
esr_i_override 28 R/W [15:0] 0 This value overrides the LTC3351's adaptive test current selection for the ESR
test. If this register is non-zero, the lower 8 bits will be used as an 8 bit DAC value
to set the charge current during the ESR test. Typically this register will not need
to be set. ITEST = 32mV * (esr_i_override[7:0] + 1) / 256 / Rsnsc
cap_i_on_settling 29 R/W [15:0] 8 Time to wait after turning the test current on before measuring the first voltage of
the capacitance measurement. Each LSB is 1024 switcher periods.
cap_delta_v_setting 30 R/W [15:0] 550 The target delta V for the capacitance test. The scale is 182.8µV per LSB. The
default is approximately 100mV.
LTC3351
46
Rev. A
For more information www.analog.com
REGISTER MAP
Symbol Name
Command
Code Access
Bit
Range Default Description
min_boost_cap_
voltage
31 R/W [15:0] 0 If this register is non-zero, it sets the minimum capacitor voltage the boost will
operate at. If any capacitor voltage falls below this value in boost mode the boost
will be forced off, the boost will not turn back on even if the capacitor voltage rises
above this voltage. Only after input power returns will the boost be re-enabled.
This prevents the boost from cycling on and off many times once the capacitors'
voltage has discharged to the point it can no longer support the system load
through the boost. To use this feature vcap[1:num_caps+1] measurements must
be enabled in backup mode, see adc_backup_ch_en_reg. Also the capacitor
voltages are only measured as often as set by adc_wait_backup.
min_vout_hs_disable 32 R/W [15:0] 0 If this register is non-zero, it sets the minimum voltage VOUT is allowed to
reach while the HotSwap is disabled. If the voltage falls below this level the
ctl_hotswap_disable bit will be cleared, re-enabling the HotSwap controller. To
use this feature the VOUT measurement must be enabled in boost mode, see
adc_backup_ch_en_reg. Also the VOUT voltage is only measured as often as set
by adc_wait_backup.
alarm_reg 35 R/W [15:0] 0 Alarms Register: A one in any bit in the register indicates its respective alarm has
triggered. All bits are active high. Alarms are cleared by clearing (writing 0) the
appropriate bit in this register. Setting (writing 1) bits has no effect. For example
to clear the alarm_gpi_uv alarm, write 0xFFFD.
alarm_gpi_uv [0] 0 GPI Under Voltage alarm
alarm_gpi_ov [1] 0 GPI Over Voltage alarm
alarm_vin_uv [2] 0 VIN Under Voltage alarm
alarm_vin_ov [3] 0 VIN Over Voltage alarm
alarm_vcap_uv [4] 0 VCAP Under Voltage alarm
alarm_vcap_ov [5] 0 VCAP Over Voltage alarm
alarm_vout_uv [6] 0 VOUT Under Voltage alarm
alarm_vout_ov [7] 0 VOUT Over Voltage alarm
alarm_dtemp_cold [8] 0 Die temperature cold alarm
alarm_dtemp_hot [9] 0 Die temperature hot alarm
alarm_ichg_uc [10] 0 Charge undercurrent alarm
alarm_iin_oc [11] 0 Input overcurrent alarm
alarm_cap_uv [12] 0 Capacitor Under Voltage alarm
alarm_cap_ov [13] 0 Capacitor Over Voltage alarm
alarm_cap_lo [14] 0 Capacitance low alarm
alarm_esr_hi [15] 0 ESR high alarm
monitor_status_reg 36 R [15:0] N/A Monitor Status: This register provides real time status information about the state
of the monitoring system. Each bit is active high.
mon_meas_active [0] N/A Capacitance/ESR measurement is active. This bit becomes one at the begining
of a capacitance/ESR measurement and remains 1 after the measurement has
completed until the capacitors have been discharged back to their regualtion
voltage.
mon_capesr_scheduled
[1] N/A Indicates that the LTC3351 is waiting programmed time to begin a capacitance/
ESR measurement
mon_capesr_pending [2] N/A Indicates that the LTC3351 is waiting for satisfactory conditions to begin a
capacitance/ESR measurement
mon_cap_done [3] N/A Indicates that the capacitance measurement has completed
mon_esr_done [4] N/A Indicates that the ESR Measurement has completed
LTC3351
47
Rev. A
For more information www.analog.com
REGISTER MAP
Symbol Name
Command
Code Access
Bit
Range Default Description
mon_meas_failed [5] N/A Indicates the last attempted capacitance and ESR measurement was unable to
complete
mon_boost_shutdown [6] N/A This bit is set in boost mode when any capacitor falls below min_boost_cap_
voltage_reg. It is cleared when power returns.
mon_disable_charger [7] N/A Indicates the capacitance and ESR measurement system has temporarily disabled
the charger.
mon_cap_meas_active [8] N/A Indicates the capacitance and ESR measurement system is measuring
capacitance.
mon_esr_meas_active [9] N/A Indicates the capacitance and ESR measurement system is measuring ESR.
mon_power_failed [10] N/A This bit is set when VIN is outside the UV/OV range or the HotSwap controller is
disabled by setting the ctl_hotswap_disable. It is cleared only when mon_power_
returned is set.
mon_power_returned [11] N/A This bit is set when the output is powered by the input and the charger is able to
charge. It is cleared only when mon_power_failed is set.
mon_balancing [12] N/A Indicates the LTC3351 is balancing the capacitor voltage.
mon_shunting [13] N/A Indicates a capacitor voltage is approaching vshunt and a shunt is turned on.
mon_cap_precharge [14] N/A Indicates the capacitor stack is being precharged for a capacitance measurement.
mon_reset [15] N/A This bit is set during a power on reset. It is cleared on any I2C/SMBus write. It
can be used to determine if the chip has reset during a power loss followed by a
power return.
meas_gpi 37 R [15:0] N/A Measurement of GPI pin voltage. 182.8µV per LSB
meas_vin 38 R [15:0] N/A Measured Input Voltage. 2.19mV per LSB
meas_vcap 39 R [15:0] N/A Measured Capacitor Stack Voltage. 1.46mV per LSB.
meas_vout 40 R [15:0] N/A Measured Output Voltage. 2.19mV per LSB.
meas_dtemp 41 R [15:0] N/A Measured die temperature. Temperature = 0.0295C per LSB - 274C
meas_ichg 42 R [15:0] N/A Measured Charge Current. 1.955µV/Rsnsc per LSB
meas_iin 43 R [15:0] N/A Measured Input Current. 1.955µV/Rsnsi per LSB
lo_vcap 44 R [15:0] N/A The lowest measured capacitor voltage from the last measurement set.
hi_vcap 45 R [15:0] N/A The highest measured capacitor voltage from the last measurement set.
meas_cap 46 R [15:0] N/A Measured capacitor stack capacitance value. When ctl_cap_scale is set to 1,
capacitance is 3.36µF * RT/RTST per LSB. When ctl_cap_scale is set to 0 it is
336µF * RT/RTST per LSB.
meas_esr 47 R [15:0] N/A Measured capacitor stack equivalent series resistance (ESR) value. Rsnsc/64 per
LSB
meas_vcap1 48 R [15:0] N/A Measured voltage between the CAP1 and CAPRTN pins. 182.8µV per LSB
meas_vcap2 49 R [15:0] N/A Measured voltage between the CAP2 and CAP1 pins. 182.8µV per LSB
meas_vcap3 50 R [15:0] N/A Measured voltage between the CAP3 and CAP2 pins. 182.8µV per LSB
meas_vcap4 51 R [15:0] N/A Measured voltage between the CAP4 and CAP3 pins. 182.8µV per LSB. When
the ITST current is on, either due to ctl_force_itst_on or during a capacitance
measurement, this voltage measurement will temporarily be low due to the ITST
current flowing in the shunt resistor.
cap_m0_vc1 52 R [15:0] N/A The voltage change on cap1 due to the capacitance measurement. The relative
voltage change on each capacitor during the capacitance measurement and the
total capacitance can be used to calculate the capacitance of each individual
capacitor.
LTC3351
48
Rev. A
For more information www.analog.com
REGISTER MAP
Symbol Name
Command
Code Access
Bit
Range Default Description
cap_m0_vc2 53 R [15:0] N/A The voltage change on cap2 due to the capacitance measurement. The relative
voltage change on each capacitor during the capacitance measurement and the
total capacitance can be used to calculate the capacitance of each individual
capacitor.
cap_m0_vc3 54 R [15:0] N/A The voltage change on cap3 due to the capacitance measurement. The relative
voltage change on each capacitor during the capacitance measurement and the
total capacitance can be used to calculate the capacitance of each individual
capacitor.
cap_m0_vc4 55 R [15:0] N/A The voltage change on cap4 due to the capacitance measurement. The relative
voltage change on each capacitor during the capacitance measurement and the
total capacitance can be used to calculate the capacitance of each individual
capacitor.
esr_m0_vc1 56 R [15:0] N/A A measurement of VCAP1 just before turning current on for the ESR
measurement. This value is used by the LTC3351 in the calculation of meas_esr.
esr_m0_vc2 57 R [15:0] N/A A measurement of VCAP2 just before turning current on for the ESR
measurement. This value is used by the LTC3351 in the calculation of meas_esr.
esr_m0_vc3 58 R [15:0] N/A A measurement of VCAP3 just before turning current on for the ESR
measurement. This value is used by the LTC3351 in the calculation of meas_esr.
esr_m0_vc4 59 R [15:0] N/A A measurement of VCAP4 just before turning current on for the ESR
measurement. This value is used by the LTC3351 in the calculation of meas_esr.
esr_m1_vc1 60 R [15:0] N/A The first VCAP1 voltage measurement with charge current on for the ESR
measurement. This value is used by the LTC3351 in the calculation of meas_esr.
esr_m1_vc2 61 R [15:0] N/A The first VCAP2 voltage measurement with charge current on for the ESR
measurement. This value is used by the LTC3351 in the calculation of meas_esr.
esr_m1_vc3 62 R [15:0] N/A The first VCAP3 voltage measurement with charge current on for the ESR
measurement. This value is used by the LTC3351 in the calculation of meas_esr.
esr_m1_vc4 63 R [15:0] N/A The first VCAP4 voltage measurement with charge current on for the ESR
measurement. This value is used by the LTC3351 in the calculation of meas_esr.
esr_m1_i 64 R [15:0] N/A The first charge current measurement with charge current on for the ESR
measurement. This value is used by the LTC3351 in the calculation of meas_esr.
esr_m2_vc1 65 R [15:0] N/A The second VCAP1 voltage measurement with the charge current on for the ESR
measurement. This value is used by the LTC3351 in the calculation of meas_esr.
esr_m2_vc2 66 R [15:0] N/A The second VCAP2 voltage measurement with the charge current on for the ESR
measurement. This value is used by the LTC3351 in the calculation of meas_esr.
esr_m2_vc3 67 R [15:0] N/A The second VCAP3 voltage measurement with the charge current on for the ESR
measurement. This value is used by the LTC3351 in the calculation of meas_esr.
esr_m2_vc4 68 R [15:0] N/A The second VCAP4 voltage measurement with the charge current on for the ESR
measurement. This value is used by the LTC3351 in the calculation of meas_esr.
esr_m2_i 69 R [15:0] N/A The second charge current measurement with charge current on for the ESR
measurement. This value is used by the LTC3351 in the calculation of meas_esr.
esr_m3_vc1 70 R [15:0] N/A The VCAP1 voltage measurement with charge current off for the ESR
measurement. This value is used by the LTC3351 in the calculation of meas_esr.
esr_m3_vc2 71 R [15:0] N/A The VCAP2 voltage measurement with charge current off for the ESR
measurement. This value is used by the LTC3351 in the calculation of meas_esr.
esr_m3_vc3 72 R [15:0] N/A The VCAP3 voltage measurement with charge current off for the ESR
measurement. This value is used by the LTC3351 in the calculation of meas_esr.
esr_m3_vc4 73 R [15:0] N/A The VCAP4 voltage measurement with charge current off for the ESR
measurement. This value is used by the LTC3351 in the calculation of meas_esr.
esr_m3_i 74 R [15:0] N/A The charge current measurement with charge current off for the ESR
measurement. This value is used by the LTC3351 in the calculation of meas_esr.
LTC3351
49
Rev. A
For more information www.analog.com
REGISTER MAP
Symbol Name
Command
Code Access
Bit
Range Default Description
rev_code 80 R [15:0] 5 The LTC3351 revision code.
next_esr_i 84 R [7:0] 32 The 8 bit DAC setting for the charge current that the LTC3351 has calculated for
the next ESR measurement based on the previous ESR measurement. The first
ESR measurement will use a setting of 32. If esr_i_override is non-zero, this
register will be calculated but esr_i_override will be used instead. If non-zero
ITEST = 32mV * (next_esr_i[7:0] + 1) / 256 / Rsnsc
num_caps 237 R [1:0] 0 Number of Capacitors. This register shows the state of the CAP_SLCT1,
CAP_SLCT0 pins. The value read in this register is the number of capacitors
programmed minus one.
sys_status 238 R [11:0] N/A System Status Register: This register provides real time status information about
the instantaneous state of the system. Each bit is active high.
stepdown_mode [0] N/A The synchronous controller is in step-down mode (charging)
stepup_mode [1] N/A The synchronous controller is in step-up mode (backup)
chrg_cv [2] N/A The charger is in constant voltage mode
chrg_uvlo [3] N/A The charger is in under-voltage lockout or has been disabled by
ctl_force_charger_off.
chrg_input_ilim [4] N/A The charger is in input current limit
cappg [5] N/A The capacitor voltage is above power good threshold
boost_en [7] N/A Indicates the boost is enabled
buck_en [8] N/A Indicates the charger is enabled
chrg_ci [9] N/A Indicates the charger is in constant current mode
vingd [11] N/A Indicates the input voltage is inside the UV/OV range.
Revision: 149 Date: 2017-08-18 15:51:04 -0400 (Fri, 18 Aug 2017)
Note: All registers are 16 bits. Unused bits not shown above should be
written as 0 and ignored when reading
LTC3351
50
Rev. A
For more information www.analog.com
TYPICAL APPLICATIONS
24V Input, 18V 36W Backup
35.7Ω
V
IN
VDD
V
IN
20V TO 30V
HS_GATE
MN5
SiS434DN
MN2
SiS434DN
L1
6.8µH
R
SNSC
0.005Ω
R
CAP
R
TN
2.7Ω
RCAP1 2.7Ω
MN3
SiS434DN
RSNSI
0.012Ω
RSNSH
0.004Ω
L
TC3351
ISNSM
UV
R
PF1
665k
D
B
1N4448HWT
C
B
0.
1
µF
C3
4.7µF
C4
0.
1
µF
C
CAP
22µF
×
4
R
FBC1
866k
R
FBC2
118k
C
F
0.
1
µF
220pF
C
CP5
0.
1
µF
CAP1 10F
C
FBO1
120pF
C
OUT2
10µF
×
4
C
OUT1
33µF
×
2
RFB02
46.4k
RFB01
649k
R
PF3
28k
R3
10k
R4
10k
C5
1
µF
107k
C
C
1.2nF
NTC
R2
10k
R1
10k
VCC2P5
CAPGD
SMBALE
R
T
SCL
SDA
VINGD
CAPGD
SMBALE
R
T
SCL
SDA
V
OUT
18V
36W IN BACKUP
CAP_SLCT0
CAP_SLCT1
3351 TA02
GND
PGND
GPI
VC
RT
ITST
CAP1-4: NESSCAP ESHSR-0010C0-002R7
L1: COILCRAFT XAL7070-682ME
D2: PDS1040L-13
D3–D5: DIODES INC 1N5819HW
R
PF3
14.3k
OV
ISNSP_HS
ISNSP_CHG
MN1
SiS434DN
SRC
CSS
C
ss
22nF
C
t
33nF
CTIMER
RETRYB
R
T
R
TST
VINGD
RVIN
100Ω
+
CAP2 10F
+
RCAP2 2.7Ω
CAP3 10F
+
RCAP3 2.7Ω
CAP4 10F
+
RCAP4 2.7Ω
RG1
10Ω
D1
SMBJ30A D2 D3 R4
1Ω
R5
1Ω
R6
1Ω
RG2
10Ω
10Ω D4
D5
10k
T
VOUT
OUTFET
OUTFB
INTVCC
DRVCC
BST
TGATE
SW
BGATE
ICAP
VCAP
CFP
CFN
VCAPP5
CAP4
CAP3
CAP2
CAP1
CAPRTN
CAPFB
LTC3351
51
Rev. A
For more information www.analog.com
TYPICAL APPLICATIONS
24V Input, 12V 36W Backup, 6 Capacitor Stack
35.7Ω
CP1
8.33F
16.2V
V
IN
VDD
V
IN
22V TO 30V
HS_GATE
MN5
SiS434DN
MN2
SiS434DN
MN4
SiS434DN
L1
6.8µH
R
SNSC
0.005Ω
MN3
SiS434DN
RSNSI
0.012Ω
RSNSH
0.004Ω
L
TC3351
ISNSM
UV
R
PF1
665k
D
B
1N4448HWT
C
B
0.
1
µF
C3
4.7µF
C4
0.
1
µF
C
CAP
22µF
×
4
R
FBC1
1.15MΩ
RT1
10k
T
NTC
R
FBC2
100k
C
F
0.
1
µF
220pF
C
CP5
0.
1
µF
C
FBO1
120pF
C
OUT2
10µF
×
4
C
OUT1
33µF
×
2
RFB02
73.2k
RFB01
665k
R
PF3
28k
R3
10k
R4
10k
C5
1
µF
107k
C
C
4.7nF
NTC
R2
10k
R1
10k
VCC2P5
CAPGD
SMBALE
R
T
SCL
SDA
VINGD
CAPGD
SMBALE
R
T
SCL
SDA
V
OUT
12V
36W IN BACKUP
CAP_SLCT0
CAP_SLCT1
3351 TA03
GND
PGND
GPI
VC
RT
ITST
CP1: TECATE GROUP PBLS-8.33/16.2
L1: COILCRAFT XAL7070-682ME
D2: PDS1040L-13
D3–D5: DIODES INC 1N5819HW
R
PF3
11k
OV
ISNSP_HS
ISNSP_CHG
MN1
SiS434DN
SRC
CSS
C
ss
22nF
C
t
33nF
CTIMER
RETRYB
R
T
R
TST
VINGD
RVIN
100Ω
+
+
+
+
+
+
RG1
10Ω
R4
1Ω
R5
1Ω
R6
1Ω
RG2
10Ω
D4
D5
RCAP4 100k
RCAP3 100k
RCAP2 100k
RCAP1 100k
BACKUP_DONE
D1
SMBJ30A D2 D3
10Ω
VOUT
OUTFET
OUTFB
INTVCC
DRVCC
BST
TGATE
SW
BGATE
ICAP
VCAP
CFP
CFN
VCAPP5
CAP4
CAP3
CAP2
CAP1
CAPRTN
CAPFB
LTC3351
52
Rev. A
For more information www.analog.com
TYPICAL APPLICATIONS
12V Backup Controller with Reverse Input Protection
35.7Ω
V
IN
VDD
V
IN
–18V TO 18V
HS_GATE
MN5
SiS438DN
MN2
BSZ060NE2LS
MN4
SiS438DN
L1
3.3µH
R
SNSC
0.006Ω
R
CAP
R
TN
2.7Ω
RCAP1 2.7Ω
MN3
BSZ060NE2LS
R
SNSI
0.008Ω
L
TC3351
ISNSM
UV
R
PF1
665k
D
B
1N4448HWT
C
B
0.
1
µF
C3
4.7µF
C4
0.
1
µF
C
CAP
22µF
×
4
R
FBC1
866k
R
FBC2
118k
C
F
0.
1
µF
C
CP5
0.
1
µF
CAP1 10F
C
FBO1
120pF
C
OUT2
2.2µF
×
2
C
OUT1
47µF
×
2
RFB02
162k
RFB01
649k
R
PF3
49.9k
R3
10k
R4
100k
C5
1
µF
71.5k
C
C
10nF
R
T1
100k
R2
10k
R1
10k
VCC2P5
CAPGD
SMBALE
R
T
SCL
SDA
PFO
CAPGD
SMBALE
R
T
SCL
SDA
V
OUT
6V
25W IN BACKUP
CAP_SLCT0
CAP_SLCT1
3351 TA04
GND
PGND
T
GPI
VC
RT
ITST
CAP1-4: NESSCAP ESHSR-0010C0-002R7
L1: COILCRAFT XAL7030-332ME
D1: SMBJ18CA
D2: 1N4148
R
PF3
33.2k
OV
ISNSP_HS
ISNSP_CHG
MN1
SiS438DN
SRC
CSS
C
ss
22nF
C
t
33nF
CTIMER
RETRYB
R
RT1
1M
R
RT2
52.3k
R
T
R
TST
VINGD
RVIN
1k
DIN
BATS4
+
CAP2 10F
+
RCAP2 2.7Ω
CAP3 10F
+
RCAP3 2.7Ω
CAP4 10F
+
RCAP4 2.7Ω
D1 RGATE1
10Ω
RQ2
10k
DQ2
1n4148
Q1
2n3904
RGATE2
10Ω
RHS_GATE
100k
RSRC
100k
D2
VOUT
OUTFET
OUTFB
INTVCC
DRVCC
BST
TGATE
SW
BGATE
ICAP
VCAP
CFP
CFN
VCAPP5
CAP4
CAP3
CAP2
CAP1
CAPRTN
CAPFB
LTC3351
53
Rev. A
For more information www.analog.com
TYPICAL APPLICATIONS
4.8V to 12V 10A Supercap Charger with 5V 30W Backup Mode
20Ω
VOUT
RTRY2
10k
RTRY1
200k
V
IN
VDD
V
IN
4.8V TO 12V
HS_GATE
MN5
SiS452DN
MN2
SiS452DN
L1
1µH
R
SNSC
0.003Ω
R
CAP
R
TN
2.7Ω
RCAP1 2.7Ω
MN3
SiS452DN
R
SNSI
0.005Ω
L
TC3351
ISNSM
UV
R
PF1
30.1k
D
B
1N4448HWT
C
B
0.
1
µF
C3
4.7µF
C4
0.
1
µF
C
CAP
22µF
×
4
R
FBC1
866k
R
FBC2
118k
C
F
0.
1
µF
C
CP5
0.
1
µF
CAP1 50F
C
FBO1
100pF
C
OUT2
2.2µF
×
2
C
OUT1
100µF
×
6
RFB02
210k
RFB01
665k
R
PF3
4.02k
R3
10k
R4
100k
C5
1
µF
C
C
4.7nF
R
T1
100k
R2
10k
R1
10k
VCC2P5
CAPGD
SMBALE
R
T
SCL
SDA
PFO
CAPGD
SMBALE
R
T
SCL
SDA
V
OUT
5V
5V 30W
CAP_SLCT0
CAP_SLCT1
3351 TA05
GND
PGND
T
GPI
VC
RT
ITST
CAP1-4: NESSCAP ESHSR-0010C0-002R7
L1: COILCRA
F
T XAL7030-332ME
R
PF3
6.04k
OV
ISNSP_HS
ISNSP_CHG
MN1
SiS452DN
SRC
CSS
C
ss
22nF
C
t
33nF
CTIMER
RETRYB
RT
88.7k
R
TST
VINGD
RVIN
100Ω
+
CAP2 50F
+
RCAP2 2.7Ω
SMAJ10A RGATE
10Ω 10Ω
2k
VOUT
OUTFET
OUTFB
INTVCC
DRVCC
BST
TGATE
SW
BGATE
ICAP
VCAP
CFP
CFN
VCAPP5
CAP4
CAP3
CAP2
CAP1
CAPRTN
CAPFB
LTC3351
54
Rev. A
For more information www.analog.com
PACKAGE DESCRIPTION
4.00 ±0.10
5.60 REF
6.10 ±0.05
2.64 ±0.05
7.50 ±0.05
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
PIN 1
TOP MARK
(SEE NOTE 6)
43
1
2
44
BOTTOM VIEW—EXPOSED PAD
2.40 REF
3.10 ±0.05
4.50 ±0.05
7.00 ±0.10 5.60 REF
0.75 ±0.05
0.20 ±0.05
(UFF44) QFN REV 0 0415
0.40 BSC
0.200 REF
0.00 – 0.05
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
2.40 REF
2.64
±0.10
0.40 ±0.10
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 NOTCH
R = 0.30 TYP
OR 0.35 × 45°
CHAMFER
UFF Package
44-Lead Plastic QFN (4mm × 7mm)
(Reference LTC DWG # 05-08-1500 Rev Ø)
5.64
±0.10
0.74 ±0.10
R = 0.10 TYP
R = 0.10 TYP
R = 0.10
TYP
0.40 BSC
PACKAGE
OUTLINE
0.20 ±0.05
5.64 ±0.05
0.70 ±0.05
LTC3351
55
Rev. A
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 08/19 Split FSW specification into room temperature and overtemperature and changed limits
Hot Swap Component Selection: Changed verbiage from “reduced” to “increased”
3
26
LTC3351
56
Rev. A
For more information www.analog.com
ANALOG DEVICES, INC. 2017-2019
08/19
www.analog.com
RELATED PARTS
TYPICAL APPLICATION
12V PCLE Backup Controller
35.7Ω
V
IN
VDD
V
IN
11V TO 18V
HS_GATE
MN5
SiS438DN
MN2
BSZ060NE2LS
MN4
SiS438DN
L1
3.3µH
R
SNSC
0.006Ω
R
CAP
R
TN
2.7Ω
RCAP1 2.7Ω
MN3
BSZ060NE2LS
R
SNSI
0.008Ω
L
TC3351
ISNSM
UV
R
PF1
665k
D
B
1N4448HWT
C
B
0.
1
µF
C3
4.7µF
C4
0.
1
µF
C
CAP
22µF
×
4
R
FBC1
866k
R
FBC2
118k
C
F
0.
1
µF
C
CP5
0.
1
µF
CAP1 10F
C
FBO1
120pF
C
OUT2
2.2µF
×
2
C
OUT1
47µF
×
2
RFB02
162k
RFB01
649k
R
PF3
49.9k
R3
10k
R4
100k
C5
1
µF
71.5k
C
C
10nF
R
T1
100k
R2
10k
R1
10k
VCC2P5
CAPGD
SMBALE
R
T
SCL
SDA
PFO
CAPGD
SMBALE
R
T
SCL
SDA
V
OUT
6V
25W IN BACKUP
CAP_SLCT0
CAP_SLCT1
3351 TA06
GND
PGND
T
GPI
VC
RT
ITST
CAP1-4: NESSCAP ESHSR-0010C0-002R7
L1: COILCRA
F
T XAL7030-332ME
R
PF3
33.2k
OV
ISNSP_HS
ISNSP_CHG
MN1
SiS438DN
SRC
CSS
C
ss
22nF
C
t
33nF
CTIMER
RETRYB
R
RT1
1M
R
RT2
52.3k
R
T
R
TST
VINGD
RVIN
100Ω
+
CAP2 10F
+
RCAP2 2.7Ω
CAP3 10F
+
RCAP3 2.7Ω
CAP4 10F
+
RCAP4 2.7Ω
D1
SMBJ18A
RGATE
10Ω
VOUT
OUTFET
OUTFB
INTVCC
DRVCC
BST
TGATE
SW
BGATE
ICAP
VCAP
CFP
CFN
VCAPP5
CAP4
CAP3
CAP2
CAP1
CAPRTN
CAPFB
PART NUMBER DESCRIPTION COMMENTS
Power Management
LTC3350 Bidirectional Controller, Monitor and PowerPath for Supercapacitors ICHARGE = 10A+, VIN: 4.5V to 35V, VOUT: 4V to 35V
LTC3225 Boost Charge Pump Supercapacitor Charger ICHARGE = 0.15A, VIN: 2.8V to 5.5V, VOUT: 4.8V to 5.3V
LTC3226 Boost Charge Pump and PowerPath Manager for Supercapacitors ICHARGE = 0.33A, VIN: 2.5V to 5.5V, VOUT: 2.5V to 5.5V
LTC3625 Buck and Boost Supercapacitor Charger ICHARGE = 1A, VIN: 2.7V to 5.5V, VOUT: 4V to 5.3V
LTC3355 Buck Supercapacitor Charger and Boost Backup ICHARGE = 1A, VIN: 3V to 20V, VOUT: 2.7V to 5.5V
LTC3110 Bidirectional Buck-Boost and PowerPath Manager for Supercapacitors ICHARGE = 2A, VIN: 0.1V to 5.5V, VOUT: 1.8V to 5.5V
LTC3643 Bidirectional Boost Charger/Buck Backup, Electrolytic Capacitors ICHARGE = 2A, VIN: 3V to 17V, VOUT: Up to 40V
LTC4040 Buck Battery Charger and Boost Backup for Li Batteries ICHARGE = 2.5A, VIN: 2.5V to 5.5V, VOUT: 3.5V to 5V
LTC3128 Buck-Boost Supercapacitor Charger ICHARGE = 3A, VIN: 1.7V to 5.5V, VOUT: 1.8V to 5.5V
LTC4425 Linear/Ideal Diode Supercapacitor Charger ICHARGE = 3A, VIN: 1.7V to 5.5V, VOUT: 2.7V to 5.5V
LTC4110 Bidirectional Buck-Boost Flyback Controller ICHARGE = 3A, VIN: 4.5V to 19V, VOUT: 2.7V to 19V
