XCCACE128-I - Xilinx, Inc.

DS080 (v1.4) January 3, 2002 www.xilinx.com 1

Advance Product Specification 1-800-255-7778

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

Features

• System-Level Features:

- High-capacity pre-engineered configuration

solution for FPGAs

- Chipset configuration solution:

·ACE™ Controller – Configuration manager

·ACE Flash – High-capacity CompactFlash™

storage device

- Non -volatile sy st em solu tion

- Fle xible configuration interfaces

- System configuration rates of up to 30 Mb/s

- Board space requirement as low as 25 cm2

•A CE Flash (Xilinx-supplied Flash Cards):

- Densities of 128 Mbits and 256 Mbits

- CompactFlash Type I form factor

- PC Card ATA protocol compatible

- Noiseless and low CMOS power

- A utoma tic error corre ction and write retry capabilitie s

- Multiple partitions

- Program/erase over full commercial/industrial

temperature range

- Removable storage device

- Excellent quality and reliability

·MTBF >1,000,000 hours

·Minimum 10,000 insertions

•ACE Controller:

- CompactFlash interface supports ACE Flash

cards, standard third-party CompactFlash (Type I

or Type II) cards, and IBM Microdrives with up to

8 Gbit capacity

- Configuration of a target FPGA chain through

IEEE 1149.1 JTAG with a throughput up to

16.7 Mbits/sec

- Interfaces include CompactFlash, JTAG, and MPU

- MPU interface is compatible with microprocessor/

microcontroller bus interfaces, such as the IBM

PPC405, and Siemens 80C166

- IEEE 1149.1 Boundary-Scan Standard Compliant

(JTAG)

- FAT12/16 file system

- Compact 144-pin TQFP package

-Low power

General Description

Xilinx devel oped th e Sys tem A dvanced Conf iguration Envi-

ronment (System ACE) family to address the need for a

space-efficient, pre-engineered, high-density configuration

solution for systems with multiple FPGAs. System ACE

technology is a ground-breaking in-system programmable

configuration solution that provides substantial savings in

development effort and cost per bit over traditional PROM

and embedded solutions for high-capacity FPGA systems.

The System ACE family combines Xilinx expertise in config-

uration control with industry expertise in commodity memo-

ries. The first member of the System ACE family uses

CompactFlash.

As shown in Figure 1, the System ACE CompactFlash solu-

tion is a chipset, consisting of a controller device (ACE Con-

troller) and a CompactFlash storage device (ACE Flash).

0System ACE

CompactFlash Solution

DS080 (v1.4 ) Januar y 3, 2002 00Advance Product Specification

Figure 1: System ACE Chipset

Interface to FPGA Target Chain

from CompactFlash, MPU,

or Test JTAG Port

ACE Flash

CompactFlash Storage Device

DS080_01_032101

128 Mbits or 256 Mbits

System ACE

Controller Device

System ACE CompactFlash Solution

2www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

Figure 2 shows that the ACE Controller contains multiple

interfaces, including CompactFlash, MPU, and JTAG, to

allow for a highly flexible configuration solution. For added

flexibility, a CompactFlash or IBM Microdriv e storage device

such as the Xilinx ACE Flash card can be used to store mul-

tiple bitstreams, with a capacity of up to 256 Mbits. The

combination of the ACE Controller and a standard Com-

pactFlash or IBM Microdrive storage device delivers a pow-

erful configuration solution for high-density FPGA systems.

ACE Flash Memory Card

The Xilinx ACE Flash memory card is a CompactFlash

solid-state storage device that complies with the Personal

Computer Memory Card International Association ATA

(PCMCIA ATA) specification. The ACE Flash card is avail-

able in two densities: 128 Mbits and 256 Mbits. This card

contains an on-card intelligent controller that manages

interface proto cols, data stora ge and retr ieval, ECC, defect

handling and diagnostics, power management, and clock

control.

Using commercially available, low-cost peripheral devices,

the ACE Flash card can be programmed independently in a

PC environment, in which the Flash card appears as an

additional hard drive. Besides these standard options, the

System ACE solution allows for in-system programming of

an ACE Flash ca rd through the ACE Controller MPU inter-

face.

The ACE Flash card also interfaces directly with the ACE

Controller to provide a powerful pre-engineered configura-

tion solution. See Figure 3.

Figure 2: ACE Controller Interfaces

MPU Interface

Boundary-Scan Test Tools

PC-Based Tools

Embedded

MPU

Automatic Test Equipment

FPGA

Target Chain

DS080_02_032201

Configuration JTAG

Interface (CFGJTAG)

Test JTAG Interface

(TSTJTAG)

CompactFlash

Interface

ACE Flash,

Third Party CompactFlash,

or IBM Microdrive

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 3

Advance Product Specification 1-800-255-7778

System ACE File Structure

The System ACE file structure setup allows ACE Flash

memory not used for configuration storage to be used as

scratchpad memory for other system storage needs. The

ability to store multiple bitstreams empowers designers to

use a single ACE Flash card to run BIST patterns, PCI

applications, or store multiple bitstream variations of a

design (for example, versions for different geographical

regions).

The file st ruct ure als o gives des ig ners the flexibilit y to st or e

supporting information with the bitstreams in addition to

configuration data, such as release notes, user guides,

FAQs, or other supporting files.

Figure 3: ACE Flash Card Block Diagram

DS080_03_032101

CompactFlash Internal

Single Chip Controller

Host

Interface

Data In/Out

CompactFlash

Modules

Control

Table 1: ACE Flash Card Capacity Specifications

Capacity (Bits)

Sectors/Card

(Max LBA+1) Number of

Heads Number of

Sectors/Tracks Number of

Cylinders

128,450,560 31,360 2 32 490

256,901,120 62,720 4 32 490

System ACE CompactFlash Solution

4www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

ACE Controller

The ACE Controller manages FPGA configuration data.

The controller provides an intelligent interface between an

FPGA target chain and various supported configuration

sources; it can target multiple FPGA de vices using JTAG at

a selectable throughput of up to 16.7 Mbits/sec. As shown in

Figure 4, thr ee in terfac e s ar e availabl e f o r con fi g uri n g a ta r -

get FPGA chain through the Configuration JTAG Port.

These interfaces are: CompactFlash, Microprocessor

(MPU), and Test JTAG.

The directory structure used by the ACE Controller enables

it to support both CompactFlash and IBM Microdrive

devices through the CompactFlash port.

The MPU interface has access to the CompactFlash por t,

the Configuration JTAG port, and local control/status fea-

tures. The Test JTAG port is used when doing Bound-

ary-Scan testing of the target FPGA chain or the ACE

Controller. Details about each interface are discussed

below.

The ACE Contro ller has two main power s uppli es: the c ore

power supply ( VCCL) and a Com pactFlash /Test J TAG inter-

face power supply (VCCH). The VCCH pow er source supplies

the Test JTAG and CompactFlash port levels. These two

interfaces must be powered at 3.3V. The V CCL core power

source supplies the MPU and Configuration JTAG ports,

which can be run at 3.3V or 2.5V. It is important to note that

these two interfaces are always powered at the same volt-

age. Considerat ions for the inter face voltage a re dis cusse d

in Typical Configuration Modes, page 35. See Figure 5.

Figure 4: System ACE Controller Block Diagram

DS080_04_030801

CompactFlash Port

MPU Port

Test JTAG (TSTJTAG) Port

Configuration JTAG (CFGJTAG) Port

Configuration

JTAG Controller

CompactFlash

Arbiter

MPU

Control

and

Status

CompactFlash

Controller Misc.

(LEDs,

etc.)

Test Scan

JTAG

Interface

(Target FPGA Chain)

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 5

Advance Product Specification 1-800-255-7778

Status Indicators

The ACE Controller has indicator pins to help monitor device status during operation.

Figure 5: ACE Controller I/O Requirements

DS080_05_030801

CompactFlash

CORE

CFGJTAG

MPU

TSTJTAG

LS LS LS LS

LS LS

Shaded output

buffers drive

VOH = VCCL =

2.5V or 3.3V

Shaded input

buffers sense

VIH = VCCL =

2.5V or 3.3V

All non-shaded

output buffers

drive VOH =

VCCH = 3.3V

All non-shaded

input buffers sense

VIH = VCCH = 3.3V

"LS" denotes

level-shifter

Core voltage level =

VCCL = 2.5V or 3.3V

Table 2: ACE Controller Status Indicators

Name Pin Description

STATLED 95 •When on, the Status LED indicates that configuration is DONE.

•When blinking, this LED indicates that configuration is still in progress.

•When off this LED indicates that configuration is in an IDLE state.

ERRLED 96

•When on, the ERROR LED indicates that an error occurred.

•When b linking, t his LED ind icates that no Co mpactFlash device was found when the CompactF lash

f or the C onfigura tion JTAG interface was enab led.

•When off, this LED indicates that no errors are detected.

System ACE CompactFlash Solution

6www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

System ACE RESET

Notes:

1. When using the System ACE Controller RESET, TSRESET + TWRESET of three rising edges of CLK is required.

Figure 6: System ACE RESET Function Timing Diagram

CYCLE

CLK

RESET

Cycle 0 Cycle 1 Cycle 2 Cycle 3

TSRESET

THRESET

TWRESET

ds080_56_071801

Table 3: System ACE RESET

Symbol Parameter Min Max Units

TW(R ES ET) System ACE Controller Res et puls e widt h 3(1) rising edges

TH(RESET) Reset hold time after rising edge of CLK 0 ns

TS(RESET) System ACE Controller Reset setup up time

before rising edge of CLK 7(1) ns

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 7

Advance Product Specification 1-800-255-7778

Interfaces Overview

This section discusses the details of each supported ACE

Controller interface.

CompactFlash Interface (CF)

The CompactFlash interface is the ke y A CE Controller inter-

f ace for high-capacity systems. The CompactFlash port can

accommo date Xili nx ACE Flash cards, any standard Com-

pactFlash module, or IBM Microdrives up to 8 Gbits, all with

the same form factor and board space requirements.

The use of standard CompactFlash devices gives system

designers access to high-density Flash in a very efficient

footprint that does not change with density. CompactFlash

is a removable medium, which makes changes and/or

upgrades to the memory contents or density simple.

The CompactFlash interface is comprised of two pieces: a

CompactFlash Controller, and a CompactFlash Arbiter. The

CompactFlash Controller detects the presence and main-

tains the status of the CompactFlash device. This Controller

also handles all CompactFlash device access bus cycles,

and abstracts and implements CompactFlash commands

such as soft reset, identify drive, and read/write sector(s).

The CompactFlash Arbiter controls the interface between

the MPU an d the Confi guration J TAG Controll er fo r acce ss

to the CompactFlash data buffer.

CompactFlash devices are compliant with multiple read and

write modes. The System ACE Configuration Controller

suppor ts ATA Common Memory Read and Write functions

specifically. Figure 7 and Figure 8 provide detailed timing

information on these functions.

Figure 7: ACE Flash ATA Memory Write Timing Diagram

DS080_09_031301

ADDRESS

REG

DIN

WAIT

TV(WT-WE)

(WT-WE)

DIN Valid

TV(WT)

(WT)

TSU

(A)

TSU

(CE)

TW(WE)

(WE)

TW(WT)

(WT)

TSU

(D - WEH)

TH(D)

(D)

TH(CE)

(CE)

TREC

REC

(WE)

Table 4: Common Memory Write Timing

Item Symbol IEEE Symbol Min (ns) Max (ns)

Data Setup before WE TSU(D-WEH) tDVWH 80

Data Hold followin g WE TH(D) tlWMDX 30

WE Pul se Width TW(WE) tWLWH 150

Address Setup Time TSU(A) tAVWL 30

CE Setup before WE TSU(CE) tELWL 0

Write Recovery Time TREC(WE) tWMAX 30

CE Hold following WE TH(CE) tGHEH 20

Wait Delay Falling from WE TV(WT-WE) tWLWTV 35

WE HIGH from Wait Release TV(WT) tWTHWH 0

Wait Width Time (Default Speed) TW(WT) tWTLWTH 350

System ACE CompactFlash Solution

8www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

Figure 8: ACE Flash ATA Memory Read Timing Diagram

DS080_10_031301

ADDRESS

REG

DOUT

WAIT

TV(WT-OE)

(WT-OE)

TV(WT)

(WT)

TSU

(A)

TSU

(CE)

TA(OE)

(OE)

TW(WT)

(WT)

TH(CE)

(CE)

TH(A)

(A)

TDIS

DIS

(OE)

Table 5: I/O Read Timing

Item Symbol IEEE Symbol Min (ns) Max (ns)

Data Delay after IORD TD(IORD) tlGLQV 100

Data Hold following IORD TH(IORD) tlGHQX 0

IORD Width Time TW(IORD) tlGLIGH 165

Address Setup before IORD TSU A(IORD) tAVIGL 70

Address Hold following IORD TH A(IORD) tlGHAX 20

CE Setup before IORD TSU CE(IORD) tELIGL 5

CE Hold following IORD TH CE(IORD) tlGHEH 20

REG Setup before IORD TSU REG(IORD) tRGLIGL 5

REG Hold following IORD TH REG(IORD) tlGHRGH 0

INPACK Delay Falling from IORD TDF INPACK(IORD) tlGLIAL 0 45

INPACK Delay Rising from IORD TDR INPACK(IORD) tlGHIAH 45

IOIS16 Delay Falling from Address TDF IOIS16(ADR) tAVISL 35

IOIS16 Delay Rising from Address TDR IOIS 16(ADR) tAVISH 35

Wait Delay Falling from IORD TD WT(IORD) tlGLWTL 35

Data Delay from Wait Rising TD(WT) tWTHQV 0

Wait Width Time (Default Speed) TW(WT) tWTLWTH 350

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 9

Advance Product Specification 1-800-255-7778

A basic understanding of the typical System ACE file and directory structure (shown in Figure 9) is useful when

programming an FPGA target system with a CompactFlash device in the System ACE solution.

The .ACE file is at the lowest lev el of the directory structure.

The Xilinx System ACE software converts a revision of a

design (bitstream) into an .ACE file. An .ACE file repr es ents

a single set of bitstreams for a particular chain of devices.

The next le vel up in the file structure is a collection. The col-

lection consists of eight .ACE files grouped together. All of

the .ACE files in a collection (directory) can be addressed

when in the System ACE environment. There can be sev-

eral collect ions stored on a Com pactFlash device, but only

one collection can be active at any given time.

The xilinx.sys file determines the collection from which

designs can be read.

The hierarchi cal desi gn of the Sy stem ACE directo r y str uc-

ture provides the ability to maintain multiple revisions or col-

lections of different designs in a single ACE Flash device.

Each collection director y can contain one or m ore designs

that reside in different subdirectories. Each design subdi-

rector y should contain a single .ACE file that represents a

single s et of bitstreams for a par ticular chai n of dev ices. In

addition to FPGA configuration information, the collection

and design subdirectories can contain other information

pertaining to the system design such as system software,

documentation, etc.

The xilinx.sys file in the root directory of the ACE Flash

device is used to control which of the designs within the

active colle ction is to be us ed to con figure th e chain o f tar-

get devices. Only one collection, containing up to eight

designs, can be active at one time.

The ACE Controller parses the xilinx.sys file to determine

the acti ve collection designs and uses the th ree config ura-

tion address pins or MPU register bits (CFGADDR) to select

the desired design. If no xilinx.sys file exists in the root

direct ory of the ACE Flash device, a singl e .ACE file in the

root directory is used by System ACE as the active design.

F ollowing are rules for the System ACE directory structure:

•System ACE configuration files must reside on the first

partition of the CompactFlash device.

•The System ACE partition must be f ormatted as FAT12

or FAT16.

•A xilinx.sys or single .ACE file must be in the root

(project) directory. An .ACE file is used only if the

xilinx.sys file cannot be found in this directory.

•Only one .ACE file should exist in the ROOT and/or

design directories. This directory structure allows the

Configuration controller to be able to use the .ACE file

to program the FPGA target system correctly.

Figure 9: System ACE Directory Structure

DS080_11_032101

dir = Rev_3;

cfgaddr0 = asia;

cfgaddr1 = europe;

cfgaddr3 = samerica;

cfgaddr4 = diag_1;

cfgaddr5 = diag_1;

cfgaddr6 = diag_2;

cfgaddr7 = diag_2;

xilinx.sys

Project Name - (root dir) "/"

*.ace *.ace *.ace

asia

(sub-dir)

europe

(sub-dir)

diag_2

(sub-dir)

Rev_3 (sub-dir)

Rev_2 (sub-dir)

Rev_1 (sub-dir)

CompactFlash

Available Collections

Collection Rev_3 Available Designs

for Target FPGA Chain

ACE System File

Containing Active Collection

(Up to 8 Designs)

System ACE CompactFlash Solution

10 www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

Microprocessor Inte rfac e (MPU )

The MPU Interface provides a useful means of monitoring

the status o f a nd c on t roll in g t he S y ste m ACE Contro ll er, as

well as ACE Flash card READ / WRITE data. The MPU is

not required for normal operation, but when used, it pro-

vides numerous capabilities. This interface enables commu-

nication between an MPU device and a CompactFlash

module and the FPGA target system.

The MPU interface is composed of a set of registers that

provide a means for communicating with CompactFlash

control logic, configuration control logic, and other

resources in the ACE Controller. Specifically, this interface

can be used to read the identi ty of a Comp actFlash device

and read/write sectors from or to a CompactFlash device.

The MPU interface can also be used to control configuration

flow . The MPU interf ace enables monitoring of ACE Control-

ler configuration status and error conditions. The MPU inter-

face can be used to delay configuration, start configuration,

determine the source of configuration (CompactFlash or

MPU), control the bitstream version, reset the de vice, etc.

Two important issues should be understood when using the

microprocessor port:

•For the controller to be properly synchronized, the MPU

must provide the clock.

•The MPU must comply with System ACE timing diagrams.

This genera l-purpos e microproces sor interface can update

the CompactFlash, read the ACE status or obtain direct

access to the JTAG configuration ports using the ACE

Microprocessor commands. This interface supports either

8-bit (def ault) or 16-bit data transfers. The bus width can be

configured dynamically.

All communications between the ACE Controller and a host

microp ro ce ss or involve transfer of data to or fr om ACE reg-

isters. There are 128 addressable registers in 8-bit mode

and 64 addressable registers in 16-bit mode. For easy

selection of a new configuration from CompactFlash data,

the MPU interface allows for easy reconfiguration of an

FPGA chain or capability.

The following sections describe supported operations when

using the MPU interface.

MPU Port Signal Description

MPU interf ace port signals are described in Table 6.

Table 6: MPU Interface Port Signal Description

Name Width Direction Active Description

MPA 7 In N/A Synchronous address inputs. The internal address register is loaded by MPA

by a combination of the rising edge of CLK and MPCE LOW.

MPD 16 In/Out N/A Synchronous data input/output pins. Both the data input and output path are

registered and triggered by the rising edge of CLK.

MPCE 1InLOW

Synchronous active LOW chip enab le. MPCE LOW is used to enable the

MPU interface. MPCE LOW is also used in conjunction with MPOE LO W to

enable the MPD output.

MPWE 1InLOW

Synchronous active LO W write enable. A high-to-low-to-high transition must

occur on MPWE in three consecutive clock cycles in order for the write to take

place.During a v alid write cycle , MPCE must be LO W and MPD must be v alid

during the clock cycle that MPWE.

MPOE 1InLOW

Asynchronous active LOW output enable. Both MPOE and MPCE must be

LOW to read from the MPU interf ace. When either MPOE or MPCE is HI GH,

the MPD pins of the ACE Controller are in a high-impedance state.

MPBRDY 1 Out HIGH

Synchronous active HIGH buff er ready output. During data buff er read mode

MPBRDY is HIGH when the data in the D ATABUF buff er is v alid. During data

buffer write mode MPBRDY is HIGH when data can be written to the

DATABUF buffer.

MPIRQ 1 Out HIGH

Synchronous active HIGH interrupt request output. MPIRQ HIGH indicates

that an interrupt condition has occurred in the MPU interface. All interrupt

conditions must be manually cleared before MPIRQ will go LOW. MPIRQ is

always LOW when interrupts are disabled.

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 11

Advance Product Specification 1-800-255-7778

MPU Timing Description

This section contains timing diagrams for the MPU interface. Parameters used in the timing diagrams are described in

Table 7.

Si ngle Register Read Cycle

The sin gle regi st er read cycl e is sh own in Figure 10. A si n-

gle register read is accomplished by asserting a valid

address (MPA), asserting the chip enable (MPCE = LOW)

and de-asser ting the write enable (MPWE = HIGH) during

the first clock cycle (Cycle 0). These signals should hold

these values at least until the rising edge of the f ourth clock

cycle (C yc le 3).

The output enable signal should be asserted (MPOE =

LOW) during the third clock cycle (Cycle 2). Register data

associ ate d wi th the spe ci fied address ap pear s on the MP D

bus two clock cycles after the falling edge of MP CE during

the assertion of MPCE. The r egist er re ad cycl e is th en com-

pleted by de-asserting the output enable during the fourth

clock cycle (Cycle 3).

Table 7: MPU Interface Timing Para meters

Symbol Parameter Min Max Units

tSA Address setup time 4 -- ns

tSCE Chip enable setup time 4 -- ns

tSWE Write enable setup time 12 -- ns

tSOE Output enable setup time 12 -- ns

tSD Data setup time 4 -- ns

tDD Clock HIGH to valid data -- 22 ns

tDOE Chip/Output enable LOW to valid data -- 13 ns

tDBRDY Clock HIGH to buffer ready valid -- 22 ns

tH Hold time 0 -- ns

Figure 10: Single Read From an ACE Register

40ns 60ns 80ns 100ns 120ns 140ns 160

CYCLE

CLK

MPA

MPD

MPCE

MPWE

MPOE

Cycle 0 Cycle 1 Cycle 2 Cycle 3 Cycle 4

ADDRESS

DATA

tSA

tSCE

tSWE

tDD

tDOE tDOE

tDOE

tSOE

tDD

DS080_14_013101

System ACE CompactFlash Solution

12 www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

Single Register Write Cycle

The sin gl e regi st er write cy c le is sh own in Figure 11. A sin-

gle register write is accomplished by asserting a valid

address (MPA), asserting the chip enable (MPCE = LOW)

and de-as serting the output enable (MPOE = HIGH) during

the first clock cycle (Cycle 0). These signals should hold

these values at least until the rising ed ge of the third clock

cycle (C yc le 2).

The write enable signal should be asserted (MPWE = LOW)

duri ng the second clock cycle ( Cycle 1). Data (M PD) to be

written to the specified address should be a sser ted during

the same clock cycle that the write enable is asserted

(Cycle 1). The register write cycle is then completed by

de-asserting the write enable during the third clock cycle

(Cycle 2).

Figure 11: Single WORD Write to an ACE Register

60ns 80ns 100ns 120ns 140ns 160

CYCLE

CLK

MPA

MPD

MPCE

MPWE

MPOE

Cycle 0 Cycle 1 Cycle 2 Cycle 3

ADDRESS

DATA

tSA

tSCE tH

tSWE tSWE

tSD

tSOE

DS080_15_013101

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 13

Advance Product Specification 1-800-255-7778

Multiple Register Read Timing

The minimum timing requirements for sequential register read cycles are shown in Figure 12. Sequential read cycles are

identical to single read cycles, except that the chip enable (MPCE) and write enable (MPWE) signals do not need to be

de-asserted between read cycles.

Figure 12: Multiple WORD Reads From ACE Register(s)

50ns 100ns 150ns 200ns 250

CYCLE

CLK

MPA

MPD

MPCE

MPWE

MPOE

Cycle 0 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7

ADDRESS <0> ADDRESS <1>

DATA <0> DATA <1>

tSA

tSCE

tSWE

tDD

tDOE tDOE

tDOE

tSOE

tSA

tDOE tDOE

tSOE

tDOE

tSOE

tDDtDD tDD

DS080_16_013101

System ACE CompactFlash Solution

14 www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

Multiple Register Write Timing

The minimum timing requirements for sequential write

cycles are shown in Figure 13. Seq uential wr ite cycl es are

identical to single write cycles except that the chip enable

(MPCE) and outp ut enable (MPOE) signals do not ne ed to

be de-asserted between write cycles.

Data Buffer Ready Timing

The data buffer ready (MPBRDY) signal indicates whether

the data buffer is ready to accept new data during a write

cycle or whether the data buffer contains valid data to be

read during a read cycle. The data buffer itself is sixteen

words deep, where each word is 16 bits wide.

The data buffer mode transfer direction is identified by the

state of the DATABUFMODE bit in the STATUSREG regis-

ter:

•DATABUFMODE = 0 indicates data buffer read mode

•DATABUFMODE = 1 indicates data buffer write mode

The data buff er mode depends on the type of command that

was issued to the ACE Controller. If an IdentifyMemCard or

ReadMemCar d comm and was issu ed, then th e data buffer

remains in read mode until the command is finished ex ecut-

ing (i.e., all sector data ha s been read from the buffer). If a

Wri teMemCard c ommand was issued, th en the data buffer

remains in write mode until the command is finished ex ecut-

ing (i.e., all sector data has been written to the buffer).

Figure 13: Multiple WORD Writes to ACE Register(s)

60ns 80ns 100ns 120ns 140ns 160ns 180ns 200ns 22

CYCLE

CLK

MPA

MPD

MPCE

MPWE

MPOE

Cycle 0 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5

ADDRESS <0> ADDRESS <1>

DATA <0> DATA <1>

tSA

tSCE tH

tSWE tSWE

tSD

tSOE

tSA

tSD

tH tH

tSWE tSWE

DS080_17_020101

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 15

Advance Product Specification 1-800-255-7778

Data Buffer Read Cycle Ready Timing

When the data buffer is in read mode and the last data word

is read from the buffer, the data buffer ready signal will go

inactive (MPBRDY = LOW) two clock cycles following the

last clock cycle that the output enable is active (MPOE =

LOW). Any attempt to read data out of an “empty” data

buffer (MPOE = LOW while MPBRDY = LOW) results in

inv alid data. V alid and inv alid data buffer reads are shown in

Figure 14.

Figure 14: Valid and Invalid Reads From DATABUFREG Data Buffer

50ns 100ns 150ns 200ns 250

CYCLE

CLK

MPA

MPD

MPCE

MPWE

MPOE

MPBRDY

Cycle 0 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7

DATABUFREG ADDRESS DATABUFREG ADDRESS

VALID DATA INVALID DATA

tSA

tSCE

tSWE

tDD

tDOE tDOE

tDOE

tSOE

tSA

tDOE tDOE

tSOE

tDOE

tSOE

tDDtDD tDD

tDBRDY

DS080_18_020101

System ACE CompactFlash Solution

16 www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

Data Buffer Read Cycle Ready Timing

When the data buff er is in write mode and the last available

space for a data word has been fil led, the data buffer ready

signal will go inactive (MPBRDY = LOW) two clock cycles

following the last clock cycle that the wr ite enable is active

(MPWE = LOW). Any attempt to write data to a “full” data

buffer (MPWE = LOW while MPBRDY = LOW) does not

result in a successful write to the buffer. Valid and invalid

data buffer writes are shown in Figure 15.

Figure 15: Valid and In valid Writes to DATABUFREG Data Buffer

60ns 80ns 100ns 120ns 140ns 160ns 180ns 200ns 22

CYCLE

CLK

MPA

MPD

MPCE

MPWE

MPOE

MPBRDY

Cycle 0 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5

DATABUFREG ADDRESS DATABUFREG ADDRESS

VALID DATA INVALID DATA

tSA

tSCE tH

tSWE tSWE

tSD

tSOE

tSA

tSD

tH tH

tSWE tSWE

tBRDY

DS080_19_020101

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 17

Advance Product Specification 1-800-255-7778

Interrupt Timing

The interrupt request and clearing cycles are shown in

Figure 16. In Figure 16, the interrupt request (MPIRQ =

HIGH) occurs sometime before Cycle 0. The interrupt

request is cleared by performing a single MPU write cycle

that sets RESETIRQ = 1 (bit number 11) in the CONTROL-

REG(15:0) register (BYTE address 0x19 or WORD address

0x0C).

The MPU interrupt request line (MPIRQ) remains active

HIGH until the RESETIRQ bit is set. The MPIRQ line

becomes inactive LOW two cycles after the completion of

the RESE T IRQ write cyc le ( Cyc l e 4 ). For subsequent MP U

interrupt requests to be enabled, the RESETIRQ bit must be

reset and one of the three IRQ enable bits (DATABU-

FRDYIRQ, ERRORIRQ, and/or CFGDONEIRQ) in the

CONTROLREG register should be set.

Figure 16: Interrupt Request Timing

0ns 50ns 100ns 150ns

CYCLE

CLK

MPA

MPD

MPCE

MPWE

MPOE

MPIRQ

Cycle 0 Cycle 1 Cycle 2 Cycle 3 Cycle 4

CONTROLREG(15:0) ADDRESS

0800h

tSA

tSCE tH

tSWE tSWE

tSD

tSOE

tDIRQ tDIRQ

DS080_44_030501

System ACE CompactFlash Solution

18 www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

Reg ister Spec i f i c ation

The BYTE-mode register space of the MPU interface is shown in Table 8.

Table 8: Register Address Map (BYTE Mode Addresses)

BYTE Address

(MPA [6:0]) Register Name Width Mode Description

0x00 BUSMOD ER EG 1 RW Used to control the data bus access mode (8-bi t

BYTE mode or 16-bit WORD mode)

0x01 BUSMODEREG 1 RW

0x02 -- -- -- Reserved

0x03 -- -- -- Reserved

0x04 STATUSREG(7:0) 8 R Used to monitor ACE Con troller status

0x05 STATUSREG(15:8) 8 R

0x06 STATUSREG(23:16) 8 R

0x07 STATUSREG(31:24) 8 R

0x08 ERRORREG(7:0) 8 R Used to indicate any existing error condition

0x09 ERRORREG(15:8) 8 R

0x0A ERRORREG(23:16) 8 R

0x0B ERRORREG(31:24) 8 R

0x0C CFGLBAREG(7:0) 8 R Logical block address used by the Configuration

Controller during CompactFlash data transfers

0x0D CFGLBAREG(15:8) 8 R

0x0E CFGLBAREG(23:16) 8 R

0x0F CFGLBAREG(27:24) 4 R

0x10 MPULBAREG(7:0) 8 RW Logical block address used by the MPU interface

during CompactFlash data transfers

0x11 MPULBAREG(15:8) 8 RW

0x12 MPULBAREG(23:16) 8 RW

0x13 MPULBAREG(27:24) 4 RW

0x14 SECCNTCMDREG(7:0) 8 RW Sector count and CompactFlash command

0x15 SECCNTCMDREG(15:8) 8 RW

0x16 VERSIONREG(7:0) 8 R Version register

0x17 VERSIONREG(15:8) 8 R

0x18 CONTROLRE G(7 :0) 8 RW Used to control ACE Controller operations

0x19 CONTROLREG(15:8) 8 RW

0x1A CONTROLREG(23:16) 8 RW

0x1B CONTROLREG(31:24) 8 RW

0x1C F A TSTA TREG(7:0) 8 R Contains information about the FA T table of the first

valid partition found in the CompactFlash device.

0x1D FATSTATREG(15:8) 8 R

0x1E through 0x3F -- -- -- Reserved

Even Values

0x40 through 0x7E DATABUFREG(7:0) 8 R W Address range that provides read and write access

to the data buffer.

Odd Values

0x41 through 0x7F DATABUFREG(15:8) 8 RW

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 19

Advance Product Specification 1-800-255-7778

The 16-bit WORD mode register space of the MPU interface is shown in Table 9.

Table 9: Register Address Map (WORD Mode Addresses)

WORD

Address

(MPA [6:1]) Register Name Width Mode Description

0x00 BUSMODEREG 1 RW Used to control the data bus access mode (8-bit BYTE

mode or 16-bit WORD mode)

0x01 -- -- -- Reserved

0x02 STATUSREG(15:0) 16 R Used to monitor ACE Controller status

0x03 STATUSREG(31:16) 16 R

0x04 ERRORREG(15:0) 16 R Used to indicate any existing error condition

0x05 ERRORREG(31:16) 16 R

0x06 CFGLBAREG(15:0) 16 R Logical block address used by the Configuration

Controller dur i ng Comp ac tFlas h data transfers

0x07 CFGLBAREG(27:16) 12 R

0x08 MPULBAREG(15:0) 16 RW Logical block address used by the MPU interf ace during

CompactFlas h data transfers

0x09 MPULBAREG(27:16) 12 RW

0x0A SECCNTCMDREG(15:0) 16 RW Sector count and CompactFlash command register

0x0B VERSIONREG( 15:0) 16 R Version register

0x0C CONTROLREG(15:0) 16 RW Used to control ACE Controller operations

0x0D CONTROLREG(31:16) 16 RW

0x0E F ATSTATREG(15:0) 16 R Contains information about the F AT table of the first valid

partition found in the CompactFlash device.

0x0F through

0x1F -- -- -- Reserved

0x20 through

0x3F DA TABUFREG(15:0) 16 RW Address range that provides read and write access to the

data buffer.

System ACE CompactFlash Solution

20 www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

BUSMODEREG Register (BYTE address 00h-01h, WORD address 00h)

The BUSMODEREG register is used to control the mode of the MPU address and data bus. The single-bit BUSMODEREG

ensures th at the MP U bus mode ca n be set regardless of the mod e of the microproc essor that is communic ating wit h the

ACE Controller. Table 10 provides a description of the BUSMODEREG register bits.

STATUSREG Register (BYTE address 04h-07h, WORD address 02h-03h)

The STATUSREG register allows a microproces sor to mon itor impor tant AC E Controll er operating mo des. This is als o the

registe r that is rea d upon rece ivin g an IRQ reques t in o rder to identi fy an inter rupt sour ce. Table 11 provides a description

of the STATUSREG register bits.

Table 10: BUSMODEREG Register Bit Descriptions

Bit Name Description

0 BUSMODE0 The BUSMODE bits are used to select the width of the data bus portion of the

Microprocessor/MultiLIN X bus (default is 0):

•When 0, the MPU interf ace is in BYTE mode (all MPU address bits are used, but only

MPU data bits 7:0 are used).

•When 1, the MPU interface is in WORD mode (all MPU data bits are used, but only

MPU address bits 6:1 are used).

1 -- Reserved

2 -- Reserved

3 -- Reserved

4 -- Reserved

5 -- Reserved

6 -- Reserved

7 -- Reserved

Table 11: STATUSREG Register Bit Descriptions

Bit Name Description

0 CFGLOCK Configuration controller lock status:

•0 means that the configuration controller does not currently have a lock on the

CompactFlash controller resource

•1 means that the configuration controller has successfully locked the CompactFlash

controller resource

1 MPULOCK MPU interface lock status:

•0 means that the MPU interface does not currently have a lock on the CompactFlash

controller resource

•1 means that the MPU interface has successfully locked the CompactFlash controller

resource

2 CFGERROR Configuration Controller error status:

•0 means that no Configuration Controller error condition exists

•1 means that an error has occurred in the Configuration Controller (check the

ERRORREG register for more information)

3 CFCERROR CompactFlash Controller error status:

•0 means that no CompactFlash Controller error condition exists

•1 means that an error has occurred in the CompactFlash controller (check the

ERRORREG register for more information)

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 21

Advance Product Specification 1-800-255-7778

4 CFDETECT CompactFlash detect flag:

•0 means that no CompactFlash device is connected to the ACE Controller

•1 means that a CompactFlash is connected to the ACE Controller

5 DATABUFRDY Data buffer ready status:

•0 means that the data buffer is not ready for data transf er

•1 means that the data buffer is ready for data to be transferred out of the buffer when

reading from the CompactFlash controller or into the buffer when writing to the

CompactFlash or Configuration controller

6 DATABUFMODE Data buffer mode status:

•0 means read-only mode

•1 means write-only mode

7 CFGDONE Configuration DONE status:

•0 means that the configuration process has not completed

•1 means that the entire ACE Controller configuration file has been executed and

configuration of all devices in the target Boundary-Scan chain is complete

8 RDYFORCFCMD Ready for CompactFlash controller command:

•0 means not ready for command

•1 means ready for command

9 CFGMODEPIN Configuration mode pin (note that this can be overridden by the CFGMODE bit in the

CONTROLREG register):

•1 means automatically start the configuration process immediately after ACE

Controller Reset

•0 means wait for CFGSTART bit in CONTROLREG before starting the configuration

process

10 -- Reserved

11 -- Reserved

12 -- Reserved

13 CFGADDRPIN0 Configuration address pins that are used as an offset into the system configuration file in

the CompactFlash device used to locate the ACE Controller configuration data file (note

that these pins can be overridden by the contents of the CFGADDRBIT[2:0] of the

CONTROLREG register)

14 CFGADDRPIN1

15 CFGADDRPIN2

16 -- Reserved

17 CFBSY CompactFlash BUSY bit (reflects the state of the BSY bit in the status register of the

CompactFlash device):

•0 means that the CompactFlash device is not busy

•1 means that the CompactFlash command register and data buffer cannot be

accessed; Bits 1-6 of the STATUSREG register are not valid when this bit is set

18 CFRD Y CompactFlash ready for operation bit (reflects the state of the RD Y bit in the status register

of the CompactFlash device):

•0 means the CompactFlash device is NOT ready to accept commands

•1 means CompactFlash device is ready to accept commands

19 CFDWF CompactFlash data write fault bit (reflects the state of the DWF bit in the status register of

the CompactFlash device):

•0 means that a write fault has NOT occurred

•1 means that a write fault has occurred

Table 11: STATUSREG Register Bit Descriptions (Continued)

Bit Name Description

System ACE CompactFlash Solution

22 www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

ERRORREG Register (BYTE address 08h-0Bh, WORD address 04h-05h)

The ERRORREG register identifies specific information on any error conditions that might exist in the ACE Controller.

Table 12 provides a description of the ERRORREG register bits.

20 CFDSC CompactFlash ready bit (reflects the state of the DSC bit in the status register of the

CompactFlash device):

•0 means that the CompactFlash device is NOT ready

•1 means that the CompactFlash device is ready

21 CFDRQ CompactFlash data request bit (reflects the state of the DRQ bit in the status register of

the CompactFlash device):

•0 means that no data is ready to be transferred to/from the data buffer of the

CompactFlash device

•1 means that information be transferred to/from the data buffer of the CompactFlash

device

22 CFCORR CompactFlash correctable error bit (reflects the state of the CORR bit in the status register

of the CompactFlash device):

•0 means that a correctable data error was NOT encountered

•1 means that a correctable data error was encountered (check the ERRORREG

23 CFERR CompactFlash ERROR bit (reflects the state of the ERR bit in the status register of the

CompactFlash device):

•0 means that no error has occurred during the execution of the previous command

•1 means that the previous command has ended in some type of error (check the

ERRORREG register for more information)

24 -- Reserved

25 -- Reserved

26 -- Reserved

27 -- Reserved

28 -- Reserved

29 -- Reserved

30 -- Reserved

31 -- Reserved

Table 12: ERRORREG Register Bit Descriptions

Bit Name Description

0 CARDRESETERR CompactFlash card reset error:

•0 means no error

•1 means that the CompactFlash card has failed to reset properly before a time-out

conditi on oc cu rred

1 CARDRDYERR CompactFlash card ready error:

•0 means no error

•1 means that the CompactFlash card has failed to become properly ready for

commands before a time-out condition occurred

2 CARDREADERR CompactFlash card read error:

•0 means no error

•1 means that a CompactFlash data read command (either ReadMemCardData or

IdentifyMemCard) has failed

Table 11: STATUSREG Register Bit Descriptions (Continued)

Bit Name Description

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 23

Advance Product Specification 1-800-255-7778

3 CARDWRITEERR CompactFlash card write error:

•0 means no error

•1 means that a CompactFlash data write command (WriteMemCardData) has failed

4 SECTORRDYERR CompactFlash sector ready:

•0 means no error

•1 means that a sector has failed to become properly valid during a CompactFlash read

or write command before a time-out condition occurred

5 CFGADDRERR CFGADDR error:

•0 means no error

•1 means that the CFGADDR (i.e., the CFGADDR(15:0) register or CFGADDR(1:0)

pins, depending on the state of the FORCECFGADDR bit in the CONTROLREG

6 CFGFAILED Configuration failure error:

•0 means no error

•1 means that configuration of one or more devices in the target Boundary-Scan chain has

failed

7 CFGREADERR Configuration read error:

•0 means no error

•1 means that an error oc curr ed while readi ng con fig urati on inform ation fro m

CompactFlash

8 CFGINSTRERR Configuration instruction error:

•0 means no error

•1 means that an invalid instruction was encountered during configuration

9 CFGINITERR Configuration INIT monitor error:

•0 means no error

•1 means that the CFGINIT pin did not go HIGH within 500 ms of the start of

configuration

10 -- Reserved

11 CFBBK CompactFlash bad b lock error (reflects the state of the BBK bit in the error register of the

CompactFlash device):

•0 means no error

•1 means that a bad block has been detected

12 CFUNC CompactFlash uncorrectable error (reflects the state of the UNC bit in the error register of

the CompactFlash device):

•0 means no error

•1 means that an uncorr ec table error has been enc oun tered

13 CFIDNF CompactFlash ID not found error (reflects the state of the IDNF bit in the error register of

the CompactFlash device):

•0 means no error

•1 means that the requested sector ID is in error or cannot be found

14 CF ABORT CompactFlash command abort error (reflects the state of the ABRT bit in the error register

of the CompactFlash device):

•0 means no error

•1 means that the command has been aborted because of a CompactFlash status

condition (i.e., Not Ready, Write Fault) or when an invalid command has been issued

Table 12: ERRORREG Register Bit Descriptions (Continued)

Bit Name Description

System ACE CompactFlash Solution

24 www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

15 CFAMNF CompactFlash general error (reflects the state of the AMNF bit in the error register of the

CompactFlash device):

•0 means no error

•1 means that a general error has occurred

16 -- Reserved

17 -- Reserved

18 -- Reserved

19 -- Reserved

20 -- Reserved

21 -- Reserved

22 -- Reserved

23 -- Reserved

24 -- Reserved

25 -- Reserved

26 -- Reserved

27 -- Reserved

28 -- Reserved

29 -- Reserved

30 -- Reserved

31 -- Reserved

Table 12: ERRORREG Register Bit Descriptions (Continued)

Bit Name Description

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 25

Advance Product Specification 1-800-255-7778

CFGLBAREG Register (BYTE address 0Ch-0Fh, WORD address 06h-07h)

The CFGLBAREG read-only register contains the logical block address used by the ACE Controller configuration logic

duri ng CompactFlash read/wr ite operations. The CFGL BAREG register affects only transfers between the ACE Controller

configuration logic and the CompactFlash card. The MPU uses a separate set of registers (MPULBAREG(27:0)) to transfer

data to and from the CompactFlash card. Table 13 provides a description of the CFGLBAREG register bits.

Table 13: CFGLBAREG Register Bit Descriptions

Bit Name Description

0 CFGLBA00 Logical Block Address used during CompactFlash read or write sector commands: each

block address points to a sector location which is made up of 512 bytes (i.e., maximum

CompactFlash device capacity is up to 128 gigabytes, or 137,438,953,472 bytes)

1CFGLBA01

2CFGLBA02

3CFGLBA03

4CFGLBA04

5CFGLBA05

6CFGLBA06

7CFGLBA07

8CFGLBA08

9CFGLBA09

10 CFGLBA10

11 CFGLBA11

12 CFGLBA12

13 CFGLBA13

14 CFGLBA14

15 CFGLBA15

16 CFGLBA16

17 CFGLBA17

18 CFGLBA18

19 CFGLBA19

20 CFGLBA20

21 CFGLBA21

22 CFGLBA22

23 CFGLBA23

24 CFGLBA24

25 CFGLBA25

26 CFGLBA26

27 CFGLBA27

28 -- Reserved

29 -- Reserved

30 -- Reserved

31 -- Reserved

System ACE CompactFlash Solution

26 www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

MPULBAREG Register (BYTE address 10h-13h, WORD address 08h-09h)

The MPULBAREG read-write register contains the logical block address that is used by the MPU interface during

CompactF la sh read /write operations. The MP ULB A REG reg is ter affects o nly trans fers between t he MPU in ter face and th e

CompactF lash card. ACE Cont roller con figuration logi c mainta ins a separate s et of register s (CFGLBA REG(27 :0)) for use

when transferring data to and from the CompactFlash card. Table 14 provides a description of MPULBAREG register bits.

Table 14: MPULBAREG Register Bit Descriptions

Bit Name Description

0 MPULBA00 Logical Block Address used during CompactFlash read or write sector commands: each

block address points to a sector location which is made up of 512 bytes (i.e., maximum

CompactFlash device capacity is up to 128 gigabytes, or 137,438,953,472 bytes)

1MPULBA01

2MPULBA02

3MPULBA03

4MPULBA04

5MPULBA05

6MPULBA06

7MPULBA07

8MPULBA08

9MPULBA09

10 MPULBA10

11 MPULBA11

12 MPULBA12

13 MPULBA13

14 MPULBA14

15 MPULBA15

16 MPULBA16

17 MPULBA17

18 MPULBA18

19 MPULBA19

20 MPULBA20

21 MPULBA21

22 MPULBA22

23 MPULBA23

24 MPULBA24

25 MPULBA25

26 MPULBA26

27 MPULBA27

28 -- Reserved

29 -- Reserved

30 -- Reserved

31 -- Reserved

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 27

Advance Product Specification 1-800-255-7778

SECCNTCMDREG Register (BYTE address 014h-15h, WORD address 0Ah)

The SECCNT CMDREG re gister p rovides the mea ns for an

MPU interface to set the sector count and execute Com-

pactFlash Controller commands. Table 15 provides a

description of the SECCNTCMDREG register bits.

The SECCNT bits of the SECCNTCMDREG regi ster spec-

ify the number of sectors to transfer during each ReadMem-

CardData or WriteMemCardData command:

•A SECCNT value of 1 to 255 indicates to the

CompactFlash device that 1 to 255 sectors should be

transferred.

•A SECCNT v alue of 0 indicates that 256 sectors should

be transferred.

The CMD bits of the SECCNTCMDREG register identify a

specific command to be executed:

•If the MPU has NOT successfully locked access to the

CompactFlash Controller, then writes to the CMD bits

of the SECCNTCMDREG register do not change the

valu e of the regis te r.

•If the MPU has successfully locked access to the

CompactFlash Controller and a non-zero value is

written to the CMD bits of the SECCNTCMDREG

the CompactFlash Controller.

•If the MPU has successfully lock ed access to the

CompactFlash Controller and a zero value is written to

the CMD bits of the SECCNTCMDREG register , there is

no eff ect on the value of the CMD bits. The only way to

clear the CMD bits is to issue the cfAbort command,

whic h abo rts the curr ent ly ex ec ut ing co mm an d an d

waits until the CompactFlash Controller clears the CMD

bits.

Table 15: SECCNTCMDREG Register Bit Descriptions

Bit Name Description

0 SECCNT0 Sector Count used during CompactFlash read or write sector commands: each sector is

made up of 512 bytes

1 SECCNT1

2 SECCNT2

3 SECCNT3

4 SECCNT4

5 SECCNT5

6 SECCNT6

7 SECCNT7

8 CMD0 Command value:

0x0 : Reserved

0x1 : ResetMemCard command

0x2 : IdentifyMemCard command

0x3 : ReadMemCardData command

0x4 : WriteMemCardData command

0x5: Reserved

0x6 : Abort command

0x7 : Reserved

9CMD1

10 CMD2

11 -- Reserved

12 -- Reserved

13 -- Reserved

14 -- Reserved

15 -- Reserved

System ACE CompactFlash Solution

28 www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

VERSIONREG Register (BYTE address 16h-17h, WORD address 0Bh)

The VERSIONREG register holds the ACE Controller version number in the form of a 4-bit major version field, a 4-bit minor

version field, and an 8-bit revision/build number field. Table 16 provides a description of the VERSIONREG register bits.

Table 16: VERSIONREG Register Bit Descriptions

Bit Name Description

0 VERSION0 Rev ision / build number: MSB is bit 7, LSB is bit 0

1 VERSION1

2 VERSION2

3 VERSION3

4 VERSION4

5 VERSION5

6 VERSION6

7 VERSION7

8 VERSION8 Minor version number: MSB is bit 11, LSB is bit 8

9 VERSION9

10 VERSION10

11 VERSION11

12 VERSION12 Major version number: MSB is bit 15, LSB is bit 12

13 VERSION13

14 VERSION14

15 VERSION15

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 29

Advance Product Specification 1-800-255-7778

CONTROLREG Register (BYTE address 18h-1Bh, WORD address 0Ch-0Dh)

The CONTROLREG register provides the means for the MPU interface to control ACE Controller functionality. Table 17

provides a description of the CONTROLREG register bits.

Table 17: CONTROLREG Register Bit Descriptions

Bit Name Description

0 FORCELOCKREQ Forces the CompactFlash arbitration logic to grant a loc k to the MPU interface based on

the value of the LOCKREQ bit of the CONTROLREG register (default is 0):

•0 means do not force MPU lock request (i.e., arbitrate between Configuration

Controller and MPU interface)

•1 means force MPU lock request (i.e., do not perform arbitration: grant lock request

based only on MPU requests)

1 LOCKREQ CF arbitration l ock request signal; Once a lock is granted, the LOCKREQ must be

de-asserted before the lock is removed (default is 0):

•0 means do not request Com pactFlash access lock

•1 means request CompactFlash access lock

2 FORCECFGADDR Forces the ov erriding of the CFGADDR(1:0) pins in f av or of using the CFGADDRBIT(2:0)

bits of the CONTROLREG(15:13) register (default is 0):

•0 means use the CFGADDR(1:0) pins

•1 means use the CONTROLREG(15:13) register bits

3 FORCECFGMODE Forces the overriding of CFGMODEPIN in favor of using the CFGMODE bit of the

CONTROLREG register (default is 0):

•0 means use CFGMODEPIN

•1 means use the CFGMODE bit of the CONTROLREG register

4 CFGMODE Configuration mode (def ault is 0):

•1 means automatically start the configuration process immediately after ACE Controller

Reset

•0 means wa it f or CF GSTAR T bit in CON TR OLRE G bef ore sta rting the con figur ation

process

5 CFGSTART Configuration start bit (default is 0):

•0 means do not start configuration

•1 means start configuration process

6 CFGSEL Configuration select (default is 0):

•0 means configure from CompactFlash

•1 means configure from MPU interface

7 CFGRESET Configuration/CompactFlash controller reset (default is 0):

•0 means do not reset

•1 means reset the Configuration and CompactFlash controllers (this also causes a

“soft-reset” of the CompactFlash device)

8 DATABUFRDYIRQ Data buffer ready IRQ enable (default is 0):

•1 means interrupts are enabled for when data buff er is ready for transfer of data into or

out of the buffer

•0 means data buffer ready interrupts are disabled

9 ERRORIRQ Error IRQ enable (default is 0):

•1 means interrupts are enabled for when an error occurs

•0 means error interrupts are disabled

System ACE CompactFlash Solution

30 www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

10 CFGDONEIRQ Configuration DONE IRQ enable (default is 0):

•1 means interrupts are enabled for when configuration is DONE

•0 means configuration DONE interrupts are disabled

11 RESETIRQ Resets the interrupt request line when a ’1’ is written to this register bit. Note that a ’0’ must

be written to this register bit in order to re-arm for subsequent interrupt conditions.

12 CFGPROG Inverted ACE Controller CFGPROG pin control (default is 0):

•0 means set the CFGPROG pin to its inactive HIGH state of 1

•1 means set the CFGPROG pin to its active LOW state of 0

13 CFGADDRBIT0 Configuration address register bits that are used as an offset into the system configuration

file in the CompactFlash device used to locate the ACE Controller configuration data file

(note that these register bits can be used to ov erride the CFGADDR[2:0] pins of the A CE

Controller)

14 CFGADDRBIT1

15 CFGADDRBIT2

16 CFGRSVD0 Reserved for future use. These bits must be set to zero at all times.

17 CFGRSVD1

18 CFGRSVD2

19 -- Reserved

20 -- Reserved

21 -- Reserved

22 -- Reserved

23 -- Reserved

24 -- Reserved

25 -- Reserved

26 -- Reserved

27 -- Reserved

28 -- Reserved

29 -- Reserved

30 -- Reserved

31 -- Reserved

Table 17: CONTROLREG Register Bit Descriptions (Continued)

Bit Name Description

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 31

Advance Product Specification 1-800-255-7778

FATSTATREG Register (BYTE address 1Ch-1Dh, WORD address 0Eh)

The FATS TATRE G regi s ter c ont ains information abou t th e f ir st valid partitio n o f th e Compact Flas h device s uc h a s the boot

record and FAT types found. Table 18 provides a description of the FATSTATREG register bits.

Table 18: FATSTATREG Register Bit Descriptions

Bit Name Description

0 MBR VALID Master boot record (MBR) valid flag:

•0 means no MBR was detected

•1 means a valid MBR was found

1 PBRVALID Partition boot record (PBR) valid flag:

•0 means no PBR was detected

•1 means a valid PBR was found

2 MBRFAT12 Master boot record (MBR) FAT12 flag:

•0 means FAT12 flag is not set in MBR

•1 means FAT12 flag is set in MBR

3 PBRFAT12 Partitio n b oot record (PB R) FAT12 flag:

•0 means FAT12 flag is not set in PBR

•1 means FAT12 flag is set in PBR

4 MBRFAT16 Master boot record (MBR) FAT16 flag:

•0 means FAT16 flag is not set in MBR

•1 means FAT16 flag is set in MBR

5 PBRFAT16 Partitio n b oot record (PB R) FAT16 flag:

•0 means FAT16 flag is not set in PBR

•1 means FAT16 flag is set in PBR

6 CALCFAT12 Calculated FAT12 flag (based on cluster count):

•0 means not FAT12 (cluster count > 4085)

•1 means FAT12 (cluster count < 4085)

7 CALCFAT16 Calculated FAT12 flag (based on cluster count):

•0 means not FAT16 (cluster count > 65525)

•1 means FAT16 (4085 < cluster count < 65535)

8 -- Reserved

9 -- Reserved

10 -- Reserved

11 -- Reserved

12 -- Reserved

13 -- Reserved

14 -- Reserved

15 -- Reserved

System ACE CompactFlash Solution

32 www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

DATABUFREG Register (BYTE address 40h-7Fh, WORD address 20h-3Fh)

The DATA BUFREG register is the porta l registe r to the data buffer that is used to transfer data between the MPU interface

and the CompactFlash and/or Configuration controllers. The description of the DATABUFREG register bits are shown in

Table 19.

Test JTAG Interface (TSTJTAG)

The Test JTAG Interface (TSTJTAG) supports 1149.1

Boundary-Scan operations on the ACE Controller and all

chained FPGA devices connected to the Configuration

JTAG (CFGJTAG) port. This interface can also be used to

program the target FPGA chain on the CFGJTAG port,

using Xilinx or third-party JTAG programming tools.

The ACE Controller is fully com pliant with the IEEE 1149.1

Boundary-Scan standard, commonly referred to as JTAG.

As shown in Figure 17, a Test Access P ort (TAP), ins truction

decoder, and the required IEEE 1149.1 Registers are

included in the ACE Controller to support the mandatory

Boundary-Scan ins tructi on s. In additio n, the Cont roll er also

supports an optional 32-bit identification register. Refer to

the 1149.1 Boundary-Scan standard specification for a

complete description of the required instructions and

detailed information on JTAG.

Table 19: DATABUFREG Register Bit Descriptions

Bit Name Description

0 DATA00 Data buffer portal register:

•Data register bits are read-only when the DATABUFMODE bit in the STATUSREG

•DATABUFREG(07:00) are accessible in BYTE and WORD bus modes.

1DATA01

2DATA02

3DATA03

4DATA04

5DATA05

6DATA06

7DATA07

8 DATA08 Data register:

•Data register bits are read-only when the DATABUFMODE bit in the STATUSREG

•DATABUFREG(15:08) are accessible in BYTE and WORD bus modes.

•During BYTE bus write mode, if the data buffer is ready, any writes to the

DATABUFREG(15:08) bits cause the DATABUFREG(15:00) contents to be written to

the data buffer.

•During BYTE bus read mode, if the data buffer is ready, the DATABUFREG(15:00)

DATABUFREG(15:08) is read, the DATABUFREG(15:00) register is loaded with any

pending new data.

9DATA09

10 DATA10

11 DATA11

12 DATA12

13 DATA13

14 DATA14

15 DATA15

Table 20: ACE Controller TAP Pins

Pins Description

TSTTDI (TDI) Test Data In

TSTTDO (TDO) Test Data Out

TSTTMS (TMS) Test Mode Select

TSTTCK (TCK) Test Clock

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 33

Advance Product Specification 1-800-255-7778

The TSTJTAG logic is connected to the CFGJTAG port as long as the CompactFlash and MPU interfaces are not connected

to the CFGJTAG port. Outlined in the following sections are the details of the JTAG interface for the ACE Controller.

The availabl e Boundary-Scan registers for the ACE Controller are shown in Table 21.

Instruction Register

The Instruction Register (IR) for the ACE Controller is eight bits wide and is conne cted between TDI and TDO during an

instruction scan sequence. The Instruction Register is parallel loaded with a fixed instruction capture pattern in preparation

f or an instruction sequence. This pattern is shifted out onto TDO (LSB first), while an instruction is shifted into the instruction

The optional IDCODE instruction is supported in addition to the mandatory instructions (BYPASS, SAMPLE/PRELOAD, and

EXTEST). The binary values for these instructions are listed in Table 23.

Figure 17: Test JTAG Interface Block Diagram

TAP

Controller

Logic

Identifcation Register

Instruction Register

Bypass Register

Boundary Scan Register

TSTTDI

TSTTMS

TSTTCK

CFGTDO

TSTTDO

CFGTCK

CFGTMS

CFGTDI

CFGSEL (from core)

CFGDATA (from core)

DS080_45_030801

Table 21: ACE Controller Boundary-Sca n Registers

Instruction Register 8 bits Holds current instruction OPCODE and captures internal device status.

Boundary-Scan Register 109 bits Controls and observes input, output, and output enable.

Identification Register 32 bits Captures device IDCODE.

Bypass Register 1 bit Device bypass.

Table 22: Instruction Register Values Loaded into IR During Instruction Scan Sequence

IR[7] IR[6] IR[5] IR[4] IR[3] IR[2] IR[1:

CFGINSTRERR

(MPU ERRORREG

CFGFAILED

(MPU ERRORREG

CFGREADERR

(MPU ERRORREG

CFCERROR

(MPU STATUSREG

CFGERROR

(MPU ST ATUSREG

CFGDONE 01

System ACE CompactFlash Solution

34 www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

Boundary-Scan Register

The Bounda ry -Sc an re gis te r, whi ch is the pr imary test data re gis ter, is used to control and obs erve the state of device pins

during EXTEST and SAMPLE/PRELOAD instructions. For more information on the System ACE Boundary-Scan register

(such as bit sequence, 3-state control, and so f orth), refer to the System ACE Boundary-Scan Description Language (BSDL)

file available from the software download area at: www.xilinx.com.

Bit Sequence

The bit sequ ence of the device is obtai nable from the B oundary -Scan Descr ipti on Langu age (BSD L) File s. These fil es are

available from the software download area at: www.xilinx.com.

Identification Register

The Identification Register known as the IDCODE is a fixed, vendor-assigned value that is used to electronically identify the

type of device and the manufacturer f or a specific device being tested. The ACE Controller IDCODE register is 32 bits wide.

The contents of this register can be shifted out for examination by selecting the IDCODE instruction. The IDCODE is

available to any other system component via JTAG. The IDCODE register has the following binary format, described in

Table 24: vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1

Bypass Register

The last standard 1149.1 Boundary-Scan data register in the ACE Controller is the single flip-flop BYPASS register. It

directl y passes data serial ly from the TDI pi n to the TDO pin during a bypass instruc tion. This r egister is init ialized to zero

when the TAP controller is in the UPDATE-DR state.

TAP Timing Characteristi cs

IEEE 1149.1 boundary-scan (JTAG) testing is performed via the standard 4-wire Test Access Por t (TAP). The Boundary

Scan timing waveforms and switching characteristics of the TAP are described in Figure 18 and Table 25, respectively.

Table 23: ACE Controller Boundary-Scan Instructions

Boundary-Scan Instruction Binary Code [7:0] Description

BYPASS 11111111 Enable s BY PASS

SAMPLE/PRELOAD 00000001 Enables boundary-scan SAMPLE/PRELOAD Operation

IDCODE 00001001 E nables sh ifti ng out 32- bit IDCODE

EXTEST 00000000 Enables boundary-scan EXTEST operation

Table 24: ACE Controller Identification Register

Version Family Array Size Manufacturer Required by 1149.1

0000 0000001 00000000 00001001001 1

Figure 18: Test JTAG Boundary-Scan Port Timing Waveforms

0ns 50ns 100ns 150ns

TSTTMS

TSTTDI

TSTTCK

TSTTDO

VALID

TTCKTDO

TTAPTCK

TTCKTAP

DS080_46_030801

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 35

Advance Product Specification 1-800-255-7778

Configuration JTAG Interface (CFGJTAG)

Configuration JTAG Port is the interface between the ACE Controller and the target FPGA chain. This port is accessed when

configuring the target FPGA chain of de vices via any of the ACE Controller interfaces (Test JTAG, MPU, or CompactFlash).

To program or test the FPGA target chain, the data from these interfaces is converted to 1149.1 Boundar y-Scan (JTAG)

serial data.

Typical Configuration Modes

The four ACE Controller interfaces are designed to work together in a number of different combinations. This section

discus se s typ ic al us er co nfi gura tion mo des. A hand ful of s i gnal s dete rmine wh ich i nter face provides the co nfi gurat ion dat a

source. Table 26 describes these important signals, and Table 27 shows how they work together to determine which

interface will be used. This is especially important when using multiple interfaces in a design, or when not using the default

value s of these s ignals. The default values of these s ignals s et the Compac tFlash int erface as the source of configura tion

data.

Table 25: System ACE Controller TAP Characteristics

Symbol Parameter Min Max Units

T(TAPTCK) TSTTMS and TSTTDI setup time before rising edge of TSTTCK 4 ns

T(TCKTAP) TSTTMS and TSTTDI hold times after TSTTCK 0 ns

T(TCKTDO) TSTTCK falling edges to TSTTDO output valid 16 ns

F(TSTTCK) Maximum TSTTCK clock frequency 16.7 MHz

Table 26: Conf igu ration Signals Used for Selecting Configuration Modes and Active Design

Configuration Signal Description Default

CFGMODE Pin or MPU register bit CFGMODEPIN = 1

CFGMODE Register Bit = 0

CFGADDR[2:0] Pins or MPU register bits 0

CFGSEL MPU register bit 0

CFGSTART MPU re gister bit 0

CFGRESET MPU register bit (CFGRESET is a subset of the RESET pin) 0

FORCECFGADDR MPU register bit (Overrides value on CFGADDR [2:0] pins) 0

FORCECFGMODE MPU register bit (Overrides value on CFGMODEPIN) 0

Table 27: Active Configura tion Modes

Configuration Interface CFGMODE(1) CFGSEL CFGSTART CFGRESET

CompactFlash (Configure from CF immediately after reset) 10X

(2) 0

CompactFlash (Configure from CF after receiving MPU start signal) 001 0

Microprocessor (Configure from MPU after receiving MPU start signal) 111 0

Microprocessor (Configure from MPU) 11X 0

Test JTAG (Configure using the TSTJTAG port) 1X 0 0

Notes:

2. The FORCECFGMODE bit in the CONTROLREG register of the MPU interface can be used to force the CFGMODE register bit to

override the ACE Controller CFGMODEPIN.

3. An X entry indicates “don’t care”.

System ACE CompactFlash Solution

36 www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

CompactFlash (CF) to Configuration JTAG (CFGJTAG) Setup

This setup provides a standard CompactFlash interf ace f or high-density FPGA systems. The CompactFlash interface is the

source of configuration data. The data configures the Xilinx FPGA chain through Boundary-Scan (JTAG) using the

Configuration JTAG port, as shown in Figure 19.

The ACE Controller handles all necessary steps to perform configuration from the CF to the target system. The appropriate

signal connections for this setup are shown in Figure 20. This setup can be used in conjunction with any of the other

interfaces.

Figure 19: Data Flow Diagram of CF to CFGJTAG

MPU TSTTDI

TAP

CTRL.

CompactFlash

ACE

Controller

Core

TSTTDO

TDO TDI

CFGTDO CFGTDI

TDI

TDO TDI TDOTDO TDI

DS080_22_030801

*CFCGTCK and CFGTMS lines are driven

by ACE Controller Core Logic and are broadcast

to all target devices.

BS NAC

(Test JTAG Port)

(Configuration JTAG Port)

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 37

Advance Product Specification 1-800-255-7778

CompactFlash (CF) to Microprocessor (MPU) Setup

This setup provides a stan dard Comp actFlas h to MPU int erfa ce for high-density FPGA sys tems. This inte rface provid es a

great deal of flexibility. The ability to communicate with the CF through the MPU port allows the user to perform many

operations, such as being able to switch the programming .ACE file so that it can be used for the target system.

Figure 20: Wiring Diagram for CF to CFGJTAG

ACE

Controller

CompactFlash

Device

CFD(15:0)

CFA(10:0)

D(15:0)

A(10:0)

Xilinx FPGA

Target Chain

CFGTMS TMS

CFGTCK

CFGTDI

CFGTDO

TCK

TDO

TDI

DS080_24_121201

CE1

CE2

WAIT

REG

CD1

CD2

CFCE1

CFCE2

CFWE

CFOE

CFWAIT

CFREG

CFCD1

CFCD2

CFGPROG

CFGINIT

PROGRAM

INIT

STATLED

RESET

ERRLED

VCC

5.1 kΩ

1.0 kΩ

RESET

VCC

180 Ω

5.1 kΩ

CFRSVD

VCC

CFRESET

CSEL

IOWR

IORD

Figure 21: Data Flow Diagram of CF to MPU

TAP

CTRL.

TDO TDI

CFGTDO CFGTDI

TDI

TDO TDI TDOTDO TDI

DS080_28_030801

BS NAC

MPU

CompactFlash

ACE

Controller

Core TSTTDI

TSTTDO (Test JTAG Port)

(Configuration JTAG Port)

System ACE CompactFlash Solution

38 www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

The ACE Controller handles all necessary steps to perf orm a CF to MPU operation. This setup uses the CF to MPU signals

shown in the wiring diagram in Figure 22.

Figure 22: Wiring Diagram CF to MPU

ACE Controller

MPU Device

CLK

MPBRDY

MPIRQ

MPA(6:0)

MPD(15:0)

DS080_27_121201

CompactFlash

Device

D(15:0)

A(10:0)

CFD(15:0)

CFA(10:0)

Refer to the microprocessor

or microcontroller data sheet

for appropriate signal names.

CE2

CE1

WAIT

REG

CD1

CD2

CFCE1

CFCE2

CFWE

CFOE

CFWAIT

CFREG

CFCD1

CFCD2

RESET

STATLED

ERRLED

MPCE

MPWE

MPOE

VCC

5.1 kΩ

1.0 kΩ

IOWR

IORD

CSEL

CFRESET

VCC

5.1 kΩ

CFRSVD

VCC

180 Ω

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 39

Advance Product Specification 1-800-255-7778

Reading Sector Dat a from Compact Flash Control

Flow Process

Sector data can be read from the CompactFlash device via

the MPU interface of the SystemACE controller by f ollowing

the control flow sequence shown in Figure 23. Th e firs t step

in the sequence of accessing the CompactFlash interface is

to arbitrate for a lock. The control flow process for obtaining

a CompactFlash resource lock is shown in Figure 24. Once

the MPU inter fa ce has been granted a Compac tFlash lock,

the MPU interface needs to make sure that the Compact-

Flash device is ready to receive a command. The process

for polling the command readiness indicator is shown in

Figure 25.

Figure 23: Reading Sector Data from CompactFlash Control Flow Pr ocess

Set ReadMemCardData

Command Control

Set MPU LBA

Set Sector

Count Control

Initialize Buffer

Count variable*

Read Data Buffer

Release CF Lock

Data is read.

Return success.

Buffer Count

equal to 0?

Decrement Buffer

Count variable

Yes

*Set Buffer Count variable equal to

the number of buffers in a sector transfer

= ((Sector Count)*(512 Bytes per sector))/

(32 bytes per buffer)

= (Sector Count) * (16 buffers per sector)

Read Data from CF

Get CF Lock

Check If Ready

For Command

• Write LBA bits 7:0 to byte address 10h

Write LBA bits 15:8 to byte address 11h

Write LBA bits 23:16 to byte address 12h

Write LBA bits 27:24 to byte address 13h

Write SECCNT bits 7:0 to byte address 14h

Write CFGRESET bit = 1 to byte address 18h

Write LOCKREQ

bit = 0 to byte

address 18h

Reset configuration

controller

Clear configuration

controller reset

Write CFGRESET

bit = 0 to byte

address 18h

Write CMD bits to byte address 15h

DS080_48_051701

System ACE CompactFlash Solution

40 www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

Once the CompactFlash device is ready to receive a new

command, the following information needs to be written to

the MPU interface:

1. The sector address or logical block address (LBA) of

the first sector to be transferred should be written to the

following MPU address locations:

- LBA[7:0] @ MPU byte address 10h

- LBA[15:8] @ MPU byte address 11h

- LBA[23:16] @ MPU byte address 12h

- LBA[27:24] @ MPU byte address 13h (note that

only four bits are used in the most significant LBA

byte)

2. The number of sectors to be read should be written to

the low byte of the SECCNTCMDREG register (MPU

byte address 14h)

3. The ReadMemCardData command (03h) should be

written to the high byte of the SECCNTCMDREG

registe r (MPU byte address 15h)

4. Reset the CFGJTAG controller by setting the

CFGRESET bit (bit 7) of the CONTROLREG register

(MPU address 18h) to a 1.

Immediately after writing the command to the MPU inter-

face, the CFGJTAG controller should be reset before read-

ing the sector data from the data buffer.

The control flow process for reading the sector data from

the data buffer is shown in Figure 26.

After all of the requested sector data has been read, the

CFGJTAG controller should be taken out of reset and the

CompactFlash lock should be released by setting the

LOCKREQ bit (bit 1) and CFGRESET bit (bit 7) o f the low

byte of the CONTROLREG register (MPU byte address

18h) to a 0. Note that all requested sector data should be

read from the data buffer in order to avoid a deadlock situa-

tion with the CompactFlash device.

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 41

Advance Product Specification 1-800-255-7778

Get CompactFlash Lock Control Flow Process

The CompactFlash resource must be arbitrated for before it

can be acce ssed via th e MPU in te rf a ce. The C ompa ctF lash

arbitration p rocess is shown in Figure 24. A CompactFl ash

lock is requ ested by setting the LOCKREQ bit (bit 1) to a 1

in the CONTROLREG register (MPU address 18h) and poll-

ing the MPULOCK bit (bit 1) in the STATUSREG register

(MPU byte address 04h).

Note that if the CFGLOCK bit (bit 0) in the STATUSREG reg-

ister (MPU byte address 04h) is set, then the CFGJTAG

controller has locked the CompactFlash resource. In this

case, the MPU interface must eith er wait for the CFGJTAG

interface to release the lock or it can force the lock to be

releas ed. Thi s is do ne by resetti ng th e CFGJ TAG controller

by setting the CFGRESET bit (bit 7) and the FORCELOCK-

REQ bit (bit 0) in the CONTROLREG register (MPU byte

address 18h). The lock request process can be started

again after forcing the CFGJTAG controller to release the

lock.

Figure 24: Get CompactFlash Lock Control Flow Process

CF Locked?

Timer Expired?

Decrement timer

variable

CF is busy.

Return timeout

error.

CF is locked.

Return success.

Yes

Write LOCKREQ bit = 1

to byte address 18h

Get CF Lock

Set Lock Control

Initialize timer variable

Get Lock Status Read MPULOCK bit

from byte address 04h

DS080_49_051701

System ACE CompactFlash Solution

42 www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

Check if Ready for a Command Control

Flow Process

Before reading or writing sector data, it is important to make

sure that the CompactFlash device is ready f or a command.

This is done by polling the RDYFORCFCMD bit (bit 0) in the

second byte of the STATUSREG register (MPU byte

address 05h) until it is set to a 1. This control flow process is

shown in Figure 25.

Figure 25: Check if Ready for a Command Control Flow Process

Check If Ready

For Command

Get Command

Ready Status

Ready For

Command?

Timer Expired?

Decrement timer

variable

Initialize timer variable

Busy.

Return timeout

error.

Ready.

Return success.

Yes

Read RDYFORCMD bit

from byte address 05h

DS080_50_051701

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 43

Advance Product Specification 1-800-255-7778

Read Data Buffer Control Flow Process

The control flow process for reading from the data buffer is

shown in Figure 26. The SystemACE data buffer is imple-

mented as a 32-byte (16-word) deep FIFO that is aliased

across a range of MPU byte addresses (40h through 7Fh) in

order to facilitate burst transfers across the MPU interface.

Sector data is read from the data buffer by first waiting for

the buffer to become ready (i.e., full of sector data), as

shown in Figure 27. Once the buffer is ready, then all 32

bytes can be read from the buff er from alternating ev en and

odd byte addresses. Reading from an odd byte address

while in BYTE mode causes the FIFO to increment the data

word to the next available word in the FIFO. Reading from

any data buff er address while in WORD mode will cause the

FIFO to increment.

Figure 26: Read Data Buffer Control Flow Process

Read data word

from buffer

Decrement Data

Count variable

Data Count

equal to 0?

Buffer is written.

Return success.

Yes

Wait for Buffer Ready

Read Data Buffer

Initialize Data

Count variable*

*Set Data Count variable equal to

the number of data items in a buffer

(e.g., 16 bytes or 32 words)

Read data bits 7:0 from byte address 40h

Read data bits 15:8 from byte address 41h

(Note that the following conditions must

be valid for a data read to occur from the

CompactFlash data buffer:

1. The data buffer must be ready

2. A single read from byte address 41h

must occur that will cause the entire 16-

bit data register to be overwritten by the

buffer with new data)

DS080_51_051701

System ACE CompactFlash Solution

44 www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

Wait for Buffer Ready Control Flow Process

The rea dines s of the Sys temACE data buffer indicates tha t

the buffer is either full during a ReadMemCardData com-

mand execution or empty during a WriteMemCardData

command e xecution. The control flow process for waiting f or

the buffer to become ready is shown in Figure 27. The

buffer ready status can be obtained from either the

DATA BUFRDY bit (bit 5 ) of the S TATUS REG register ( MPU

byte address 04h) or from the MPBRDY pin of the Sys-

temACE controller.

Figure 27: Wait for Buffer Ready Control Flow Process

Wait for Buffer Ready

Get Buffer

Ready Status

Buffer Ready?

Timer Expired?

Decrement timer

variable

Initialize timer variable

Buffer not

ready. Return

timeout error.

Buffer is ready.

Return success.

Yes

Read DATABUFRDY bit

from byte address 04h

DS080_52_051701

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 45

Advance Product Specification 1-800-255-7778

Microprocessor (MPU) to CompactFlash (CF) Setup

This setup provides a communication path from the MPU to the CF device. The CompactFlash is the source of the

configuration data, and this path enables users to read the contents of the CF device.

The ACE Controller handles all nec essary steps to perform an MPU t o CF ope ration. The nec ess ar y si gnals for this setu p

are shown in Figure 22.

Figure 28: Data Flow Diagram of MPU to CF

MPU TSTTDI

TAP

CTRL.

CompactFlash

TSTTDO TDO TDI

CFGTDO CFGTDI

TDI

TDO TDI TDOTDO TDI

DS080_25_030801

BS NAC

ACE

Controller

Core

(Test JTAG Port)

(Configuration JTAG Port)

System ACE CompactFlash Solution

46 www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

Writing Sector Data to Compact Flash Control

Flow Process

Secto r data can be wr itten to th e CompactFla sh device via

the MPU interface of the SystemACE controller by f ollowing

the control flow sequence shown in Figure 29. Th e firs t step

in the sequence of accessing the CompactFlash interface is

to arbitrate for a lock. The control flow process for obtaining

a CompactFlash resource lock is shown in Figure 24. Once

the MPU inter fa ce has been granted a Compac tFlash lock,

the MPU interface needs to make sure that the Compact-

Flash device is ready to receive a command. The process

for polling the command readiness indicator is shown in

Figure 25.

Figure 29: Write Data to CompactFlash Control Flow Process

Set MPU LBA

Set WriteMemCardData

Command Control

Set Sector

Count Control

Initialize Buffer

Count variable*

Write Data Buffer

Release CF Lock

Data is written.

Return success.

Buffer Count

equal to 0?

Decrement Buffer

Count variable

Yes

*Set Buffer Count variable equal to

the number of buffers in a sector transfer

= ((Sector Count)*(512 Bytes per sector))/

(32 bytes per buffer)

= (Sector Count) * (16 buffers per sector)

Write Data to CF

Get CF Lock

Check If Ready

For Command

Write LBA bits 7:0 to byte address 10h

Write LBA bits 15:8 to byte address 11h

Write LBA bits 23:16 to byte address 12h

Write LBA bits 27:24 to byte address 13h

Write SECCNT bits 7:0 to byte address 14h

Write CFGRESET bit = 1 to byte address 18h

Write LOCKREQ

bit = 0 to byte

address 18h

Reset configuration

controller

Clear configuration

controller reset

Write CFGRESET

bit = 0 to byte

address 18h

Write CMD bits to byte address 15h

DS080_053_051701

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 47

Advance Product Specification 1-800-255-7778

Once the CompactFlash device is ready to receive a new

command, the following information needs to be written to

the MPU interface:

1. The sector address or logical block address (LBA) of

the first sector to be transferred should be written to the

following MPU address locations:

- LBA[7:0] @ MPU byte address 10h

- LBA[15:8] @ MPU byte address 11h

- LBA[23:16] @ MPU byte address 12h

- LBA[27:24] @ MPU byte address 13h (note that

only four bits are used in the most significant LBA

byte)

2. The number of sectors that will be written should be

loaded into the low b yte of the SECCNTCMDREG

registe r (MPU byte address 14h)

3. The WriteMemCardData command (04h) should be

written to the high byte of the SECCNTCMDREG

registe r (MPU byte address 15h)

4. Reset the CFGJTAG controller by setting the

CFGRESET bit (bit 7) of the CONTROLREG register

(MPU address 18h) to a 1.

Immediately after writing the command to the MPU inter-

face, the CFGJTAG controller should be reset before writing

the sector data to the data buffer.

The control flow process f or writing the sector data from the

data buffer is shown in Figure 30.

After all of the required sector data has been written, the

CFGJTAG controller should be taken out of reset and the

CompactFlash lock should be released. This is done by set-

ting the CFGRESET (bit 7) and LOCKREQ (bit 1) bits of the

low byte of the CONTROLREG register (MPU byte address

18h) to a 0, respectively. Note that all requested sector data

should be written to the data buff er in order to avoid a dead-

lock situation with the CompactFlash device.

Figure 30: Write Data Buffer Control Flow Process

Write data word

to buffer

Decrement Data

Count variable

Data Count

equal to 0?

Buffer is written.

Return success.

Yes

Wait for Buffer Ready

Write Data Buffer

Initialize Data

Count variable*

*Set Data Count variable equal to

the number of data items in a buffer

(e.g., 16 bytes or 32 words)

Write data bits 7:0 to byte address 40h

Write data bits 15:8 to byte address 41h

(Note that the following conditions must

be valid for a data write to occur to the

CompactFlash data buffer:

1. The data buffer must be ready

2. A single write to byte address 41h

must occur that will cause the entire 16-

bit data register to be written to the

buffer)

DS080_54_051701

System ACE CompactFlash Solution

48 www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

Write Data Buffe r Control Flow Process

The control flow process for writing to the data buffer is

shown in Figure 30. The SystemACE data buffer is imple-

mented as a 32-byte (16-word) deep FIFO that is aliased

across a range of MPU byte addresses (40h through 7Fh) in

order to facilitate burst transfers across the MPU interface.

Sector data is written to the data buffer by first waiting for

the buffer to becom e ready (i.e., empty of any sector data),

as shown i n Figure 27. On ce the buffer is ready, then all 32

bytes can be written to the buffer to alternating even and

odd byte addresses. Writing to an odd b yte address while in

BYTE mode causes the FIFO to increment the data word to

the next available word in the FIFO. Writing to any data

buffer address while in WORD mode will cause the FIFO to

increment.

Microprocessor (MPU) to Configuration JTAG (CFGJTAG) Setup

This setup provides an MPU to CFGJTAG communication path. The data configures the FPGA system through JTAG via the

Configuration JTAG Port.

The ACE Controller handl es all n ecessa r y steps to perform c onfigu ration usin g the MPU co mmunica tion path to the targe t

system. Figure 32 shows the connections required for this setup.

Figure 31: Data Flow Diagram of MPU to CFGJTAG

TSTTDI

TAP

CTRL. TSTTDO TDO TDI

CFGTDO CFGTDI

TDI

TDO TDI TDOTDO TDI

DS080_30_030801

*CFCGTCK and CFGTMS lines are driven

by ACE Controller Core Logic and are broadcast

to all target devices.

BS NAC

MPU

CompactFlash

ACE

Controller

Core

(Test JTAG Port)

(Configuration JTAG Port)

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 49

Advance Product Specification 1-800-255-7778

Write Data to CFGJTAG Interface Cont rol

Flow Process

The target devi ces in the CFGJ TAG chain can also be pr o-

grammed via the MPU interf ace as shown in Figure 33. The

first step is to arbitrate for the data buffer by requesting a

CompactFlash lock as shown in Figure 24. Once the lock

has been granted, the following steps should be taken to

write configuration data to the CFGJTAG controller:

1. Reset the CFGJTAG controller by setting the

CFGRESET bit (bit 7) of the CONTROLREG register

(MPU address 18h) to a 1.

2. Select the MPU interface as the source of the

configuration data by setting the CFGSEL bit (bit 6) of

the CONTROLREG register (MPU byte address 18h) to

a 1.

3. Direct the CFGJTAG controller to wait for the MPU

interface for the start signal by setting the both the

FORCECFGMODE (bit 3) and CFGMODE (bit 4) bits of

the CONTROLREG register (MPU byte address 18h) to

a 1.

4. Set the configuration start signal by setting the

CFGSTART bit (bit 5) of the CONTROLREG register

(MPU byte address 18h) to a 1.

Figure 32: Wiring Diagram of MPU to CFGJTAG

ACE Controller Xilinx FPGA

Target Chain

CFGTCK

CFGTMS

CFGTDO

CFGTDI

TCK

TMS

TDI

TDO

CLK

MPBRDY

MPIRQ

MPA(6:0)

MPD(15:0)

VCC

DS080_33_121201

MPU Device

Refer to the microprocessor

or microcontroller data sheet

for appropriate signal names.

CFGINIT

CFGPROG PROGRAM

INIT

RESET STATLED

ERRLED

MPCE

MPWE

MPOE

5.1 kΩ

VCC

CFRSVD

180 Ω

System ACE CompactFlash Solution

50 www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

5. Take the CFGJTAG controller out of reset by setting the

CFGRESET bit (bit 7) of the CONTROLREG register

(MPU address 18h) to a 0.

6. At this point, the configuration data should be written to

the data buffer (as shown in Figure 30) until

configuration is done or until an error is encountered.

Note that in either case that an entire buffer’s worth of

data should be written to the buff er to ensure that it gets

sent to the CFGJTAG controller.

After the configuration information has been written suc-

cessfully, the CFGDONE bit (bit 7) of the STATUSREG reg-

ister (M PU byte add re ss 0 4h) shou ld be se t to a 1. If thi s is

not the case, then the other bits of the STATUSREG and

ERRORREG regis ter shou ld ind icate the sta tus of th e con-

figuration process.

Figure 33: Write Data to CFGJTAG Interface Control Flow Process

Read status & error

bits at byte addresses

04h through 0Bh

Initialize Buffer

Count variable*

Write Data Buffer

Return error.

Decrement Buffer

Count variable

NoYes

*Set Buffer Count variable equal to

the number of buffers in a transfer

Write Data

to CFGJTAG

Set CFGSEL bit to a 1 at byte address 18h

Select MPU as config

data source

Set CFGRESET bit to a 0 at byte address 18h

Clear configuration

controller reset

Get CF Lock

Set FORCECFGMODE bit to a 1 at byte address 18h

Set CFGMODE bit to a 0 at byte address 18h

Direct controller

to wait for MPU

Set CFGRESET bit to a 1 at byte address 18h

Reset configuration

controller

Set CFGSTART bit to a 1 at byte address 18h

Start

configuration

Buffer Count

equal to 0?

Check status of

configuration

Error? Data written.

Return status.

Yes

DS080_55_051701

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 51

Advance Product Specification 1-800-255-7778

Test JTAG (TSTJTAG) to Configurat ion JTAG (CFGJTAG) Setup

This se tup provides a 1149.1 Bo undary -Scan c ommunicati on path to the target FPG A syste m. Usin g this setup, the target

system can be configured via JTAG from a JTAG compliant tool.

Figure 34: Data Flow Diagram of TSTJTAG to CFGJTAG (Using Bypass Path)

TSTTDI

TAP

CTRL.

TSTTDO

TDO TDI

CFGTDO CFGTDI

TDI

TDO TDI TDOTDO TDI

DS080_32_030801

*CFCGTCK and CFGTMS lines are driven

by ACE Controller Core Logic and are broadcast

to all target devices.

BS NAC

MPU

CompactFlash

ACE

Controller

Core

(Test JTAG Port)

(Configuration JTAG Port)

Figure 35: Data Flow Diagram of TSTJTAG to CFGJTAG (Using Boundary-Scan Path)

TSTTDI

TAP

CTRL.

TSTTDO

TDO TDI

CFGTDO CFGTDI

TDI

TDO TDI TDOTDO TDI

DS080_34_051701

*TSTTCK, TSTTMS are multiplexed onto

the CFGTCK, CFGTMS lines, respectively

and are brodcast to all devices.

BS NAC

MPU

CompactFlash

ACE

Controller

Core

(Test JTAG Port)

(Configuration JTAG Port)

System ACE CompactFlash Solution

52 www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

The ACE Controller ha ndles all necess ar y s teps to perfor m a confi guratio n from the TS TJTAG to the target sys tem via th e

CFGJTAG interface. When using the TSTJTAG to CFGJTAG setup, the signals in Figure 36 should be connected.

Figure 36: Wiring Diagram of TSTJTAG to CFGJTAG

Test JTAG

Interface

ACE

Controller

Configuration

JTAG Interface

(Xilinx FPGA

Target Chain)

TCK

TMS

TCK

TDI

TDO

CFGTMS

CFGTCK

CFGTDO

CFGTDI

TMS TDI TDO

TSTTCK

TSTTMS

TSTTDI

TSTTDO

VCC

DS080_35_121201

RESET

CFGINIT

CFGPROG PROGRAM

INIT

RESET

CFRSVD

STATLED

ERRLED

VCC

5.1 kΩ

180 kΩ

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 53

Advance Product Specification 1-800-255-7778

General Timing Specifications

MPU Inter face Timing Characteristics

Table 28: Clock Frequency Characteristics

Symbol Parameter Min Max Units

F(CLK) System ACE clock frequen cy 33 MHz

F(TSTTCK) Test JTAG clock frequency 16.7 MHz

Table 29: MPU Interface Timing Characteristics

Symbol Parameter Min Max Units

TS(MPACLK) MPA[6:0] setup time before rising edge of CLK 4 ns

TS(MPCECLK) MPCE setup time before rising edge of CLK 4 ns

TS(MPDCLK) MPD[15:0] setup time before rising edge of CLK 4 ns

TS(MPOECLK) MPOE setup time before rising edge of CLK 12 ns

TS(MPWECLK) MPWE setup time before rising edge of CLK 12 ns

TH(CLKMPA) MPA hold time after rising edge of CLK 0 ns

TH(CLKMPCE) MPCE hold time after rising edge of CLK 0 ns

TH(CLKMPD) MPD[15:0] hold time after rising edge of CLK 0 ns

TH(CLKMPOE) MPOE hold time after rising edge of CLK 0 ns

TH(CLKMPWE) MPWE hold time after rising edge of CLK 0 ns

TD(CLKMPD) CLK rising edge to MPD 22 ns

TD(CLKMPBRDY) CLK rising edge to MPBRDY 22 ns

TD(CLKMPIRQ) CLK rising edge to MPIRQ 22 ns

TD(MPCEMPD) Propagation delay from MPCE to MPD 13 ns

TD(MPOEMPD) Propagation delay from MPOE to MPD 13 ns

System ACE CompactFlash Solution

54 www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

CompactFlash Interface Timing Characteristics

Configuration JTAG Interface Timing Characteristics

Table 30: CompactFlash Interface Timing Characteristics

Symbol Parameter Min Max Units

TS(CFCDCLK) CFCD1 and CFCD2 setup time before rising edge of CLK 4 ns

TS(CFDCLK) CFD[15:0] setup time before rising edge of CLK 4 ns

TS(CFWAITCLK) CFWAIT setup time before rising edge of CLK 4 ns

TH(CLKCFCD) CFCD1 and CFCD2 hold time after rising edge of CLK 0 ns

TH(CLKCFD) CFD[15:0] hold time after rising edge of CLK 0 ns

TH(CLKCFWAIT) CFWAIT hold time after rising edge of CLK 0 ns

TD(CLKCFA) CLK rising edge to CFA[10:0] 19 ns

TD(CLKCFCE) CLK rising edge to CFCE1 and CFCE2 16 ns

TD(CLKCFD) CLK rising edge to CFD[15:0] 19 ns

TD(CLKCFOE) CLK rising edge to CFOE 16 ns

TD(CLKCFWE) CLK rising edge to CFWE 16 ns

Table 31: Configuration JTAG Interface Timing Characteristics

Symbol Parameter Min Max Units

TS(CFGADDRCLK) CFGADDR[2:0] setup time before rising edge of CLK 6 ns

TS(CFGINITCLK) CFGINIT setup time before rising edge of CLK 11 ns

TS(CFGMODEPINCLK) CFGMODEPIN setup time before rising edge of CLK 7 ns

TS(CFGTDICLK) CFGTDI setup time before falling edge of CLK 4 ns

TH(CLKCFGADDR) CFGADDR[2:0] hold time after rising edge of CLK 0 ns

TH(CLKCFGINIT) CFGINIT hold time after rising edge of CLK 0 ns

TH(CLKCFGMODEPIN) CFGMODEPIN hold time after rising edge of CLK 0 ns

TH(CLKCFGTDI) CFGTDI hold time after falling edge of CLK 0 ns

TD(CLKCFGPROG) CLK rising edge to CFGPROG 17 ns

TD(CLKCFGTDO) CLK falling edge to CFGTDO 16 ns

TD(CLKCFGTMS) CLK falling edge to CFGTMS 20 ns

TD(CLKCFGTCK) Propagation delay from CLK to CFGTCK 15 ns

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 55

Advance Product Specification 1-800-255-7778

Test JTAG Interface Timing Characteristics

Miscellaneous Timing Characteristics

Table 32: Test JTAG Interface Timing Characteristics

Symbol Parameter Min Max Units

TS(TSTTDITSTTCK) TSTTDI setup time before rising edge of TSTTCK 4 ns

TS(TSTTMSTSTTCK) TSTTMS setup time before rising edge of TSTTCK 4 ns

TS(INTSTTCK) All other inputs setup time before rising edge of TSTTCK 5 ns

TH(TSTTCKTSTTDI) TSTTDI hold time after rising edge of TSTTCK 0 ns

TH(TSTTCKTSTTMS) TSTTMS hold time after rising edge of TSTTCK 0 ns

TH(TSTTCKIN) All other inputs hold time after rising edge of TSTTCK 0 ns

TD(TSTTCKOUT) TSTTCK f alling edge to all other outputs 24 ns

TD(TSTTCKCFGTCK) Propagation delay from TSTTCK to CFGTCK 14 ns

TD(CFGTDITSTTDO) Propagation delay from CFGTDI to TSTTDO 11 ns

TD(TSTTMSCFGTMS) Propagation dela y from TSTTMS to CFGTMS 13 ns

Table 33: Miscel laneous Timing Characteristics

Symbol Parameter Min Max Units

TS(RESETCLK) RESET setup time before rising edge of CLK 7 ns

TH(CLKRESET) RESET hold time after rising edge of CLK 0 ns

TH(CLKERRLED) CLK rising edge to ERRLED 17 ns

TH(CLKSTATLED) CLK rising edge to STATLED 17 ns

System ACE CompactFlash Solution

56 www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

Electrical Characteristics

F or more detailed ACE Flash specifications, ref er to the CompactFlash Memory Card Product Manual from SanDisk, or visit

their website at: www.sandisk.com.

Table 34: ACE Flash Card Characteristics

Type Description Symbol Min Typ Max Units Conditions

DC Input Voltage VCC –0.3 7.0 V

1 Input Voltage

(VCC = 3.3 V) VIH

VIL

2.4 0.6 V

2 Input Voltage

(VCC = 3.3 V) VIH

VIL

1.5 0.6 V

3 Input Voltage

(VCC = 3.3 V) VTH

VTL

1.8

1.0 V

1 Output Voltage VOH

VOL

VCC – 0.8 GND + 0.4 VI

OH = –4 mA

IOL = 4 mA

2 Output Voltage VOH

VOL

VCC – 0.8 GND + 0.4 VI

OH = –8 mA

IOL = 8 mA

3 Output Voltage VOH

VOL

VCC – 0.8 GND + 0.4 VI

OH = –8 mA

IOL = 8 mA

X 3-State Leakage

Current IOZ –10 10 µA VOL = GND

VOH = VCC

Ambient Temperature TA060°C

IxZ IL Input

Leakage

Current

–1 1 µA VIH = VCC/VIL = GND

IxU RPU1 Pull-Up

Resistor 50 500 k

VCC = 5.0 V

IxD RPD1 Pull-Down

Resistor 50 500 k

VCC = 5.0 V

OTX Totempole IOH & IOL

OZX 3-State N-P

Channel IOH & IOL

OPX P-Channel

Only IOH Only

ONX N-Channel

Only IOL Only

Notes:

1. The minimum pull-up resistor leakage current meets the PCMCIA specification of 10 K

but is intentionally higher in the

CompactFlash Memory Card Series product to reduce power use. x refers to the Type 1, 2, or 3. For example, OT3 refers to

Totempole output with a type 3 output drive characteristic.

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 57

Advance Product Specification 1-800-255-7778

Table 35: ACE Controller Absolute Maximum Ratings (for VCCL = 2.5 [V] or VCCL = 3.3 [V ])

Description Symbol Limits Units

Power Supply Voltage VCCH(1) GND – 0.3 to 7.0 V

VCCL(1) GND – 0.3 to 4.0

Input Voltage VIH GND – 0.3 to VCCH + 0 .5 V

VIL GND – 0.3 to VCCL + 0.5

Output Voltage VOH GND – 0.3 to VCCH + 0 .5 V

VOL GND – 0.3 to VCCL + 0.5

Output Curr ent/P in IOUT ±30 mA

Storage Temperature TSTG –65 to 150 °C

Notes:

1. VCCH is greater than or equal to VCCL.

Table 36: ACE Controller Recommended Operating Conditions (for VCCL = 2.5 [V])

Description Symbol Min Typ Max Units

Power Supply Voltage VCCH 3.0 3.3 3.6 V

VCCL 2.25 2.5 2.75

Input Voltage VIH GND –VCCH V

VIL GND –VCCL

Ambient Temperature TA–40 –85(1) °C

Notes:

1. The ambient temperature range is recommended for TJ = –40 to 125 °C.

Table 37: ACE Controller Recommended Operating Conditions (for VCCL = 3.3 [V])

Description Symbol Min Typ Max Units

Power Supply Voltage VCCH 3.0 3.3 3.6 V

VCCL 3.0 3.3 3.6

Input Voltage VIH GND –VCCH V

VIL GND –VCCL

Ambient Temperature TA–40 –85(1) °C

Notes:

1. The ambient temperature range is recommended for TJ = –40 to 125 °C.

System ACE CompactFlash Solution

58 www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

Table 38: ACE Controller Characteristics

Description Symbol Min Typ Max Units Conditions

Quies cent Cur rent

(between VCCH and GND) ICCSH -- -- 300 µA VI = VCCH or VCCL or GND,

VCCH = Max, VCCL = Max,

IOH = IOL = 0

Quies cent Cur rent

(between VCCL and GND) ICCSL -- -- 420 µA VI = VCCH or VCCL or GND,

VCCH = Max, VCCL = Max,

IOH = IOL = 0

Input Leakage Current ILI –1-- 1µA

VCCH = Max, VCCL = Max,

VIHH = VCCH, VIHL = VCCL, VIL = GND

High-Level Input Voltage VIH1H 2.0 -- -- V Input Characteristics for I/O Supply

Rail

VCCH = Max

Low-Level Input Voltage VIL1H -- -- 0.8 V Input Characteristics for I/O Supply

Rail

VCCH = Min

High-Level Input Voltage VIH1L 2.0 -- -- V Input Characteristics for I/O Supply

Rail

VCCL = Max

Low-Level Input Voltage VIL1L -- -- 0.8 V Input Characteristics for I/O Supply

Rail

VCCL = Min

Pull-Up Resistance RPU1H 40 100 240 k

VI = GND

Pull-Down Resistance RPD1H 40 100 240 k

VI = VCCH

Pull-Up Resistance RPU1L 20 50 120 k

VI = GND

Pull-Down Resistance RPD1L 20 50 120 k

VI = VCCL

High-Level Output Voltage VOH3H VCCH – 0.4 -- -- V VCCH = Min, IOH = –12 mA

Low-Level Output Voltage VOL3H -- -- GND + 0.4 V VCCH = Min, IOL = 12 mA

High-Level Output Voltage VOH3L VCCL – 0.4 -- -- V VCCL = Min, IOH = –12 mA

Low-Level Output Voltage VOL3L -- -- GND + 0.4 V VCCL = Min, IOL = 12 mA

Off-State Leakage Current IOZ –1-- 1µA

VCCH = Max, VCCL = Max,

VOHH = VCCH, VOHL = VCCL,

VOL = GND

Input Terminal

Capacitance CI-- -- -- pF --

Output Termi nal

Capacitance CO-- -- -- pF --

Input/Output Terminal

Capacitance CIO -- -- -- pF --

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 59

Advance Product Specification 1-800-255-7778

Package Specifications: (Package Dimensions and Reliability Data)

Figure 37: ACE Flash Card Dimensions

1.685±.004

[42.80]

1.433±.006

[36.40]

.039±.002

[1.00]

.063±.002

[1.60]

.040±.003

[1.00] .040±.003

[1.00]

.130±.004

[3.30]

2X 1.015±.003

[25.78]

2X .472±.004

[12.00]

2X .118±.003

[3.00]

TOP

1.640±.005 [41.66]

.096±.003

[2.4]

.030±.003

[0.8]

.025±.003

[0.6]

4X R.020±.004

[0.5]

DS080_36_020601

System ACE CompactFlash Solution

60 www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

Table 39 shows ACE Flash reliability considerations.

Figure 38: ACE Flash Card Adapter Dimensions

0.130

[3.3]

0.196

[5.0]

1.196

[30.4]

3.370

[85.6]

2.126

[54.0]

1.694

[43.03] 0.138

[3.5]

.866

[22.0]

1.536

[39.03]

.472

[12.0] .078

[2.0]

DS080_37_020601

Table 39: ACE Flash Reliability

MTBF (@ 25 degrees C) >1,000,000 hours

Preventative Maintenance None

Data Reliability <1 non-recoverab le error in 1014 bits read

Endurance >= 300,000 erase/program cycles per logical sector

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 61

Advance Product Specification 1-800-255-7778

Figure 39: ACE Controller TQ144 Package Drawing

DS080_47_030801

System ACE CompactFlash Solution

62 www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

Pin Descriptions

This section provides ACE Flash and ACE Controller pinout information.

ACE Flash Card I/O Pins

Table 40 lists ACE Flash signal/pin assignments. LOW active signals have an overline. Pin types are Input, Output, or

Input/Output.

Table 40: ACE Flash Card Pin Assignme nts and Pin

Types

PC Card Memory Mode

Number Signal Name Pin

Type In, Out(2) Type

1 GND Ground

2 D03 I/O I1Z,OZ3

3 D04 I/O I1Z,OZ3

4 D05 I/O I1Z,OZ3

5 D06 I/O I1Z,OZ3

6 D07 I/O I1Z,OZ3

7CE1

II3U

8 A10 I I1Z

9OE

II3U

10 A09 I I1Z

11 A08 I I1Z

12 A07 I I1Z

13 VCC Power

14 A06 I I1Z

15 A05 I I1Z

16 A04 I I1Z

17 A03 I I1Z

18 A02 I I1Z

19 A01 I I1Z

20 A00 I I1Z

21 D00 I/O I1Z,OZ3

22 D01 I/O I1Z,OZ3

23 D02 I/O I1Z,OZ3

24 WP O OT3

25 CD2 O Ground

26 CD1 O Ground

27 D11(1) I/O I1Z,OZ3

28 D12(1) I/O I1Z,OZ3

29 D13(1) I/O I1Z,OZ3

30 D14(1) I/O I1Z,OZ3

31 D15(1) I/O I1Z,OZ3

32 CE2(1) II3U

33 VS1 OGround

34 IORD II3U

35 IOWR II3U

36 WE II3U

37 RDY/BSY OOT1

38 VCC Power

39 CSEL II2Z

40 VS2 O OPEN

41 RESET I I2Z

42 WAIT OOT1

43 INPACK OOT1

44 REG II3U

45 BVD2 I/O I1U,OT1

46 BVD1 I/O I1U,OT1

47 D08(1) I/O I1Z,OZ3

48 D09(1) I/O I1Z,OZ3

49 D10(1) I/O I1Z,OZ3

50 GND Ground

Notes:

1. These signals are required only for 16-bit access and not

required when installed in 8-bit systems. For lowest power

dissi pation, leave these signals open.

2. For definition s of In, Out Type, refer to Electrical

Characteristics, page 56.

Table 40: ACE Flash Card Pin Assignments and Pin

Types (Continued)

PC Card Memory Mode

Number Signal Name Pin

Type In, Out(2) Type

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 63

Advance Product Specification 1-800-255-7778

Table 41 defines the DC characteristics for all ACE Flash input and output type structures.

Table 41: ACE Flash Signal Descriptions

Signal Name Dir. Pin Description

A10 - A0 I 8, 10, 11,

12, 14, 15,

16, 17, 18,

19, 20

These address lines along with the REG signal are used to select the

following: The I/O port address registers within the CompactFlash

Card, the memory mapped port address regis ter s with in the card, a

byte in the card's information structure and its configuration control

and status registers.

BVD1 I/O 46 This signal is asserted HIGH as the BVD1 signal since a battery is not

used with this product.

BVD2 I/O 45 This output line is always driven to a HIGH state in Memory Mode

since a battery is not required for this product.

CD1, CD2 O 26, 25 These Card Detect pins are connected to ground on the

CompactFlash Card. They are used by the host to determine if the

card is fully inserted into its socket.

CE1, CE2 I 7, 32 The se inpu t sign als are us ed bot h to selec t the car d and to indica te to

the card whether a byte or a word operation is being performed. CE2

always access es the odd byte of the word. CE1 accesses the even

byte or the Odd byte of the word depending on A0 and CE2. A

multiplexing scheme based on A0, CE1, CE2 allows 8 bit hosts to

access all data on D0-D7. See the “Attribute Memory Function” tables

in the CompactFlash Memory Card Product Manual.

CSEL I 39 This signal is not used for this mode.

D15 - D00 I/O 31, 30, 29,

28, 27, 49,

48, 47, 6, 5,

4, 3, 2, 23,

22, 21

These lines carry the Data, Commands and Status information

between the host and the controller. D00 is the LSB of the Even Byte

of the Word. D08 is the LSB of the Odd Byte of the Word.

GND -- 1, 50 Ground.

INPACK O 43 This signal is not used in this mode.

IORD I 34 This signal is not used in this mode.

IOWR I 35 This signal is not used in this mode.

OE I 9 This is an Output Enable strobe generated by the host interface. It is

used to read data from the CompactFlash Card in Memory Mode and

to read the CIS and configuration registers.

RDY/BSY O 37 In Memory Mode this signal is set HIGH when the CompactFlash Card

is ready to accept a new data transfer operation and held LOW when

the card is busy. The Host memory card sock et must provide a pull-up

resistor.

At power up and at Reset, the RDY/-BSY signal is held LOW (busy)

until the CompactFlash Card has completed its power up or reset

funct ion. No acce ss of an y ty pe shoul d be ma de to the Comp actFla sh

Card during this time. The RDY/-BSY signal is held HIGH (disabled

from being busy) whenever the following condition is true: The

CompactFlash Card has been powered up with RESET continuously

disconnected or asserted.

System ACE CompactFlash Solution

64 www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

ACE Controller I/O Pins

Table 42 lists ACE Controller active pins.

REG

Attribute Memory Select I 44 This signal is used during Memory Cycles to distinguish between

Common Memory and Register (Attribute) Memory accesses. HIGH

for Common Memory, LOW for Attribute Memory.

RESET I 41 When the pin is HIGH, this signal resets the CompactFlash Card. The

card is Reset only at power up if this pin is left HIGH or open from

power-up . The card is also reset when the Soft Reset bit in the Card

Configuration Option Register is set.

VCC -- 13, 38 +5 V, +3.3 V power.

VS1

VS2 O 33

40 Voltage Sense Signals. VS1 is grounded so that the CompactFlash

Card CIS can be read at 3.3 vo lts and VS2 is open and reserved by

PCMCIA for a secondary voltage.

WAIT O42 The WAIT signal is driven LOW by the CompactFlash Card to signal

the host to delay completion of a memory or I/O cycle that is in

progress.

WE I 36 This is a signal driv en by the host and used f or strobing memory write

data to the registers of the CompactFlash Card when the card is

configured in the memory interface mode. It is also used f or writing the

conf ig uration re gis ter s.

Write Protect O 24 Memory Mode — the CompactFlash Card does not have a write

protect switch. This signal is held LOW after the completion of the reset

initialization sequence.

Table 41: ACE Flash Signal Descriptions (Continued)

Signal Name Dir. Pin Description

Table 42: ACE Controller Pin Table (IN = input, OUT2 = 2-State O utput, OUT3 = 3-State Output)

Pin Name Pin # I/O Type I/O Supply Rail Termination Description

CLK 93 IN VCCL N/A ACE Controller system clock

RESET 33 IN VCCL Int. Pull-up ACE Controller reset (active LOW; needs to be

acti ve for th ree cl ock cycl es)

STATLED 95 OUT3

(Open-drain) VCCL Ext. Pull-up ACE Controller status LED

ERRLED 96 OUT3

(Open-drain) VCCL Ext. Pull-up ACE Controller error LED; when LOW, this pin

indicates that an error has occurred in the ACE

Controller.

MPCE 42 IN VCCL Int. Pull-up Chip enable (active LOW)

MPWE 76 IN VCCL Int. Pull-up Write enable (active LOW)

MPOE 77 IN VCCL Int. Pull-up Output enable (active LOW)

MPIRQ 41 OUT2 VCCL N/A Interrupt request flag

MPBRDY 39 OUT2 VCCL N/A Data buffer ready flag

MPA00 70 IN VCCL N/A MPU address line 0

MPA01 69 IN VCCL N/A MPU address line 1

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 65

Advance Product Specification 1-800-255-7778

MPA02 68 IN VCCL N/A MPU address line 2

MPA03 67 IN VCCL N/A MPU address line 3

MPA04 45 IN VCCL N/A MPU address line 4

MPA05 44 IN VCCL N/A MPU address line 5

MPA06 43 IN VCCL N/A MPU address line 6

MPD00 66 IN/OUT3 VCCL N/A MPU data line 0

MPD01 65 IN/OUT3 VCCL N/A MPU data line 1

MPD02 63 IN/OUT3 VCCL N/A MPU data line 2

MPD03 62 IN/OUT3 VCCL N/A MPU data line 3

MPD04 61 IN/OUT3 VCCL N/A MPU data line 4

MPD05 60 IN/OUT3 VCCL N/A MPU data line 5

MPD06 59 IN/OUT3 VCCL N/A MPU data line 6

MPD07 58 IN/OUT3 VCCL N/A MPU data line 7

MPD08 56 IN/OUT3 VCCL N/A MPU data line 8

MPD09 53 IN/OUT3 VCCL N/A MPU data line 9

MPD10 52 IN/OUT3 VCCL N/A MPU data line 10

MPD11 51 IN/OUT3 VCCL N/A MPU data line 11

MPD12 50 IN/OUT3 VCCL N/A MPU data line 12

MPD13 49 IN/OUT3 VCCL N/A MPU data line 13

MPD14 48 IN/OUT3 VCCL N/A MPU data line 14

MPD15 47 IN/OUT3 VCCL N/A MPU data line 15

CFA00 4 OUT2 VCCH N/A CompactFlash address line 0

CFA01 142 OUT2 VCCH N/A CompactFlash address line 1

CFA02 141 OUT2 VCCH N/A CompactFlash address line 2

CFA03 139 OUT2 VCCH N/A CompactFlash address line 3

CFA04 137 OUT2 VCCH N/A CompactFlash address line 4

CFA05 135 OUT2 VCCH N/A CompactFlash address line 5

CFA06 134 OUT2 VCCH N/A CompactFlash address line 6

CFA07 132 OUT2 VCCH N/A CompactFlash address line 7

CFA08 130 OUT2 VCCH N/A CompactFlash address line 8

CFA09 125 OUT2 VCCH N/A CompactFlash address line 9

CFA10 121 OUT2 VCCH N/A CompactFlash address line 10

CFD00 5 IN/OUT3 VCCH N/A CompactFlash data line 0

CFD01 6 IN/OUT3 VCCH N/A CompactFlash data line 1

CFD02 8 IN/OUT3 VCCH N/A CompactFlash data line 2

Table 42: ACE Controller Pin Table (IN = input, OUT2 = 2-State O utput, OUT3 = 3-State Output) (Continued)

Pin Name Pin # I/O Type I/O Supply Rail Termination Description

System ACE CompactFlash Solution

66 www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

CFD03 104 IN/OUT3 VCCH N/A CompactFlash data line 3

CFD04 106 IN/OUT3 VCCH N/A CompactFlash data line 4

CFD05 113 IN/OUT3 VCCH N/A CompactFlash data line 5

CFD06 115 IN/OUT3 VCCH N/A CompactFlash data line 6

CFD07 117 IN/OUT3 VCCH N/A CompactFlash data line 7

CFD08 7 IN/OUT3 VCCH N/A CompactFlash data line 8

CFD09 11 IN/OUT3 VCCH N/A CompactFlash data line 9

CFD10 12 IN/OUT3 VCCH N/A CompactFlash data line 10

CFD11 105 IN/OUT3 VCCH N/A CompactFlash data line 11

CFD12 107 IN/OUT3 VCCH N/A CompactFlash data line 12

CFD13 114 IN/OUT3 VCCH N/A CompactFlash data line 13

CFD14 116 IN/OUT3 VCCH N/A CompactFlash data line 14

CFD15 118 IN/OUT3 VCCH N/A CompactFlash data line 15

CFCE1 119 OUT2 VCCH N/A CompactFlash chip enable 1 (active LOW);

CFCE2 138 OUT2 VCCH N/A CompactFlash chip enable 2 (active LOW);

CFREG 3OUT2 V

CCH N/A CompactFlash register select line (active LOW);

this pin is always driven to a 1 but is provided he re

for future compatibility.

CFWE 131 OUT2 VCCH N/A CompactFlash write enable line (active LOW)

CFOE 123 OUT2 VCCH N/A CompactFlash output enable line (active LOW)

CFWAIT 140 IN VCCH N/A CompactFlash memory cycle wait flag (active

LOW)

CFRSVD 133 IN VCCH Ext. Pull-up This pin must be pulled up to VCCH using an

external pull-up resistor.

CFCD1 103 IN VCCH Int. Pull-up CompactFlash card detect line 1 (active LOW)

CFCD2 13 IN VCCH Int. Pull-up CompactFlash card detect line 2 (active LOW)

CFGADDR0 86 IN VCCL Int. Pull-down Configuration addr ess select pin 0

CFGADDR1 87 IN VCCL Int. Pull-down Configuration addr ess select pin 1

CFGADDR2 88 IN VCCL Int. Pull-down Configuration addr ess select pin 2

CFGMODEPIN 89 IN VCCL Int. Pull-up

Configuration mode pin:

•When 0, this pin instructs the ACE Controller to

start the configuration process when the

CFGSTART bit is set in the CONTROLREG

regi ster in the MPU interface.

•When 1, this pin instructs the ACE Controller to

start the configuration process immediately

f ollowing reset.

TSTTDI 102 IN VCCH Int. Pull-up Test JTAG port test data input

TSTTCK 101 IN VCCH N/A Test JTAG port test clock

Table 42: ACE Controller Pin Table (IN = input, OUT2 = 2-State O utput, OUT3 = 3-State Output) (Continued)

Pin Name Pin # I/O Type I/O Supply Rail Termination Description

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 67

Advance Product Specification 1-800-255-7778

TSTTMS 98 IN VCCH Int. Pull-up Test JTAG port test mode select

TSTTDO 97 OUT3 VCCH Ext. Pull-up(1) Test JTAG port test data output

CFGTDO 82 OUT3 VCCL Ext. Pull-up(1) Configuration JTAG test data output

CFGTDI 81 IN VCCL Int. Pull-up Configuration JTAG test data input

CFGTCK 80 OUT2 VCCL N/A Configurat ion JTAG test clock

CFGTMS 85 OUT3 VCCL Ext. Pull-up(1) Configuration JTAG test mode select

CFGPROG 79 OUT3

(Open-drain) VCCL Ext. Pull-up Configuration JTAG PROGRAM pin (active LOW);

this pin is driven LOW when the ACE Controller

PROG instruction is executed.

CFGINIT 78 IN VCCL Int. Pull-up

Configuration JTAG INIT pin (active LOW); this pin

is used to sense when all devices are ready to be

programmed (i.e., INIT = 1 indicates target

device(s) are ready to receive configuration data

and INIT = 0 indicates that the target device(s) are

being cleared and are not ready to be configured)

POR_BYPASS 108 IN VCCH Int. Pull-down

Power-on-reset (POR) bypass input; used in

conjunction with POR_RESET to bypass the

internal POR circuit in favor of using an external

board-level POR circuit; the internal POR circuit is

bypassed when POR_BYPASS = 1; the

POR_BYPASS pin should be hel d a t a sta tic 0 or 1

while the ACE controller is receiving power.

POR_RESET 72 IN VCCH Int. Pull-down

Power-on-reset bypass input; can be used in

conjunction with POR_BYPASS to bypass the

internal POR circuit in favor of using an external

board-le v el POR circuit ; all internal circuitry is reset

when POR_BYPASS = 1 and POR_RESET = 1;

The POR_RESET pulse duration should be at least

1 microsecond long.

POR_TEST 74 OUT2 VCCH N/A P ower-on-reset test output; this pin should be a true

“no connect” on the board. This pin is Low when it

is finish ed res etti ng.

Notes:

1. JTAG 1149.1 requires a pull-up resistor on potentially undriven TDO/TMS signals.

Table 42: ACE Controller Pin Table (IN = input, OUT2 = 2-State O utput, OUT3 = 3-State Output) (Continued)

Pin Name Pin # I/O Type I/O Supply Rail Termination Description

System ACE CompactFlash Solution

68 www.xilinx.com DS080 (v1.4) January 3, 2002

1-800-255-7778 Advance Pr odu ct Specifi cati on

Table 43 lists ACE Controller voltage and ground pins. Table 44 lists ACE Controller no-connect pins.

Table 43: ACE Controller Voltage and Ground Pins

Pin Name Pin Number Description

VCCH 1 High-voltage (3.3V)

source pins

109

128

VCCL 10 Low-voltage (2.5V or

3.3V) source pins

126

GND 9 Ground pins

100

110

111

112

120

129

136

144

Table 44: ACE Controller No-Connect Pins

Pin Na m e Pin

Number Description

NC 2 Pins that must not be

connected to any board-level

signals, including ground and

power planes.

122

124

127

143

System ACE CompactFlash Solution

DS080 (v1.4) January 3, 2002 www.xilinx.com 69

Advance Product Specification 1-800-255-7778

Ordering Information

Revision History

System ACE

Valid Ordering Combinations Description Package Operating Range

XCCACE — TQ144I ACE Controller Chip TQ144 (TA = -40 to +85 °C)

XCCACE128-I 128-Mbit ACE Flash Card CF Type I (TA = -40 to +85 °C)

XCCACE256-I 256-Mbit ACE Flash Card CF Type I (TA = -40 to +85 °C)

Version No. Date Description

1.0 05/18/01 Initial Xilinx release.

1.1 06/04/01 Corrected Table 27, page 35. CFGMODE is 1 after Reset, 0 after MPU start signal.

1.2 07/18/01 Updated.

1.3 12/12/01 Updated.

1.4 01/03/02 Updated Table 2, Figure 20, Figure 22, Figure 32, Figure 36, and Table 42 (last row only).