Rev.3.00 Jun. 28, 2004 page 1 of 10
HD74LV393A
Dual 4-bit Binary Counters REJ03D0333–0300Z
(Previous ADE-205-2 76A (Z))
Rev.3.00
Jun. 28, 2004
Description
The HD74LV393A contain two 4-bit ripple carry binary counters, which can be cascaded to create a single divide-by-
256 counter.
The HD74LV393A is incremented on the high to low transition (negative edge) of the clock input, and each has an
independent clear input. When clear is set high all four bits of each counter is set to a low level. This enables count
truncation and allows the implementation of divide-by-N counter configurations.
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the
low-power consumption extends the battery life.
Features
• VCC = 2.0 V to 5.5 V operation
• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
• All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)
• Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
• Ordering Information
Part Name Package Type Package Code Package
Abbreviation Taping Abbreviation
(Quantity)
HD74LV393AFPEL SOP–14 pin(JEITA) FP–14DAV FP EL (2,000 pcs/reel)
HD74LV393ARPEL SOP–14 pin(JEDEC) FP–14DNV RP EL (2,500 pcs/reel)
HD74LV393ATELL TSSOP–14 pin TTP–14DV T ELL (2,000 pcs/reel)
Note: Please consult the sales office for the above package availability.
HD74LV393A
Rev.3.00 Jun. 28, 2004 page 2 of 10
Function Table
Inputs
CLK CLR Output
XHL
H L No change
L L No change
↑L No change
↓L Count up
Note: H: High level
L: Low level
X: Immaterial
↑: Low to high transition
↓: High to low transition
Pin Arrangement
11
12
9
10
13
14
8
V
CC
2CLK
2CLR
2QA
2QB
2QC
1
2
3
4
5
6
7
1CLK
1CLR
1QA
1QB
1QC
1QD
GND 2QD
(Top view)
HD74LV393A
Rev.3.00 Jun. 28, 2004 page 3 of 10
Absolute Maximum Ratings
Item Symbol Ratings Unit Conditions
Supply voltage range VCC –0.5 to 7.0 V
Input voltage range*1VI–0.5 to 7.0 V
–0.5 to VCC + 0.5 Output: H or LOutput voltage range*1, 2 VO–0.5 to 7.0 VVCC: OFF
Input clamp current IIK –20 mA VI < 0
Output clamp current IOK ±50 mA VO < 0 or VO > VCC
Continuous output current IO±25 mA VO = 0 to VCC
Continuous current through
VCC or GND ICC or
IGND
±50 mA
785 SOPMaximum power dissipation at
Ta = 25°C (in still air)*3PT500 mW TSSOP
Storage temperature Tstg –65 to 150 °C
Notes: The absolute maximum ratings are values, which must not individual ly be exceeded, and furthermore, no two of
which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and outp ut clamp-current ratings are
observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Recommended Operating Conditions
Item Symbol Min Max Unit Conditions
Supply voltage range VCC 2.0 5.5 V
Input voltage range VI05.5V
Output voltage range VO0V
CC VH or L
— –50 µAV
CC = 2.0 V
—–2 V
CC = 2.3 to 2.7 V
—–6 V
CC = 3.0 to 3.6 V
IOH
— –12
mA
VCC = 4.5 to 5.5 V
—50µAV
CC = 2.0 V
—2 V
CC = 2.3 to 2.7 V
—6 V
CC = 3.0 to 3.6 V
Output current
IOL
—12
mA
VCC = 4.5 to 5.5 V
0 200 VCC = 2.3 to 2.7 V
0 100 VCC = 3.0 to 3.6 V
Input transition rise or fall rate ∆t /∆v
020
ns/V
VCC = 4.5 to 5.5 V
Operating free-air temperature Ta –40 85 °C
Note: Unused or floating inputs must be held high or low.
HD74LV393A
Rev.3.00 Jun. 28, 2004 page 4 of 10
Logic Diagram
CK
D
Q
R
CK
D
Q
R
CK
D
Q
R
CK
D
Q
R
QA QB QC QD
CLK
CLR
Timing Diagram
CLK
CLR
QA
QB
QC
QD
HD74LV393A
Rev.3.00 Jun. 28, 2004 page 5 of 10
DC Electrical Characteristics
Ta = –40 to 85°C
Item Symbol VCC (V)*Min Typ Max Unit Test Conditions
2.0 1.5 — —
2.3 to 2.7 VCC × 0.7 — —
3.0 to 3.6 VCC × 0.7 — —
VIH
4.5 to 5.5 VCC × 0.7 — —
2.0 — — 0.5
2.3 to 2.7 — — VCC × 0.3
3.0 to 3.6 — — VCC × 0.3
Input voltage
VIL
4.5 to 5.5 — — VCC × 0.3
V
Min to Max VCC – 0.1 — — IOH = –50 µA
2.3 2.0 — — IOH = –2 mA
3.0 2.48 — — IOH = –6 mA
VOH
4.5 3.8 — —
V
IOH = –12 mA
Min to Max — — 0.1 IOL = 50 µA
2.3 — — 0.4 IOL = 2 mA
3.0 — — 0.44 IOL = 6 mA
Output voltage
VOL
4.5 — — 0.55
V
IOL = 12 mA
Input current IIN 0 to 5.5 — — ±1 µAV
IN = 5.5 V or GND
Quiescent supply
current ICC 5.5 — — 20 µAV
IN = VCC or GND, IO = 0
Output leakage
current IOFF 0——5µAV
I or VO = 0 V to 5.5 V
Input capacitance CIN 3.3 — 1.7 — pF VI = VCC or GND
Note: For conditions shown as Min or Max, use the appropriate values under recommended operatin g conditions.
Switching Characteristics
VCC = 2.5 ± 0.2 V
Ta = 25°C Ta = –40 to 85°C
Item Symbol Min Typ Max Min Max Unit Test
Conditions FROM
(Input) TO
(Output)
50 90 — 40 — CL = 15 pF
Maximum clock
frequency fmax 30 60 — 25 — MHz CL = 50 pF
— 11.8 17.7 1.0 20.5 CL = 15 pF
— 15.1 21.3 1.0 24.5 CL = 50 pF QA
— 13.4 20.3 1.0 23.5 CL = 15 pF
— 16.7 23.9 1.0 27.5 CL = 50 pF QB
— 14.9 22.5 1.0 26.0 CL = 15 pF
— 18.2 26.1 1.0 30.0 CL = 50 pF QC
— 16.2 24.2 1.0 28.0 CL = 15 pF
tPLH/tPHL
— 19.5 27.8 1.0 32.0 CL = 50 pF
CLK
QD
— 10.8 14.8 1.0 17.0 CL = 15 pF
Propagation
delay time
tPHL — 14.2 17.4 1.0 20.0
ns
CL = 50 pF CLR Qn
Setup time tsu 6.0 — — 6.0 — ns CLR L before CLK ↓
5.0 — — 5.0 — CLR HPulse width tw5.0 — — 5.0 — ns
CLK H or L
HD74LV393A
Rev.3.00 Jun. 28, 2004 page 6 of 10
Switching Characteristics (cont)
VCC = 3.3 ± 0.3 V
Ta = 25°C Ta = –40 to 85°C
Item Symbol Min Typ Max Min Max Unit Test
Conditions FROM
(Input) TO
(Output)
75 120 — 65 — CL = 15 pFMaximum clock
frequency fmax 45 65 — 35 — MHz CL = 50 pF
— 8.6 13.2 1.0 15.5 CL = 15 pF
— 11.1 16.7 1.0 19.0 CL = 50 pF QA
— 10.2 15.8 1.0 18.5 CL = 15 pF
— 12.7 19.3 1.0 22.0 CL = 50 pF QB
— 11.7 18.0 1.0 21.0 CL = 15 pF
— 14.2 21.5 1.0 24.5 CL = 50 pF QC
— 13.0 19.7 1.0 23.0 CL = 15 pF
tPLH/tPHL
— 15.5 23.2 1.0 26.5 CL = 50 pF
CLK
QD
— 7.9 12.3 1.0 14.5 CL = 15 pF
Propagation
delay time
tPHL — 10.4 15.8 1.0 18.0
ns
CL = 50 pF CLR Qn
Setup time tsu 5.0 — — 5.0 — ns CLR L before CLK ↓
5.0 — — 5.0 — CLR HPulse width tw5.0 — — 5.0 — ns
CLK H or L
VCC = 5.0 ± 0.5 V
Ta = 25°C Ta = –40 to 85°C
Item Symbol Min Typ Max Min Max Unit Test
Conditions FROM
(Input) TO
(Output)
125 170 — 105 — CL = 15 pFMaximum clock
frequency fmax 85 115 — 75 — MHz CL = 50 pF
— 5.8 8.5 1.0 10.0 CL = 15 pF
— 7.3 10.5 1.0 12.0 CL = 50 pF QA
— 6.8 9.8 1.0 11.5 CL = 15 pF
— 8.3 11.8 1.0 13.5 CL = 50 pF QB
— 7.7 11.2 1.0 13.0 CL = 15 pF
— 9.2 13.2 1.0 15.0 CL = 50 pF QC
— 8.5 12.5 1.0 14.5 CL = 15 pF
tPLH/tPHL
— 10.0 14.5 1.0 16.5 CL = 50 pF
CLK
QD
— 5.4 8.1 1.0 9.5 CL = 15 pF
Propagation
delay time
tPHL — 6.9 10.1 1.0 11.5
ns
CL = 50 pF CLR Qn
Setup time tsu 4.0 — — 4.0 — ns CLR L before CLK ↓
5.0 — — 5.0 — CLR HPulse width tw5.0 — — 5.0 — ns
CLK H or L
Operating Characteristics
CL = 50 pF
Ta = 25°C
Item Symbol VCC (V) Min Typ Max Unit Test Conditions
3.3 — 12.0 —Power dissipation capacitance CPD 5.0 — 15.0 — pF f = 10 MHz
HD74LV393A
Rev.3.00 Jun. 28, 2004 page 7 of 10
Noise Characteristics
CL = 50 pF
Ta = 25°C
Item Symbol VCC = (V) Min Typ Max Unit Test Conditions
Quiet output, maximum
dynamic VOL
VOL (P) 3.3 — 0.4 0.8 V
Quiet output, minimum
dynamic VOL
VOL (V) 3.3 — –0.4 –0.8 V
Quiet output, minimum
dynamic VOH
VOH (V) 3.3 — 3.2 — V
High-level dynamic input
voltage VIH (D) 3.3 2.31——V
Low-level dynamic input
voltage VIL (D) 3.3 ——0.99V
Test Circuit
L*
Note: C includes the probe and jig capacitance.
Measurement point
C
L
HD74LV393A
Rev.3.00 Jun. 28, 2004 page 8 of 10
t
PHL
V
OH
V
OL
0 V
V
CC
0 V
V
CC
V
OH
V
OL
V
OH
V
OL
V
OH
n
V
OL
t
PHL
t
PLH
10 %
90 %
CC
50 % V
CC
50 % V
CC
50 % V
CC
50 % V
CC
50 % V 10 %
90 %
CLR CLK
t
r
t
f
0 V
V
CC
0 V
V
CC
t
w
CC
50 % V
CC
50 % V
CLR
Q
n
Q
n
Q
n
Q
CLK
10 %
t
f
CC
50 % V
10 %
t
f
t
w
t
r
t
PHL
t
PLH
t
su
t
w
CC
50 % V
CC
50 % V
10 %
90 %
90 % 90 %
t
r
•
Waveforms
−
1
•
Waveforms
−
2
1. Input waveform: PRR ≤ 10 MHz, Zo = 50 Ω, t ≤ 3 ns, t ≤ 3 ns
2. The output are measured one at a time with one transition per measurement.
Notes:
rf
HD74LV393A
Rev.3.00 Jun. 28, 2004 page 9 of 10
Package Dimensions
Package Code
JEDEC
JEITA
Mass
(reference value)
FP-14DAV
—
Conforms
0.23 g
*Ni/Pd/Au plating
*0.20 ± 0.05
*0.40 ± 0.06
0.70 ± 0.20
0.12
0.15
0˚ – 8˚
M
0.10 ± 0.10
2.20 Max
5.5
10.06
1.42 Max
14 8
17
10.5 Max
+ 0.20
– 0.30
7.80
1.15
1.27
As of January, 2003
Unit: mm
Package Code
JEDEC
JEITA
Mass
(reference value)
FP-14DNV
Conforms
Conforms
0.13 g
0˚ – 8˚
1.27
14 8
17
0.15
0.25
M
1.75 Max 3.95
*0.20 ± 0.05
8.65
9.05 Max
*0.40 ± 0.06
0.14+ 0.11
– 0.04
0.635 Max 6.10+ 0.10
– 0.30
0.60+ 0.67
– 0.20
1.08
*Ni/Pd/Au plating
As of January, 2003
Unit: mm
HD74LV393A
Rev.3.00 Jun. 28, 2004 page 10 of 10
Package Code
JEDEC
JEITA
Mass
(reference value)
TTP-14DV
—
—
0.05 g
*Ni/Pd/Au plating
0.50 ± 0.10
0˚ – 8˚
*0.15 ± 0.05
6.40 ± 0.20
0.10
1.10 Max
0.13 M
0.65
17
14 8
4.40
5.00
5.30 Max
0.83 Max
*0.20 ± 0.05
0.07
+0.03
–0.04
1.0
As of January, 2003
Unit: mm
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