FEATURES 5V + 10% write and erase JEDEC-standard EEPROM commands Minimum 1,000/10,000 write/erase cycles Fast access time: 100/120/150ns Sector erase architecture - 16 equal sectors of 128k bytes each ~ Sector erase time: 50ms typical Auto Erase and Auto Program Algorithms - Automatically erases any one of the sectors or the whole chip with Erase Suspend capability - Automatically programs and verifies data at specified addresses Status Register feature for detection of program or erase cycle completion Low VCC write inhibit < 3.2V Software and hardware data protection . oeoeee GENERAL DESCRIPTION The MX29F1610 is a 16-mega bit Fiash memory organized as either 1M wordx16 or 2M bytex8. The MX29F 1610 includes 16-128KB(131,072) blocks or 16- 64KW(65,536) blocks. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29F 1610 is packaged in 48-pin TSOP or 44-pin SOP. For 48-pin TSOP, CE2 and RAY/BY are extra pins compared with 44-pin SOP package. This is to optimize the products (such as solid- state disk drives or flash memory cards) contro! pin budget. PWD is available in 48 -pin TSOP for low power environment. All the above three pins(CE2,RY/BY and PWD) plus one extra VGC pin are not provided in 44-pin SOP. itis designed ta be reprogrammed and erased in- system or in-standard EPROM rogrammers. The standard MX29F 1610 offers access times as fast as 100ns, allowing operation of high-speed microprocessors without wait. To eliminate bus contention, the MX29F1610 has separate chip enables(CE1 and CE2), output enable (OE), and write enable (WE) controis. MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29F 1610 uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility. SSB LMM Any MxX29F1610 16M-BIT(2M x 8/4M x 16}. cag SINGLE VOLTAGE FLASH EEPROM Page program operation ~ Internal address and data latches for 128 bytes/64 words per page ~ Page programming time: 3ms typical - Byte programming time: 16us in average * Low power dissipation - 50mA active current - 100HA standby current CMOS and TTL compatible inputs and outputs Two independently Protected sectors Deep Power-Down Input - 1pA ICC typical * industry standard surface mount packaging - 48 lead TSOP, TYPE I - 44 lead SOP To allow for simple in-system reprogrammability, the MX29F1610 does not require high input voltages for programming. Five-volt-only commands determine the operation of the device. Reading data out of the device is similar to reading from an EPROM. MXIC Flash technology reliably stores memory contents even after 1,000/10,000 erase and program cycies. The MXIC's cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and !ow internal electric fields for erase and programming operations produces reliable cycling. The MX29F 1610 uses a 5V + 10% VCC supply to perform the Auto Erase and Auto Program algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin frarn -1V to VCC +1V. PIN: PMGZ60 REV.1.7, Sep 25, 1996Mic PIN CONFIGURATIONS 48 TSOP(TYPE I) (12mm x 20mm) 44 SOP(500mil} we | io 44 we RY/BY 1 : a A1B 4g Ag Al6 2 ao AI? 3 42 AB AIS 1 3 46 ar | 4 arf. Ag aa : 45 AG 5 40 Alo A12 6 a AS 6 39 Att Att 7 2 ad 7 38 At A10 a 2 A3 8 37 A3 ag 9 40 A2 ob S e AIG AB bia) 39 AI to 2 45 AGS AQe 1 38 ao ta ats WP 12 MX29F 1610 37 m1 3 MI Be We - | 13 CEI 2 Y ws aYTE Ais ta 36 GNO | 13 32 | GND AN? 15 = oF | 14 arf. OSA AT 16. 3 oo | 15 0 5 46 17 $ Qs 16 29 ais AS 18 31 Qi 7 28 C6 Aad 1B 30 as | 18 az | 13 a3 a 29 az 19 ze | as AY 22 28 aio -| 2 25 ai2 AO 23 pa a3 21 24 as vec 24 25 ai 22 ag | vec (NORMAL TYPE) 48 PDIP NC [Na] NC nc l2 a7] NC WE {3 46} WP PWD 48 1 Aig [4 45] Atg ayTe =| 47 2 Al? | 5 44 ag GND 46 73 az | 4a} Ag QisA+ | 45 4 ag (7 2] At a7 | 44 5 * Qt 43 5 as [8 ar] oan os. | 42 SF Ad 9 40]. Ate O13 41 8 AB 170 gaa] Ar as | 40 9 A2 [tt ~ 38 Al4 a2 33 10} ai fre r av}. Als Qa | 38 1" ao 113 g 36 AI6 vec oF MX28F 1610 42 cei ita Sos | BYTE a 2 13 eno jis H aa} GND or (| 34 is OE {16 ga} OtSAt a2 | 33 16 Qo 1/17 a2 a7 ag 32 17 as [te 34 aw Qi yu +8 a {19 30, a6 a8 | 30 19 ag }20 20} aia aq "| 29 20 : OE 28 2t a2 {at 2a fo as cnn te 2 aio [22 ar, az CE: | 26 os & 38 26 oH ce2 | 25 24 1 a 25 (REVERSE TYPE) PIN DESCRIPTION SYMBOL PIN NAME SYMBOL PIN NAME AQ-A19 = Address Input WE Write Enable Input Q0-Q14 = Data Input/Output RY/BY Ready/Busy Output Q15/A-1 Q15(Word mode)/LSB addr.(Byte mode) WP Sector Write Profect Input CE1/CE2 Chip Enable Input BYTE Word/Byte Selection Input PWD Deep Power- Down Input vec Power Supply OE Output Enable Input GND Ground Pin 59-2MIS , MxXa9F 1 Sto BLOCK DIAGRAM f poor renee ann sca ements ap een eo i ee ce | We | | } I i WRITE : GEuGE | CONTROL | | PROGRAMERASE i iy es | STATE OE 5.7, INPUT ' HIGH VOLTAGE book away ip | rosie | : | MACHINE { Bw teen od (SM) i EVIE meen ee ; i ooo. | rf i co ' (COMMAND INTERFACE! | i a x | |! RegsTER | i & | Mxzarieto | 4 (aR) i | | ADDRESS | . | 8 FLASH | ns a rer ap | LATCH Fo poo om | PP argat PS, pw} 2 ARRAY ARRAY pote ney | Pa t t Aoais Tb AND | COMMAND , BUFFER | | ! | DATA : | | i | DECODER i : Pe be ee - ; i | ae L : sense |. PSM bop | : 1 | DATA). i AMPLIFIER, ma | COMMAND | ; | DATALATCH i 1 oe ae ee ee | | ele ; i a c 1 1 PT PAGE i 1 ot ;PRogRAM [| | |pataates t eo ! | | 4s I : j i ii | | I 1 oe een: ovata VO BUFFER fe eed fe pnt ere elMX28F16810 Table1,.PIN DESCRIPTIONS SYMBOL AO - AiS TYPE INPUT NAME AND FUNCTION ADDRESS INPUTS: for memory addresses. Addresses are internally latched during a write cycle. QO - Q7 Q8 - Q14 INPUT/OUTPUT INPUT/OUTPUT LOW-BYTE DATA BUS: Input data and commands during Command Interface Register(CIR) write cycles. Outputs array,status and identifier data in the appropriate read mode. Floated when the chip is de-selected or the outputs are disabled. HIGH-BYTE DATABUS: Inputs data during x 16 Data-Write operations. Outputs array, identifier data in the appropriate read mode; not used for status register reads. Floated when the chip is de-selected or the outputs are disabled QIS/A -1 CEI/CE2 INPUT/OUTPUT INPUT Selects between high-byte data INPUT/OUTPUT(BYTE = HIGH) and LSB ADDRESS(BYTE = LOW) CHIP ENABLE INPUTS: Activate the device's control logic. Input buffers, decoders and sense amplifiers. With either CE1 or CE2 high, the device is de- selected and power consumption reduces to Standby level upon completion of any current program or erase operations. Both CE1,CE2 must be low to select the device. CE2 is not provided in 44-pin SOP package. All timing specifications are the same for both signals. Device selection occurs with the latter falling edge of CE1 or CE2. The first rising edge of CE1 or CE2 disables the device. PWD INPUT POWER-DOWN: Puts the device in deep power-down mode. PWDis active low; PWD high gates normal operation. PWD also locks out erase or program operation when active low providing data protection during power transitions. INPUT OUTPUT ENABLES: Gates the device's data through the output buffers during a read cycle OE is active low. INPUT WRITE ENABLE: Controls writes to the Command Interface Register(CIR). WE is active tow. RY/BY OPEN DRAIN OUTPUT READY/BUSY: Indicates the status of the internal Write State Machine(WSM). When low it indicates that the WSM is performing a erase or program operation. RY/BY high indicate that the WSM is ready for new commands, sector erase is suspended or the device is in deep power-down mode. RY/BY is always active and does not float to tristate off when the chip is deselected or data output are disabled. INPUT WRITE PROTECT: Top or Bottom sector can be protected by writing a non- volatile protect-bit for each sector. When WP is high, all sectors can be programmed or erased regardless of the state of the protect-bits. The WP input buffer is disabled when PWD transitions low(deep power-down mode). BYTE INPUT BYTE ENABLE: BYTE Low places device in x8 mode. Ail data is then input or output on Q0-7 and Q8-14 float. AddressQ15/A-1 selects between the high and low byte. BYTE high places the device in x16 mode, and turns off the Q15/ A-1 input buffer. Address AO, then becomes the lowest order address. Vcc DEVICE POWER SUPPLY (5V+10%) GND GROUND 59-4M=Iif | MxX28F1610 BUS OPERATION Flash memory reads, erases and writes in-system via the local CPU. Allbus cycles to or from the flash memory conform to standard microprocessor bus cycles. Table 2.1 Bus Operations for Word-Wide Mode (BYTE = VIH) Mode Notes) PWD] GE1|GE2 | OE | WE | Ao 1 A1/ A9 | Q0-a7 | @8-014 | Q15/A-1 | RY/BY { Read 12.7 | vie; VIL) vit jviL | ViH | xX | x | x pDOUT | DOUT DOUT | Xx OutputDisable | 1,6,7 | VIH | VIL | VIL |VIH| VIH | X | X | X HighZ HighZ HighZ | X : Standby 167] VIH|; VL] VIH| Xx ! X .x | X 4 x HighZ . HighZ Highz X | VIH | VIL VIH_ | VIH | DeepPower-Down: 1,3 | VIL| X | X i xX | xX |X | xX | Xx HighZ HighZ High? VOH I ManufacturenD 48 i WH] VIL) VIL | vit | VIK | ViL | VIL} VID] = C2H o0H == 0B} VOH DevicelD i 4,8 | VIH | VIL P VIL) VIL | VIR | VIH , VIL VID FiH OOH 0B ' VOH Write 15.6] VIH| Vi; vit TVH] we ix | x | X DIN DIN DIN | Xx : : \ ! Table2.2 Bus Operations for Byte-Wide Mode (BYTE = VIL) Mode Notes! PWD! GE1/CE2|O& | WE | Ao | A1 | AS | Q0-Q7 | G8-Q14 QI15/A-1 | RY/BY Read 1,2,7,9| VIH | VIL] VIL | VIL | VIH x x x DOUT | HighZ VILAVIH x 4 4 T OutputDisable | 16,7; VIH: VIL] VIL iVIH| VIN | X = XxX | X HighZ | HighZ x x rm Standby 1,6.7 | VIH | VIL | VIH | X xX |x +x |] xX HighZ HighZ X x VIH | VIL ; VIH | VIH | DeepPower-Down . 13 VIL Xx x x Xx x x x HighZ Highz x VOH | j { \ManufactureriD | 4.8 | VIH | VIL | VIL] VIL | VIR | VIL | VIL; VID) C2H | HighZ VIL VOH | DeviceiD 48 VIH | VILE Vi | VIL | VIHE ] VIH | VIL of VID FIH HighZ VIL VOH Write 115.6 | VIR | VIL | VIL PVIHO VIL x x x DIN HighZ VIL/VIH x i | ! bo NOTES : 1.X can be ViH or VIL for address or control pins except for RY/BY which is either VOL orVOH. __ 2.RY/BY output is open drain. When the WSM is ready, Erase is suspended or the device is in deep power-down mode, RY/BY will be at VOH if itis tied to VCC through a 1K ~ 100K resistor. When the RY/BY at VOH is independent of OE while a WSM operation is in progress. 3.PWD at GND + 0.2V ensures the lowest deep power-down current. 4, AO and At at VIL provide manufacturer 1D codes. AQ at VIH and A1 at VIL provide device 1D codes. AO at VIL, A1 at VIH and with appropriate sector addresses provide Sector Protect Code.(Refer to Table 4) 5. Commands for different Erase operations, Data program operations or Sector Protect operations can only be successfully completed through proper command sequence. __ _. 6.While the WSM is running. RY/BY in Level-Mode stays at VOL until ail operations are complete. RY/BY goes to VOH when the WSM is not busy or in erase suspend mode. 7. RY/BY may be at VOL while the WSM ts busy performing various operations. For example, a status register read during a write operation. 8. VID = 11.5V- 12.5V. 9, Q15/A-1 = VIL, QO -Q7 =DO0-D7 out. Q15/A-1 = VIH, QO - Q7 = DS -D45 out. 59-5WRITE OPERATIONS Commands are written to the COMMAND INTERFACE REGISTER (CIR) using standard microprocessor write timings. The CIR serves as the interface between the microprocessor and the internal chip operation. The CIR can decipher Read Array, Read Silicon ID, Erase and Program command. in the.event of a read command, the CIR simply points the read path at either the array or the silicon ID, depending on the specific read command given. For a program or erase cycle, the CIR informs the write state machine that a program or erase has been requested. During a program cycle, the write state machine will control the program sequences and the CIR MxX29F171610 will only respond to status reads. During a sector/chip erase cycle, the CIR will respond to status reads and erase suspend. After the write state machine has completed its task, it will allow the CfR to respond to its full command set. The CIR stays at read status register made until the microprocessor issues another valid command sequence. Device operations are selected by writing commands into the CIR. Table 3 below defines 16 Mbit flash family command. N TIONS | Command Read/ Silicon | Page/Byte] Chip Sector Erase Erase Read Clear Sequence Reset | [0 Readj Program | Erase Erase | Suspend] Resume Status Reg [Status Reg Bus Write 4 4 4 6 6 3 3 4 3 Cycles Req'd First Bus Adar 5555H 5555H | 5555H | 5555+ 5555H | 5555 | 5555H AS555H 5RS55H _. Write Cycie Data AAH AAH AAH AAH AAH AAH AAH AAH AAH | Second Bus Addr | 2AAAH |] 2AAAHT 2AAAH | 2AAAH | 2AAAH | 2AAAH] 2AAAH] 2AAAH 2AAAH | Write Cycle Data 55H 55H 55H 55H 55H 55H 55H 55H 55H | Third Bus Addr 5555H. 5555H 5555H 5555H 5555H 5555H 5555H 5555H 5555H Write Cycle Data FOH 90H AOH 80H 80H BOH DOH 70H 50H | Fourth Bus Addr RA 00H/01H PA 5555H 5555H xX | Read/Write Cycld Data RAD C2H/F 1H PD AAH AAH SRD P.. - - Fifth Bus Addr 2AAAH | 2AAAH . | Write Cycle Data 55H 55H t . t T ~ 1 | Sixth Bus Addr 5555H SA | ' Write Cycle Data 10H 30H 'COMMAND DEFINITIONS(continue Table 3.) Command Sector Sector Verify Sector Sleep Abort Sequence Protection | Unprotect Protect Bus Write 6 6 4 3 3 Cycles Req'd iFirst Bus Adar 5555H 5555H 5555H 55554 5555+ Write Cycle Data AAH AAH AAN AAH AAH [Second Bus Addr 2AAAH 2AAAH 2AAAH 2AAAH 2ASAH Write Cycle Data 55H 55H 55H 55H 55H Third Bus Addr 5555H 5655H 5555H 5555H 5555H Write Cycle Data 60H 60H 90H COH EOH Fourth Bus Addr 5555H 5555H * Read/Write Cycief Data AAH AAH 2H Fifth Bus Addr 2AAAH 2AAAH : Write Cycle ata SoH Bor Sixth Bus Addr | SA" sas | Write Cycle Data 20H 40H Notes: 1.Address bit A15 -- A19 = X = Don't care for all addrass commands except for Program Address(PA) and Sector Address(SA). 5555H and 2AAAH address command codes stand for Hex number starting from AO to A714. 2. Bus operations are defined in Table 2. 3. RA = Address of the memory focation to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse SA = Address of the sector to ba erased. The combination of A16 -- A19 will uniquely select any sector. 4. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data ts latched on the rising edge of WE. SRD = Data read from status register. 5 Only Q0-Q7 command data is taken, Q8-Q15 = Dan't cara. * Refer to Table 4, Figure 12. -* Only the top and the bottom sectors have protect- bit feature. SA = (A19,A18.A17,A416) = O000B or 11118 is valid. 59-7MI MxX29F1610 DEVICE OPERATION SILICON ID READ The Silicon iD Read mode allows the reading out of a binary code from the device and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VID (11.5V~12.5V) on address pin A9. Two identifier bytes may then be sequenced from the device outputs by toggling address AO from VIL to VIH. All addresses are don't cares except AO and A1. The manufacturer and device codes may also be read via the command register, for instances when the MX29F1610 is erased or programmed in a system without access to high voltage on the AQ pin. The command sequence is illustrated in Table 3. Byte 0 (AO=VIL) represents the manfacturer's code (MXIC=G2H) and byte 1 (A0=VIH) the device identifier code (MX29F1610=F 1H). To terminate the operation, it is necessary to write the read/reset command sequence into the CIR. ode Table 4. MX29F1610 Silion ID Codes and Verify Sector Protect Code Type DQ, | DG. A, | Aig | A | Aye | Ar | Ay | Code(HEX)) DQ, | DQ, | DA, A ,; DQ,; DQ, ; DA, Manufacturer Code x | x Xx KX | VIET VEIL G2H* 1 1 G 0 0 0 1 0 IMX29F 1610 Device Code | X x x X | VIL | VIH FIH* i 1 1 1 0 0 0 1 Verify Sector Protect Sector Address*** VIH | VIL CeH"* 1 1 9 o 0 0 1 0 * MX29F1610 Manufacturer Code = C2H, Device Code = F1H when BYTE = VIL MX29F1610 Manufacturer Code = 00C2H, Device Code = 00F1H when BYTE = VIH * Outputs C2H at protected sector address, OOH at unprotected scetor address. *Only the top and the bottom sectors have protect-bit feature. Sector address = (A19, A18,A17,A16) = OOO0B or 1111BMEIGS READ/RESET COMMAND The read or reset operation is initiated by writing the read/ reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the CIR contents are altered by a valid command sequence. The device will automatically power-up in the read/reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific.timing parameters. The MX29F 1610 is accessed like an EPROM. When cE and O are low and WE. is. high the data stored at the memory location determined by the .address pins is asserted on the outputs. The outputs.are put in. the high impedance state whenever CE or OE is-high. This dual line control gives designers flexibility in preventing bus contention. CE stands for the combination of CE1 and GE2 in 48-pin TSOP package.. CE stands for CE1 in 44-pin SOP package. Note. that the read/reset command is not valid when pragram or erase is in progress. PAGE PROGRAM To initiate Page program mode, a three-cycle command sequence is required. There are two " unlock" write cycles. These are followed by writing the page program command-A0H. Any attempt to write to the device without the three-cycle command sequence will not start the internal Write State Machine(WS), no data will be written to the device. After three-cycle command sequence is given. a byte(word) load is performed by applying a low pulse on the WE or CE input with CE or WE tow (respectively) and GE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Maximum of 128 bytes of data may be loaded into each page by the same procedure as outlined in the page program section below. MxX2S9F1610 BYTE-WIDE LOAD/WORD-WIDE LOAD Byte(word) loads are used to enter the 128 bytes(64 words) of a page to be programmed or the software codes tor data protection. A byte laad(word load) is performed by applying a low pulse.on the WE or GE input with CE or WE low (respectively) and GE high. The address is latched on the falling edge of CE or WE, whichever occurs ast The data is latched by the first rising edge of CE or E. Either byte-wide load or word-wide load is determined(Byte = VIL or VIH is latched) on the falling edge of the WE(or CE) during the 3rd command write cycle. PROGRAM Any page to be programmed should have the page in the erased state first, ie. performing sector erase is suggested before page programming can be performed..: The device is programmed on a page basis. ff a byte(word) of data within a page is to be changed, data for the entire page can be loaded into the device. Any byte(word) that is not toaded during the programming of its page will be still in the erased state (i.e. FFH). Once the bytes of a page are loaded into the device, they are simultaneously programmed during the internal programming period. After the first data byte(word) has been loaded into the.device, successive bytes(words) are entered in the same manner. Each new byte(word) to be programmed must have its high to low transition of WE (or CE) within 30s of the low to high transition of WE (or CE) of the preceding byte(word). A6 to A19 specify the page address, i.e., the device is page-aligned on 128 bytes(64 words)boundary. The page address must be valid during each high to low transition of WE or CE. A-1 to A5 specify the byte address within the page, AO to A5 specify the word address withih the page. The byte(word) may be loaded in any order, sequential loading is not required. if a high to low transition of CE or WE is not detected whithin 100us of the last low to high transition, the load period will end and the internal programming period will start. The Auto page program terminates when status on DQ7 is 't' at which time the device stays at read status register mode until the CIR contents are altered by a valid command sequence. (Refer to table 3,6 and Figure 1,7,8} 59-9CHIP ERASE Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the set-up* command-80H. Two more unlock write cycles are then followed by the chip erase command- 10H. Chip erase does not require the user to program the device prior to erase. The automatic erase begins on the rising edge of the iast WE pulse in the command sequence and terminates when the status on DQ7 is "1" at which time the device stays at read status register mode. The device remains enabled for read status register mode until the CIR contents are altered by a valid command sequence. (Refer to table 3,6 and Figure 2,7,9) _- Table 5. MX29F 1610 Sector Address Table (Byte-Wide Mode) A19 | ais | A17 | A16 | Address Range[A19, -1] SAG ; 0 0 0 0 QOQ000H--07 FFFFH SA1 |) 0 | 6 0 1 O20000H--03FFFFH SA2 | 0 0 1 0 040000H--05FFFFH SA3 | 0] 6 1 1 060000H--07FFFFH 080000H--O9FFFFH SA15/ 1 1/1 1 4E0Q00H--1-FFFFFH SECTOR ERASE Sector erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the set-up command-80H. Two more "unlock" write cycies are then followed by the sector erase command-30H. The sector address is latched on the falling edge of WE, while the command (data) is latched on the rising edge of WE. MxX298F1610 Sector erase does not require the user to program the device prior to erase. The system is not required to provide any controls or timings during these operations. The automatic sector erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the status on DQ7 is "1" at which time the device stays at read status register mode. The device remains enabled for read status register mode until the CIR contents are altered by a valid command sequence.(Refer to table 3,6 and Figure 3,4,7,9)) ERASE SUSPEND This command only has meaning while the the WSM is executing SECTOR or CHIP erase operation, and therefore will only be responded to during SECTOR or CHIP erase operation. After this command has been executed, the CIR will initiate the WSM to Suspend erase operations, and then return to Read Status Register mode. The WSM will set the DQ6 bit to a 1. Once the WSM has reached the Suspend state,the WSM will set the DQ7 bit toa "1", At this time, WSM allows the CIR to respond to the Read Array, Read Status Register, Abort and Erase Resume commands only. in this mode, the CIR will not resopnd to any other comands. The WSM will continue to run, idling in the SUSPEND state, regardless of the state of all input controt pins, with the exclusion of PWD. PWD tow will immediately shut down the WSM and the remainder of the chip. ERASE RESUME This command will cause the CIR to clear the suspend state and set the DQ6 to a 0', but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in ali other conditions. 59-10Mic READ STATUS REGISTER The MXIC'si6 Mbit flash famity contains a status register which may be read to determine when a program or erase operation is complete, and whether that operation completed successfully. The status register may be read at any time by writing the Read Status command to the CIR. After writing this command, all subsequent read operations output data from the status register until another valid command sequence is written to the CIR. A Read Array command must be written to the CIR to return to the Read Array mode. The status register bits are output on DQ2 - DQ7(table 6) whether the device is in the byte-wide (x8) or word-wide (x16) mode for the MX29F 1610. In the word-wide mode the upper byte, BQ(8:15) is set to OOH during a Read Status command. In the byte-wide mode, DQ(8:14) are tri-stated and DQ15/A-1 retains. the low order address function. DQ0-DQ1 is set to OH in either x8 or x16 mode. it should be noted that the contents of the status register are latched on the falling edge of OF or CE whichever occurs last in the read cycle. This prevents possibie bus errors which might occur if the contents of the status register change while reading the status register. CE or OE must be toggled with each subsequent status read, or the compietion of a program or erase operation will not be evident. The Status Register is the interface between the microprocessor and the Write State Machine (WSM). When the WSM is active, this register will indicate the status of the WSM, and will atso hold the bits indicating whether or not the WSM was successful in performing the desired operation. The WSM sets status bits four through seven and clears bits six and seven, but cannot clear status bits four and five. If Erase fait or Program fait status bit is detected, the Status Register is not cleared until the Clear Status Register command is written. The MX29F 1610 automatically outputs Status Register data when read after Chip Erase, Sector Erase, Page Program or Read Status Command write cycle. The default state of the Status Register after powerup and return from deep power-down mode is (DQ7, DQ6, DOS, DQ4) = 1000B. DQ3 = 0 or 1 depends on sector-protect status, can not be changed by Clear Status Register Command or Write State Machine. DQ2 = 0 or 1 depends on Sleep status, During Sleep mode or Abort mode DQ2 is set to "1"; DQ2 is reset to "0" by Read Array command. MxX29F1610 CLEAR STATUS REGISTER The Eraes fail status bit (DQ5) and Program fail status bit (DQ4) are set by the write state machine, and can only be reset by the system software. These bits can indicate various failure conditions(see Table 6). By allowing the system software to control the resetting of these bits, several operations may be performed {such as cumulatively programrning several pages or erasing multipl blocks in squence). The status register may then be read to determine if an error occurred during that programming or erasure series. This adds flexibility to the way the device may be programmed or erased. Additionally, once the program(erase) fail bit happens, the program (erase) operation can not be performed further. The program(erase) faii bit must be reset by system software before further page program or sector (chip) erase are atiempted. To clear the status register. the Clear Status Register command is written to the CIR. Then, any other command may be issued to the CIR. Note again that before a read cycle can be initiated, a Read command must be written to the CIR to specify whether the read data is to come from the Array, Status Register or Silicon ID. 59-11MX298F1620 TABLE 6. MX29F1610 STATUS REGISTER ! T + STATUS NOTES | DQ7 | DQ8/ DQ5 bas | 0Q2 IN PROGRESS PROGRAM 1.2, 6,7 0 Q 0 0/1 : of ERASE 1.3, 6,7 0 0 0 Of | O/T SUSPEND (NOT COMPLETE) 1,4, 6.7 0 1 0 Of! O (COMPLETE) ~ 1 1 Q O/t | O/1 COMPLETE PROGRAM 1,2, 6,7 1 0 0 oft | Off | ERASE : oe 1,3, 6,7 1 0 0 ot o/1 | RAIL : PROGRAM 1,5, 6,7 1 0 0 Ot} Off ERASE 1,5, 6,7 1 0 t oft | ast - AFTER CLEARING STATUS REGISTER 6,7 1 0 0 9 | , Oost * _ NOTES: ' 4, 0Q7: WRITE STATE MACHINE STATUS ' 4= READY, 0= BUSY DQ6 : ERASE SUSPEND STATUS 1 = SUSPEND, 0 = NO SUSPEND DQ5 : ERASE FAIL STATUS 1 = FAIL IN ERASE, 0 = SUCCESSFUL ERASE DQ4 : PROGRAM FAIL STATUS 1 = FAIL IN PROGRAM, 0 = SUCCESSFUL PROGRAM DQ3 : SECTOR-PROTECT STATUS 1 = SECTOR 0 OR/AND 15 PROTECTED 0 = NONE OF SECTOR PROTECTED DQ2 : SLEEP STATUS 1 = DEVICE IN SLEEP STATUS 0 = DEVICE NOT IN SLEEP STATUS DQ1 - 6 = RESERVED FOR FUTURE ENHANCEMENTS. These bits are reserved for future use ; mask them out when polling the Status Register. . PROGRAM STATUS is for the status during Page Programming or Sector Unprotect mode. . ERASE STATUS is for the status during Sector/Chip Erase or Sector.Protection mode. . SUSPEND STATUS is for both Sector and Chip Erase mode . . FAIL STATUS bit(DQ4 or DQ5) is provided during Page Program or Sector/Chip Erase modes respectively. . DQ3 = 0 ort depends on Sector-Protect Status. DQ2 = 0 or 1 depends on whether device is in the Sleep mode or not . " Once in the Sieep mode. DQ2 is set to "1", and is reset by read array command only.- NOOR wWH 59-12HARDWARE SECTOR PROTECTION The MX29F 1610 features sector protection. This feature will disable both program and erase operations in either the top or the bottom sector (0 or 15). The sector protection feature is enabled using system software by the user(Referto table 3). The device is shipped with both sectors unprotected. Alternatively, MXIC may protect sectors in the factory prior to shipping the device. SECTOR PROTECTION To activate this mode, a six-bus cycle operation is required. There are two uniock' write cycles. These are followed by writing the setup' command. Twe more unlock write cycles are then followed by the Lock Sector command - 20H. Sector address is latched on the falling edge of CE or WE of the sixth cycle of the command sequence. The automatic Lock operation begins on the rising edge of the last WE pulse in the command sequence and terminates when the Status on DQ7 is '1' at which time the-device stays at the read status register mode. The device remains enabled for read status register mode until the CIR contents are altered by a valid command sequence (Refer to table 3,6 and Figure 10,12 ). VERIFY SECTOR PROTECT To verify the Protect status of the Top and the Bottom sector, operation is initiated by writing Silicon ID read command into the command register. Following the command write, a read cycle from address XXXOH retrieves the Manufacturer code of C2H. A read cycle from XXX1H returns the Device code F1H. A read cycle from appropriate address returns information as to which sectors are protected. To terminate the operation, it is necessary to write the read/reset command sequence into the CIR. (Refer to table 3,4 and Figure 12) A few retries are required if Protect status can not be verified succsstully after each operation. SECTOR UNPROTECT Htis also possible to unprotect the sector ,same as the first MX28F16170 five write command cycles in activating sector protection mode followed by the Unprotect Sector command - 40H, the automatic Unprotect operation begins on the rising edge of the last WE pulse in the command sequence and terminates when the Status on DQ7 is '1' af which time the device stays at the read status register mode.(Refer to table 3,6 and Figure 11,12) The device remains enabled for read status register mode until the CIR contents are altered by a valid command sequence. Either Protect or Unprotect sector mode is accomplished by keeping WP high, i.e. protect-bit status can only be changed with a valid command sequence and WP at high. When WP is high, all sectors can be programmed or erased regardless of the state of the protect-bits. Protect- bit status will not be changed during chip/sector erase operations. With WP at VIL, anly unprotected sectors can be programmed or erased. DEEP POWER-DOWN MODE The MXIC's16 Mbit fiash family supports a typical ICC of pA in deep power-down mode. One of the target markets for these devices is in protable equipment where the power consumption of the machine is of prime importance. When PWD is a logic tow (GND + 0.2V), all circuits are turned off and the device typically draws 1A of ICC current. During read modes, the PWD pin going low deselects the memory and places the output drivers in a high impedarice state. Recovery from the deep power-down state, requires a minimum of 700 nanoseconds to access valid data. During erase or program modes, PWD iow will abort either erase or program operation: The contents of the memory are no fonger valid as the data has been corrupted by the PWD function. As in the read mode above, allinternai circuitry is turned off to achieve the 1A current level. PWD transitions to VIL or turning power off to the device will clear the status register. PWD pin is not provided in 44-pin SOP package. 59-13SLEEP MODE The MX29F1610 features two software controtled low- power modes : Sleep and Abort modes. Sleep made is allowed during any current operations except that once Suspend commandisissued, Sleep commandis ignored. Abort mode is excuted only during Page Program and Chip/Sector Erase mode. To activate Sleep mode; a three-bus cycle operation is required. The COH command (Refer to table 3) puts the device in the Sleep mode. Once in the Sleep mode and with CMOS input level applied, the power of the device is reduced to deep power-down current levels. The only power consumed is diffusion leakage, transistor sub- threshold conduction, input leakage, and oufput leakage. The Sleep command atiows the device to COMPLETE Current operations before going into Sleep mode. Once current operation is done, device stays at read status register mode, RY/BY returns to ready state. The status _ registers are not reset during sleep command. Program orerase fail bit may have been setif during program/erase _ mode the device retry exceeds maximum count. : , a During Sleep mode. the status ragisters, Silicon ID codes -" remain valid and can still be read. The Device Sleep Status bit - DQ2 will indicate that the device in the sleep mode. Writing the Read Array command wakes up the device out of sleep mode. DQ2 is reset to "0" and Device returns to standby current level. ABORT MODE To activate Abort mode, a three-bus cycle operation is required. The EOH command (Refer to table 3) only stops Page program or Sector /Chip erase operation currently in progress and puts the device in Sleep mode. But unlike the sleep command, the program or erase operation will not be completed. Since the data in some page/sectors is no longer valid due to an incomplete program or erase operation, the program fail (DQ4) or erase fail (DO5)bit will be set. After the abort command is executed and with CMOS input jevel applied, the device current is reduced to the MxX29F1610 same level as in deep power-down or sleap modes. Device stays at read status registet mode, RY/BY returns to ready state. During Abort mode, the status registers, Silicon 1D codes remain valid and can still be read. The Device Sleep Status bit - DQ2 will indicate that the device in the sleep mode. Similar to the sleep mode, A read array-command MUST be written to bring the device out of the abort state without incurring any wake up latency. Note that once device is waken up, Clear status register mode is required before a program or erase operation can be executed, RY/BY PIN AND PROGRAM/ERASE POLLING RY/BY is a full CMOS output that provides a hardware method of detecting page program and sector erase completion. It transitions to VIL after a program or erase command sequence is written to the MX29F1610, and returns to VOH when the WSM has finished executing the imtemat algorithm. RY/BY can be connected to the interrupt input of the system CPU or controller. It is active at ail times, not tristated if the CE or OE inputs are brought to VIH. RY/ BY is also VOH when the device is in erase suspend or deep power-down modes. RY/BY pin is not provided in 44-pin SOP package. DATA PROTECTION The MX29F 1610 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically resets the internal state machine in the Read Array mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transitions or system noise. 59-14Mic LOW VCC WRITE INHIBIT To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than VLKO(= 3.2V , typically 3.5V). If VCC < VLKO, the command register is disabled and all internal program/ erase circuits are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. Itis the user's responsibility to ensure that the control pins are logically correct to prevent unintentional write when VCC is above VLKO. WRITE PULSE "GLITCH" PROTECTION Noise pulses of less than 10ns (typical) on CE or WE will not initiate a write cycle. LOGICAL INHIBIT Writing is inhibited by holding any one of OE = VIL,CE = VIH or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one. Mx29F1610 59-15M=Ic Figure 1. AUTOMATIC PAGE PROGRAM FLOW CHART | Write Datla AAH Address 5555H } Write Data 55tl Address 2AAAH Le | Write Data AOH Address 5555H | Yo. ae | Write Program DetaAddruss |- pone a en ae Ee ee, L Read Status Reqister Fe C Page Program Completed Program Error ) ce ee te on eee NO 3 Xx ' t fES a Te t Ta Gontnue Other Operations ES Program I Do Clear 5.9. Mode First another page? _-- ~ me oe NO Operation Done, Device Stays At Read S.R Modal Note : S.R. Stands for Status Register Mx29F1670 59-16MxX29F1670 Figure 2, AUTOMATIC CHIP ERASE FLOW CHART { START ) NL - Write Data AAH Address 5555H L. a ' Whie Data 55H Address ZAAAH AN. | | t | ___ | | ! | i | White Data 8GH Adcress 5555H ] | | Write Data 5SH Address ZAAAH Ad Write Data 10H Address 5555H 5 a | i ' Read Status Register ! 7 Le 1 NO a t a eo, / NOU To Execute ~~_YES i . SR7 = TS, Susp Moge aad Erase Suspand Fiow (Figure 4.) a * ee we i ; VES i A ao i a wh \ a NO ' < srs=0 De ne a A - : ~~ YES ; PE Yo | 1 f ; \ a \ : { Chip Erase Compisted ) { Erase Error \ | | Ne eT 4 ' ' | f Anti ! Operation Done To Continue Other | i Device Stays at Operations, Do Clear i } \ | Read S A. Mode | S.R. Mode First \ i { | | 59-17Mx29F1610 Figure 3. AUTOMATIC SECTOR ERASE FLOW CHART f a : f START } Wrte Data AAH Address 5555 White Data 55H Address 2AAAH t bed | | Write Data 80H Address 5555H VY Write Data AAH Address 5555H y | Write Data 55H Address 2AAAH i Write Data 30H Sector Address Read Status Regist | | | . | TAN UN me, << , NO To Execute yes ~. SRT = 1 - ~ < Suspend Erase ? a " we a ' | i | YES f y i me i << ses 0 ON NO _ =0 _ -y | so a | se ' YES ! | __ 1 { \ oo oN, | i Sector Erase Completed } i Erase Error | Sa ___. on | Operation Done j Te Continue Other Device Stays al Operations, De Clear Read SR Mode S.R. Mode First 4 Erase Suspenc Flow (Figure 4} bo. 59-1840] Figure 4. ERASE SUSPEND/ERASE RESUME FLOW CHART fo mo START } eo tL. ~ | Write Data AAH Address 55551 { tw ____-__-_- inte Data SSH Address 2AAAH we _____. t White Data BOH Address 55554 | poe A i Read Status Register LL YES YES ~~ f a ( Erase Suspend ( Erase has completed } Erage Error 4 NN. . _ wt a pre EN i - ~ t Operation Done. | Write Data AAH Address SSSSH pe To Gentinua Other Dewice Stays ai Cperations, De Ciear JY L. Reay SR. au S.R, Mode ! SR Mode First [ Wrte Data 55H Address 2AAAH [ Write Data FOH Address 5555H | oe _4 [ Read Array ' | aa a | << Reading End ? oo | ail ' YES t i ee ce Wrie Data AAH Aadress 5555H | pn Write Data 5544 Aaudras5 2AAAH | i... Whte Data DOH Address 55554 | f \ LL Continue Erase \ at _ 59-19ELECTRICAL SPECIFICATIONS NOTICE: Stresses greater than those listed under ABSOLUTE ABSOLUTE MAXIMUM RATINGS MAXIMUM RATINGS may cause permanent damage to the RATING VALUE device. This is stress rating only and functional operationai Ambient Operating Temperature 0C to 70C sections of this specification is not implied. Exposure to - Se : . : absolute maximum rating conditions for extended period may Storage Temperature -65C to 125C affect reliability. . . 7 . NOTICE: Applied Input Voltage -0.5 to 7.0V Specifications contained within the following tables are subject . . . to change. Applied Output Voltage -0.5V to 7.0V VCC to Ground Potential -0.5V to 7 OV AQ -0.5V to 13.5V CAPACITANCE TA = 25C, f = 1.0 MHz SYMBOL PARAMETER MIN. TYP. MAX. UNIT CONDITIONS CIN Input Capacitance 14 pF VIN = OV COUT Output Capacitance 16 pF VOUT = 0V |. SWITCHING TEST CIRCUITS note [ DEVICE | o 1.8KQ UNDER - to oe nan Pi coon +5V TEST a mee vo | : ro ae < + DIODES = IN3064 | - 6.2KQ v ! OR EQUIVALENT CL = 100 pF Including jig capacitance SWITCHING TEST WAVEFORMS 24V \ y ee SF wy 20V 2.0V GN ; SCY TEST POINTS esx LX. Oa oav4oZ4X\ O45V _. f ee INPUT OUTPUT } AG TESTING: Inputs are driven at 2.4V for a iogic "1" and 0.454 for a iogic "0". i Input pulse rise and fall times are < 10ns. 59-20DC CHARACTERISTICS = 0C to 70C, VCC = 5Vi10% MX29F1640 SYMBOL PARAMETER NOTES MIN. TYP. MAX, UNITS TEST CONDITIONS lit Input Load 1 +10 pA VCC = VCC Max _ Current ; a VIN = VCC or GND ILO Output Leakage 1 +10 uA VCC = VCC Max Current VIN = VCC or GND ISB1 VCC Standby 1 50 100 bA VEC =VCC-Max Current(CMOS} CE1, CE2, PWD = VCC +0.2V ISB2 VGC Standby 2 4 mA VCC =VEC-Max Current(FTL} CE1, CE2, PWD = VIH iDP VCC Deep 1 1 20 BA PWD = GND + 0.2V Power-Down Current ICC1 VCC Read 1 50 60 mA VCC = VCC Max. Current CMOS: CEt, CE2 = GND + 0.2V BYTE = GND + 0.2V or VCC + 0.2V Inputs.=. GND +0.2V or VCC + 0.2V TIL: CE1, CE2 = VIL, BYTE = VIL or VIH Inputs = VIL or VIH, f = 10MHz, IOUT = 0 mA Icc2 VCC Read 1 30 35 mA VOC = VEC Max, Current CMOS: CE1, CE2 = GND + 0.2V BYTE = VCC 0.2V or GND + 0.2V inputs = GND + 0.2V or VCC + 0.2V TTL: CE1, CE2 = VIL. BYTE = VIH or VIL Inputs = VIL or VIH, f = SMHz, 1OUT = OmA icc3 VCC Erase 1,2 5 10 mA CE1. CE2 = VIH Suspend Current BLock Erase Suspended IcC4 VCC Program 1 30 50 mA Program in Progress Current ICC5 VCC Erase Current 1 30 50 mA Erase in Progress VIL Input Low Voltage 3 -0.3 0.8 Vv ~ VIH Input High Voltage 4 2.4 VCC+0.3 OV VOL Output Low Voltage 0.45 Vv iOL = 2.4mA VOH Output High Voltage 24 Vv IOH = -400pA ~MIS MxX29F71610 DC CHARACTERISTICS = 0C to 70C, VCC = 5V+10%(CONTINUE P.21) NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0V, T = 25C. These currents are valid for all product versions (package and speeds}. 2. 1CC3 is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum af ICC3 and iCC1/2. 3. VIL min, = -1.0V for pulse width < 50ns. VIL min. = -2.0V for pulse width < 20ns. 4. VIH max. = VCC + 1.5V for pulse width < 20ns. If VIH is over the specified maximum value, read operation cannot be guaranteed. AC CHARACTERISTICS ~READ OPERATIONS @9F1610-10 = 29F 1610-12: 29F 1610-15 SYMBOL DESCRIPTIONS MIN. MAX. MIN. MAX. MIN. MAX. UNIT CONDITIONS tACC Address to Output Delay 100 120 150 ons CE=OE=VIL CE Eto OutputDelty = it00s( sists 10E OE toOutputDelay Sw ms EN OF CE Highto Output Delay =o 55S OH Address toOutputhod = ngs BERL tBACC BYTE to Output Delay 100 120 150 ons CE= OE=VIL 1BHZ BYTE Low to Output in High Z 55 55 70 ns CE=VIL tOPR . Deep Power-Down Recovery 700 700 800 ns TEST CONDITIONS: NOTE: * Input pulse tevels: 0.45V/2.4V 1. tDF is defined as the time at which the output achieves the Input rise and fall times: 10ns apen circuit condition and data 1s no longer driven. * Outputload: 1TTL gate+100pF (Including scope and jig) Reference levels for measuring timing: 0.8V, 2.0V 9-22Figure 5. READ TIMING WAVEFORMS ADDRESSES CE (1) OE WE DATA OUT vec PWD NOTE: 1.CE is defined as the latter of CE1 or CE2 going Low or the first of CEt or CE2 going High. 2.For real world application, BYTE pin should be either static high(word mode) or static low(byte mode); Device and _ 5 Standby ; Outputs Enabled Standby Vec Power-up address selection Data valid Vee Paower-down VH eT ADDRESSES STABLE viL Vit eo y a / \ VIL _/ \ f So VI poo * foo \ um Ve = = DF - VIH . / \ va a OE ~ CE ~ VOH - OH ~= HIGH Z 7 7 vs HIGH Z { Data out valid , VOL SA L - : tacc - 50V / \ _/ XK GND = 1OPR ~ VIH f \ Le VIL oo dynamic switching of BYTE pin is not recommended. 59:23Mai. Mx2SF16410 Figure 6. BYTE TIMING WAVEFORMS | | Vi ' ADDRESSES = ADDRESSES STABLE , i vit | | i Vid aoe ~ ~ xz _/ \ / Le cea | Viet | _ ( \ / \ - vit 7 \ aS Le OF (DF = ~ a 1BACC - VIH a a 2 _ 10E -_ / > A __. ' BYTE VL ane | ~ IGE ~ m ICH pacar) SH? Maat wc z DATA( DQ?7} Data Output Dats Output vOL VAXA \ ) ; ) ) tacc 1BHZ VOH ~- _ DATA(DQ8-DQ15) HIGH Z fff. bala Ouinn \ biG z VOL V / NOTE: 1.CE is defined as the latter of CE1 or CE2 going Low or the first of CE1 or GE2 going High. 59-24AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS 29F 1610-10 29F 1610-12 29F 1610-15 SYMBOL DESCRIPTION MIN. MAX. MIN. MAX. MIN. MAX. UNIT twe Write Cycle Time 100 120 150 ns tAS Address Setup Time 0 0 0 ns tAH Address Hoid Time 45 50 60 ns tDS Data Setup Time 45 50 60 ns tDH Data Hold Time 10 10 10 ns tOES Qutput Enable Setup Time 0 0 0 ns 1CES CE Setup Time 0 0 0 ns tGHWL Read Recover TimeBefore Write 0 0 0 tCS CE Setup Time 0 0 0 ns tCH CE Hold Time 0 0 0 ns twP Write Pulse Width 45 50 60 ns tWPH Write Pulse Width High 50 50 50 ns tBALC Byte(Word) Address Load Cycle 0.3 30 03 30 0.3 30 us {BAL Byte(Word) Address Load Time 100 4 00 100 ys tSRA Status Register Access Time 100 120 150 ns tCESR CE Setup before S.A. Read 100 100 100 as tWHAL WE High to RY/BY Going Low 100 100 100 ns tWHALP WE High to RY/BY Going Low 100.1 100.1 100.1 us {in Page Program mode) tPHWL PWD High Recovery to WE Going Low 1 1 1 us tVCS VCC Setup Time 2 2 2 us 59-25Poi ay Figure 7. COMMAND WRITE TIMING WAVEFORMS MX2@F 1670 WE ADDRESSES DATA (D/Q) vec PWD NOTE: \ ~ tH we LO \ tOES - ics 1 -_ ~ +E ta - errr. . ~ IGHWL > L . IWR 2 - we - - 1DS 1DH HIGH 2 ~ wes <= > _/ ~- - tPHWiL 1.BYTE pin is treated as Address pin. All-timing specifications for BYTE pin are the same as those for address pin. 2.BYTE pin is sampled on the falling edge of WE or CE during the 3rd command write bus cycle; for real world application, BYTE pin should be either static high{word made) or static low(byte mode). 59-26Figure 8. AUTOMATIC PAGE PROGRAM TIMING WAVEFORMS \ Vf AO~AS 55H AAH BSH BH X Word offset \ Cee oe Ad (byte mode oniy) a \ \/ \/ AG~AI4 =x 55H A 2AH XX SSH -Page Address tAS tAH _ ~~" ~~ AIS~AIS ~~ ~ tBALC tBAL . -_ > - - CE(1} __ my a 7 r ITN Loo \, / \ \ / \ / \ / \ f \ , f WP IWPH Lo <_ = ~<ip WE 7, sf on ns oC n / f% \ / \ \ \ j xX yy / \ i \ t 'GES a f \ / OE J {WHRLP od RY/BY NS (DS -_ ton ~ SFA DATA RAH YS 55H} { AOH ) S Wete \__ Of (Last wie = sro } ~ \ SN Ne \_Data__/ we \_ tPHWL ~ <_< PWD NOTE: 1.CE is defined as the latter of CE1 or CE2 going low, or the first of CE4 or CE2 going high. 2.Please refer to page 9 for detad page program operation. 59-27Figure 9. AUTOMATIC SECTOR/CHIP ERASE TIMING WAVEFORMS AO~A14 AIS AI6~A19 1CESA -_ > | CE# { * fo / ~~! ra a fo rs \__f \y VF eee / _Y TS . a mp tWPH Peo, WE Pr. fo. aN my fy fo ee Bs \ Vo? \_ sf VL / YU it . tCES _- ' / \ i | of Ve I (WHRE - RY/BY NS _ we 10 - ~ iSRA LON NE pm TTT 6 eo | DATA +{ AAH }{ 55H { , ( \ 4 i Se | ~ 80H }{ ARH {55H }~<30HOH}-4_ SAD. + tPHWL ~~ : 1 / | PWD | | | NOTES: | : 1,CE# is defined as the latter of CE or CE2 going low, or the first of CE1 or CE2 going high. 2."*" means "don't care" in this diagram. 3."SA" mearis Sector Adddress. 59-28Figure 10. SECTOR PROTECTION ALGORITHM LO { eant \ LSCNT=G J cl _ oe a White Data AAH Address 5555H t | Wrne Data 55H Aadress 2AAAH Y | Write Data 60H Adcress 5555 ! Write Data AAW Adcress SS55H | oo | 1. Wote Oata 55H Addrese 2AAAH | | increment PLSCNT, | ee ; to To Protect Sector Agan a oe Write Data 20H, Sector Agdress* ! ___-_~ ~-_____! oT Read Status Register Protect Sector Operation Terminated oN a To YES [ | qn Venty Protect | Very Protect Slatus Flow Sans? | 1 Figure 12) : NO YES : / Device Stays at Ny ~ 7 { . ) Sector Protected,Operation | Q Read S R. Mode $ | } KEE Dene, Device Stays at Verify Sector Protect Mode I Only the Top or the Bottom Sector Address is vaild in this feature. i.e, Sector Address = (A19.A18.A17,A16) = 00008 or 1171B \ | | t NOTE : | | | 59-29MxX26F1610 Figure 11. SECTOR UNPROTECT ALGORITHM ~, START. PLSCNT=0 / eee y t Write Data AAH Agdress 5555H ' oy Write Data 55H Address 2AAAH | i White Data 60H Address 5555H Write Data AAH Address 5555 ' Write Data 55H Address 2AAAM Y Write Data 40H. Sector Address ' a | Read Status Register ; a, eI Unprotect Sector Operation Terminated Increment PLSCNT, To Unprotect Sector Again a NO i neon ah Te t << went Provect Verily Protect Status Flow Status (Figure 12) Noe | Ne NO | Device Fated | i NO { Device Stays at \ Read S.A. Mode f tre NOTE : Only the Top or the Bottom Sector Address is vaild in this feature, i.e. Sector Address = (A19,A18,A17,A16) = OOOOB or 1111B 1 ~ a [ Data <2 + > A a _. yee Sector Unprotecied, Operation. | Done. Device Stays at ! Varity Sector Protect Mode Le eer eeMx29F16140 Figure 12. VERIFY SECTOR PROTECT FLOW CHART ~ i \ STAAT ) 1 Write Data AAH. Address 5555H ne Write Data 55H. Address 2AAAH Ld _ Write Data 90H, Address 5555H ., { Ptoect Status Read } NO * 1. Protect Status: Data Outputs C2H as Protected Sector Verified Code. 2. Sepecified address wilt be either (A19,A18,A17,A16,AT AQ) = (000010) or (171110), tha rest of the address pins are don't care. 3. Silicon 1D can be read via this Flow Chart. Refer to Table 4 Data Outputs 00H as Unprotected Sector Verified Code. 59-31MxIc Figure 13. COMMAND WRITE TIMING WAVEFORMS(Alternate CE Controlled) MxX29F 1670 WE nn , vA ~ tOES ~ - ws OE Saal ~ / ae we . ~ CO f~ tGHWL \ i ICPH \ a ~ - \ Top = - ADDRESSES DATA HIGH Z f~ OE GH ey vec _S wes > PWD ~ iPHWL NOTE BYTE pin should be either static high(word mode) or static low(byte mode). 59-32AO~A5 A-t {(Byte Mode Only) AG~A14 Ai5~A18 WE CE() OE RYBY DATA PWD i \ f X 2H XX 56H A A po poo Page Address 1.CE is defined as the latter of CE1 or CE2 going low, or tne first of CE1 or CE2 going high. 2.Please refer to page 9 for detail page program operation. we _ ~ IBALC i =P ' a. / f ~ as \ __/ \ \ ff \\ ff \ y f \ Sf re tCPH iBAL < ~~ ~<a . _ . a _ a VIN LDN SN PRN SNS / Ve _/ NL SU VS Ye / Ices = & J \ / eS Ne tWHRLP i = PP : \ NS J (DS iow { Pe - ~ SRA. | - po TON T*NWTTN TNee | fo AAH 55H i {Write Last Write . __ (aan HC set) \ AoH ) Spa JA ata / _ SRO | tPHWL. | ~- - | / | | i | NOTE: | | ' 59-33ERASE AND PROGRAMMING PERFORMANCE | LIMITS | PARAMETER MIN. TYP. MAX. UNITS ' Chip/Sector Erase Time 50 ms 300 Page Programming Time : 3 2 ms : | Chip Programming Time 33 66 sec | Erase/Program Cycles | 1,000/10,000 Cycles 7 a ai Byte Program Time 16 HS } : \ & { a a. LATCHUP CHARACTERISTICS NIN, | MAX. Input Voltage with respect to GND on all pins except 1/0 pins -1.0V i 13.5V Input Voltage with respect to GND on all /O pins -1.0V Vcc + 1.0V Current -100mA +100mA incitudes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time. Note. Revision History Revision # Description 1.7 fast access time : 100ns