LTC2225
1
2225fa
FEATURES
DESCRIPTIO
U
TYPICAL APPLICATIO
U
■
Sample Rate: 10Msps
■
Single 3V Supply (2.7V to 3.4V)
■
Low Power: 60mW
■
71.3dB SNR
■
90dB SFDR
■
No missing codes
■
Flexible Input: 1V
P-P
to 2V
P-P
Range
■
575MHz Full Power Bandwidth S/H
■
Clock Duty Cycle Stabilizer
■
Shutdown and Nap Modes
■
Pin Compatible Family
125Msps: LTC2253 (12-Bit), LTC2255 (14-Bit)
105Msps: LTC2252 (12-Bit), LTC2254 (14-Bit)
80Msps: LTC2229 (12-Bit), LTC2249 (14-Bit)
65Msps: LTC2228 (12-Bit), LTC2248 (14-Bit)
40Msps: LTC2227 (12-Bit), LTC2247 (14-Bit)
25Msps: LTC2226 (12-Bit), LTC2246 (14-Bit)
10Msps: LTC2225 (12-Bit), LTC2245 (14-Bit)
■
32-Pin (5mm × 5mm) QFN Package
12-Bit, 10Msps
Low Power 3V ADC
The LTC
®
2225 is a 12-bit 10Msps, low power 3V A/D
converter designed for digitizing high frequency, wide
dynamic range signals. The LTC2225 is perfect for de-
manding imaging and communications applications with
AC performance that includes 71.3dB SNR and 90dB
SFDR for signals well beyond the Nyquist frequency.
DC specs include ±0.3LSB INL (typ), ±0.15LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.25LSB
RMS
.
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.6V
logic.
A single-ended CLK input controls converter operation. An
optional clock duty cycle stabilizer allows high perfor-
mance at full speed for a wide range of clock duty cycles.
Typical INL, 2V Range
APPLICATIO S
U
■
Wireless and Wired Broadband Communication
■
Imaging Systems
■
Spectral Analysis
■
Portable Instrumentation
–
+
INPUT
S/H
CORRECTION
LOGIC
OUTPUT
DRIVERS
12-BIT
PIPELINED
ADC CORE
CLOCK/DUTY
CYCLE
CONTROL
FLEXIBLE
REFERENCE
D11
•
•
•
D0
CLK
REFH
REFL
ANALOG
INPUT
2225 TA01
OV
DD
OGND
CODE
0
–1.0
INL ERROR (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
1024 2048
2225 G01
–0.6
0.6
0.8
0.2
3072 4096
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
LTC2225
2
2225fa
ABSOLUTE AXI U RATI GS
W
WW
U
PACKAGE/ORDER I FOR ATIO
UUW
OVDD = VDD (Notes 1, 2)
Supply Voltage (V
DD
) ................................................. 4V
Digital Output Ground Voltage (OGND) ....... –0.3V to 1V
Analog Input Voltage (Note 3) ..... –0.3V to (V
DD
+ 0.3V)
Digital Input Voltage .................... –0.3V to (V
DD
+ 0.3V)
Digital Output Voltage ................ –0.3V to (OV
DD
+ 0.3V)
Power Dissipation............................................ 1500mW
Operating Temperature Range
LTC2225C ............................................... 0°C to 70°C
LTC2225I.............................................–40°C to 85°C
Storage Temperature Range ..................–65°C to 125°C
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution ●12 Bits
(No Missing Codes)
Integral Differential Analog Input ●–1.1 ±0.3 1.1 LSB
Linearity Error (Note 5)
Differential Differential Analog Input ●–0.7 ±0.15 0.7 LSB
Linearity Error
Offset Error (Note 6) ●–12 ±212 mV
Gain Error External Reference ●–2.5 ±0.5 2.5 %FS
Offset Drift ±10 µV/°C
Full-Scale Drift Internal Reference ±30 ppm/°C
External Reference ±5 ppm/°C
Transition Noise SENSE = 1V 0.25 LSB
RMS
CO VERTER CHARACTERISTICS
U
ORDER PART NUMBER
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
T
JMAX
= 125°C, θ
JA
= 34°C/W
EXPOSED PAD IS GND (PIN 33)
MUST BE SOLDERED TO PCB
32 31 30 29 28 27 26 25
9 10 11 12
TOP VIEW
UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
13 14 15 16
17
18
19
20
21
22
23
24
8
7
6
5
4
3
2
1AIN+
AIN–
REFH
REFH
REFL
REFL
VDD
GND
D8
D7
D6
OVDD
OGND
D5
D4
D3
VDD
VCM
SENSE
MODE
OF
D11
D10
D9
CLK
SHDN
OE
NC
NC
D0
D1
D2
33
QFN PART MARKING
LTC2225CUH
LTC2225IUH
2225*
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
LTC2225
3
2225fa
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SNR Signal-to-Noise Ratio 5MHz Input ●69.8 71.3 dB
70MHz Input 70.7 dB
SFDR Spurious Free Dynamic Range 5MHz Input ●76 90 dB
2nd or 3rd Harmonic 70MHz Input 85 dB
SFDR Spurious Free Dynamic Range 5MHz Input ●82 90 dB
4th Harmonic or Higher 70MHz Input 90 dB
S/(N+D) Signal-to-Noise Plus Distortion Ratio 5MHz Input ●69.5 71.3 dB
70MHz Input 70.4 dB
I
MD
Intermodulation Distortion f
IN1
= 4.3MHz, f
IN2
= 4.6MHz 90 dB
DY A IC ACCURACY
U
W
PARAMETER CONDITIONS MIN TYP MAX UNITS
V
CM
Output Voltage I
OUT
= 0 1.475 1.500 1.525 V
V
CM
Output Tempco ±25 ppm/°C
V
CM
Line Regulation 2.7V < V
DD
< 3.4V 3 mV/V
V
CM
Output Resistance –1mA < I
OUT
< 1mA 4 Ω
I TER AL REFERE CE CHARACTERISTICS
UU U
(Note 4)
A ALOG I PUT
UU
The ● denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IN
Analog Input Range (A
IN+
–A
IN–
) 2.7V < V
DD
< 3.4V (Note 7) ●±0.5V to ±1V V
V
IN,CM
Analog Input Common Mode(A
IN+
+A
IN–
)/2 Differential Input (Note 7) ●1 1.5 1.9 V
Single Ended Input (Note 7) ●0.5 1.5 2 V
I
IN
Analog Input Leakage Current 0V < A
IN+
, A
IN–
< V
DD
●–1 1 µA
I
SENSE
SENSE Input Leakage 0V < SENSE < 1V ●–3 3 µA
I
MODE
MODE Pin Leakage ●–3 3 µA
t
AP
Sample-and-Hold Acquisition Delay Time 0 ns
t
JITTER
Sample-and-Hold Acquisition Delay Time Jitter 0.2 ps
RMS
CMRR Analog Input Common Mode Rejection Ratio 80 dB
LTC2225
4
2225fa
DIGITAL I PUTS A D DIGITAL OUTPUTS
UU
The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
POWER REQUIRE E TS
WU
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
DD
Analog Supply Voltage (Note 9) ●2.7 3 3.4 V
OV
DD
Output Supply Voltage (Note 9) ●0.5 3 3.6 V
I
VDD
Supply Current ●20 23 mA
P
DISS
Power Dissipation ●60 69 mW
P
SHDN
Shutdown Power SHDN = H, OE = H, No CLK 2 mW
P
NAP
Nap Mode Power SHDN = H, OE = L, No CLK 15 mW
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
LOGIC INPUTS (CLK, OE, SHDN)
V
IH
High Level Input Voltage V
DD
= 3V ●2V
V
IL
Low Level Input Voltage V
DD
= 3V ●0.8 V
I
IN
Input Current V
IN
= 0V to V
DD
●–10 10 µA
C
IN
Input Capacitance (Note 7) 3 pF
LOGIC OUTPUTS
OV
DD
= 3V
C
OZ
Hi-Z Output Capacitance OE = High (Note 7) 3 pF
I
SOURCE
Output Source Current V
OUT
= 0V 50 mA
I
SINK
Output Sink Current V
OUT
= 3V 50 mA
V
OH
High Level Output Voltage I
O
= –10µA 2.995 V
I
O
= –200µA●2.7 2.99 V
V
OL
Low Level Output Voltage I
O
= 10µA 0.005 V
I
O
= 1.6mA ●0.09 0.4 V
OV
DD
= 2.5V
V
OH
High Level Output Voltage I
O
= –200µA 2.49 V
V
OL
Low Level Output Voltage I
O
= 1.6mA 0.09 V
OV
DD
= 1.8V
V
OH
High Level Output Voltage I
O
= –200µA 1.79 V
V
OL
Low Level Output Voltage I
O
= 1.6mA 0.09 V
LTC2225
5
2225fa
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above V
DD
, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above V
DD
without latchup.
Note 4: V
DD
= 3V, f
SAMPLE
= 10MHz, input range = 2V
P-P
with differential
drive, unless otherwise noted.
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 7: Guaranteed by design, not subject to test.
Note 8: V
DD
= 3V, f
SAMPLE
= 10MHz, input range = 1V
P-P
with
differential drive.
Note 9: Recommended operating conditions.
TI I G CHARACTERISTICS
UW
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
s
Sampling Frequency (Note 9) ●1 10 MHz
t
L
CLK Low Time Duty Cycle Stabilizer Off ●40 50 500 ns
Duty Cycle Stabilizer On ●5 50 500 ns
(Note 7)
t
H
CLK High Time Duty Cycle Stabilizer Off ●40 50 500 ns
Duty Cycle Stabilizer On ●5 50 500 ns
(Note 7)
t
AP
Sample-and-Hold Aperture Delay 0ns
t
D
CLK to DATA delay C
L
= 5pF (Note 7) ●1.4 2.7 5.4 ns
Data Access Time After OE↓C
L
= 5pF (Note 7) ●4.3 10 ns
BUS Relinquish Time (Note 7) ●3.3 8.5 ns
Pipeline 5 Cycles
Latency
Typical DNL, 2V RangeTypical INL, 2V Range
8192 Point FFT, fIN = 5.1MHz,
–1dB, 2V Range
TYPICAL PERFOR A CE CHARACTERISTICS
UW
CODE
0
–1.0
INL ERROR (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
1024 2048
2225 G01
–0.6
0.6
0.8
0.2
3072 4096
CODE
0
–1.0
DNL ERROR (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
1024 2048
2225 G02
–0.6
0.6
0.8
0.2
3072 4096
FREQUENCY (MHz)
0
AMPLITUDE (dB)
–60
–40
–20
0
4
2225 G03
–80
–100
–70
–50
–30
–10
–90
–110
–120 1235
LTC2225
6
2225fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
8192 Point FFT, fIN = 70.1MHz,
–1dB, 2V Range Grounded Input Histogram
SNR vs Input Frequency, –1dB,
2V Range
8192 Point 2-Tone FFT,
fIN = 4.3MHz and 4.6MHz,
–1dB, 2V Range
SFDR vs Input Frequency, –1dB,
2V Range
SNR and SFDR vs Sample Rate,
2V Range, fIN = 5MHz, –1dB
FREQUENCY (MHz)
0
AMPLITUDE (dB)
–60
–40
–20
0
4
2225 G04
–80
–100
–70
–50
–30
–10
–90
–110
–120 1235
FREQUENCY (MHz)
0
AMPLITUDE (dB)
–60
–40
–20
0
4
2225 G05
–80
–100
–70
–50
–30
–10
–90
–110
–120 1235
CODE
70000
60000
50000
40000
30000
20000
10000
02049
61758
2050
2225 G06
2048
2155 1607
COUNT
INPUT FREQUENCY (MHz)
0
65
SNR (dBFS)
66
68
69
70
75
72
20 40 50
2225 G07
67
73
74
71
10 30 60 70
INPUT FREQUENCY (MHz)
0
85
90
100
30 50
2225 G08
80
75
10 20 40 60 70
70
65
95
SFDR (dBFS)
SAMPLE RATE (Msps)
0
60
SNR AND SFDR (dBFS)
70
80
90
100
2468
2225 G09
10 12 14
SNR vs Input Level, fIN = 5MHz,
2V Range
SFDR vs Input Level, fIN = 5MHz,
2V Range
INPUT LEVEL (dBFS)
–70
SNR (dBc AND dBFS)
dBFS
dBc
–40
2225 G10
40
20
–60 –50 –30
10
–0
80
70
60
50
30
–20 –10 0
INPUT LEVEL (dBFS)
–70
SFDR (dBc AND dBFS)
40
100
110
120
–50 –30
dBFS
dBc
–20
2225 G11
20
10
80
60
30
90
0
70
50
–60 –40 –10 0
90dBc SFDR
REFERENCE LINE
LTC2225
7
2225fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
IOVDD vs Sample Rate, 5MHz Sine
Wave Input, –1dB, OVDD = 1.8V
IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
UU
U
PI FU CTIO S
A
IN
+ (Pin 1): Positive Differential Analog Input.
A
IN
- (Pin 2): Negative Differential Analog Input.
REFH (Pins 3, 4): ADC High Reference. Short together and
bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as
close to the pin as possible. Also bypass to pins 5, 6 with
an additional 2.2µF ceramic chip capacitor and to ground
with a 1µF ceramic chip capacitor.
REFL (Pins 5, 6): ADC Low Reference. Short together and
bypass to pins 3, 4 with a 0.1µF ceramic chip capacitor as
close to the pin as possible. Also bypass to pins 3, 4 with
an additional 2.2µF ceramic chip capacitor and to ground
with a 1µF ceramic chip capacitor.
V
DD
(Pins 7, 32): 3V Supply. Bypass to GND with 0.1µF
ceramic chip capacitors.
GND (Pin 8): ADC Power Ground.
CLK (Pin 9): Clock Input. The input sample starts on the
positive edge.
SHDN (Pin 10): Shutdown Mode Selection Pin. Connect-
ing SHDN to GND and OE to GND results in normal
operation with the outputs enabled. Connecting SHDN to
GND and OE to V
DD
results in normal operation with the
outputs at high impedance. Connecting SHDN to V
DD
and
OE to GND results in nap mode with the outputs at high
impedance. Connecting SHDN to V
DD
and OE to V
DD
results in sleep mode with the outputs at high impedance.
OE (Pin 11): Output Enable Pin. Refer to SHDN pin
function.
NC (Pins 12, 13): Do Not Connect These Pins.
D0 – D11 (Pins 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26,
27): Digital Outputs. D11 is the MSB.
OGND (Pin 20): Output Driver Ground.
OV
DD
(Pin 21): Positive Supply for the Output Drivers.
Bypass to ground with 0.1µF ceramic chip capacitor.
OF (Pin 28): Over/Under Flow Output. High when an over
or under flow has occurred.
MODE (Pin 29): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to GND selects
offset binary output format and turns the clock duty cycle
stabilizer off. 1/3 V
DD
selects offset binary output format
and turns the clock duty cycle stabilizer on. 2/3 V
DD
selects
2’s complement output format and turns the clock duty
cycle stabilizer on. V
DD
selects 2’s complement output
format and turns the clock duty cycle stabilizer off.
SAMPLE RATE (Msps)
10
I
VDD
(mA)
15
20
25
02468
2225 G12
10 12 14
2V RANGE
1V RANGE
SAMPLE RATE (Msps)
0
0
I
OVDD
(mA)
0.1
0.3
0.4
0.5
1.0
0.7
4810
2225 G13
0.2
0.8
0.9
0.6
2612 14
LTC2225
8
2225fa
SENSE (Pin 30): Reference Programming Pin. Connecting
SENSE to V
CM
selects the internal reference and a ±0.5V
input range. V
DD
selects the internal reference and a ±1V
input range. An external reference greater than 0.5V and
less than 1V applied to SENSE selects an input range of
±V
SENSE
. ±1V is the largest valid input range.
UU
U
PI FU CTIO S
FUNCTIONAL BLOCK DIAGRA
UU
W
SHIFT REGISTER
AND CORRECTION
DIFF
REF
AMP
REF
BUF
2.2µF
1µF1µF
0.1µF
INTERNAL CLOCK SIGNALSREFH REFL
CLOCK/DUTY
CYCLE
CONTROL
RANGE
SELECT
1.5V
REFERENCE
FIRST PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
SIXTH PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
REFH REFL
CLK OE
MODE
OGND
OVDD
2225 F01
INPUT
S/H
SENSE
VCM
AIN–
AIN+
2.2µF
THIRD PIPELINED
ADC STAGE
OUTPUT
DRIVERS
CONTROL
LOGIC
SHDN
OF
D11
D0
•
•
•
Figure 1. Functional Block Diagram
V
CM
(Pin 31): 1.5V Output and Input Common Mode Bias.
Bypass to ground with 2.2µF ceramic chip capacitor.
GND (Exposed Pad) (Pin 33): ADC Power Ground. The
exposed pad on the bottom of the package needs to be
soldered to ground.
LTC2225
9
2225fa
TI I G DIAGRA
UWW
DYNAMIC PERFORMANCE
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
to frequencies above DC to below half the sampling
frequency.
Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum of all
harmonics of the input signal to the fundamental itself. The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
THD = 20Log (√(V2
2
+ V3
2
+ V4
2
+ . . . Vn
2
)/V1)
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the
second through nth harmonics. The THD calculated in this
data sheet uses all the harmonics up to the fifth.
APPLICATIO S I FOR ATIO
WUUU
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at the sum and differ-
ence frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,
etc. The 3rd order intermodulation products are 2fa + fb,
2fb + fa, 2fa – fb and 2fb – fa. The intermodulation
distortion is defined as the ratio of the RMS value of either
input tone to the RMS value of the largest 3rd order
intermodulation product.
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or
spurious noise that is the largest spectral component
excluding the input signal and DC. This value is expressed
in decibels relative to the RMS value of a full scale input
signal.
Input Bandwidth
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by
3dB for a full scale input signal.
tAP
N + 1
N + 2 N + 4
N + 3 N + 5
N
ANALOG
INPUT
tH
tD
tL
N – 4 N – 3 N – 2 N – 1
CLK
D0-D11, OF
2225 TD01
N – 5 N
LTC2225
10
2225fa
Aperture Delay Time
The time from when CLK reaches mid-supply to the instant
that the input signal is held by the sample and hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion to
conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNR
JITTER
= –20log (2π • f
IN
• t
JITTER
)
CONVERTER OPERATION
As shown in Figure 1, the LTC2225 is a CMOS pipelined
multistep converter. The converter has six pipelined ADC
stages; a sampled analog input will result in a digitized
value five cycles later (see the Timing Diagram section).
For optimal AC performance the analog inputs should be
driven differentially. For cost sensitive applications, the
analog inputs can be driven single-ended with slightly
worse harmonic distortion. The CLK input is single-ended.
The LTC2225 has two phases of operation, determined by
the state of the CLK input pin.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When CLK is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that CLK transitions from low to high, the sampled input is
held. While CLK is high, the held input voltage is buffered
by the S/H amplifier which drives the first pipelined ADC
stage. The first stage acquires the output of the S/H during
this high phase of CLK. When CLK goes back low, the first
stage produces its residue which is acquired by the
second stage. At the same time, the input S/H goes back
to acquiring the analog input. When CLK goes back high,
the second stage produces its residue which is acquired
by the third stage. An identical process is repeated for the
third, fourth and fifth stages, resulting in a fifth stage
residue that is sent to the sixth stage ADC for final
evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2225
CMOS differential sample-and-hold. The analog inputs are
connected to the sampling capacitors (C
SAMPLE
) through
NMOS transistors. The capacitors shown attached to each
input (C
PARASITIC
) are the summation of all other capaci-
tance associated with each input.
Figure 2. Equivalent Input Circuit
During the sample phase when CLK is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to and track the differential input voltage.
When CLK transitions from low to high, the sampled input
voltage is held on the sampling capacitors. During the hold
phase when CLK is high, the sampling capacitors are
disconnected from the input and the held voltage is passed
to the ADC core for processing. As CLK transitions from
high to low, the inputs are reconnected to the sampling
APPLICATIO S I FOR ATIO
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V
DD
V
DD
V
DD
15Ω
15Ω
C
PARASITIC
1pF
C
PARASITIC
1pF
C
SAMPLE
4pF
C
SAMPLE
4pF
LTC2225
A
IN
+
A
IN
–
CLK
2225 F02
LTC2225
11
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APPLICATIO S I FOR ATIO
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capacitors to acquire a new sample. Since the sampling
capacitors still hold the previous sample, a charging glitch
proportional to the change in voltage between samples will
be seen at this time. If the change between the last sample
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such as
the change seen with input frequencies near Nyquist, then
a larger charging glitch will be seen.
Single-Ended Input
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the har-
monic distortion and INL will degrade, but the SNR and
DNL will remain unchanged. For a single-ended input, A
IN+
should be driven with the input signal and A
IN–
should be
connected to V
CM
or a low noise reference voltage be-
tween 0.5V and 1.5V.
Common Mode Bias
For optimal performance the analog inputs should be
driven differentially. Each input should swing ±0.5V for
the 2V range or ±0.25V for the 1V range, around a
common mode voltage of 1.5V. The V
CM
output pin (Pin
31) may be used to provide the common mode bias level.
V
CM
can be tied directly to the center tap of a transformer
to set the DC input level or as a reference level to an op amp
differential driver circuit. The V
CM
pin must be bypassed to
ground close to the ADC with a 2.2µF or greater capacitor.
Input Drive Impedance
As with all high performance, high speed ADCs, the
dynamic performance of the LTC2225 can be influenced
by the input drive circuitry, particularly the second and
third harmonics. Source impedance and reactance can
influence SFDR. At the falling edge of CLK, the sample-
and-hold circuit will connect the 4pF sampling capacitor to
the input pin and start the sampling period. The sampling
period ends when CLK rises, holding the sampled input on
the sampling capacitor. Ideally the input circuitry should
be fast enough to fully charge the sampling capacitor
during the sampling period 1/(2F
ENCODE
); however, this is
not always possible and the incomplete settling may
degrade the SFDR. The sampling glitch has been designed
to be as linear as possible to minimize the effects of
incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2225 being driven by an RF
transformer with a center tapped secondary. The second-
ary center tap is DC biased with V
CM
, setting the ADC input
signal at its optimum DC level. Terminating on the trans-
former secondary is desirable, as this provides a common
mode path for charging glitches caused by the sample and
hold. Figure 3 shows a 1:1 turns ratio transformer. Other
turns ratios can be used if the source impedance seen by
the ADC does not exceed 100Ω for each ADC input. A
disadvantage of using a transformer is the loss of low
frequency response. Most small RF transformers have
poor performance at frequencies below 1MHz.
Figure 3. Single-Ended to Differential Conversion
Using a Transformer
25Ω
25Ω
25Ω
25Ω
0.1µF
A
IN+
A
IN–
12pF
2.2µF
V
CM
LTC2225
ANALOG
INPUT
0.1µFT1
1:1
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
2225 F03
Figure 4 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides low
frequency input response; however, the limited gain band-
width of most op amps will limit the SFDR at high input
frequencies.
Figure 5 shows a single-ended input circuit. The imped-
ance seen by the analog inputs should be matched. This
circuit is not recommended if low distortion is required.
The 25Ω resistors and 12pF capacitor on the analog inputs
serve two purposes: isolating the drive circuitry from the
LTC2225
12
2225fa
sample-and-hold charging glitches and limiting the
wideband noise at the converter input.
APPLICATIO S I FOR ATIO
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The difference amplifier generates the high and low refer-
ence for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has two pins. The multiple output
pins are needed to reduce package inductance. Bypass
capacitors must be connected as shown in Figure 6.
Other voltage ranges in-between the pin selectable ranges
can be programmed with two external resistors as shown
in Figure 7. An external reference can be used by applying
its output directly or through a resistor divider to SENSE.
Figure 5. Single-Ended Drive
Figure 4. Differential Drive with an Amplifier
25Ω
25Ω
12pF
2.2µF
VCM
LTC2225
2225 F04
––
++
CM
ANALOG
INPUT
HIGH SPEED
DIFFERENTIAL
AMPLIFIER AIN+
AIN–
25Ω
0.1µF
ANALOG
INPUT
VCM
AIN+
AIN–
1k
12pF
2225 F05
2.2µF
1k
25Ω
0.1µF
LTC2225
Reference Operation
Figure 6 shows the LTC2225 reference circuitry consisting
of a 1.5V bandgap reference, a difference amplifier and
switching and control circuit. The internal voltage refer-
ence can be configured for two pin selectable input ranges
of 2V (±1V differential) or 1V (±0.5V differential). Tying the
SENSE pin to V
DD
selects the 2V range; tying the SENSE
pin to V
CM
selects the 1V range.
The 1.5V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifier to gener-
ate the differential reference levels needed by the internal
ADC circuitry. An external bypass capacitor is required for
the 1.5V reference output, V
CM
. This provides a high
frequency low impedance path to ground for internal and
external circuitry.
V
CM
REFH
SENSE
TIE TO V
DD
FOR 2V RANGE;
TIE TO V
CM
FOR 1V RANGE;
RANGE = 2 • V
SENSE
FOR
0.5V < V
SENSE
< 1V
1.5V
REFL
2.2µF
2.2µF
INTERNAL ADC
HIGH REFERENCE
BUFFER
0.1µF
2225 F06
LTC2225
4Ω
DIFF AMP
1µF
1µF
INTERNAL ADC
LOW REFERENCE
1.5V BANDGAP
REFERENCE
1V 0.5V
RANGE
DETECT
AND
CONTROL
Figure 6. Equivalent Reference Circuit
Figure 7. 1.5V Range ADC
VCM
SENSE
1.5V
0.75V
2.2µF
12k
1µF
12k
2225 F07
LTC2225
LTC2225
13
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APPLICATIO S I FOR ATIO
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An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the CLK pin to sample the analog
input. The falling edge of CLK is ignored and the internal
falling edge is generated by a phase-locked loop. The input
clock duty cycle can vary and the clock duty cycle stabilizer
will maintain a constant 50% internal duty cycle. If the
clock is turned off for a long period of time, the duty cycle
stabilizer circuit will require a hundred clock cycles for the
PLL to lock onto the input clock. To use the clock duty
cycle stabilizer, the MODE pin should be connected to
1/3V
DD
or 2/3V
DD
using external resistors.
The lower limit of the LTC2225 sample rate is determined
by droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating fre-
quency for the LTC2225 is 1Msps.
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits, and the overflow bit.
It is not recommended to drive the SENSE pin with a logic
device. The SENSE pin should be tied to the appropriate
level as close to the converter as possible. If the SENSE pin
is driven externally, it should be bypassed to ground as
close to the device as possible with a 1µF ceramic capacitor.
Input Range
The input range can be set based on the application. The
2V input range will provide the best signal-to-noise perfor-
mance while maintaining excellent SFDR. The 1V input
range will have better SFDR performance, but the SNR will
degrade by 3.8dB.
Driving the Clock Input
The CLK input can be driven directly with a CMOS or TTL
level signal. A differential clock can also be used along with
a low-jitter CMOS converter before the CLK pin (see
Figure 8).
The noise performance of the LTC2225 can depend on the
clock signal quality as much as on the analog input. Any
noise present on the clock signal will result in additional
aperture jitter that will be RMS summed with the inherent
ADC aperture jitter.
Maximum and Minimum Conversion Rates
The maximum conversion rate for the LTC2225 is 10Msps.
For the ADC to operate properly, the CLK signal should
have a 50% (±10%) duty cycle. Each half cycle must have
at least 40ns for the ADC internal circuitry to have enough
settling time for proper operation.
Figure 8. CLK Drive Using an LVDS or PECL to CMOS Converter
CLK
100Ω
0.1µF
4.7µF
FERRITE
BEAD
CLEAN
SUPPLY
IF LVDS USE FIN1002 OR FIN1018.
FOR PECL, USE AZ1000ELT21 OR SIMILAR
2225 F08
LTC2225
Table 1. Output Codes vs Input Voltage
A
IN+
– A
IN–
D11 – D0 D11 – D0
(2V Range) OF (Offset Binary) (2’s Complement)
>+1.000000V 1 1111 1111 1111 0111 1111 1111
+0.999512V 0 1111 1111 1111 0111 1111 1111
+0.999024V 0 1111 1111 1110 0111 1111 1110
+0.000488V 0 1000 0000 0001 0000 0000 0001
0.000000V 0 1000 0000 0000 0000 0000 0000
–0.000488V 0 0111 1111 1111 1111 1111 1111
–0.000976V 0 0111 1111 1110 1111 1111 1110
–0.999512V 0 0000 0000 0001 1000 0000 0001
–1.000000V 0 0000 0000 0000 1000 0000 0000
<–1.000000V 1 0000 0000 0000 1000 0000 0000
LTC2225
14
2225fa
Digital Output Buffers
Figure 9 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OV
DD
and OGND, iso-
lated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50Ω to external
circuitry and may eliminate the need for external damping
resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2225 should drive a minimal
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as an ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF.
Lower OV
DD
voltages will also help reduce interference
from the digital outputs.
Data Format
Using the MODE pin, the LTC2225 parallel digital output
can be selected for offset binary or 2’s complement
format. Connecting MODE to GND or 1/3V
DD
selects offset
binary output format. Connecting MODE to
2/3V
DD
or V
DD
selects 2’s complement output format.
An external resistor divider can be used to set the 1/3V
DD
or 2/3V
DD
logic values. Table 2 shows the logic states for
the MODE pin.
Overflow Bit
When OF outputs a logic high the converter is either
overranged or underranged.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV
DD
, should be tied
to the same power supply as for the logic being driven. For
example if the converter is driving a DSP powered by a 1.8V
supply, then OV
DD
should be tied to that same 1.8V supply.
OV
DD
can be powered with any voltage from 500mV up to
3.6V. OGND can be powered with any voltage from GND up
to 1V and must be less than OV
DD
. The logic outputs will
swing between OGND and OV
DD
.
Output Enable
The outputs may be disabled with the output enable pin, OE.
OE high disables all data outputs including OF. The output
Hi-Z state can be used to multiplex the data bus of several
LTC2225s.
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to V
DD
and OE to V
DD
results in sleep mode, which powers down all circuitry
including the reference and typically dissipates 1mW. When
exiting sleep mode it will take milliseconds for the output
data to become valid because the reference capacitors have
to recharge and stabilize. Connecting SHDN to V
DD
and OE
to GND results in nap mode, which typically dissipates
15mW. In nap mode, the on-chip reference circuit is kept
on, so that recovery from nap mode is faster than that from
sleep mode, typically taking 100 clock cycles. In both sleep
APPLICATIO S I FOR ATIO
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Figure 9. Digital Output Buffer
LTC2225
2225 F09
OVDD
VDD VDD
0.1µF
43ΩTYPICAL
DATA
OUTPUT
OGND
OVDD 0.5V
TO 3.6V
PREDRIVER
LOGIC
DATA
FROM
LATCH
OE
Table 2. MODE Pin Function
Clock Duty
MODE Pin Output Format Cycle Stablizer
0 Offset Binary Off
1/3V
DD
Offset Binary On
2/3V
DD
2’s Complement On
V
DD
2’s Complement Off
LTC2225
15
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APPLICATIO S I FOR ATIO
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and nap modes, all digital outputs are disabled and enter
the Hi-Z state.
Grounding and Bypassing
The LTC2225 requires a printed circuit board with a clean,
unbroken ground plane. A multilayer board with an inter-
nal ground plane is recommended. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the V
DD
, OV
DD
, V
CM
, REFH, and REFL pins. Bypass capaci-
tors must be located as close to the pins as possible. Of
particular importance is the 0.1µF capacitor between
REFH and REFL. This capacitor should be placed as close
to the device as possible (1.5mm or less). A size 0402
ceramic capacitor is recommended. The large 2.2µF
capacitor between REFH and REFL can be somewhat
further away. The traces connecting the pins and bypass
capacitors must be kept short and should be made as wide
as possible.
The LTC2225 differential inputs should run parallel and
close to each other. The input traces should be as short as
possible to minimize capacitance and to minimize noise
pickup.
Heat Transfer
Most of the heat generated by the LTC2225 is transferred
from the die through the bottom-side exposed pad and
package leads onto the printed circuit board. For good
electrical and thermal performance, the exposed pad
should be soldered to a large grounded pad on the PC
board. It is critical that all ground pins are connected to a
ground plane of sufficient area.
LTC2225
16
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APPLICATIO S I FOR ATIO
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1
2
C8
0.1µF
C11
0.1µF
3
4
5
V
DD
7
V
DD
V
DD
GND
9
32
V
CM
31
30
29
33
JP2
OE
10
11
8
C7
2.2µF
C6
1µF
C9
1µF
C4
0.1µF
C2
12pF
V
DD
V
DD
V
DD
GND
JP1
SHDN
C15
2.2µFC16
0.1µF
C18
0.1µF
C25
4.7µF
E2
V
DD
3V
E4
PWR
GND
V
DD
V
CC
2225 TA02
C17 0.1µF
C20
0.1µF
C19
0.1µF
C14
0.1µF
R10
33Ω
E1
EXT REF
R14
1k
R15
1k
R16
1k
R7
1k
R8
49.9Ω
R3
24.9Ω
R2
24.9Ω
R6
24.9Ω
R1
OPT
R4
24.9Ω
R5
50Ω
T1
ETC1-1T
C1
0.1µF
C3
0.1µF
J3
CLOCK
INPUT
NC7SVU04
NC7SVU04
C13
0.1µF
C10
0.1µF
C5
4.7µF
6.3V
L1
BEAD
V
DD
C12
0.1µF
R9
1k
J1
ANALOG
INPUT
A
IN+
A
IN–
REFH
REFH
6REFL
REFL
V
DD
CLK
SHDN
V
DD
V
CM
SENSE
MODE
GND
LTC2225
OE
D11
GND
D0
NC
NC
D1
D2
D3
D5
D4
D6
D8
D9
OF
OV
DD
V
CC
OGND
D10
D7
26
25
12
13
14
15
17
16
18
22
23
27
28
21
20
24
19
OE1
I
0
OE2
LE1
LE2
V
CC
V
CC
V
CC
GND
GND
GND
I
1
I
2
I
4
I
3
I
5
I
7
I
8
I
12
I
11
I
10
I
13
I
14
I
15
I
9
O11
O10
I
6
V
CC
O0
GND
GND
GND
V
CC
V
CC
GND
34
45
39
42
25
48
24
1
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
V
CC
28
74VCX16373MTD
31
21
15
18
10
4
7
R
N1C
33Ω
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
GND
O1
O2
O4
O3
O5
O7
O8
O12
O13
O14
O15
O9
O6
25
23
27
29
31
33
35
37
39
21
19
15
17
13
9
7
1
3
5
2
4
11
26
24
30
28
34
32
38
40
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
40
3201S-40G1
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
36
A3
A2
A1
A0
SDA
WP
V
CC
1
2
3
4
8
24LC025
7
6
5
SCL
22
20
16
18
14
10
8
6
12
1
2
3
5
••
4
V
CM
12
V
DD
V
DD
34
2/3V
DD
56
1/3V
DD
78
GND
JP4 MODE
12
V
DD
34
V
CM
V
DD
V
CM
56
EXT REF
JP3 SENSE
R
N1B
33Ω
R
N1A
33Ω
R
N2D
33Ω
R
N2C
33Ω
R
N2B
33Ω
R
N2A
33Ω
R
N3D
33Ω
R
N3C
33Ω
R
N3B
33Ω
R
N3A
33Ω
R
N4D
33Ω
R
N4B
33Ω
R
N4A
33Ω
R13
10k
R11
10k
R12
10k
R
N4C
33Ω
R
N1D
33Ω
C28
1µF
C27
0.01µF
V
CC
V
DD
NC7SV86P5X
BYP
GND
ADJ
OUT
SHDN
GND
IN
1
2
3
4
8
LT1763
7
6
5
GND
R18
100k
R17
105k
C26
10µF
6.3V
E3
GND C21
0.1µF
C22
0.1µF
C23
0.1µF
C24
0.1µF
LTC2225
17
2225fa
APPLICATIO S I FOR ATIO
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Silkscreen Top Topside
Inner Layer 2 GND
LTC2225
18
2225fa
APPLICATIO S I FOR ATIO
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Inner Layer 3 Power Bottomside
Silkscreen Bottom
LTC2225
19
2225fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693)
PACKAGE DESCRIPTIO
U
5.00 ± 0.10
(4 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
31
1
2
32
BOTTOM VIEW—EXPOSED PAD
3.45 ± 0.10
(4-SIDES)
0.75 ± 0.05 R = 0.115
TYP
0.25 ± 0.05
(UH32) QFN 1004
0.50 BSC
0.200 REF
0.00 – 0.05
0.70 ±0.05
3.45 ±0.05
(4 SIDES)
4.10 ±0.05
5.50 ±0.05
0.25 ± 0.05
PACKAGE OUTLINE
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 × 45° CHAMFER
LTC2225
20
2225fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2004
LT 0106 REV A • PRINTED IN USA
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LTC2236 10-Bit, 25Msps, 3V ADC, Lowest Power 75mW, 61.8dB SNR, 85dB SFDR, 32-Pin QFN
LTC2237 10-Bit, 40Msps, 3V ADC, Lowest Power 120mW, 61.8dB SNR, 85dB SFDR, 32-Pin QFN
LTC2238 10-Bit, 65Msps, 3V ADC, Lowest Power 205mW, 61.8dB SNR, 85dB SFDR, 32-Pin QFN
LTC2239 10-Bit, 80Msps, 3V ADC, Lowest Power 211mW, 61.6dB SNR, 85dB SFDR, 32-Pin QFN
LTC2245 14-Bit, 10Msps, 3V ADC, Lowest Power 60mW, 74.4dB SNR, 90dB SFDR, 32-Pin QFN
LTC2246 14-Bit, 25Msps, 3V ADC, Lowest Power 75mW, 74.5dB SNR, 90dB SFDR, 32-Pin QFN
LTC2247 14-Bit, 40Msps, 3V ADC, Lowest Power 120mW, 74.4dB SNR, 90dB SFDR, 32-Pin QFN
LTC2248 14-Bit, 65Msps, 3V ADC, Lowest Power 205mW, 74.3dB SNR, 90dB SFDR, 32-Pin QFN
LTC2249 14-Bit, 80Msps, 3V ADC, Lowest Power 222mW, 73dB SNR, 90dB SFDR, 32-Pin QFN
LTC2250 10-Bit, 105Msps, 3V ADC, Lowest Power 320mW, 61.6dB SNR, 85dB SFDR, 32-Pin QFN
LTC2251 10-Bit, 125Msps, 3V ADC, Lowest Power 395mW, 61.6dB SNR, 85dB SFDR, 32-Pin QFN
LTC2252 12-Bit, 105Msps, 3V ADC, Lowest Power 320mW, 70.2dB SNR, 88dB SFDR, 32-Pin QFN
LTC2253 12-Bit, 125Msps, 3V ADC, Lowest Power 395mW, 70.2dB SNR, 88dB SFDR, 32-Pin QFN
LTC2254 14-Bit, 105Msps, 3V ADC, Lowest Power 320mW, 72.4dB SNR, 88dB SFDR, 32-Pin QFN
LTC2255 14-Bit, 125Msps, 3V ADC, Lowest Power 395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN
LTC2284 14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk 540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN
LT5512 DC-3GHz High Signal Level Downconverting Mixer DC to 3GHz, 21dBm IIP3, Integrated LO Buffer
LT5514 Ultralow Distortion IF Amplifier/ADC Driver 450MHz to 1dB BW, 47dB OIP3, Digital Gain Control
with Digitally Controlled Gain 10.5dB to 33dB in 1.5dB/Step
LT5515 1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator High IIP3: 20dBm at 1.9GHz,
Integrated LO Quadrature Generator
LT5516 800MHz to 1.5GHz Direct Conversion Quadrature Demodulator High IIP3: 21.5dBm at 900MHz,
Integrated LO Quadrature Generator
LT5517 40MHz to 900MHz Direct Conversion Quadrature Demodulator High IIP3: 21dBm at 800MHz,
Integrated LO Quadrature Generator
LT5522 600MHz to 2.7GHz High Linearity Downconverting Mixer 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz,
NF = 12.5dB, 50Ω Single-Ended RF and LO Ports
