DATA SH EET
Product specification
File under Integrated Circuits, IC06 December 1990
INTEGRATED CIRCUITS
74HC/HCT4543
BCD to 7-segment
latch/decoder/driver for LCDs
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990 2
Philips Semiconductors Product specification
BCD to 7-segment latch/decoder/driver
for LCDs 74HC/HCT4543
FEATURES
•Latch storage of BCD inputs
•Blanking inputs
•Output capability: non-standard
•ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4543 are high-speed Si-gate CMOS
devices and are pin compatible with “4543” of the “4000B”
series. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT4543 are BCD to 7-segment
latch/decoder/drivers for liquid crystal displays. They have
four address inputs (D0to D3), an active HIGH latch
disable input (LD), an active HIGH blanking input (BI), an
active HIGH phase input (PH) and seven buffered
segment outputs (Qato Qg).
The “4543” provides the function of a 4-bit storage latch
and an 8-4-2-1 BCD to 7-segment decoder driver. The
“4543” can invert the logic levels of the output combination.
The phase (PH), blanking (BI) and latch disable (LD)
inputs are used to reverse the function table phase, blank
the display and store a BCD code, respectively.
For liquid crystal displays a square-wave is applied to PH
and the electrical common back-plane of the display. The
outputs of the “4543” are directly connected to the
segments of the liquid crystal.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25°C; tr=t
f=6ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD=C
PD ×VCC2×fi+∑ (CL×VCC2×fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑(CL×VCC2×fo) = sum of outputs
CL= output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC −1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC HCT
tPHL/ tPLH propagation delay CL= 15 pF; VCC =5V
D
n
to Qn29 33 ns
LD to Qn32 31 ns
BI to Qn20 28 ns
CIinput capacitance 3.5 3.5 pF
CPD power dissipation capacitance per package notes 1 and 2 42 42 pF
December 1990 3
Philips Semiconductors Product specification
BCD to 7-segment latch/decoder/driver for
LCDs 74HC/HCT4543
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1 LD latch disable input (active HIGH)
5, 3, 2, 4 D0 to D3address (data) inputs
6 PH phase input (active HIGH)
7 BI blanking input (active HIGH)
8 GND ground (0 V)
9, 10, 11, 12, 13, 15, 14 Qa to Qgsegment outputs
16 VCC positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 4
Philips Semiconductors Product specification
BCD to 7-segment latch/decoder/driver for
LCDs 74HC/HCT4543
Fig.4 Functional diagram. Fig.5 Segment designation.
APPLICATIONS
•Driving LCD displays
•Driving fluorescent displays
•Driving incandescent displays
•Driving gas discharge displays
FUNCTION TABLE
Notes
1. For liquid crystal displays, apply a square-wave to PH.
2. Depends upon the BCD-code previously applied when LD = HIGH.
H = HIGH voltage level
L = LOW voltage level
X = don’t care
INPUTS OUTPUTS DISPLAY
LD BI PH(1) D3D2D1D0QaQbQcQdQeQfQg
X H L X X X X L L L L L L L blank
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
H
L
H
H
H
H
H
H
H
H
L
H
H
L
H
H
H
L
H
L
H
L
L
L
L
L
H
H
0
1
2
3
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
L
H
H
H
H
L
L
H
H
H
H
H
L
H
H
L
L
L
H
L
H
H
H
L
H
H
H
L
4
5
6
7
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
L
L
L
H
H
L
L
H
H
L
L
8
9
blank
blank
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
blank
blank
blank
blank
LLL XXXX (1) (1)
as
above H as above inverse of above as
above
December 1990 5
Philips Semiconductors Product specification
BCD to 7-segment latch/decoder/driver for
LCDs 74HC/HCT4543
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134).
For RATINGS see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
, standard outputs.
Fig.6 Logic diagram.
Fig.7 Display.
December 1990 6
Philips Semiconductors Product specification
BCD to 7-segment latch/decoder/driver for
LCDs 74HC/HCT4543
DC CHARACTERISTICS FOR 74HC
Output capability: non-standard
ICC category: MSI
Voltages are referenced to GND (ground = 0 V)
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC VCC
(V) VIOTHER+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
VIH HIGH level input
voltage 1.5
3.15
4.2
1.2
2.4
3.1
1.5
3.15
4.2
1.5
3.15
4.2
V 2.0
4.5
6.0
VIL LOW level input
voltage 0.7
1.8
2.8
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V 2.0
4.5
6.0
VOH HIGH level
output voltage 1.9
4.4
5.9
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
V 2.0
4.5
6.0
VIH
or
VIL
−IO=20µA
−I
O=20µA
−I
O=20µA
V
OH HIGH level
output voltage 3.98
5.48 0.15
0.16 3.84
5.34 3.7
5.2 V 4.5
6.0 VIH
or
VIL
−IO= 1.0 mA
−IO= 1.3 mA
VOL LOW level
output voltage 0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V 2.0
4.5
6.0
VIH
or
VIL
IO=20µA
I
O=20µA
I
O=20µA
V
OL LOW level
output voltage 0.15
0.16 0.26
0.26 0.33
0.33 0.4
0.4 V 4.5
6.0 VIH
or
VIL
IO= 1.0 mA
IO= 1.3 mA
±IIinput leakage
current 0.1 1.0 1.0 µA 6.0 VCC
or
GND
ICC quiescent
supply current 8.0 80.0 160.0 µA 6.0 VCC
or
GND
IO=0
December 1990 7
Philips Semiconductors Product specification
BCD to 7-segment latch/decoder/driver for
LCDs 74HC/HCT4543
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr= tf= 6 ns; CL=50pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC VCC
(V) OTHER
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
Dn to Qn
91
33
26
340
68
58
425
85
72
510
102
87
ns 2.0
4.5
6.0
Fig.12
tPHL/ tPLH propagation delay
LD to Qn
102
37
30
370
74
63
465
93
79
555
111
94
ns 2.0
4.5
6.0
Fig.13
tPHL/ tPLH propagation delay
BI to Qn
66
24
19
265
53
45
330
66
56
400
80
68
ns 2.0
4.5
6.0
Fig.14
tPHL/ tPLH propagation delay
PH to Qn
55
20
16
200
40
34
250
50
43
300
60
51
ns 2.0
4.5
6.0
tTHL/ tTLH output transition time 63
23
18
250
50
43
315
63
54
375
75
64
ns 2.0
4.5
6.0
Figs 12, 13 and 14
tWLD pulse width
HIGH or LOW 35
7
6
11
4
3
45
9
8
55
11
9
ns 2.0
4.5
6.0
Fig.13
tsu set-up time
Dn to LD 60
12
10
8
3
2
75
15
13
90
18
15
ns 2.0
4.5
6.0
Fig.15
thhold time
Dn to LD 30
6
5
3
1
1
40
8
7
45
9
8
ns 2.0
4.5
6.0
Fig.15
December 1990 8
Philips Semiconductors Product specification
BCD to 7-segment latch/decoder/driver for
LCDs 74HC/HCT4543
DC CHARACTERISTICS FOR 74HCT
Output capability: non-standard
ICC category: MSI
Voltages are referenced to GND (ground = 0 V)
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT VCC
(V) VIOTHER+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
VIH HIGH level input
voltage 2.0 1.6 2.0 2.0 V 4.5
to
5.5
VIL LOW level input
voltage 1.2 0.8 0.8 0.8 V 4.5
to
5.5
VOH HIGH level output
voltage 4.4 4.5 4.4 4.4 V 4.5 VIH
or
VIL
−IO=20µA
V
OH HIGH level output
voltage 3.98 4.32 3.84 3.7 V 4.5 VIH
or
VIL
−IO= 1.0 mA
VOL LOW level output
voltage 0 0.1 0.1 0.1 V 4.5 VIH
or
VIL
IO=20µA
V
OL LOW level output
voltage 0.15 0.26 0.33 0.4 V 4.5 VIH
or
VIL
IO= 1.0 mA
±IIinput leakage
current 0.1 1.0 1.0 µA 5.5 VCC
or
GND
ICC quiescent supply
current 8.0 80.0 160.0 µA 5.5 VCC
or
GND
IO=0
∆I
CC additional
quiescent supply
current per input
pin for unit load
coefficient is 1
(note 1)
100 360 450 490 µA 4.5
to
5.5
VCC
−2.1V other inputs
at VCC or
GND; IO=0
December 1990 9
Philips Semiconductors Product specification
BCD to 7-segment latch/decoder/driver for
LCDs 74HC/HCT4543
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given here.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr= tf= 6 ns; CL=50pF
INPUT UNIT LOAD COEFFICIENT
D0, D1, D2
D3
BI
LD
PH
1.00
0.50
0.50
1.50
1.25
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT VCC
(V) OTHER
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
Dn to Qn
38 80 100 120 ns 4.5 Fig.12
tPHL/ tPLH propagation delay
LD to Qn
36 68 85 102 ns 4.5 Fig.13
tPHL/ tPLH propagation delay
BI to Qn
32 66 83 99 ns 4.5 Fig.14
tPHL/ tPLH propagation delay
PH to Qn
24 66 83 99 ns 4.5
tTHL/ tTLH output transition time 23 50 63 75 ns 4.5 Figs 12, 13 and 14
tWLD pulse width
HIGH or LOW 10 4 13 15 ns 4.5 Fig.13
tsu set-up time
Dn to LD 12 4 15 18 ns 4.5 Fig.15
thhold time
Dn to LD 8 2 10 12 ns 4.5 Fig.15
December 1990 10
Philips Semiconductors Product specification
BCD to 7-segment latch/decoder/driver for
LCDs 74HC/HCT4543
APPLICATION DIAGRAMS
Fig.8 Connection to liquid crystal (LCD) display
readout. Fig.9 Connection to incandescent display
readout.
Fig.10 Connection to gas discharge display
readout. Fig.11 Connection to fluorescent display readout.
December 1990 11
Philips Semiconductors Product specification
BCD to 7-segment latch/decoder/driver for
LCDs 74HC/HCT4543
AC WAVEFORMS
Fig.12 Waveforms showing the address input (Dn)
to output (Qn) propagation delays and the
output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
Fig.13 Waveforms showing the latch disable input
(LD) to output (Qn) propagation delays and
the output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
Fig.14 Waveforms showing the blanking (BI) to
output (Qn) propagation delays and the
output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.15 Waveforms showing the address (Dn) to
latch disable (LD) input set-up and hold
times.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
