ANALOG DEVICES Complete Low Cost 12-Bit D/A Converters AD DAC80/AD DAC85/AD DAC87 FEATURES Single Chip Construction On-Board Output Amplifier Low Power Dissipation: 300mW Monotonicity Guaranteed over Temperature Guaranteed for Operation with +12V Supplies Improved Replacement for Standard DAC80, DAC800 HI-5680 High Stability, High Current Output Buried Zener Reference Laser Trimmed to High Accuracy: +1/2LSB max Nonlinearity AD DAC80 SERIES FUNCTIONAL BLOCK DIAGRAMS Low Cost Plastic Packaging e s wmse; arr [1 [24] vee OUT mmsal art a[ 1 [24] veer our on GPS & | confhou F423] came ansust en2[z}5 | & | contnos [423] cam aowusr ~ CIRCUIT - CIRCUIT arsfat [22] -. ors [a] 2] + Va +4 5 urs 21] common orale ein 2] common AESISTOR ~ avs [si acdatoa Ht [za] SUMMINGJUNCTION BITB| 5/1 LADDER [20] scauna NETWORK LADDER nero 2kst WORK aT & EH NETWORK 19] 20v RANGE 67618 A comment 19] SCALING NE AND Bar or DH gunna ve] tov nanae ox aT py rents va] ScALMG nETWORK SWITCHES Ske. ons OH T]aeouromser ore [ely Fr] proven onrser Bae ona TAH re] REF weUT ors [> 4 7a] REF INPUT wrt to EH 3B] Your arto fio LY 38] toe ans fat [ey] -. evn [pL fre} -ve sa) arr v2 fiz 13} No. use) err 12 f12 wa} Nc eve AD DAG#0 PRODUCT DESCRIPTION The AD DAC80 Series is a family of low cost 12-bit digital-to-ana- log converters with both a high stability voltage reference and output amplifier combined on a single monolithic chip. The AD DAC80 Series is recommended for all low cost 12-bit D/A converter applications where reliability and cost are of paramount importance. Advanced circuit design and precision processing techniques result in significant performance advantages over conventional DAC80 devices. Innovative circuit design reduces the total power consumption to 300mW which not only improves reliability but also improves long term stability. The AD DAC80 incorporates a fully differential, non-saturating precision current switching cell structure which provides greatly increased immunity to supply voltage variation. This same struc- ture also reduces nonlinearities due to thermal transients as the various bits are switched; nearly all critical components operate at constant power dissipation. High stability, SiCr thin film resistors are trimmed with a fine resolution laser, resulting in lower differential nonlinearity errors. A low noise, high stability, subsurface Zener diode is used to produce a reference voltage with excellent long term stability, high external current capability and temperature drift characteristics which challenge the best discrete Zener references. The AD DAC80 Series is available in three performance grades and two package types. The AD DAC80 is specified for use over the 0 to + 70C temperature range and is available in both plastic and ceramic DIP packages. The AD DAC85 and AD DAC8?7 are available in hermetically sealed ceramic packages and are specified for the 25C to + 85C and 55C to + 125C temperature ranges. JOLITHNC VERSIONS. ong - MON reac + $v - HYBRID VERSIONS. van veRSIONS onc ~ MOI +5v - HYBRID VERSIONS PRODUCT HIGHLIGHTS 1. The AD DAC80 series of D/A converters directly replaces all other devices of this type with significant increases in performance. 2. Single chip construction and low power consumption provides the optimum choice for applications where low cost and high reliability are major considerations. 3. The high speed output amplifier has been designed to settle within 1/2LSB for a 10V full scale transition in 2.0us, when properly compensated. 4. The precision buried Zener reference can supply up to 2.5mA for use elsewhere in the application. 5. The low TC binary ladder guarantees that all units are monotonic over the specified temperature range. 6. System performance upgrading is possible without redesign. PRODUCT OFFERING Analog Devices has developed a number of technologies to support products within the data acquisition market. In serving the market new products are implemented with the technology best suited to the application. The DAC80 series of products was first implemented in hybrid form and now it is available in a single monolithic chip. We will provide both the hybrid and monolithic versions of the family so that in existing designs changes to documentation or product qualification will not have to be done. Specifications and ordering information for both versions are delineated in this data sheet. DIGITAL-TO-ANALOG CONVERTERS 2-411SPECIFICATIONS (TI, = +25C, rated power supplies unless otherwise noted.) Model AD DAC8a AD DACS5 AD DAC87 Min Typ Max Min Typ Max Min Typ Max Unite TECHNOLOGY Monolithic Monolithic Monolithic DIGITALINPLT Binary -CBI 12 R R Bits BCD-CCD - - - Digs Logte Levels (TTL Companbie) Vix (Logic +20 +55 +20 +55 +20 +55 v Vii Logic 0 +0.8 a +0.8 0 +08 v Tra (Vin = $.5V) 250 250 250 BA TretVin = 0.8V> 100 100 Loe BA TRANSFER CHARACTERISTICS. ACCURACY Linearity Error + 25C 12 =12 212 LsB' ccD LSB TG Tyron tO Trans 2s 212 14 212 212 234 LSB Differenual Linearity Error @ + 25C 234 234 234 LSB ccD LSB Ta @ Tinin 00 Tran 34 +1 #1 LSB Gain Error 201 203 201 0.2 0.1 0.2 FSR? Offset Error =0.05 0.15 20.05 20.L =0.05 01 oFSR> Temperacure Range for Guaranteed Monotonicity 0 +70 -15 +85 - 55 +125 cc DRIFT (Tun tO Tax! Total Bipolar Drift, max (includes gain, offset, and hnearity drifts) =20 =20 +30 ppm of FSRC Total Error: T mn tO Troax!* Unipolar = 0.08 20.15 20.12 20.3 *vof FSR Bipolar = 0.06 20.10 20.08 +0.24 sof FSR Gain Including Internal Reference =15 +30 =20 20 ppm of FSRC Excluding Internal Reference =4 =? =10 +10 ppmof FSR.C Unipolar Offser = 23 23 23 ppm of FSR.C Bipolar Offset =f +10 lo +10 ppm of FSRC CONVERSION SPEED Voltage Model (35 Setthng Time to + 0.01% of FSR for FSR change 2k91.|S00pF load; wath 10k Feedback 3 4 3 4 3 4 HS wath Sk Feedback 2 3 2 3 2 3 BS For LSB Change 1 1 1 as Slew Rate 10 10 10 Vas Current Model 11 Settling Time to +0 O1%0f FSR for FSR Change 10 to 1009 Load| 300 300 300 as for 1kQ Load 1 1 1 BS ANALOG OUTPUT Voltage Models Ranges -CBI 225, =, +10, 25, 5, +10, v +5, +10 +5, +10 -CCD v Ourput Current =5 2S =5 mA Ourput Impedance (de, 005 0.05 0.05 n Short Circuit Current 40 40 40 mA Current Models Ranges Unipolar -196 -2.0 -2.04 -19 -2.0 -2.04 -196 -20 2.04 mA -Bipolar 0.96 =1.0 21.04 0.95 =1.0 2104 0.96 zlo mA Output Impedance - Bipolar 25 3.2 4.1 25 3.2 41 25 4.1 ka -Unipoiar 30 6.6 8.2 5.0 6.6 8.2 5.0 82 kn Comphance -2s + -25 +10 2.5 +10 v Internal Reference Voltage (Vp) +6230 +63 +6.37 +623 +63 +6,37 +6230 +63 +6.37 v Output Impedance 1.5 1s 15 n Max External Current +25 425 +25 mA Tempco of Drift =10 =20 =10 +20 =10 ppmof Va POWER SUPPLY SENSITIVITY 2 1SV = 10%, SV supply when applicable 20.002 0,002 20.002 of FSR %Vs t12V =5% 0.002 0.002 20.002 % of FSR%V5 POWER SUPPLY REQUIREMENTS Rated Voltages =15 215 15 v Range Analog Supphes 2d = 16.5 21d = 16.5 2nd 216.5 Vv Logic Supphes v Supply Dran +12, + SV 5 lo 5 oy 5 10 mA 12, ~ SV 14 20 14 20 14 20 mA +5 mA TEMPERATURE RANGE Specificauon 0 +0 -25 +65 -55 +1235 c Operating -25 +85 -55 +125 -55 4125 c Storage -2$ +125 - 65 +150 - 68 +150 c NOTES 7A minimum of = 12.3V is required for a = 10V full scale output and "Least Significant Bic. = LL.4 is required for all other voltage ranges. 2Adjustable to zero with external trim potentiometer Specifications subsect to change without notice. 3 FSR means Full Scale Range and is 20V for the ~ 10V range and 10V for the =5V Range. Bs ; 0 ee Figure le, adjusted to zero at + 25C. cal cest. Results from those tests are used to calculace outgoing quality levels. All BEM min and max specification teed, altt only tl i *Maximum with no degradation of specificanon, must be a constant losd. bol ntfecc are texteton a rineeoeun although only those shown in Specifications showa in boldface are tested on all production umuts at final electri- 2-412 DIGITAL-TO-ANALOG CONVERTERSSPECIFICATIONS %,5 25%, 223 pores sets AD DAC80/AD DAC85/AD DAC87 Model AD DACS0 AD DACSSC AD DAC85 Min Typ Max Min Typ Max Min Typ Max Units TECHNOLOGY Hybrid Hybrid Hybrid DIGITAL INPUT Binary - CBI 12 re) 2 Bits BCD-CCD 3 3 3 Dyits Logie Levels TTL Companle: Vii Logic 1 +20 +55 +2.0 +85 +20 +55 v Vir (Logic 0 0 +08 0 +08 0 +08 v TaaViw = 5.5V) +250 +250 +286 nA IntVir = 0.8V) ~ 100 - 100 - 100 HA TRANSFER CHARACTERISTICS ACCURACY Linearity Error r+ 25C CBI fb 12 212 242 LsB' cca +18 zal% 214 zh LSB Tait Tyrsp tO Trae 2h al2 fl 212 =12 fh2 LSB Differential Linearny Error @ + 25C cal 212 234 =e =n2 LSB ccb =14 212 212 zh LSB Taf Fin t0 Vina at zl zh LSB Gain Error? =0.1 203 =01 zol FSR? Offset Error =0.05 015 =0.05 2008 @FSR Temperature Range for Guarantecd Monotonicity a +70 Q +70 -35 +85 C DRIFT !T min tO Tmax Total Bipolar Drift, max (includes gain, offset, and hnearity drifts) 220 ppm of FSRC Total Error? Tun tT max! Unipolar 0.08 =0.15 of FSR Bipolar =0.06 =010 of FSR, Gain Including Invernal Reference =15 =30 20 20 ppm of FSRC Excluding Internal Reference =5 27 =10 210 ppm of FSR C Unipolar Offset =I 23 =l =I ppm of FSRC Bipolar Offset +10 210 210 ppmof FSR*C CONVERSION SPEED Voltage Model V)* Settling Time to ~ 0.01% of FSR for FSR change (2k0)S00pF load} with 10k Feedback 5 5 5 us with SkfFeedback 3 3 3 Bs For LSB Change Ls Ls 15 ps Slew Rate 10 15 20 20 Vis Current Model (I Settling Time to = 0.01% of FSR for FSR Change 10 to 1009 Load 300 300 300 ns for 1k Load ' 1 1 bs ANALOG OUTPUT Voltage Models Ranges - CBI 225.2 =2 =25, v +5, +10 +5, +10 +8, 710 -CCD =10 +10 +16 Vv Output Current =$ =5 = ma Output Impedance (de) 0.05 D.0s 0.08 n Short Circu Duration Indefinite to Common Indefinite to Common Indefinite to Common Current Models Ranges - L'rupolar -2.0 -2.0 -2.0 mA - Bipolar =10 +10 210 mA Output Impedance - Bipolar 3.2 3.2 3.2 kn - Unipolar 6.6 646 6.6 kn Compliance - 15, 10 -2.5, +10 -2.5, +10 v Internal Reference Voltage (Vp! +617 +63 +643 +617 +63 +643 46.17 +63 +643 v Output Impedance 15 15 15 a Max External Current +25 +25 +25 mA Tempco of Drift =10 =20 =10 +20 =W 20 ppm of Va" POWER SUPPLY SENSITIVITY = ISV = 10%, SV supply when applicable 0.002 = 0.002 = 0.002 % of FSRV 5 POWER SUPPLY REQUIREMENTS Rared Voltages =15,5 +15.5 215.5 v Range Analog Supplies = =16 =165 =15.5 2145 2185 Vv Logic Supplies +45 +16 +45 +155 +45 +155 v Supply Drain? + SV 10 20 i 20 15 20 mA -15 20 35 25 30 25 30 mA +S a 20 15 20 5 20 mA TEMPERATURE RANGE Specification 0 +70 0 +70 ~25 +85 C Operating ~ 28 +S -3 +85 -95 +125 *c Storage ~55 +130 ~65 +150 -65 +150 c Now Si ificant But 5Cy = 0, see Figure Is. Adjustable to zero ith external trim potentiometer. *Maximum with no degradanon of specification, must be s constant load. } BSR means Full Scale Range and is 20V for the + 10V range and 10V for the =SV Range. Including $mA load. Gain and offset errors adjusted to zero at + 25C. Specifications subject to change without nonce. DIGITAL-TO-ANALOG CONVERTERS 2-413SPECIFICATIONS (I, = +25C, rated power supplies unless otherwise noted.) Model AD DACS5LD AD DAC&8SMIL AD DAC87 Min Typ Max Mio Typ Max Min Typ Max TECHNOLOGY Hybnd Hybrid Hybrid DIGITAL INPUT Binary - CBI 12 2 2 Bits BCD-CCD - - ~ Digits Logie Levels: TTL Compaubies Vin (Logic "1" +20 ~5.5 +20 +55 +26 +55 v Vir Logie o +08 0 +0.8 0 +08 v fitVin = 5.5) +250 +280 +250 BA fn Vi, = 0.8V) - 100 ~ 100 ~ 100 aa TRANSFER CHARACTERISTICS ACCURACY Linearity Errorie + 25C CBI =12 22 =14 212 LsB ccD - - - LSB Tait? Tran t Tmax =12 234 234 LSB Differential Linearity Error @t + 25C CBI 212 =12 22 LSB ccD LSB Ta Tun tO Tinax =i zl =I LSB Gain Errar* 20. 2062 % FSR? Offset Error* 20.08 O41 SoFSR? Temperature Range for Guaranteed Monotonicity 25 +85 55 +128 S5 +125 c DRIFT (Tyrunt Timex! Total Bipolar Drift, max ancludes gain, offset, and Linearity drifts) - - =15 =30 ppm of FSR.C Total Error /TyetOT max}* Unipolar - - =0.30 % of FSR Bipolar - - =0.8 % of FSR Gan Including Internal Reference +10 =20 210 =25 ppm of FSRC Excluding Internal Reference =5 =lo ppmof FSR.C Unipolar Offset zl a2 zl =3 ppm of FSR.C Bipolar Offset 25 =10 =5 =10 ppmof FSRC CONVERSION SPEED Voltage Model V)* Settling Time to + 0.01% of FSR for FSR change 2k9|500pF load) with lOkOFeedback 5 5 5 BS with 5kQ Feedback 3 3 3 Bs For LSB Change 1S 1s LS ws Slew Rate 20 20 20 Vus Current Modet (1) Setthng Time to = 0.01% of FSR for FSR Change 10 to 10022 Load 300 300 300 ns. for 1kA Load 1 1 1 BS ANALOG OUTPUT Voltage Models Ranges -CBI =25,=5, 10, =2.,=5, 210, Vv +5, +10 +8, +10 -CcD Output Current =5 8 +8 mA Qutput Impedance {dc} 005 0.05 005 n Short Circuit Duration Indefinite toCommon Indefinite to Common Indefinite to Common Current Models Ranges - Unipolar -20 -2.0 -20 mA - Bipolar =190 =he =10 mA Output Impedance - Bipolar 3.2 32 2.5 3.2 4.1 ka Unipolar 6.6 6.6 3.0 66 8.2 ka Comphance ~2.5, +10 -15, +10 Vv Internal Reference Voltage(Vr) +617 + 6.43 +6.17 +63 + 6.43 +617 +63 + 6.43 Vv Output Impedance LS 1S a Max Excernal Current +25 +28 +25 mA Tempco of Drift =10 20 10 20 5 10 ppmof VRC POWER SUPPLY SENSITIVITY = 15V = 10%, 5V supply wher applicable =0.002 +0.002 + 0.002 =0.003 % af FSR%Vs POWER SUPPLY REQUIREMENTS Rated Voltages =15,5 15,5 15,5 v Range Analog Supplies 214.5 =15.5 =l45 215.8 213.5 = 16.5 v Logic Supplies +45 +155 +45 +185 +45 +165 v Supply Drain? +15V 5 20 15 20 w 20 mA -15V 25 30 25 30 20 30 mA +5V Is 20 15 20 10 20 mA TEMPERATURE RANGE Specification -25 +85 35 +125 -55 +125 Cc Operating -55 +125 58 +125 -55 +125 aa Storage -55 +125 -55 +120 -65 +150 c NOTES Least Significant Bit. 2 Adjustable to zero with external crim potentiometer. ? FSR means Full Scale Range and is 20V for the + 10V range and 10 for the +5V Range. Gain und offset errors adjusted to zero at + 25C. 2-414 DIGITAL-TO-ANALOG CONVERTERS 5Cp=0, see Figure La. *Maximum with no degradation of specification, naust be a constant load. "Including SmA load. Specifications subject co change without notice.AD DAC80/AD DAC85/AD DAC87 ABSOLUTE MAXIMUM RATINGS +Vs to Power Ground .............2. OV to +18V Vs to Power Ground .............. OV to 18V Digital Inputs (Pins 1 to 12) to Power Ground 1.0V to +7V mses ons [FES > a] vow our REF 2 = 23] GAIN ADJUST Et | [ete Le BIT GH [2a] +Vs Bits fH ci] COMMON ars GH ReASTOR > _ {20] SUMMING JUNCTION fe canoe | (SRL See [1a] zov aance BITs | & Ni mu eT? EH gonnees 10V RANGE ares [eH BIPOLAR OFFSET eITS [eH REF INPUT BIT 10, fH Vout ans [aI vs (688) BIT 12 F12 [13] NC tv" AD DACBO "NC - MONOLITHIC VERSIONS +6 - HYBRID VERSIONS Voltage Model Functional Diagram and Pin Configuration Ref In to Reference Ground. .............. +12V Bipolar Offset to Reference Ground. .......... *12V 10V Span R to Reference Ground. ........... +#12V 20V Span R to Reference Ground... ......... *24V Ref Our... .... Indefinite short to power ground or + Vs (MSB} BIT 1 C4 oH [2] Vaex OUT waft | t FS] cam aower ~ CIRCUIT BIT3 GH [22] +s BIT 4 [EH 42.81T om 21] COMMON ars [eH vappen {20] scatina nerworx NETWORK 2g aire EH cunneys 3] SCALING NETWORK SWITCHES. Skt BT? Eh 18 | SCALING NETWORK kn rm 17 | BIPOLAR OFFSET ome iG BK BITS oe ire] REF INPUT BIT 10 ]10 PS 115) Your BIT i] [] -Vs (LSB) BIT 12 [| [3] NCS eye "NC - MONOLITHIC VERSIONS + 5V - HYBRID VERSIONS Current Model Functional Diagram and Pin Configuration ORDERING GUIDE Input Output Temperature Linearity Package Model Code Mode Technology Range Error Options* AD DAC80N-CBI-V Binary Voltage Monolithic Oto +70C + 1/2LSB N-24 AD DAC80D-CBI-V Binary Voltage Monolithic Oto +70C + 1/2LSB D-24 AD DAC80D-CBI-I Binary Current Monolithic Oto +70C + V2LSB D-24 AD DAC85D-CBI-V Binary Voltage Monolithic 25C to + 85C + V2LSB D-24 AD DAC87D-CBI-V Binary Voitage Monolithic 55Cto +125C = * V2LSB D-24 AD DAC80-CBI-V Binary Voltage Hybrid Oto + 70C + V/2LSB DH-24A AD DAC80-CBI-I Binary Current Hybrid Oto +70C + V/2LSB DH-24A AD DAC80-CCD-V Binary Coded Decimal Voltage Hybrid Oto + 70C + L/4LSB DH-24A AD DAC80-CCD-I Binary Coded Decimal Current Hybrid Oto + 70C + /4LSB DH-24A AD DAC80Z-CBI-V Binary Voltage Hybrid Oto +70C +1/2LSB DH-24A AD DAC80Z-CBI-I Binary Current Hybrid Oto +70C + V/2LSB DH-24A AD DAC80Z-CCD-V Binary Coded Decimal Voltage Hybrid Otot+ 70C + 1/4LSB DH-24A AD DAC80Z-CCD-I Binary Coded Decimal Current Hybrid Oto + 70C + V/4LSB DH-24A AD DAC85C-CBI-V Binary Voltage Hybrid 010+ 70C + 1/2LSB DH-24A AD DAC85C-CBI-I Binary Current Hybrid Oto +70C + V2LSB DH-24A AD DAC85-CBI-V Binary Voltage Hybrid 25C to + 85C + 1/2LSB DH-24A AD DAC85-CBI-I Binary Current Hybrid ~ 25C to + 85C + 1/2LSB DH-24A AD DAC85LD-CBI-V Binary Voltage Hybrid 25C to + 85C + V2LSB DH-24A AD DAC85LD-CBI-I Binary Current Hybrid 25C to + 85C + 1/2LSB DH-24A AD DAC85MIL-CBI-V Binary Voltage Hybrid 55Cto +125C = W2LSB DH-24A AD DAC85MIL-CBL-I Binary Current Hybrid 55Cto +125C = # V2 LSB DH-24A AD DAC85C-CCD-V Binary Coded Decimal! Voltage Hybrid Oto + 70C + V4LSB DH-24A AD DAC85C-CCD-I Binary Coded Decimal Current Hybrid Oto + 70C + V4LSB DH-24A AD DAC85-CCD-V Binary Coded Decimal Voltage Hybrid 25C to + 85C + V/4LSB DH-24A AD DAC85-CCD-I Binary Coded Decimal Current Hybrid 25C to +85C + V4LSB DH-24A AD DAC87-CBI-V Binary Voltage Hybrid - 55C to + 125C + 1/2LSB DH-24A AD DAC87-CBI-I Binary Current Hybrid 55Cto +:125C = V2LSB DH-24A *See Section 14 for package outline information. DIGITAL-TO-ANALOG CONVERTERS 2-415DIGITAL INPUT CODES The AD DAC80 Series accepts complementary digital input code in binary (CBI) format. The CBI model may be connected by the user for anyone of three complementary codes: CSB, COB or CTC. Digital Input Analog Output CSB Compt. COBCompl. | CTC* Compl. MSB LSB | Straight Binary Offset Binary | Twos Compl. 000000000000] +FullScale + Full Scale ILSB OLTLIVIT1111 10] +1/2 FullScale Zero Full Scale 100000000000 | Mid-Scale 1LSB + Full Scale TLLLLTITI V1] Zero Full Scale Zero *Invert the MSB of the COB code with an external inverter to obtain CTC code. Table |, Digital Input Codes ACCURACY Accuracy error of a D/A converter is the difference between the analog output that is expected when a given digital code is applied and the output that is actually measured with that code applied to the converter. Accuracy error can be caused by gain error, zero error, linearity error, or any combination of the three. Of these three specifications, the linearity error specification is the most important since it cannot be corrected. Linearity error is specified over its entire temperature range. This means that the analog output will not vary by more than its maximum specifi- cation, from an ideal straight line drawn between the end points (inputs all 1s and all 0s) over the specified temperature range. Differential linearity error of a D/A converter is the deviation from an ideal 1LSB voltage change from one adjacent output state to the next. A differential linearity error specification of + 1/2LSB means that the output voltage step sizes can range from 1/2LSB to 1 1/2LSB when the input changes from one adjacent input state to the next. DRIFT Gain Drift is a measure of the change in the full scale range outpul over temperature expressed in parts per million of full scale range per C (ppm of FSR/C). Gain drift is established by: 1) testing the end point differences for each AD DAC80 model at the lowest operating temperature, + 25C and the highest operating temperature; 2) calculating the gain error with respect to the + 25C value and; 3) dividing by the temperature change. Offset Drift is a measure of the actual change in output with all 1s on the input over the specified temperature range. The maximum change in offset is referenced to the offset at + 25C and is divided by the temperature range. This drift is expressed in parts per million of full scale range per C (ppm of FSR/C). SETTLING TIME Settling time for each model is the total time (including slew time) required for the output to settle within an error band around its final value after a change in input. Voltage Output Models. Three settling times are specified to +0.01% of full scale range (FSR); two for maximum full scale range changes of 20V, 10V and one for a 1LSB change. The 2-416 DIGITAL-TO-ANALOG CONVERTERS 1LSB change is measured at the major carry (O111...11 to 1000...00), the point at which the worst case settling time occurs. The settling time characteristic depends on the compen- sation capacitor selected, the optimum value is 25pF as shown in Figure la. Current Output Models. Two settling times are specified to + 0.01% of FSR. Each is given for current models connected with two different resistive loads: 10 to 100 ohms and 1000 to 1875 ohms. Internal resistors are provided for connecting nominal load resistances of approximately 1000 to 1800 ohms for output voltage ranges of +1V and 0 to 2V. TEKTRONIX 2k TAIZ I 100pF g ae Lr 10V SUM. JCT. HP6216A Figure Ta. Voltage Model Settling Time Circuit Figure 1b. Voltage Model Settling Time Ce = 25pF POWER SUPPLY SENSITIVITY Power supply sensitivity is a measure of the effect of a power supply change on the D/A converter output. It is defined as a per cent of FSR per per cent of change in either the positive or negative supplies about the nominal power supply voltages. REFERENCE SUPPLY All models are supplied with an internal 6.3 volt reference voltage supply. This voltage (pin 24) is accurate to + 1% and must be connected to the Reference Input (pin 16) for specified operation. This reference may also be used externally with external current drain limited to 2.5mA. An external buffer amplifier is recom- mended if this reference is to be used to drive other system components. Otherwise, variations in the load driven by the reference will result in gain variations. All gain adjustments should be made under constant load conditions.Performance Over Temperature AD DAC80/AD DAC85/AD DAC87 ANALYZING DEVICE ACCURACY OVER THE TEMPERATURE RANGE For the purposes of temperature drift analysis, the major device components are shown in Figure 2. The reference element and buffer amplifier drifts are combined to give the total reference temperature coefficient. The input reference current to the DAC, Seer, is developed from the internal reference and will show the same drift rate as the reference voltage. The DAC output current, Ipac, which is a function of the digital input codes, is designed to track peg; if there is a slight mismatch in these currents over temperature, it will contribute to the gain T.C. The bipolar offset resistor, Rgp, and gain setting resistor, Rear; also have temperature coefficients which contribute to system drift errors. The input offset voltage drift of the output amplifier, OA, also contributes a small error. There are three types of drift errors over temperature: offset, gain, and linearity. Offset drift causes a vertical translation of the entire transfer curve; gain drift is a change in the slope of the curve; and linearity drift represents a change in the shape of the curve. The combination of these three drifts results in the complete specification for total error over temperature. Total error is defined as the deviation from a true straight line transfer characteristic from exactly zero at a digital input which calls for zero output to a point which is defined as full scale. A specification for total error over temperature assumes that both the zero and full scale points have been trimmed for zero error at +25C, Total error is normally expressed a percentage of the full scale range. In the bipolar situation, this means the total range from Vrs to + Vegs. Several new design concepts not previously used in DAC80-type devices contribute to a reduction in all the error factors over temperature. The incorporation of low temperature coefficient silicon-chromium thin-film resistors deposited on a single chip, a patented, fully differential, emitter weighted, precision current steering cell structure, and a T.C. trimmed buried zener diode reference element results in superior wide temperature range performance. The gain setting resistors and bipolar offset resistor are also fabricated on the chip with the same SiCr material as the ladder network, resulting in low gain and offset drift. 15V Figure 2. Bipolar Configuration MONOTONICITY AND LINEARITY The initial linearity error of + 1/2LSB max and the differential linearity error of + 3/4LSB max guarantee monotonic performance over the specified range. It can, therefore, be assumed that linearity errors are insignificant in computation of total temperature errors. UNIPOLAR ERRORS Temperature error analysis in the unipolar mode is straightforward: there is an offset drift and a gain drift. The offset drift (which comes from leakage currents and drift in the output amplifier (OA)) causes a linear shift in the transfer curve as shown in Figure 3. The gain drift causes a change in the slope of the curve and results from reference drift, DAC drift, and drift in Regain relative to the DAC resistors. BIPOLAR RANGE ERRORS The analysis is slightly more complex in the bipolar mode. In this mode Rgp is connected to the summing node of the output amplifier (see Figure 2) to generate a current which, exactly balances the current of the MSB so that the output voltage is zero with only the MSB on. Note that if the DAC and application resistors track perfectly, the bipolar offset drift will be zero even if the reference drifts. A change in the reference voltage, which causes a shift in the bipolar offset, will also cause an equivalent change in Ipgr and thus Ipc, so that Ipac will always be exactly balanced by Igp with the MSB turned on. This effect is shown in Figure 3. The net effect of the reference drift then is simply to cause a rotation in the transfer around bipolar zero. However, consideration of second order effects (which are often overlooked) reveals the errors in the bipolar mode. The unipolar offset drifts discussed before will have the same effect on the bipolar offset. A mismatch of Rgp to the DAC resistors is usually the largest component of bipolar drift, but in the AD DAC80 this error is held to 1O0ppm/C max. Gain drift in the DAC also contributes to bipolar offset drift, as well as full scale drift, but again is held to 10ppm/C max. ACTUAL ~= GAIN SHIFT IDEAL OUTPUT m OFFSET {ZEAO) SHIFT UNIPOLAR = 'NPUT mr t GAIN SHIFT OUTPUT a OFFSET SHIFT BIPOLAR (tDEAL CASE) Figure 3. Unipolar and Bipolar Drifts DIGITAL-TO-ANALOG CONVERTERS 2-417Using the AD DAC80 Series POWER SUPPLY CONNECTIONS For optimum performance power supply decoupling capacitors should be added as shown in the connection diagrams. These capacitors (1F electrolytic recommended) should be located close to the AD DAC80. Electrolytic capacitors, if used, should be paralleled with 0.01,.F ceramic capacitors for optimum high frequency performance. EXTERNAL OFFSET AND GAIN ADJUSTMENT Offset and gain may be trimmed by installing external OFF- SET and GAIN potentiometers. These potentiometers should be connected as shown in the block diagrams and adjusted as described below. TCR of the potentiometers should be 100ppm/C or less. The 3.9MQ and 10MQ? resistors (20% carbon or better) should be located close to the AD DAC80 to prevent noise pickup. If it Cy a] = 2 x AEF - TOME 10K [ = | contro. 4 qT l = | circuit 7] 100K: (=H 22 0.01uF fa | o--0) -Vs on" 1 4 12-81T Fe = RESISTOR = = [EH [iaopee =] roe NETWORK 2ko woK2 CH ie =) CURRENT . SWITCHES Skid a. "H od fig] Fy to 5kQ tuk 8 4 7] Tt 6.3k2 = L {e LY 6] S 3 ome, [eH eH {" 4 [2 [3] Figure 4. External Adjustment and Voltage Supply Connection Diagram, Current Model TaMn 3.9M2 is not convenient to use these high-value resistors, a functionally equivalent T network, as shown in Figure 6 may be substituted in each case. The gain adjust (pin 23) is a high impedance point and a 0.01.F ceramic capacitor should be connected from this pin to common to prevent noise pickup. Offset Adjustment. For unipolar (CSB) configurations, apply the digital input code that should produce zero potential output and adjust the OFFSET potentiometer for zero output. For bipolar (COB, CTC) configurations, apply the digital input code that should produce the maximum negative output voltage. Example: If the FULL SCALE RANGE is connected for 20 volts, the maximum negative output voltage is 10V. See Table II for corresponding codes. Gain Adjustment. For either unipolar or bipolar configurations, apply the digital input that should give the maximum positive voltage output. Adjust the GAIN potentiometer for this positive full scale voltage. See Table II for positive full scale voltages. [2] e Oy 4 o +Vs x 10M2 1K | 23 a) J 100K2 RE! CONTROL CIRCUIT 4 224 O.0WE PO -Vs i iH = = 2 L} 12z.81T ol g Oe neaton pais f rain +} NETWORK +9] AND CURRENT . [7] switches a] 0 "Ns suk 7 mF H a] D APPEAR PARPIPIE Figure 5. External Adjustment and Voltage Supply Connection Diagram, Voltage Model 270KQ 270k 78k 190k 180k2, 10K Figure 6. Equivalent Resistances Digital Input Analog Output 12 Bit Resolution Voltage* Current MSB LSB Oto +10V +10V Oto 2mA +imA 000000000000 +9.9976V +9,9951V 1.9995mA | 0.9995mA OLLLELII1I1I1II +5.0000V 0.0000V 1.0000mA | 0.0000mA 100000000000 +4.9976V 4.88mV 0.9995mA | +0.0005mA ELITITII1iI11 0.0000V ~10.0000V | 0.0000mA -1.00mA 1LSB 2.44mV 0.0049V 0.488nA 0.488nA *To obtain values for other binary ranges 0 to + 5V range: divide 0 to + 10 values by 2; ~ SV range: divide + 10V range values by 2; + 2.5V range: divide + LOV range values by 4. Table ll. Digital Input/Analog Output 2-418 DIGITAL-TO-ANALOG CONVERTERSApplying the AD DAC80/AD DAC85/AD DAC87 VOLTAGE OUTPUT MODELS TO REF CONTROL CIACUIT Internal scaling resistors provided in the AD DAC80 may be connected to produce bipolar output voltage ranges of +10, +5 REE IN or +2.5V or unipolar output voltage ranges of 0 to +5 or 0 to +10V (see Figure 7). [3] an REF 5kQ iNpUT [is] [6] BIPOLAR . . . CONTROL GIRGUIT OFFSET Figure 8. Internal Scaling Resistors com . . SUMMING Internal resistors are provided to scale an external op amp or to JUNCTION configure a resistive load to offer two output voltage ranges of +1V or 0 to 2V. These resistors (Rri: TCR = 20ppm/C) are an integral part of the AD DAC80 and maintain gain and bipolar offset drift specifications. If the internal resistors are not used, external Ry (or Rg) resistors should have a TCR of + 25ppm/C = or less to minimize drift. This will typically add + SOppm/C + the TCR of R, (or Rg) to the total drift. FROM WEIGHTED RESISTOR NETWORK Figure 7. Output Amplifier Voltage Range Scaling Circuit TO REF Gain and offset drift are minimized in the AD DAC80 because BIPOLAR OFFSET of the thermal tracking of the scaling resistors with other device REFERENCE INPUT ied ronee components. Connections for various output voltage ranges are cIRCUIT 15] tour shown in Table III. Settling time is specified for a full scale range change: 4 microseconds for a 10kM feedback resistor; 3 q microseconds for a 5kOQ feedback resistor when using the com- - pensation capacitor shown in Figure 1. v) 63v + 24/ REFERENCE OUT ' < p) OTO 2ma $ 6.62 21)]COMMON The equivalent resistive scaling network and output circuit of the current model are shown in Figures 8 and 9. External Rus resistors are required to produce exactly 0 to 2V or +1V output. TCR of these resistors should be + 100ppm/C or less to Figure 9. AD DAC80 Current Model Equivalent maintain the AD DAC80 output specifications. If exact output Output Circuit ranges are not required, the external resistors are not needed. Output Digital Connect | Connect | Connect | Connect Range Input Codes | Pin1Sto | Pinl7to | Pin19to | Pinl6to +10V COBorCTC | 19 20 15 24 +5V COBorCTC | 18 20 N.C. 24 *+2.5V COBorCTC | 18 20 20 24 Oto +10V] CSB 18 21 N.C. 24 Ow +5V | CSB 18 21 20 24 Oto +10V| CCD 19 N.C. 15 24 Table lll. Output Voltage Range Connections-Voltage Model AD DAC80 1% Metal Film R,, Connections Reference Bipolar Offset Internal External Digital Output Resistance Resistance Connect | Connect | Connect | Connect | Connect Input Codes | Range Rus Ris Pinl5to | Pin1l8to | Pin20to | Pinlto | Pinl7to | Rys CSB Oto 2V | 0.968k0 2100, 20 19&Rzps | 15 24 Com (21) | Between Pin 18 & Com (21) COBorCTC | +1V 1.2k0 2490, 18 19 Ris 24 15 Between Pin 20 & Com (21) ccD Oto +2V | 3k N/A N.C. 2k N.C. 24 N.C, N/A Table IV. Current Model/Resistive Load Connections DIGITAL-TO-ANALOG CONVERTERS 2-419DRIVING A RESISTIVE LOAD UNIPOLAR A load resistance, Rr = Ryy, + Rys, connected as shown in Figure 10 will generate a voltage range, Vout, determined by: (ss x Rx Vout = 2mA \Gee sR Where Ry max = 1.54kO and Vout max = 2.5V To achieve specified drift, connect the internal scaling resistor (Ry as shown in Table IV to an external metal film trim resistor (Rs) to provide full scale output voltage range of 0 to 2V. With Rps = 0, Vout = 1.69V. 15 A + 1 oTo Bn 1g Pus Vout ama 6.62. 21|/ COMMON 6 {L CONTROLLED BY DIGITAL INPUT Figure 10. Equivalent Circuit AD DAC80-CBI-I Connected for Unipolar Voltage Output with Resistive Load DRIVING A RESISTOR LOAD BIPOLAR The equivalent output circuit for a bipolar output voltage range is shown in Figure 11, Ry. = Riz + Rus. Vour is determined by: Ry x 3.22k ) Ry + 3.22k Where Ry max = 11.18k0 and VoytT max = +2.5V Vout = +lmA ( To achieve specified drift, connect the internal scaling resistors (R,p as shown in Table FV for the COB or CTC codes and add an external metal film resistor (R,s) in series to obtain a full scale output range of +1V. In this configuration, with Rys equal to zero, the full scale range will be +0.874V. DRIVING AN EXTERNAL OP AMP The current model AD DAC80 will drive the summing junction of an op amp used as a current to voltage converter to produce an output voltage. As seen in Figure 12, Vout = Tour X Rr where Igur is the AD DAC80 output current and Rg is the feedback resistor. Using the internal feedback resistors of the current model AD DAC80 provides output voltage ranges the 18 + 3 a 20] Pus Cima 3.22k2 ( CONTROLLED BY DIGITAL INPUT Figure 11. AD DAC80-CBI-| Connected for Bipolar Output Voltage with Resistive Load same as the voltage model AD DAC80. To obtain the desired output voltage range when connecting an external op amp, refer to Table V and Figure 12. 19| 20V RANGE BkE CBI *y___ 18 . A 1OV RANGE 15 > La I 6.62 9 TO 2m n tansoekn* = Vout 4 "FOR FAST SETTLING TIMES Figure 12. External Op Amp-Using Internal Feedback Resistors OUTPUT LARGER THAN 20V RANGE For output voltage ranges larger than + 10 volts, a high voltage op amp may be employed with an external feedback resistor. Use Iour values of +1mA for bipolar voltage ranges and 2mA for unipolar voltage ranges (see Figure 13). Use protection diodes when a high voltage op amp is used. The feedback resistor, Rr, should have a temperature coefficient as low as possible. Using an external feedback resistor, overall drift of the circuit increases due to the lack of temperature tracking between Rg and the internal scaling resistor network. This will typically add 50ppm/C + Rr drift to total drift. 24 FOR OUTPUT VOLTAGE SWINGS UP TO 140V p-p. Figure 13. External Op Amp-Using External Feedback Resistors Output Digital Connect | Connect | Connect | Connect Range Input Codes | Ato Pint7to | Pinl9to | Pinl6to +10V COBorCTC | 19 15 A 24 +5V COBorCTC | 18 15 N.C. 24 +2.5V COBorCTC | 18 15 15 24 Oto +10V | CSB 18 21 N.C. 24 Oto +5V | CSB 18 21 15 24 Table V. External Op Amp Voltage Mode Connections 2-420 DIGITAL-TO-ANALOG CONVERTERS