Preliminary W24B02
256K
×
8 CMOS STATIC RAM
Publication Release Date: May 6, 2002
- 1 - Revision A1
GENERAL DESCRIPTION
The W24B02 is a normal-speed, very low-power CMOS static RAM organized as 262144 x 8 bits that
operates on a wide voltage range from 2.7V to 3.6V power supply. The W24B02, W24B02-LE and
W24B02-LI, can meet the requirement of various operating temperature. This device is manufactured
using Winbond’s high performance CMOS technology.
FEATURES
• Low power consumption
• Access time: 55/70 nS
• 2.7V to 3.6V supply voltage
• Fully static operation
• All inputs and outputs directly TTL compatible
• Three-state outputs
• Battery back-up operation capability
• Data retention voltage: 1.5V (min.)
• Available packages: TFBGA and 32-pin Type
one TSOP (8 x 13.4 mm and 8 x 20 mm)
PIN CONFIGURATIONS
TFBGA TOP VIEW
20
1
32-pin
TSOP
3
4
5
6
7
8
9
10
11
12
14
15
16
2
32
31
30
29
28
27
23
19
18
17
26
25
24
22
21
#OE
A2
I/O8
I/O5
A10
#CS
A0
A3
A1
I/O7
I/O6
I/O4
Vss
I/O3
I/O1
I/O2
A9
A8
A13
#WE
A5
A6
A7
A16
A4
A12
A17
V
A15
A11
A14
NC
1 2 3 4 5 6
AA0 A1 NC A3 A6 A8
BI/O5 A2 #WE A4 A7 I/O1
CI/O6 NC A5 I/O2
D
E
V
SS
VDD
DD
V
VSS
FI/O7 A17 I/O3
GI/O8 #OE #CS A16 A15 I/O4
HA9 A10 A11 A12 A13 A14
NC
DD
BLOCK DIAGRAM
CORE CELL ARRAY
1024 ROWS
256 X 8 COLUMNS
DATA
CNTRL.
CLK
GEN.
R
O
W
D
E
C
O
D
E
R
A6
I/O CKT.
COLUMN DECODER
#WE
#OE
CLK GEN. PRECHARGE CKT.
A5 A4 A3 A2 A1 A0
#CS
A18
A17
A16
A15
A14
A13
A12
A10
A8
A7
I/O1
I/O8
:
A9
A11
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 − A17 Address Inputs
I/O1 − I/O8 Data Inputs/Outputs
#CS Chip Select Input
#WE Write Enable Input
#OE Output Enable Input
VDD Power Supply
VSS Ground
NC No Connection
Preliminary W24B02
- 2 -
TRUTH TABLE
#CS #OE #WE MODE I/O1
−
I/O8 VDD CURRENT
H X X Not Selected High Z ISB, ISB1
L H H Output Disable High Z IDD
L L H 2 Bytes Read DOUT IDD
L L H Lower Byte Read DOUT IDD
L L H Upper Byte Read High Z IDD
L X L 2 Bytes Write DIN IDD
L X L Lower Byte Write DIN IDD
L X L Upper Byte Write High Z IDD
X X X Not Selected High Z ISB, ISB1
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER RATING UNIT
Supply Voltage to VSS Potential -0.5 to +4.6 V
Input/Output to VSS Potential -0.5 to VDD +0.5 V
Allowable Power Dissipation 1.0 W
Storage Temperature -65 to +150 °C
LE -20 to 85 °C
Operating Temperature LI -40 to 85 °C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
Operating Characteristics
(VSS = 0V; TA (°C) = -20 to 85 for LE, -40 to 85 for LI)
W24B02
PARAMETER SYM. TEST
CONDITIONS MIN. MAX. UNIT
Operating Power Voltage VDD - 2.7 3.6 V
Input Low Voltage VIL - -0.2 +0.4 V
Input High Voltage VIH - +2.2 VDD +0.3 V
Input Leakage Current ILI VIN = VSS to VDD -1 +1 µA
Output Leakage Current ILO VI/O = VSS to VDD; #CS = VIH
(min.) or #OE = VIH (min.)
or #WE = VIL (max.) -1 +1 µA
Output Low Voltage VOL IOL = +0.1 mA - 0.4 V
Preliminary W24B02
Publication Release Date: May 6, 2002
- 3 - Revision A1
Operating Characteristics, continued
W24B02
PARAMETER SYM. TEST
CONDITIONS MIN. MAX. UNIT
Output High Voltage VOH IOH = -1.0 mA 2.4 - V
Operating Power Supply
Current IDD #CS = VIL (max.), I/O = 0 mA;
Cycle = min. Duty = 100% - 20 mA
ISB #CS = VIH (min.) - 0.3 mA
Standby Power Supply
Current ISB1 #CS ≥ VDD -0.2V - 5 µA
CAPACITANCE
(TA = 25° C, f = 1 MHz)
PARAMETER SYM. CONDITIONS MAX. UNIT
Input Capacitance CIN VIN = 0V 8 pF
Input/Output Capacitance CI/O VOUT = 0V 10 pF
Note: These parameters are sampled but not 100% tested.
AC CHARACTERISTICS
AC Test Conditions
PARAMETER CONDITIONS
Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 5 nS
Input and Output Timing Reference Level 1.5V
Output Load See the drawing below
AC Test Loads and Waveform
90% 90%
5 nS
10%
5 nS 10%
OUTPUT OUTPUT
0V
30 pF
Including
Jig and
Scope
5 pF
Including
Jig and
Scope
1 TTL 1 TTL
CLZ, OLZ, CHZ, OHZ, WHZ, OW
(For T T T T T T )
3.0V
Preliminary W24B02
- 4 -
AC Characteristics, continued
(VSS = 0V; TA (°C) = -20 to 85 for LE, -40 to 85 for LI)
Read Cycle
W24B02-55 W24B02-70
PARAMETER SYM.
MIN. MAX. MIN. MAX. UNIT
Read Cycle Time TRC 55 - 70 - nS
Address Access Time TAA - 55 - 70 nS
Chip Select Access Time TACS - 55 - 70 nS
Output Enable to Output Valid TAOE - 35 - 35 nS
Chip Selection to Output in Low Z TCLZ* 10 - 10 - nS
Output Enable to Output in Low Z TOLZ* 5 - 5 - nS
Chip Deselection to Output in High Z TCHZ* - 25 - 30 nS
Output Disable to Output in High Z TOHZ* - 25 - 30 nS
Output Hold from Address Change TOH 10 - 10 - nS
∗These parameters are sampled but not 100% tested
Write Cycle
W24B02-55 W24B02-70
PARAMETER SYM. MIN. MAX. MIN. MAX. UNIT
Write Cycle Time TWC 55 - 70 - nS
Chip Selection to End of Write TCW 45 - 60 - nS
Address Valid to End of Write TAW 45 - 60 - nS
Address Setup Time TAS 0 - 0 - nS
Write Pulse Width TWP 45 - 55 - nS
Write Recovery Time #CS, #WE
TWR 0 - 0 - nS
Data Valid to End of Write TDW 40 - 40 - nS
Data Hold from End of Write TDH 0 - 0 - nS
Write to Output in High Z TWHZ* - 25 - 30 nS
Output Disable to Output in High Z TOHZ* - 25 - 30 nS
Output Active from End of Write TOW 5 - 5 - nS
∗These parameters are sampled but not 100% tested
Preliminary W24B02
Publication Release Date: May 6, 2002
- 5 - Revision A1
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
Address
TRC
TAA
TOH TOH
DOUT
Read Cycle 2
(Chip Select Controlled, #OE = VIL, #WE= VIH)
Address
RC
T
TACS T
#CS
CHZ
TCLZ
T
#OE
OHZ
TOLZ TAOE
DOUT HIGH-Z
HIGH-Z
Preliminary W24B02
- 6 -
Timing Waveforms, continued
Read Cycle 3
(Output Enable
Controlled)
Address
TR
CC
#CS
TAA
#OE
TAOE
TOLZ
TOH
D
TACS
OUT CLZ
TCHZ
TTOHZ
Write Cycle 1
(#OE Clock)
Address
#OE
WC
DOUT
DIN
TWP
TAS
TOHZ (1, 4)
TDW TDH
TAW
#CS TCW
Preliminary W24B02
Publication Release Date: May 6, 2002
- 7 - Revision A1
Timing Waveforms, continued
Write Cycle 2
(#OE = VIL Fixed)
#WE
DOUT
DIN
TAS
TDH
TWP
TWHZ
DW
T
(2) (3)
TOW
TOH
AW
T
(1, 4)
TCW TWR
Address
TWC
#CS
Notes:
1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.
2. The data output from DOUT are the same as the data written to DIN during the write cycle.
3. DOUT provides the read data for the next address.
4. Transition is measured ±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.
Preliminary W24B02
- 8 -
DATA RETENTION CHARACTERISTICS
(TA (°C) = -20 to 85 for LE; -40 to 85 for LI)
PARAMETER SYM.
TEST CONDITIONS MIN.
TYP.
MAX.
UNIT
VDD for Data Retention VDR #CS ≥ VDD -0.2V 1.5 - - V
Data Retention Current IDDDR
#CS ≥ VDD -0.2V, VDD = 3.0V - - 5 µA
Chip Deselect to Data
Retention Time TCDR
See data retention waveform 0 - - nS
Operation Recovery Time
TR TRC*
- - nS
* Read Cycle Time
DATA RETENTION WAVEFORM
TCDR
VDD
TR
#CS
VDR 1.5V
=
>
-0.2V
DD
V
#CS
=
>
0.9 x DD
V0.9 x DD
V
ORDERING INFORMATION
PART NO. ACCESS
TIME
(nS)
OPERATING VOLTAGE (V)
STANDBY CURRENT (µA)
OPERATING
TEMPERATURE
(
°
C) PACKAGE
W24B02B-70LE 70 3V/5 µA -20 to 85 TFBGA
W24B02Q-70LE 70 3V/5 µA -20 to 85 TSOP I (8 x 13.4 mm)
W24B02T-70LE 70 3V/5 µA -20 to 85 TSOP I (8 x 20 mm)
W24B02B-70LI 70 3V/5 µA -40 to 85 TFBGA
W24B02Q-70LI 70 3V/5 µA -40 to 85 TSOP I (8 x 13.4 mm)
W24B02T-70LI 70 3V/5 µA -40 to 85 TSOP I (8 x 20 mm)
W24B02B-55LE 55 3V/5 µA -20 to 85 TFBGA
W24B02Q-55LE 55 3V/5 µA -20 to 85 TSOP I (8 x 13.4 mm)
W24B02T-55LE 55 3V/5 µA -20 to 85 TSOP I (8 x 20 mm)
W24B02B-55LI 55 3V/5 µA -40 to 85 TFBGA
W24B02Q-55LI 55 3V/5 µA -40 to 85 TSOP I (8 x 13.4 mm)
W24B02T-55LI 55 3V/5 µA -40 to 85 TSOP I (8 x 20 mm)
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.
Preliminary W24B02
Publication Release Date: May 6, 2002
- 9 - Revision A1
PACKAGE DIMENSIONS
TFBGA
32-Lead Small Type One TSOP (8x13.4)
A
AA
2
1
L
L1Y
c
E
H
D
D
b
e
1
θ
Controlling dimension: Millimeters
Min.
Dimension in mm
Nom. Max. Min. Nom. Max.
Symbol
A
A
b
c
D
E
e
L
L
Y
1
1
2
A
HD
11.70
13.20
0.675
1.25
0.05 0.15
1.05
1.00
0.95
0.17
0.14
0.30
0.00
0.20 0.27
0.15 0.16
11.80 11.90
13.40 13.60
0.50
0.50 0.70
0.10
0.049
0.006
0.0410.0390.037
0.007 0.008 0.009
0.0056 0.0059 0.0062
0.461 0.465 0.469
7.90 8.00 8.100.311 0.315 0.319
0.520 0.528 0.536
0.020
0.012 0.020 0.028
0.027
0.000 0.004
0 3 50 3 5
0.002
θ
Dimension in Inches
Preliminary W24B02
- 10 -
Package Dimensions, continued
32-Lead TSOP (8 x 20 mm)
A
A
A
2
1
L
L1Y
c
E
H
D
D
b
e
M
0.10(0.004)
θ
Min. Nom. Max. Min. Nom. Max.
Symbol
A
A
b
c
D
E
e
L
L
Y
1
1
2
A
HD
Note:
Controlling dimension: Millimeters
Dimension in Inches
0.047
0.006
0.041
0.039
0.037
0.007 0.008 0.009
0.005 0.006 0.007
0.720 0.724 0.728
0.311 0.315 0.319
0.780 0.787 0.795
0.020
0.016 0.020 0.024
0.031
0.000 0.004
135
0.002
1.20
0.05 0.15
1.051.00
0.95
0.17
0.12
18.30
7.90
19.80
0.40
0.00
1
0.20 0.23
0.15 0.17
18.40 18.50
8.00 8.10
20.00 20.20
0.50
0.50 0.60
0.80
0.10
35
Dimension in mm
θ
__ __ __ __
__ __
__ __
__ __
__
__
__
__
__
__
Preliminary W24B02
Publication Release Date: May 6, 2002
- 11 - Revision A1
VERSION HISTORY
VERSION DATE PAGE DESCRIPTION
A1 May 6, 2002 - Initial Issued
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/
Taipei Office
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
Winbond Electronics Corporation America
2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798
Winbond Electronics (H.K.) Ltd.
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
FAX: 852-27552064
Unit 9-15, 22F, Millennium City,
TEL: 852-27513100
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
Winbond Electronics (Shanghai) Ltd.
200336 China
FAX: 86-21-62365998
27F, 2299 Yan An W. Rd. Shanghai,
TEL: 86-21-62365999
Winbond Electronics Corporation Japan
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
FAX: 81-45-4781800
7F Daini-ueno BLDG, 3-7-18
TEL: 81-45-4781881
9F, No.480, Rueiguang Rd.,
Neihu Chiu, Taipei, 114,
Taiwan, R.O.C.