KS88C0416/P0416/C0424/P0424 PRODUCT OVERVIEW
1-1
1PRODUCT OVERVIEW
KS88-SERIES MICROCONTROLLERS
Samsung's KS88 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU with a wide
range of integrated peripheral, in various mask-programmable ROM sizes. Among its major CPU features are:
—Efficient register-oriented architecture
—Selectable CPU clock sources
—Idle and Stop power-down mode release by interrupt
—Built-in basic timer with watchdog function
The sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum of six CPU clocks) can be assigned to
specific interrupt levels.
KS88C0416/C0424 MICROCONTROLLER
The KS88C0416/C0424 single-chip CMOS microcontrollers are fabricated using a highly advanced CMOS
process, based on Samsung’s newest CPU architecture.
The KS88C0416/C0424 are microcontrollers containing a 16/24-Kbyte mask-programmable ROM. The
KS88P0416/P0424 are microcontroller containing a 16/24-Kbyte one-time-programmable EPROM.
Using a proven modular design approach, Samsung engineers have successfully developed the
KS88C0416/C0424 by integrating the following peripheral modules with the powerful SAM87 core:
—Four programmable I/O ports, including three 8-bit ports and one 2-bit port, for a total of 26 pins.
—Twelve bit-programmable pins for external interrupts.
—One 8-bit basic timer for oscillation stabilization and watchdog functions (system reset).
—One 8-bit timer/counter and one 16-bit timer/counter with selectable operating modes.
—One 8-bit counter with auto-reload function and one-shot or repeat control.
The KS88C0416/C0424 are versatile general-purpose microcontrollers especially suitable for use as a unified
remote transmitter controller.
OTP
The KS88P0416/P0424 is an OTP (One Time Programmable) version of the KS88C0416/C0424 microcontroller.
The KS88P0416/P0424 microcontroller has an on-chip 16/24-Kbyte one-time-programmable EPROM instead of
a masked ROM. The KS88P0416/P0424 is comparable to the KS88C0416/C0424, both in function and in pin
configuration.
PRODUCT OVERVIEW KS88C0416/P0416/C0424/P0424
1-2
FEATURES
CPU
•SAM87 CPU core
Memory
•16-Kbyte internal program memory (ROM):
KS88C0416
•24-Kbyte internal program memory (ROM):
KS88C0424
•Data memory: 317-byte internal register file
Instruction Set
•78 instructions
•IDLE and STOP instructions added for power-
down modes
Instruction Execution Time
•750 ns at 8 MHz fOSC (minimum)
Interrupts
•Six interrupt levels and 18 interrupt sources
•15 vectors (14 sources have a dedicated vector
address and four sources share a single vector)
•Fast interrupt processing feature (for one
selected interrupt level)
I/O Ports
•Three 8-bit I/O ports (P0–P2) and one 2-bit port
(P3) for a total of 26 bit-programmable pins
•Twelve input pins for external interrupts
Timers and Timer/Counters
•One programmable 8-bit basic timer (BT) for
oscillation stabilization control or watchdog timer
(software reset) function
•One 8-bit timer/counter (Timer 0) with three
operating modes; Interval, Capture, and PWM
•One 16-bit timer/counter (Timer 1) with two
operating modes; Interval and Capture
Carrier Frequency Generator
•One 8-bit counter with auto-reload function and
one-shot or repeat control (Counter A)
Stop Error Detection and Recovery (SED and R)
•Special logic in relation to P0 and P1 to prevent
abnormal-stop status
•Releasing stop mode by level switching
detection in P0 and P1
Back-up mode by reset input
•When reset pin is low, the chip enters back-up
mode to reduce current
Operating Temperature Range
•– 40°C to + 85°C
Operating Voltage Range
•2.0 V to 5.5 V at 4 MHz fOSC
•2.2 V to 5.5 V at 8 MHz fOSC
Package Type
•32-pin SOP
•32-pin SDIP
•40-pin DIP (KS88C0424 only)
KS88C0416/P0416/C0424/P0424 PRODUCT OVERVIEW
1-3
BLOCK DIAGRAM
I/O PORT and INTERRUPT
CONTROL
SAM87
CPU
INTERNAL BUS
8-BIT
BASIC
TIMER
PORT2
XIN
XOUT
16/24-KBYTE
PROGRAM
MEMORY
317-BYTE
REGISTER
FILE
P2.0–P2.3
(INT5–INT8)
P2.4–P2.7
PORT 0
P1.0–P1.7
PORT 1
8-BIT
TIMER/
COUNTER
16-BIT
TIMER/
COUNTER
CARRIER
GENERATOR
(COUNTER A)
RESET
TEST
PORT 3
P3.1/REM/T0CK
P3.0/T0PWM/
T0CAP/T1CAP
P0.0–P0.7
(INT0–INT4)
MAIN
OSC
Figure 1-1. Block Diagram
PRODUCT OVERVIEW KS88C0416/P0416/C0424/P0424
1-4
PIN ASSIGNMENTS
VSS
XIN
XOUT
TEST
P2.0/INT5
P2.1/INT6
P2.2/INT7
P2.3/INT8
P0.0/INT0
P0.1/INT1
P0.2/INT2
P0.3/INT3
P0.4/INT4
P0.5/INT4
P0.6/INT4
P0.7/INT4
VDD
P3.1/REM/T0CK
P3.0/T0PWM/T0CAP/T1CAP
P2.7
P2.6
P2.5
P2.4
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
KS88C0416
KS88C0424
32-SOP/SDIP
(Top View)
RESET/BACK-UP MODE
Figure 1-2. Pin Assignment (32-Pin SOP/SDIP Package)
VSS
XIN
XOUT
TEST
NC
NC
P2.0/INT5
P2.1/INT6
P2.2/INT7
P2.3/INT8
P0.0/INT0
P0.1/INT1
P0.2/INT2
P0.3/INT3
NC
NC
P0.4/INT4
P0.5/INT4
P0.6/INT4
P0.7/INT4
VDD
P3.1/REM/T0CK
P3.0/T0PWM/T0CAP/T1CAP
NC
NC
P2.7
P2.6
P2.5
P2.4
P1.7
P1.6
P1.5
P1.4
NC
NC
P1.3
P1.2
P1.1
P1.0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
KS88C0424
40-DIP
(Top View)
RESET/BACK-UP MODE
Figure 1-3. Pin Assignment (40-Pin DIP Package)
KS88C0416/P0416/C0424/P0424 PRODUCT OVERVIEW
1-5
PIN DESCRIPTIONS
Table 1-1. Pin Descriptions
Pin
Names Pin
Type Pin
Description Circuit
Type Pin No.
(32-pin) Pin No.
(40-pin) Shared
Functions
P0.0–P0.7 I/O I/O port with bit-programmable pins.
Configurable to input or push-pull output
mode. Pull-up resistors are assignable by
software. Pins can be assigned individually
as external interrupt inputs with noise filters,
interrupt enable/disable, and interrupt
pending control.
1 9–16 11–14,
17–20 INT0–INT4
P1.0–P1.7 I/O I/O port with bit-programmable pins.
Configurable to C-MOS input mode or
output mode. Pin circuits are either push-
pull or n-channel open-drain type. Pull-up
resistors are assignable by software.
2 17–24 21–24,
27–30 –
P2.0–P2.3
P2.4–P2.7 I/O General-purpose I/O port with bit-
programmable pins. Configurable to C-
MOS input mode, push-pull output mode, or
n-channel open-drain output mode. Pull-up
resistors are assignable by software. Lower
nibble pins, P2.3–P2.0, can be assigned as
external interrupt inputs with noise filters,
interrupt enable/disable, and interrupt
pending control.
3
45–8,
25–28 7–10,
31–34 INT5–INT8
–
P3.0
P3.1 I/O 2-bit I/O port with bit-programmable pins.
Configurable to C-MOS input mode, push-
pull output mode, or n-channel open-drain
output mode. Pull-up resistors are
assignable by software. The two port 3 pins
have high current drive capability.
5 29
30 37
38 T0PWM/
T0CAP/
T1CAP/
REM/T0CK
XIN, XOUT –System clock input and output pins –2, 3 2, 3 –
RESET/
BACK-UP
MODE
ISystem reset signal input pin and back-up
mode input pin. The pin circuit is a C-MOS
input.
6 31 39 –
TEST ITest signal input pin (for factory use only;
must be connected to VSS). – 4 4 –
VDD –Power supply input pin – 32 40 –
VSS –Ground pin – 1 1 –
PRODUCT OVERVIEW KS88C0416/P0416/C0424/P0424
1-6
PIN CIRCUITS
PULL-UP RESISTOR
(Typical 21 KΩ)
VDD
I/O
VSS
DATA
PULL-UP
ENABLE
NORMAL
INPUT
OUTPUT
DISABLE
VDD
INTERRUPT INPUT
IRQ6,7 (INT0-4)
Oscillator Release (SED and R circuit)
STOP
NOISE
FILTER
To prevent and recover from abnormal stop status caused by battery bouncing, the KS88C0416/C0424
has a special logic−SED and R circuit −related to P0 and P1. This is a specific function for key
input/output of universal remote controller. When these ports (P0, P1) are used as a normal
input pin without pull-up resistor, unexpected stop mode recovery can occur by input level switching.
Hence, the user should be aware of input level switching, if P0 and P1 are to be used as normal input
ports and stop mode be used.
NOTE:
Figure 1-4. Pin Circuit Type 1 (Port 0)
KS88C0416/P0416/C0424/P0424 PRODUCT OVERVIEW
1-7
PULL-UP RESISTOR
(Typical 21 KΩ)
VDD
I/O
VSS
DATA
PULL-UP
ENABLE
OUTPUT
DISABLE
VDD
NORMAL INPUT
Oscillator Release (SED and R circuit)
STOP
NOISE
FILTER
To prevent and recover from abnormal stop status caused by battery bouncing, the KS88C0416/C0424
has a special logic −SED and R circuit −related to P0 and P1. This is a specific function for key
input/output of universal remote controller. When these ports (P0, P1) are used as a normal
input pin without pull-up resistor, unexpected stop mode recovery can occur by input level switching.
Hence, the user should be aware of input level switching, if P0 and P1 are to be used as normal input
ports and stop mode be used.
NOTE:
Figure 1-5. Pin Circuit Type 2 (Port 1)
PRODUCT OVERVIEW KS88C0416/P0416/C0424/P0424
1-8
PULL-UP RESISTOR
(Typical 21 KΩ)
VDD
I/O
VSS
DATA
PULL-UP
ENABLE
OUTPUT
DISABLE
VDD
EXTERNAL
INTERRUPT
IRQ5 (INT5-8)
NOISE
FILTER
OPEN-DRAIN
NORMAL INPUT
Figure 1-6. Pin Circuit Type 3 (Ports 2.0−−2.3)
KS88C0416/P0416/C0424/P0424 PRODUCT OVERVIEW
1-9
PULL-UP RESISTOR
(Typical 21 KΩ)
VDD
I/O
VSS
DATA
PULL-UP
ENABLE
OUTPUT
DISABLE
VDD
OPEN-DRAIN
NORMAL INPUT
Figure 1-7. Pin Circuit Type 4 (P2.4−−P2.7)
PRODUCT OVERVIEW KS88C0416/P0416/C0424/P0424
1-10
PULL-UP RESISTOR
(Typical 21 KΩ)
VDD
I/O
VSS
DATA
PULL-UP
ENABLE
OUTPUT
DISABLE
VDD
OPEN-DRAIN
NORMAL INPUT
NOISE
FILTER
ALTERNATIVE
INPUT
M
U
X
PORT 3 DATA
ALTERNATIVE
OUTPUT
SELECT
Figure 1-8. Pin Circuit Type 5 (PORT 3)
BACK-UP MODE
SYSTEM RESET
RESET/
BACK-UP
MODE
NOISE
FILTER
Figure 1-9. Pin Circuit Type 6 (RESET/Back-up mode)
KS88C0416/P0416/C0424/P0424 ADDRESS SPACES
2-1
2ADDRESS SPACES
OVERVIEW
The KS88C0416/C0424 microcontrollers have two types of address space:
—Internal program memory
—Internal register file
A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and
data between the CPU and the register file.
The KS88C0416/C0424 have a programmable internal 16/24-Kbyte ROM. An external memory interface has not
been implemented.
The 256-byte physical register space is expanded into an addressable area of 320 bytes through the use of
addressing modes.
There are 317 mapped registers in the internal register file. Of these, 272 registers are for general-purpose. (This
number includes a 16-byte working register common area used as a “scratch area” for data operations, a 192-
byte prime register area, and a 64-byte area (Set 2) for stack operations.) Eighteen 8-bit registers are used for the
CPU and system control and 27 registers are mapped for peripheral control and data registers. Three register
locations are not mapped.
ADDRESS SPACES KS88C0416/P0416/C0424/P0424
2-2
PROGRAM MEMORY
Programmable memory stores program code or table data. The KS88C0416 has 16 K bytes of programmable
internal memory and the KS88C0424 has 24 K bytes. The programmable memory address range of the
KS88C0416 is therefore 0H–3FFFH and that of the KS88C0424 is 0H–5FFFH (see Figure 2-1).
The first 256 bytes of the ROM (0H–0FFH) are reserved for interrupt vector addresses. Unused locations in this
address range can be used as normal program memory. When you use the vector address area to store program
code, be careful not to overwrite the vector addresses stored in these locations.
The ROM address at which program execution starts after a reset is 0100H.
0
255 0FFH
(DECIMAL) (HEX)
3FFFH
16,383
0H
Interrupt
Vector Area
24,575 5FFFH
Internal Program
Memory (ROM)
KS88C0416
(16-Kbyte)
KS88C0424
(24-Kbyte)
Figure 2-1. Program Memory Address Space
KS88C0416/P0416/C0424/P0424 ADDRESS SPACES
2-3
REGISTER ARCHITECTURE
The KS88C0416/C0424 register files have 317 registers. To increase the size of the internal register file, the
upper 64-byte area of the register file is expanded to two 64-byte areas, set 1 and set 2. The remaining 192-byte
area of the physical register file contains freely-addressable, general-purpose registers called prime registers.
The extension of register space into separately addressable sets is internally supported by addressing mode
restrictions.
Specific register types and the area (in bytes) they occupy in the KS88C0416/C0424 internal register space are
summarized in Table 2-1.
Table 2-1. KS88C0416/C0424 Register Type Summary
Register Type Number of Bytes
General-purpose registers (including the 16-byte
common working register area, the 192-byte prime
register area, and the 64-byte set 2 area)
272
CPU and system control registers 18
Mapped clock, peripheral, I/O control, and data registers 27
Total Addressable Bytes 317
ADDRESS SPACES KS88C0416/P0416/C0424/P0424
2-4
SYSTEM REGISTERS
(Register addressing
mode)
WORKING REGISTERS
(Working register
addressing only)
E0H
C0H
CFH
DFH
D0H
64
BYTES
SYSTEM AND
PERIPHERAL
CONTROL REGISTERS
(Register addressing
mode)
256
BYTES
BFH
FFH
C0H
SET 2
192
BYTES
00H
FFH
SET 1
PRIME
DATA REGISTERS
(All addressing
modes)
~ ~
GENERAL-
PURPOSE DATA
REGISTERS
(Indirect Register,
Indexed addressing
modes, or
stack operations)
Figure 2-2. Internal Register File Organization
KS88C0416/P0416/C0424/P0424 ADDRESS SPACES
2-5
REGISTER PAGE POINTER (PP)
The KS88-series architecture supports the logical expansion of the physical 256-byte internal register file (using
an 8-bit data bus) into as many as 15 separately addressable register pages. Page addressing is controlled by the
register page pointer (PP, DFH). In the KS88C0416/C0424 microcontroller, a paged register file expansion is not
implemented and the register page pointer settings therefore always point to “page 0.”
After a reset, the page pointer's source value (lower nibble) and the destination value (upper nibble) are always
"0000", automatically selecting page 0 as the source and the destination page for register addressing. These
page pointer (PP) register settings, as shown in Figure 2-3, should not be modified during the normal operation.
LSBMSB .2 .1 .0.3.6 .5 .4.7
REGISTER PAGE POINTER (PP)
DFH, Set 1, R/W
Source register page selection bits:
0 0 0 0 Source: page 0
Destination register page selection bits:
0 0 0 0 Destination: page 0
NOTE:In the KS88C0416/C0424 microcontroller, only page 0 is implemented. A hardware
reset operation writes the 4-bit destination and source values shown above to the
register page pointer. These values should not be modified.
Figure 2-3. Register Page Pointer (PP)
ADDRESS SPACES KS88C0416/P0416/C0424/P0424
2-6
REGISTER SET 1
The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FFH.
In some KS88-series microcontrollers, the upper 32-byte area of this 64-byte space (E0H–FFH) is divided into two
32-byte register banks, bank 0 and bank 1. The set register bank instructions SB0 or SB1 are used to address
one bank or the other. In the KS88C0416/C0424 microcontroller, bank 1 is not implemented. A hardware reset
operation therefore always selects bank 0 addressing, and the SB0 and SB1 instructions are not necessary.
The upper 32-byte area of set 1 (FFH–E0H) contains 26 mapped system and peripheral control registers. The
lower 32-byte area contains 16 system registers (DFH–D0H) and a 16-byte common working register area (CFH–
C0H). You can use the common working register area as a “scratch” area for data operations being performed in
other areas of the register file.
Registers in set 1 locations are directly accessible at all times using Register addressing mode. The 16-byte
working register area can only be accessed using working register addressing. (For more information about
working register addressing, please refer to Chapter 3, “Addressing Modes.”)
REGISTER SET 2
The same 64-byte physical space that is used for set 1 locations C0H–FFH is logically duplicated to add another
64 bytes of register space. This expanded area of the register file is called set 2. All set 2 locations (C0H–FFH)
are addressed as part of page 0 in the KS88C0416/C0424 register space.
The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions. You can use only
Register addressing mode to access set 1 locations. In order to access registers in set 2, you must use Register
Indirect addressing mode or Indexed addressing mode.
The set 2 register area is commonly used for stack operations.
KS88C0416/P0416/C0424/P0424 ADDRESS SPACES
2-7
PRIME REGISTER SPACE
The lower 192 bytes of the 256-byte physical internal register file (00H–BFH) is called the prime register space or,
more simply, the prime area. You can access registers in this address using any addressing mode. (In other
words, there is no addressing mode restriction for these registers, as is the case for set 1 and set 2 registers.) All
registers in prime area locations are addressable immediately after a reset.
00H
CPU and system registers
General-purpose registers
Peripheral control registers
SET 1
FFH
FCH
E0H
D0H
C0H
FFH
C0H
SET 2
PRIME
REGISTER
AREA
Figure 2-4. Set 1, Set 2, and Prime Area Register Map
ADDRESS SPACES KS88C0416/P0416/C0424/P0424
2-8
WORKING REGISTERS
Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields.
When 4-bit working register addressing is used, the 256-byte register file can be seen as 32 groups or "slices" of
8-byte registers. Each slice consists of eight 8-bit registers.
Using the two 8-bit register pointers, RP1 and RP0, two working register slices can be selected at any one time to
form a 16-byte working register block. Using the register pointers, you can move this 16-byte register block
anywhere in the addressable register file, except for the set 2 area.
The terms slice and block are used in this manual to help you visualize the size and relative locations of selected
working register spaces:
—One working register slice is 8 bytes (eight 8-bit working registers, R0–R7 or R8–R15)
—One working register block is 16 bytes (sixteen 8-bit working registers, R0–R15)
All the registers in an 8-byte working register slice have the same binary value for their five most significant
address bits. This makes it possible for each register pointer to point to one of the 24 slices in the register file. The
base addresses for the two selected 8-byte register slices are contained in the register pointers, RP0 and RP1.
After a reset, RP0 and RP1 always point to the 16-byte common area in set 1 (C0H–CFH).
1 1 1 1 1 X X X
RP1 (Registers R8–R15)
0 0 0 0 0 X X X
RP0 (Registers R0–R7) SLICE 1
SLICE 32 FFH
F8H
F7H
F0H
10H
FH
8H
7H
0H
Each register pointer points to
one 8-byte slice of the register
space, selecting a total 16-byte
working register block.
CFH
C0H
SET 1
ONLY
~ ~
Figure 2-5. 8-Byte Working Register Areas (Slices)
KS88C0416/P0416/C0424/P0424 ADDRESS SPACES
2-9
USING THE REGISTER POINTERS
The register pointers, RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable
8-byte working register slices in the register file. After a reset, they point to the working register common area:
RP0 points to the addresses, C0H–C7H, and RP1 points to the addresses C8H–CFH.
To change a register pointer value, you should load a new value to RP0 and/or RP1 using an SRP or LD
instruction (see Figures 2-6 and 2-7).
With working register addressing, you can only access those two 8-bit slices of the register file that are currently
pointed to by RP0 and RP1. You cannot, however, use the register pointers to select a working register space in
set 2, C0H–FFH, because these locations can be accessed only using Indirect Register or Indexed addressing
modes.
The selected 16-byte working register block usually consists of two contiguous 8-byte slices. As a general
programming guideline, it is recommended that RP0 point to the "lower" slice and RP1 point to the "upper" slice
(see Figure 2-6). In some cases, it may be necessary to define working register areas in different (non-
contiguous) areas of the register file. In Figure 2-7, RP0 points to the "upper" slice and RP1 to the "lower" slice.
Because a register pointer can point to either of the two 8-byte slices in the working register block, you can
flexibly define the working register area to support program requirements.
++ PROGRAMMING TIP — Setting the Register Pointers
SRP #70H ;RP0 ← 70H, RP1 ← 78H
SRP1 #48H ;RP0 ← no change, RP1 ← 48H,
SRP0 #0A0H ;RP0 ← A0H, RP1 ← no change
CLR RP0 ;RP0 ← 00H, RP1 ← no change
LD RP1,#0F8H ;RP0 ← no change, RP1 ← 0F8H
0 0 0 0 1 x x x
RP1
0 0 0 0 0 x x x
RP0
FH
8H
7H
0H
UPPER SLICE
8-BYTE SLICE
8-BYTE SLICE
16-BYTE
CONTIGUOUS
WORKING
REGISTER
BLOCK
REGISTER FILE
CONTAINS 32
8-BYTE SLICES
(R15)
(R0)
•
•
•
Figure 2-6. Contiguous 16-Byte Working Register Block
ADDRESS SPACES KS88C0416/P0416/C0424/P0424
2-10
1 1 1 1 0 x x x
RP0
0 0 0 0 0 x x x
RP1
F7H
F0H
7H
0H
8-BYTE SLICE
8-BYTE SLICE
16-BYTE NON-
CONTIGUOUS
WORKING
REGISTER
BLOCK
REGISTER FILE
CONTAINS 32
8-BYTE SLICES
(R7)
(R0)
|
(R15)
(R8)
|
Figure 2-7. Non-Contiguous 16-Byte Working Register Block
++ PROGRAMMING TIP — Using the RPs to Calculate the Sum of a Series of Registers
Calculate the sum of the registers, 80H–85H, using the register pointer. The register addresses from 80H through
85H contain the values 10H, 11H, 12H, 13H, 14H, and 15 H, respectively:
SRP0 #80H ;RP0 ← 80H
ADD R0,R1 ;R0 ← R0 + R1
ADC R0,R2 ;R0 ← R0 + R2 + C
ADC R0,R3 ;R0 ← R0 + R3 + C
ADC R0,R4 ;R0 ← R0 + R4 + C
ADC R0,R5 ;R0 ← R0 + R5 + C
The sum of these six registers, 6FH, is located in the register R0 (80H). The instruction string used in this
example takes 12 bytes of instruction code and its execution time is 36 cycles. If the register pointer is not used to
calculate the sum of these registers, the following instruction sequence would have to be used:
ADD 80H,81H ;80H ← (80H) + (81H)
ADC 80H,82H ;80H ← (80H) + (82H) + C
ADC 80H,83H ;80H ← (80H) + (83H) + C
ADC 80H,84H ;80H ← (80H) + (84H) + C
ADC 80H,85H ;80H ← (80H) + (85H) + C
Now, the sum of the six registers is also located in the register 80H. In this case, this instruction string takes 15
bytes of instruction code rather than 12 bytes, and its execution time is 50 cycles rather than 36 cycles.
KS88C0416/P0416/C0424/P0424 ADDRESS SPACES
2-11
REGISTER ADDRESSING
The KS88-series register architecture provides an efficient method of working register addressing that takes full
advantage of shorter instruction formats to reduce execution time.
With Register (R) addressing mode, in which the operand value is the content of a specific register or a register
pair, you can access any location in the register file except for set 2. With working register addressing, you can
use a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within
that space.
Registers are addressed either as a single 8-bit register or as a paired 16-bit register space. In a 16-bit register
pair, the address of the first 8-bit register is always an even number and the address of the next register is always
an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register, and
the least significant byte is always stored in the next (+ 1) odd-numbered register.
Working register addressing differs from Register addressing as it uses a register pointer to identify a specific
8-byte working register space in the internal register file and a specific 8-bit register within that space.
MSB LSB
Rn Rn + 1
n = EVEN ADDRESS
Figure 2-8. 16-Bit Register Pair
ADDRESS SPACES KS88C0416/P0416/C0424/P0424
2-12
PAGE 0 PAGE 0
CFH
BFH
Each register pointer (RP) can independently point to
one of the 24 8-byte "slices" of the register file (other
than set 2). After a reset, RP0 points to locations
C0H–C7H and RP1 to locations C8H–CFH (that is, to
the common working register area).
REGISTER ADDRESSING ONLY ALL
ADDRESSING
MODES
INDIRECT
REGISTER,
INDEXED
ADDRESSING
MODES
CAN BE POINTED TO BY REGISTER POINTER
00H
REGISTER
POINTERS
RP1
RP0
D7H
D6H
SET 2
FFH
C0H
C0H
GENERAL-PURPOSE
REGISTERS
FFH
D0H
NOTE:Only page 0 is implemented. Page 0
contains all the addressable registers in
the internal register file.
SPECIAL-PURPOSE
REGISTERS
SET 1
CONTROL
REGISTERS
SYSTEM
REGISTERS
PRIME
REGISTERS
Figure 2-9. Register File Addressing
KS88C0416/P0416/C0424/P0424 ADDRESS SPACES
2-13
COMMON WORKING REGISTER AREA (C0H–CFH)
After a reset, the register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations
C0H–CFH, as the active 16-byte working register block:
RP0 → C0H–C7H
RP1 → C8H–CFH
This 16-byte address range is called common area. That is, locations in this area can be used as working
registers by operations that address any location on any page in the register file. Typically, these working
registers serve as temporary buffers for data operations between different pages.
Following a hardware reset, the register
pointers, RP0 and RP1, point to the
common working register area,
locations C0H–CFH.
1 1 0 0 0 0 0 0
1 1 0 0 1 0 0 0
RP0 =
RP1 =
C0H
FFH
E0H
CFH
DFH
FCH
SET 1 FFH
00H
C0H
BFH
~
~ ~
PRIME
AREA
SET 2
PAGE 0
Figure 2-10. Common Working Register Area
ADDRESS SPACES KS88C0416/P0416/C0424/P0424
2-14
++ PROGRAMMING TIP — Addressing the Common Working Register Area
As the following examples show, you should access working registers in the common area, locations C0H–CFH,
using working register addressing mode only.
Examples1.LD 0C2H,40H ;Invalid addressing mode!
Use working register addressing instead:
SRP #0C0H
LD R2,40H ;R2 (C2H) ← the value in location 40H
2. ADD 0C3H,#45H ;Invalid addressing mode!
Use working register addressing instead:
SRP #0C0H
ADD R3,#45H ;R3 (C3H) ← R3 + 45H
4-BIT WORKING REGISTER ADDRESSING
Each register pointer defines a movable 8-byte slice of working register space. The address information stored in
a register pointer serves as an addressing "window" that makes it possible for instructions to access working
registers very efficiently using short 4-bit addresses. When an instruction addresses a location in the selected
working register area, the address bits are concatenated in the following way to form a complete 8-bit address:
—The high-order bit of the 4-bit address selects one of the register pointers ("0" selects RP0, "1" selects RP1).
—The five high-order bits in the register pointer select an 8-byte slice of the register space.
—The three low-order bits of the 4-bit address select one of the eight registers in the slice.
As shown in Figure 2-11, the result of this operation is that the five high-order bits from the register pointer are
concatenated with the three low-order bits from the instruction address to form the complete address. As long as
the address stored in the register pointer remains unchanged, the three bits from the address will always point to
an address in the same 8-byte register slice.
Figure 2-12 shows a typical example of 4-bit working register addressing. The high-order bit of the instruction
"INC R6" is "0", which selects RP0. The five high-order bits stored in RP0 (01110B) are concatenated with the
three low-order bits of the instruction's 4-bit address (110B) to produce the register address 76H (01110110B).
KS88C0416/P0416/C0424/P0424 ADDRESS SPACES
2-15
TOGETHER THEY CREATE AN
8-BIT REGISTER ADDRESS
REGISTER POINTER
PROVIDES FIVE
HIGH-ORDER BITS
SELECTS
RP0 OR RP1
RP0
RP1
ADDRESS OPCODE
4-BIT ADDRESS
PROVIDES THREE
LOW-ORDER BITS
Figure 2-11. 4-Bit Working Register Addressing
0 1 1 1 0
RP0
0 1 1 1 0
0 1 1 1 1
RP1
R6 OPCODE
REGISTER
ADDRESS
(76H)
SELECTS RP0
INSTRUCTION:
'INC R6'
q
0 1 1 0 1 1 1 0
0 0 0
1 1 0
0 0 0
Figure 2-12. 4-Bit Working Register Addressing Example
ADDRESS SPACES KS88C0416/P0416/C0424/P0424
2-16
8-BIT WORKING REGISTER ADDRESSING
You can also use 8-bit working register addressing to access registers in a selected working register area. To
initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value
1100B. This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working
register addressing.
As shown in Figure 2-13, the lower nibble of the 8-bit address is concatenated in much the same way as for 4-bit
addressing: Bit 3 selects either RP0 or RP1, which then supplies the five high-order bits of the final address; the
three low-order bits of the complete address are provided by the original instruction.
Figure 2-14 shows an example of 8-bit working register addressing. The four high-order bits of the instruction
address (1100B) specify 8-bit working register addressing. Bit 4 ("1") selects RP1 and the five high-order bits in
RP1 (10101B) become the five high-order bits of the register address. The three low-order bits of the register
address (011) are provided by the three low-order bits of the 8-bit instruction address. The five address bits from
RP1 and the three address bits from the instruction are concatenated to form the complete register address,
0ABH (10101011B).
8-BIT PHYSICAL ADDRESS
REGISTER POINTER
PROVIDES FIVE
HIGH-ORDER BITS
SELECTS
RP0 OR RP1
RP0
RP1
ADDRESS
THREE
LOW-ORDER BITS
8-BIT LOGICAL
ADDRESS
1 1 0 0
THESE ADDRESS
BITS INDICATE
8-BIT WORKING
REGISTER
ADDRESSING
Figure 2-13. 8-Bit Working Register Addressing
KS88C0416/P0416/C0424/P0424 ADDRESS SPACES
2-17
RP0 RP1
R11
8-BIT ADDRESS
FROM INSTRUCTION
'LD R2,R11'
SPECIFIES WORKING
REGISTER ADDRESSING
SELECTS RP1
REGISTER ADDRESS (0ABH)
1 1 0 0 10 1 1
1 0 1 0 1 0 1 1
1 0 1 0 1 0 0 00 1 1 0 0 0 0 0
Figure 2-14. 8-Bit Working Register Addressing Example
ADDRESS SPACES KS88C0416/P0416/C0424/P0424
2-18
SYSTEM AND USER STACKS
The KS88-series microcontrollers use the system stack for data storage, and subroutine calls and returns. The
PUSH and POP instructions are used to control system stack operations. The KS88C0416/C0424 architecture
supports stack operations in the internal register file.
Stack Operations
Return addresses for procedure calls, interrupts, and data are stored on the stack. The contents of the PC are
saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents
of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to
their original locations. The stack address value is always decreased by one before a push operation and
increased by one after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top
of the stack, as shown in Figure 2-15.
STACK CONTENTS
AFTER A CALL
INSTRUCTION
PCH
PCL
HIGH ADDRESS
PCH
PCL
FLAGS
STACK CONTENTS
AFTER AN
INTERRUPT
TOP OF
STACK
LOW ADDRESS
TOP OF
STACK
Figure 2-15. Stack Operations
User-Defined Stacks
You can freely define stacks in the internal register file as data storage locations. The instructions PUSHUI,
PUSHUD, POPUI, and POPUD support user-defined stack operations.
Stack Pointers (SPL)
The register location D9H contains the 8-bit stack pointer (SPL) that is used for system stack operations. After a
reset, the SPL value is undetermined. Because only an internal memory 256-byte is implemented in the
KS88C0416/C0424, the SPL must be initialized to an 8-bit value in the range of 00H–FFH.
KS88C0416/P0416/C0424/P0424 ADDRESS SPACES
2-19
++ PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP
The following example shows you how to perform stack operations in the internal register file using PUSH and
POP instructions:
LD SPL,#0FFH ;SPL ← FFH
;(Normally, the SPL is set to 0FFH by the initialization
;routine)
•
•
•
PUSH PP ;Stack address 0FEH ← PP
PUSH RP0 ;Stack address 0FDH ← RP0
PUSH RP1 ;Stack address 0FCH ← RP1
PUSH R3 ;Stack address 0FBH ← R3
•
•
•
POP R3 ;R3 ← Stack address 0FBH
POP RP1 ;RP1 ← Stack address 0FCH
POP RP0 ;RP0 ← Stack address 0FDH
POP PP ;PP ← Stack address 0FEH
ADDRESS SPACES KS88C0416/P0416/C0424/P0424
2-20
NOTES
KS88C0416/P0416/C0424/P0424 ADDRESSING MODES
3-1
3ADDRESSING MODES
OVERVIEW
The program counter is used to fetch instructions that are stored in program memory for execution. Instructions
indicate the operation to be performed and the data to be operated on. Addressing mode is used to determine the
location of the data operand. The operands specified in instructions may be condition codes, immediate data, a
location in the register file, program memory, or data memory.
The KS88-series instruction set supports seven explicit addressing modes. Not all of these addressing modes are
available for each instruction:
—Register (R)
—Indirect Register (IR)
—Indexed (X)
—Direct Address (DA)
—Indirect Address (IA)
—Relative Address (RA)
—Immediate (IM)
ADDRESSING MODES KS88C0416/P0416/C0424/P0424
3-2
REGISTER ADDRESSING MODE (R)
In Register addressing mode, the operand is the content of a specified register or a register pair (see Figure 3-1).
Working register addressing differs from Register addressing as it uses a register pointer to specify an 8-byte
working register space in the register file and an 8-bit register within that space (see Figure 3-2).
PROGRAM MEMORY
dst
OPCODE
8-BIT REGISTER
FILE ADDRESS
ONE-OPERAND
INSTRUCTION
(EXAMPLE)
REGISTER
FILE
OPERAND
POINTS TO ONE
REGISTER IN REGISTER
FILE
VALUE USED IN
INSTRUCTION EXECUTION
SAMPLE INSTRUCTION:
DEC CNTR ;Where CNTR is the label of an 8-bit register address
Figure 3-1. Register Addressing
SAMPLE INSTRUCTION:
ADD R1,R2 ;Where R1 and R2 are registers in the currently selected
working register area
PROGRAM MEMORY
dst
OPCODE
4-BIT
WORKING
REGISTER
TWO-
OPERAND
INSTRUCTION
(EXAMPLE)
POINTS TO THE
WORKING REGISTER
(1 of 8)
OPERAND
3 LSBs
src
SELECTED
RP POINTS
TO START
OF WORKING
REGISTER
BLOCK
REGISTER
FILE
RP0 or RP1
MSB POINTS TO
RP0 or RP1
Figure 3-2. Working Register Addressing
KS88C0416/P0416/C0424/P0424 ADDRESSING MODES
3-3
INDIRECT REGISTER ADDRESSING MODE (IR)
In Indirect Register (IR) addressing mode, the content of a specified register or a register pair is the address of the
operand. Depending on the instruction used, the actual address may point to a register in the register file, program
memory (ROM), or an external memory space, if implemented (see Figures 3-3 through 3-6).
You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to
indirectly address another memory location. Remember, however, that the locations, C0H–FFH, in set 1 cannot be
accessed in Indirect Register addressing mode.
SAMPLE INSTRUCTION:
RL @SHIFT ;Where SHIFT is the label of an 8-bit register address.
8-BIT REGISTER
FILE ADDRESS
ONE-OPERAND
INSTRUCTION
(EXAMPLE)
POINTS TO ONE
REGISTER IN
REGISTER FILE
REGISTER FILE
OPERAND
PROGRAM MEMORY
dst
OPCODE
ADDRESS
ADDRESS OF OPERAND
USED BY INSTRUCTION
VALUE USED IN
INSTRUCTION
EXECUTION
Figure 3-3. Indirect Register Addressing to Register File
ADDRESSING MODES KS88C0416/P0416/C0424/P0424
3-4
INDIRECT REGISTER ADDRESSING MODE (Continued)
PROGRAM MEMORY
EXAMPLE
INSTRUCTION
REFERENCES
PROGRAM
MEMORY
POINTS TO
REGISTER
PAIR
REGISTER
FILE
16-BIT
ADDRESS
POINTS TO
PROGRAM
MEMORY
OPERAND
VALUE USED IN
INSTRUCTION
PROGRAM MEMORY
REGISTER
PAIR
dst
OPCODE
SAMPLE INSTRUCTIONS:
CALL @RR2
JP @RR2
Figure 3-4. Indirect Register Addressing to Program Memory
KS88C0416/P0416/C0424/P0424 ADDRESSING MODES
3-5
INDIRECT REGISTER ADDRESSING MODE (Continued)
PROGRAM MEMORY
dst
OPCODE
4-BIT
WORKING
REGISTER
ADDRESS POINTS TO THE
WORKING
REGISTER (1 of 8)
REGISTER FILE
RP0 or RP1
ADDRESS
3 LSBs
MSB POINTS TO
RP0 or RP1
src
SELECTED
RP POINTS
TO START OF
WORKING
REGISTER
BLOCK
OPERAND
VALUE USED IN
INSTRUCTION
SAMPLE INSTRUCTION:
OR R3,@R6
~ ~
~~
Figure 3-5. Indirect Working Register Addressing to Register File
ADDRESSING MODES KS88C0416/P0416/C0424/P0424
3-6
INDIRECT REGISTER ADDRESSING MODE (Continued)
SAMPLE INSTRUCTIONS:
LDC R5,@RR6 ;Program memory access
LDE R3,@RR14 ;Internal font and data memory, and External data memory access
LDE @RR4,R8 ;Internal font and data memory, and External data memory access
NEXT 2 BITS POINT
TO WORKING
REGISTER PAIR
(1 of 4)
REGISTER FILE
RP0 or RP1
REGISTER
PAIR
MSB POINTS TO
RP0 or RP1
SELECTED RP
POINTS TO
START OF
WORKING
REGISTER
BLOCK
OPERAND
VALUE USED
IN
INSTRUCTION
4-BIT
WORKING
REGISTER
ADDRESS
EXAMPLE
INSTRUCTION
REFERENCES
EITHER
PROGRAM
MEMORY OR
DATA MEMORY
PROGRAM MEMORY
OPCODE
dst src
16-BIT
ADDRESS
POINTS TO
PROGRAM
MEMORY OR
DATA
MEMORY
PROGRAM MEMORY
or
DATA MEMORY
LSB SELECTS
NOTE: LDE command is not available.
Figure 3-6. Indirect Working Register Addressing to Program or Data Memory
KS88C0416/P0416/C0424/P0424 ADDRESSING MODES
3-7
INDEXED ADDRESSING MODE (X)
Indexed (X) addressing mode adds an offset value to a base address during an instruction execution in order to
calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access
locations in the internal register file or in external memory (if implemented). You cannot, however, access the
locations, C0H–FFH, in set 1 in Indexed addressing mode.
In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range –128 to
+127. This applies to external memory accesses only (see Figure 3-8).
For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained
in a working register. For external memory accesses, the base address is stored in the working register pair
designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to the base address
(see Figure 3-9).
The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction
(LD). The LDC and the LDE instructions support Indexed addressing mode for internal program memory and for
external data memory (if implemented).
SAMPLE INSTRUCTION:
LD R0,#BASE[R1] ;Where BASE is an 8-bit immediate value
POINTS TO ONE
OF THE
WORKING
REGISTERS
(1 of 8)
MSB POINTS TO
RP0 or RP1
VALUE USED IN
INSTRUCTION
TWO-
OPERAND
INSTRUCTION
EXAMPLE
PROGRAM MEMORY
OPCODE
dst / src x3 LSBs
REGISTER FILE
RP0 or RP1
OPERAND
SELECTED RP
POINTS TO
START OF
WORKING
REGISTER
BLOCK
INDEX
BASE ADDRESS
+
~ ~
~ ~
Figure 3-7. Indexed Addressing to Register File
ADDRESSING MODES KS88C0416/P0416/C0424/P0424
3-8
INDEXED ADDRESSING MODE (Continued)
SAMPLE INSTRUCTIONS:
LDC R4,#04H[RR2] ;The values in the program address (RR2 + 04H) are
loaded into the register R4.
LDE R4,#04H[RR2] ;Operation identical to the LDC example, except that
external data memory is accessed.
MSB POINTS TO
RP0 or RP1
4-BIT
WORKING
REGISTER
ADDRESS
PROGRAM MEMORY
OPCODE
dst / src x
OFFSET
REGISTER
FILE
RP0 or RP1 SELECTED
RP POINTS
TO START OF
WORKING
REGISTER
BLOCK
OPERAND
REGISTER
PAIR 16-BIT
ADDRESS
ADDED TO
OFFSET
LSB SELECTS
8 BITS 16 BITS
16 BITS
VALUE USED IN
INSTRUCTION
PROGRAM MEMORY
or
DATA MEMORY
NEXT 2 BITS
POINT TO
WORKING
REGISTER
PAIR (1 of 4)
~ ~
NOTE:LDE command is not available.
+
Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset
KS88C0416/P0416/C0424/P0424 ADDRESSING MODES
3-9
INDEXED ADDRESSING MODE (Continued)
SAMPLE INSTRUCTIONS:
LDC R4,#1000H[RR2] ;The values in the program address (RR2 + 1000H) are
loaded into the register R4.
LDE R4,#1000H[RR2] ;Operation identical to the LDC example, except that external
data memory is accessed.
MSB POINTS TO
RP0 OR RP1
4-BIT
WORKING
REGISTER
ADDRESS
PROGRAM MEMORY
OPCODE
dst / src x
OFFSET
+
REGISTER FILE
RP0 OR RP1 SELECTED
RP POINTS
TO START OF
WORKING
REGISTER
BLOCK
OPERAND
REGISTER
PAIR 16-BIT
ADDRESS
ADDED TO
OFFSET
LSB SELECTS
16 BITS 16 BITS
16 BITS VALUE USED IN
INSTRUCTION
PROGRAM MEMORY
or
DATA MEMORY
NEXT 2 BITS
POINT TO
WORKING
REGISTER
PAIR
OFFSET
~ ~
NOTE:LDE command is not available.
Figure 3-9. Indexed Addressing to Program or Data Memory
ADDRESSING MODES KS88C0416/P0416/C0424/P0424
3-10
DIRECT ADDRESS MODE (DA)
In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call
(CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC
whenever a JP or CALL instruction is executed.
The LDC and the LDE instructions can use Direct Address mode to specify the source or the destination address
for Load operations to program memory (LDC) or to external data memory (LDE), if implemented.
MEMORY
ADDRESS
USED
LSB SELECTS PROGRAM
MEMORY OR DATA MEMORY:
"0" = PROGRAM MEMORY
"1" = DATA MEMORY
PROGRAM or
DATA MEMORY
UPPER ADDR BYTE
LOWER ADDR BYTE
dst / src
OPCODE
"0" or "1"
PROGRAM MEMORY
SAMPLE INSTRUCTIONS:
LDC R5, 1234H ;The values in the program address (1234H) are
are loaded into the register R5.
LDE R5,1234H ;Operation identical to the LDC example, except that
external program memory is accessed.
NOTE: LDE command is not available.
Figure 3-10. Direct Addressing for Load Instructions
KS88C0416/P0416/C0424/P0424 ADDRESSING MODES
3-11
DIRECT ADDRESS MODE (Continued)
SAMPLE INSTRUCTIONS:
JP C,JOB1 ; Where JOB1 is a 16-bit immediate address
CALL DISPLAY ; Where DISPLAY is a 16-bit immediate address
PROGRAM MEMORY
NEXT OPCODE
LOWER ADDR BYTE
PROGRAM
MEMORY
ADDRESS
USED
UPPER ADDR BYTE
OPCODE
Figure 3-11. Direct Addressing for Call and Jump Instructions
ADDRESSING MODES KS88C0416/P0416/C0424/P0424
3-12
INDIRECT ADDRESS MODE (IA)
In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program
memory. The selected pair of memory locations contains the actual address of the next instruction to be executed.
Only the CALL instruction can use Indirect Address mode.
Because Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory,
only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are assumed to be
all zeros.
SAMPLE INSTRUCTION:
CALL #40H ;The 16-bit value in the program memory addresses,
40H and 41H, is the subroutine start address.
PROGRAM
MEMORY
LOWER ADDR BYTE
PROGRAM MEMORY
LOCATIONS 0–255
UPPER ADDR BYTE
OPCODE
dst LSB MUST BE ZERO
NEXT INSTRUCTION
CURRENT
INSTRUCTION
Figure 3-12. Indirect Addressing
KS88C0416/P0416/C0424/P0424 ADDRESSING MODES
3-13
RELATIVE ADDRESS MODE (RA)
In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified
in the instruction. The displacement value is then added to the current PC value. The result is the address of the
next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction
immediately following the current instruction.
Several program control instructions use Relative Address mode to perform conditional jumps. The instructions
that support RA addressing are BTJRF, BTJRT, DJNZ, CPIJE, CPIJNE, and JR.
PROGRAM MEMORY
PROGRAM MEMORY
ADDRESS USED
DISPLACEMENT
OPCODE SIGNED
DISPLACEMENT
VALUE
+
CURRENT
PC VALUE
CURRENT
INSTRUCTION
NEXT OPCODE
SAMPLE INSTRUCTION:
JR ULT,$+OFFSET ;Where OFFSET is a value in the range
+127 to –128
Figure 3-13. Relative Addressing
ADDRESSING MODES KS88C0416/P0416/C0424/P0424
3-14
IMMEDIATE MODE (IM)
In Immediate (IM) mode, the operand value used in the instruction is the value supplied in the operand field itself.
The operand may be one byte or one word in length, depending on the instruction used. Immediate addressing
mode is useful for loading constant values into registers.
PROGRAM MEMORY
(The operand value is in the instruction.)
OPCODE
OPERAND
SAMPLE INSTRUCTION:
LD R0,#0AAH
Figure 3-14. Immediate Addressing
KS88C0416/P0416/C0424/P0424 CONTROL REGISTERS
4-1
4CONTROL REGISTERS
OVERVIEW
In this chapter, detailed descriptions of the KS88C0416/C0424 control registers are presented in an easy-to-read
format. You can use this chapter as a quick-reference source when writing application programs. Figure 4-1
illustrates the important features of the standard register description format.
Control register descriptions are arranged in alphabetical order according to register mnemonic. More detailed
information about control registers is presented in the context of the specific peripheral hardware descriptions in
Part II of this manual.
Data and counter registers are not described in detail in this reference chapter. More information about all of the
registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this
manual.
The locations and read/write characteristics of all mapped registers in the KS88C0416/C0424 register file are
listed in Table 4-1. The hardware reset value for each mapped register is described in Chapter 8, “RESET and
Power-Down.”
CONTROL REGISTERS KS88C0416/P0416/C0424/P0424
4-2
Table 4-1. Mapped Registers (Set 1)
Register Name Mnemonic Decimal Hex R/W
Timer 0 counter T0CNT 208 D0H R (note)
Timer 0 data register T0DATA 209 D1H R/W
Timer 0 control register T0CON 210 D2H R/W
Basic timer control register BTCON 211 D3H R/W
Clock control register CLKCON 212 D4H R/W
System flags register FLAGS 213 D5H R/W
Register pointer 0 RP0 214 D6H R/W
Register pointer 1 RP1 215 D7H R/W
Location D8H is not mapped.
Stack pointer (low byte) SPL 217 D9H R/W
Instruction pointer (high byte) IPH 218 DAH R/W
Instruction pointer (low byte) IPL 219 DBH R/W
Interrupt request register IRQ 220 DCH R (note)
Interrupt mask register IMR 221 DDH R/W
System mode register SYM 222 DEH R/W
Register page pointer PP 223 DFH R/W
Port 0 data register P0 224 E0H R/W
Port 1 data register P1 225 E1H R/W
Port 2 data register P2 226 E2H R/W
Port 3 data register P3 227 E3H R/W
Location E4H is not mapped.
Port 2 interrupt enable register P2INT 229 E5H R/W
Port 2 interrupt pending register P2PND 230 E6H R/W
Port 0 pull-up resistor enable register P0PUR 231 E7H R/W
Port 0 control register (high byte) P0CONH 232 E8HR/W
Port 0 control register (low byte) P0CONL 233 E9HR/W
Port 1 control register (high byte) P1CONH234 EAHR/W
Port 1 control register (low byte) P1CONL 235 EBHR/W
Port 1 pull-up enable register P1PUR 236 ECH R/W
Port 2 pull-up enable register P2PUR 237 EDH R/W
Port 2 control register (high byte) P2CONH 238 EEH R/W
Port 2 control register (low byte) P2CONL 239 EFH R/W
Port 3 control register P3CON 240 F0H R/W
KS88C0416/P0416/C0424/P0424 CONTROL REGISTERS
4-3
Table 4-1. Mapped Registers (Continued)
Register Name Mnemonic Decimal Hex R/W
Port 0 interrupt enable register P0INT 241 F1H R/W
Port 0 interrupt pending register P0PND 242 F2H R/W
Counter A control register CACON 243 F3H R/W
Counter A data register (high byte) CADATAH 244 F4H R/W
Counter A data register (low byte) CADATAL 245 F5H R/W
Timer 1 counter register (high byte) T1CNTH 246 F6H R (note)
Timer 1 counter register (low byte) T1CNTL 247 F7H R (note)
Timer 1 data register (high byte) T1DATAH 248 F8H R/W
Timer 1 data register (low byte) T1DATAL 249 F9H R/W
Timer 1 control register T1CON 250 FAH R/W
STOP Control register STOPCON 251 FBH W
Locations FCH is not mapped.
Basic timer counter BTCNT 253 FDH R (note)
External memory timing register EMT 254 FEH R/W
Interrupt priority register IPR 255 FFH R/W
NOTE:You cannot use a read-only register as a destination for the instructions OR, AND, LD, or LDB.
CONTROL REGISTERS KS88C0416/P0416/C0424/P0424
4-4
FLAGS — System Flags Register D5H Set 1
Bit Identifier
RESET Value
Read/Write
Addressing Mode
.7
.6
Carry Flag (C)
0
1Operation does not generate a carry or borrow condition
Operation generates a carry-out or a borrow in the high-order bit 7
Register
mnemonic Full register name Register address
(hexadecimal)
Bit number:
MSB = Bit 7
LSB = Bit 0
R
W
R/W
'–'
=
=
=
=
Read-only
Write-only
Read/write
Not used
Bit number(s) that is/are appended to
the register name for bit addressing
Description of the
effect of specific
bit settings
Name of an individual
bit or a bit function
Addressing mode/
modes you can use to
modify register values
Register addressing mode only
.7 .6 .5 .4 .3 .2 .1 .0
x x x x x x 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Not used
Undetermined value
Logic zero
Logic one
'–'
'x'
'0'
'1'
=
=
=
=
RESET value notation:
Register location
in the internal
register file
Zero Flag (Z)
0
1Operation result is a non-zero value
Operation result is zero
Sign Flag (S)
0
1Operation generates a positive number (MSB = "0")
Operation generates a negative number (MSB = "1")
.5
Figure 4-1. Register Description Format
KS88C0416/P0416/C0424/P0424 CONTROL REGISTERS
4-5
BTCON — Basic Timer Control Register D3H Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.4 Watchdog Timer Function Disable Code (for System Reset)
1010Disable watchdog timer function
Others Enable watchdog timer function
.3 and .2 Basic Timer Input Clock Selection Bits
0 0 fOSC/4096
0 1 fOSC/1024
1 0 fOSC/128
1 1 Invalid setting; not used for the KS88C0416/C0424
.1 Basic Timer Counter Clear Bit (1)
0No effect
1Clear the basic timer counter value
.0 Clock Frequency Divider Clear Bit for Basic Timer and Timer 0 (2)
0No effect
1Clear both clock frequency dividers
NOTES:
1. When you write a “1” to BTCON.1, the basic timer counter value is cleared to "00H". Immediately following the write
operation, the BTCON.1 value is automatically cleared to “0”.
2. When you write a "1" to BTCON.0, the corresponding frequency divider is cleared to "00H". Immediately following the
write operation, the BTCON.0 value is automatically cleared to "0".
CONTROL REGISTERS KS88C0416/P0416/C0424/P0424
4-6
CACON — Counter A Control Register F3H Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7 and .6 Counter A Input Clock Selection Bits
0 0 fOSC
0 1 fOSC/2
1 0 fOSC/4
1 1 fOSC/8
.5 and .4 Counter A Interrupt Timing Selection Bits
0 0 Elapsed time for Low data value
0 1 Elapsed time for High data value
1 0 Elapsed time for combined Low and High data values
1 1 Invalid setting; not used for the KS88C0416/C0424
.3 Counter A Interrupt Enable Bit
0Disable interrupt
1Enable interrupt
.2 Counter A Start Bit
0Stop counter A
1Start counter A
.1 Counter A Mode Selection Bit
0One-shot mode
1Repeating mode
.0 Counter A Output Flip-Flop Control Bit
0Flip-Flop Low level (T-FF = Low)
1Flip-flop High level (T-FF = High)
KS88C0416/P0416/C0424/P0424 CONTROL REGISTERS
4-7
CLKCON — System Clock Control Register D4H Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value –––00000
Read/Write –––R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.5 Not used for the KS88C0416/C0424
.4 and .3 CPU Clock (System Clock) Selection Bits (1)
0 0 fOSC/16
0 1 fOSC/8
1 0 fOSC/2
1 1 fOSC (non-divided)
.2–.0 Subsystem Clock Selection Bits (2)
101Invalid setting for the KS88C0416/C0424
Others Select main system clock (MCLK)
NOTES:
1. After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load the
appropriate values to CLKCON.3 and CLKCON.4.
2. These selection bits are required only for systems that have a main clock and a subsystem clock. The
KS88C0416/C0424 use only the main oscillator clock circuit. For this reason, the setting "101B" is invalid.
CONTROL REGISTERS KS88C0416/P0416/C0424/P0424
4-8
EMT — External Memory Timing Register (note) FEH Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value 0111110–
Read/Write R/W R/W R/W R/W R/W R/W R/W –
Addressing Mode Register addressing mode only
.7 External WAIT Input Function Enable Bit
0Disable WAIT input function for external device
1Enable WAIT input function for external device
.6 Slow Memory Timing Enable Bit
0Disable slow memory timing
1Enable slow memory timing
.5 and .4 Program Memory Automatic Wait Control Bits
0 0 No wait
0 1 Wait one cycle
1 0 Wait two cycles
1 1 Wait three cycles
.3 and .2 Data Memory Automatic Wait Control Bits
0 0 No wait
0 1 Wait one cycle
1 0 Wait two cycles
1 1 Wait three cycles
.1 Stack Area Selection Bit
0Select internal register file area
1Select external data memory area
.0 Not used for the KS88C0416/C0424
NOTE:Not used for the KS88C0416/C0424. As an external peripheral interface is not implemented in the
KS88C0416/C0424, the EMT register is not used. The program initialization routine should clear the EMT register to
"00H" after a reset. Modification of the EMT values during a normal operation may cause a system malfunction.
KS88C0416/P0416/C0424/P0424 CONTROL REGISTERS
4-9
FLAGS — System Flags Register D5H Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value xxxxxx0 0
Read/Write R/W R/W R/W R/W R/W R/W RR/W
Addressing Mode Register addressing mode only
.7 Carry Flag (C)
0Operation does not generate a carry or a borrow condition
1Operation generates a carry-out or a borrow into high-order bit 7
.6 Zero Flag (Z)
0Operation result is a non-zero value
1Operation result is zero
.5 Sign Flag (S)
0Operation generates a positive number (MSB = "0")
1Operation generates a negative number (MSB = "1")
.4 Overflow Flag (V)
0Operation result is ≤ +127 or ≥ –128
1Operation result is > +127 or < –128
.3 Decimal Adjust Flag (D)
0Add operation completed
1Subtraction operation completed
.2 Half-Carry Flag (H)
0No carry-out of bit 3 by addition or no borrow into bit 3 by subtraction
1Addition generated a carry-out of bit 3 or subtraction generated a borrow into
bit 3
.1 Fast Interrupt Status Flag (FIS)
0Interrupt return (IRET) in progress (when read)
1Fast interrupt service routine in progress (when read)
.0 Bank Address Selection Flag (BA)
0Bank 0 is selected (normal setting for the KS88C0416/C0424)
1Invalid selection (bank 1 is not implemented)
CONTROL REGISTERS KS88C0416/P0416/C0424/P0424
4-10
IMR — Interrupt Mask Register DDH Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value xxxx––x x
Read/Write R/W R/W R/W R/W – – R/W R/W
Addressing Mode Register addressing mode only
.7 Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P0.7–P0.4
0Disable (mask)
1Enable (un-mask)
.6 Interrupt Level 6 (IRQ6) Enable Bit; External Interrupts P0.3–P0.0
0Disable (mask)
1Enable (un-mask)
.5 Interrupt Level 5 (IRQ5) Enable Bit; External Interrupts P2.3–P2.0
0Disable (mask)
1Enable (un-mask)
.4 Interrupt Level 4 (IRQ4) Enable Bit; Counter A Interrupt
0Disable (mask)
1Enable (un-mask)
.3 and .2 Not used for the KS88C0416/C0424
.1 Interrupt Level 1 (IRQ1) Enable Bit; Timer 1 Match/Capture or Overflow
0Disable (mask)
1Enable (un-mask)
.0 Interrupt Level 0 (IRQ0) Enable Bit; Timer 0 Match/Capture or Overflow
0Disable (mask)
1Enable (un-mask)
NOTES:
1. When an interrupt level is masked, any interrupt request is not recognized by the CPU.
2. The interrupt levels, IRQ2 and IRQ3, are not used in the KS88C0416/C0424 interrupt structure.
KS88C0416/P0416/C0424/P0424 CONTROL REGISTERS
4-11
IPH — Instruction Pointer (High Byte)DAH Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value xxxxxxxx
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.0 Instruction Pointer Address (High Byte)
The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction
pointer address (IP15–IP8). The lower byte of the IP address is located in the IPL
register (DBH).
IPL — Instruction Pointer (Low Byte)DBH Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value xxxxxxxx
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.0 Instruction Pointer Address (Low Byte)
The low-byte instruction pointer value is the lower eight bits of the 16-bit instruction
pointer address (IP7–IP0). The upper byte of the IP address is located in the IPH
register (DAH).
CONTROL REGISTERS KS88C0416/P0416/C0424/P0424
4-12
IPR — Interrupt Priority Register FFH Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value xxxxxxxx
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7, .4, and .1 Priority Control Bits for Interrupt Groups A, B, and C
000Group priority undefined
001B > C > A
010A > B > C
011B > A > C
100C > A > B
101C > B > A
110A > C > B
111Group priority undefined
.6 Interrupt Subgroup C Priority Control Bit
0IRQ6 > IRQ7
1IRQ7 > IRQ6
.5 Interrupt Group C Priority Control Bit
0IRQ5 > (IRQ6, IRQ7)
1(IRQ6, IRQ7) > IRQ5
.3 Interrupt Subgroup B Priority Control Bit (note)
0IRQ4
1IRQ4
.2 Interrupt Group B Priority Control Bit (note)
0IRQ4
1IRQ4
.0 Interrupt Group A Priority Control Bit
0IRQ0 > IRQ1
1IRQ1 > IRQ0
NOTE:The KS88C0416/C0424 interrupt structure uses only six levels: IRQ0, IRQ1, and IRQ4–IRQ7. Because IRQ2 and
IRQ3 are not recognized, the interrupt B group and the subgroup settings (IPR.2 and IPR.3) are not evaluated.
KS88C0416/P0416/C0424/P0424 CONTROL REGISTERS
4-13
IRQ — Interrupt Request Register DCH Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value 0000––00
Read/Write RRRR– – R R
Addressing Mode Register addressing mode only
.7Level 7 (IRQ7) Request Pending Bit; External Interrupts P0.7–P0.4
0Not pending
1Pending
.6 Level 6 (IRQ6) Request Pending Bit; External Interrupts P0.3–P0.0
0Not pending
1Pending
.5 Level 5 (IRQ5) Request Pending Bit; External Interrupts P2.3–P2.0
0Not pending
1Pending
.4 Level 4 (IRQ4) Request Pending Bit; Counter A Interrupt
0Not pending
1Pending
.3 and .2 Not used for the KS88C0416/C0424
.1 Level 1 (IRQ1) Request Pending Bit; Timer 1 Match/Capture or Overflow
0Not pending
1Pending
.0 Level 0 (IRQ0) Request Pending Bit; Timer 0 Match/Capture or Overflow
0Not pending
1Pending
NOTE:The interrupt levels, IRQ2 and IRQ3, are not used in the KS88C0416/C0424 interrupt structure.
CONTROL REGISTERS KS88C0416/P0416/C0424/P0424
4-14
P0CONH — Port 0 Control Register (High Byte)E8H Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7 and .6 P0.7/INT4 Mode Selection Bits
0 0 C-MOS input mode; interrupt on falling edges
0 1 C-MOS input mode; interrupt on rising and falling edges
1 0 Push-pull output mode
1 1 C-MOS input mode; interrupt on rising edges
.5 and .4 P0.6/INT4 Mode Selection Bits
0 0 C-MOS input mode; interrupt on falling edges
0 1 C-MOS input mode; interrupt on rising and falling edges
1 0 Push-pull output mode
1 1 C-MOS input mode; interrupt on rising edges
.3 and .2 P0.5/INT4 Mode Selection Bits
0 0 C-MOS input mode; interrupt on falling edges
0 1 C-MOS input mode; interrupt on rising and falling edges
1 0 Push-pull output mode
1 1 C-MOS input mode; interrupt on rising edges
.1 and .0 P0.4/INT4 Mode Selection Bits
0 0 C-MOS input mode; interrupt on falling edges
0 1 C-MOS input mode; interrupt on rising and falling edges
1 0 Push-pull output mode
1 1 C-MOS input mode; interrupt on rising edges
NOTES:
1. The INT4 external interrupts at the P0.7–P0.4 pins share the same interrupt level (IRQ7) and interrupt vector address
(E8H).
2. You can assign pull-up resistors to individual port 0 pins by making the appropriate settings to the P0PUR register.
KS88C0416/P0416/C0424/P0424 CONTROL REGISTERS
4-15
P0CONL — Port 0 Control Register (Low Byte)E9HSet 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7 and .6 P0.3/INT3 Mode Selection Bits
0 0 C-MOS input mode; interrupt on falling edges
0 1 C-MOS input mode; interrupt on rising and falling edges
1 0 Push-pull output mode
1 1 C-MOS input mode; interrupt on rising edges
.5 and .4 P0.2/INT2 Mode Selection Bits
0 0 C-MOS input mode; interrupt on falling edges
0 1 C-MOS input mode; interrupt on rising and falling edges
1 0 Push-pull output mode
1 1 C-MOS input mode; interrupt on rising edges
.3 and .2 P0.1/INT1 Mode Selection Bits
0 0 C-MOS input mode; interrupt on falling edges
0 1 C-MOS input mode; interrupt on rising and falling edges
1 0 Push-pull output mode
1 1 C-MOS input mode; interrupt on rising edges
.1 and .0 P0.0/INT0 Mode Selection Bits
0 0 C-MOS input mode; interrupt on falling edges
0 1 C-MOS input mode; interrupt on rising and falling edges
1 0 Push-pull output mode
1 1 C-MOS input mode; interrupt on rising edges
NOTES:
1. The INT3–INT0 external interrupts at P0.3–P0.0 are in the interrupt level IRQ6. Each interrupt has a separate vector
address.
2. You can assign pull-up resistors to individual port 0 pins by making the appropriate settings to the P0PUR register.
CONTROL REGISTERS KS88C0416/P0416/C0424/P0424
4-16
P0INT — Port 0 External Interrupt Enable Register F1HSet 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7 P0.7 External Interrupt (INT4) Enable Bit
0Disable interrupt
1Enable interrupt
.6 P0.6 External Interrupt (INT4) Enable Bit
0Disable interrupt
1Enable interrupt
.5 P0.5 External Interrupt (INT4) Enable Bit
0Disable interrupt
1Enable interrupt
.4 P0.4 External Interrupt (INT4) Enable Bit
0Disable interrupt
1Enable interrupt
.3 P0.3 External Interrupt (INT3) Enable Bit
0Disable interrupt
1Enable interrupt
.2 P0.2 External Interrupt (INT2) Enable Bit
0Disable interrupt
1Enable interrupt
.1 P0.1 External Interrupt (INT1) Enable Bit
0Disable interrupt
1Enable interrupt
.0 P0.0 External Interrupt (INT0) Enable Bit
0Disable interrupt
1Enable interrupt
KS88C0416/P0416/C0424/P0424 CONTROL REGISTERS
4-17
P0PND — Port 0 External Interrupt Pending Register F2HSet 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7 P0.7 External Interrupt (INT4) Pending Flag (note)
0No P0.7 external interrupt pending (when read)
1P0.7 external interrupt is pending (when read)
.6 P0.6 External Interrupt (INT4) Pending Flag
0No P0.6 external interrupt pending (when read)
1P0.6 external interrupt is pending (when read)
.5 P0.5 External Interrupt (INT4) Pending Flag
0No P0.5 external interrupt pending (when read)
1P0.5 external interrupt is pending (when read)
.4 P0.4 External Interrupt (INT4) Pending Flag
0No P0.4 external interrupt pending (when read)
1P0.4 external interrupt is pending (when read)
.3 P0.3 External Interrupt (INT3) Pending Flag
0No P0.3 external interrupt pending (when read)
1P0.3 external interrupt is pending (when read)
.2 P0.2 External Interrupt (INT2) Pending Flag
0No P0.2 external interrupt pending (when read)
1P0.2 external interrupt is pending (when read)
.1 P0.1 External Interrupt (INT1) Pending Flag
0No P0.1 external interrupt pending (when read)
1P0.1 external interrupt is pending (when read)
.0 P0.0 External Interrupt (INT0) Pending Flag
0No P0.0 external interrupt pending (when read)
1P0.0 external interrupt is pending (when read)
NOTE:To clear an interrupt pending condition, write a “0” to the appropriate pending flag. Writing a “1” to an interrupt
pending flag (P0PND.0–.7) has no effect.
CONTROL REGISTERS KS88C0416/P0416/C0424/P0424
4-18
P0PUR — Port 0 Pull-Up Resistor Enable Register E7HSet 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7 P0.7 Pull-Up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.6 P0.6 Pull-Up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.5 P0.5 Pull-Up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.4 P0.4 Pull-Up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.3 P0.3 Pull-Up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.2 P0.2 Pull-Up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.1 P0.1 Pull-Up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.0 P0.0 Pull-Up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
KS88C0416/P0416/C0424/P0424 CONTROL REGISTERS
4-19
P1CONH — Port 1 Control Register (High Byte)EAH Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7 and .6 P1.7 Mode Selection Bits
0 0 C-MOS input mode
0 1 Open-drain output mode
1 0 Push-pull output mode
1 1 Invalid selection
.5 and .4 P1.6 Mode Selection Bits
0 0 C-MOS input mode
0 1 Open-drain output mode
1 0 Push-pull output mode
1 1 Invalid selection
.3 and .2 P1.5 Mode Selection Bits
0 0 C-MOS input mode
0 1 Open-drain output mode
1 0 Push-pull output mode
1 1 Invalid selection
.1 and .0 P1.4 Mode Selection Bits
0 0 C-MOS input mode
0 1 Open-drain output mode
1 0 Push-pull output mode
1 1 Invalid selection
NOTE:Pull-up resistors can be assigned to individual port 1 pins by making the appropriate settings to the P1PUR control
register, location ECH, set 1.
CONTROL REGISTERS KS88C0416/P0416/C0424/P0424
4-20
P1CONL — Port 1 Control Register (Low Byte)EBHSet 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7 and .6 P1.3 Mode Selection Bits
0 0 C-MOS input mode
0 1 Open-drain output mode
1 0 Push-pull output mode
1 1 Invalid selection
.5 and .4 P1.2 Mode Selection Bits
0 0 C-MOS input mode
0 1 Open-drain output mode
1 0 Push-pull output mode
1 1 Invalid selection
.3 and .2 P1.1 Mode Selection Bits
0 0 C-MOS input mode
0 1 Open-drain output mode
1 0 Push-pull output mode
1 1 Invalid selection
.1 and .0 P1.0 Mode Selection Bits
0 0 C-MOS input mode
0 1 Open-drain output mode
1 0 Push-pull output mode
1 1 Invalid selection
NOTE:Pull-up resistors can be assigned to individual port 1 pins by making the appropriate settings to the P1PUR control
register, location ECH, set 1.
KS88C0416/P0416/C0424/P0424 CONTROL REGISTERS
4-21
P1PUR — Port 1 Pull-Up Resistor Enable Register ECHSet 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7 P1.7 Pull-Up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.6 P1.6 Pull-Up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.5 P1.5 Pull-Up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.4 P1.4 Pull-Up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.3 P1.3 Pull-Up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.2 P1.2 Pull-Up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.1 P1.1 Pull-Up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.0 P1.0 Pull-Up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
CONTROL REGISTERS KS88C0416/P0416/C0424/P0424
4-22
P2CONH — Port 2 Control Register (High Byte)EEHSet 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7 and .6 P2.7 Mode Selection Bits
0 0 C-MOS input mode
0 1 Open-drain output mode
1 0 Push-pull output mode
1 1 Invalid selection
.5 and .4 P2.6 Mode Selection Bits
0 0 C-MOS input mode
0 1 Open-drain output mode
1 0 Push-pull output mode
1 1 Invalid selection
.3 and .2 P2.5 Mode Selection Bits
0 0 C-MOS input mode
0 1 Open-drain output mode
1 0 Push-pull output mode
1 1 Invalid selection
.1 and .0 P2.4 Mode Selection Bits
0 0 C-MOS input mode
0 1 Open-drain output mode
1 0 Push-pull output mode
1 1 Invalid selection
NOTE:Pull-up resistors can be assigned to individual port 2 pins by making the appropriate settings to the P2PUR control
register, location EDH, set 1.
KS88C0416/P0416/C0424/P0424 CONTROL REGISTERS
4-23
P2CONL — Port 2 Control Register (Low Byte)EFHSet 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7 and .6 P2.3 Mode Selection Bits
0 0 C-MOS input mode; interrupt on falling edges
0 1 Open-drain output mode
1 0 Push-pull output mode
1 1 C-MOS input mode; interrupt on rising edges
.5 and .4 P2.2 Mode Selection Bits
0 0 C-MOS input mode; interrupt on falling edges
0 1 Open-drain output mode
1 0 Push-pull output mode
1 1 C-MOS input mode; interrupt on rising edges
.3 and .2 P2.1 Mode Selection Bits
0 0 C-MOS input mode; interrupt on falling edges
0 1 Open-drain output mode
1 0 Push-pull output mode
1 1 C-MOS input mode; interrupt on rising edges
.1 and .0 P2.0 Mode Selection Bits
0 0 C-MOS input mode; interrupt on falling edges
0 1 Open-drain output mode
1 0 Push-pull output mode
1 1 C-MOS input mode; interrupt on rising edges
NOTE:Pull-up resistors can be assigned to individual port 2 pins by making the appropriate settings to the P2PUR control
register, location EDH, set 1.
CONTROL REGISTERS KS88C0416/P0416/C0424/P0424
4-24
P2INT — Port 2 External Interrupt Enable Register E5HSet 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value ––––0000
Read/Write ––––R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.4 Not used for the KS88C0416/C0424
.3 P2.3 External Interrupt (INT8) Enable Bit
0Disable interrupt
1Enable interrupt
.2 P2.2 External Interrupt (INT7) Enable Bit
0Disable interrupt
1Enable interrupt
.1 P2.1 External Interrupt (INT6) Enable Bit
0Disable interrupt
1Enable interrupt
.0 P2.0 External Interrupt (INT5) Enable Bit
0Disable interrupt
1Enable interrupt
KS88C0416/P0416/C0424/P0424 CONTROL REGISTERS
4-25
P2PND — Port 2 External Interrupt Pending Register E6HSet 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value ––––0000
Read/Write ––––R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.4 Not used for the KS88C0416/C0424
.3 P2.3 External Interrupt (INT8) Pending Flag
0No P2.3 external interrupt pending (when read)
1P2.3 external interrupt is pending (when read)
.2 P2.2 External Interrupt (INT7) Pending Flag
0No P2.2 external interrupt pending (when read)
1P2.2 external interrupt is pending (when read)
.1 P2.1 External Interrupt (INT6) Pending Flag
0No P2.1 external interrupt pending (when read)
1P2.1 external interrupt is pending (when read)
.0 P2.0 External Interrupt (INT5) Pending Flag
0No P2.0 external interrupt pending (when read)
1P2.0 external interrupt is pending (when read)
NOTE:To clear an interrupt pending condition, write a “0” to the appropriate pending flag. Writing a “1” to an interrupt
pending flag (P2PND.0–.3) has no effect.
CONTROL REGISTERS KS88C0416/P0416/C0424/P0424
4-26
P2PUR — Port 2 Pull-Up Resistor Enable Register EDHSet 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7 P2.7 Pull-Up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.6 P2.6 Pull-Up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.5 P2.5 Pull-Up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.4 P2.4 Pull-Up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.3 P2.3 Pull-Up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.2 P2.2 Pull-Up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.1 P2.1 Pull-Up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
.0 P2.0 Pull-Up Resistor Enable Bit
0Disable pull-up resistor
1Enable pull-up resistor
KS88C0416/P0416/C0424/P0424 CONTROL REGISTERS
4-27
P3CON — Port 3 Control Register F0HSet 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.5 P3.1 Configuration Bits
0x0C-MOS input mode (P3.1/T0CK)
1x0C-MOS input mode with pull-up (P3.1/T0CK)
001Push-pull output mode (P3.1/REM)
011Open-drain output mode (P3.1/REM)
111Open-drain output mode with pull-up (P3.1/REM)
.4 P3.1 Alternative Function Enable Bit
0Normal I/O function (P3.1)
1REM/T0CK
.3 P3.0 Alternative Function Enable Bit
0Normal I/O function (P3.0)
1T0PWM/T0_T1CAP
.2–.0 P3.0 Configuration Bits
0x0C-MOS input mode (P3.0/T0_T1CAP)
1x0C-MOS input mode with pull-up (P3.0/T0_T1CAP)
001Push-pull output mode (P3.0/T0PWM)
011Open-drain output mode (P3.0/T0PWM)
111Open-drain output mode with pull-up (P3.0/T0PWM)
NOTES:
1. An "x" means that the bit setting is not evaluated (doesn’t matter).
2. The port 3 data register, P3, at location E3H, contains three bit values which correspond to the following port 3 pin
functions (other data register bits are not used for the KS88C0416/C0424):
a. P3, bit 5: carrier signal on (“1”) or off (“0”).
b. P3, bit 1: P3.1/REM/T0CK pin status.
c. P3, bit 0: P3.0/T0PWM/T0CAP/T1CAP pin level.
CONTROL REGISTERS KS88C0416/P0416/C0424/P0424
4-28
PP — Register Page Pointer DFH Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.4 Destination Register Page Selection Bits
0000Destination: page 0 (note)
.3–.0 Source Register Page Selection Bits
0000Source: page 0 (note)
NOTE:In the KS88C0416/C0424 microcontroller, a paged expansion of the internal register file is not implemented. For this
reason, only page 0 settings are valid. Register page pointer values for the source and the destination register page
are automatically set to "0000B" following a hardware reset. These values should not be changed during the normal
operation.
KS88C0416/P0416/C0424/P0424 CONTROL REGISTERS
4-29
RP0 — Register Pointer 0 D6H Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value 11000–––
Read/Write R/W R/W R/W R/W R/W –––
Addressing Mode Register addressing only
.7–.3 Register Pointer 0 Address Value
Register pointer 0 can independently point to one of the 24 8-byte working register
areas in the register file. Using the register pointers RP0 and RP1, you can select
two 8-byte register slices at one time as active working register space. After a reset,
RP0 points to the address C0H in the register set 1, selecting the 8-byte working
register slice C0H–C7H.
.2–.0 Not used for the KS88C0416/C0424
RP1 — Register Pointer 1 D7H Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value 11001–––
Read/Write R/W R/W R/W R/W R/W –––
Addressing Mode Register addressing only
.7–.3 Register Pointer 1 Address Value
Register pointer 1 can independently point to one of the 24 8-byte working register
areas in the register file. Using the register pointers RP0 and RP1, you can select
two 8-byte register slices at one time as active working register space. After a reset,
RP1 points to the address C8H in the register set 1, selecting the 8-byte working
register slice C8H–CFH.
.2–.0 Not used for the KS88C0416/C0424
CONTROL REGISTERS KS88C0416/P0416/C0424/P0424
4-30
SPL — Stack Pointer (Low Byte)D9H Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value xxxxxxxx
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7–.0 Stack Pointer Address (Low Byte)
The SP value is undefined after a reset.
KS88C0416/P0416/C0424/P0424 CONTROL REGISTERS
4-31
STOPCON — Stop Control Register FBHSet 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value 00000000
Read/Write WWWWWWWW
Addressing Mode Register addressing mode only
.7–.0 Stop Control Register enable bits
1 0 1 0 0 1 0 1 Enable STOP mode
NOTES:
1. To get into STOP mode, the stop control register must be enabled just before the STOP instruction.
2. When STOP mode is released, the stop control register (STOPCON) value is cleared automatically.
3. It is prohibited to write another value into STOPCON.
CONTROL REGISTERS KS88C0416/P0416/C0424/P0424
4-32
SYM — System Mode Register DEH Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value 0––xxx0 0
Read/Write R/W – – R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7 Tri-State External Interface Control Bit (1)
0Normal operation (disable tri-state operation)
1Set external interface lines to high impedance (enable tri-state operation)
.6 and .5 Not used for the KS88C0416/C0424
.4–.2 Fast Interrupt Level Selection Bits (2)
000IRQ0
001IRQ1
010Not used for the KS88C0416/C0424
011Not used for the KS88C0416/C0424
100IRQ4
101IRQ5
110IRQ6
111IRQ7
.1 Fast Interrupt Enable Bit (3)
0Disable fast interrupt processing
1Enable fast interrupt processing
.0 Global Interrupt Enable Bit (4)
0Disable global interrupt processing
1Enable global interrupt processing
NOTES:
1. Because an external interface is not implemented for the KS88C0416/C0424, SYM.7 must always be "0".
2. You can select only one interrupt level at a time for fast interrupt processing.
3. Setting SYM.1 to "1" enables fast interrupt processing for the interrupt level currently selected by SYM.2–SYM.4.
4. After a reset, you must enable global interrupt processing by executing an EI instruction (not by writing a "1"
to SYM.0).
KS88C0416/P0416/C0424/P0424 CONTROL REGISTERS
4-33
T0CON — Timer 0 Control Register D2H Set 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7 and .6 Timer 0 Input Clock Selection Bits
0 0 fOSC/4096
0 1 fOSC/256
1 0 fOSC/8
1 1 External clock input (at the T0CK pin, P3.1)
.5 and .4 Timer 0 Operating Mode Selection Bits
0 0 Interval timer mode (counter cleared by match signal)
0 1 Capture mode (rising edges, counter running, OVF interrupt can occur)
1 0 Capture mode (falling edges, counter running, OVF interrupt can occur)
1 1 PWM mode (OVF interrupt can occur)
.3 Timer 0 Counter Clear Bit
0No effect (when write)
1Clear T0 counter, T0CNT (when write)
.2 Timer 0 Overflow Interrupt Enable Bit (note)
0Disable T0 overflow interrupt
1Enable T0 overflow interrupt
.1 Timer 0 Match/Capture Interrupt Enable Bit
0Disable T0 match/capture interrupt
1Enable T0 match/capture interrupt
.0 Timer 0 Match/Capture Interrupt Pending Flag
0No T0 match/capture interrupt pending (when read)
0Clear T0 match/capture interrupt pending condition (when write)
1T0 match/capture interrupt is pending (when read)
1No effect (when write)
NOTE:A timer 0 overflow interrupt pending condition is automatically cleared by hardware. However, the timer 0 match/
capture interrupt, IRQ0, vector FCH, must be cleared by the interrupt service routine.
CONTROL REGISTERS KS88C0416/P0416/C0424/P0424
4-34
T1CON — Timer 1 Control Register FAHSet 1
Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0
RESET Value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Addressing Mode Register addressing mode only
.7 and .6 Timer 1 Input Clock Selection Bits
0 0 fOSC/4
0 1 fOSC/8
1 0 fOSC/16
1 1 Internal clock (counter A flip-flop, T-FF)
.5 and .4 Timer 1 Operating Mode Selection Bits
0 0 Interval timer mode (counter cleared by match signal)
0 1 Capture mode (rising edges, counter running, OVF can occur)
1 0 Capture mode (falling edges, counter running, OVF can occur)
1 1 Capture mode (rising and falling edges, counter running, OVF can occur)
.3 Timer 1 Counter Clear Bit
0No effect (when write)
1Clear T1 counter, T1CNT (when write)
.2 Timer 1 Overflow Interrupt Enable Bit (see Note)
0Disable T1 overflow interrupt
1Enable T1 overflow interrupt
.1 Timer 1 Match/Capture Interrupt Enable Bit
0Disable T1 match/capture interrupt
1Enable T1 match/capture interrupt
.0 Timer 1 Match/Capture Interrupt Pending Flag
0No T1 match/capture interrupt pending (when read)
0Clear T1 match/capture interrupt pending condition (when write)
1T1 match/capture interrupt is pending (when read)
1No effect (when write)
NOTE:A timer 1 overflow interrupt pending condition is automatically cleared by hardware. However, the timer 1 match/
capture interrupt, IRQ1, vector F6H, must be cleared by the interrupt service routine.
KS88C0416/P0416/C0424/P0424 INTERRUPT STRUCTURE
5-1
5INTERRUPT STRUCTURE
OVERVIEW
The KS88-series interrupt structure has three basic components: levels, vectors, and sources. The SAM87 CPU
recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt level
has more than one vector address, the vector priorities are established in hardware. A vector address can be
assigned to one or more sources.
Levels
Interrupt levels are the main unit for interrupt priority assignment and recognition. All peripherals and I/O blocks
can issue interrupt requests. In other words, peripheral and I/O operations are interrupt-driven. There are eight
possible interrupt levels: IRQ0–IRQ7, also called level 0–level 7. Each interrupt level directly corresponds to an
interrupt request number (IRQn). The total number of interrupt levels used in the interrupt structure varies from
device to device. The KS88C0416/C0424 interrupt structure recognizes six interrupt levels.
The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. They are just
identifiers for the interrupt levels that are recognized by the CPU. The relative priority of different interrupt levels
is determined by settings in the interrupt priority register, IPR. Interrupt group and subgroup logic controlled by
IPR settings lets you define more complex priority relationships between different levels.
Vectors
Each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all.
The maximum number of vectors that can be supported for a given level is 128. (The actual number of vectors
used for the KS88-series devices is always much smaller.) If an interrupt level has more than one vector address,
the vector priorities are set in hardware. The KS88C0416/C0424 use fifteen vectors. One vector address is
shared by four interrupt sources.
Sources
A source is any peripheral that generates an interrupt. A source can be an external pin or a counter overflow.
Each vector can have several interrupt sources. In the KS88C0416/C0424 interrupt structure, there are eighteen
possible interrupt sources.
When a service routine starts, the respective pending bit should be either cleared automatically by hardware or
cleared "manually" by program software. The characteristics of the source's pending mechanism determine which
method would be used to clear its respective pending bit.
INTERRUPT STRUCTURE KS88C0416/P0416/C0424/P0424
5-2
INTERRUPT TYPES
The three components of the KS88 interrupt structure described before — levels, vectors, and sources — are
combined to determine the interrupt structure of an individual device and to make full use of its available
interrupt logic. There are three possible combinations of interrupt structure components, called interrupt types 1,
2, and 3. The types differ in the number of vectors and interrupt sources assigned to each level (see Figure 5-1):
Type 1: One level (IRQn) + one vector (V1) + one source (S1)
Type 2: One level (IRQn) + one vector (V1) + multiple sources (S1 – Sn)
Type 3: One level (IRQn) + multiple vectors (V1 – Vn) + multiple sources (S1 – Sn , Sn+1 – Sn+m)
In the KS88C0416/C0424 microcontroller, all three interrupt types are implemented.
NOTES:
1. The number of S n and Vn values is expandable.
2. In the KS88C0416/C0424 implementation, interrupt
types 1 and 3 are used.
SOURCESVECTORSLEVELS
S1
V1
S1
S2
S3
Sn
V1
IRQn
IRQn
IRQn
S1
S2
S3
Sn
Sn + 1
Sn + 2
Sn + m
V1
V2
V3
Vn
TYPE 1:
TYPE 2:
TYPE 3:
Figure 5-1. KS88-Series Interrupt Types
KS88C0416/P0416/C0424/P0424 INTERRUPT STRUCTURE
5-3
KS88C0416/C0424 INTERRUPT STRUCTURE
The KS88C0416/C0424 microcontrollers support eighteen interrupt sources. Fourteen of the interrupt sources
have a corresponding interrupt vector address; the remaining four interrupt sources share the same vector
address. Six interrupt levels are recognized by the CPU in this device-specific interrupt structure, as shown in
Figure 5-2.
When multiple interrupt levels are active, the interrupt priority register (IPR) determines the order in which
contending interrupts are to be serviced. If multiple interrupts occur within the same interrupt level, the interrupt
with the lowest vector address is usually processed first (The relative priorities of multiple interrupts within a
single level are fixed in hardware).
When the CPU grants an interrupt request, interrupt processing starts. All other interrupts are disabled and the
program counter value and status flags are pushed to stack. The starting address of the service routine is fetched
from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the
service routine is executed.
INTERRUPT STRUCTURE KS88C0416/P0416/C0424/P0424
5-4
NOTE: For interrupt levels with two or more vectors, the lowest vector address usually has
the highest priority. For example, FAH has higher priority (0) than FCH (1) within the
level IRQ0. These priorities are fixed in hardware.
VECTOR
LEVEL SOURCE RESET/CLEAR
IRQ0 FCH 1
0Timer 0 match/capture S/W
S/W
IRQ4 ECHCounter A H/W
S/W
IRQ1 F6H 1
0Timer 1 match/capture S/W
FAH
F4H
Timer 0 overflow
Timer 1 overflow H/W
H/W
RESET 100H Basic timer overflow H/W
D6H P2.3 external interrupt S/W
D4HP2.2 external interrupt S/W
1
IRQ5 D2H0P2.1 external interrupt S/W
D0HP2.0 external interrupt S/W
2
3
E6HP0.3 external interrupt S/W
E4HP0.2 external interrupt S/W
1
IRQ6 E2H0P0.1 external interrupt S/W
E0HP0.0 external interrupt S/W
2
3
IRQ7 E8H
P0.7 external interrupt
S/W
S/W
P0.6 external interrupt
P0.5 external interrupt
P0.4 external interrupt
Figure 5-2. KS88C0416/C0424 Interrupt Structure
KS88C0416/P0416/C0424/P0424 INTERRUPT STRUCTURE
5-5
INTERRUPT VECTOR ADDRESSES
All interrupt vector addresses for the KS88C0416/C0424 interrupt structure are stored in the vector address area
of the internal 16/24-Kbyte ROM, 00H–FFH (see Figure 5-3).
You can allocate unused locations in the vector address area as normal program memory. If you do so, please be
careful not to overwrite any of the stored vector addresses (Table 5-1 lists all vector addresses).
The program reset address in the ROM is 0100H.
0
255 0FFH
(DECIMAL) (HEX)
3FFFH
16,383
0H
Interrupt
Vector Area
24,575 5FFFH
Internal Program
Memory (ROM)
KS88C0416
(16-Kbyte)
KS88C0424
(24-Kbyte)
Figure 5-3. ROM Vector Address Area
INTERRUPT STRUCTURE KS88C0416/P0416/C0424/P0424
5-6
Table 5-1. KS88C0416/C0424 Interrupt Vectors
Vector Address Interrupt Source Request Reset/Clear
Decimal
Value Hex
Value Interrupt
Level Priority in
Level H/W S/W
254 100H Basic timer overflow RESET –√
252 FCH Timer 0 (match/capture) IRQ0 1√
250 FAHTimer 0 overflow 0√
246 F6HTimer 1 (match/capture) IRQ1 1√
244 F4HTimer 1 overflow 0√
236 ECH Counter A IRQ4 –√
232 E8H P0.7 external interrupt IRQ7 –√
232 E8H P0.6 external interrupt √
232 E8H P0.5 external interrupt √
232 E8H P0.4 external interrupt √
230 E6H P0.3 external interrupt IRQ6 3√
228 E4H P0.2 external interrupt 2√
226 E2H P0.1 external interrupt 1√
224 E0H P0.0 external interrupt 0√
214 D6H P2.3 external interrupt IRQ5 3√
212 D4H P2.2 external interrupt 2√
210 D2H P2.1 external interrupt 1√
208 D0H P2.0 external interrupt 0√
NOTES:
1. Interrupt priorities are identified in inverse order: "0" is the highest priority, "1" is the next highest, and so on.
2. If two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has
priority over one with a higher vector address. The priorities within a given level are fixed in hardware.
KS88C0416/P0416/C0424/P0424 INTERRUPT STRUCTURE
5-7
ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI)
Executing the Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are then
serviced as they occur, according to the established priorities.
NOTE
The system initialization routine executed after a reset must always contain an EI instruction to globally
enable the interrupt structure.
During the normal operation, you can execute the DI (Disable Interrupt) instruction at any time to globally disable
interrupt processing. The EI and DI instructions change the value of bit 0 in the SYM register. Although you can
directly manipulate SYM.0 to enable or disable interrupts, it is recommended that you use the EI and DI
instructions instead.
SYSTEM-LEVEL INTERRUPT CONTROL REGISTERS
In addition to the control registers for specific interrupt sources, four system-level registers control interrupt
processing:
—The interrupt mask register, IMR, enables (un-masks) or disables (masks) interrupt levels.
—The interrupt priority register, IPR, controls the relative priorities of interrupt levels.
—The interrupt request register, IRQ, contains interrupt pending flags for each interrupt level (as opposed to
each interrupt source).
—The system mode register, SYM, enables or disables global interrupt processing (SYM settings also enable
fast interrupts and control the activity of external interface, if implemented).
Table 5-2. Interrupt Control Register Overview
Control Register ID R/W Function Description
Interrupt mask register IMR R/W Bit settings in the IMR register enable or disable interrupt
processing for each of the six interrupt levels: IRQ0, IRQ1,
and IRQ4–IRQ7.
Interrupt priority register IPR R/W Controls the relative processing priorities of the interrupt
levels. The six levels of the KS88C0416/C0424 are organized
into three groups: A, B, and C. Group A is IRQ0 and IRQ1,
group B is IRQ4, and group C is IRQ5, IRQ6, and IRQ7.
Interrupt request register IRQ RThis register contains a request pending bit for each interrupt
level.
System mode register SYM R/W Dynamic global interrupt processing enable/disable, fast
interrupt processing, and external interface control (An
external memory interface is not implemented in the
KS88C0416/C0424 microcontroller).
INTERRUPT STRUCTURE KS88C0416/P0416/C0424/P0424
5-8
INTERRUPT PROCESSING CONTROL POINTS
Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source.
Among the system-level control points in the interrupt structure are:
—Global interrupt enabled and disabled (by EI and DI instructions or by direct manipulation of SYM.0 )
—Interrupt level enable/disable settings (IMR register)
—Interrupt level priority settings (IPR register)
—Interrupt source enable/disable settings in the corresponding peripheral control registers
NOTE
When writing an application program that deals with interrupt processing, be sure to include the
necessary register file address (register pointer) information.
SQ
R
EI
RESET
POLLING
CYCLE
INTERRUPT REQUEST
REGISTER (Read-only)
IRQ0, IRQ1,
and IRQ4-IRQ7
INTERRUPTS
VECTOR
INTERRUPT
CYCLE
INTERRUPT MASK
REGISTER
INTERRUPT PRIORITY
REGISTER
GLOBAL INTERRUPT
CONTROL (EI, DI, or
SYM.0 manipulation)
a
Figure 5-4. Interrupt Function Diagram
KS88C0416/P0416/C0424/P0424 INTERRUPT STRUCTURE
5-9
PERIPHERAL INTERRUPT CONTROL REGISTERS
For each interrupt source there is one or more corresponding peripheral control registers that let you control the
interrupt generated by that peripheral (see Table 5-3).
Table 5-3. Interrupt Source Control and Data Registers
Interrupt Source Interrupt Level Register(s) Location(s) in Set 1
Timer 0 match/capture or
timer 0 overflow IRQ0 T0CON (note)
T0DATA D2H
D1H
Timer 1 match/capture or
timer 1 overflow IRQ1 T1CON (note)
T1DATAH, T1DATAL FAH
F8H, F9H
Counter A IRQ4 CACON
CADATAH, CADATAL F3H
F4H, F5H
P0.7 external interrupt
P0.6 external interrupt
P0.5 external interrupt
P0.4 external interrupt
IRQ7 P0CONH
P0INT
P0PND
E8H
F1H
F2H
P0.3 external interrupt
P0.2 external interrupt
P0.1 external interrupt
P0.0 external interrupt
IRQ6 P0CONL
P0INT
P0PND
E9H
F1H
F2H
P2.3 external interrupt
P2.2 external interrupt
P2.1 external interrupt
P2.0 external interrupt
IRQ5 P2CONL
P2INT
P2PND
EFH
E5H
E6H
NOTE:Because the timer 0 and timer 1 overflow interrupts are cleared by hardware, the T0CON and T1CON registers
control only the enable/disable functions. The T0CON and T1CON registers contain enable/disable and pending
bits for the timer 0 and timer 1 match/capture interrupts, respectively.
INTERRUPT STRUCTURE KS88C0416/P0416/C0424/P0424
5-10
SYSTEM MODE REGISTER (SYM)
The system mode register, SYM (set 1, DEH), is used to globally enable and disable interrupt processing and to
control fast interrupt processing (see Figure 5-5).
A reset clears SYM.7, SYM.1, and SYM.0 to "0". The 3-bit value for fast interrupt level selection, SYM.4–SYM.2,
is undetermined.
The instructions EI and DI enable and disable global interrupt processing, respectively, by modifying the bit 0
value of the SYM register. In order to enable interrupt processing, an Enable Interrupt (EI) instruction must be
included in the initialization routine, which follows a reset operation. Although you can manipulate SYM.0 directly
to enable and disable interrupts during the normal operation, it is recommended to use the EI and DI instructions
for this purpose.
External interface tri-state enable bit:
0= Normal operation (Tri-state disabled)
1= High impedance (Tri-state enabled)
SYSTEM MODE REGISTER (SYM)
DEH, Set 1, R/W
MSB LSB.7 .6 .5 .4 .3 .2 .1 .0
Not used for the
KS88C0416/C0424
Global interrupt enable bit:
0 = Disable all interrupts
1 = Enable all interrupts
Fast interrupt level selection bits:
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
IRQ0
IRQ1
Not used
Not used
IRQ4
IRQ5
IRQ6
IRQ7
Fast interrupt enable bit:
0 = Disable fast interrupts
1 = Enable fast interrupts
NOTE: Because an external memory interface is not implemented for the
KS88C0416/C0424, SYM.7 must always be “0”.
(note)
Figure 5-5. System Mode Register (SYM)
KS88C0416/P0416/C0424/P0424 INTERRUPT STRUCTURE
5-11
INTERRUPT MASK REGISTER (IMR)
The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual
interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required
settings by the initialization routine.
Each IMR bit corresponds to a specific interrupt level: bit 1 to IRQ1, bit 2 to IRQ2, and so on. When the IMR bit
of an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). When you set a
level's IMR bit to "1", interrupt processing for the level is enabled (not masked).
The IMR register is mapped to the register location DDH in set 1. Bit values can be read and written by
instructions using Register addressing mode.
INTERRUPT MASK REGISTER (IMR)
DDH, Set 1, R/W
MSB LSB.7 .6 .5 .4 .3 .2 .1 .0
IRQ7 IRQ6 IRQ5 IRQ4 Not
used
Not
used
IRQ1 IRQ0
Interrupt level enable bits (7–4, 1, 0):
0 = Disable (mask) interrupt level
1 = Enable (un-mask) interrupt level
Figure 5-6. Interrupt Mask Register (IMR)
INTERRUPT STRUCTURE KS88C0416/P0416/C0424/P0424
5-12
INTERRUPT PRIORITY REGISTER (IPR)
The interrupt priority register, IPR (set 1, bank 0, FFH), is used to set the relative priorities of the interrupt levels
in the microcontroller’s interrupt structure. After a reset, all IPR bit values are undetermined and must therefore
be written to their required settings by the initialization routine.
When more than one interrupt sources are active, the source with the highest priority is serviced first. If two
sources belong to the same interrupt level, the source with the lower vector address usually has priority (This
priority is fixed in hardware).
To support programming of the relative interrupt level priorities, they are organized into groups and subgroups by
the interrupt logic. Please note that these groups (and subgroups) are used only by IPR logic for the IPR register
priority definitions (see Figure 5-7):
Group A IRQ0, IRQ1
Group B IRQ4
Group C IRQ5, IRQ6, IRQ7
IRQ0 IRQ1 IRQ4 IRQ5 IRQ7
A1 A2 C1
IPR
GROUP A IPR
GROUP B IPR
GROUP C
C2
C21 C22
IRQ6
Figure 5-7. Interrupt Request Priority Groups
As you can see in Figure 5-8, IPR.7, IPR.4, and IPR.1 control the relative priority of the interrupt groups A, B, and
C. For example, the setting "001B" for these bits would select the group relationship B > C > A. The setting
"101B" would select the relationship C > B > A.
The functions of other IPR bit settings are as follows:
—IPR.5 controls the relative priorities of the group C interrupts.
—The interrupt group B includes a subgroup that has an additional priority relationship among the interrupt
levels 2, 3, and 4. IPR.3 defines the subgroup B relationship. IPR.2 controls the interrupt group B. In the
KS88C0416/C0424 implementation, the interrupt levels 2 and 3 are not used. Therefore, IPR.2 and IPR.3
settings are not evaluated, as IRQ4 is the only remaining level in the group.
—IPR.0 controls the relative priority setting of IRQ0 and IRQ1 interrupts.
KS88C0416/P0416/C0424/P0424 INTERRUPT STRUCTURE
5-13
GROUP C
0 = IRQ5 > (IRQ6, IRQ7)
1 = (IRQ6, IRQ7) > IRQ5
INTERRUPT PRIORITY REGISTER (IPR)
FFH, Set 1, Bank 0, R/W
GROUP A
0 = IRQ0 > IRQ1
1 = IRQ1 > IRQ0
GROUP B (note)
0 = IRQ4
1 = IRQ4
SUBGROUP B (note)
0 = IRQ4
1 = IRQ4
GROUP PRIORITY:
D7
0
0
0
0
1
1
1
1
D4
0
0
1
1
0
0
1
1
D1
0
1
0
1
0
1
0
1
=
=
=
=
=
=
=
=
UNDEFINED
B > C > A
A > B > C
B > A > C
C > A > B
C > B > A
A > C > B
UNDEFINED
MSB LSB.7 .6 .5 .4 .3 .2 .1 .0
SUBGROUP C
0 = IRQ6 > IRQ7
1 = IRQ7 > IRQ6
NOTE:In the KS88C0416/C0424 interrupt structure, only the levels IRQ0 and IRQ1, and IRQ4-IRQ7
are used. Setting for the group/subgroup B, which control relative priorities for the level IRQ2
and IRQ3 are therefore not evaluated.
Figure 5-8. Interrupt Priority Register (IPR)
INTERRUPT STRUCTURE KS88C0416/P0416/C0424/P0424
5-14
INTERRUPT REQUEST REGISTER (IRQ)
You can poll bit values in the interrupt request register, IRQ (set 1, DCH), to monitor interrupt request status for
all levels in the microcontroller’s interrupt structure. Each bit corresponds to the interrupt level of the same
number: bit 0 to IRQ0, bit 1 to IRQ1, and so on. A "0" indicates that no interrupt request is currently being issued
for that level; a "1" indicates that an interrupt request has been generated for that level.
IRQ bit values are read-only addressable using Register addressing mode. You can read (test) the contents of
the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of
specific interrupt levels. After a reset, all IRQ status bits are cleared to “0”.
You can poll IRQ register values even if a DI instruction has been executed (that is, if global interrupt processing
is disabled). If an interrupt occurs while the interrupt structure is disabled, the CPU will not service it. You can,
however, still detect a interrupt request by polling the IRQ register. In this way, you can determine which events
occurred while the interrupt structure was globally disabled.
INTERRUPT REQUEST REGISTER (IRQ)
DCH, Set 1, Read-only
MSB LSB.7 .6 .5 .4 .3 .2 .1 .0
IRQ7 IRQ6 IRQ5 IRQ4 Not
used
Not
used
IRQ1 IRQ0
0 = Interrupt level is not pending
1 = Interrupt level is pending
Interrupt level request pending bits:
Figure 5-9. Interrupt Request Register (IRQ)
KS88C0416/P0416/C0424/P0424 INTERRUPT STRUCTURE
5-15
INTERRUPT PENDING FUNCTION TYPES
Overview
There are two types of interrupt pending bits: One type that is automatically cleared by hardware after the
interrupt service routine is acknowledged and executed; the other that must be cleared by the interrupt service
routine.
Pending Bits Cleared Automatically by Hardware
For interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding
pending bit to "1" when a request occurs. It then issues an IRQ pulse to inform the CPU that an interrupt is
waiting to be serviced. The CPU acknowledges the interrupt source by sending an IACK, executes the service
routine, and clears the pending bit to "0". This type of pending bit is not mapped and cannot, therefore, be read or
written by application software.
In the KS88C0416/C0424 interrupt structure, the timer 0 and timer 1 overflow interrupts (IRQ0 and IRQ1), and
the counter A interrupt (IRQ4) belong to this category of interrupts whose pending condition is cleared
automatically by hardware.
Pending Bits Cleared by the Service Routine
The second type of pending bit is the one that should be cleared by program software. The service routine must
clear the appropriate pending bit before a return-from-interrupt subroutine (IRET) occurs. To do this, a "0" must
be written to the corresponding pending bit location in the source’s mode or control register.
In the KS88C0416/C0424 interrupt structure, pending conditions for all interrupt sources, except the timer 0 and
timer 1 overflow interrupt and the counter A borrow interrupt, must be cleared by the interrupt service routine.
INTERRUPT STRUCTURE KS88C0416/P0416/C0424/P0424
5-16
INTERRUPT SOURCE POLLING SEQUENCE
The interrupt request polling and servicing sequence is as follows:
1. A source generates an interrupt request by setting the interrupt request bit to "1".
2. The CPU polling procedure identifies a pending condition for that source.
3. The CPU checks the source's interrupt level.
4. The CPU generates an interrupt acknowledge signal.
5. Interrupt logic determines the interrupt's vector address.
6. The service routine starts and the source's pending bit is cleared to "0" (by hardware or by software).
7. The CPU continues polling for interrupt requests.
INTERRUPT SERVICE ROUTINES
Before an interrupt request is serviced, the following conditions must be met:
—Interrupt processing must be globally enabled (EI, SYM.0 = "1")
—The interrupt level must be enabled (IMR register)
—The interrupt level must have the highest priority if more than one levels are currently requesting service
—The interrupt must be enabled at the interrupt's source (peripheral control register)
When all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction
cycle. The CPU then initiates an interrupt machine cycle that completes the following processing sequence:
1. Reset (clear to "0") the interrupt enable bit in the SYM register (SYM.0) to disable all subsequent interrupts.
2. Save the program counter (PC) and status flags to the system stack.
3. Branch to the interrupt vector to fetch the address of the service routine.
4. Pass control to the interrupt service routine.
When the interrupt service routine is completed, the CPU issues an Interrupt Return (IRET). The IRET restores
the PC and status flags, setting SYM.0 to "1". It allows the CPU to process the next interrupt request.
KS88C0416/P0416/C0424/P0424 INTERRUPT STRUCTURE
5-17
GENERATING INTERRUPT VECTOR ADDRESSES
The interrupt vector area in the ROM (00H–FFH) contains the addresses of interrupt service routines that
correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence:
1. Push the program counter's low-byte value to the stack.
2. Push the program counter's high-byte value to the stack.
3. Push the FLAG register values to the stack.
4. Fetch the service routine's high-byte address from the vector location.
5. Fetch the service routine's low-byte address from the vector location.
6. Branch to the service routine specified by the concatenated 16-bit vector address.
NOTE
A 16-bit vector address always begins at an even-numbered ROM address within the range of 00H–FFH.
NESTING OF VECTORED INTERRUPTS
It is possible to nest a higher-priority interrupt request while a lower-priority request is being serviced. To do this,
you must follow these steps:
1. Push the current 8-bit interrupt mask register (IMR) value to the stack (PUSH IMR).
2. Load the IMR register with a new mask value that enables only the higher priority interrupt.
3. Execute an EI instruction to enable interrupt processing (a higher priority interrupt will be processed if it
occurs).
4. When the lower-priority interrupt service routine ends except a DI instruction, return the IMR to its original
value by restoring the previous mask value from the stack (POP IMR).
5. Execute an IRET.
Depending on the application, you may be able to simplify the procedure above to some extent.
INSTRUCTION POINTER (IP)
The instruction pointer (IP) is adopted by all the KS88-series microcontrollers to control the optional high-speed
interrupt processing feature called fast interrupts. The IP consists of register pair DAH and DBH. The names of IP
registers are IPH (high byte, IP15–IP8) and IPL (low byte, IP7–IP0).
FAST INTERRUPT PROCESSING
The feature called fast interrupt processing allows an interrupt within a given level to be completed in
approximately six clock cycles rather than the usual 22 clock cycles. To select a specific interrupt level for fast
interrupt processing, you should write the appropriate 3-bit value to SYM.4–SYM.2. Then, to enable fast interrupt
processing for the selected level, you should set SYM.1 to “1”.
INTERRUPT STRUCTURE KS88C0416/P0416/C0424/P0424
5-18
FAST INTERRUPT PROCESSING (Continued)
Two other system registers support fast interrupt processing:
—The instruction pointer (IP) contains the starting address of the service routine (and is later used to swap the
program counter values), and
—When a fast interrupt occurs, the contents of the FLAGS register is stored in an unmapped, dedicated
register called FLAGS' (“FLAGS prime”).
NOTE
For the KS88C0416/C0424 microcontroller, the service routine for any one of the six interrupt levels,
IRQ0 and IRQ1, or IRQ4–IRQ7, can be selected for fast interrupt processing.
Procedure for Initiating Fast Interrupts
To initiate fast interrupt processing, follow these steps:
1. Load the start address of the service routine into the instruction pointer (IP).
2. Load the interrupt level number (IRQn) into the fast interrupt selection field (SYM.4–SYM.2)
3. Write a "1" to the fast interrupt enable bit in the SYM register.
Fast Interrupt Service Routine
When an interrupt occurs in the level selected for fast interrupt processing, the following events occur:
1. The contents of the instruction pointer and the PC are swapped.
2. The FLAG register values are written to the FLAGS' (“FLAGS prime”) register.
3. The fast interrupt status bit in the FLAGS register is set.
4. The interrupt is serviced.
5. Assuming that the fast interrupt status bit is set, when the fast interrupt service routine ends, the instruction
pointer and PC values are swapped back.
6. The content of FLAGS' (“FLAGS prime”) is copied automatically back to the FLAGS register.
7. The fast interrupt status bit in FLAGS is cleared automatically.
Relationship to Interrupt Pending Bit Types
As described previously, there are two types of interrupt pending bits: One is the type that is automatically
cleared by hardware after the interrupt service routine is acknowledged and executed, and the other is the one
that must be cleared by the application program's interrupt service routine. You can select fast interrupt
processing for interrupts with either type of pending condition clear function — by hardware or by software.
Programming Guidelines
Remember that the only way to enable/disable a fast interrupt is to set/clear the fast interrupt enable bit in the
SYM register, SYM.1. Executing an EI or DI instruction globally enables or disables all interrupt processing,
except fast interrupts. If you use fast interrupts, remember to load the IP with a new start address when the fast
interrupt service routine ends.
KS88C0416/P0416/C0424/P0424 CLOCK CIRCUITS
7-1
7CLOCK CIRCUITS
OVERVIEW
The clock frequency generated for the KS88C0416/C0424 by an external crystal, or supplied by an external clock
source, can range from 1 MHz to 8 MHz. The maximum CPU clock frequency, as determined by CLKCON
register settings, is 8 MHz. The XIN and XOUT pins connect the external oscillator or clock source to the on-chip
clock circuit.
SYSTEM CLOCK CIRCUIT
The system clock circuit has the following components:
—External crystal or ceramic resonator oscillation source (or an external clock)
—Oscillator stop and wake-up functions
—Programmable frequency divider for the CPU clock (fOSC divided by 1, 2, 8, or 16)
—Clock circuit control register, CLKCON
XIN
XOUT
KS88C0416
KS88C0424
C1
C2
Figure 7-1. Main Oscillator Circuit
(External Crystal or Ceramic Resonator)
XIN
XOUT
KS88C0416
KS88C0424
EXTERNAL
CLOCK
OPEN PIN
Figure 7-2. External Clock Circuit
CLOCK CIRCUITSKS88C0416/P0416/C0424/P0424
7-2
CLOCK STATUS DURING POWER-DOWN MODES
The two power-down modes, Stop mode and Idle mode, affect the system clock as follows:
—In Stop mode, the main oscillator is halted. Stop mode is released and the oscillator is started, by a reset
operation, by an external interrupt with RC-delay filter, or by execution of SED and R circuit. To enter the
Stop mode, STOPCON (STOP Control register) has to be loaded with the value, #0A5H before an STOP
instruction execution. After recovering from the Stop mode by a reset or an interrupt, STOPCON register is
automatically cleared.
—In Idle mode, the internal clock signal is gated away from the CPU, but continues to be supplied to the
interrupt structure, timer 0, and counter A. Idle mode is released by a reset or by an interrupt (externally or
internally generated).
NOISE
FILTER
INT Pin (1)
Oscillator
Wake-up 1/16
M
U
X
CLKCON.3, .4
CPU CLOCK
M
U
X
CLKCON.0–.2
3-Bit Signature Code (2)
1/2
1/8
MAIN
OSC
STOP
Instruction
Oscillator
Stop
NOTES:
1. An external interrupt with an RC-delay noise filter (for the KS88C0416/C0424,
INT0) is fixed to release Stop mode and "wake up" the main oscillator.
Because the KS88C0416/C0424 have no subsystem clock, the 3-bit
CLKCON signature code (CLKCON.2–CLKCON.0) has no meaning.
2.
STOPCON
Figure 7-3. System Clock Circuit Diagram
KS88C0416/P0416/C0424/P0424 CLOCK CIRCUITS
7-3
SYSTEM CLOCK CONTROL REGISTER (CLKCON)
The system clock control register, CLKCON, is located in set 1, address D4H. It is read/write addressable and
has the following functions:
—Oscillator frequency divide-by value
—System clock signal selection
CLKCON register settings control whether or not an external interrupt can be used to trigger a Stop mode release
(This is called the "IRQ wake-up" function). The IRQ wake-up enable bit is CLKCON.7. In the
KS88C0416/C0424, this bit is no longer valid. In reality, bits 7, 6, 5, 2, 1, and 0 have no significance in the
KS88C0416/C0424.
After a reset, the external interrupt oscillator wake-up function is enabled, the main oscillator is activated, and the
fOSC/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU
clock speed to fOSC, fOSC/2, or fOSC/8.
MSB LSB.7 .6 .5 .4 .3 .2 .1 .0
SYSTEM CLOCK CONTROL REGISTER (CLKCON)
D4H, Set 1, R/W
Divide-by selection bits for
CPU clock frequency:
00 = fOSC/16
01 = fOSC/8
10 = fOSC/2
11 = fOSC (non-divided)
Not used for the KS88C0416/C0424 Not used for the KS88C0416/C0424
Figure 7-4. System Clock Control Register (CLKCON)
CLOCK CIRCUITSKS88C0416/P0416/C0424/P0424
7-4
NOTES
KS88C0416/P0416/C0424/P0424 RESET and POWER-DOWN
8-1
8RESET and POWER-DOWN
SYSTEM RESET
OVERVIEW
The reset pin supplies two operating modes: back-up mode input, and system reset input. Back-up mode input
automatically creates a chip stop state when the reset pin is set to a low level. When the reset pin is at a high
state, the rising edge detector becomes activated, the reset pulse generator makes a pulse, system reset occurs
and system operation starts.
System reset has three different sources: the rising edge signal of the external reset input pin, BT overflow for
the watch-dog timer, and the internal POR circuit. The internal POR is operated during powering-up stage.
Internal POR can detect the power-up condition through the internal schmitt trigger input, resistor and capacitor
circuit, but it cannot detect the low non-operating voltage range. Therefore, it is true that the internal POR circuit
sometimes can not generate the reset signal. Another reset source, the Watch-Dog Timer (WDT) is very useful
in this situation. Please refer to Chapter 10, "Basic Timer and Timer 0," for more information.
BACK-UP MODE
SYSTEM RESET
RESET/
BACK-UP
MODE
NOISE
FILTER
Rising Edge
Detector Reset Pulse
Generator
VDD
POR
fOSC BT(WDT)
Figure 8-1. Reset Block Diagram
RESET and POWER-DOWN KS88C0416/P0416/C0424/P0424
8-2
POWER-ON RESET(POR)
The power-on reset circuit is built on the KS88C0416/C0424 product. During a power-on reset, the voltage at
VDD goes to High level and the schmitt trigger input of POR circuit is forced to Low level and then to High level.
The power-on reset circuit makes a reset signal whenever the power supply voltage is powering-up and the
schmitt trigger input senses the Low level. This on-chip POR circuit consists of an internal resistor, an internal
capacitor, and a schmitt trigger input transistor. A resistor and capacitor circuit works as a delay circuit and
makes a Va signal (Schmitt trigger input signal) according to VDD changing. When the power is rising-up, the
schmitt trigger input can detect the low level of Va caused by the R-C delay circuit. After a few mili-seconds, Va
level rises to the Vdd level and the schmitt input can also detect the VIH level. That is, when powering-up, the
schmitt trigger input detects a low level and a high level in turn. The duration between VIL and VIH is equal to a
reset pulse time. For more information, please see the following examples.
Examples
1. When the power supply level is changed to VDD = 3.3 V from VDD = 2 V,
VIL ≤≤ 0.4 VDD. VIH ≥≥ 0.85 VDD, therefore VIL ≤ 0.4 x 3.3 V, VIL ≤ 1.32 V. 2 V is larger than VIL (1.32 V).
So, POR circuit can not detect the low level, and does not make a system reset.
2. When the power supply level is changed to VDD = 3.3 V from VDD = 1.3 V,
VIL ≤≤ 0.4 VDD. VIH ≥≥ 0.85 VDD, therefore VIL ≤ 0.4 x 3.3V, VIL ≤ 1.32 V. 1.3 V is smaller than VIL (1.32 V).
So, POR circuit can detect the low level, and, make a reset signal.
3. When the power supply level is changed to VDD = 3.0 V from VDD = 2 V,
VIL ≤≤ 0.4 VDD. VIH ≥≥ 0.85 VDD, therefore VIL ≤ 0.4 x 3.0 V, VIL ≤ 1. 2 V. 2 V is larger than VIL (1.2 V).
So, POR circuit can not detect the low level, and does not make a system reset.
4. When the power supply level is changed to VDD = 3.0 V from VDD = 1.3 V,
VIL ≤≤ 0.4 VDD. VIH ≥≥ 0.85 VDD, therefore VIL ≤ 0.4 x 3.0 V, VIL ≤ 1.2 V. 1.3 V is larger than VIL (1.32 V).
So, POR circuit can not detect the low level, and does not make a system reset.
R
VDD
VSS
SYSTEM RESET
Va
CSchmitt Trigger Inverter
R: On-chip resistor
C: On-chip capacitor
Figure 8-2. Power-On Reset Circuit
KS88C0416/P0416/C0424/P0424 RESET and POWER-DOWN
8-3
Va
VDD
Reset Pulse Width
Reset Pulse
Time
Voltage (V)
VDD
If Va voltage is under 0.4 V , Reset fulse signal is generated.
If Va voltage is over 0.4 V , Reset fulse signal is not generated.
DD
DD
(VDD Rising Time)
VIH = 0.85 VDD
VIL = 0.4 VDD
TVDD
Figure 8-3. Timing Diagram for Power-On Reset Circuit
EXTERNAL RESET
An external reset occurs whenever the reset pin makes a rising edge signal, which takes place when the reset pin
switches to High level from Low level. Even though the chip has a built-in POR circuit, an external Resistor-
Capacitor circuit can do a reset while the power is on. An improvement in functions of the external POR circuit
depends on the quality of the external circuit to be added. The chip can also be operated without an additional
circuit to the reset pin. In that case, the reset pin should be connected to the VDD level. In practice, the external
reset pin is connected to both system reset and back-up mode input. For further information on back-up mode,
please refer to the Power-down mode in the next page. To reset the system by using an external reset, the input
level of the reset pin should be lower than VIL, and you should hold the low level long enough to pass the noise
filter, and by then the input level of reset pin should rise higher than VIH. A system reset pulse is generated by
the reset pulse generator, if the sequence above is carried out satisfactorily.
WATCH-DOG TIMER RESET
The KS88C0416/C0424 contain a watch-dog timer that can recover normal operation from malfunction. A watch-
dog timer generates a system reset signal if the BT-Basic Counter is not cleared by the program within a
specification. System reset helps return to the normal operation of a chip. For more information on the watch-dog
timer function, please refer to Chapter 10, "Basic Timer and Timer 0."
RESET and POWER-DOWN KS88C0416/P0416/C0424/P0424
8-4
SYSTEM RESET OPERATION
System reset starts the oscillation circuit, synchronizes a chip operation with the CPU clock, and initializes the
internal CPU and peripheral modules. This procedure brings the KS88C0416/C0424 into the normal operating
status. To allow some time for the internal CPU clock oscillation to stabilize, the reset pulse generator must be
held to an active level for a minimum time interval after the power supply comes within tolerance. The minimum
reset operation time required for oscillation stabilization is 16 oscillation clocks. All system and peripheral control
registers are then reset to their default hardware values (see Table 8-1).
In summary, the following sequence of events occurs during a reset operation:
—All interrupts are disabled.
—The watchdog function (basic timer) is enabled.
—Ports 0, 1, 2, and 3 are set to input mode and all pull-up resistors are disabled for the I/O port pin circuits.
—Peripheral control and data register settings are disabled and reset to their default hardware values (see
Table 8-1).
—The program counter (PC) is loaded with the program reset address in the ROM, 0100H.
—When the programmed oscillation stabilization time interval has elapsed, the instruction stored in the ROM
location 0100H (and 0101H) is fetched and executed.
NOTE
To program the duration of the oscillation stabilization interval, you should make the appropriate settings
to the basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use
the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs),
you can disable it by writing "1010B" to the upper nibble of BTCON. But it is recommended to use it to
prevent a chip malfunction.
KS88C0416/P0416/C0424/P0424 RESET and POWER-DOWN
8-5
HARDWARE RESET VALUES
Table 8-1 lists the reset values for CPU and system registers, peripheral control registers, and peripheral data
registers after a reset operation. The following notations are used to represent reset values:
—A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively.
—An "x" means that the bit value is undefined after a reset.
—A dash ("–") means that the bit is either "not used" or "not mapped" (but a "0" is read from the bit position)
Table 8-1. Set 1 Register Values After Reset
Register Name Mnemonic Address Bit Values After Reset
Dec Hex 76543210
Timer 0 counter (read-only) T0CNT 208 D0H 00000000
Timer 0 data register T0DATA 209 D1H 11111111
Timer 0 control register T0CON 210 D2H 00000000
Basic timer control register BTCON 211 D3H 00000000
Clock control register CLKCON 212 D4H –––00000
System flags register FLAGS 213 D5H xxxxxx0 0
Register pointer 0 RP0 214 D6H 11000–− −
Register pointer 1 RP1 215 D7H 11001−−−
Location D8H (SPH) is not mapped.
Stack pointer (low byte) SPL 217 D9H xxxxxxxx
Instruction pointer (high byte) IPH 218 DAH xxxxxxxx
Instruction pointer (low byte) IPL 219 DBH xxxxxxxx
Interrupt request register (read-only) IRQ 220 DCH 00000000
Interrupt mask register IMR 221 DDH xxxx––x x
System mode register SYM 222 DEH 0−−xxx0 0
Register page pointer PP 223 DFH 00000000
Port 0 data register P0 224 E0H 00000000
Port 1 data register P1 225 E1H 00000000
Port 2 data register P2 226 E2H 00000000
Port 3 data register P3 227 E3H −−0−−−0 0
Location E4H is not mapped.
Port 2 interrupt enable register P2INT 229 E5H −−−−0000
Port 2 interrupt pending register P2PND 230 E6H −−−−0000
Port 0 pull-up enable register P0PUR 231 E7H 00000000
Port 0 control register (high byte) P0CONH 232 E8H 00000000
Port 0 control register (low byte) P0CONL 233 E9H 00000000
RESET and POWER-DOWN KS88C0416/P0416/C0424/P0424
8-6
Table 8-1. Set 1 Register Values After Reset (Continued)
Register Name Mnemonic Address Bit Values After Reset
Dec Hex 76543210
Port 1 control register (high byte) P1CONH 234 EAH00000000
Port 1 control register (low byte) P1CONL 235 EBH00000000
Port 1 pull-up enable register P1PUR 236 ECH 00000000
Port 2 pull-up enable register P2PUR 237 EDH 00000000
Port 2 control register (high byte) P2CONH 238 EEH 00000000
Port 2 control register (low byte) P2CONL 239 EFH 00000000
Port 3 control register P3CON 240 F0H ––000000
Port 0 interrupt enable register P0INT 241 F1H 00000000
Port 0 interrupt pending register P0PND 242 F2H 00000000
Counter A control register CACON 243 F3H 00000000
Counter A data register (high byte) CADATAH 244 F4H 11111111
Counter A data register (low byte) CADATAL 245 F5H 11111111
Timer 1 counter register (high byte) T1CNTH 246 F6H 00000000
Timer 1 counter register (low byte) T1CNTL 247 F7H 00000000
Timer 1 data register (high byte) T1DATAH 248 F8H 11111111
Timer 1 data register (low byte) T1DATAL 249 F9H 11111111
Timer 1 control register T1CON 250 FAH 00000000
Stop control register STOPCON 251 FBH 00000000
Locations FCH is not mapped.
Basic timer counter BTCNT 253 FDH xxxxxxxx
External memory timing register EMT 254 FEH 0111110–
Interrupt priority register IPR 255 FFH xxxxxxxx
NOTES:
1. Although the SYM register is not used for the KS88C0416/C0424, SYM.5 should always be “0”. If you accidentally
write a "1" to this bit during the normal operation, a system malfunction may occur.
2. Except for T0CNT, IRQ, T1CNTH, T1CNTL, and BTCNT, which are read-only, all registers in set 1 are read/write
addressable.
3. You cannot use a read-only register as a destination field for the instructions OR, AND, LD, and LDB.
4. Interrupt pending flags are noted by shaded table cells.
KS88C0416/P0416/C0424/P0424 RESET and POWER-DOWN
8-7
POWER-DOWN MODES
BACK-UP MODE
An external reset pin can be used as both a Back-up mode input and an external reset input. When the external
reset pin is at a low state, the chip is changed to back-up mode, in which the CPU and peripheral operations are
stopped due to the oscillation stop. In back-up mode, the chip cannot released the stop state by any interrupt.
The stop mode can be released by a reset operation which is done by pulling-up the reset pin to VDD power
supply level - or VIH, a reset pin input high level. when reset pin is pulled below low input voltage level (VIL), the
chip returns to stop mode or back-up mode. The chip will remain in back-up mode as long as logic zero remains
on the reset pin. When logic one is applied to the reset pin, a reset operation occurs and releases back-up mode.
This feature is very useful in remote control applications with a low voltage detect circuit connected to the reset
pin. When the voltage detect circuit senses low power supply voltage, it pulls down the reset pin and activates
back-up mode to minimize the current consumption. The chip can keep the internal data for a long time. When a
new power supply is employed, the chip starts from the reset status.
BACK-UP MODE
SYSTEM RESET
RESET/
BACK-UP
MODE
NOISE
FILTER
Rising Edge
Detector Reset Pulse
Generator
Figure 8-4. Block Diagram for Back-Up Mode
RESET and POWER-DOWN KS88C0416/P0416/C0424/P0424
8-8
Reset Input
VIH = 0.85
VDD
Reset Pulse Width
(16 clock)
Back-Up ModeLow Voltage Detect
(Ex: 1.8 V)
Reset Pulse
Time
Voltage (V)
VDD
If reset pin is under 0.4 V , back-up mode is activated.
If reset pin is changed to over 0.85 V from a low level. reset pulse is generated.
DD DD
(Reset < 0.4 VDD)
(rising edge detect)
VDD)
Figure 8-5. Timing Diagram for Back-Up Mode and External Reset
STOP MODE
Stop mode is invoked by the stop control register (STOPCON) setting and the STOP instruction. Another Stop
source is the back-up mode invoked by forcing the reset pin the Low state. In Stop mode, the operation of the
CPU and all peripherals is halted. That is, the on-chip main oscillator stops and the current supply is reduced to
less than 1 µA. All system functions stop when the clock "freezes," but the data stored in the internal register file
is retained. Stop mode can be released in one of the following two ways: by a system reset or by an external
interrupt.
After releasing from STOP mode, the value of the stop control register (STOPCON) is cleared automatically.
KS88C0416/P0416/C0424/P0424 RESET and POWER-DOWN
8-9
++ PROGRAMMING TIP — To enter STOP mode.
This example shows how to enter the stop mode.
ORG 0000H ;Reset address
•
•
•
JP T,START
ENTER_STOP:
LD STOPCON,#0A5H
STOP
NOP
NOP
NOP
RET
ORG 0100H-3
JP T,START
ORG 0100H ;Reset address
START LD BTCON,#03 ;Clear basic timer counter.
•
•
•
MAIN NOP
•
•
•
CALL ENTER_STOP ;Enter the STOP mode
•
•
•
LD BTCON,#02H ;Clear basic timer counter.
JP T,MAIN
•
•
•
RESET and POWER-DOWN KS88C0416/P0416/C0424/P0424
8-10
Using RESET to Release Stop Mode
Stop mode is released when the reset signal goes active (Low level to High level): all system and peripheral
control registers are reset to their default hardware values and the contents of all data registers are retained.
When the programmed oscillation stabilization interval has elapsed, the CPU starts the system initialization
routine by fetching the program instruction stored in the ROM location 0100H.
Using an External Interrupt to Release Stop Mode
External interrupts with an RC-delay noise filter circuit can be used to release Stop mode. For the
KS88C0416/C0424 microcontroller, we recommend using the INT0–INT8 interrupt at P0 and P2.0–P2.3.
Please note the following conditions for Stop mode release:
—If you release Stop mode using an external interrupt, the current values in the system and peripheral control
registers are unchanged.
—If you use an external interrupt for Stop mode release, you can also program the duration of the oscillation
stabilization interval. To do this, you must make the appropriate control and clock settings before entering
Stop mode.
—If you use an interrupt to release Stop mode, the bit-pair setting for CLKCON.4/CLKCON.3 remains
unchanged and the currently selected clock value is used.
The external interrupt is serviced when a Stop mode release occurs. Following the IRET from the service routine,
the instruction immediately following the one that initiated Stop mode is executed.
Using a SED and R (Stop Error Detect and Recovery) to Release Stop Mode
The Stop Error Detect and Recovery circuit can be used to release stop mode and prevent abnormal status -
stop mode that can occur by battery bouncing. It executes two functions in relation to the internal logic of P0 and
P1:
Releasing from stop mode
The moment the level of the input port (P0 or P1) is switched, the chip is released from stop mode even though
an external interrupt is disabled.
Preventing the chip from entering stop mode in abnormal status
This circuit detects abnormal status by checking the port (P0 and P1) status. If the chip is in abnormal status, the
circuit prevents the chip from entering stop mode.
NOTE
Do not use stop mode if you are using an external clock source XIN input must be cleared internally for
VSS to reduce the current leakage.
KS88C0416/P0416/C0424/P0424 RESET and POWER-DOWN
8-11
IDLE MODE
Idle mode is invoked by the instruction IDLE (opcode 6FH). In Idle mode, CPU operations are halted while some
peripherals remain active. During Idle mode, the internal clock signal is gated away from the CPU and from all
but the following peripherals, which remain active:
—Interrupt logic
—Timer 0
—Timer 1
—Counter A
I/O port pins retain the mode (input or output) they had at the time Idle mode was entered.
Idle Mode Release
You can release Idle mode in one of the following two ways:
1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents
of all data registers are retained. The reset automatically selects the slowest clock (1/16) because of the
hardware reset value for the CLKCON register. If all external interrupts are masked in the IMR register, a
reset is the only way you can release Idle mode.
2. Activate any enabled interrupt, internal or external. When you use an interrupt to release Idle mode, the 2-bit
CLKCON.4/CLKCON.3 value remains unchanged, and the currently selected clock value is used. The
interrupt is then serviced. When the return-from-interrupt condition (IRET) occurs, the instruction
immediately following the one which initiated Idle mode is executed.
NOTE
Only external interrupts with an RC delay built in to the pin circuit can be used to release Stop mode. To
release Idle mode, you can use either an external interrupt or an internally-generated interrupt.
RESET and POWER-DOWN KS88C0416/P0416/C0424/P0424
8-12
RECOMMENDATION FOR UNUSUED PINS
To reduce overall power consumption, please configure unused pins according to the guideline description Table
8-2.
Table 8-2. Guideline for Unused Pins to Reduced Power Consumption
Pin Name Recommend Example
Port 0 Set Input mode
Enable Pull-up Resister
No Connection for Pins
P0CONH ← # 00H or 01H
P0CONL ← # 00H or 01H
P0PUR ← # 0FFH
Port 1 Set Open-Drain Output mode
Set P1 Data Register to #00H.
Disable Pull-up Resister
No Connection for Pins
P1CONH ← # 55H
P1CONL ← # 55H
P1 ← # 00H
P1PUR ← # 00H
Port 2 Set Push-pull Output mode
Set P2 Data Register to #00H.
Disable Pull-up resister
No Connection for Pins
P2CONH ← # 0AAH
P2CONL ← # 0AAH
P2 ← # 00H
P2PUR ← # 00H
Port 3 Set Push-pull Output mode
Disable Pull-up Resister
Set P3 Data Register to #00H.
No Connection for Pins
P3CON ← # 21H
P3 ← # 00H
TEST Connect to VSS.–
KS88C0416/P0416/C0424/P0424 RESET and POWER-DOWN
8-13
SUMMARY TABLE OF BACK-UP MODE, STOP MODE, AND RESET STATUS
For further understanding, please see the description Table 8-3 below.
Table 8-3. Summary of each mode
Item/Mode Back-up Reset status Stop
Approach
Condition External reset pin is in low
level External reset pin is on rising
edge. POR circuit is activated.
WDT overflow signal is
activated.
STOPCON ← # A5H
STOP
( LD STOPCON,#0A5H STOP)
PORT
Status All ports are floating status. All
ports enter input mode but are
blocked. All port data registers
set to #00H. Disable all pull-
up resistor
All ports are input mode, and
not blocked.
All port data registers set to
#00H. Disable all pull-up
resistor
All ports are keep in the previous
status.
Input port data is not changed.
Control
Register All control registers and
system registers are initialized
as Table 8-1
All control registers and
system registers are initialized
as Table 8-1.
–
Releasing
Condition External reset pin transition
(Rising edge) After passing an oscillation
warming-up time Interrupt, or reset SED and R
circuit.
Others There is no current
consumption in the chip. There can be input leakage
current in chip. It depends on control program
RESET and POWER-DOWN KS88C0416/P0416/C0424/P0424
8-14
NOTES
KS88C0416/P0416/C0424/P0424 I/O PORTS
9-1
9I/O PORTS
OVERVIEW
The KS88C0416/C0424 microcontrollers have four bit-programmable I/O ports, P0–P3. Three ports, P0–P2, are
8-bit ports and P3 is a 2-bit port. This gives a total of 26 I/O pins. Each port is bit-programmable and can be
flexibly configured to meet application design requirements. The CPU accesses ports by directly writing or
reading port registers. No special I/O instructions are required.
For IR universal remote controller applications, ports 0, 1, and 2 are usually configured to the keyboard matrix
and port 3 is used to transmit the remote controller carrier signal or to indicate operating status by turning on a
LED.
Table 9-1 gives you a general overview of the KS88C0416/C0424 I/O port functions.
Table 9-1. KS88C0416/C0424 Port Configuration Overview
Port Configuration Options
08-bit general-purpose I/O port; Input or push-pull output; external interrupt input on falling
edges, rising edges, or both edges; all P0 pin circuits have noise filters and interrupt
enable/disable (P0INT) and pending control (P0PND); Pull-up resistors can be assigned to
individual P0 pins using P0PUR register settings. This port is dedicated for key input in remote
controller application.
18-bit general-purpose I/O port; Input, open-drain output, or push-pull output. Pull-up resistors
can be assigned to individual P1 pins using P1PUR register settings. This port is dedicated for
key output in remote controller application.
28-bit general-purpose I/O port; Input, open-drain output, or push-pull output. The low-byte P2
pins, P2.3–P2.0, can be used as external interrupt inputs and have noise filters. The P2INT
register (low-byte) is used to enable/disable interrupts and P2PND bits can be polled by
software for interrupt pending control. Pull-up resistors can be assigned to individual P2 pins
using P2PUR register settings.
32-bit I/O port; P3.0 and P3.1 are configured together using a 4-bit data value to support input
functions (Input mode, with or without pull-up, for T0CK, T0CAP, or T1CAP) or output functions
(push-pull or open-drain output mode, or open-drain with pull-up, for REM and T0PWM). Port 3
pins have high current drive capability to support LED applications. The port 3 data register
contains three status bits: two for P3.0 and P3.1 and one for carrier signal on/off status.
I/O PORTS KS88C0416/P0416/C0424/P0424
9-2
PORT DATA REGISTERS
Table 9-2 gives you an overview of the register locations of all four KS88C0416/C0424 I/O port data registers.
Data registers for ports 0, 1, and 2 have the general format shown in Figure 9-1.
NOTE
The data register for port 3, P3, contains two bits for P3.0 and P3.1, and an additional status bit for
carrier signal on/off.
Table 9-2. Port Data Register Summary
Register Name Mnemonic Decimal Hex Location R/W
Port 0 data register P0 224 E0H Set 1 R/W
Port 1 data register P1 225 E1H Set 1 R/W
Port 2 data register P2 226 E2H Set 1 R/W
Port 3 data register P3 227 E3H Set 1 R/W
Because port 3 is a 2-bit I/O port, the port 3 data register only contains values for P3.0 and P3.1. The P3 register
also contains values for P3.0 and P3.1. The P3 register also contains a special carrier on/off bit (P3.5). See the
port 3 description for details. All other KS88C0416/C0424 I/O ports are 8-bit.
I/O Port Data Register Format (n = 0-3)
MSB LSB.7 .6 .5 .4 .3 .2 .1 .0
Pn.7 Pn.6 Pn.5 Pn.4 Pn.3 Pn.2 Pn.1 Pn.0
NOTE: Because port 3 is a 2-bit I/O port, the port 3 data register
only contains values for P3.0 and P3.1.
The P3 register also contains a special carrier on/off bit (P3.5).
See the port 3 description for details. All other KS88C0416/C0424
I/O ports are 8-bit.
Figure 9-1. KS88C0416/C0424 I/O Port Data Register Format
KS88C0416/P0416/C0424/P0424 I/O PORTS
9-3
PULL-UP RESISTOR ENABLE REGISTERS
You can assign pull-up resistors to the pin circuits of individual pins in ports 0, 1, and 2. To do this, you should
make the appropriate settings to the corresponding pull-up resistor enable registers — P0PUR, P1PUR, and
P2PUR. These registers are located in set 1 at locations E7H, ECH, and EDH, respectively, and are read/write
accessible using Register addressing mode.
You can assign a pull-up to the port 3 pins, P3.0 and P3.1, in Input mode (T0CK/T0CAP/T1CAP) or in output
mode (REM/T0_PWM) using basic port configuration setting in the P3CON register.
NOTE:Pull-up resistors can be assigned to the port 3 pins,
P3.0 and P3.1, by making the appropriate setting to
the port 3 control register, P3CON.
MSB LSB.7 .6 .5 .4 .3 .2 .1 .0
Pull-Up Resistor Enable Registers (PnPUR, where n = 0–2)
Set 1, (E7H, ECH, EDH), R/W
Pn.7 Pn.6 Pn.5 Pn.4 Pn.3 Pn.2 Pn.1 Pn.0
Pull-up resistor enable bit:
0 = Disable pull-up resistor
1 = Enable pull-up resistor
Figure 9-2. Pull-Up Resistor Enable Registers (Ports 0, 1, and 2 only)
I/O PORTS KS88C0416/P0416/C0424/P0424
9-4
PORT 0
Port 0 is a general-purpose, 8-bit I/O port. It is bit-programmable. Port 0 pins are accessed directly by read/write
operations to the port 0 data register, P0 (set 1, E0H). The P0 pin circuits support pull-up resistor assignment
using P0PUR register settings and all pins have noise filters for external interrupt inputs.
Two 8-bit control registers are used to configure port 0 pins: P0CONH (set 1, E8H) for the upper nibble pins,
P0.7–P0.4, and P0CONL (set 1, E9H) for lower nibble pins, P0.3–P0.0. Each control register byte contains four
bit-pairs and each bit-pair configures one pin (see Figures 9-3 and 9-4). A hardware reset clears all P0 control
and data registers to "00H".
A separate register, the port 0 interrupt control register, P0INT (set 1, F1H), is used to enable and disable
external interrupt input. You can poll the port 0 interrupt pending register, P0PND, to detect and clear pending
conditions for these interrupts.
The lower-nibble pins, P0.3–P0.0, are used for INT3–INT0 input (IRQ6), respectively. The upper nibble pins,
P0.7–P0.4, are all used for INT4 input (IRQ7). Interrupts that are detected at any of these four pins are processed
using the same vector address (E8H).
PORT 0 CONTROL REGISTER, HITGH BYTE (P0CONH)
E8H, Set 1, R/W
MSB LSB.7 .6 .5 .4 .3 .2 .1 .0
P0.7/INT4 P0.6/INT4 P0.5/INT4 P0.4/INT4
P0CONH Pin Configuration Settings:
00
01
10
11
Input mode; interrupt on falling edges
Input mode; interrupt on rising and falling edges
Push-pull output mode
Input mode; interrupt on rising edges
Figure 9-3. Port 0 High-Byte Control Register (P0CONH)
KS88C0416/P0416/C0424/P0424 I/O PORTS
9-5
PORT 0 CONTROL REGISTER, LOW BYTE (P0CONL)
E9H, Set 1, R/W
MSB LSB.7 .6 .5 .4 .3 .2 .1 .0
P0.3/INT3 P0.2/INT2 P0.1/INT1 P0.0/INT0
P0CONL Pin Configuration Settings:
00
01
10
11
Input mode; interrupt on falling edges
Input mode; interrupt on rising and falling edges
Push-pull output mode
Input mode; interrupt on rising edges
Figure 9-4. Port 0 Low-Byte Control Register (P0CONL)
PORT 0 INTERRUPT ENABLE REGISTER (P0INT)
The port 0 interrupt control register, P0INT, is used to enable and disable external interrupt input at individual P0
pins (see Figure 9-5). To enable a specific external interrupt, you should set its P0INT.n bit to “1”. You must also
be sure to make the correct settings in the corresponding port 0 control register (P0CONH, P0CONL).
PORT 0 INTERRUPT PENDING REGISTER (P0PND)
The port 0 interrupt pending register, P0PND, contains pending bits (flags) for each port 0 interrupt (see Figure
9-6). When a P0 external interrupt is acknowledged by the CPU, the service routine must clear the pending
condition by writing a “0” to the appropriate pending flag in the P0PND register (Writing a “1” to the pending bit
has no effect).
NOTE
A hardware reset clears the P0INT and P0PND registers to "00H". For this reason, the application
program’s initialization routine must enable the required external interrupts for port 0, and for the other
I/O ports.
I/O PORTS KS88C0416/P0416/C0424/P0424
9-6
PORT 0 INTERRUPT REGISTER (P0INT)
F1H, Set 1, R/W
MSB LSB.7 .6 .5 .4 .3 .2 .1 .0
Port 0 Interrupt Enable Bits:
0 = Disable interrupt
1 = Enable interrupt
P0.7/INT4
P0.6/INT4
P0.5/INT4
P0.4/INT4
P0.3/INT3
P0.2/INT2
P0.1/INT1
P0.0/INT0
Figure 9-5. Port 0 External Interrupt Control Register (P0INT)
PORT 0 INTERRUPT PENDING REGISTER (P0PND)
F2H, Set 1, R/W
MSB LSB.7 .6 .5 .4 .3 .2 .1 .0
P0.7/INT4
P0.6/INT4
P0.5/INT4
P0.4/INT4
P0.3/INT3
P0.2/INT2
P0.1/INT1
P0.0/INT0
Port 0 Interrupt Pending Bits:
Interrupt not pending
Clear P0.n pending condition (when write)
P0.n interrupt is pending
No effect (when write)
0
0
1
1
Figure 9-6. Port 0 External Interrupt Pending Register (P0PND)
KS88C0416/P0416/C0424/P0424 I/O PORTS
9-7
PORT 1
Port 1 is a bit-programmable 8-bit I/O port. Port 1 pins are accessed directly by read/write operations to the port 1
data register, P1 (set 1, E1H).
To configure port 1, the initialization routine writes the appropriate values to the two port 1 control registers:
P1CONH (set 1, EAH) for the upper nibble pins, P1.7–P1.4, and P1CONL (set 1, EBH) for the lower nibble pins,
P1.3–P1.0. Each 8-bit control register contains four bit-pairs and each 2-bit value configures one port pin (see
Figures 9-7 and 9-8).
After a hardware reset, the port 1 control registers are cleared to "00H", configuring port 0 initially to Input mode.
To assign pull-up resistors to P1 pins, you should make the appropriate settings to the port 1 pull-up resistor
enable register, P1PUR.
PORT 1 CONTROL REGISTER, HITGH BYTE (P1CONH)
EAH, Set 1, R/W
MSB LSB.7 .6 .5 .4 .3 .2 .1 .0
P1.7 P1.6 P1.5 P1.4
P1CONH Pin Configuration Settings:
00
01
10
11
Input mode
Open-drain output mode
Push-pull output mode
Invalid setting
Figure 9-7. Port 1 High-Byte Control Register (P1CONH)
I/O PORTS KS88C0416/P0416/C0424/P0424
9-8
PORT 1 CONTROL REGISTER, LOW BYTE (P1CONL)
EBH, Set 1, R/W
MSB LSB.7 .6 .5 .4 .3 .2 .1 .0
P1.3 P1.2 P1.1 P1.0
P1CONH Pin Configuration Settings:
00
01
10
11
Input mode
Open-drain output mode
Push-pull output mode
Invalid setting
Figure 9-8. Port 1 Low-Byte Control Register (P1CONL)
KS88C0416/P0416/C0424/P0424 I/O PORTS
9-9
PORT 2
Port 2 is a bit-programmable 8-bit I/O port. Port 2 pins are accessed directly by read/write operations to the port 2
data register, P2 (set 1, E2H). You can configure port 2 pins individually to Input mode, open-drain output mode,
or push-pull output mode.
The low-byte P2 pins, P2.3–P2.0, can also be used as external interrupt inputs and have noise filters. P2INT
register lower nibble settings are used to enable/disable the INT8–INT5 interrupts, and the corresponding lower
nibble P2PND bits can be polled by software for interrupt pending control.
To configure port 2, the initialization routine writes the appropriate values to the two port 2 control registers:
P2CONH (set 1, EEH) for the upper nibble pins, P2.7–P2.4, and P2CONL (set 1, EFH) for the lower nibble pins,
P2.3–P2.0. Each 8-bit control register contains four bit-pairs and each 2-bit value configures one port pin (see
Figures 9-9 and 9-10).
To assign pull-up resistors to P2 pins, you should make the appropriate settings to the port 2 pull-up resistor
enable register, P2PUR.
After a hardware reset, the P2CONH and P2CONL registers are cleared to "00H". This initially configures all port
2 pins to input mode.
PORT 2 CONTROL REGISTER, HITGH BYTE (P2CONH)
EEH, Set 1, R/W
MSB LSB.7 .6 .5 .4 .3 .2 .1 .0
P2.7 P2.6 P2.5 P2.4
P2CONH Pin Configuration Settings:
00 Input mode
01 Open-drain output mode
10 Push-pull output mode
11 Invalid setting
Figure 9-9. Port 2 High-Byte Control Register (P2CONH)
I/O PORTS KS88C0416/P0416/C0424/P0424
9-10
PORT 2 CONTROL REGISTER, LOW BYTE (P2CONL)
EFH, Set 1, R/W
MSB LSB.7 .6 .5 .4 .3 .2 .1 .0
P2.3/INT8 P2.2/INT7 P2.1/INT6 P2.0/INT5
P2CONL Pin Configuration Settings:
00 Input mode; interrupt on falling edge
01 Open-drain output mode
10 Push-pull output mode
11 Input mode; interrupt on rising edge
Figure 9-10. Port 2 Low-Byte Control Register (P2CONL)
PORT 2 INTERRUPT REGISTER (P2INT)
E5H, Set 1, R/W
MSB LSB.7 .6 .5 .4 .3 .2 .1 .0
Port 2 Interrupt Enable Bits:
0 = Disable interrupt
1 = Enable interrupt
Not used for the KS88C0416/C0424
P2.3/INT8
P2.2/INT7
P2.1/INT6
P2.0/INT5
Figure 9-11. Port 2 Interrupt Enable Register (P2INT)
KS88C0416/P0416/C0424/P0424 I/O PORTS
9-11
PORT 2 INTERRUPT PENDING REGISTER (P2PND)
E6H, Set 1, R/W
MSB LSB.7 .6 .5 .4 .3 .2 .1 .0
Port 2 Interrupt Pending Bits:
Not used for the KS88C0416/C0424
P2.3/INT8
P2.2/INT7
P2.1/INT6
P2.0/INT5
Interrupt not pending
Clear P2.n pending condition (when write)
P2.n interrupt is pending
No effect (when write)
0
0
1
1
Figure 9-12. Port 2 Interrupt Pending Register (P2PND)
PORT 3
Port 3 is a bit-programmable 2-bit I/O port. The port 3 pins, P3.0 and P3.1, are accessed directly by read/write
operations to the port 3 data register, P3 (set 1, E3H).
P3.0 and P3.1 are configured by writing 6-bit data value to the port 3 control register, P3CON. You can configure
these pins to support input functions (Input mode, with or without pull-up, for T0CK/T0CAP/T1CAP) or output
functions (push-pull or open-drain output mode, or open-drain with pull-up, for T0 and timer 0 PWM).
Port 3 pins have high current drive capability to support LED applications.
A reset operation clears P3CON to "00H", selecting Input mode (T0CK/T0CAP/T1CAP) as the initial port 3
function.
I/O PORTS KS88C0416/P0416/C0424/P0424
9-12
PORT 3 CONTROL REGISTER (P3CON)
F0H, Set 1, R/W
MSB LSB.7 .6 .5 .4 .3 .2 .1 .0
Alternative function enable bit:
0 = Normal I/O function (P3.1)
1 = REM/T0CK
Configuration bits for pin P3.0
Input mode (P3.1/T0CK, P3.0/T0CAP/T1CAP)
Input, pull-up mode (P3.1/T0CK, P3.0/T0CAP/T1CAP)
Output, push-pull mode (P3.1/REM, P3.0/T0PWM)
Output, open-drain mode (P3.1/REM, P3.0/T0PWM)
Output, open-drain, pull-up mode (P3.1/REM, P3.0/T0PWM)
Port selection
x
x
0
1
1
Alternative function enable bit:
0 = Normal I/O function (P3.0)
1 = T0PWM/T0CAP/T1CAP
Configuration bits for pin P3.1
0
1
0
0
1
0
0
1
1
1
2/7 1/6 0/5
(“x” means ‘don’t care’.)
Figure 9-13. Port 3 Control Register (P3CON)
MSB LSB.7 .6 .5 .4 .3 .2 .1 .0
PORT 3 DATA REGISTER (P3)
E3H, Set 1, R/W
Not used for the
KS88C0416/C0424
Carrier on/off for
remote controller
P3.0/T0_PWM/
T0CAP/T1CAP
P3.1/REM/TOCK
Not used for the
KS88C0416/C0424
Figure 9-14. Port 3 Data Register (P3)
KS88C0416/P0416/C0424/P0424 I/O PORTS
9-13
P3.0 AND P3.1 CIRCUITS
The circuit diagram for port 3 pins shown in Chapter 1, “Overview,” (Figure 1-6) is a simplified version and does
not show some details of these circuits which may be useful when designing specific applications using the
KS88C0416/C0424 microcontroller. For this reason, supplemental information about the P3.0 and P3.1 circuits is
provided below in Figures 9-15 and 9-16.
SELECT
PULL-UP RESISTOR
(Typical 21 KΩ)
VDD
P3.1/REM/T0CK
VSS
DATA
PULL-UP ENABLE
OUTPUT DISABLE
VDD
OPEN-DRAIN
P3.1 INPUT
NOISE
FILTER
T0CK
M
U
X
PORT 3.1 DATA
CAOF (CACON.0)
CARRIER ON/OFF (P3.5)
Figure 9-15. P3.1 Circuit Diagram (Supplemental Information)
I/O PORTS KS88C0416/P0416/C0424/P0424
9-14
PULL-UP
RESISTOR
(Typical 21 ΚΩ)
VDD
PULL-UP
ENABLE
OPEN-DRAIN
OUTPUT
DISABLE
P3.0 INPUT
DATA
PORT 3.0 DATA
P3CON.3
T0CAP or
T1CAP
P3.0/T0CAP/
T1CAP/T0PWM
T0_PWM
M
U
X
VDD
VSS
NOISE FILTER
Figure 9-16. P3.0 Circuit Diagram (Supplemental Information)
KS88C0416/P0416/C0424/P0424 BASIC TIMER and TIMER 0
10-1
10 BASIC TIMER and TIMER 0
OVERVIEW
The KS88C0416/C0424 has two default timers: an 8-bit basic timer and an 8-bit general-purpose timer/counter.
The 8-bit timer/counter is called timer 0.
Basic Timer (BT)
You can use the basic timer (BT) in two different ways:
—As a watchdog timer providing an automatic reset mechanism in the event of a system malfunction, or
—To signal the end of the required oscillation stabilization interval after a reset or a Stop mode release.
The functional components of the basic timer block are:
—Clock frequency divider (fOSC divided by 4096, 1024, or 128) with multiplexer
—8-bit basic timer counter, BTCNT (set 1, FDH, read-only)
—Basic timer control register, BTCON (set 1, D3H, read/write)
Timer 0
Timer 0 has three operating modes, one of which you select using the appropriate T0CON setting:
—Interval timer mode
—Capture input mode with a rising or falling edge trigger at the P3.0 pin
—PWM mode
Timer 0 has the following functional components:
—Clock frequency divider (fOSC divided by 4096, 256, or 8 ) with multiplexer
—External clock input pin (P3.1, T0CK)
—8-bit counter (T0CNT), 8-bit comparator, and 8-bit reference data register (T0DATA)
—I/O pins for capture input (P3.0) or match output
—Timer 0 overflow interrupt (IRQ1, vector FAH) and match/capture interrupt (IRQ1, vector FCH) generation
—Timer 0 control register, T0CON (set 1, D2H, read/write)
BASIC TIMER and TIMER 0 KS88C0416/P0416/C0424/P0424
10-2
BASIC TIMER CONTROL REGISTER (BTCON)
The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer
counter and frequency dividers, and to enable or disable the watchdog timer function. It is located in set 1,
address D3H, and is read/write addressable using Register addressing mode.
A reset clears BTCON to "00H". This enables the watchdog function and selects a basic timer clock frequency of
fOSC/4096. To disable the watchdog function, you must write the signature code "1010B" to the basic timer
register control bits BTCON.7–BTCON.4. For improved reliability, we recommend using the Watch-dog timer
function in remote controllers and hand-held product applications.
MSB LSB.7 .6 .5 .4 .3 .2 .1 .0
BASIC TIMER CONTROL REGISTER (BTCON)
D3H, Set 1, R/W
Watchdog function enable bits:
1010B = Disable watchdog timer
Others = Enable watchdog timer
Divider clear bit for basic
timer and timer 0:
0 = No effect
1 = Clear both dividers
Basic timer counter clear bit:
0 = No effect
1 = Clear BTCNT
Basic timer input clock selection bits:
00 = fOSC/4096
01 = fOSC/1024
10 = fOSC/128
11 = Invalid selection
Figure 10-1. Basic Timer Control Register (BTCON)
KS88C0416/P0416/C0424/P0424 BASIC TIMER and TIMER 0
10-3
BASIC TIMER FUNCTION DESCRIPTION
Watchdog Timer Function
You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to
any value other than "1010B". (The "1010B" value disables the watchdog function.) A reset clears BTCON to
"00H", automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by
the current CLKCON register setting), divided by 4096, as the BT clock.
Reset whenever a basic timer counter overflow occurs. During the normal operation, the application program
must prevent the overflow and the accompanying reset operation from occurring. To do this, the BTCNT value
must be cleared (by writing a "1" to BTCON.1) at regular intervals.
If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation
will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during the normal
operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken
by a BTCNT clear instruction. If a malfunction occurs, a reset is triggered automatically.
Oscillation Stabilization Interval Timer Function
You can also use the basic timer to program a specific oscillation stabilization interval after a reset or when Stop
mode has been released by an external interrupt.
In Stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. The BTCNT value then starts
increasing at the rate of fOSC/4096 (for reset), or at the rate of the preset clock source (for an external interrupt).
When BTCNT.3 overflows, a signal is generated to indicate that the stabilization interval has elapsed and to gate
the clock signal off to the CPU so that it can resume the normal operation.
In summary, the following events occur when Stop mode is released:
1. During the Stop mode, a power-on reset or an external interrupt occurs to trigger a Stop mode release and
oscillation starts.
2. If a power-on reset occurs, the basic timer counter increases at the rate of fOSC/4096. If an external interrupt
is used to release Stop mode, the BTCNT value increases at the rate of the preset clock source.
3. Clock oscillation stabilization interval begins and continues until bit 3 of the basic timer counter overflows.
4. When a BTCNT.3 overflow occurs, the normal CPU operation resumes.
TIMER 0 CONTROL REGISTER (T0CON)
You use the timer 0 control register, T0CON, to
—Select the timer 0 operating mode (interval timer, capture mode, or PWM mode)
—Select the timer 0 input clock frequency
—Clear the timer 0 counter, T0CNT
—Enable the timer 0 overflow interrupt or timer 0 match/capture interrupt
—Clear timer 0 match/capture interrupt pending conditions
BASIC TIMER and TIMER 0 KS88C0416/P0416/C0424/P0424
10-4
T0CON is located in set 1, at address D2H, and is read/write addressable using Register addressing mode.
A reset clears T0CON to "00H". This sets timer 0 to normal interval timer mode, selects an input clock frequency
of fOSC/4096, and disables all timer 0 interrupts. You can clear the timer 0 counter at any time during the normal
operation by writing a "1" to T0CON.3.
The timer 0 overflow interrupt (T0OVF) is in the interrupt level IRQ0 and has the vector address FAH. When a
timer 0 overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by
hardware.
To enable the timer 0 match/capture interrupt (IRQ0, vector FCH), you must write T0CON.1 to "1". To detect a
match/capture interrupt pending condition, the application program polls T0CON.0. When a "1" is detected, a
timer 0 match or capture interrupt is pending. When the interrupt request has been serviced, the pending
condition must be cleared by software by writing a "0" to the timer 0 interrupt pending bit, T0CON.0.
MSB LSB.7 .6 .5 .4 .3 .2 .1 .0
TIMER 0 CONTROL REGISTER (T0CON)
D2H, Set 1, R/W
Timer 0 match/capture
interrupt pending bit:
0 = No interrupt pending
0 = Clear pending bit (when write)
1 = Interrupt is pending
Timer 0 match/capture interrupt
enable bit:
0 = Disable interrupt
1 = Enable interrupt
Timer 0 overflow interrupt enable bit:
0 = Disable overflow interrupt
1 = Enable overflow interrupt
Timer 0 counter clear bit:
0 = No effect
1 = Clear the timer 0 counter (when write)
Timer 0 input clock selection bits:
00 = fOSC/4096
01 = fOSC/256
10 = fOSC/8
11 = External clock (P3.1/T0CK)
Timer 0 operating mode selection bits:
00 = Interval mode
01 = Capture mode (capture on rising edge,
counter running, OVF can occur)
10 = Capture mode (capture on falling
edge, counter running, OVF can occur)
11 = PWM mode (OVF interrupt can occur)
Figure 10-2. Timer 0 Control Register (T0CON)
KS88C0416/P0416/C0424/P0424 BASIC TIMER and TIMER 0
10-5
TIMER 0 FUNCTION DESCRIPTION
Timer 0 Interrupts (IRQ0, Vectors FAH and FCH)
The timer 0 module can generate two interrupts: the timer 0 overflow interrupt (T0OVF), and the timer 0 match/
capture interrupt (T0INT). T0OVF is in the interrupt level IRQ0, vector FAH. T0INT also belongs to the interrupt
level IRQ0, but is assigned the separate vector address, FCH.
A timer 0 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced.
The T0INT pending condition must, however, be cleared by the application’s interrupt service routine by writing a
"0" to the T0CON.0 interrupt pending bit.
Interval Timer Mode
In interval timer mode, a match signal is generated when the counter value is identical to the value written to the
T0 reference data register, T0DATA. The match signal generates a timer 0 match interrupt (T0INT, vector FCH)
and clears the counter.
If, for example, you write the value "10H" to T0DATA and "0BH" to T0CON, the counter will increment until it
reaches "10H". At this point, the T0 interrupt request is generated, the counter value is reset, and counting
resumes. With each match, the level of the signal at the timer 0 output pin is inverted (see Figure 10-3).
COUNTER
COMPARATOR
CLK R (Clear)
IRQ0 (INT)
INTERRUPT
ENABLE/DISABLE
(T0CON.1)
Match
T0CON.5
T0CON.4
P3.0/T0OUTCTL
PENDING
(T0CON.0)
BUFFER REGISTER
DATA REGISTER
Match Signal
T0CON.3
Figure 10-3. Simplified Timer 0 Function Diagram: Interval Timer Mode
BASIC TIMER and TIMER 0 KS88C0416/P0416/C0424/P0424
10-6
Pulse Width Modulation Mode
Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the
T0OUT pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value
written to the timer 0 data register. In PWM mode, however, the match signal does not clear the counter. Instead,
it runs continuously, overflowing at "FFH", and then continues incrementing from "00H".
Although you can use the match signal to generate a timer 0 overflow interrupt, interrupts are not typically used in
PWM-type applications. Instead, the pulse at the T0OUT pin is held to Low level as long as the reference data
value is less than or equal to ( ≤ ) the counter value and then the pulse is held to High level for as long as the data
value is greater than ( > ) the counter value. One pulse width is equal to tCLK × 256 (see Figure 10-4).
COUNTER
COMPARATOR
CLK IRQ0 (T0OVF)
Match P3.0/T0OUT
T0CON.5
T0CON.4
CTL
High level when
data > counter;
Low level when
data ≤ counter
NOTE:Interrupts are usually not used when timer 0 is configured to operate in PWM mode.
BUFFER REGISTER
DATA REGISTER
IRQ0
(T0INT)
INTERRUPT
ENABLE/DISABLE
(T0CON.1)
PND
Match Signal
T0CON.3
T0OVF
T0CON.0
Figure 10-4. Simplified Timer 0 Function Diagram: PWM Mode
KS88C0416/P0416/C0424/P0424 BASIC TIMER and TIMER 0
10-7
Capture Mode
In capture mode, a signal edge that is detected at the T0CAP pin opens a gate and loads the current counter
value into the T0 data register. You can select rising or falling edges to trigger this operation.
Timer 0 also gives you capture input source: the signal edge at the T0CAP pin. You can select the capture input
by setting the value of the timer 0 capture input selection bit in the port 3 control register, P3CON.3, (set 1, bank
0, F0H). When P3CON.3 is “1”, the T0CAP input is selected. When P3CON.3 is set to “0”, normal I/O port (P3.0)
is selected.
Both kinds of timer 0 interrupts can be used in capture mode: the timer 0 overflow interrupt is generated whenever
a counter overflow occurs; the timer 0 match/capture interrupt is generated whenever the counter value is loaded
into the T0 data register.
By reading the captured data value in T0DATA, and assuming a specific value for the timer 0 clock frequency,
you can calculate the pulse width (duration) of the signal that is being input at the T0CAP pin (see Figure 10-5).
COUNTER
DATA REGISTER
CLK IRQ0 (T0OVF)
P3.0/T0CAP
INTERRUPT ENABLE /
DISABLE (T0CON.1)
IRQ0 (T0INT)
T0CON.5
T0CON.4
T0CON.2
PENDING
(T0CON.0)
Figure 10-5. Simplified Timer 0 Function Diagram: Capture Mode
BASIC TIMER and TIMER 0 KS88C0416/P0416/C0424/P0424
10-8
Bits 7, 6
NOTES:
1. In a power-on reset operation, the CPU is idle during the required oscillation
stabilization interval (until bit 4 of the basic timer counter overflows).
2. It is available only in interval mode.
DIV
R
Bit 0
R
DIV
XIN
1/4096
1/1024
1/128
MUX
1/4096
1/256
1/8 MUX
Bits 3, 2
8-Bit Basic Counter
(Read-Only)
RESET or STOP
Data Bus
Basic Timer Control Register
(Write “1010xxxxB” to disable.)
RESET
OVF
8-Bit Up-Counter
(Read-Only)
8-Bit Comparator
R
Bits 5, 4
T0PWM
Match
Bit 2
Bit 3
T0INT
Basic Timer Control Register
Timer 0 Control Register
Data Bus
Timer 0 Buffer Reg
Clear
OVF
P3.1
P3.0
Timer 0 Data Register
(Read/Write)
Data Bus
Clear
Match Signal
T0CLR
T0OVF
(2)
Bit 1
PND
T0CON.0
T0OVF
Bit 1
Figure 10-6. Basic Timer and Timer 0 Block Diagram
KS88C0416/P0416/C0424/P0424 BASIC TIMER and TIMER 0
10-9
++ PROGRAMMING TIP — Configuring the Basic Timer
This example shows how to configure the basic timer to sample specifications:
ORG 0100H
RESET DI ;Disable all interrupts
LD BTCON,#0AAH ;Disable the watchdog timer
LD CLKCON,#18H ;Non-divided clock
CLR SYM ;Disable global and fast interrupts
CLR SPL ;Stack pointer low byte ← "0"
;Stack area starts at 0FFH
•
•
•
SRP #0C0H ;Set register pointer ← 0C0H
EI ;Enable interrupts
•
•
•
MAIN LD BTCON,#52H ;Enable the watchdog timer
;Basic timer clock: fOSC/4096
;Clear basic timer counter
NOP
NOP
•
•
•
JP T,MAIN
•
•
•
BASIC TIMER and TIMER 0 KS88C0416/P0416/C0424/P0424
10-10
++ PROGRAMMING TIP — Programming Timer 0
This sample program sets timer 0 to interval timer mode, sets the frequency of the oscillator clock, and
determines the execution sequence which follows a timer 0 interrupt. The program parameters are as follows:
—Timer 0 is used in interval mode; the timer interval is set to 4 milliseconds
—Oscillation frequency is 6 MHz
—General register 60H (page 0) ← 60H + 61H + 62H + 63H + 64H (page 0) is executed after a timer 0
interrupt
ORG 0FAH ;Timer 0 overflow interrupt
VECTOR T0OVER
ORG 0FCH ;Timer 0 match/capture interrupt
VECTOR T0INT
ORG 0100H
RESET DI ;Disable all interrupts
LD BTCON,#0AAH ;Disable the watchdog timer
LD CLKCON,#18H ;Select non-divided clock
CLR SYM ;Disable global and fast interrupts
CLR SPL ;Stack pointer low byte ← "0"
;Stack area starts at 0FFH
•
•
•
LD T0DATA,#5DH ;Set timer interval to 4 milliseconds
;(6 MHz/256) ÷ (93 + 1) = 0.25 kHz (4 ms)
LD T0CON,#4AH;Write "01001010B"
;Input clock is fOSC/256
;Interval timer mode
;Enable the timer 0 interrupt
;Disable the timer 0 overflow interrupt
SRP #0C0H ;Set register pointer ← 0C0H
EI ;Enable interrupts
•
•
•
T0INT PUSH RP0 ;Save RP0 to stack
SRP0 #60H ;RP0 ← 60H
INC R0 ;R0 ← R0 + 1
ADD R2,R0 ;R2 ← R2 + R0
ADC R3,R2 ;R3 ← R3 + R2 + Carry
ADC R4,R0 ;R4 ← R4 + R0 + Carry
(Continued on next page)
KS88C0416/P0416/C0424/P0424 BASIC TIMER and TIMER 0
10-11
++ PROGRAMMING TIP — Programming Timer 0 (Continued)
CP R0,#32H ;50 × 4 = 200 ms
JR ULT,NO_200MS_SET
BITS R1.2 ;Bit setting (61.2H)
NO_200MS_SET:
LD T0CON,#42H;Clear pending bit
POP RP0 ;Restore register pointer 0 value
T0OVER IRET ;Return from interrupt service routine
BASIC TIMER and TIMER 0 KS88C0416/P0416/C0424/P0424
10-12
NOTES
KS88C0416/P0416/C0424/P0424 TIMER 1
11-1
11 TIMER 1
OVERVIEW
The KS88C0416/C0424 microcontrollers have a 16-bit timer/counter called timer 1 (T1). For universal remote
controller applications, timer 1 can be used to generate the envelope pattern for the remote controller signal.
Timer 1 has the following components:
—One control register, T1CON (set 1, FAH, R/W)
—Two 8-bit counter registers, T1CNTH and T1CNTL (set 1, F6H and F7H, read-only)
—Two 8-bit reference data registers, T1DATAH and T1DATAL (set 1, F8H and F9H, R/W)
—A 16-bit comparator
You can select one of the following clock sources as the timer 1 clock:
—Oscillator frequency (fOSC) divided by 4, 8, or 16
—Internal clock input from the counter A module (counter A flip/flop output)
You can use Timer 1 in three ways:
—As a normal free run counter, generating a timer 1 overflow interrupt (IRQ1, vector F4H) at programmed time
intervals.
—To generate a timer 1 match interrupt (IRQ1, vector F6H) when the 16-bit timer 1 count value matches the 16-
bit value written to the reference data registers.
—To generate a timer 1 capture interrupt (IRQ1, vector F6H) when a triggering condition exists at the P3.0 pin
(You can select a rising edge, a falling edge, or both edges as the trigger).
In the KS88C0416/C0424 interrupt structure, the timer 1 overflow interrupt has higher priority than the timer 1
match or capture interrupt.
TIMER 1 KS88C0416/P0416/C0424/P0424
11-2
TIMER 1 OVERFLOW INTERRUPT
Timer 1 can be programmed to generate an overflow interrupt (IRQ1, F4H) whenever an overflow occurs in the
16-bit up counter. When you set the timer 1 overflow interrupt enable bit, T1CON.2, to “1”, the overflow interrupt is
generated each time the 16-bit up counter reaches "FFFFH". After the interrupt request is generated, the counter
value is automatically cleared to "00H" and up counting resumes. By writing a “1” to T1CON.3, you can clear/reset
the 16-bit counter value at any time during the program operation.
TIMER 1 CAPTURE INTERRUPT
Timer 1 can be used to generate a capture interrupt (IRQ1, vector F6H) whenever a triggering condition is
detected at the P3.0 pin. The T1CON.5 and T1CON.4 bit-pair setting is used to select the trigger condition for
capture mode operation: rising edges, falling edges, or both signal edges.
P3.0 is used as the input pin for both the timer 0 and timer 1 capture functions. To set P3.0 as the input pin for the
timer 1 capture functions, it should be set to schmitt trigger input mode and T0PWM/T0CAP/T1CAP mode by
setting P3CON to "00001000B" or "00001100B". To start the capture function of the timer 1, T1CON should be
set to capture mode and T1CAP_MAT interrupt enable by setting T1CON to "00011111B" or etc.
In capture mode, program software can poll the timer 1 match/capture interrupt pending bit, T1CON.0, to detect
when a timer 1 capture interrupt pending condition exists (T1CON.0 = “1”). When the interrupt request is
acknowledged by the CPU and the service routine starts, the interrupt service routine for vector F6H must clear
the interrupt pending condition by writing a “0” to T1CON.0.
16-BIT UP COUNTER
TIMER 1 DATA
CLK IRQ1 (T1OVF)
P3.0/T1CAP
INTERRUPT ENABLE /
DISABLE (T1CON.1)
IRQ1 (T1INT)
T1CON.5
T1CON.4
T1CON.2
PENDING
(T1CON.0)
Figure 11-1. Simplified Timer 1 Function Diagram: Capture Mode
KS88C0416/P0416/C0424/P0424 TIMER 1
11-3
TIMER 1 MATCH INTERRUPT
Timer 1 can also be used to generate a match interrupt (IRQ1, vector F6H) whenever the 16-bit counter value
matches the value that is written to the timer 1 reference data registers, T1DATAH and T1DATAL. When a match
condition is detected by the 16-bit comparator, the match interrupt is generated, the counter value is cleared, and
up counting resumes from "00H".
In match mode, program software can poll the timer 1 match/capture interrupt pending bit, T1CON.0, to detect
when a timer 1 match interrupt pending condition exists (T1CON.0 = “1”). When the interrupt request is
acknowledged by the CPU and the service routine starts, the interrupt service routine for vector F6H must clear
the interrupt pending condition by writing a “0” to T1CON.0.
16-BIT UP COUNTER
(Read Only)
16-BIT COMPARATOR
CLK R (Clear)
IRQ1 (T1INT)
INTERRUPT
ENABLE/DISABLE
(T1CON.2)
Match
T1CON.5
T1CON.4
P3.0/T1CAPCTL
PENDING
(T1CON.0)
TIMER 1 Hihg/Low
BUFFER REGISTER
Match Signal
T1CON.3
TIMER 1 DATA Hihg/Low
BUFFER REGISTER
Figure 11-2. Simplified Timer 1 Function Diagram: Interval Timer Mode
TIMER 1 KS88C0416/P0416/C0424/P0424
11-4
NOTE: Match signal is occured only in interval mode.
CAOF (T-F/F)
fOSC/4 MUX 16-Bit Up Counter
(Read-Only)
16-Bit Comparator
R
T1CON.5, .4
Match
T1INT
Clear
OVF
Timer 1 Data
High/Low Register
Data Bus
T1CON.3
Match Signal
T1OVF
(note)
T1CON.0
T1CON.2
M
U
X
Timer 1 High/Low
Buffer Register
fOSC/8
fOSC/16
T1OVF
T1CON.3
T1CON.7, .6
T1CON.1
T1CAP
P3.0
T1CON.5, .4
Figure 11-3. Timer 1 Block Diagram
KS88C0416/P0416/C0424/P0424 TIMER 1
11-5
TIMER 1 CONTROL REGISTER (T1CON)
The timer 1 control register, T1CON, is located in set 1, FAH, and is read/write addressable. T1CON contains
control settings for the following T1 functions:
—Timer 1 input clock selection
—Timer 1 operating mode selection
—Timer 1 16-bit down counter clear
—Timer 1 overflow interrupt enable/disable
—Timer 1 match or capture interrupt enable/disable
—Timer 1 interrupt pending control (read for status, write to clear)
A reset operation clears T1CON to "00H", selects fOSC divided by 4 as the T1 clock, configures timer 1 as a
normal interval timer, and disables the timer 1 interrupts.
MSB LSB.7 .6 .5 .4 .3 .2 .1 .0
TIMER 1 CONTROL REGISTER (T1CON)
FAH, Set 1, R/W
Timer 1 interrupt pending bit:
0 = No interrupt pending
0 = Clear pending bit (when write)
1 = Interrupt is pending
Timer 1 interrupt match
and capture enable bit:
0 = Disable interrupt
1 = Enable interrupt
Timer 1 overflow interrupt enable bit:
0 = Disable overflow interrupt
1 = Enable overflow interrupt
Timer 1 counter clear bit:
0 = No effect
1 = Clear the timer 1 counter (when write)
Timer 1 input clock selection bits:
00 = fOSC/4
01 = fOSC/8
10 = fOSC/16
11 = Internal clock (T-F/F)
Timer 1 operating mode selection bits:
00 = Interval mode
01 = Capture mode (capture on rising edge,
counter running, OVF can occur)
10 = Capture mode (capture on falling edge,
counter running, OVF can occur)
11 = Capture mode (capture on rising and
falling edge, OVF interrupt can occur)
Figure 11-4. Timer 1 Control Register (T1CON)
TIMER 1 KS88C0416/P0416/C0424/P0424
11-6
TIMER 1 COUNTER HIGH-BYTE REGISTER (T1CNTH)
F6H, Set1, R
Reset Value : 00H
TIMER 1 COUNTER LOW-BYTE REGISTER (T1CNTL)
F7H, Set1, R
Reset Value : 00H
TIMER 1 DATA HIGH-BYTE REGISTER (T1DATAH)
F8H, Set1, R/W
Reset Value : FFH
TIMER 1 DATA LOW-BYTE REGISTER (T1DATAL)
F9H, Set1, R/W
Reset Value : FFH
MSB LSB.7 .6 .5 .4 .3 .2 .1 .0
MSB LSB.7 .6 .5 .4 .3 .2 .1 .0
MSB LSB.7 .6 .5 .4 .3 .2 .1 .0
MSB LSB.7 .6 .5 .4 .3 .2 .1 .0
Figure 11-5. Timer 1 Registers
KS88C0416/P0416/C0424/P0424 COUNTER A
12-1
12 COUNTER A
OVERVIEW
The KS88C0416/C0424 microcontrollers have an 8-bit counter called counter A. Counter A, which can be used to
generate the carrier frequency, has the following components (see Figure 12-1):
—Counter A control register, CACON
—8-bit down counter with auto-reload function
—Two 8-bit reference data registers, CADATAH and CADATAL
Counter A has two functions:
—As a normal interval timer, it generates a counter A interrupt (IRQ4, vector ECH) at programmed time
intervals.
—Supplies a clock source to the 16-bit timer/counter module, timer 1, for generating the timer 1 overflow
interrupt.
COUNTER A KS88C0416/P0416/C0424/P0424
12-2
CACON.6-.7
MUX 8-BIT
DOWN COUNTER
MUX
CACON.4-.5
IRQ4
(CAINT)
To Other Block
(P3.1/REM)
CACON.3
INT. GEN.
COUNTER A Data
High Byte Register
Data Bus
fOSC
CLK
REPEAT
CONTROL
COUNTER A Data
Low Byte Register
CACON.2
CACON.O
(CAOF)
NOTE:The value of the CADATAL register is loaded into the 8-bit counter when the operation of the
counter A starts. If a borrow occurs in the counter, the value of the CADATAH register is loaded
into the 8-bit counter .
However, if the next borrow occurs, the value of the CADATAL register is loaded into the 8-bit counter.
INTERRUPT
CONTROL
DIV 1
DIV 2
DIV 4
DIV 8
Figure 12-1. Counter A Block Diagram
KS88C0416/P0416/C0424/P0424 COUNTER A
12-3
COUNTER A CONTROL REGISTER (CACON)
The counter A control register, CACON, is located in set 1, bank 0, F3H, and is read/write addressable. CACON
contains control settings for the following functions (see Figure 12-2):
—Counter A clock source selection
—Counter A interrupt enable/disable
—Counter A interrupt pending control (read for status, write to clear)
—Counter A interrupt time selection
MSB LSB.7 .6 .5 .4 .3 .2 .1 .0
COUNTER A CONTROL REGISTER (CACON)
F3H, Set 1, R/W
Counter A mode selection bit:
0 = One-shot mode
1 = Repeating mode
Counter A start/stop bit:
0 = Stop counter A
1 = Start counter A
Counter A input clock selection bits:
00 = fOSC
01 = fOSC/2
10 = fOSC/4
11 = fOSC/8
Counter A interrupt time selection bits:
00 = Elapsed time for Low data value
01 = Elapsed time for High data value
10 = Elapsed time for Low and High
data values
11 = Invalid setting
Counter A interrupt enable bit:
0 = Disable interrupt
1 = Enable interrut
Counter A output flip-flop control bit:
0 = T-FF is Low
1 = T-FF is High
Figure 12-2. Counter A Control Register (CACON)
COUNTER A KS88C0416/P0416/C0424/P0424
12-4
MSB LSB
.7 .6 .5 .4 .3 .2 .1 .0
COUNTER A DATA HIGH-BYTE REGISTER
(CADATAH) F4H, Set1, R/W
Reset Value : FFh
MSB LSB
.7 .6 .5 .4 .3 .2 .1 .0
COUNTER A DATA LOW-BYTE REGISTER
(CADATAL) F5H, Set1, R/W
Reset Value : FFh
Figure 12-3. Counter A Registers
COUNTER A PULSE WIDTH CALCULATIONS
tLOW tHIGH tLOW
To generate the repeated waveform above, which consists of low period time, tLOW, and high period time, tHIGH.
When CAOF = 0,
tLOW = (CADATAL + 2) x 1/Fx , 0H < CADATAL < 100H, where Fx = The selected clock.
tHIGH = (CADATAH + 2) x 1/Fx , 0H < CADATAH < 100H, where Fx = The selected clock.
When CAOF = 1,
tLOW = (CADATAH + 2) x 1/Fx , 0H < CADATAH < 100H, where Fx = The selected clock.
tHIGH = (CADATAL + 2) x 1/Fx , 0H < CADATAL < 100H, where Fx = The selected clock.
To make tLOW = 24 µs and tHIGH = 15 us. fOSC = 4 MHz, Fx = 4 MHz / 4 = 1 MHz
[Method 1] When CAOF = 0,
tLOW = 24 µs = (CADATAL + 2) / Fx = (CADATAL + 2) x 1µs, CADATAL = 22.
tHIGH = 15 µs = (CADATAH + 2) / Fx = (CADATAH + 2) x 1µs, CADATAH = 13.
[Method 2] When CAOF = 1,
tHIGH = 15 µs = (CADATAL + 2) / Fx = (CADATAL + 2) x 1µs, CADATAL = 13.
tLOW = 24 µs = (CADATAH + 2) / Fx = (CADATAH + 2) x 1µs, CADATAH = 22.
KS88C0416/P0416/C0424/P0424 COUNTER A
12-5
0H
COUNTER A
CLOCK
CAOF = ‘0’
CADATAL = 01-FFH
CADATAH = 00H
HIGH
CAOF = ‘0’
CADATAL = 00H
CADATAH = 01-FFH LOW
CAOF = ‘0’
CADATAL = 00H
CADATAH = 00H LOW
CAOF = ‘1’
CADATAL = 00H
CADATAH = 00H
HIGH
0H 100H 200H
80H
COUNTER A
CLOCK
80H
CAOF = ‘1’
CADATAL = DEH
CADATAH = 1EH
E0H
20H
CAOF = ‘1’
CADATAL = 7EH
CADATAH = 7EH
CAOF = ‘0’
CADATAL = DEH
CADATAH = 1EH 20H
E0H
80H 80H
CAOF = ‘0’
CADATAL = 7EH
CADATAH = 7EH
Figure 12-4. Counter A Output Flip-Flop Waveforms in Repeat Mode
COUNTER A KS88C0416/P0416/C0424/P0424
12-6
++ PROGRAMMING TIP — To generate 38 kHz, 1/3duty signal through P3.1
This example sets Counter A to repeat mode the oscillation frequency as the Counter A clock source, and
CADATAH and CADATAL to make a 38 kHz, 1/3 Duty carrier frequency. The program parameters are:
17.59 µs
8.795 µs
37.9 kHz 1/3Duty
—Counter A is used in repeat mode
—Oscillation frequency is 4 MHz (0.25 µs)
—CADATAH = 8.795 µs / 0.25 µs = 35.18, CADATAL = 17.59 µs / 0.25 µs = 70.36
—Set P3.1 C-Mos push-pull output and CAOF mode.
ORG 0100H ;Reset address
START DI
•
•
•
LD CADATAL,#(70–2) ;Set 17.5 µs
LD CADATAH,#(35–2) ;Set 8.75 µs
;
LD P3CON,#00110001B ;Set P3 to C-Mos push-pull output.
;Set P3.1 to REM output
;
LD CACON,#00000110B ;Clock Source ← fOSC
;Disable Counter A interrupt.
;Select repeat mode for Counter A.
; Start Counter A operation.
; Set Counter A Output Flip-flop (CAOF) high.
;
LD P3,#20H ;Set P3.5 (Carrier On/Off) to high.
;This command generates 38 kHz, 1/3 duty pulse signal
;through P3.1
;
•
•
•
KS88C0416/P0416/C0424/P0424 COUNTER A
12-7
++ PROGRAMMING TIP — To generate a one pulse signal through P3.1
This example sets Counter A to one shot mode the oscillation frequency as the Counter A clock source, and
CADATAH and CADATAL to make a 40 µs width pulse. The program parameters are:
40 µs
—Counter A is used in one shot mode
—Oscillation frequency is 4 MHz ( 1 clock = 0.25 µs)
—CADATAH = 40 µs / 0.25 µs = 160, CADATAL = 1
—Set P3.1 C-Mos push-pull output and CAOF mode.
ORG 0100H ;Reset address
START DI
•
•
LD CADATAH,# (160–2) ;Set 40 µs
LD CADATAL,# 1 ;Set any value except 00H
;
LD P3CON,#00110001B ;Set P3 to C-Mos push-pull output.
;Set P3.1 to REM output
;
LD CACON,#00000001B ;Clock Source ← fOSC
;Disable Counter A interrupt.
;Select one shot mode for Counter A.
; Stop Counter A operation.
; Set Counter A Output Flip-Flop (CAOF) high
LD P3,#20H ;Set P3.5(Carrier On/Off) to high.
•
•
•
Pulse_out: LD CACON,#00000101B ;Start Counter A operation
; to make the pulse at this point.
•;After the intsruction is executed, 0.75 µs is required
•;before the falling edge of the pulse starts.
•
COUNTER A KS88C0416/P0416/C0424/P0424
12-8
NOTES
KS88C0416/P0416/C0424/P0424 ELECTRICAL DATA
13-1
13 ELECTRICAL DATA
OVERVIEW
In this section, the KS88C0416/C0424 electrical characteristics are presented in tables and graphs. The
information is arranged in the following order:
—Absolute maximum ratings
—D.C. electrical characteristics
—Data retention supply voltage in Stop mode
—Stop mode release timing when initiated by an external interrupt
—Stop mode release timing when initiated by a Reset
—I/O capacitance
—A.C. electrical characteristics
—Input timing for external interrupts (port 0, P2.3–P2.0)
—Input timing for RESET
—Oscillation characteristics
—Oscillation stabilization time
—Operating voltage range
ELECTRICAL DATA KS88C0416/P0416/C0424/P0424
13-2
Table 13-1. Absolute Maximum Ratings
(TA = 25°C)
Parameter Symbol Conditions Rating Unit
Supply voltage VDD –– 0.3 to + 6.5 V
Input voltage VIN –– 0.3 to VDD + 0.3 V
Output voltage VOAll output pins – 0.3 to VDD + 0.3 V
Output current High IOH One I/O pin active – 18 mA
All I/O pins active – 60
Output current Low IOL One I/O pin active + 30 mA
Total pin current for ports 0, 1, and 2 + 100
Total pin current for port 3 + 40
Operating
temperature TA–– 40 to + 85 °C
Storage
temperature TSTG –– 65 to + 150 °C
Table 13-2. D.C. Electrical Characteristics
(TA = – 40°C to + 85°C, VDD = 2.0 V to 5.5 V)
Parameter Symbol Conditions Min Typ Max Unit
Operating Voltage VDD fOSC = 8 MHz
(Instruction clock = 1.33 MHz) 2.2 –5.5 V
fOSC = 4 MHz
(Instruction clock = 0.67 MHz) 2.0 –5.5
Input High voltage VIH1 All input pins except VIH2 and VIH3 0.8 VDD –VDD V
VIH2 RESET 0.85 VDD VDD
VIH3 XIN VDD – 0.3 VDD
Input Low voltage VIL1 All input pins except VIL2 and VIL3 0 – 0.2 VDD V
VIL2 RESET 0.4 VDD
VIL3 XIN 0.3
Output High
voltage VOH1 VDD = 2.4 V; IOH = – 6 mA
Port 3.1 only; TA = 25°CVDD – 0.7 – – V
VOH2 VDD = 2.4 V; IOH = – 3 mA
Port 3.0 only; TA = 25°CVDD – 0.7
KS88C0416/P0416/C0424/P0424 ELECTRICAL DATA
13-3
Table 13-2. D.C. Electrical Characteristics (Continued)
(TA = – 40°C to + 85°C, VDD = 2.0 V to 5.5 V)
Parameter Symbol Conditions Min Typ Max Unit
Output High
voltage VOH3 VDD = 5 V; IOH = – 3 mA
Port 2.7 only; TA = 25°CVDD– 0.25 – – V
VDD = 2 V; IOH = – 1 mA
Port 2.7 only; TA = 25°C
VOH4 VDD = 3.0 V; IOH = – 1 mA
All output pins except P3 and P2.7
port; TA = 25°C
VDD – 1
Output Low
voltage VOL1 VDD = 2.4 V; IOL = 15 mA
Port 3.1 only; TA = 25°C–0.4 0.5 V
VOL2 VDD = 2.4 V; IOL = 5 mA
Port 3.0 only; TA = 25°C0.4 0.5
VOL3 IOL = 1 mA
Port 0, 1, and 2; TA = 25°C0.4 1
Input High
leakage current ILIH1 VIN = VDD
All input pins except XIN and XOUT
– – 1 µA
ILIH2 VIN = VDD, XIN, and XOUT 20
Input Low
leakage current ILIL1 VIN = 0 V
All input pins except XIN, XOUT, and
RESET
– 1
ILIL2 VIN = 0 V
XIN and XOUT
– 20
Output High
leakage current ILOH VOUT = VDD
All output pins 1
Output Low
leakage current ILOL VOUT = 0 V
All output pins – 1
Pull-up resistorsRL1 VIN = 0 V; VDD = 2.0 V
TA = 25°C; Ports 0–3 65 95 143 KΩ
VDD = 5.5 V 15 21 32
ELECTRICAL DATA KS88C0416/P0416/C0424/P0424
13-4
Table 13-2. D.C. Electrical Characteristics (Concluded)
(TA = – 40°C to + 85°C, VDD = 2 V to 5.5 V)
Parameter Symbol Conditions Min Typ Max Unit
Supply current
(note) IDD1 Operating mode
VDD = 5 V ± 10%
8 MHz crystal
– 6 11 mA
4 MHz crystal 4.5 9
IDD2 Idle mode
VDD = 5 V ± 10%
8 MHz crystal
1.8 3.5
4 MHz crystal 1.6 3
IDD3 Stop mode
VDD = 5 V ± 10% 0.3 3µA
VDD = 3.6 V 0.1 1
NOTE:Supply current does not include the current drawn through internal pull-up resistors or external output current
loads.
Table 13-3. Data Retention Supply Voltage in Stop Mode
(TA = – 40 °C to + 85 °C)
Parameter Symbol Conditions Min Typ Max Unit
Data retention supply
voltage VDDDR –1.0 –5.5 V
Data retention supply
current IDDDR VDDDR = 1.0 V
Stop mode – – 1 µA
KS88C0416/P0416/C0424/P0424 ELECTRICAL DATA
13-5
VDD
EXT
INT
EXECUTION OF
STOP INSTRUCTION
VDDDR
DATA RETENTION MODE
STOP MODE NORMAL
OPERATING
MODE
tWAIT
0.2 VDD 0.8 VDD
IDLE MODE
(Basic Timer active)
~
~
~
~
Figure 13-1. Stop Mode Release Timing When Initiated by an External Interrupt
VDD
RESET
EXECUTION OF
STOP INSTRUCTION
DATA RETENTION MODE
STOP MODE NORMAL
OPERATING
MODE
tWAIT
OSCILLATION
STABILIZATION
TIME
RESET
OCCURS
~
~
~
~
VDDDR
NOTE: t WAIT is the same as 4096 x 16 x 1/fOSC.
Figure 13-2. Stop Mode Release Timing When Initiated by a Reset
ELECTRICAL DATA KS88C0416/P0416/C0424/P0424
13-6
Table 13-4. Input/Output Capacitance
(TA = – 40°C to + 85°C, VDD = 0 V)
Parameter Symbol Conditions Min Typ Max Unit
Input
capacitance CIN f = 1 MHz; unmeasured pins
are connected to VSS – – 10 pF
Output
capacitance COUT
I/O capacitance CIO
Table 13-5. A.C. Electrical Characteristics
(TA = – 40°C to + 85°C)
Parameter Symbol Conditions Min Typ Max Unit
Interrupt input,
High, Low width tINTH,
tINTL
P0.0–P0.7, P2.3–P2.0
VDD = 5 V 200 300 – ns
RESET input Low
width tRSL Input
VDD = 5 V 1000 – –
tINTLtINTH
0.8 VDD
0.2 VDD
NOTE:The unit tCPU means one CPU clock period.
Figure 13-3. Input Timing for External Interrupts (Port 0, P2.3–P2.0)
KS88C0416/P0416/C0424/P0424 ELECTRICAL DATA
13-7
Back-Up Mode (STOP MODE)
RESET
VDD
RESET
OCCRURRS OSCILLATION
STABILIZATION
TIME
NORMAL
OPERATING
MODE
tWAIT
NORMAL
OPERATING
MODE
NOTE: t WAIT is the same as 4096 x 16 x 1/fOSC.
Figure 13-4. Input Timing for RESET
Table 13-6. Oscillation Characteristics
(TA = – 40°C + 85°C)
Oscillator Clock Circuit Conditions Min Typ Max Unit
Crystal
C2
C1 XIN
XOUT
CPU clock oscillation
frequency 1–8MHz
Ceramic
C2
C1 XIN
XOUT
CPU clock oscillation
frequency 1–8MHz
External clock
KS88C0416
EXTERNAL
CLOCK
OPEN PIN
XIN
XOUT
XIN input frequency 1–8MHz
ELECTRICAL DATA KS88C0416/P0416/C0424/P0424
13-8
Table 13-7. Oscillation Stabilization Time
(TA = – 40°C + 85°C, VDD = 4.5 V to 5.5 V)
Oscillator Test Condition Min Typ Max Unit
Main crystal fOSC > 400 kHz – – 20 ms
Main ceramic Oscillation stabilization occurs when VDD is equal
to the minimum oscillator voltage range. – – 10 ms
External clock
(main system) XIN input High and Low width (tXH, tXL)25 – 500 ns
Oscillator
stabilization wait
time
tWAIT when released by a reset (1) –216/fOSC –ms
tWAIT when released by an interrupt (2) –––ms
NOTES:
1. fOSC is the oscillator frequency.
2. The duration of the oscillation stabilization time (tWAIT) when it is released by an interrupt is determined by the setting
in the basic timer control register, BTCON.
KS88C0416/P0416/C0424/P0424 ELECTRICAL DATA
13-9
Instruction Clock = 1/6n x oscillator frequency (n = 1, 2, 8, 16)
Supply Voltage (V)
250 kHz
500 kHz
670 kHz
1.00 MHz
8.32 kHz
Instruction
Clock
1 2 3 4 5 6 7
fOSC
(Main oscillation
frequency)
6 MHz
4 MHz
400 kHz
8 MHz
1.33 MHz
2.2 5.5
Figure 13-5. Operating Voltage Range
ELECTRICAL DATA KS88C0416/P0416/C0424/P0424
13-10
NOTES
KS88C0416/P0416/C0424/P0424 MECHANICAL DATA
14-1
14 MECHANICAL DATA
OVERVIEW
The KS88C0416/C0424 microcontroller is currently available in a 32-pin SOP and SDIP package. The
KS88C0424 is available one more 40 DIP package.
0.25 +0.10
- 0.05
8.34 ± 0.2
0.90 ± 0.20
#1 #16
#32 #17
32-SOP-450A
12.00 ± 0.2
NOTE: Dimensions are in millimeters.
19.90
± 0.2
0.10 MAX
0.05MIN 2.00 ± 0.1
2.30MAX
(0.43) 0.40 ± 0.1 1.27
10.02 ± 0.1
Figure 14-1. 32-Pin SOP Package Mechanical Data
MECHANICAL DATA KS88C0416/P0416/C0424/P0424
14-2
NOTE: Dimensions are in millimeters.
9.10 ± 0.20
#1 #16
#32 #17 0 – 15 *
0.25 +0.1
– 0.05
10.16
0.51MIN 3.80 ± 0.2
3.30 ± 0.3 5.08MAX
(1.37)
29.40± 0.2
29.80 MAX
1.778
0.45 ± 0.10
1.00 ± 0.10
32-SDIP-400
Figure 14-2. 32-Pin SDIP Package Mechanical Data
KS88C0416/P0416/C0424/P0424 MECHANICAL DATA
14-3
#40 #21
NOTE: Dimensions are in millimeters.
15.24
0.25 + 0.1
– 0.05
0.3 MIN 4.10 ± 0.2
3.30 ± 0.3 5.08MAX
52.10 ± 0.2
1.27 ± 0.1
0.46 ± 0.1
(1.92)
40-DIP-600B
13.80 ± 0.2
#1 #20
2.54
Figure 14-3. 40-Pin DIP Package Mechanical Data of KS88C0424
MECHANICAL DATA KS88C0416/P0416/C0424/P0424
14-4
NOTES
KS88C0416/P0416/C0424/P0424 KS88P0416/P0424 OTP
15-1
15 KS88P0416/P0424 OTP
OVERVIEW
The KS88P0416/P0424 single-chip CMOS microcontrollers are the OTP (One Time Programmable) version of
the KS88C0416/C0424 microcontrollers. They have an on-chip EPROM instead of a masked ROM.
The KS88P0416/P0424 are fully compatible with the KS88C0416/C0424, both in function and in pin
configuration. Because of their simple programming requirements, the KS88P0416/P0424 are ideal as an
evaluation chip for the KS88C0416/C0424.
VSS
XIN
A14 (2)/XOUT
MODE/TEST
PGM/P2.0/INT5
MEM_REG/P2.1/INT6
A8/P2.2/INT7
A9/P2.3/INT8
A0/P0.0/INT0
A1/P0.1/INT1
A2/P0.2/INT2
A3/P0.3/INT3
A4/P0.4/INT4
A5/P0.5/INT4
A6/P0.6/INT4
A7/P0.7/INT4
VDD
P3.1/REM/T0CK/ CE
P3.0/T0PWM/T0CAP/T1CAP/OE
P2.7/A13
P2.6/A12
P2.5/A11
P2.4/A10
P1.7/D7
P1.6/D6
P1.5/D5
P1.4/D4
P1.3/D3
P1.2/D2
P1.1/D1
P1.0/D0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
KS88P0416
KS88P0424
32-SOP/SDIP
(Top View)
RESET/VPP
NOTES:
1. The bolds indicate an OTP pin name.
2. A14 is not valid in KS88P0416.
Figure 15-1. KS88P0416/P0424 Pin Assignments of 32SOP/32SDIP
KS88P0416/P0424 OTP KS88C0416/P0416/C0424/P0424
15-2
VSS
XIN
A14/XOUT
MODE/TEST
NC
NC
PGM/P2.0/INT5
MEM_REG/P2.1/INT6
A8/P2.2/INT7
A9/P2.3/INT8
A0/P0.0/INT0
A1/P0.1/INT1
A2/P0.2/INT2
A3/P0.3/INT3
NC
NC
A4/P0.4/INT4
A5/P0.5/INT4
A6/P0.6/INT4
A7/P0.7/INT4
VDD
P3.1/REM/T0CK/CE
P3.0/T0PWM/T0CAP/T1CAP/OE
NC
NC
P2.7/A13
P2.6/A12
P2.5/A11
P2.4/A10
P1.7/D7
P1.6/D6
P1.5/D5
P1.4/D4
NC
NC
P1.3/D3
P1.2/D2
P1.1/D1
P1.0/D0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
KS88P0416/
KS88P0424
40-DIP
(Top View)
RESET/VPP
NOTES:
1. The bolds indicate an OTP pin name.
2. A14 is not valid in KS88P0416.
Figure 15-2. KS88P0424 Pin Assignments of 40DIP
KS88C0416/P0416/C0424/P0424 KS88P0416/P0424 OTP
15-3
Table 15-1. 32 SOP/SDIP Pin Descriptions used to read/write the EPROM
Pin Name Pin No. I/O Function
A0–A14 3, 7–16, 25–28 OAddress lines to read/write EPROM
D0–D7 17–24 I/O 8-bit data input/output lines to read/write EPROM
MODE 4 – Select EPROM mode.
CE 30 IChip enable (Connect to VSS, when read/write EPROM)
OE 29 IOutput enable
PGM 5IEPROM Program enable
MEM_REG 6ISelect Memory space of EPROM
VDD 32 – Supply voltage (normally 5 V)
VPP 31 – EPROM Program/Verify voltage (normally 12.5 V)
VSS 1 – Ground
XIN 2 – System clock input pin
XOUT 3 – System clock output pin (when KS88P0416)
CHARACTERISTICS OF EPROM OPERATION
When +12.5 V is supplied to VPP and MODE pins of the KS88P0416/P0424, the EPROM programming mode is
entered. The operating mode (read, write) is selected according to the input signals to the pins listed in Table 2
as below.
Table 15-2. Operating Mode Selection Criteria
VDD MODE VPP PGM MEM OE Mode
5 V VPP 12.5 V 110READ
011PROGRAM
110PROGRAM VERIFY
NOTE:"0" means Low level; "1" means High level.
KS88P0416/P0424 OTP KS88C0416/P0416/C0424/P0424
15-4
MODE
D7−−D0
A14−−A0
tOED
tACC
tOEW
tOEH
12.5V
OE
Figure 15-3. OTP Read Timing
Table 15-3. OTP Read characteristics
(TA = 25 °C ± 5°C, VDD = 5 V ± 5 %, VPP = 12.5 V ± 0.25V)
Parameter Symbol Min Typ Max Units
Address to Output Delay tACC – – 75 ns
to Address Delay tOED 0––
OE Pulse Width tOEW 75 – –
Output hold from OE
whichever occurs first TOEH 0––
KS88C0416/P0416/C0424/P0424 KS88P0416/P0424 OTP
15-5
PGM
D7−−D0
A14−−A0
tOEW
tOE
tOEH
tPW
tVS
tDS
Data In Stable Data Out Valid
PROGRAM VERIFYPROGRAM
tDH
MODE
OE
Figure 15-4. Program Memory Write Timing
Table 15-4. OTP Program/Program Verify Characteristics
(TA = 25 °C ± 5°C, VDD = 5 V ± 5 %, VPP = 12.5 V ± 0.25V)
Parameter Symbol Min Typ Max Units
VPP Setup Time tVS –2–µs
Data Setup Time tDS –2–
Data Hold Time tDH –2–
Pulse Width tPW – 300 500
Data Valid from OE tOE75 – – ns
OE Pulse Width tOEW 75 – –
Output Enable to Output Float
Delay tOEH0 – 130
KS88P0416/P0424 OTP KS88C0416/P0416/C0424/P0424
15-6
START
Address= First Location
VDD=5V, VPP=12.5V
x = 0
Program One 1ms Pulse
Increment X
x = 10
Verify 1 Byte
Last Address
VDD = VPP= 5 V
Compare All Byte
Device Passed
Increment Address
Verify Byte
Device Failed
PASS
FAIL
NO
FAIL
YES
FAIL
NO
Figure 15-5. OTP Programming Algorithm
KS88C0416/P0416/C0424/P0424 KS88P0416/P0424 OTP
15-7
Table 15-5. D.C. Electrical Characteristics
(TA = – 40°C to + 85°C, VDD = 2.0 V to 5.5 V)
Parameter Symbol Conditions Min Typ Max Unit
Operating Voltage VDD fOSC = 8 MHz
(Instruction clock = 1.33 MHz) 2.2 –5.5 V
fOSC = 4 MHz
(Instruction clock = 0.67 MHz) 2.0 –5.5
Input High voltage VIH1 All input pins except VIH2 and VIH3 0.8 VDD –VDD V
VIH2 RESET 0.85 VDD VDD
VIH3 XIN VDD – 0.3 VDD
Input Low voltage VIL1 All input pins except VIL2 and VIL3 0 – 0.2 VDD V
VIL2 RESET 0.4 VDD
VIL3 XIN 0.3
Output High
voltage VOH1 VDD = 2.4 V; IOH = – 6 mA
Port 3.1 only; TA = 25°CVDD – 0.7 – – V
VOH2 VDD = 2.4 V; IOH = – 3 mA
Port 3.0 only; TA = 25°CVDD – 0.7
Output High
voltage VOH3 VDD = 5 V; IOH = – 3 mA
Port 2.7 only; TA = 25°CVDD– 0.25 – – V
VDD = 2 V; IOH = – 1 mA
Port 2.7 only; TA = 25°C
VOH4 VDD = 3.0 V; IOH = – 1 mA
All output pins except P3 and P2.7
port; TA = 25°C
VDD – 1
Output Low
voltage VOL1 VDD = 2.4 V; IOL = 15 mA
Port 3.1 only; TA = 25°C–0.4 0.5 V
VOL2 VDD = 2.4 V; IOL = 5 mA
Port 3.0 only; TA = 25°C0.4 0.5
VOL3 IOL = 1 mA
Port 0, 1, and 2; TA = 25°C0.4 1
Input High
leakage current ILIH1 VIN = VDD
All input pins except XIN and XOUT
– – 1 µA
ILIH2 VIN = VDD, XIN, and XOUT 20
KS88P0416/P0424 OTP KS88C0416/P0416/C0424/P0424
15-8
Table 15-5. D.C. Electrical Characteristics (Continued)
(TA = – 40°C to + 85°C, VDD = 2.0 V to 5.5 V)
Parameter Symbol Conditions Min Typ Max Unit
Input Low
leakage current ILIL1 VIN = 0 V
All input pins except XIN, XOUT, and
RESET
– – – 1 µA
ILIL2 VIN = 0 V
XIN and XOUT
– 20
Output High
leakage current ILOH VOUT = VDD
All output pins 1
Output Low
leakage current ILOL VOUT = 0 V
All output pins – 1
Pull-up resistorsRL1 VIN = 0 V; VDD = 2.0 V
TA = 25°C; Ports 0–3 65 95 143 kΩ
VDD = 5.5 V 15 21 32
Supply current
(note) IDD1 Operating mode
VDD = 5 V ± 10%
8 MHz crystal
– 6 11 mA
4 MHz crystal 4.5 9
IDD2 Idle mode
VDD = 5 V ± 10%
8 MHz crystal
1.8 3.5
4 MHz crystal 1.6 3
IDD3 Stop mode
VDD = 5 V ± 10% 0.3 3µA
VDD = 3.6 V 0.1 1
NOTE:Supply current does not include the current drawn through internal pull-up resistors or external output current loads.
KS88C0416/P0416/C0424/P0424 KS88P0416/P0424 OTP
15-9
Instruction Clock = 1/6n x oscillator frequency (n = 1, 2, 8, 16)
Supply Voltage (V)
250 kHz
500 kHz
670 kHz
1.00 MHz
8.32 kHz
Instruction
Clock
1 2 3 4 5 6 7
fOSC
(Main oscillation
frequency)
6 MHz
4 MHz
400 kHz
8 MHz
1.33 MHz
2.2 5.5
Figure 15-6. Operating Voltage Range
KS88P0416/P0424 OTP KS88C0416/P0416/C0424/P0424
15-10
NOTES
KS88C0416/P0416/C0424/P0424 DEVELOPMENT TOOLS
16-1
16 DEVELOPMENT TOOLS
OVERVIEW
Samsung provides a powerful and easy-to-use development support system on a turnkey basis. The
development support system is composed of a host system, debugging tools, and supporting software. For a host
system, any standard computer that employs MS-DOS as its operating system can be used. A sophisticated
debugging tool is provided both in hardware and software: the powerful in-circuit emulator, SMDS2+, for the
KS57, KS86, and KS88 microcontroller families. SMDS2+ is a newly improved version of SMDS2. Samsung also
offers supporting software that includes, debugger, an assembler, and a program for setting options.
SHINE
Samsung Host Interface for In-Circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE
provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked
help. It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be
easily sized, moved, scrolled, highlighted, added, or removed.
SAMA ASSEMBLER
The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generating
an object code in the standard hexadecimal format. Assembled program codes include the object code used for
ROM data and required SMDS program control data. To assemble programs, SAMA requires a source file and
an auxiliary definition (DEF) file with device specific information.
SASM88
The SASM88 is an relocatable assembler for Samsung's KS88-series microcontrollers. The SASM88 takes a
source file containing assembly language statements and translates them into a corresponding source code, an
object code and comments. The SASM88 supports macros and conditional assembly. It runs on the MS-DOS
operating system. As it produces relocatable object codes only, the user should link object files. Object files can
be linked with other object files and loaded into memory.
HEX2ROM
HEX2ROM file generates a ROM code from a HEX file which is produced by the assembler. A ROM code is
needed to fabricate a microcontroller which has a mask ROM. When generating a ROM code (.OBJ file) by
HEX2ROM, the value "FF" is automatically filled into the unused ROM area, upto the maximum ROM size of the
target device.
TARGET BOARDS
Target boards are available for all the KS88-series microcontrollers. All the required target system cables and
adapters are included on the device-specific target board.
OTPs
One time programmable microcontrollers (OTP) for the KS88C0416/C0424 and OTP programmer (Gang) are
now available.
DEVELOPMENT TOOLS KS88C0416/P0416/C0424/P0424
16-2
RAM BREAK/ DISPLAY UNIT
TARGET
APPLICATION
SYSTEM
PROBE
ADAPTER
TB880416A/24A
TB8801416A/24A
TARGET
BOARD
PROM/OTP WRITER UNIT
TRACE/TIMER UNIT
SAM8 BASE UNIT
POWER SUPPLY UNIT
POD
RS-232C
IBM-PC AT or Compatible
BUS
SMDS2+
EVA
CHIP
Figure 16-1. SMDS Product Configuration (SMDS2+)
KS88C0416/P0416/C0424/P0424 DEVELOPMENT TOOLS
16-3
TB880416A/24A TARGET BOARD
The TB880416A/24A target board is used for the KS88C0416/C0424 and the KS88P0416/P0424 microcontroller.
It is supported by the SMDS2+ development system.
SM1304A
TB880416A/24A
TB8801416A/24A
3
0-PIN CONNECTOR
1 30
15 16
1
25
EXTERNAL
TRIGGERS
CH1
CH2
OFF ON
To User_Vcc
RESET
100 QFP
KS88E0400
EVA CHIP
GND VCC
CN1
U2
+
STOP
+
IDLE
100-PIN CONNECTOR
1 30
74HC11
SMDS2 SMDS2+
CN2
Figure 16-2. TB880416A/24A Target Board Configuration
DEVELOPMENT TOOLS KS88C0416/P0416/C0424/P0424
16-4
Table 16-1. Power Selection Settings for TB880416A/24A
"To User_Vcc"
Settings Operating Mode Comments
To User_Vcc
ONOFF TARGET
SYSTEM
SMDS2/SMDS2+
VCC
VCC
TB880416A/24A
TB8801416A/24A VSS
SMDS2/SMDS2+ supplies
VCC to the target board
(evaluation chip) and the
target system.
To User_Vcc
ONOFF
VCC
TARGET
SYSTEM
External
VCC
SMDS2/SMDS2+
VSS
TB880416A/24A
TB8801416A/24A
SMDS2/SMDS2+ supplies
VCC only to the target board
(evaluation chip). The target
system must have a power
supply of its own.
SMDS2+ Selection (SAM8)
In order to write data into program memory available in SMDS2+, the target board should be selected for
SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available.
Table 16-2. The SMDS2+ Tool Selection Setting
"SW1" Setting Operating Mode
SMDS2 SMDS2+
SMDS2+
TARGET
BOARD
R/W* R/W*
KS88C0416/P0416/C0424/P0424 DEVELOPMENT TOOLS
16-5
Table 16-3. Using Single Header Pins as the Input Path for External Trigger Sources
Target Board Part Comments
EXTERNAL
TRIGGERS
CH1
CH2
Connector from
external trigger
sources of the
application system
You can connect an external trigger source to one of the two external
trigger channels (CH1 or CH2) for the SMDS2+ breakpoint and trace
functions.
IDLE LED
This LED is ON when the evaluation chip (KS88E0400) is in idle mode.
STOP LED
This LED is ON when the evaluation chip (KS88E0400) is in stop mode.
DEVELOPMENT TOOLS KS88C0416/P0416/C0424/P0424
16-6
VSS
TEST
P2.0
P2.1
P2.2
P2.3
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
VDD
RESET
P3.1
P3.0
P2.7
P2.6
P2.5
P2.4
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
CN2
3
0-PIN DIP CONNECTOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Figure 16-3. 30-Pin Connector (CN2) for TB880416A/24A
30-PIN DIP SOCKET
TARGET BOARD TARGET SYSTEM
Part Name: AP32SD-A
Order Code: SM6506
130
15 16
CN2
1 30
15 16
1 32
16 17
AP32SD-A
Figure 16-4. TB880416A/24A Adapter Cable for 32-SDIP Package (KS88C0416/C0424)
