ÉlanSC400 Microcontroller
Register Set
Reference Manual
Rev. A, December 1996
© 1996 Advanced Micro Devices, Inc.
Advanced Micro Devices reserves the right to make changes in its products
without notice in order to improve design or performance characteristics.
The information in this publication is believed to be accurate at the time of publication, but AMD makes no representations or warranties with
respect to accuracy or completeness of the contents of this publication or the information contained herein, and reserves the right to make changes
at an time, without any notice. AMD disclaims responsibility for any consequences resulting from the use of the information included in this
publication.
This publication neither states nor implies any representations or warranties of any kind, including but not limited to, any implied warranty of
merchantability or fitness for a particular purpose. AMD products are not authorized for use as critical components in life support devices or
systems without AMD’s written approval. AMD assumes no liability whatsoever for claims associated with the sale or use (including the use of
engineering samples) of AMD product except as provided in AMD’s Terms and Conditions of Sale for such product.
Trademarks
AMD, the AMD logo and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Am386 and Am486 are registered trademarks, and Am186, Am188, E86, K86, Élan, Systems in Silicon, and AMD Facts-On-Demand are trade-
marks of Advanced Micro Device s, Inc. Microsoft and Windows are registered trademarks of Microsoft Corp. Product names used in this publi-
cation are for identification purposes and may be trademarks of their respective companies.
FusionE86 is a service mark of Advanced Micro Devices, Inc.
Table of Contents iii
TABLE OF CONTENTS
PREFACE INTRODUCTION
ÉlanSC400 Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
Purpose of This Manual. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
Overview of This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv
AMD Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv
Documentation Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xv
CHAPTER 1 OVERVIEW
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1
Direct-Mapped Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1
Internal I/O Port Address Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2
Indexed Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2
CHAPTER 2 PC/AT-COMPATIBLE DIRECT-MAPPED REGISTERS
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
PC/AT-Compatible Direct-Mapped Register Map . . . . . . . . . . . . . . . . . . . .2-1
Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5
Slave DMA Channel 0 Memory Address Register . . . . . . . . . . . . . . . . . . . .2-6
Slave DMA Channel 0 Transfer Count Register . . . . . . . . . . . . . . . . . . . . . .2-7
Slave DMA Channel 1 Memory Address Register . . . . . . . . . . . . . . . . . . . .2-8
Slave DMA Channel 1 Transfer Count Register . . . . . . . . . . . . . . . . . . . . . .2-9
Slave DMA Channel 2 Memory Address Register . . . . . . . . . . . . . . . . . . .2-10
Slave DMA Channel 2 Transfer Count Register . . . . . . . . . . . . . . . . . . . . .2-11
Slave DMA Channel 3 Memory Address Register . . . . . . . . . . . . . . . . . . .2-12
Slave DMA Channel 3 Transfer Count Register . . . . . . . . . . . . . . . . . . . . .2-13
Slave DMA Status Register for Channels 0–3 . . . . . . . . . . . . . . . . . . . . . .2-14
Slave DMA Control Register for Channels 0–3. . . . . . . . . . . . . . . . . . . . . .2-15
Slave Software DRQ(n) Request Register . . . . . . . . . . . . . . . . . . . . . . . . .2-17
Slave DMA Mask Register Channels 0–3. . . . . . . . . . . . . . . . . . . . . . . . . .2-18
Slave DMA Mode Register Channels 0–3 . . . . . . . . . . . . . . . . . . . . . . . . .2-19
Slave DMA Clear Byte Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . .2-20
Slave DMA Controller Reset Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-21
Slave DMA Controller Temporary Register. . . . . . . . . . . . . . . . . . . . . . . . .2-22
Slave DMA Reset Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-23
Slave DMA General Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-24
Master 8259 Interrupt Request Register. . . . . . . . . . . . . . . . . . . . . . . . . . .2-25
Master 8259 In-Service Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-26
Master 8259 Initialization Control Word 1 Register. . . . . . . . . . . . . . . . . . .2-27
Master 8259 Operation Control Word 2 Register . . . . . . . . . . . . . . . . . . . .2-28
Master 8259 Operation Control Word 3 Register . . . . . . . . . . . . . . . . . . . .2-29
Master 8259 Initialization Control Word 2 Register. . . . . . . . . . . . . . . . . . .2-30
Master 8259 Initialization Control Word 3 Register. . . . . . . . . . . . . . . . . . .2-31
Master 8259 Initialization Control Word 4 Register. . . . . . . . . . . . . . . . . . .2-32
Master 8259 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-33
ÉlanSC400 Microcontroller Chip Setup and Control
(CSC) Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-34
ÉlanSC400 Microcontroller Chip Setup and Control
(CSC) Data Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-35
Table of Contents
iv
Programmable Interval Timer #1 Channel 0 Count
Register (System Timer/Timer Tick) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-36
Programmable Interval Timer #1 Channel 1 Count
Register (Refresh Timer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-37
Programmable Interval Timer #1 Channel 2 Count
Register (Speaker Timer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-38
Programmable Interval Timer #1 Status Register. . . . . . . . . . . . . . . . . . . .2-39
Counter Mode Status Bits 3–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-40
Programmable Interval Timer #1 Mode Control Register . . . . . . . . . . . . . .2-41
Programmable Interval Timer #1 Counter Latch Command Register . . . .2-43
Programmable Interval Timer #1 Read-back Command Register . . . . . . .2-44
Keyboard/Mouse Interface Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . .2-45
PC/AT Keyboard Interface Data Register. . . . . . . . . . . . . . . . . . . . . . . . . .2-46
PC/XT Keyboard Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-47
System Control Port B/NMI Status Register . . . . . . . . . . . . . . . . . . . . . . . .2-48
PC/AT Keyboard/Mouse Interface Status Register . . . . . . . . . . . . . . . . . .2-49
Keyboard/Mouse Interface Command Register . . . . . . . . . . . . . . . . . . . . .2-51
RTC/CMOS RAM Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-52
RTC/CMOS RAM Data Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-53
General Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-54
DMA Channel 2 Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-55
DMA Channel 3 Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-56
DMA Channel 1 Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-57
General Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-58
General Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-59
General Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-60
DMA Channel 0 Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-61
General Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-62
DMA Channel 6 Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-63
DMA Channel 7 Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-64
DMA Channel 5 Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-65
General Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-66
General Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-67
General Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-68
General Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-69
System Control Port A Register (PS/2 Compatibility Port) . . . . . . . . . . . . .2-70
Slave 8259 Interrupt Request Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .2-71
Slave 8259 In-Service Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-72
Slave 8259 Initialization Control Word 1 Register. . . . . . . . . . . . . . . . . . . .2-73
Slave 8259 Operation Control Word 2 Register . . . . . . . . . . . . . . . . . . . . .2-75
Slave 8259 Operation Control Word 3 Register . . . . . . . . . . . . . . . . . . . . .2-76
Slave 8259 Initialization Control Word 2 Register. . . . . . . . . . . . . . . . . . . .2-77
Slave 8259 Initialization Control Word 3 Register. . . . . . . . . . . . . . . . . . . .2-78
Slave 8259 Initialization Control Word 4 Register . . . . . . . . . . . . . . . . . . .2-79
Slave 8259 Interrupt Mask Register (also known as
Operation Control Word 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-80
Master DMA Channel 4 Memory Address Register . . . . . . . . . . . . . . . . . .2-81
Master DMA Channel 4 Transfer Count Register . . . . . . . . . . . . . . . . . . . .2-82
Master DMA Channel 5 Memory Address Register . . . . . . . . . . . . . . . . . .2-83
Master DMA Channel 5 Transfer Count Register . . . . . . . . . . . . . . . . . . . .2-84
Master DMA Channel 6 Memory Address Register . . . . . . . . . . . . . . . . . .2-85
Master DMA Channel 6 Transfer Count Register . . . . . . . . . . . . . . . . . . . .2-86
Master DMA Channel 7 Memory Address Register . . . . . . . . . . . . . . . . . .2-87
Master DMA Channel 7 Transfer Count Register . . . . . . . . . . . . . . . . . . .2-88
Master DMA Status Register for Channels 4–7 . . . . . . . . . . . . . . . . . . . . .2-89
Master DMA Control Register for Channels 4–7 . . . . . . . . . . . . . . . . . . . .2-90
Master Software DRQ(n) Request Register . . . . . . . . . . . . . . . . . . . . . . . .2-92
Table of Contents v
Master DMA Mask Register Channels 4–7 . . . . . . . . . . . . . . . . . . . . . . . .2-93
Master DMA Mode Register Channels 4–7 . . . . . . . . . . . . . . . . . . . . . . . .2-94
Master DMA Clear Byte Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . .2-95
Master DMA Controller Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . .2-96
Master DMA Controller Temporary Register . . . . . . . . . . . . . . . . . . . . . . .2-97
Master DMA Reset Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-98
Master DMA General Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-99
Alternate Gate A20 Control Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-100
Alternate CPU Reset Control Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-101
Parallel Port 2 Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-102
Parallel Port 2 Status Register (PC/AT Compatible Mode). . . . . . . . . . . .2-103
Parallel Port 2 Status Register (Bidirectional Mode). . . . . . . . . . . . . . . . .2-104
Parallel Port 2 Status Register (EPP Mode) . . . . . . . . . . . . . . . . . . . . . . .2-105
Parallel Port 2 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-106
Parallel Port 2 EPP Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . .2-107
Parallel Port 2 EPP 32-bit Data Register . . . . . . . . . . . . . . . . . . . . . . . . .2-108
COM2 Transmit Holding Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-109
COM2 Receive Buffer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-110
COM2 Baud Clock Divisor Latch LSB. . . . . . . . . . . . . . . . . . . . . . . . . . . .2-111
COM2 Baud Clock Divisor Latch MSB . . . . . . . . . . . . . . . . . . . . . . . . . . .2-112
COM2 Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-113
COM2 Interrupt ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-114
COM2 FIFO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-116
COM2 Line Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-117
COM2 Modem Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-118
COM2 Line Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-119
COM2 Modem Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-121
COM2 Scratch Pad Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-122
Parallel Port 1 Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-123
Parallel Port 1 Status Register (PC/AT Compatible Mode). . . . . . . . . . . .2-124
Parallel Port 1 Status Register (Bidirectional Mode) . . . . . . . . . . . . . . . .2-125
Parallel Port 1 Status Register (EPP Mode) . . . . . . . . . . . . . . . . . . . . . .2-126
Parallel Port 1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-127
Parallel Port 1 EPP Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . .2-128
Parallel Port 1 EPP 32-bit Data Register . . . . . . . . . . . . . . . . . . . . . . . . .2-129
MDA/HGA Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-130
MDA/HGA Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-131
MDA/HGA Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-132
MDA/HGA Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-133
HGA Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-134
CGA Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-135
CGA Data Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-136
CGA Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-137
CGA Color Select Register 03D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-138
CGA Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-139
Primary 82365-Compatible PC Card Controller Index Register . . . . . . .2-140
Primary 82365-Compatible PC Card Controller Data Port . . . . . . . . . . .2-141
COM1 Transmit Holding Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-142
COM1 Receive Buffer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-143
COM1 Baud Clock Divisor Latch LSB. . . . . . . . . . . . . . . . . . . . . . . . . . . .2-144
COM1 Baud Clock Divisor Latch MSB . . . . . . . . . . . . . . . . . . . . . . . . . . .2-145
COM1 Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-146
COM1 Interrupt ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-147
COM1 FIFO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-148
COM1 Line Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-149
COM1 Modem Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-150
COM1 Line Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-151
COM1 Modem Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-153
Table of Contents
vi
COM1 Scratch Pad Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-154
CHAPTER 3 CHIP SETUP AND CONTROL (CSC) INDEXED REGISTERS
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
Chip Setup and Control (CSC) Index Register Map . . . . . . . . . . . . . . . . . .3-1
Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7
ÉlanSC400 Microcontroller Chip Setup and Control
(CSC) Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8
ÉlanSC400 Microcontroller Chip Setup and Control
(CSC) Data Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9
DRAM Bank 0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-10
DRAM Bank 1 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-11
DRAM Bank 2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12
DRAM Bank 3 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-13
DRAM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14
DRAM Refresh Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16
Drive Strength Control Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-17
Drive Strength Control Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-18
Non-Cacheable Window 0 Address Register . . . . . . . . . . . . . . . . . . . . . . .3-19
Non-Cacheable Window 0 Address/Attributes/SMM Register . . . . . . . . . .3-20
Non-Cacheable Window 1 Address Register . . . . . . . . . . . . . . . . . . . . . . .3-21
Non-Cacheable Window 1 Address/Attributes Register . . . . . . . . . . . . . . .3-22
Cache and VL Miscellaneous Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .3-23
Pin Strap Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-25
Linear ROMCS0/Shadow Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-26
Linear ROMCS0 Attributes Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-28
ROMCS0 Configuration Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-29
ROMCS0 Configuration Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-31
ROMCS1 Configuration Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-32
ROMCS1 Configuration Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-34
ROMCS2 Configuration Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-35
ROMCS2 Configuration Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-37
MMS Window C–F Attributes Register . . . . . . . . . . . . . . . . . . . . . . . . . . .3-38
MMS Window C–F Device Select Register . . . . . . . . . . . . . . . . . . . . . . . .3-39
MMS Window A Destination Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-40
MMS Window A Destination/Attributes Register . . . . . . . . . . . . . . . . . . . .3-41
MMS Window B Destination Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-42
MMS Window B Destination/Attributes Register . . . . . . . . . . . . . . . . . . . .3-43
Pin Mux Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-44
Pin Mux Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-45
Pin Mux Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-46
GPIO Termination Control Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-47
GPIO Termination Control Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-48
GPIO Termination Control Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-49
GPIO Termination Control Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-50
PMU Force Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-51
PMU Present and Last Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-53
Hyper/High-Speed Mode Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-54
Low-Speed/Standby Mode Timers Register . . . . . . . . . . . . . . . . . . . . . . . .3-55
Suspend/Temporary Low-Speed Mode Timers Register . . . . . . . . . . . . . .3-56
Wake-Up Pause/High-Speed Clock Timers Register . . . . . . . . . . . . . . . . .3-57
SUS_RES Pin Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-58
Wake-Up Source Enable Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-59
Wake-Up Source Enable Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-60
Wake-Up Source Enable Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-61
Wake-Up Source Enable Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-62
Wake-Up Source Status Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-63
Wake-Up Source Status Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-64
Table of Contents vii
Wake-Up Source Status Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-65
Wake-Up Source Status Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-66
GPIO as a Wake-Up or Activity Source Status Register A . . . . . . . . . . . .3-67
GPIO as a Wake-Up or Activity Source Status Register B . . . . . . . . . . . . .3-68
GP_CS Activity Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-69
GP_CS Activity Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-70
Activity Source Enable Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-71
Activity Source Enable Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-72
Activity Source Enable Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-73
Activity Source Enable Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-74
Activity Source Status Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-75
Activity Source Status Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-76
Activity Source Status Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-77
Activity Source Status Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-78
Activity Classification Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-79
Activity Classification Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-80
Activity Classification Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-81
Activity Classification Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-82
Battery/AC Pin Configuration Register A . . . . . . . . . . . . . . . . . . . . . . . . . .3-83
Battery/AC Pin Configuration Register B . . . . . . . . . . . . . . . . . . . . . . . . . .3-85
Battery/AC Pin State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-86
CPU Clock Speed Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-87
CPU Clock Auto Slowdown Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-88
Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-90
CLK_IO Pin Output Clock Select Register . . . . . . . . . . . . . . . . . . . . . . . . .3-91
Factory Debug Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-92
Factory Debug Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-93
Miscellaneous SMI/NMI Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . .3-94
PC Card and Keyboard SMI/NMI Enable Register . . . . . . . . . . . . . . . . . .3-95
Mode Timer SMI/NMI Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . .3-96
Battery Low and ACIN SMI/NMI Enable Register . . . . . . . . . . . . . . . . . . .3-97
Miscellaneous SMI/NMI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . .3-99
PC Card and Keyboard SMI/NMI Status Register . . . . . . . . . . . . . . . . . .3-100
Mode Timer SMI/NMI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . .3-101
Battery Low and ACIN SMI/NMI Status Register . . . . . . . . . . . . . . . . . . .3-102
SMI/NMI Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-104
I/O Access SMI Enable Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-105
I/O Access SMI Enable Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-106
I/O Access SMI Status Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-107
I/O Access SMI Status Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-108
XMI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-109
GPIO_CS Function Select Register A . . . . . . . . . . . . . . . . . . . . . . . . . . .3-110
GPIO_CS Function Select Register B . . . . . . . . . . . . . . . . . . . . . . . . . . .3-111
GPIO_CS Function Select Register C . . . . . . . . . . . . . . . . . . . . . . . . . . .3-112
GPIO_CS Function Select Register D . . . . . . . . . . . . . . . . . . . . . . . . . . .3-113
GPIO Function Select Register E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-114
GPIO Function Select Register F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-115
GPIO Read-Back/Write Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-116
GPIO Read-Back/Write Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-117
GPIO Read-Back/Write Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-118
GPIO Read-Back/Write Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-119
GPIO_PMUA Mode Change Register . . . . . . . . . . . . . . . . . . . . . . . . . . .3-120
GPIO_PMUB Mode Change Register . . . . . . . . . . . . . . . . . . . . . . . . . . .3-122
GPIO_PMUC Mode Change Register . . . . . . . . . . . . . . . . . . . . . . . . . . .3-124
GPIO_PMUD Mode Change Register . . . . . . . . . . . . . . . . . . . . . . . . . . .3-126
GPIO_PMU to GPIO_CS Map Register A . . . . . . . . . . . . . . . . . . . . . . . .3-128
GPIO_PMU to GPIO_CS Map Register B . . . . . . . . . . . . . . . . . . . . . . . .3-129
GPIO_XMI to GPIO_CS Map Register . . . . . . . . . . . . . . . . . . . . . . . . . .3-130
Table of Contents
viii
Standard Decode to GPIO_CS Map Register . . . . . . . . . . . . . . . . . . . . .3-131
GP_CS to GPIO_CS Map Register A . . . . . . . . . . . . . . . . . . . . . . . . . . .3-132
GP_CS to GPIO_CS Map Register B . . . . . . . . . . . . . . . . . . . . . . . . . . .3-133
GP_CSA I/O Address Decode Register . . . . . . . . . . . . . . . . . . . . . . . . . .3-134
GP_CSA I/O Address Decode and Mask Register . . . . . . . . . . . . . . . . .3-135
GP_CSB I/O Address Decode Register . . . . . . . . . . . . . . . . . . . . . . . . . .3-136
GP_CSB I/O Address Decode and Mask Register . . . . . . . . . . . . . . . . .3-137
GP_CSA/B I/O Command Qualification Register . . . . . . . . . . . . . . . . . .3-138
GP_CSC Memory Address Decode Register . . . . . . . . . . . . . . . . . . . . .3-140
GP_CSC Memory Address Decode and Mask Register . . . . . . . . . . . . .3-141
GP_CSD Memory Address Decode Register . . . . . . . . . . . . . . . . . . . . .3-142
GP_CSD Memory Address Decode and Mask Register . . . . . . . . . . . . .3-143
GP_CSC/D Memory Command Qualification Register . . . . . . . . . . . . . .3-144
Keyboard Configuration Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-146
Keyboard Configuration Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-149
Keyboard Input Buffer Read-Back Register . . . . . . . . . . . . . . . . . . . . . . .3-151
Keyboard Output Buffer Write Register . . . . . . . . . . . . . . . . . . . . . . . . . .3-152
Mouse Output Buffer Write Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-153
Keyboard Status Register Write Register . . . . . . . . . . . . . . . . . . . . . . . .3-154
Keyboard Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-155
Keyboard Column Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-156
Keyboard Row Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-158
Keyboard Row Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-160
Keyboard Column Termination Control Register . . . . . . . . . . . . . . . . . . .3-162
Internal I/O Device Disable/Echo Z-Bus Configuration Register. . . . . . . .3-164
Parallel/Serial Port Configuration Register . . . . . . . . . . . . . . . . . . . . . . .3-167
Parallel Port Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-168
UART FIFO Control Shadow Register . . . . . . . . . . . . . . . . . . . . . . . . . . .3-169
Interrupt Configuration Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-170
Interrupt Configuration Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-171
Interrupt Configuration Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-172
Interrupt Configuration Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-173
Interrupt Configuration Register E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-174
DMA Channel 0–3 Extended Page Register . . . . . . . . . . . . . . . . . . . . . .3-175
DMA Channel 5–7 Extended Page Register . . . . . . . . . . . . . . . . . . . . . .3-176
DMA Resource Channel Map Register A . . . . . . . . . . . . . . . . . . . . . . . .3-177
DMA Resource Channel Map Register B . . . . . . . . . . . . . . . . . . . . . . . .3-178
Internal Graphics Control Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-179
Internal Graphics Control Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-180
Write-protected System Memory (DRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Window/Overlapping ISA Window Enable Register . . . . . . . . . . . . . . . . .3-181
Overlapping ISA Window Start Address Register . . . . . . . . . . . . . . . . . .3-182
Overlapping ISA Window Size Register . . . . . . . . . . . . . . . . . . . . . . . . . .3-183
Suspend Pin State Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-184
Suspend Pin State Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-185
Suspend Mode Pin State Override Register . . . . . . . . . . . . . . . . . . . . . .3-186
IrDA Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-188
IrDA Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-190
IrDA CRC Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-192
IrDA Own Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-193
IrDA Frame Length Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-194
IrDA Frame Length Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-195
PC Card Extended Features Register . . . . . . . . . . . . . . . . . . . . . . . . . . .3-196
PC Card Mode and DMA Control Register . . . . . . . . . . . . . . . . . . . . . . . .3-198
PC Card Socket A/B Input Pull-Up Control Register. . . . . . . . . . . . . . . . .3-200
ÉlanSC400 Microcontroller Revision ID Register . . . . . . . . . . . . . . . . . . .3-201
Table of Contents ix
CHAPTER 4 RTC AND CMOS RAM INDEXED REGISTERS
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
RTC and CMOS RAM Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
RTC/CMOS RAM Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
RTC/CMOS RAM Data Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
RTC Current Second Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
RTC Alarm Second Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6
RTC Current Minute Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7
RTC Alarm Minute Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-8
RTC Current Hour Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-9
RTC Alarm Hour Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-10
RTC Current Day of the Week Register . . . . . . . . . . . . . . . . . . . . . . . . . . .4-11
RTC Current Day of the Month Register. . . . . . . . . . . . . . . . . . . . . . . . . . .4-12
RTC Current Month Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-13
RTC Current Year Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-14
General Purpose CMOS RAM (114 bytes). . . . . . . . . . . . . . . . . . . . . . . . .4-15
Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-16
Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-18
Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-19
Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-20
CHAPTER 5 GRAPHICS CONTROLLER INDEXED REGISTERS
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
Graphics Controller Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3
CGA/MDA Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-4
CGA/MDA Data Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-5
Cursor Start Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-6
Cursor End Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-7
Start Address High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-8
Start Address Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-9
Cursor Address High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-10
Cursor Address Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-11
Light Pen High Register (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-12
Light Pen Low Register (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-13
Horizontal Total Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-14
Horizontal Display End Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-15
Horizontal Line Pulse Start Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-16
Horizontal Border End Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-17
Non-display Lines Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-18
Vertical Adjust Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-19
Overflow Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-20
Vertical Display End Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-21
Vertical Border End Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-22
Frame Sync Delay Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-23
Dual Scan Row Adjust Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
Dual Scan Offset Address High Register . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
Dual Scan Offset Address Low Register. . . . . . . . . . . . . . . . . . . . . . . . . . 5-26
Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27
Underline Location Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
Maximum Scan Line Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
LCD Panel AC Modulation Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30
Font Table Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
Graphics Controller Grayscale Mode Register . . . . . . . . . . . . . . . . . . . . . 5-32
Graphics Controller Grayscale Remapping Register . . . . . . . . . . . . . . . . .5-34
Pixel Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36
Frame Buffer Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-37
Table of Contents
x
Font Buffer Base Address High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-38
Frame/Font Buffer Base Address Register Low . . . . . . . . . . . . . . . . . . . . 5-39
PMU Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-40
PMU Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41
Extended Feature Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-42
CHAPTER 6 PC CARD CONTROLLER INDEXED REGISTERS
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1
PC Card Controller Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1
Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-4
Primary 82365-Compatible PC Card Controller Index Register . . . . . . . . . .6-5
Primary 82365-Compatible PC Card Controller Data Port . . . . . . . . . . . . . .6-6
Identification and Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-7
Interface Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-8
Power and RESETDRV Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . .6-9
Interrupt and General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . .6-11
Card Status Change Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-12
Card Status Change Interrupt Configuration Register . . . . . . . . . . . . . . . .6-13
Address Window Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-15
PC Card Socket B Memory Window Resources Used for MMS . . . . . . . .6-15
I/O Window Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-16
I/O Window 0 Start Address Low Register . . . . . . . . . . . . . . . . . . . . . . . . .6-17
I/O Window 0 Start Address High Register. . . . . . . . . . . . . . . . . . . . . . . . .6-18
I/O Window 0 Stop Address Low Register . . . . . . . . . . . . . . . . . . . . . . . . .6-19
I/O Window 0 Stop Address High Register. . . . . . . . . . . . . . . . . . . . . . . . .6-20
I/O Window 1 Start Address Low Register . . . . . . . . . . . . . . . . . . . . . . . . .6-21
I/O Window 1 Start Address High Register. . . . . . . . . . . . . . . . . . . . . . . . .6-22
I/O Window 1 Stop Address Low Register . . . . . . . . . . . . . . . . . . . . . . . . .6-23
I/O Window 1 Stop Address High Register. . . . . . . . . . . . . . . . . . . . . . . . .6-24
Memory Window 0 Start Address Low Registe. . . . . . . . . . . . . . . . . . . . . .6-25
Memory Window 0 Start Address High Register. . . . . . . . . . . . . . . . . . . . .6-26
Memory Window 0 Stop Address Low Register . . . . . . . . . . . . . . . . . . . . .6-27
Memory Window 0 Stop Address High Register. . . . . . . . . . . . . . . . . . . . .6-28
Memory Window 0 Address Offset Low Register . . . . . . . . . . . . . . . . . . . .6-29
Memory Window 0 Address Offset High Register. . . . . . . . . . . . . . . . . . . .6-30
Memory Window 1 Start Address Low Register . . . . . . . . . . . . . . . . . . . . .6-31
Memory WIndow 1 Start Address High Register . . . . . . . . . . . . . . . . . . . .6-32
Memory Window 1 Stop Address Low Register . . . . . . . . . . . . . . . . . . . . .6-33
Memory Window 1 Stop Address High Register. . . . . . . . . . . . . . . . . . . . .6-34
Memory Window 1 Address Offset Low Register . . . . . . . . . . . . . . . . . . . .6-35
Memory Window 1 Address Offset High Register. . . . . . . . . . . . . . . . . . . .6-36
Memory Window 2 Start Address Low Register . . . . . . . . . . . . . . . . . . . . .6-37
Memory Window 2 Start Address High Register. . . . . . . . . . . . . . . . . . . . .6-38
Memory Window 2 Stop Address Low Register . . . . . . . . . . . . . . . . . . . . .6-39
Memory Window 2 Stop Address High Register. . . . . . . . . . . . . . . . . . . . .6-40
Memory Window 2 Address Offset Low Register . . . . . . . . . . . . . . . . . . . .6-41
Memory Window 2 Address Offset High Register. . . . . . . . . . . . . . . . . . . .6-42
Memory Window 3 Start Address Low Register . . . . . . . . . . . . . . . . . . . .6-43
Memory Window 3 Start Address High Register. . . . . . . . . . . . . . . . . . . . .6-44
Memory Window 3 Stop Address Low Register . . . . . . . . . . . . . . . . . . . . .6-45
Memory Window 3 Stop Address High Register. . . . . . . . . . . . . . . . . . . . .6-46
Memory Window 3 Address Offset Low Register . . . . . . . . . . . . . . . . . . .6-47
Memory Window 3 Address Offset High Register . . . . . . . . . . . . . . . . . . .6-48
Memory Window 4 Start Address Low Register . . . . . . . . . . . . . . . . . . . .6-49
Memory Window 4 Start Address High Register. . . . . . . . . . . . . . . . . . . . .6-50
Memory Window 4 Stop Address Low Register . . . . . . . . . . . . . . . . . . . . .6-51
Memory Window 4 Stop Address High Register . . . . . . . . . . . . . . . . . . . .6-52
Memory Window 4 Address Offset Low Register . . . . . . . . . . . . . . . . . . .6-53
Table of Contents xi
Memory Window 4 Address Offset High Register . . . . . . . . . . . . . . . . . . .6-54
Setup Timing 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-55
Command Timing 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-56
Recovery Timing 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-57
Setup Timing 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-58
Command Timing 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-59
Recovery Timing 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-60
Setup Timing 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-61
Command Timing 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-62
Recovery Timing 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-63
Setup Timing 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-64
Command Timing 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-65
Recovery Timing 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-66
INDEX
Table of Contents
xii
Preface xiii
PREFACE
INTRODUCTION
ÉLANSC400 MICROCONTROLLER
The ÉlanSC400 microcontroll e r is the latest in a series of E86 famil y microcontrollers
using AMD’s new Systems-i n-SiliconTM design philosophy, which integrates proven x86
CPU cores with a comprehensive set of on-chip peripherals in an advanced 0.35 micron
process.
The ÉlanSC400 microcont roller combines a 32-bit, low-voltage Am486 CPU with a
complete set of PC/AT-compatible peripherals, along with the power management features
required f or batt ery operati on. With i ts low-v oltage Am486 CPU core and ultra -small fo rm
factor, the ÉlanSC400 microcontroller is highly optimized for mobile computing applications.
PURPOSE OF THIS MANUAL
This manual includes in reference format the complete set of configuration and control
registers required to program the ÉlanSC400 microcontroller.
Intended Audie nce
This r eference manual i s intended pr imarily for programmers who are developing code for
the ÉlanSC400 microcontroller. Computer software and hardware architects and syst em
enginee rs who are designing or are considering designing systems based on the
ÉlanSC400 microcontroller may also be inter e sted in the info rmation contained in this
document. For more information on using the ÉlanSC400 micr ocontroller, see the
ÉlanSC400 Microcontroller User’s Manual
(order #21030).
Overview of This Manual
This manual is organized into the following chapters.
■Chapter 1 contains an overview of the configuration registers on the ÉlanSC400
microcontroller.
■Chapter 2 inclu des descriptions for all of the direct-mapped registers.
■Chapter 3 includes desc riptions f or the indexed ÉlanSC400 Chip Setup and Control
(CSC) register s
■Chapter 4 inclu des descriptions for the indexed Real-Time Clock and CMOS RAM
registers.
■Chapter 5 inclu des descriptions for the indexed LCD Graphics Controller registers.
■Chapter 6 inclu des descriptions for the indexed PC Card Controll er registers.
Within each chapt er, the registers are listed in ascending hexadecimal order.
Preface
xiv
RELATED DOCUMENTS
AMD Documentation
The following AMD documents provide additional information about the ÉlanSC400
microcontroller.
■The
ÉlanSC400 Microcontr oller Data Sheet
(order #21028) inc ludes complete pin li sts,
pin state tables, timing and the rmal characteristics, and package dimensions fo r the
ÉlanSC400 microcontroller .
■The
ÉlanSC400 Microcontroller User’s Manual
(order #21030) provides a functional
description of the microcontrol ler for both hardware and software desig ners.
■The
Am486 Microprocessor Software User’s Manual
(order #18497) includes the Am486
microprocessor instruction set. Appendices provide useful information about
programming the base ar chitecture and system lev e l registers, as well as describing
segmentat ion and paging on the Am486 microproce ssor. A glossary of terms is also
included. Note that this document describes floating-point features not supported on the
ÉlanSC400 microcontroller .
Other documents of interest:
■
Enhanced Am486 Microprocessor Data Sheet
(order #19225)
■
Am486DX/DX2 Microprocessor Hardware Reference Manual
(order #17965). Note that
this document describes floating-point featur es not supported on the ÉlanSC400
microcontroller.
Preface xv
DOCUMENTATION CONVENTIONS
The followi ng tabl e lists the documentati on conventions used throughout this manual.
Document atio n Conventions Table
Notation Meaning
Register Descriptions
Default Power-on reset value or value after master reset asserted
x in default register value Non-deterministic or floating; no value is guaranteed
? in default register value Determined by sources external to the ÉlanSC400
microcontroller
Shading in PC Card index
registe r bit desc ripti on Deviates from strict 83865SL compliance
Reference Notation
CSC index 00h[1] ÉlanSC400 Chip Setup and Control (CSC) indexed register 00h,
bit 1
Graphics index 00h[1] Graphics controller indexed register 00h, bit 1
PC Card index 00h[1] PC Card controller indexed register 00h, bit 1
Port 00h[1] Direct-mapped register 00h, bit 1
RTC index 00h[1] RTC and configuration RAM indexed register 00h, bit 1
Pin Naming
/ Two functions available on the pin at the same time
{ } Pin function during hardware reset
[ ] Alternative pin function selected by firmware configuration
[[ ]] Alternative pin function selected by a hardware configuration pin
state at power-on reset
ROMCS2–ROMCS0 All three ROM chip select signals
ROMCSx Any of the three ROM chip sele ct sig nals
Numbers
b Binary number
d Decimal number
Decimal is the default radix
h Hexadecimal number
x in register address Any of several legal values; e.g., 3x4h as a graphics index
address register can be either 3B4h or 3D4h, depending on the
mode selected
Preface
xvi
[X–Y, Z] The bit field that consists of bits X through Y, and the bit field
consisting of the single bit Z.
Example: Use CSC index 52h[5–3,1]
General
field Bit field in a register (one or more consecutive and related bits)
can It is possible to perform an action if properly configured
will A certain action is going to occur
XMI SMI or NMI
Set 29h[1] Write bit 1 of index 29h to 1.
Note: The applicable indexed register space will either be
obvious from the surrounding text, or will be stated explicitly. For
example, RTC index 0h[1] would be a reference to index 1 in
Real-time Clock indexed register space.
Clear 29h[1] Write bit 1 of index 29h to 0.
Note: The applicable indexed register space will either be
obvious from the surrounding text, or will be stated explicitly. For
example, RTC index 0h[1] would be a reference to index 1 in
Real-time Clock indexed register space.
Notation Meaning
Overview 1-1
CHAPTER
1OVERVIEW
This chapter provid es an overview of the di fferen t types of configur ation registers that are
documented in this manual.
1.1 CONFIGURATION REGISTERS
Configuration registers are used to read back status or to control various aspects of the
ÉlanSC400 microcontroller ’s on-board cores or peripherals. The internal configuration
registers on the ÉlanSC400 microcontroller fal l into one of five categories:
■Direct-mapped PC/AT-compati b le I/O registers
■ÉlanSC400 Chip Setup and Control (CSC) indexed registers
■Real-Time Clock (RTC) and CMOS RAM indexed registers
■LCD graphics controller indexed registers
■PC Card controlle r indexed register s
1.1.1 Direct-Mapped Configuration Registers
Direct-m apped PC/AT-compatibl e I/O registers incl ude those for the ty pical PC/AT cores,
such as t he DMA controller s, programmable int erval timer, prioriti zed interrupt c ontrollers,
parallel port, and serial port. The registers in thi s group include the industry-standard li st
of regist ers for IBM PC/AT-compatible computers which have been implemented in the
ÉlanSC400. A summary listing of these standard I/O port addr esses is shown in
Table 1-1 .
Overview
1-2
Table 1-1 Internal I/O Port Address Map Summary
Note: DMA Page register extension bits are found in Chip Setup and Control (CSC) indexed registers
D9h and DAh.
1.1.2 Indexed Configuration Registers
Four additional groups of configuration registers are indirectly accessible to the programmer
by using pair s of direc t-mapped I/ O ports. The fo ur additional groups of r egisters available
on the ÉlanSC400 microcontroller are illustrated in Figure 1-1.
All of the registers accessed through this mechanism are referred to as “indexed.” Indexing
uses direct-mapped I/O index and data ports to expand the I/O space for reading and writing
internal system registers.
■An I/O write to one of the index regi sters latc hes the index numbe r of the register to be
indirec tl y accessed.
■A subsequent I/O write to the correspo nding data port will write the regist er indexed by
the index register. Similarly, an I /O read from dat a port will read the regi ster indexed b y
the index regi ster.
■A read from an index r egister provides the l ast index value written t o that internal i ndex
latch.
An example of using indexing to access the ÉlanSC400 Chip Setup and Control (CSC)
registers is shown in Figure 1-2.
Internal I/O Device I/O Address Range
Slave DMA (DMA1) 0000–000Fh
Master Programmable Interrupt Controller
(PIC) 0020–0021h
CSC Index, Data 0022h, 0023h
Programm abl e Inter val Ti me r (PIT) 0040–004 3h
Keyboard 0060h, 0064h
System Control Port B/NMI Status 0061h
RTC Index, Data 0070h, 0071h
General 8x Registers 0080h, 0084–0086h, 0088h, 008C–008Fh
DMA Page Registers 0081–0083h, 0087h, 0089–008Bh
System Control Port A 0092h
Slave PIC 00A0–00A1h
Master DMA (DMA0) 00C0–00DEh (even addresses only)
Alternate A20 Gate Control 00EEh
Alternate CPU Reset Control 00EFh
Parallel Port LPT2 0278–027Fh
Serial Port COM2 02F8–02FFh
Parallel Port LPT1 0378–037Fh
MDA Graphics Index, Data 03B4h, 03B5h
CGA Graphics Index, Data 03D4h, 03D5h
PC Card Index, Data 03E0h, 03E1h
Serial Port COM1 03F8–03FFh
Overview 1-3
Figure 1-1 Indexed Configuration Register Space
Figure 1-2 Using the Index and Data I/O Ports to Access CSC Register Space
CSC Data
•
•
•
00h
22h
23h
CSC Index CSC Indexed
Register Space
RTC and CMOS
RAM Indexed
Register Space
Graphics Controller
Indexed Register
Space
PC Card Contro ller
Indexed Register
Space
70h
71h
RTC/RAM Index
RTC/RAM Data
3B4h
3B5h
3D4h
3D5h
3E0h
3E1h
MDA Data
MDA Index
CGA Data
CGA Index
PC Card Data
PC Card Index
Direct-Mapped I/O Ports Indexed Register Spaces
•
•
•
65h
81h
ÉlanSC400 Chip Setup and
Control (CSC) Register Space
CSC Index Port (22h)
CSC Data Port (23h)
81h 65h
64h
66h
63h
00h
•
•
•
CSC Index
CSC Data
In this e xample, the v alue of 81 h is writ-
ten to CSC index 65h.
Overview
1-4
1.1.2.1 ÉlanSC400 Chip Setup and Control (CSC) Indexed Registers
ÉlanSC400 Chip Setup and Control (CSC) regis ter s are defi ned as ÉlanSC400
microcontroller-specific registers which support features beyond standard PC/AT
compatibility requirement s (i.e., all memory cont roller and power management registers
are CSC indexed registers). The se registers are acces sed through an indexing sch eme to
limit the numbe r of direct-mapped I/O ports required.
To access the CSC register s, an I/O write to I/O port 0022h is first performed. The data
written is the index of the CSC regist er. This I/O write is followed by an I/O read or write to
port 0023h to access the data from the selected register.
The ÉlanSC400 microcontroller does not implement any locking mechanism for CSC
registe r access. Also, back-to-b ack access of I/O address 0022h/0023h is not require d for
access to the CSC indexed regi sters. For example, the following code fragment:
mov al, 90h; force an SMI
out 22h, al
mov al, 1
out 23h, al
:
:
has the same result as this code fr agment:
mov AX, 0190h; force an SMI.
out 22h, AX
1.1.2.2 RTC and CMOS RAM Indexed Registers
Real-Time Clock and CMOS RAM indexed registers are accessed using I/O ports 70h
(index) and 71h (dat a). These register s function as setup, contr ol, and status for the RTC,
as well as user CMOS RAM locations.
1.1.2.3 Graphics Control ler Indexed Regist er s
Graphics controller indexed registers are accessed using I/O ports 3D4h (index) and 3D5h
(data) for CGA mode and I/O ports 3B4h (ind ex) and 3B5h (data) for MDA mode. These
registers functi on as setup, control , and status for the LCD graphics contr oller.
1.1.2.4 PC Card Controller Indexed Registers
PC Card contr oller indexed regis ters are accessed usi ng I/O ports 3E0h (index) and 3E1h
(data). These registers function as setup, control , and status for the PC Card controller.
PC/AT-Compatible Direct-Mapped Registers 2-1
CHAPTER
2PC/AT-COMPAT IBLE
DIRECT-MAPPED REGISTERS
2.1 OVERVIEW
This chapter describes the direct-mapped registers on the ÉlanSC400 microcontroller.
These regist ers include those for the t ypical PC/AT cores, such as the DMA controllers,
programmable int erval timer, programmable interrupt controllers, parallel port, and serial
port. The regi sters in this grou p include those PC/AT compatible I/ O ports that have been
implemented in the ÉlanSC400 microcontroller. They are listed in hexadecimal order in
Table 2-1 .
The register s in this chapter are all addressed dire ctly; no indexing i s requi red. Other
control s that relate to the PC/AT legac y core functions can be found in t he Chip Setup and
Control (CSC) registers found in Chapter 3.
Table 2-1 PC/AT-Compatible Direct-Mapped Register Map
Register Name I/O (Port) Address Page Number
Slave DMA Channel 0 Memory Address Register 0000h page 2-6
Slave DMA Channel 0 Transfer Count Register 0001h page 2-7
Slave DMA Channel 1 Memory Address Register 0002h page 2-8
Slave DMA Channel 1 Transfer Count Register 0003h page 2-9
Slave DMA Channel 2 Memory Address Register 0004h page 2-10
Slave DMA Channel 2 Transfer Count Register 0005h page 2-11
Slave DMA Channel 3 Memory Address Register 0006h page 2-12
Slave DMA Channel 3 Transfer Count Register 0007h page 2-13
Slave DMA Status Register for Channels 0–3 0008h page 2-14
Slave DMA Control Register for Channels 0–3 0008h page 2-15
Slave Software DRQ(n) Request Register 0009h page 2-17
Slave DMA Mask Register Channels 0–3 000Ah page 2-18
Slave DMA Mode Register Channels 0–3 000Bh page 2-19
Slave DMA Clear Byte Pointer Register 000Ch page 2-20
Slave DMA Controller Reset Register 000Dh page 2-21
Slave DMA Controller Temporary Register 000Dh page 2-22
Slave DMA Reset Mask Register 000Eh page 2-23
Slave DMA General Mask Register 000Fh page 2-24
Master 8259 Interrupt Request Register 0020h page 2-25
Master 8259 In-Service Register 0020h page 2-26
Master 8259 Initialization Control Word 1 Register 0020h page 2-27
PC/AT-Compatible Direct-Mapped Registers
2-2
Master 8259 Operation Control Word 2 Register 0020h page 2-28
Master 8259 Operation Control Word 3 Register 0020h page 2-29
Master 8259 Initialization Control Word 2 Register 0021h page 2-30
Master 8259 Initialization Control Word 3 Register 0021h page 2-31
Master 8259 Initialization Control Word 1 Register 0021h page 2-27
Master 8259 Interrupt Mask Register (also known as
Master 8259 Operation Control Word 1 Register) 0021h page 2-33
ÉlanSC400 Mi crocon troller Ch ip Set up and C ontr ol
(CSC) Index Register 0022h page 2-34
ÉlanSC400 Microcontroller Chip Setup and Control
(CSC) Data Port 0023h page 2-35
Programmable Interval Timer #1 Channel 0 Count
Register 0040h page 2-36
Programmable Interval Timer #1 Channel 1 Count
Register 0041h page 2-37
Programmable Interval Timer #1 Channel 2 Count
Register 0042h page 2-38
Programmable Interval Timer #1 Status Byte Format 0040–0042h page 2-39
Programmable Interval Timer #1 Mode Control
Register (Mode selection) 0043h page 2-41
Programmable Interval Timer #1 Mode Control
Register (Counter latch) 0043h page 2-43
Programmable Interval Timer #1 Mode Control
Register (Read-back) 0043h page 2-44
Keyboard/Mouse Interface Output Buffer 0060h page 2-45
PC/AT Keyboard Interface Data Register 0060h page 2-46
XT Keyboard Data Register 0060h page 2-47
System Control Port B/ NMI Status Register 0061h page 2-48
Keyboard/Mouse Interface Status Register 0064h page 2-49
Keyboard/Mouse Interface Command Register 0064h page 2-51
RTC/CMOS RAM Index Register 0070h page 2-52
RTC/CMOS RAM Data Port 0071h page 2-53
General Register 0080h page 2-54
DMA Channel 2 Page Register 0081h page 2-55
DMA Channel 3 Page Register 0082h page 2-56
DMA Channel 1 Page Register 0083h page 2-57
General Registers 0084–0086h page 2-58
DMA Channel 0 Page Register 0087h page 2-61
General Register 0088h page 2-62
DMA Channel 6 Page Register 0089h page 2-63
Register Name I/O (Port) Address Page Number
PC/AT-Compatible Direct-Mapped Registers 2-3
DMA Channel 7 Page Register 008Ah page 2-64
DMA Channel 5 Page Register 008Bh page 2-65
General Registers 008C–008Fh pa g es 2- 6 6 –2 - 69
System Control Port A Register (PS/2 compatibility
port) 0092h page 2-70
Slave 8259 Interrupt Request Register 00A0h page 2-71
Slave 8259 In-Service Register 00A0h page 2-72
Slave 8259 Initialization Control Word 1 Register 00A0h page 2-73
Slave 8259 Operation Control Word 2 Register 00A0h page 2-75
Slave 8259 Operation Control Word 3 Register 00A0h page 2-76
Slave 8259 Initialization Control Word 2 Register 00A1h page 2-77
Slave 8259 Initialization Control Word 3 Register 00A1h page 2-76
Slave 8259 Initialization Control Word 4 Register 00A1h page 2-79
Slave 8259 Interrupt Mask Register
(AKA Operation Control Word 1) 00A1h page 2-80
Master DMA Channel 4 Memory Address Register 00C0h page 2-81
Master DMA Channel 4 Transfer Count Register 00C2h page 2-82
Master DMA Channel 5 Memory Address Register 00C4h page 2-83
Master DMA Channel 5 Transfer Count Register 00C6h page 2-84
Master DMA Channel 6 Memory Address Register 00C8h page 2-85
Master DMA Channel 6 Transfer Count Register 00CAh page 2-86
Master DMA Channel 7 Memory Address Register 00CCh page 2-87
Master DMA Channel 7 Transfer Count Register 00CEh page 2-88
Master DMA Status Register for Channels 4–7 00D0h page 2-89
Master DMA Control Register for Channels 4–7 00D0h page 2-90
Master Software DRQ(n) Request Register 00D2h page 2-92
Master DMA Mask Register Channels 4–7 00D4h page 2-93
Master DMA Mode Register Channels 4–7 00D6h page 2-94
Master DMA Clear Byte Pointer Register 00D8h page 2-95
Master DMA Controller Reset Register 00DAh page 2-96
Master DMA Controller Temporary Register 00DAh page 2-97
Master DMA Reset Mask Register 00DCh page 2-98
Master DMA General Mask Register 00DEh page 2-99
Alternate Gate A20 Control Port 00EEh page 2-100
Alternate CPU Reset Control Port 00EFh page 2-101
Parallel Port 2 Data Register 0278h page 2-102
Parallel Port 2 Status Register(PC/AT Compatible
mode) 0279h page 2-103
Register Name I/O (Port) Address Page Number
PC/AT-Compatible Direct-Mapped Registers
2-4
Parallel Port 2 Status Register (Bidirectional mode) 0279h page 2-104
Parallel Port 2 Status Register (EPP mode) 0279h page 2-105
Parallel Port 2 Control Register 027Ah page 2-106
Parallel Port 2 EPP Address Register 027Bh page 2-107
Parallel Port 2 EPP 32-bit Data Register 027C–027Fh page 2-108
COM2 Transmit Holding Register
(When 02FB[7] = 0, (COM2 DLAB=0) 02F8h page 2-109
COM2 Receive Buffer Register
(When 02FB[7] = 0, COM2 DLAB = 0) 02F8h page 2-110
COM2 Baud Clock Divisor Latch LSB
(When 02FB[7] = 1, COM2 DLAB =1) 02F8h page 2-111
COM2 Baud Clock Divisor Latch MSB
(When 02FB[7] = 1, COM2 DLAB =1) 02F9h page 2-112
COM2 Interrupt Enable Register
(When 02FB[7] = 0, COM2 DLAB = 0) 02F9h page 2-113
COM2 Interrupt ID Register 02FAh page 2-114
COM2 FIFO Control Register 02FAh page 2-116
COM2 Line Control Register 02FBh page 2-117
COM2 Modem Control Register 02FCh page 2-118
COM2 Line Status Register 02FDh page 2-119
COM2 Modem Status Register 02FEh page 2-121
COM2 Scratch Pad Register 02FFh page 2-122
Parallel Port 1 Data Register 0378h page 2-123
Parallel Port 1 Status Register (PC/AT Compatible
mode) 0379h page 2-124
Parallel Port 1 Status Register (Bidirectional) mode) 0379h page 2-125
Parallel Port 1 Status Register (EPP mode) 0379h page 2-126
Parallel Port 1 Control Register 037Ah page 2-127
Parallel Port 1 EPP Address Register 037Bh page 2-128
Parallel Port 1 EPP 32-bit Data Register 037C–037Fh page 2-129
MDA/HGA Index Register 03B4h page 2-130
MDA/HGA Data Port 03B5h page 2-131
MDA/HGA Mode Control Register 03B8h page 2-132
MDA/HGA Status Register 03BAh page 2-133
HGA Configuration Register 3BFh page 2-134
CGA Index Register 03D4h page 2-135
CGA Data Port 03D5h page 2-136
CGA Mode Control Register 03D8h page 2-137
CGA Color Select Register 03D9h page 2-138
Register Name I/O (Port) Address Page Number
PC/AT-Compatible Direct-Mapped Registers 2-5
2.2 REGISTER DESCRIPTIONS
Each direct-mappe d PC/AT Compatibl e register is described on the followi ng pages.
Addition al information about usi ng these registe rs to program the ÉlanSC400
microcontroller can be found in the
ÉlanSC400 User’s Manual
(order #21030).
CGA Status Register 03DAh page 2-139
Primary 82365-Compatible PC Card Controller
Index Register 03E0h page 2-140
Primary 82365-Compatible PC Card Controller Data
Port 03E1h page 2-141
COM1 Transmit Holding Register
(When 03FB[7] = 0, (COM1 DLAB =0) 03F8h page 2-142
COM1 Receive Buffer Register
(When 03FB[7] = 0, COM1 DLAB = 0) 03F8h page 2-143
COM1 Baud Clock Divisor Latch LSB
(When 03FB[7] =1, COM1 DLAB =1) 03F8h page 2-144
COM1 Baud Clock Divisor Latch MSB
(When 03FB[7] = 1, COM1 DLAB = 1) 03F9h page 2-145
COM1 Interrupt Enable Register
(When 03FB[7] = 0, COM1 DLAB = 0) 03F9h page 2-146
COM1 Interrupt ID Register 03FAh page 2-147
COM1 FIFO Control Register 03FAh page 2-148
COM1 Line Control Register 03FBh page 2-149
COM1 Modem Control Register 03FCh page 2-150
COM1 Line Status Register 03FDh page 2-151
COM1 Modem Status Register 03FDh page 2-153
COM1 Scratch Pad Register 03FFh page 2-154
Register Name I/O (Port) Address Page Number
PC/AT-Compatible Direct-Mapped Registers
2-6
Slave DMA Channel 0 Memory Ad dress Register I/O Address 0000h
Programming Notes
The ÉlanSC400 microcontroller is capable of performing 26-bit DMA accesses using the extended
DMA page registers that reside in the indexed ÉlanSC400 microcontroller registers D9h and DAh.
76543210
Bit DMA0MAR[15–0]
Default xxxxxxxx
R/W R/W
Bit Name Function
7–0 DMA0MAR[15–0] Lower 16 Bits of DMA Channel 0 Memory Address
This register is written/read via two successive I/O accesses to/from this
port (alw ays low byt e follo wed by hig h byte imme diatel y foll owin g a reset o f
the byt e poin ter at dire ct-mappe d I/O ad dress 0C h). Use i n conjun ction w ith
DMA Page Register for Channel 0 (I/O 87h) to form 24-bit memory
address.