Reference Manual - Advanced Micro Devices

ÉlanSC400 Microcontroller

Reference Manual

Rev. A, December 1996

Advanced Micro Devices reserves the right to make changes in its products

without notice in order to improve design or performance characteristics.

The information in this publication is believed to be accurate at the time of publication, but AMD makes no representations or warranties with

respect to accuracy or completeness of the contents of this publication or the information contained herein, and reserves the right to make changes

at an time, without any notice. AMD disclaims responsibility for any consequences resulting from the use of the information included in this

publication.

This publication neither states nor implies any representations or warranties of any kind, including but not limited to, any implied warranty of

merchantability or fitness for a particular purpose. AMD products are not authorized for use as critical components in life support devices or

systems without AMD’s written approval. AMD assumes no liability whatsoever for claims associated with the sale or use (including the use of

engineering samples) of AMD product except as provided in AMD’s Terms and Conditions of Sale for such product.

Trademarks

AMD, the AMD logo and combinations thereof are trademarks of Advanced Micro Devices, Inc.

Am386 and Am486 are registered trademarks, and Am186, Am188, E86, K86, Élan, Systems in Silicon, and AMD Facts-On-Demand are trade-

marks of Advanced Micro Device s, Inc. Microsoft and Windows are registered trademarks of Microsoft Corp. Product names used in this publi-

cation are for identification purposes and may be trademarks of their respective companies.

FusionE86 is a service mark of Advanced Micro Devices, Inc.

Table of Contents iii

TABLE OF CONTENTS

PREFACE INTRODUCTION

ÉlanSC400 Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii

Purpose of This Manual. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii

Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii

Overview of This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv

AMD Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv

Documentation Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xv

CHAPTER 1 OVERVIEW

Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1

Direct-Mapped Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1

Internal I/O Port Address Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2

Indexed Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2

CHAPTER 2 PC/AT-COMPATIBLE DIRECT-MAPPED REGISTERS

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1

PC/AT-Compatible Direct-Mapped Register Map . . . . . . . . . . . . . . . . . . . .2-1

Slave DMA Channel 0 Memory Address Register . . . . . . . . . . . . . . . . . . . .2-6

Slave DMA Channel 0 Transfer Count Register . . . . . . . . . . . . . . . . . . . . . .2-7

Slave DMA Channel 1 Memory Address Register . . . . . . . . . . . . . . . . . . . .2-8

Slave DMA Channel 1 Transfer Count Register . . . . . . . . . . . . . . . . . . . . . .2-9

Slave DMA Channel 2 Memory Address Register . . . . . . . . . . . . . . . . . . .2-10

Slave DMA Channel 2 Transfer Count Register . . . . . . . . . . . . . . . . . . . . .2-11

Slave DMA Channel 3 Memory Address Register . . . . . . . . . . . . . . . . . . .2-12

Slave DMA Channel 3 Transfer Count Register . . . . . . . . . . . . . . . . . . . . .2-13

Slave DMA Status Register for Channels 0–3 . . . . . . . . . . . . . . . . . . . . . .2-14

Slave DMA Control Register for Channels 0–3. . . . . . . . . . . . . . . . . . . . . .2-15

Slave Software DRQ(n) Request Register . . . . . . . . . . . . . . . . . . . . . . . . .2-17

Slave DMA Mask Register Channels 0–3. . . . . . . . . . . . . . . . . . . . . . . . . .2-18

Slave DMA Mode Register Channels 0–3 . . . . . . . . . . . . . . . . . . . . . . . . .2-19

Slave DMA Clear Byte Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . .2-20

Slave DMA Controller Reset Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-21

Slave DMA Controller Temporary Register. . . . . . . . . . . . . . . . . . . . . . . . .2-22

Slave DMA Reset Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-23

Slave DMA General Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-24

Master 8259 Interrupt Request Register. . . . . . . . . . . . . . . . . . . . . . . . . . .2-25

Master 8259 In-Service Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-26

Master 8259 Initialization Control Word 1 Register. . . . . . . . . . . . . . . . . . .2-27

Master 8259 Operation Control Word 2 Register . . . . . . . . . . . . . . . . . . . .2-28

Master 8259 Operation Control Word 3 Register . . . . . . . . . . . . . . . . . . . .2-29

Master 8259 Initialization Control Word 2 Register. . . . . . . . . . . . . . . . . . .2-30

Master 8259 Initialization Control Word 3 Register. . . . . . . . . . . . . . . . . . .2-31

Master 8259 Initialization Control Word 4 Register. . . . . . . . . . . . . . . . . . .2-32

Master 8259 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-33

ÉlanSC400 Microcontroller Chip Setup and Control

(CSC) Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-34

ÉlanSC400 Microcontroller Chip Setup and Control

(CSC) Data Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-35

Table of Contents

Programmable Interval Timer #1 Channel 0 Count

Programmable Interval Timer #1 Channel 1 Count

Programmable Interval Timer #1 Channel 2 Count

Programmable Interval Timer #1 Status Register. . . . . . . . . . . . . . . . . . . .2-39

Counter Mode Status Bits 3–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-40

Programmable Interval Timer #1 Mode Control Register . . . . . . . . . . . . . .2-41

Programmable Interval Timer #1 Counter Latch Command Register . . . .2-43

Programmable Interval Timer #1 Read-back Command Register . . . . . . .2-44

Keyboard/Mouse Interface Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . .2-45

PC/AT Keyboard Interface Data Register. . . . . . . . . . . . . . . . . . . . . . . . . .2-46

PC/XT Keyboard Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-47

System Control Port B/NMI Status Register . . . . . . . . . . . . . . . . . . . . . . . .2-48

PC/AT Keyboard/Mouse Interface Status Register . . . . . . . . . . . . . . . . . .2-49

Keyboard/Mouse Interface Command Register . . . . . . . . . . . . . . . . . . . . .2-51

RTC/CMOS RAM Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-52

RTC/CMOS RAM Data Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-53

General Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-54

DMA Channel 2 Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-55

DMA Channel 3 Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-56

DMA Channel 1 Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-57

General Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-58

General Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-59

General Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-60

DMA Channel 0 Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-61

General Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-62

DMA Channel 6 Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-63

DMA Channel 7 Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-64

DMA Channel 5 Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-65

General Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-66

General Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-67

General Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-68

General Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-69

System Control Port A Register (PS/2 Compatibility Port) . . . . . . . . . . . . .2-70

Slave 8259 Interrupt Request Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .2-71

Slave 8259 In-Service Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-72

Slave 8259 Initialization Control Word 1 Register. . . . . . . . . . . . . . . . . . . .2-73

Slave 8259 Operation Control Word 2 Register . . . . . . . . . . . . . . . . . . . . .2-75

Slave 8259 Operation Control Word 3 Register . . . . . . . . . . . . . . . . . . . . .2-76

Slave 8259 Initialization Control Word 2 Register. . . . . . . . . . . . . . . . . . . .2-77

Slave 8259 Initialization Control Word 3 Register. . . . . . . . . . . . . . . . . . . .2-78

Slave 8259 Initialization Control Word 4 Register . . . . . . . . . . . . . . . . . . .2-79

Slave 8259 Interrupt Mask Register (also known as

Operation Control Word 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-80

Master DMA Channel 4 Memory Address Register . . . . . . . . . . . . . . . . . .2-81

Master DMA Channel 4 Transfer Count Register . . . . . . . . . . . . . . . . . . . .2-82

Master DMA Channel 5 Memory Address Register . . . . . . . . . . . . . . . . . .2-83

Master DMA Channel 5 Transfer Count Register . . . . . . . . . . . . . . . . . . . .2-84

Master DMA Channel 6 Memory Address Register . . . . . . . . . . . . . . . . . .2-85

Master DMA Channel 6 Transfer Count Register . . . . . . . . . . . . . . . . . . . .2-86

Master DMA Channel 7 Memory Address Register . . . . . . . . . . . . . . . . . .2-87

Master DMA Channel 7 Transfer Count Register . . . . . . . . . . . . . . . . . . .2-88

Master DMA Status Register for Channels 4–7 . . . . . . . . . . . . . . . . . . . . .2-89

Master DMA Control Register for Channels 4–7 . . . . . . . . . . . . . . . . . . . .2-90

Master Software DRQ(n) Request Register . . . . . . . . . . . . . . . . . . . . . . . .2-92

Table of Contents v

Master DMA Mask Register Channels 4–7 . . . . . . . . . . . . . . . . . . . . . . . .2-93

Master DMA Mode Register Channels 4–7 . . . . . . . . . . . . . . . . . . . . . . . .2-94

Master DMA Clear Byte Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . .2-95

Master DMA Controller Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . .2-96

Master DMA Controller Temporary Register . . . . . . . . . . . . . . . . . . . . . . .2-97

Master DMA Reset Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-98

Master DMA General Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-99

Alternate Gate A20 Control Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-100

Alternate CPU Reset Control Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-101

Parallel Port 2 Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-102

Parallel Port 2 Status Register (PC/AT Compatible Mode). . . . . . . . . . . .2-103

Parallel Port 2 Status Register (Bidirectional Mode). . . . . . . . . . . . . . . . .2-104

Parallel Port 2 Status Register (EPP Mode) . . . . . . . . . . . . . . . . . . . . . . .2-105

Parallel Port 2 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-106

Parallel Port 2 EPP Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . .2-107

Parallel Port 2 EPP 32-bit Data Register . . . . . . . . . . . . . . . . . . . . . . . . .2-108

COM2 Transmit Holding Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-109

COM2 Receive Buffer Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-110

COM2 Baud Clock Divisor Latch LSB. . . . . . . . . . . . . . . . . . . . . . . . . . . .2-111

COM2 Baud Clock Divisor Latch MSB . . . . . . . . . . . . . . . . . . . . . . . . . . .2-112

COM2 Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-113

COM2 Interrupt ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-114

COM2 FIFO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-116

COM2 Line Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-117

COM2 Modem Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-118

COM2 Line Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-119

COM2 Modem Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-121

COM2 Scratch Pad Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-122

Parallel Port 1 Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-123

Parallel Port 1 Status Register (PC/AT Compatible Mode). . . . . . . . . . . .2-124

Parallel Port 1 Status Register (Bidirectional Mode) . . . . . . . . . . . . . . . .2-125

Parallel Port 1 Status Register (EPP Mode) . . . . . . . . . . . . . . . . . . . . . .2-126

Parallel Port 1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-127

Parallel Port 1 EPP Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . .2-128

Parallel Port 1 EPP 32-bit Data Register . . . . . . . . . . . . . . . . . . . . . . . . .2-129

MDA/HGA Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-130

MDA/HGA Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-131

MDA/HGA Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-132

MDA/HGA Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-133

HGA Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-134

CGA Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-135

CGA Data Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-136

CGA Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-137

CGA Color Select Register 03D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-138

CGA Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-139

Primary 82365-Compatible PC Card Controller Index Register . . . . . . .2-140

Primary 82365-Compatible PC Card Controller Data Port . . . . . . . . . . .2-141

COM1 Transmit Holding Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-142

COM1 Receive Buffer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-143

COM1 Baud Clock Divisor Latch LSB. . . . . . . . . . . . . . . . . . . . . . . . . . . .2-144

COM1 Baud Clock Divisor Latch MSB . . . . . . . . . . . . . . . . . . . . . . . . . . .2-145

COM1 Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-146

COM1 Interrupt ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-147

COM1 FIFO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-148

COM1 Line Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-149

COM1 Modem Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-150

COM1 Line Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-151

COM1 Modem Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-153

Table of Contents

COM1 Scratch Pad Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-154

CHAPTER 3 CHIP SETUP AND CONTROL (CSC) INDEXED REGISTERS

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1

Chip Setup and Control (CSC) Index Register Map . . . . . . . . . . . . . . . . . .3-1

ÉlanSC400 Microcontroller Chip Setup and Control

(CSC) Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8

ÉlanSC400 Microcontroller Chip Setup and Control

(CSC) Data Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9

DRAM Bank 0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-10

DRAM Bank 1 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-11

DRAM Bank 2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12

DRAM Bank 3 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-13

DRAM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14

DRAM Refresh Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16

Drive Strength Control Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-17

Drive Strength Control Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-18

Non-Cacheable Window 0 Address Register . . . . . . . . . . . . . . . . . . . . . . .3-19

Non-Cacheable Window 0 Address/Attributes/SMM Register . . . . . . . . . .3-20

Non-Cacheable Window 1 Address Register . . . . . . . . . . . . . . . . . . . . . . .3-21

Non-Cacheable Window 1 Address/Attributes Register . . . . . . . . . . . . . . .3-22

Cache and VL Miscellaneous Register. . . . . . . . . . . . . . . . . . . . . . . . . . . .3-23

Pin Strap Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-25

Linear ROMCS0/Shadow Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-26

Linear ROMCS0 Attributes Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-28

ROMCS0 Configuration Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-29

ROMCS0 Configuration Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-31

ROMCS1 Configuration Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-32

ROMCS1 Configuration Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-34

ROMCS2 Configuration Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-35

ROMCS2 Configuration Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-37

MMS Window C–F Attributes Register . . . . . . . . . . . . . . . . . . . . . . . . . . .3-38

MMS Window C–F Device Select Register . . . . . . . . . . . . . . . . . . . . . . . .3-39

MMS Window A Destination Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-40

MMS Window A Destination/Attributes Register . . . . . . . . . . . . . . . . . . . .3-41

MMS Window B Destination Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-42

MMS Window B Destination/Attributes Register . . . . . . . . . . . . . . . . . . . .3-43

Pin Mux Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-44

Pin Mux Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-45

Pin Mux Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-46

GPIO Termination Control Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-47

GPIO Termination Control Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-48

GPIO Termination Control Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-49

GPIO Termination Control Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-50

PMU Force Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-51

PMU Present and Last Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-53

Hyper/High-Speed Mode Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-54

Low-Speed/Standby Mode Timers Register . . . . . . . . . . . . . . . . . . . . . . . .3-55

Suspend/Temporary Low-Speed Mode Timers Register . . . . . . . . . . . . . .3-56

Wake-Up Pause/High-Speed Clock Timers Register . . . . . . . . . . . . . . . . .3-57

SUS_RES Pin Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-58

Wake-Up Source Enable Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-59

Wake-Up Source Enable Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-60

Wake-Up Source Enable Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-61

Wake-Up Source Enable Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-62

Wake-Up Source Status Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-63

Wake-Up Source Status Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-64

Table of Contents vii

Wake-Up Source Status Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-65

Wake-Up Source Status Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-66

GPIO as a Wake-Up or Activity Source Status Register A . . . . . . . . . . . .3-67

GPIO as a Wake-Up or Activity Source Status Register B . . . . . . . . . . . . .3-68

GP_CS Activity Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-69

GP_CS Activity Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-70

Activity Source Enable Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-71

Activity Source Enable Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-72

Activity Source Enable Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-73

Activity Source Enable Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-74

Activity Source Status Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-75

Activity Source Status Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-76

Activity Source Status Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-77

Activity Source Status Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-78

Activity Classification Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-79

Activity Classification Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-80

Activity Classification Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-81

Activity Classification Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-82

Battery/AC Pin Configuration Register A . . . . . . . . . . . . . . . . . . . . . . . . . .3-83

Battery/AC Pin Configuration Register B . . . . . . . . . . . . . . . . . . . . . . . . . .3-85

Battery/AC Pin State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-86

CPU Clock Speed Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-87

CPU Clock Auto Slowdown Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-88

Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-90

CLK_IO Pin Output Clock Select Register . . . . . . . . . . . . . . . . . . . . . . . . .3-91

Factory Debug Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-92

Factory Debug Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-93

Miscellaneous SMI/NMI Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . .3-94

PC Card and Keyboard SMI/NMI Enable Register . . . . . . . . . . . . . . . . . .3-95

Mode Timer SMI/NMI Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . .3-96

Battery Low and ACIN SMI/NMI Enable Register . . . . . . . . . . . . . . . . . . .3-97

Miscellaneous SMI/NMI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . .3-99

PC Card and Keyboard SMI/NMI Status Register . . . . . . . . . . . . . . . . . .3-100

Mode Timer SMI/NMI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . .3-101

Battery Low and ACIN SMI/NMI Status Register . . . . . . . . . . . . . . . . . . .3-102

SMI/NMI Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-104

I/O Access SMI Enable Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-105

I/O Access SMI Enable Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-106

I/O Access SMI Status Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-107

I/O Access SMI Status Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-108

XMI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-109

GPIO_CS Function Select Register A . . . . . . . . . . . . . . . . . . . . . . . . . . .3-110

GPIO_CS Function Select Register B . . . . . . . . . . . . . . . . . . . . . . . . . . .3-111

GPIO_CS Function Select Register C . . . . . . . . . . . . . . . . . . . . . . . . . . .3-112

GPIO_CS Function Select Register D . . . . . . . . . . . . . . . . . . . . . . . . . . .3-113

GPIO Function Select Register E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-114

GPIO Function Select Register F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-115

GPIO Read-Back/Write Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-116

GPIO Read-Back/Write Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-117

GPIO Read-Back/Write Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-118

GPIO Read-Back/Write Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-119

GPIO_PMUA Mode Change Register . . . . . . . . . . . . . . . . . . . . . . . . . . .3-120

GPIO_PMUB Mode Change Register . . . . . . . . . . . . . . . . . . . . . . . . . . .3-122

GPIO_PMUC Mode Change Register . . . . . . . . . . . . . . . . . . . . . . . . . . .3-124

GPIO_PMUD Mode Change Register . . . . . . . . . . . . . . . . . . . . . . . . . . .3-126

GPIO_PMU to GPIO_CS Map Register A . . . . . . . . . . . . . . . . . . . . . . . .3-128

GPIO_PMU to GPIO_CS Map Register B . . . . . . . . . . . . . . . . . . . . . . . .3-129

GPIO_XMI to GPIO_CS Map Register . . . . . . . . . . . . . . . . . . . . . . . . . .3-130

Table of Contents

viii

Standard Decode to GPIO_CS Map Register . . . . . . . . . . . . . . . . . . . . .3-131

GP_CS to GPIO_CS Map Register A . . . . . . . . . . . . . . . . . . . . . . . . . . .3-132

GP_CS to GPIO_CS Map Register B . . . . . . . . . . . . . . . . . . . . . . . . . . .3-133

GP_CSA I/O Address Decode Register . . . . . . . . . . . . . . . . . . . . . . . . . .3-134

GP_CSA I/O Address Decode and Mask Register . . . . . . . . . . . . . . . . .3-135

GP_CSB I/O Address Decode Register . . . . . . . . . . . . . . . . . . . . . . . . . .3-136

GP_CSB I/O Address Decode and Mask Register . . . . . . . . . . . . . . . . .3-137

GP_CSA/B I/O Command Qualification Register . . . . . . . . . . . . . . . . . .3-138

GP_CSC Memory Address Decode Register . . . . . . . . . . . . . . . . . . . . .3-140

GP_CSC Memory Address Decode and Mask Register . . . . . . . . . . . . .3-141

GP_CSD Memory Address Decode Register . . . . . . . . . . . . . . . . . . . . .3-142

GP_CSD Memory Address Decode and Mask Register . . . . . . . . . . . . .3-143

GP_CSC/D Memory Command Qualification Register . . . . . . . . . . . . . .3-144

Keyboard Configuration Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-146

Keyboard Configuration Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-149

Keyboard Input Buffer Read-Back Register . . . . . . . . . . . . . . . . . . . . . . .3-151

Keyboard Output Buffer Write Register . . . . . . . . . . . . . . . . . . . . . . . . . .3-152

Mouse Output Buffer Write Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-153

Keyboard Status Register Write Register . . . . . . . . . . . . . . . . . . . . . . . .3-154

Keyboard Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-155

Keyboard Column Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-156

Keyboard Row Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-158

Keyboard Row Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-160

Keyboard Column Termination Control Register . . . . . . . . . . . . . . . . . . .3-162

Internal I/O Device Disable/Echo Z-Bus Configuration Register. . . . . . . .3-164

Parallel/Serial Port Configuration Register . . . . . . . . . . . . . . . . . . . . . . .3-167

Parallel Port Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-168

UART FIFO Control Shadow Register . . . . . . . . . . . . . . . . . . . . . . . . . . .3-169

Interrupt Configuration Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-170

Interrupt Configuration Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-171

Interrupt Configuration Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-172

Interrupt Configuration Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-173

Interrupt Configuration Register E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-174

DMA Channel 0–3 Extended Page Register . . . . . . . . . . . . . . . . . . . . . .3-175

DMA Channel 5–7 Extended Page Register . . . . . . . . . . . . . . . . . . . . . .3-176

DMA Resource Channel Map Register A . . . . . . . . . . . . . . . . . . . . . . . .3-177

DMA Resource Channel Map Register B . . . . . . . . . . . . . . . . . . . . . . . .3-178

Internal Graphics Control Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-179

Internal Graphics Control Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-180

Write-protected System Memory (DRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Window/Overlapping ISA Window Enable Register . . . . . . . . . . . . . . . . .3-181

Overlapping ISA Window Start Address Register . . . . . . . . . . . . . . . . . .3-182

Overlapping ISA Window Size Register . . . . . . . . . . . . . . . . . . . . . . . . . .3-183

Suspend Pin State Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-184

Suspend Pin State Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-185

Suspend Mode Pin State Override Register . . . . . . . . . . . . . . . . . . . . . .3-186

IrDA Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-188

IrDA Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-190

IrDA CRC Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-192

IrDA Own Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-193

IrDA Frame Length Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-194

IrDA Frame Length Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-195

PC Card Extended Features Register . . . . . . . . . . . . . . . . . . . . . . . . . . .3-196

PC Card Mode and DMA Control Register . . . . . . . . . . . . . . . . . . . . . . . .3-198

PC Card Socket A/B Input Pull-Up Control Register. . . . . . . . . . . . . . . . .3-200

ÉlanSC400 Microcontroller Revision ID Register . . . . . . . . . . . . . . . . . . .3-201

Table of Contents ix

CHAPTER 4 RTC AND CMOS RAM INDEXED REGISTERS

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1

RTC and CMOS RAM Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1

RTC/CMOS RAM Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3

RTC/CMOS RAM Data Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4

RTC Current Second Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5

RTC Alarm Second Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6

RTC Current Minute Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7

RTC Alarm Minute Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-8

RTC Current Hour Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-9

RTC Alarm Hour Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-10

RTC Current Day of the Week Register . . . . . . . . . . . . . . . . . . . . . . . . . . .4-11

RTC Current Day of the Month Register. . . . . . . . . . . . . . . . . . . . . . . . . . .4-12

RTC Current Month Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-13

RTC Current Year Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-14

General Purpose CMOS RAM (114 bytes). . . . . . . . . . . . . . . . . . . . . . . . .4-15

CHAPTER 5 GRAPHICS CONTROLLER INDEXED REGISTERS

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1

Graphics Controller Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1

CGA/MDA Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-4

CGA/MDA Data Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-5

Cursor Start Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-6

Cursor End Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-7

Start Address High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-8

Start Address Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-9

Cursor Address High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-10

Cursor Address Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-11

Light Pen High Register (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-12

Light Pen Low Register (Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-13

Horizontal Total Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-14

Horizontal Display End Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-15

Horizontal Line Pulse Start Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-16

Horizontal Border End Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-17

Non-display Lines Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-18

Vertical Adjust Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-19

Overflow Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-20

Vertical Display End Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-21

Vertical Border End Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-22

Frame Sync Delay Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-23

Dual Scan Row Adjust Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24

Dual Scan Offset Address High Register . . . . . . . . . . . . . . . . . . . . . . . . . 5-25

Dual Scan Offset Address Low Register. . . . . . . . . . . . . . . . . . . . . . . . . . 5-26

Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27

Underline Location Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28

Maximum Scan Line Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29

LCD Panel AC Modulation Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30

Font Table Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31

Graphics Controller Grayscale Mode Register . . . . . . . . . . . . . . . . . . . . . 5-32

Graphics Controller Grayscale Remapping Register . . . . . . . . . . . . . . . . .5-34

Pixel Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36

Frame Buffer Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-37

Table of Contents

Font Buffer Base Address High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-38

Frame/Font Buffer Base Address Register Low . . . . . . . . . . . . . . . . . . . . 5-39

PMU Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-40

PMU Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41

Extended Feature Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-42

CHAPTER 6 PC CARD CONTROLLER INDEXED REGISTERS

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1

PC Card Controller Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1

Primary 82365-Compatible PC Card Controller Index Register . . . . . . . . . .6-5

Primary 82365-Compatible PC Card Controller Data Port . . . . . . . . . . . . . .6-6

Identification and Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-7

Interface Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-8

Power and RESETDRV Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . .6-9

Interrupt and General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . .6-11

Card Status Change Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-12

Card Status Change Interrupt Configuration Register . . . . . . . . . . . . . . . .6-13

Address Window Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-15

PC Card Socket B Memory Window Resources Used for MMS . . . . . . . .6-15

I/O Window Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-16

I/O Window 0 Start Address Low Register . . . . . . . . . . . . . . . . . . . . . . . . .6-17

I/O Window 0 Start Address High Register. . . . . . . . . . . . . . . . . . . . . . . . .6-18

I/O Window 0 Stop Address Low Register . . . . . . . . . . . . . . . . . . . . . . . . .6-19

I/O Window 0 Stop Address High Register. . . . . . . . . . . . . . . . . . . . . . . . .6-20

I/O Window 1 Start Address Low Register . . . . . . . . . . . . . . . . . . . . . . . . .6-21

I/O Window 1 Start Address High Register. . . . . . . . . . . . . . . . . . . . . . . . .6-22

I/O Window 1 Stop Address Low Register . . . . . . . . . . . . . . . . . . . . . . . . .6-23

I/O Window 1 Stop Address High Register. . . . . . . . . . . . . . . . . . . . . . . . .6-24

Memory Window 0 Start Address Low Registe. . . . . . . . . . . . . . . . . . . . . .6-25

Memory Window 0 Start Address High Register. . . . . . . . . . . . . . . . . . . . .6-26

Memory Window 0 Stop Address Low Register . . . . . . . . . . . . . . . . . . . . .6-27

Memory Window 0 Stop Address High Register. . . . . . . . . . . . . . . . . . . . .6-28

Memory Window 0 Address Offset Low Register . . . . . . . . . . . . . . . . . . . .6-29

Memory Window 0 Address Offset High Register. . . . . . . . . . . . . . . . . . . .6-30

Memory Window 1 Start Address Low Register . . . . . . . . . . . . . . . . . . . . .6-31

Memory WIndow 1 Start Address High Register . . . . . . . . . . . . . . . . . . . .6-32

Memory Window 1 Stop Address Low Register . . . . . . . . . . . . . . . . . . . . .6-33

Memory Window 1 Stop Address High Register. . . . . . . . . . . . . . . . . . . . .6-34

Memory Window 1 Address Offset Low Register . . . . . . . . . . . . . . . . . . . .6-35

Memory Window 1 Address Offset High Register. . . . . . . . . . . . . . . . . . . .6-36

Memory Window 2 Start Address Low Register . . . . . . . . . . . . . . . . . . . . .6-37

Memory Window 2 Start Address High Register. . . . . . . . . . . . . . . . . . . . .6-38

Memory Window 2 Stop Address Low Register . . . . . . . . . . . . . . . . . . . . .6-39

Memory Window 2 Stop Address High Register. . . . . . . . . . . . . . . . . . . . .6-40

Memory Window 2 Address Offset Low Register . . . . . . . . . . . . . . . . . . . .6-41

Memory Window 2 Address Offset High Register. . . . . . . . . . . . . . . . . . . .6-42

Memory Window 3 Start Address Low Register . . . . . . . . . . . . . . . . . . . .6-43

Memory Window 3 Start Address High Register. . . . . . . . . . . . . . . . . . . . .6-44

Memory Window 3 Stop Address Low Register . . . . . . . . . . . . . . . . . . . . .6-45

Memory Window 3 Stop Address High Register. . . . . . . . . . . . . . . . . . . . .6-46

Memory Window 3 Address Offset Low Register . . . . . . . . . . . . . . . . . . .6-47

Memory Window 3 Address Offset High Register . . . . . . . . . . . . . . . . . . .6-48

Memory Window 4 Start Address Low Register . . . . . . . . . . . . . . . . . . . .6-49

Memory Window 4 Start Address High Register. . . . . . . . . . . . . . . . . . . . .6-50

Memory Window 4 Stop Address Low Register . . . . . . . . . . . . . . . . . . . . .6-51

Memory Window 4 Stop Address High Register . . . . . . . . . . . . . . . . . . . .6-52

Memory Window 4 Address Offset Low Register . . . . . . . . . . . . . . . . . . .6-53

Table of Contents xi

Memory Window 4 Address Offset High Register . . . . . . . . . . . . . . . . . . .6-54

Setup Timing 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-55

Command Timing 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-56

Recovery Timing 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-57

Setup Timing 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-58

Command Timing 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-59

Recovery Timing 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-60

Setup Timing 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-61

Command Timing 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-62

Recovery Timing 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-63

Setup Timing 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-64

Command Timing 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-65

Recovery Timing 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-66

INDEX

Table of Contents

xii

Preface xiii

PREFACE

INTRODUCTION

ÉLANSC400 MICROCONTROLLER

The ÉlanSC400 microcontroll e r is the latest in a series of E86 famil y microcontrollers

using AMD’s new Systems-i n-SiliconTM design philosophy, which integrates proven x86

CPU cores with a comprehensive set of on-chip peripherals in an advanced 0.35 micron

process.

The ÉlanSC400 microcont roller combines a 32-bit, low-voltage Am486 CPU with a

complete set of PC/AT-compatible peripherals, along with the power management features

required f or batt ery operati on. With i ts low-v oltage Am486 CPU core and ultra -small fo rm

factor, the ÉlanSC400 microcontroller is highly optimized for mobile computing applications.

PURPOSE OF THIS MANUAL

This manual includes in reference format the complete set of configuration and control

registers required to program the ÉlanSC400 microcontroller.

Intended Audie nce

This r eference manual i s intended pr imarily for programmers who are developing code for

the ÉlanSC400 microcontroller. Computer software and hardware architects and syst em

enginee rs who are designing or are considering designing systems based on the

ÉlanSC400 microcontroller may also be inter e sted in the info rmation contained in this

document. For more information on using the ÉlanSC400 micr ocontroller, see the

ÉlanSC400 Microcontroller User’s Manual

(order #21030).

Overview of This Manual

This manual is organized into the following chapters.

■Chapter 1 contains an overview of the configuration registers on the ÉlanSC400

microcontroller.

■Chapter 2 inclu des descriptions for all of the direct-mapped registers.

■Chapter 3 includes desc riptions f or the indexed ÉlanSC400 Chip Setup and Control

(CSC) register s

■Chapter 4 inclu des descriptions for the indexed Real-Time Clock and CMOS RAM

registers.

■Chapter 5 inclu des descriptions for the indexed LCD Graphics Controller registers.

■Chapter 6 inclu des descriptions for the indexed PC Card Controll er registers.

Within each chapt er, the registers are listed in ascending hexadecimal order.

Preface

xiv

Other documents of interest:

■

Enhanced Am486 Microprocessor Data Sheet

(order #19225)

■

Am486DX/DX2 Microprocessor Hardware Reference Manual

(order #17965). Note that

this document describes floating-point featur es not supported on the ÉlanSC400

microcontroller.

Preface xv

DOCUMENTATION CONVENTIONS

The followi ng tabl e lists the documentati on conventions used throughout this manual.

Document atio n Conventions Table

Notation Meaning

Default Power-on reset value or value after master reset asserted

x in default register value Non-deterministic or floating; no value is guaranteed

? in default register value Determined by sources external to the ÉlanSC400

microcontroller

Shading in PC Card index

registe r bit desc ripti on Deviates from strict 83865SL compliance

Reference Notation

CSC index 00h[1] ÉlanSC400 Chip Setup and Control (CSC) indexed register 00h,

bit 1

Graphics index 00h[1] Graphics controller indexed register 00h, bit 1

PC Card index 00h[1] PC Card controller indexed register 00h, bit 1

Port 00h[1] Direct-mapped register 00h, bit 1

RTC index 00h[1] RTC and configuration RAM indexed register 00h, bit 1

Pin Naming

/ Two functions available on the pin at the same time

{ } Pin function during hardware reset

[ ] Alternative pin function selected by firmware configuration

[[ ]] Alternative pin function selected by a hardware configuration pin

state at power-on reset

ROMCS2–ROMCS0 All three ROM chip select signals

ROMCSx Any of the three ROM chip sele ct sig nals

Numbers

b Binary number

d Decimal number

Decimal is the default radix

h Hexadecimal number

x in register address Any of several legal values; e.g., 3x4h as a graphics index

address register can be either 3B4h or 3D4h, depending on the

mode selected

Preface

xvi

[X–Y, Z] The bit field that consists of bits X through Y, and the bit field

consisting of the single bit Z.

Example: Use CSC index 52h[5–3,1]

General

field Bit field in a register (one or more consecutive and related bits)

can It is possible to perform an action if properly configured

will A certain action is going to occur

XMI SMI or NMI

Set 29h[1] Write bit 1 of index 29h to 1.

Note: The applicable indexed register space will either be

obvious from the surrounding text, or will be stated explicitly. For

example, RTC index 0h[1] would be a reference to index 1 in

Real-time Clock indexed register space.

Clear 29h[1] Write bit 1 of index 29h to 0.

Note: The applicable indexed register space will either be

obvious from the surrounding text, or will be stated explicitly. For

example, RTC index 0h[1] would be a reference to index 1 in

Real-time Clock indexed register space.

Notation Meaning

Overview 1-1

CHAPTER

1OVERVIEW

This chapter provid es an overview of the di fferen t types of configur ation registers that are

documented in this manual.

1.1 CONFIGURATION REGISTERS

Configuration registers are used to read back status or to control various aspects of the

ÉlanSC400 microcontroller ’s on-board cores or peripherals. The internal configuration

registers on the ÉlanSC400 microcontroller fal l into one of five categories:

■Direct-mapped PC/AT-compati b le I/O registers

■ÉlanSC400 Chip Setup and Control (CSC) indexed registers

■Real-Time Clock (RTC) and CMOS RAM indexed registers

■LCD graphics controller indexed registers

■PC Card controlle r indexed register s

1.1.1 Direct-Mapped Configuration Registers

Direct-m apped PC/AT-compatibl e I/O registers incl ude those for the ty pical PC/AT cores,

such as t he DMA controller s, programmable int erval timer, prioriti zed interrupt c ontrollers,

parallel port, and serial port. The registers in thi s group include the industry-standard li st

of regist ers for IBM PC/AT-compatible computers which have been implemented in the

ÉlanSC400. A summary listing of these standard I/O port addr esses is shown in

Table 1-1 .

Overview

1-2

Table 1-1 Internal I/O Port Address Map Summary

Note: DMA Page register extension bits are found in Chip Setup and Control (CSC) indexed registers

D9h and DAh.

1.1.2 Indexed Configuration Registers

Four additional groups of configuration registers are indirectly accessible to the programmer

by using pair s of direc t-mapped I/ O ports. The fo ur additional groups of r egisters available

on the ÉlanSC400 microcontroller are illustrated in Figure 1-1.

All of the registers accessed through this mechanism are referred to as “indexed.” Indexing

uses direct-mapped I/O index and data ports to expand the I/O space for reading and writing

internal system registers.

■An I/O write to one of the index regi sters latc hes the index numbe r of the register to be

indirec tl y accessed.

■A subsequent I/O write to the correspo nding data port will write the regist er indexed by

the index register. Similarly, an I /O read from dat a port will read the regi ster indexed b y

the index regi ster.

■A read from an index r egister provides the l ast index value written t o that internal i ndex

latch.

An example of using indexing to access the ÉlanSC400 Chip Setup and Control (CSC)

registers is shown in Figure 1-2.

Internal I/O Device I/O Address Range

Slave DMA (DMA1) 0000–000Fh

Master Programmable Interrupt Controller

(PIC) 0020–0021h

CSC Index, Data 0022h, 0023h

Programm abl e Inter val Ti me r (PIT) 0040–004 3h

Keyboard 0060h, 0064h

System Control Port B/NMI Status 0061h

RTC Index, Data 0070h, 0071h

General 8x Registers 0080h, 0084–0086h, 0088h, 008C–008Fh

DMA Page Registers 0081–0083h, 0087h, 0089–008Bh

System Control Port A 0092h

Slave PIC 00A0–00A1h

Master DMA (DMA0) 00C0–00DEh (even addresses only)

Alternate A20 Gate Control 00EEh

Alternate CPU Reset Control 00EFh

Parallel Port LPT2 0278–027Fh

Serial Port COM2 02F8–02FFh

Parallel Port LPT1 0378–037Fh

MDA Graphics Index, Data 03B4h, 03B5h

CGA Graphics Index, Data 03D4h, 03D5h

PC Card Index, Data 03E0h, 03E1h

Serial Port COM1 03F8–03FFh

Overview 1-3

Figure 1-1 Indexed Configuration Register Space

Figure 1-2 Using the Index and Data I/O Ports to Access CSC Register Space

CSC Data

•

00h

22h

23h

CSC Index CSC Indexed

RTC and CMOS

RAM Indexed

Graphics Controller

Indexed Register

Space

PC Card Contro ller

Indexed Register

Space

70h

71h

RTC/RAM Index

RTC/RAM Data

3B4h

3B5h

3D4h

3D5h

3E0h

3E1h

MDA Data

MDA Index

CGA Data

CGA Index

PC Card Data

PC Card Index

Direct-Mapped I/O Ports Indexed Register Spaces

•

65h

81h

ÉlanSC400 Chip Setup and

Control (CSC) Register Space

CSC Index Port (22h)

CSC Data Port (23h)

81h 65h

64h

66h

63h

00h

•

CSC Index

CSC Data

In this e xample, the v alue of 81 h is writ-

ten to CSC index 65h.

Overview

1-4

1.1.2.1 ÉlanSC400 Chip Setup and Control (CSC) Indexed Registers

ÉlanSC400 Chip Setup and Control (CSC) regis ter s are defi ned as ÉlanSC400

microcontroller-specific registers which support features beyond standard PC/AT

compatibility requirement s (i.e., all memory cont roller and power management registers

are CSC indexed registers). The se registers are acces sed through an indexing sch eme to

limit the numbe r of direct-mapped I/O ports required.

To access the CSC register s, an I/O write to I/O port 0022h is first performed. The data

written is the index of the CSC regist er. This I/O write is followed by an I/O read or write to

port 0023h to access the data from the selected register.

The ÉlanSC400 microcontroller does not implement any locking mechanism for CSC

registe r access. Also, back-to-b ack access of I/O address 0022h/0023h is not require d for

access to the CSC indexed regi sters. For example, the following code fragment:

mov al, 90h; force an SMI

out 22h, al

mov al, 1

out 23h, al

has the same result as this code fr agment:

mov AX, 0190h; force an SMI.

out 22h, AX

1.1.2.2 RTC and CMOS RAM Indexed Registers

Real-Time Clock and CMOS RAM indexed registers are accessed using I/O ports 70h

(index) and 71h (dat a). These register s function as setup, contr ol, and status for the RTC,

as well as user CMOS RAM locations.

1.1.2.3 Graphics Control ler Indexed Regist er s

Graphics controller indexed registers are accessed using I/O ports 3D4h (index) and 3D5h

(data) for CGA mode and I/O ports 3B4h (ind ex) and 3B5h (data) for MDA mode. These

registers functi on as setup, control , and status for the LCD graphics contr oller.

1.1.2.4 PC Card Controller Indexed Registers

PC Card contr oller indexed regis ters are accessed usi ng I/O ports 3E0h (index) and 3E1h

(data). These registers function as setup, control , and status for the PC Card controller.

PC/AT-Compatible Direct-Mapped Registers 2-1

CHAPTER

2PC/AT-COMPAT IBLE

DIRECT-MAPPED REGISTERS

2.1 OVERVIEW

This chapter describes the direct-mapped registers on the ÉlanSC400 microcontroller.

These regist ers include those for the t ypical PC/AT cores, such as the DMA controllers,

programmable int erval timer, programmable interrupt controllers, parallel port, and serial

port. The regi sters in this grou p include those PC/AT compatible I/ O ports that have been

implemented in the ÉlanSC400 microcontroller. They are listed in hexadecimal order in

Table 2-1 .

The register s in this chapter are all addressed dire ctly; no indexing i s requi red. Other

control s that relate to the PC/AT legac y core functions can be found in t he Chip Setup and

Control (CSC) registers found in Chapter 3.

Table 2-1 PC/AT-Compatible Direct-Mapped Register Map

Slave DMA Channel 0 Memory Address Register 0000h page 2-6

Slave DMA Channel 0 Transfer Count Register 0001h page 2-7

Slave DMA Channel 1 Memory Address Register 0002h page 2-8

Slave DMA Channel 1 Transfer Count Register 0003h page 2-9

Slave DMA Channel 2 Memory Address Register 0004h page 2-10

Slave DMA Channel 2 Transfer Count Register 0005h page 2-11

Slave DMA Channel 3 Memory Address Register 0006h page 2-12

Slave DMA Channel 3 Transfer Count Register 0007h page 2-13

Slave DMA Status Register for Channels 0–3 0008h page 2-14

Slave DMA Control Register for Channels 0–3 0008h page 2-15

Slave Software DRQ(n) Request Register 0009h page 2-17

Slave DMA Mask Register Channels 0–3 000Ah page 2-18

Slave DMA Mode Register Channels 0–3 000Bh page 2-19

Slave DMA Clear Byte Pointer Register 000Ch page 2-20

Slave DMA Controller Reset Register 000Dh page 2-21

Slave DMA Controller Temporary Register 000Dh page 2-22

Slave DMA Reset Mask Register 000Eh page 2-23

Slave DMA General Mask Register 000Fh page 2-24

Master 8259 Interrupt Request Register 0020h page 2-25

Master 8259 In-Service Register 0020h page 2-26

Master 8259 Initialization Control Word 1 Register 0020h page 2-27

PC/AT-Compatible Direct-Mapped Registers

2-2

Master 8259 Operation Control Word 2 Register 0020h page 2-28

Master 8259 Operation Control Word 3 Register 0020h page 2-29

Master 8259 Initialization Control Word 2 Register 0021h page 2-30

Master 8259 Initialization Control Word 3 Register 0021h page 2-31

Master 8259 Initialization Control Word 1 Register 0021h page 2-27

Master 8259 Interrupt Mask Register (also known as

Master 8259 Operation Control Word 1 Register) 0021h page 2-33

ÉlanSC400 Mi crocon troller Ch ip Set up and C ontr ol

(CSC) Index Register 0022h page 2-34

ÉlanSC400 Microcontroller Chip Setup and Control

(CSC) Data Port 0023h page 2-35

Programmable Interval Timer #1 Channel 0 Count

Programmable Interval Timer #1 Channel 1 Count

Programmable Interval Timer #1 Channel 2 Count

Programmable Interval Timer #1 Status Byte Format 0040–0042h page 2-39

Programmable Interval Timer #1 Mode Control

Keyboard/Mouse Interface Output Buffer 0060h page 2-45

PC/AT Keyboard Interface Data Register 0060h page 2-46

XT Keyboard Data Register 0060h page 2-47

System Control Port B/ NMI Status Register 0061h page 2-48

Keyboard/Mouse Interface Status Register 0064h page 2-49

Keyboard/Mouse Interface Command Register 0064h page 2-51

RTC/CMOS RAM Index Register 0070h page 2-52

RTC/CMOS RAM Data Port 0071h page 2-53

General Register 0080h page 2-54

DMA Channel 2 Page Register 0081h page 2-55

DMA Channel 3 Page Register 0082h page 2-56

DMA Channel 1 Page Register 0083h page 2-57

General Registers 0084–0086h page 2-58

DMA Channel 0 Page Register 0087h page 2-61

General Register 0088h page 2-62

DMA Channel 6 Page Register 0089h page 2-63

PC/AT-Compatible Direct-Mapped Registers 2-3

DMA Channel 7 Page Register 008Ah page 2-64

DMA Channel 5 Page Register 008Bh page 2-65

General Registers 008C–008Fh pa g es 2- 6 6 –2 - 69

System Control Port A Register (PS/2 compatibility

port) 0092h page 2-70

Slave 8259 Interrupt Request Register 00A0h page 2-71

Slave 8259 In-Service Register 00A0h page 2-72

Slave 8259 Initialization Control Word 1 Register 00A0h page 2-73

Slave 8259 Operation Control Word 2 Register 00A0h page 2-75

Slave 8259 Operation Control Word 3 Register 00A0h page 2-76

Slave 8259 Initialization Control Word 2 Register 00A1h page 2-77

Slave 8259 Initialization Control Word 3 Register 00A1h page 2-76

Slave 8259 Initialization Control Word 4 Register 00A1h page 2-79

Slave 8259 Interrupt Mask Register

(AKA Operation Control Word 1) 00A1h page 2-80

Master DMA Channel 4 Memory Address Register 00C0h page 2-81

Master DMA Channel 4 Transfer Count Register 00C2h page 2-82

Master DMA Channel 5 Memory Address Register 00C4h page 2-83

Master DMA Channel 5 Transfer Count Register 00C6h page 2-84

Master DMA Channel 6 Memory Address Register 00C8h page 2-85

Master DMA Channel 6 Transfer Count Register 00CAh page 2-86

Master DMA Channel 7 Memory Address Register 00CCh page 2-87

Master DMA Channel 7 Transfer Count Register 00CEh page 2-88

Master DMA Status Register for Channels 4–7 00D0h page 2-89

Master DMA Control Register for Channels 4–7 00D0h page 2-90

Master Software DRQ(n) Request Register 00D2h page 2-92

Master DMA Mask Register Channels 4–7 00D4h page 2-93

Master DMA Mode Register Channels 4–7 00D6h page 2-94

Master DMA Clear Byte Pointer Register 00D8h page 2-95

Master DMA Controller Reset Register 00DAh page 2-96

Master DMA Controller Temporary Register 00DAh page 2-97

Master DMA Reset Mask Register 00DCh page 2-98

Master DMA General Mask Register 00DEh page 2-99

Alternate Gate A20 Control Port 00EEh page 2-100

Alternate CPU Reset Control Port 00EFh page 2-101

Parallel Port 2 Data Register 0278h page 2-102

Parallel Port 2 Status Register(PC/AT Compatible

mode) 0279h page 2-103

PC/AT-Compatible Direct-Mapped Registers

2-4

Parallel Port 2 Status Register (Bidirectional mode) 0279h page 2-104

Parallel Port 2 Status Register (EPP mode) 0279h page 2-105

Parallel Port 2 Control Register 027Ah page 2-106

Parallel Port 2 EPP Address Register 027Bh page 2-107

Parallel Port 2 EPP 32-bit Data Register 027C–027Fh page 2-108

COM2 Transmit Holding Register

(When 02FB[7] = 0, (COM2 DLAB=0) 02F8h page 2-109

COM2 Receive Buffer Register

(When 02FB[7] = 0, COM2 DLAB = 0) 02F8h page 2-110

COM2 Baud Clock Divisor Latch LSB

(When 02FB[7] = 1, COM2 DLAB =1) 02F8h page 2-111

COM2 Baud Clock Divisor Latch MSB

(When 02FB[7] = 1, COM2 DLAB =1) 02F9h page 2-112

COM2 Interrupt Enable Register

(When 02FB[7] = 0, COM2 DLAB = 0) 02F9h page 2-113

COM2 Interrupt ID Register 02FAh page 2-114

COM2 FIFO Control Register 02FAh page 2-116

COM2 Line Control Register 02FBh page 2-117

COM2 Modem Control Register 02FCh page 2-118

COM2 Line Status Register 02FDh page 2-119

COM2 Modem Status Register 02FEh page 2-121

COM2 Scratch Pad Register 02FFh page 2-122

Parallel Port 1 Data Register 0378h page 2-123

Parallel Port 1 Status Register (PC/AT Compatible

mode) 0379h page 2-124

Parallel Port 1 Status Register (Bidirectional) mode) 0379h page 2-125

Parallel Port 1 Status Register (EPP mode) 0379h page 2-126

Parallel Port 1 Control Register 037Ah page 2-127

Parallel Port 1 EPP Address Register 037Bh page 2-128

Parallel Port 1 EPP 32-bit Data Register 037C–037Fh page 2-129

MDA/HGA Index Register 03B4h page 2-130

MDA/HGA Data Port 03B5h page 2-131

MDA/HGA Mode Control Register 03B8h page 2-132

MDA/HGA Status Register 03BAh page 2-133

HGA Configuration Register 3BFh page 2-134

CGA Index Register 03D4h page 2-135

CGA Data Port 03D5h page 2-136

CGA Mode Control Register 03D8h page 2-137

CGA Color Select Register 03D9h page 2-138

PC/AT-Compatible Direct-Mapped Registers 2-5

2.2 REGISTER DESCRIPTIONS

Each direct-mappe d PC/AT Compatibl e register is described on the followi ng pages.

Addition al information about usi ng these registe rs to program the ÉlanSC400

microcontroller can be found in the

ÉlanSC400 User’s Manual

(order #21030).

CGA Status Register 03DAh page 2-139

Primary 82365-Compatible PC Card Controller

Index Register 03E0h page 2-140

Primary 82365-Compatible PC Card Controller Data

Port 03E1h page 2-141

COM1 Transmit Holding Register

(When 03FB[7] = 0, (COM1 DLAB =0) 03F8h page 2-142

COM1 Receive Buffer Register

(When 03FB[7] = 0, COM1 DLAB = 0) 03F8h page 2-143

COM1 Baud Clock Divisor Latch LSB

(When 03FB[7] =1, COM1 DLAB =1) 03F8h page 2-144

COM1 Baud Clock Divisor Latch MSB

(When 03FB[7] = 1, COM1 DLAB = 1) 03F9h page 2-145

COM1 Interrupt Enable Register

(When 03FB[7] = 0, COM1 DLAB = 0) 03F9h page 2-146

COM1 Interrupt ID Register 03FAh page 2-147

COM1 FIFO Control Register 03FAh page 2-148

COM1 Line Control Register 03FBh page 2-149

COM1 Modem Control Register 03FCh page 2-150

COM1 Line Status Register 03FDh page 2-151

COM1 Modem Status Register 03FDh page 2-153

COM1 Scratch Pad Register 03FFh page 2-154

PC/AT-Compatible Direct-Mapped Registers

2-6

Slave DMA Channel 0 Memory Ad dress Register I/O Address 0000h

Programming Notes

The ÉlanSC400 microcontroller is capable of performing 26-bit DMA accesses using the extended

DMA page registers that reside in the indexed ÉlanSC400 microcontroller registers D9h and DAh.

76543210

Bit DMA0MAR[15–0]

Default xxxxxxxx

R/W R/W

Bit Name Function

7–0 DMA0MAR[15–0] Lower 16 Bits of DMA Channel 0 Memory Address

This register is written/read via two successive I/O accesses to/from this

port (alw ays low byt e follo wed by hig h byte imme diatel y foll owin g a reset o f

the byt e poin ter at dire ct-mappe d I/O ad dress 0C h). Use i n conjun ction w ith

DMA Page Register for Channel 0 (I/O 87h) to form 24-bit memory

address.

PC/AT-Compatible Direct-Mapped Registers 2-7

Slave DMA Channel 0 Transfer Count Register I/O Address 0001h

Programming Notes

76543210

Bit DMA0TC[15–0]

Default xxxxxxxx

R/W R/W

Bit Name Function

7–0 DMA0TC[15–0] DMA Channel 0 Transfer Count (16-Bit Register)

This register is written/read via two successive I/O accesses to/from this

port (alw ays low byt e follo wed by hig h byte imme diatel y foll owin g a reset o f

the byte pointer at direct-mapped I/O address 0Ch). The actual number of

transfers will be one more than specified by this register.

PC/AT-Compatible Direct-Mapped Registers

2-8

Slave DMA Channel 1 Memory Ad dress Register I/O Address 0002h

Programming Notes

The ÉlanSC400 microcontroller is capable of performing 26-bit DMA accesses using the extended

DMA page registers that reside in the indexed ÉlanSC400 microcontroller registers D9h and DAh.

76543210

Bit DMA1MAR[15–0]

Default xxxxxxxx

R/W R/W

Bit Name Function

7–0 DMA1MAR[15–0] Lower 16 Bits of DMA Channel 1 Memory Address

This register is written/read via two successive I/O accesses to/from this

port (alw ays low byt e follo wed by hig h byte imme diatel y foll owin g a reset o f

the byt e poin ter at dire ct-mappe d I/O ad dress 0C h). Use i n conjun ction w ith

DMA Page Register for Channel 1 (I/O 83h) to form 24-bit memory

address.

PC/AT-Compatible Direct-Mapped Registers 2-9

Slave DMA Channel 1 Transfer Count Register I/O Address 0003h

Programming Notes

76543210

Bit DMA1TC[15–0]

Default xxxxxxxx

R/W R/W

Bit Name Function

7–0 DMA1TC[15–0] DMA Channel 1 Transfer Count (16-Bit Register)

This register is written/read via two successive I/O accesses to/from this

port (alw ays low byt e follo wed by hig h byte imme diatel y foll owin g a reset o f

the byte pointer at direct-mapped I/O address 0Ch.The actual number of

transfers will be one more than specified by this register.

PC/AT-Compatible Direct-Mapped Registers

2-10

Slave DMA Channel 2 Memory Ad dress Register I/O Address 0004h

Programming Notes

The ÉlanSC400 microcontroller is capable of performing 26-bit DMA accesses using the extended

DMA page registers that reside in the indexed ÉlanSC400 microcontroller registers D9h and DAh.

76543210

Bit DMA2MAR[15–0]

Default xxxxxxxx

R/W R/W

Bit Name Function

7–0 DMA2MAR[15–0] Lower 16 Bits of DMA Channel 2 Memory Address

This register is written/read via two successive I/O accesses to/from this

port (alw ays low byt e follo wed by hig h byte imme diatel y foll owin g a reset o f

the byt e poin ter at dire ct-mappe d I/O ad dress 0C h). Use i n conjun ction w ith

DMA Page Register for Channel 2 (I/O 81h) to form 24-bit memory

address.

PC/AT-Compatible Direct-Mapped Registers 2-11

Slave DMA Channel 2 Transfer Count Register I/O Address 0005h

Programming Notes

76543210

Bit DMA2TC[15–0]

Default xxxxxxxx

R/W R/W

Bit Name Function

7–0 DMA2TC[15–0] DMA Channel 2 Transfer Count (16-Bit Register)

This register is written/read via two successive I/O accesses to/from this

port (alw ays low byt e follo wed by hig h byte imme diatel y foll owin g a reset o f

the byte pointer at direct-mapped I/O address 0Ch). The actual number of

transfers will be one more than specified by this register.

PC/AT-Compatible Direct-Mapped Registers

2-12

Slave DMA Channel 3 Memory Ad dress Register I/O Address 0006h

Programming Notes

The ÉlanSC400 microcontroller is capable of performing 26-bit DMA accesses using the extended

DMA page registers that reside in the indexed ÉlanSC400 microcontroller registers D9h and DAh.

76543210

Bit DMA3MAR[15–0]

Default xxxxxxxx

R/W R/W

Bit Name R/W Function

7–0 DMA3MAR[15–0] R/W Lower 16 Bits of DMA Channel 3 Memory Address

This register is written/read via two successive I/O accesses to/

from this port (always low byte followed by high byte immediately

following a reset of the byte pointer at direct-mapped I/O address

0Ch). Use in conjunction with DMA Page Register for Channel 3

(I/O 82h) to form 24-bit memory address.

PC/AT-Compatible Direct-Mapped Registers 2-13

Slave DMA Channel 3 Transfer Count Register I/O Address 0007h

Programming Notes

76543210

Bit DMA3TC[15–0]

Default xxxxxxxx

R/W R/W

Bit Name Function

7–0 DMA3TC[15–0] DMA Channel 3 Transfer Count (16-Bit Register)

This register is w ritt en/read as tw o su cc es si ve bytes . T he actual nu mber of

transfers will be one more than specified by this register.

PC/AT-Compatible Direct-Mapped Registers

2-14

Slave DMA Status Register for Channels 0–3 I/O Address 0008h

Programming Notes

Bits 3–0 of this register are read/reset. Any read from this direct-mapped port clears bits 3–0.

76543210

Bit DMAR3 DMAR2 DMAR1 DMAR0 TC3 TC2 TC1 TC0

Default 00000000

R/W RRRRRRRR

Bit Name Function

7DMAR3 Channel 3 DMA Request

0 = Channel 3 DMA request not pending

1 = Channel 3 DMA request pending

6DMAR2 Channel 2 DMA Request

0 = Channel 2 DMA request not pending

1 = Channel 2 DMA request pending

5DMAR1 Channel 1 DMA Request

0 = Channel 1 DMA request not pending

1 = Channel 1 DMA request pending

4DMAR0 Channel 0 DMA Request

0 = Channel 0 DMA request not pending

1 = Channel 0 DMA request pending

3TC3 Channel 3 Terminal Count

0 = Channel 3 terminal count not detected

1 = Channel 3 terminal count detected

2TC2 Channel 2 Terminal Count

0 = Channel 2 terminal count not detected

1 = Channel 2 terminal count detected

1TC1 Channel 1 Terminal Count

0 = Channel 1 terminal count not detected

1 = Channel 1 terminal count detected

0TC0 Channel 0 Terminal Count

0 = Channel 0 terminal count not detected

1 = Channel 0 terminal count detected

PC/AT-Compatible Direct-Mapped Registers 2-15

Slave DMA Control Register for Cha nnels 0–3 I/O Address 0008h

76543210

Bit DAKSEN DRQSEN WRTSEL PRITYPE COMPTIM ENADMA ADRHEN MEM2MEM

Default 00000000

R/W WWWWWWWW

Bit Name Function

7 DAKSEN DACK(n) Sense

This bit controls the polarity of all DACK outputs from the slave DMA

controller:

0 = Asserted Low

1 = Asserted High

System logic external to the DMA controller expects the DMA controller to

drive active Low DACK outputs. This bit must be written to ‘0b’ for proper

system operation.

6 DRQSEN DREQ(n) Sense

This bi t con trol s the polarit y of a ll DR EQ inp uts to the s lave DMA co ntrolle r:

0 = Asserted High

1 = Asserted Low

System logic external to the DMA controller expects the DMA controller to

respond to active High DREQ inputs. This bit must be written to ‘0b’ for

proper system operation.

5 WRTSEL Write Selection Control

0 =Lat e write selection

Any DMA channel that is routed to the ÉlanSC400 IrDA controller must

have this bit cleared.

1 =Extended (early) write selection

Enabling this feature will result in timing changes on the ISA bus that can

viol ate the ISA s pecification.

4 PRITYPE Priority Type

0 = Fixed priority

1 = Rotating priority

3 COMPTIM Compressed Timing

0 = Nor mal t iming

1 = Compressed timing

Enabling this feature will result in timing changes on the ISA bus that can

viol ate the ISA s pecification.

2 ENADMA Enable DMA Controller

0 = Enabled

1 = DMA requests are ignored but DMA registers are available to the CPU

The DMA controller should be disabled prior to programming it in order to

prevent unintended transfers from occurring during the DMA controller

programming operation. If an I/O DMA initiator as sert s DRE Q while the

DMA cont roller is di sa ble v ia thi s bit, abnormal sys tem o pera tio n c an oc c ur.

PC/AT-Compatible Direct-Mapped Registers

2-16

Programming Notes

1 ADRHEN Enable Channel 0 Address Hold Control

IF bit 0 = 1, then:

0 =Disabled, Channel 0 memory address changes for each

memor y-to-memory transfer

1 =Enabled, Channel 0 memory address does not change for each

memory-to-memory transfer (not supported by the system)

ELSE this bit does nothing.

Since bit 0 should always be written to 0, this bit will be a don’t care after

the DMA controller has been initialized.

0 MEM2MEM Enable Memory-to-Memory Transfer

0 = Disabled

1 = Enabled (not supported by the system)

Memory-to-memory DMA support is not provided in a PC/AT Compatible

system. This bit should always be written to 0.

Bit Name Function

PC/AT-Compatible Direct-Mapped Registers 2-17

Slave Softwar e DRQ (n) Request Register I/O Address 0009h

Programming Notes

76543210

Bit Reserved REQDMA REQSEL1

REQSEL0

Default xxxxxxxx

R/W WW

Bit Name Function

7–3 Reserved Reserved

Software should write these bits to 0.

2 REQDMA Software DMA Request

0 = Reset request bit for channel selected by bits 1–0

1 = Set requ est bit for chann el selected by bits 1–0

1–0 REQSEL1

REQSEL0 DMA Channel Select

Bits 1–0 select which DMA channel will latch bit 2 internally to assert or

deassert a DMA request via software:

0 0 = Set/reset DMA Channel 0 internal DMA request per the REQDMA bit

0 1 = Set/reset DMA Channel 1 internal DMA request per the REQDMA bit

1 0 = Set/reset DMA Channel 2 internal DMA request per the REQDMA bit

1 1 = Set/reset DMA Channel 3 internal DMA request per the REQDMA bit

PC/AT-Compatible Direct-Mapped Registers

2-18

Slave DMA Mask Register Channels 0–3 I/ O Ad dress 000Ah

Programming Notes

The same DMA channel masks can be controlled via DMA registers 0Ah, 0Eh, and 0Fh.

76543210

Bit Reserved CHMASK MSKSEL1

MSKSEL0

Default xxxxxxxx

R/W WW

Bit Name Function

7–3 Reserved Reserved

Software should write these bits to 0.

2 CHMASK DMA Channel Mask

0 = Clear mask bit for channel selected by bits 1–0

1 = Set mask bit for channel selected by bits 1–0

1–0 MSKSEL1

MSKSEL0 DMA Channel Mask Select

Bits 1–0 select which DMA channel will latch bit 2 internally to mask or

unmask the DRQ signal into the specified DMA channel:

0 0 = Mask/unmask DMA Channel 0 mask per the CHMASK bit

0 1 = Mask/unmask DMA Channel 1 mask per the CHMASK bit

1 0 = Mask/unmask DMA Channel 2 mask per the CHMASK bit

1 1 = Mask/unmask DMA Channel 3 mask per the CHMASK bit

PC/AT-Compatible Direct-Mapped Registers 2-19

Slave DMA Mode Register Channels 0–3 I/O Address 000 Bh

Programming Notes

76543210

Bit TRNMOD ADDDEC AINIT OPSEL1

OPSEL0 MODSEL1

MODSEL0

Default xxxxxxxx

R/W WWWW W

Bit Name Function

7–6 TRNMOD Transfer Mode

0 0 = Demand transfer mode

0 1 = Single transfer mode

1 0 = Block transfer mode

1 1 = Cascade mode

5 ADDDEC Address Decrement

0 = Increment the DMA memory address after each transfer

1 = Decrement the DMA memory address after each transfer

4 AINIT Automatic Initialization Control

If enabled, the base address and transfer count registers are restored to

the values they contained prior to performing the last DMA transfer. The

channel selected by bits 0–1 of this register is then ready to perform

another DMA transfer without processor intervention as soon as the next

DRQ is detected.

0 = Aut omatic initialization disabled

1 = Aut omatic initialization enabl ed

3–2 OPSEL1

OPSEL0 Operation Select

0 0 =Verify mode

DMA controller acts normally except that no I/O or memory

commands are generated, and no data is transferred

0 1 =Write transfer

Data will be transferred from a DMA-capable I/O device into system

memory

1 0 =Read transfer

Data will be transferred from system memory to a DMA-capable I/O

device

1 1 =Reserved

1–0 MODSEL1

MODSEL0 DMA Channel Select

Bits 7–2 of this register are latched internally for each channel. Bits 0–1

determine which of the channels will be programmed by the write to port

0Bh as follows:

0 0 = Select Channel 0

0 1 = Select Channel 1

1 0 = Select Channel 2

1 1 = Select Channel 3

PC/AT-Compatible Direct-Mapped Registers

2-20

Slave DMA Clear Byte Pointer Regi ster I/O Address 000Ch

Programming Notes

76543210

Bit SLAVE_CPB

Default xxxxxxxx

R/W W

Bit Name Function

7–0 SLAVE_CPB Slave DMA Clear Byte Pointer

The DMA Controller contains some 16-bit registers which are accessed by

writing or reading consecutive 8-bit values to the same direct-mapped I/O

location. A single byte pointer is used across the slave DMA Controller to

determine which byte will be accessed. Any access to one of these 16-bit

registers toggles the byte pointer between the low and high bytes. A write

of any data to I/O address 0Ch clears this pointer so that the next access

will be to the low byte.

PC/AT-Compatible Direct-Mapped Registers 2-21

Slave DMA Controller Reset Register I/O Address 000Dh

Programming Notes

76543210

Bit SLAVE_RST

Default 00000000

R/W W

Bit Name Function

7–0 SLAVE_RST Slave DMA Controller Reset

A write of any data to this address resets the DMA Controller to the same

state as a hardware reset.

PC/AT-Compatible Direct-Mapped Registers

2-22

Slave DMA Controller Temporary Register I/O Address 000Dh

Programming Notes

The same DMA channel masks can be controlled via DMA registers 0Ah, 0Eh, and 0Fh.

76543210

Bit SLAVE_TMP

Default 00000000

R/W R

Bit Name Function

7–0 SLAVE_TMP Slave DMA Controller Temporary Register

Used as a temporary storage buffer when doing memory-to-memory DMA.

Memory-to-memory DMA transfer is not supported, and this register was

included for compatibility reasons only.

PC/AT-Compatible Direct-Mapped Registers 2-23

Slave DMA Reset Mask Register I/O Address 000Eh

Programming Notes

The same DMA channel mask can be controlled via DMA register 0Ah, 0Eh, and 0Fh.

76543210

Bit SLAVE_MSK_RST

Default xxxxxxxx

R/W W

Bit Name Function

7–0 SLAVE_MSK_RST Slave DMA Reset Mask

Writing any data to this I/O address resets the Mask Register, thereby

activating the four slave DMA channels.

PC/AT-Compatible Direct-Mapped Registers

2-24

Slave DMA General Mask Register I/O Address 000Fh

Programming Notes

The same DMA channel masks can be controlled via DMA registers 0Ah, 0Eh, and 0Fh.

76543210

Bit Reserved DIS3 DIS2 DIS1 DIS0

Default 00001111

R/W WWWW

Bit Name Function

7–4 Reserved Reserved

Software should write these bits to 0.

3DIS3 DMA Channel 3 Mask

0 = Enable DMA Channel 3 for servicing DMA requests

1 = Disable DMA Channel 3 from servicing DMA requests

2DIS2 DMA Channel 2 Mask

0 = Enable DMA Channel 2 for servicing DMA requests

1 = Disable DMA Channel 2 from servicing DMA requests

1DIS1 DMA Channel 1 Mask

0 = Enable DMA Channel 1 for servicing DMA requests

1 = Disable DMA Channel 1 from servicing DMA requests

0DIS0 DMA Channel 0 Mask

0 = Enable DMA Channel 0 for servicing DMA requests

1 = Disable DMA Channel 0 from servicing DMA requests

PC/AT-Compatible Direct-Mapped Registers 2-25

Master 8259 Interrupt Request Register I/O Address 0020h

Programming Notes

This register provides a real-time status of the IRQ (interrupt request) inputs to the Master 8259.

The Master Interrupt Request register (IRR) is accessed by first writing a value of 0Ah to port 20h

followed by a read-back from port 20h.

Since the Slave 8259 cascades into Channel 2 of the Master 8259, IR2 is a real-time status indication

that one of the slave IRQ inputs is asserted.

76543210

Bit IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0

Default xxxxxxxx

R/W RRRRRRRR

Bit Name Function

7IR7 Interrupt Request 7

0 = IRQ7 input to the Maste r 8259 is not asserted

1 = IRQ7 is asserted

6IR6 Interrupt Request 6

0 = IRQ6 input to the Maste r 8259 is not asserted

1 = IRQ6 is asserted

5IR5 Interrupt Request 5

0 = IRQ5 input to the Maste r 8259 is not asserted

1 = IRQ5 is asserted

4IR4 Interrupt Request 4

0 = IRQ4 input to the Maste r 8259 is not asserted

1 = IRQ4 is asserted

3IR3 Interrupt Request 3

0 = IRQ3 input to the Maste r 8259 is not asserted

1 = IRQ3 is asserted

2IR2 Interrupt Request 2

0 = IRQ2 input to the Maste r 8259 is not asserted

1 = IRQ2 is asserted

1IR1 Interrupt Request 1

0 = IRQ1 input to the Maste r 8259 is not asserted

1 = IRQ1 is asserted

0IR0 Interrupt Request 0

0 = IRQ0 input to the Maste r 8259 is not asserted

1 = IRQ0 is asserted

PC/AT-Compatible Direct-Mapped Registers

2-26

Master 8259 In-Service Register I/O Address 0020 h

Programming Notes

The Master In-Service register (ISR) is accessed by first writing a value of 0Bh to port 20h followed

by a read-back from port 20h.

Since the Slave 8259 cascades into Channel 2 of the Master 8259, IS2 will be asserted if any slave

IRQ level is asserted.

76543210

Bit IS7 IS6 IS5 IS4 IS3 IS2 IS1 IS0

Default xxxxxxxx

R/W RRRRRRRR

Bit Name Function

7IS7 IRQ7 In-Service

0 = IRQ7 is not being serviced

1 = IRQ7 is being serviced

6IS6 IRQ6 In-Service

0 = IRQ6 is not being serviced

1 = IRQ6 is being serviced

5IS5 IRQ5 In-Service

0 = IRQ5 is not being serviced

1 = IRQ5 is being serviced

4IS4 IRQ4 In-Service

0 = IRQ4 is not being serviced

1 = IRQ4 is being serviced

3IS3 IRQ3 In-Service

0 = IRQ3 is not being serviced

1 = IRQ3 is being serviced

2IS2 IRQ2 In-Service

0 = IRQ2 is not being serviced

1 = IRQ2 is being serviced

1IS1 IRQ1 In-Service

0 = IRQ1 is not being serviced

1 = IRQ1 is being serviced

0IS0 IRQ0 In-Service

0 = IRQ0 is not being serviced

1 = IRQ0 is being serviced

PC/AT-Compatible Direct-Mapped Registers 2-27

Master 8259 Initialization Contr ol Word 1 Register I/O Address 0020h

Programming Notes

76543210

Bit Reserved SLCT_ICW1 LTIM ADI SNGL IC4

Default xxxxxxxx

R/W W WWWWW

Bit Name Function

7–5 Reserved Reserved

Must all be written to 0.

4 SLCT_ICW1 Select ICW1

Must be written to 1 to access ICW1 (D4 = 1 means the IOW to port 20h is

Initializati on Control Word 1).

3 LTIM Level-Triggered Interrupt Mode

0 = Edge-sensitive IRQ de tection

1 = Level-sensitive IRQ detection

2ADI Address Interval (has no effect when the 8259 is used in x86 mode)

0 = Interrupt vectors are separated by 8 locations

1 = Interrupt vectors are separated by 4 locations

In the ÉlanSC400 microcontroller design, this PC/AT Compatible bit is

internally fixed to ‘1b’.

1SNGL Single 8259

If this bit is set, then t he inte rnal re gister pointe r will skip ICW3, and p oint to

ICW4 if I CW4 was se lected to be pro grammed v ia bit 0 o f this regis ter. See

the explanation for bit 0 of this register:

0 = Cascade mode, ICW3 will be expected

1 = Single 8259 in the system, ICW3 will not be expected

In the ÉlanSC400 microcontroller design, this PC/AT Compatible bit is

internally fixed to ‘0b’.

0IC4 Initializa tion Control Word 4

ICW4 is required. The 8259’s initial ization c ontrol word (ICW) reg isters 1–4

are programmed in sequence. Writing to port 20h with bit 4 = 1 causes the

internal ICW1 Register to be written, and resets the PIC’s internal state

machine and ICW register pointer. Master ICW2–4 are programmed via

port 21h. Each time 21h is written to (following ICW1), the register pointer

points to the next internal ICW register. ICW1 and ICW2 must always be

programm ed, b ut ICW3 and ICW4 ne ed on ly b e prog ramme d under c ertain

circumstances.

0 =Ini tial ization Control Word 4 is cleared by writ ing I nitialization Control

Word 1, ICW4 will not be expe cted by the PIC

1 =ICW4 is not cleared by this write t o Initialization Con trol Word 1, and

software is expected to initialize IC W4

This bit determines whether ICW4 is required to be explicitly programmed,

or whether a value of 00h will serve for ICW4. If ICW4 is selected to be

programmed, the register pointer will point to ICW4 after ICW3, and the

PIC will expect software to provide an initialization value for it.

In the ÉlanSC400 microcontroller design, this PC/AT Compatible bit is

internally fixed to ‘1b’.

PC/AT-Compatible Direct-Mapped Registers

2-28

Master 8259 Oper ation Con tr ol Word 2 Regist er I/O Ad dress 0020h

Programming Notes

I/O writes to port 20h access different PIC registers based on bits 4–3 of the data that is written.

See the following table:

76543210

Bit R

EOI SLCT_ICW1 IS_OCW3 LS[2–0]

Default xxxxxxxx

R/W WWWW

Bit Name R/W Function

7–5 R

EOI

WIRQ EOI and Priority Rotation Controls

0 0 0 = Rotate in auto EOI mode (clear)

0 0 1 = Non-specific EOI

0 1 0 = No operation

0 1 1 = Specific EO I

1 0 0 = Rotate in auto EOI mode (set)

1 0 1 = Rotate on non-specific EOI command

1 1 0 = Set priority command

1 1 1 = Rotate on specific EOI command

4 SLCT_ICW1 W Select Initialization Control Word 1

Software must write this bit to 0 to access OCW2 or OCW3.

3IS_OCW3 WAccess is OCW3

An I/O write to port 20h with this bit cleared indicates that OCW2

is to be accessed.

2–0 LS[2–0] W Specific EOI Level Select

Interrupt level which is acted upon when the SL bit = ‘1b’ (see bits

7–5 of this register):

0 0 0 = IRQ0

0 0 1 = IRQ1

0 1 0 = IRQ2

0 1 1 = IRQ3

1 0 0 = IRQ4

1 0 1 = IRQ5

1 1 0 = IRQ6

1 1 1 = IRQ7

Bit 4 Bit 3 Register Accessed

00OCW2

01OCW3

1xICW1

PC/AT-Compatible Direct-Mapped Registers 2-29

Master 8259 Oper ation Con tr ol Word 3 Regist er I/O Ad dress 0020h

Programming Notes

I/O writes to port 20h access different PIC registers based on bits 4–3 of the data that is written.

See the following table:

76543210

Bit Reserved ESMM

SMM SLCT_ICW1 IS_OCW3 P RR

RIS

Default xxxxxxxx

R/W W WWW W

Bit Name Function

7Reserved Reserved

Software should write this bit to 0.

6–5 ESMM

SMM Special Mask Mode

0 x = No operation

1 0 = Reset special mask

1 1 = Set special mask

In the ÉlanSC 400 micro controlle r des ign, the ESM M bit is i nternal ly f ixed to

‘1b’.

4 SLCT_ICW1 Initializa tion Control Word 1 Select

Software should write this bit to 0 to access OCW2 or OCW3.

3IS_OCW3 Access is OCW3

An I/O write to port 20h with this bit set indicates that OCW3 is to be

accessed.

2P PIC Poll Command

A system design can choose to use the PIC in a non-interrupting mode. In

this case, the interrupt controller can be polled for the status of pending

interrupts. In order to support this PC/AT incompatible mode of operation,

the PIC supports a special poll command which is invoked by writing

OCW3 with this bit set.

0 = Not poll command

1 = Poll command

1–0 RR

RIS Status Register Select

0 0 = No change from last state

0 1 = No change from last state

1 0 = Next port 20h read will return Interrupt Request Register (IRR)

1 1 = Next port 20h read will return In-Service Register (ISR)

Bit 4 Bit 3 Register Accessed

00OCW2

01OCW3

1xICW1

PC/AT-Compatible Direct-Mapped Registers

2-30

Master 8259 Initialization Contr ol Word 2 Register I/O Address 0021h

Programming Notes

76543210

Bit T7–T3 A10–A8

Default xxxxxxxx

R/W WW

Bit Name Function

7–3 T7–T3 Base Interrupt Vector Number

Bits 7–3 of base interrupt vector number for this PIC. Bits 2–0 are

conc atenated by PIC ba sed on IRQ level. For example, these bits will be

programmed to 00001b for the master PIC (IRQ0 generates int 8), and

01110b for the slave PIC (IRQ8 corresponds to int 70h) in a

PC/AT-compatible system.

2–0 A10–A8 A10–A8 of Interrupt Vector

Always = 0 in a PC/AT-compatible system.

PC/AT-Compatible Direct-Mapped Registers 2-31

Master 8259 Initialization Contr ol Word 3 Register I/O Address 0021h

Programming Notes

Bits 7–3 and 1–0 of ICW3 are internally fixed to ‘0b’ in this design. Bit 2 is internally fixed to ‘1b’.

76543210

Bit S7 S6 S5 S4 S3 S2 S1 S0

Default xxxxxxxx

R/W WWWWWWWW

Bit Name Function

7S7 Channel 7 Slave Cascade Select

0 = I/O device attached to IRQ7 input

1 = IRQ7 input used for slave cascading

6S6 Channel 6 Slave Cascade Select

0 = I/O device attached to IRQ6 input

1 = IRQ6 input used for slave cascading

5S5 Channel 5 Slave Cascade Select

0 = I/O device attached to IRQ5 input

1 = IRQ5 input used for slave cascading

4S4 Channel 4 Slave Cascade Select

0 = I/O device attached to IRQ4 input

1 = IRQ4 input used for slave cascading

3S3 Channel 3 Slave Cascade Select

0 = I/O device attached to IRQ3 input

1 = IRQ3 input used for slave cascading

2S2 Channel 2 Slave Cascade Select

0 = I/O device attached to IRQ2 input

1 = IRQ2 input used for slave cascading

1S1 Channel 1 Slave Cascade Select

0 = I/O device attached to IRQ1 input

1 = IRQ1 input used for slave cascading

In the ÉlanSC400 microcontroller design, this PC/AT Compatible bit is

internally fixed to ‘1b’.

0S0 Channel 0 Slave Cascade Select

0 = I/O device attached to IRQ0 input

1 = IRQ0 input used for slave cascading

PC/AT-Compatible Direct-Mapped Registers

2-32

Master 8259 Initialization Contr ol Word 4 Register I/O Address 0021h

Programming Notes

76543210

Bit Reserved SFNM BUF

M/S AEOI PM

Default xxxxxxxx

R/W W WWWW

Bit Name Function

7–5 Reserved Reserved

Software should write these bits to 0.

4SFNM Special Fully Nested Mode Enable

0 = Normal nested mode

1 = Special f ully nested mode

3–2 BUF

M/S Buffered Mode and Master/Slave Select

0 x = Non-buffered mode

1 0 = Buffered mode/slave

1 1 = Buffered mode/master

In the ÉlanSC400 microcontroller design, these bits are internally fixed to

‘00b’.

1 AEOI Automatic EOI Mode

0 =Normal EOI

Interrupt handler must send an End of Interrupt command to the PIC(s)

1 =Auto EOI

EOI is automatically performed after the second INTA signal from the

CPU

0PM Micro pr oce sso r Mod e

0 = 8080/8085 mode

1 = 8086 mode

In the ÉlanSC400 microcontroller design, this PC/AT Compatible bit is

internally fixed to ‘1b’.

PC/AT-Compatible Direct-Mapped Registers 2-33

Master 8259 Interrupt Mask Register I/O Address 0021h

(also known as Operation Control Word 1)

Programming Notes

76543210

Bit IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM0

Default xxxxxxxx

R/W R/W R/W R/W R/W R/W R/W R/W R/W

Bit Name Function

7IM7 IRQ7 Mask

0 = Unmask IRQ7

1 = Mask IRQ7

6IM6 IRQ6 Mask

0 = Unmask IRQ6

1 = Mask IRQ6

5IM5 IRQ5 Mask

0 = Unmask IRQ5

1 = Mask IRQ5

4IM4 IRQ4 Mask

0 = Unmask IRQ4

1 = Mask IRQ4

3IM3 IRQ3 Mask

0 = Unmask IRQ3

1 = Mask IRQ3

2IM2 IRQ2 Mask

0 = Unmask IRQ2

1 = Mask IRQ2

1IM1 IRQ1 Mask

0 = Unmask IRQ1

1 = Mask IRQ1

0IM0 IRQ0 Mask

0 = Unmask IRQ0

1 = Mask IRQ0

PC/AT-Compatible Direct-Mapped Registers

2-34

ÉlanSC400 Microcontroller I/O Address 0022h

Chip Setup and Control (CSC) Ind ex Register

Programming Notes

76543210

Bit CSC_INDEX[7–0]

Default 00000000

R/W R/W

Bit Name Function

7–0 CSC_INDEX[7–0] ÉlanSC400 Microcontroller Chip Setup and Control (CSC) Index

Specify an 8-bit CSC indexed configuration register address via this

port. Data can then be read from or written to the specified

configuration register via direct-mapped port 23h.

PC/AT-Compatible Direct-Mapped Registers 2-35

ÉlanSC400 Microcontroller I/O Address 0023h

Chip Setu p and Control ( CSC) Data Port

Programming Notes

76543210

Bit CSC_DATA[7–0]

Default 00000000

R/W R/W

Bit Name Function

7–0 CSC_DATA[7–0] ÉlanSC400 Microcontroller Chip Setup and Control (CSC) Data Port

Via this p ort, data can be rea d or w ri tten to th e c onf iguration reg ister that is

specif ied usin g direc t -m app ed port 22h.

PC/AT-Compatible Direct-Mapped Registers

2-36

Programmable Interval Timer #1 I/O Address 0040h

Channel 0 Count Register (System Timer/Ti mer Tick)

Programming Notes

If a r ead -back command is issued in which LSTAT = ‘0b’, and the CNT0 bit = ‘1b’, a status byte for

this channel, as defined by the Programmable Interval Timer #1 Status Register (see below), will

be read back. If a read-back command is issued in which LSTAT = ‘0b’, LCNT = ‘0b’, and the CNT0

bit = ‘1b’, the first read from this register will return the status byte, and the second/third bytes will

return the 1 or 2 (low/high) latched count byte(s).

When set up for either BCD or 16-bit binary count operation, the maximum count for Channel 0 is

achieved by writing the internal counting element associated with this register to 0000h/d. See

direct-mapped register 43h for more detail.

76543210

Bit CH0_COUNT[15–0]

Default 00000000

R/W R/W

Bit Name Function

7–0 CH0_COUNT[15–0] 16-bit Counter for Programmable Interval Timer #1, Channel 0

Access either the counter high byte only, low byte only, or low byte

followed by high byte as defined by bits 5–4 of direct-mapped register

43h for either read or write operations.

Immediately following a counter latch command (or a read-back

command in which the LCNT bit = ‘0b’, and the CNT0 bit = ‘1b’), the

latched count can be read from this register. After the 1 or 2 bytes of

latched count are read, subsequent reads return the unlatched count.

PC/AT-Compatible Direct-Mapped Registers 2-37

Programmable Interval Timer #1 I/O Address 0041h

Chan nel 1 Count Register (Refresh Timer)

Programming Notes

If a r ead -back command is issued in which LSTAT = ‘0b’, and the CNT1 bit = ‘1b’, a status byte for

this channel, as defined by the Programmable Interval Timer #1 Status Register (see below), will

be read back. If a read-back command is issued in which LSTAT = ‘0b’, LCNT = ‘0b’, and the CNT1

bit = ‘1b’, the first read from this register will return the status byte, and the second/third bytes will

return the 1 or 2 (low/high) latched count byte(s).

When set up for either BCD or 16-bit binary count operation, the maximum count for Channel 1 is

achieved by writing the internal counting element associated with this register to 0000h/d. See

direct-mapped register 43h for more detail.

76543210

Bit CH1_COUNT[15–0]

Default 00000000

R/W R/W

Bit Name Function

7–0 CH1_COUNT[15–0] 16-bit Counter for Programmable Interval Timer #1, Channel 1

Access either the counter high byte only, low byte only, or low byte

followed by high byte as defined by bits 5–4 of direct-mapped register

43h for either read or write operations.

Immediately following a counter latch command (or a read-back

command in which the LCNT bit = ‘0b’, and the CNT1 bit = ‘1b’), the

latched count can be read from this register. After the 1 or 2 bytes of

latched count are read, subsequent reads return the unlatched count.

PC/AT-Compatible Direct-Mapped Registers

2-38

Programmable Interval Timer #1 I/O Address 0042h

Channel 2 Count Register (Speaker Timer)

Programming Notes

If a r ead -back command is issued in which LSTAT = ‘0b’, and the CNT2 bit = ‘1b’, a status byte for

this channel, as defined by the Programmable Interval Timer #1 Status Register (see below), will

be read back. If a read-back command is issued in which LSTAT = ‘0b’, LCNT = ‘0b’, and the CNT2

bit = ‘1b’, the first read from this register will return the status byte, and the second/third bytes will

return the 1 or 2 (low/high) latched count byte(s).

When set up for either BCD or 16-bit binary count operation, the maximum count for Channel 2 is

achieved by writing the internal counting element associated with this register to 0000h/d. See

direct-mapped register 43h for more detail.

76543210

Bit CH2_COUNT[15–0]

Default 00000000

R/W R/W

Bit Name Function

7–0 CH2_COUNT[15–0] 16-bit Counter for Programmable Interval Timer #1, Channel 2

Access either the counter high byte only, low byte only, or low byte

followed by high byte as defined by bits 5–4 of direct-mapped register

43h for either read or write operations.

Immediately following a counter latch command (or a read-back

command in which the LCNT bit = ‘0b’, and the CNT2 bit = ‘1b’), the

latched count can be read from this register. After the 1 or 2 bytes of

latched count are read, subsequent reads return the unlatched count.

PC/AT-Compatible Direct-Mapped Registers 2-39

Programmable Interval Timer #1 Status Register I/O Address 00 40–0042h

76543210

Bit OUTPUT NULLCNT RW1

RW0

M0 BCD

Default 00000000

R/W RR R R R

Bit Name Function

7 OUTPUT Output Pin State

Output signal for the current timer channel. Each timer channel has an

output pin that is driven high or low based on the current mode. See the

brief mode descriptions for bits 3–1 of this register for more detail.

0 = Current state of OUT(x) signal = logic 0

1 = Current state of OUT(x) signal = logic 1

6 NULLCNT Null Count

When programming a new count value into one of the timers, the new value

does not take effect until it has actually been transferred to the counting

element, which can take some time. Thus, when attempting to read back a

count value, this bit indicates whether th e valu e read back is valid or not.

1 = Null count, re ad back of the counter will be invalid

0 = Counter is available for reading

5–4 RW1

RW0 Counter Read/Write Operation Control or Counter Latch Command

Reflects the last bit setting that was programmed into this field for this

counter channel via the Programmable Interval Timer #1 Mode Control

on page 2-41 for more information.

0 0 = Counter Latch Command

0 1 = Read/Write LSB only

1 0 = Read/Write MSB only

1 1 = Read/Write LSB first followed by MSB

3–1 M2

Counter Mode Status

Reflects the last counter mode setting for counters 0, 1, or 2 that was

programmed into this channel via the Programmable Interval Timer #1

Mode Control Register. See the Programmable Interval Timer #1 Mode

Control Register on page 2-41 for more information.

Gate = High unless noted

0 0 0 = Mode 0: Interrupt on termina l count

0 0 1 = Mode 1: Hardware retriggerable one-shot

0 1 0 = Mode 2: Rate gener ator

0 1 1 = Mode 3: Square wave generato r

1 0 0 = Mode 4: Software retrig gerable strobe

1 0 1 = Mode 5: Hardware retriggera ble strobe

1 1 0 = Alias for mode 2

1 1 1 = Alias for mode 3

See the table below for more detail on this register.

0BCD Binary Coded Decimal Select Status

Reflects the last BCD setting for counters 0, 1, or 2 that was programmed

into this chann el via t he Programmable Interval Timer #1 Mode Control

on page 2-41 for more information.

0 = 16-bit binary counter with a range of 0–FFFFh

1 = BCD counter with a range of 0–9999d

PC/AT-Compatible Direct-Mapped Registers

2-40

Programming Notes

These three registers (at direct-mapped I/O addresses 40h, 41h, and 42h) are separately available

only as a result of sending a read-back command with the LSTAT bit = ‘0b’, and the appropriate

CNTX bit set (where X is a counter from 0–2). For more detail, see the Read-Back Command Register

on page 2-44. Note also that modes 1 and 5 require a rising edge on the gate input for each timer

channel. Only Timer 2 has a gate control (see direct-mapped port 61h[0]) so only Channel 2 is

capable of running all modes. The gate controls for Timers 0 and 1 are fixed internally to ‘1b’, so

they are only capable of operation in modes 0, 2, 3 and 4.

Coun ter Mode Stat us Bit s 3–1

Settings Mode Name Description

0 0 0 = Mode 0 Interrupt on terminal count When the counter is programmed, the

Counter Output Signal transitions to 0.

When counter reaches 0, the Counter

Output signal transitions to 1 until another

count is written.

0 0 1 = Mode 1 Hardware retriggerable one-shot When mode/counter are programmed, the

Counter Output signal transitions to 1.

When gate goes 0 transitions to 1, OUT

transitions to 0 until the count reaches 0,

then OUT transitions to 1 until the next

low-high transition on gate.

0 1 0 = Mode 2 Rate generator Each time the count transitions to 1, OUT

transitions to 0, and remains there for 1

cycle of the input clock, and then OUT

transitions to 1. The count is automatically

reloaded, and the proc ess repea ts. Timer 0

uses this mode by default in the PC/AT.

0 1 1 = Mode 3 Square wave generator When the count is loaded, OUT transitions

to 1. When 1/2 of the count has expired,

OUT transitions to 0. When count

transitions to 0, OUT transitions to 1, and

count is automatically reloaded. In the PC/

AT, Timers 1 and 2 use this mode by

default to drive DRAM refresh and the

speaker res pec tiv ely.

1 0 0 = Mode 4 Software retriggerable strobe When the count is loaded, OUT transitions

to 1. When counter = 0, OUT transitions to

0 for 1 clock and then OUT transitions to 1.

1 0 1 = Mode 5 Hardware retriggerable strobe The Counter Output signal behaves just

like mode 4 except that the triggering is

done by a lo w to hig h transit ion on the gate

input. A trigger seen during the count

reloads the count to the initial value and

then counting continues.

1 1 0 = Alias for mode 2

1 1 1 = Alias for mode 3

PC/AT-Compatible Direct-Mapped Registers 2-41

Programmable Interval Timer #1 Mode Control Regi ster I/O Address 0043h

76543210

Bit SC1

SC0 RW1

RW0

M0 BCD

Default 00000000

R/W WW WW

Bit Name Function

7–6 SC1

SC0 Channel Select or Read-back Command

When this register is written to with bits 7–6 = ‘11b’, this register is

redefined (for the duration of the current I/O write) as the Read-back

Command Register which is described as a separate register below.

When this register is written to with bits 7–6 ≠ ‘11b’, and bits 5–4 ≠ ‘00b’,

these bits specify to which of the three on-chip counters the settings in bits

5–0 apply :

0 0 = Select Channel 0

0 1 = Select Channel 1

1 0 = Select Channel 2

1 1 = Read-back Co mmand

A read-back command is a higher priority command than the counter latch

command. If bits 5–4 are written to ‘00b’, and bits 7–6 are written to ‘11b’,

only th e read-bac k co mm an d w il l b e recogn ize d as co mm and bi ts , an d bits

5–4 will take on the meanings as described by the Read-back Command

Regis ter bel ow .

5–4 RW1

RW0 Counter Read/Write Operation Control or Counter Latch Command

When this register is written to with bits 5–4 = ‘00b’, and bits 7–6 ≠ ‘11b’,

this register is redefined (for the duration of the current I/O write) as the

Counter Latch Command Register which is described as a separate

When this register is written to with bits 7–6 ≠ ‘11b’, and bits 5–4 ≠ ‘00b’,

these bits define what can be written to the Channel X Count Register,

where X is selected by bits 7–6 of this register. Note that if only 8 bits of a

count reg ister wil l be accessed (i.e., bits 5– 4 = ‘01b’ or ‘10 b’), a su bsequent

write to the count register (as indicated by bits 7–6) will automatically clear

the 8 bit s of the associ ated int ernal 16-b it count ing elem ent wh ich were not

explicitly wr itten to.

0 0 = Counter Latch Command

0 1 = Read/Write counter bits [7–0]

1 0 = Read/Write counter bits [15–8]

1 1 = Read/Write counter bits [7–0] followed immediately by [15–8]

A counter latch command does not stop a counter from running, but rather

takes a snapshot of the current value. When a counter’s current value is

required, a counter latch command or a read-back command should be

used to ob tain it. On ce the coun t has been la tched, furth er latch com mands

are ignored until all latched count data is read back from the associated

count register. Also note that the 8254 Programmable Interval Timer does

not pr ovide an y way to re ad back the origin al count programme d into an y of

the three count registers.

PC/AT-Compatible Direct-Mapped Registers

2-42

Programming Notes

Writing to this register to change the mode for a particular counter resets the control logic and resets

the associated counter value and OUT pin.

3–1 M2

Counter Mode

When this register is written to with bits 7–6 ≠ ‘11b’, and bits 5–4 ≠ ‘00b’,

these bits control the counter operation:

0 0 0 = Mode 0: Interrupt on termina l count

0 0 1 = Mode 1: Hardware retriggerable one-shot

0 1 0 = Mode 2: Rate gener ator

0 1 1 = Mode 3: Square wave generato r

1 0 0 = Mode 4: Software retrig gerable strobe

1 0 1 = Mode 5: Hardware retriggera ble strobe

1 1 0 = Alias for mode 2

1 1 1 = Alias for mode 3

0BCD Binary Coded Decimal Select

When this register is written to with bits 7–6 ≠ ‘11b’, and bits 5–4 ≠ ‘00b’,

this bi t controls whether the counter i ndicated by bits 7–6 of this re gister wil l

count in binary with a range of 0–FFFFh or in binary coded decimal (BCD)

with a range of 0–9999d.

0 = 16-bit binary counter

1 = BCD counter

Bit Name Function

PC/AT-Compatible Direct-Mapped Registers 2-43

Programmable Interval Timer #1 I/O Address 0043h

Coun ter Latch Command Re gister

Programming Notes

76543210

Bit SC1

SC0 RW1

RW0 Reserved

Default 00000000

R/W WW

Bit Name Function

7–6 SC1

SC0 Counter Select

Specify whic h of th e th ree c oun ter e lem en ts to latch for rea d back fr om t he

associated count register. The counter latch command is a subset of the

read-back command since only one channel can have its counter latched

per counter latch comm and :

0 0 = Select counter 0

0 1 = Select counter 1

1 0 = Select counter 2

1 1 = N/A

5–4 RW1

RW0 Counter Command

0 0 = Counter Latch Command

See Programmable Interval Timer #1 Mode Control Register on page 2-41

for more detail.

3–0 Reserved Reserved

Software should write these bits to 0.

PC/AT-Compatible Direct-Mapped Registers

2-44

Programmable Interval Timer #1 I/O Address 0043h

Read-Back Command Re gister

Programming Notes

76543210

Bit SC1

SC0 LCNT LSTAT CNT2 CNT1 CNT0 Reserved

Default 00000000

W WWWWWW

Bit Name Function

7–6 SC1

SC0 Counter Select/Read-back Command

1 1 =Read-back Command

Values a s sel ected by bit s 5–1 o f this registe r are availab le t o be rea d

back from direct-mapped ports 40h–42h immediately following

completion of the I/O write that implements this Read-back

Command. Latched counts will be read back based on the current

mode for eac h counter (bits 7–0, bit s 15–8, or bits 7–0 fol lowed by bits

15–8). For the format of the returned status byte, see the

Programmable Interval Timer#1 Status Register bit descriptions

above. See the Programmable Interval Timer #1 Mode Control

If both LSTAT and LCNT = ‘0b’, the status byte will be available at the

respective count register (direct-mapped 40h, 41h, and 42h) first. When

this b yte ha s been read, the latched co unt byte(s ) wi ll be av ai lab le , a nd w ill

read bac k low ord er byte a nd then hig h order by te (if s et up to re ad back al l

16-bits of count via the Programmable Interval Timer #1 Mode C ontrol

5 LCNT Latch Count (low true)

0 = Latch count for counters selected via bits 3–1

1 = Do not latch count for counters selected via bits 3–1

4 LSTAT Latch Status (low true)

0 = Latch status for counters sele cted v ia bit s 3–1

1 = Do not latch status for counters selected via bits 3–1

3 CNT2 Select Counter 2

0 = Counter 2 not selected for operations specified by bits 5–4

1 = Counter 2 selected for operations specified by bits 5–4

2 CNT1 Select Counter 1

0 = Counter 1 not selected for operations specified by bits 5–4

1 = Counter 1 selected for operations specified by bits 5–4

1 CNT0 Select Counter 0

0 = Counter 0 not selected for operations specified by bits 5–4

1 = Counter 0 selected for operations specified by bits 5–4

0Reserved Reserved

Software should write this bit to 0.

PC/AT-Compatible Direct-Mapped Registers 2-45

Keyboar d/Mous e Interfac e Output Buffer I/O Address 0060h

Programming Notes

This port is typically inside the external processor that is used to implement the SCP (System Control

Processor) on a PC/AT Compatible system. Although an entire SCP is not implemented on-board

in this design, some SCP registers are available to support the ÉlanSC400 microcontroller’s

capability of SCP emulation using a matrix keyboard. This PC/AT SCP emulation support register

is only available to be read from this location when the ÉlanSC400 microcontroller’s SCP emulation

feature is enabled via CSC index C1h[3–2].

76543210

Bit SCP_OB[7–0]

Default 00000000

R/W R

Bit Name Function

7–0 SCP_OB[7–0] System Control Processor Output Buffer

Data is read back from the System Control Processor (SCP) through this

port. A read from this port simultaneously clears bit 0 of port 64h and the

keyboard IRQ signal to the PIC (Master 8259, Channel 1). This data can

either be keyboard scan codes, mouse coordinate data, SCP response

codes, or keyboard retu rn codes.

PC/AT-Compatible Direct-Mapped Registers

2-46

PC/AT Keyboard Interface Data Register I/O Address 0060h

Programming Notes

This port is typically inside the external processor that is used to implement the SCP (System Control

Processor) on a PC/AT Compatible system. Although an entire SCP is not implemented on-board

in this design, some SCP registers are available to support the ÉlanSC400 microcontroller’s

capability of SCP emulation using a matrix keyboard. This PC/AT SCP emulation support register

is only available to be read from this location when the ÉlanSC400 microcontroller’s SCP emulation

feature is enabled via CSC index register C1h[3–2].

76543210

Bit SCP_DATA[7–0]

Default 00000000

R/W W

Bit Name Function

7–0 SCP_DATA[7–0] System Control Processor Data

When the PC/XT keyboard interface is disabled via indexed CSC register

C1h[4], writes to this port are interpreted as PC/AT SCP data or

parameters when they follow SCP (System Control Processor) commands

to port 64h that expect parameters. If a previous SCP command that

requires parameters has not been written to port 64h previously, writes to

this po rt are serial iz ed b y t he SC P and sent to the ke yb oard. Writing to thi s

port sets bit 1, clears bit 3 of port 64h.

Writes to this port have no effect if the PC/XT keyboard interface is

enabled.

PC/AT-Compatible Direct-Mapped Registers 2-47

PC/XT Keyboard Data Register I/O Address 0060h

Programming Notes

76543210

Bit XT_DATA[7–0]

Default 00000000

R/W R

Bit Name Function

7–0 XT_DATA[7–0] XT Keyboard Controller Data

When the XT keyboard controller is enabled via indexed ÉlanSC400

microcontroller regis ter C1h[4], scan codes from an XT keyboard are read

from this registe r. The act of readin g data from this re giste r cl ears t he IRQ1

that can be enabled to occur when data is received into the register from

the XT keyboard interface. While the XT keyboard function is enabled, this

the I/O location 60h is used for the AT keyboard interface.

PC/AT-Compatible Direct-Mapped Registers

2-48

System Control Port B/NMI Status Reg ister I/O Address 0061h

Programming Notes

76543210

Bit PERR IOCHCK T2OUT RFD Reserved Reserved SPKD T2G

Default 00x00000

R/W R/W R/W R R R/W R/W R/W R/W

Bit Name Function

7 PERR PC/AT Parity Error Indicator

Not supported (always reads back ‘0b’).

6 IOCHCK PC/AT Channel Check Indicator

Not supported (always reads back ‘0b’).

5T2OUT Timer 2 (Speaker) Output Pin State

This status bi t di rec tly reflects the sta te of the ou tput signa l o f Cha nnel 2 of

the on-boa rd 8254 Programm able Interval Tim er and is sample d before the

gate controlled by bit 1 of this r egister.

0 = T2 output is low

1 = T2 output is high

4RFD DRAM Refresh Indicator

This bit changes state each time a refresh is detected. On the original

PC/AT, the Pro grammable Inte rval Timer Cha nnel 1 outpu t pin was used to

generate the ref resh sign al. As an alte rnativ e in th is des ign, t he dou bled 3 2

KHz clock can be used as the input to a divider to obtain the refresh clock.

This bit tracks the current refresh source, regardless of the refresh

generation source .

3Reserved Reserved

On the original PC/AT, this bit was used to enable I/O channel check.

Although this read/w rite regi ster bit has been i mplemented on this de sign, it

does not c ontrol an ything . For softwar e using this regist er to remain PC /AT

Compatible, read/modify/write operations should preserve this bit.

2Reserved Reserved

On the original PC/AT, this bit was used to enable RAM parity check.

Although this read/w rite regi ster bit has been i mplemented on this de sign, it

does not c ontrol an ything . For softwar e using this regist er to remain PC /AT

Compatible, read/modify/write operations should preserve this bit.

1 SPKD Speaker Data Enable

This bi t c on trol s a s ign al whi ch is AN Ded w ith the outp ut f rom Ti me r 2. The

AND gate output is then used to drive the system speaker.

0 = Do not propagate speaker data

1 = Propagate speaker data

0T2G Timer 2 GATE Input Control

This bit drives the GATE input signal for Channel 2 of the 8254

Programmable Interval Timer which can be used to control the Timer

Channel 2 operation depending on the current timer mode. See the

Programm abl e I nte rval Ti me r Sta t us R eg is ter des cri pti on at direct-m ap pe d

40–42h for more detail on the function of the gate input.

0 = Programmable Interval Timer GATE input is deasserted

1 = Programmable Interval Timer GATE input is asserted

PC/AT-Compatible Direct-Mapped Registers 2-49

PC/AT Keyboard/Mouse Interface Sta tu s Re gister I/O Address 0064h

76543210

Bit KEYPAR KEYRTO KEYTTO KEYENB KEYCMD KEYSYS KEYIBF KEYOBF

Default 00000000

R/W RRRRRRRR

Bit Name Function

7 KEYPAR Keyboard Data Transmission Parity Error

0 =No keyboard serial data parity error occurred

1 =Parity error occurred in the serial data transmission between the

processor within the keyboard and the SCP

There is no real SCP on-board the ÉlanSC400 microcontroller. This bit is

provided for software compat ibility purposes only. SCP emul ation software

can control this bit via the Keyboard Status Register Write Register at

ÉlanSC400 microcontroller configuration index register C5h.

6 KEYRTO Keyboard Data Receive Time-out

0 =No re ceive time-out

1 =Receive time-ou t

A transmission started by the keyboard did not complete.

There is no real SCP on-board the ÉlanSC400 microcontroller. This bit is

provided for software compat ibility purposes only. SCP emul ation software

can control this bit via the Keyboard Status Register Write Register at

ÉlanSC400 microcontroller configuration index register C5h.

5 KEYTTO Transmit Time-out/Mouse Output Buffer Full

When CSC in dex C 0h [0] is set, this bi t is a PC /2 m ou se -co mpatible mo us e

output buffer full flay. When CSC index C0h[0] is cleared, this bit becomes

an emulated keyboard time-out bit. See CSC indexes C0h and C5h for

more detail.

0 =No keyboard to SCP communications time-out or no mouse data

available

1 =Keyboard to SCP communications time-out or mouse data available

When Co nfiguratio n Index Register C 0h[0] = 0 (Trans mit Time-Out) , this bit

indicates that a transmission started by the keyboard was not properly

compl eted; the tr ansmit byte was not clocke d out in the tim e limit. Thi s bit is

set/cleared by AT SCP emulation software via a CSC index register.

When Configuration Index Register C0h[0] = 1 (Mouse Output Buffer Full),

this bi t is automat ica ll y s et when AT SC P emu lation s oftw a re p lac es a byte

in the SC P output buffer u sing the M ouse Outpu t Buffer Exten ded Regi ster.

It is cleared when AT SCP emulation software places a byte in the output

buffer using the Output Buffer Extended Register. In this mode, this bit is

set/cleared automatically by writing to CSC index registers, not by a direct

of th is re gis ter. Wh en bits 0 and 5 are set, th en mous e d ev ic e data is in the

output buffer. If bit 0 is set and bit 5 is cleared then keyboard or command

controller (SCP) response data is in the buffer.

4 KEYENB Keyboard Password Protection Status

0 = Password protected

1 = Not protected

There is no real SCP on-board the ÉlanSC400 microcontroller. This bit is

provided for software compat ibility purposes only. SCP emul ation software

can control this bit via the Keyboard Status Register Write Register at chip

configura tion index registe r C5h.

PC/AT-Compatible Direct-Mapped Registers

2-50

Programming Notes

This port is typically inside the external processor that is used to implement the SCP (System Control

Processor) on a PC/AT Compatible system. Although an entire SCP is not implemented on-board

in this design, some SCP registers are available to support the ÉlanSC400 microcontroller’s

capability of SCP emulation using a matrix keyboard. This PC/AT SCP Emulation Support Register

is only available to be read from this location when the ÉlanSC400 microcontroller’s SCP emulation

feature is enabled via CSC index register C1h[3–2].

3 KEYCMD Command/Data

0 =Between the keyboard command and data ports, the data port at direct

mapped 60h that was last written to

1 =Between the keyboard command and data ports, the command port at

direct-mapped 64h that was last written to

2 KEYSYS System Flag Bit

In a PC/AT-compatible system, this bit reads back the state of the system

flag bit (bit 2) of the SCP’s command byte. This SCP command byte is

stored in location 0 of the on-board SCP RAM of a normal PC/AT system.

This bit w ould normal ly be clear ed by the SCP upon system pow er-up (cold

boot) and would remain that way until the system BIOS enabled the

keyboa rd interface. At t his time , the result of the SCP’s on -board diag nostic

would be written to the system flag bit (1 = pass, 0 = fail). Since BIOS must

alway s enable th e keyb oard in terfa ce before th e syst em flag bit can be set,

BIOS wo ul d re ad thi s b it afte r a res et t o k now whether the res et was a c ol d

reset, or if the reset was initiated by software.

0 =A keyboard diagnostic pass indication has not been posted since SCP/

system cold power-up reset

1 =A keyboard diagnostic pass has been posted since SCP/system cold

power-up reset

There is no real SCP or SCP RAM on-board the ÉlanSC400

microcontroller. This bit is provided for software compatibility purposes

only . SCP emulat ion software can control this bit via t he Keyboard Status

1 KEYIBF Input Buffer Full (Keyboard Input Buffer Status)

0 = Buffer empty (SCP able to receive next command/data byte)

1 = Buffer full (SCP has not read the last command/data byte)

0 KEYOBF Output Buffer Full (Keyboard Output Buffer Status)

0 = SCP (System Control Processor) has no data available for the system

1 = SC P has data available for rea d-back by th e system

When this bit is active, either the keyboard IRQ1 signal to the PIC (master

8259, Channel 1), or the mouse IRQ12 signal to the PIC (slave 8259,

Channel 4) is automatically asserted based upon w hether the data in the

output buffer was from the keyboard or from the mouse. If bit 5 of this

this reg is ter are set, IRQ12 is be ing as se rted to the sl av e PIC . If bit 5 is no t

defined to be mouse output buffer full, then when bit 0 is set IRQ1 is being

asserted to the master PIC. Either IRQ1 or IRQ12 are cleared by reading

port 60h.

PC/AT-Compatible Direct-Mapped Registers 2-51

Keyboard/Mouse Int erface Comma nd Register I/O Address 0064h

Programming Notes

This port is typically inside the external processor that is used to implement the SCP (System Control

Processor) on a PC/AT Compatible system. Although an entire SCP is not implemented on-board

in this design, some SCP registers are available to support the ÉlanSC400 microcontroller’s

capability of SCP emulation using a matrix keyboard. This PC/AT SCP emulation support register

is only available to be read from this location when the ÉlanSC400 microcontroller’s SCP emulation

feature is enabled via CSC index register C1h[3–2].

76543210

Bit KEY_CMD[7–0]

Default 00000000

R/W W

Bit Name Function

7–0 KEY_CMD[7–0] Keyboard Command Register

Write s to this port are in terp reted as key board or mo use co mmand s. Some

commands require parameters which would be written to port 60h. Writing

to this port sets bits 1 and 3 of port 64h.

PC/AT-Compatible Direct-Mapped Registers

2-52

RTC/CMOS RAM Ind ex Registe r I/O Ad dress 0070h

Programming Notes

Bit 7 of this register is the master NMI gate control in a typical PC/AT Compatible system. For various

reason, this bit has been made to reside at CSC index 9Dh[2] on the ÉlanSC400 microcontroller.

Compatibility issues are minimized since the ÉlanSC400 microcontroller does not support generation

of either of the legacy NMI sources (channel check or parity error).

76543210

Bit Reserved CMOSIDX

Default –xxx0000

R/W W

Bit Name Function

7Reserved Reserved

6–0 CMOSIDX CMOS RAM Index

CMOS RAM index to read/write.

PC/AT-Compatible Direct-Mapped Registers 2-53

RTC/CMOS RAM Data Port I/O Address 0071h

Programming Notes

76543210

Bit CMOSDATA

Default xxxxxxxx

R/W W

Bit Name Function

7–0 CMOSDATA RTC/CMOS Data Port

Data to be written or read.

PC/AT-Compatible Direct-Mapped Registers

2-54

General Register I/O Address 0080h

Programming Notes

In the original PC/AT, this register would have been DMA Channel 4 Page Register, but DMA

Channel 4 was used for the cascade function, so this register was not used by the DMA subsystem.

The I/O address 80h, however, was used to send BIOS Power-on Self Test (POST) codes to the

ISA bus where a special card (port 80h card) could display the progress/error codes from BIOS.

Because of this legacy use by BIOS, I/O writes to this internal ÉlanSC400 microcontroller register

automatically go to the ISA bus as well as to an internal storage element for this register. I/O reads

from port 80h come from the internal register only.

Access to this register is not affected by the DMA disable bits in CSC index D0h.

76543210

Bit PORT80[7–0]

Default 00000000

R/W R/W

Bit Name Function

7–0 PORT80[7–0] General Purpose R/W Register

PC/AT-Compatible Direct-Mapped Registers 2-55

DMA Channel 2 Page Registe r I/O Ad dress 0081h

Programming Notes

The ÉlanSC400 microcontroller is capable of performing 26-bit DMA accesses using the extended

DMA page registers that reside in CSC index registers D9h and DAh.

Access to this register is not affected by the DMA disable bits in CSC index D0h.

76543210

Bit DMA2MAR[23–16]

Default 00000000

R/W R/W

Bit Name Function

7–0 DMA2MAR[23–16] DMA Channel 2 Memory Address Bits [A23–A16]

PC/AT-Compatible Direct-Mapped Registers

2-56

DMA Channel 3 Page Registe r I/O Ad dress 0082h

Programming Notes

The ÉlanSC400 microcontroller is capable of performing 26-bit DMA accesses using the extended

DMA page registers that reside in CSC index registers D9h and DAh.

Access to this register is not affected by the DMA disable bits in CSC index D0h.

76543210

Bit DMA3MAR[23–16]

Default 00000000

R/W R/W

Bit Name Function

7–0 DMA3MAR[23–16] DMA Channel 3 Memory Address Bits [A23–A16]

PC/AT-Compatible Direct-Mapped Registers 2-57

DMA Channel 1 Page Registe r I/O Ad dress 0083h

Programming Notes

The ÉlanSC400 microcontroller is capable of performing 26-bit DMA accesses using the extended

DMA page registers that reside in CSC index registers D9h and DAh.

Access to this register is not affected by the DMA disable bits in CSC index D0h.

76543210

Bit DMA1MAR[23–16]

Default 00000000

R/W R/W

Bit Name Function

7–0 DMA1MAR[23–16] DMA Channel 1 Memory Address Bits [A23–A16]

PC/AT-Compatible Direct-Mapped Registers

2-58

General Register I/O Address 0084h

Programming Notes

Access to this register is not affected by the DMA disable bits in CSC index D0h.

Writes to this port go both to an internal register and externally to the VL or ISA bus. Reads from

this port produce an internal cycle only and return the contents of the internal register.

76543210

Bit PORT84[7–0]

Default 00000000

R/W R/W

Bit Name Function

7–0 PORT84[7–0] General Purpose R/W Register

PC/AT-Compatible Direct-Mapped Registers 2-59

General Register I/O Address 0085h

Programming Notes

Access to this register is not affected by the DMA disable bits in CSC index D0h.

Writes to this port go both to an internal register and externally to the VL or ISA bus. Reads from

this port produce an internal cycle only and return the contents of the internal register.

76543210

Bit PORT85[7–0]

Default 00000000

R/W R/W

Bit Name Function

7–0 PORT85[7–0] General Purpose R/W Register

PC/AT-Compatible Direct-Mapped Registers

2-60

General Register I/O Address 0086h

Programming Notes

Access to this register is not affected by the DMA disable bits in CSC index D0h.

Writes to this port go both to an internal register and externally to the VL or ISA bus. Reads from

this port produce an internal cycle only and return the contents of the internal register.

76543210

Bit PORT86[7–0]

Default 00000000

R/W R/W

Bit Name Function

7–0 PORT86[7–0] General Purpose R/W Register

PC/AT-Compatible Direct-Mapped Registers 2-61

DMA Channel 0 Page Registe r I/O Ad dress 0087h

Programming Notes

The ÉlanSC400 microcontroller is capable of performing 26-bit DMA accesses using the extended

DMA page registers that reside in CSC index registers D9h and DAh.

Access to this register is not affected by the DMA disable bits in CSC index D0h.

Writes to this port go both to an internal register and externally to the VL or ISA bus. Reads from

this port produce an internal cycle only and return the contents of the internal register.

76543210

Bit DMA0MAR[23–16]

Default 00000000

R/W R/W

Bit Name Function

7–0 DMA0MAR[23–16] DMA Channel 0 Memory Address Bits [A23–A16]

PC/AT-Compatible Direct-Mapped Registers

2-62

General Register I/O Address 0088h

Programming Notes

Access to this register is not affected by the DMA disable bits in CSC index D0h.

Writes to this port go both to an internal register and externally to the VL or ISA bus. Reads from

this port produce an internal cycle only and return the contents of the internal register.

76543210

Bit PORT88[7–0]

Default 00000000

R/W R/W

Bit Name Function

7–0 PORT88[7–0] General Purpose R/W Register

PC/AT-Compatible Direct-Mapped Registers 2-63

DMA Channel 6 Page Registe r I/O Ad dress 0089h

Programming Notes

The ÉlanSC400 microcontroller is capable of performing 26-bit DMA accesses using the extended

DMA page registers that reside in CSC index registers D9h and DAh.

Access to this register is not affected by the DMA disable bits in CSC index D0h.

76543210

Bit DMA6MAR[23–17] Reserved

Default 00000000

R/W R/W R/W

Bit Name Function

7–1 DMA6MAR[23–17] DMA Channel 6 Memory Address Bits [A23–A17] (16-bit channel)

0Reserved Reserved

Not u sed fo r D M A m emory a ddress g ene rati on . So ftw are s hou ld wr ite th is

bit to 0.

PC/AT-Compatible Direct-Mapped Registers

2-64

DMA Channel 7 Page Registe r I/O Address 008Ah

Programming Notes

The ÉlanSC400 microcontroller is capable of performing 26-bit DMA accesses using the extended

DMA page registers that reside in CSC index registers D9h and DAh.

Access to this register is not affected by the DMA disable bits in CSC index D0h.

76543210

Bit DMA7MAR[23–17] Reserved

Default 00000000

R/W R/W R/W

Bit Name Function

7–1 DMA7MAR[23–17] DMA Channel 7 Memory Address Bits [A23–A17] (16-bit channel)

0Reserved Reserved

Not u sed fo r D M A m emory a ddress g ene rati on . So ftw are s hou ld wr ite th is

bit to 0.

PC/AT-Compatible Direct-Mapped Registers 2-65

DMA Channel 5 Page Registe r I/O Address 008Bh

Programming Notes

Access to this register is not affected by the DMA disable bits in CSC index D0h.

76543210

Bit DMA5MAR[23–17] Reserved

Default 00000000

R/W R/W R/W

Bit Name Function

7–1 DMA5MAR[23–17] DMA Channel 5 Memory Address Bits [A23–A17] (16-bit channel)

0Reserved Reserved

Not u sed fo r D M A m emory a ddress g ene rati on . So ftw are s hou ld wr ite th is

bit to 0.

PC/AT-Compatible Direct-Mapped Registers

2-66

General Register I/O Address 008Ch

Programming Notes

Access to this register is not affected by the DMA disable bits in CSC index D0h.

Writes to this port go both to an internal register and externally to the VL or ISA bus. Reads from

this port produce an internal cycle only and return the contents of the internal register.

76543210

Bit PORT8C[7–0]

Default 00000000

R/W R/W

Bit Name Function

7–0 PORT8C[7–0] General Purpose R/W Register

PC/AT-Compatible Direct-Mapped Registers 2-67

General Register I/O Address 008Dh

Programming Notes

Access to this register is not affected by the DMA disable bits in CSC index D0h.

Writes to this port go both to an internal register and externally to the VL or ISA bus. Reads from

this port produce an internal cycle only and return the contents of the internal register.

76543210

Bit PORT8D[7–0]

Default 00000000

R/W R/W

Bit Name Function

7–0 PORT8D[7–0] General Purpose R/W Register

PC/AT-Compatible Direct-Mapped Registers

2-68

General Register I/O Address 008Eh

Programming Notes

Access to this register is not affected by the DMA disable bits in CSC index D0h.

Writes to this port go both to an internal register and externally to the VL or ISA bus. Reads from

this port produce an internal cycle only and return the contents of the internal register.

76543210

Bit PORT8E[7–0]

Default 00000000

R/W R/W

Bit Name Function

7–0 PORT8E[7–0] General Purpose R/W Register

PC/AT-Compatible Direct-Mapped Registers 2-69

General Register I/O Address 008Fh

Programming Notes

This general register is slightly different from the other direct-mapped general registers. All I/O

accesses to port 8Fh go to the internal register only. Therefore, no VL or ISA bus cycles are generated

on I/O writes to this port.

76543210

Bit PORT8F[7–0]

Default 00000000

R/W R/W

Bit Name Function

7–0 PORT8F[7–0] General Purpose R/W Register

PC/AT-Compatible Direct-Mapped Registers

2-70

System Control Port A Register (PS/2 Compatibility Port) I/ O Ad dress 0092h

Programming Notes

76543210

Bit Reserved AGA20 ACPURESET

Default 00000000

R/W R/W R/W

Bit Name R/W Function

7–2 Reserved Reserved

Software should write these bits to 0.

1AGA20 R/WAlternate A20 Gate Control

This bit can be used to cause the same type of masking of the

CPU A20 signal that was historically performed by an external

SCP (System Control Processor) in a PC/AT Compatible system,

but much faster:

0 =Deasserts the forcing of the propagation of the A20 signal via

this particular control

1 =Forces the A20 signal to propagate

For software compatibility and other reasons, there are several

sources of GateA20 control. These controls are effectively ORed

together with the output of the OR gate driving the Enhanced

Am486 m icroprocesso r A20M input . Therefore, A2 0 will propag ate

if any of the independent sources are forcing A20 to propagate.

0 ACPURESET R/W Alternate CPU Core Reset Control

Changing this bit from ‘0b’ to ‘1b’ will pulse the CPU SRESET

signal. This will cause the same type of CPU core reset to occur

that was historically performed by an external SCP (System

Control Processor) in a PC/AT Compatible system, but much

faster. The 486 cache state, SMBASE, and ÉlanSC400

microcontroller indexed or direct-mapped registers will not be

affected as a result of this soft reset. Following the reset, this bit

will re main set un til sof tware clears it. Th is feat ure can b e used by

the BIOS as an indication that port 92h was used to generate the

reset.

0 = Do not generate a soft reset to the CPU core

1 = Pulse the SRESET CPU signal

PC/AT-Compatible Direct-Mapped Registers 2-71

Slave 8259 Interrupt Request Register I/O Address 00A0h

Programming Notes

Thi s r egi st e r prov id es a re a l-time status of the IRQ inputs to the Slave 8259. It is accessed by first

writing a value of 0Ah to port A0h followed by a read-back of port A0h.

76543210

Bit IR15 IR14 IR13 IR12 IR11 IR10 IR9 IR8

Default xxxxxxxx

R/W RRRRRRRR

Bit Name Function

7IR15 Interrupt Request 15

0 = IRQ15 is not asserted

1 = IRQ15 is asserted

6IR14 Interrupt Request 14

0 = IRQ14 is not asserted

1 = IRQ14 is asserted

5IR13 Interrupt Request 13

0 = IRQ13 is not asserted

1 = IRQ13 is asserted

4IR12 Interrupt Request 12

0 = IRQ12 is not asserted

1 = IRQ12 is asserted

3IR11 Interrupt Request 11

0 = IRQ11 is not asserted

1 = IRQ11 is asserted

2IR10 Interrupt Request 10

0 = IRQ10 is not asserted

1 = IRQ10 is asserted

1IR9 Interrupt Request 9

0 = IRQ9 is not asserted

1 = IRQ9 is asserted

0IR8 Interrupt Request 8

0 = IRQ8 is not asserted

1 = IRQ8 is asserted

PC/AT-Compatible Direct-Mapped Registers

2-72

Slave 8259 In-Service Reg ister I/O Address 00A0h

Programming Notes

The Slave In-Service Register (ISR) is accessed by writing a value of 0Bh to port A0h followed by

a read-back from port A0h.

76543210

Bit IS15 IS14 IS13 IS12 IS11 IS10 IS9 IS8

Default xxxxxxxx

R/W RRRRRRRR

Bit Name Function

7IS15 IRQ15 In-Service

0 = IRQ15 is not being serviced

1 = IRQ15 is being serviced

6IS14 IRQ14 In-Service

0 = IRQ14 is not being serviced

1 = IRQ14 is being serviced

5IS13 IRQ13 In-Service

0 = IRQ13 is not being serviced

1 = IRQ13 is being serviced

4IS12 IRQ12 In-Service

0 = IRQ12 is not being serviced

1 = IRQ12 is being serviced

3IS11 IRQ11 In-Service

0 = IRQ11 is not being serviced

1 = IRQ11 is being serviced

2IS10 IRQ10 In-Service

0 = IRQ10 is not being serviced

1 = IRQ10 is being serviced

1IS9 IRQ9 In-Service

0 = IRQ9 is not being serviced

1 = IRQ9 is being serviced

0IS8 IRQ8 In-Service

0 = IRQ8 is not being serviced

1 = IRQ8 is being serviced

PC/AT-Compatible Direct-Mapped Registers 2-73

Slave 8259 Initial ization Co ntrol Wor d 1 Registe r I/O Ad dress 00A0h

76543210

Bit Reserved SLCT_ICW1 LTIM ADI SNGL IC4

Default xxxxxxxx

R/W W WWWWW

Bit Name Function

7–5 Reserved Reserved

Must all be written to 0.

4 SLCT_ICW1 Initializa tion Control Word 1 Select

Must be wri tten to 1 to acces s ICW1 (D4 = 1 m ean s th e IO W to po rt A0h is

Initializati on Control Word 1).

3 LTIM Level Triggered Interrupt Mode

0 = Edge sensiti v e IRQ detection

1 = Level sensitive IRQ detection

2ADI Address Interval

Has no effect when the 8259 is used in x86 mode:

0 = Interrupt vectors are separated by 8 locations

1 = Interrupt vectors are separated by 4 locations

In the ÉlanSC400 microcontroller design, this PC/AT Compatible bit is

internally fixed to ‘1b’.

1SNGL Single 8259

If this bit is set, the internal register pointer will skip ICW3 and point to

ICW4, i f ICW4 wa s selected to be prog rammed via bit 0 of this registe r. See

the explanation for bit 0 of this register:

0 = Cascade mode, ICW3 will be expected

1 = Single 8259 in the system, ICW3 will not be expected

In the ÉlanSC400 microcontroller design, this PC/AT Compatible bit is

internally fixed to ‘0b’.

0IC4 Initializa tion Control Word 4

ICW4 is required. The 8259’s initialization control word (ICW) Registers

1–4 ar e progra mmed in seq uence . Writin g to port A0h wi th bit 4 = 1 cau ses

the inte rnal IC W1 Reg is ter to be w rit ten, and res et s t he PI C ’s internal st at e

machine and ICW register pointer. Slave ICW2–4 are programmed via port

A1. Each ti me A1 h is writt en to (fo llo wing ICW 1), the re gis ter po inter points

to the next internal ICW register. ICW1 and ICW2 must always be

programm ed, b ut ICW3 and ICW4 ne ed on ly b e prog ramme d under c ertain

circumstances. This bit determines whether ICW4 is required to be

explicitly programmed, or whether a value of 00h will serve for ICW4. If

ICW4 is selected to be programmed, the register pointer will point to ICW4

after ICW3, and the PIC will expect software to provide an initialization

value for it.

0 =Ini tial ization Control Word 4 is cleared by writ ing I nitialization Control

Word 1, ICW4 will not be expe cted by the PIC

1 =ICW4 is not cleared by this write t o Initialization Con trol Word 1, and

software is expected to initialize IC W4

In the ÉlanSC400 microcontroller, this bit is internally fixed to ‘1b’.

PC/AT-Compatible Direct-Mapped Registers

2-74

Programming Notes

I/O writes to port A0h access different slave PIC registers based on bits 4–3 of the data that is written.

See the following table:

Bit 4 Bit 3 Register Accessed

00OCW2

01OCW3

1xICW1

PC/AT-Compatible Direct-Mapped Registers 2-75

Slave 8259 Operation Control Word 2 Register I/O Address 00A0h

Programming Notes

I/O writes to port A0h access different slave PIC registers based on bits 4–3 of the data that is written.

See the following table:

76543210

Bit R

EOI SLCT_ICW1 IS_OCW3 LS[2–0]

Default xxxxxxxx

R/W WWWW

Bit Name Function

7–5 R

EOI

IRQ EOI and Priority Rotation Controls

0 0 0 = Rotate in auto EOI mode (clear)

0 0 1 = Non-specific EOI

0 1 0 = No operation

0 1 1 = Specific EO I

1 0 0 = Rotate in auto EOI mode (set)

1 0 1 = Rotate on non-specific EOI command

1 1 0 = Set priority command

1 1 1 = Rotate on specific EOI command

4 SLCT_ICW1 Initializa tion Control Word 1 Select

Software should write this bit to 0 to access OCW2 or OCW3.

3IS_OCW3 Access is OCW3

An I/O write to port A0h with this bit set indicates that OCW3 is to be

accessed.

2–0 LS[2–0] Specific EOI Level Select

Interrupt level which is acted upon when the SL bit = ‘1b’ (see bits 7–5]

below:

0 0 0 = IRQ8

0 0 1 = IRQ9

0 1 0 = IRQ10

0 1 1 = IRQ11

1 0 0 = IRQ12

1 0 1 = IRQ13

1 1 0 = IRQ14

1 1 1 = IRQ15

Bit 4 Bit 3 Register Accessed

00OCW2

01OCW3

1xICW1

PC/AT-Compatible Direct-Mapped Registers

2-76

Slave 8259 Operation Control Word 3 Register I/O Address 00A0h

Programming Notes

I/O writes to port A0h access different slave PIC registers based on bits 4–3 of the data that is written.

See the following table:

76543210

Bit Reserved ESMM

SMM SLCT_ICW1 IS_OCW3 P RR

RIS

Default xxxxxxxx

R/W W WWW W

Bit Name Function

7Reserved Reserved

Software should write this bit to 0.

6–5 ESMM

SMM Special Mask Mode

0 x = No operation

1 0 = Reset special mask

1 1 = Set special mask

In the ÉlanSC 400 micro controlle r des ign, the ESM M bit is i nternal ly f ixed to

‘1b’.

4 SLCT_ICW1 Initializa tion Control Word 1 Select

Software must write this bit to 0 to access OCW2 or OCW3.

3IS_OCW3 Access is OCW3

An I/O write to port A0h with this bit set indicates that OCW3 is to be

accessed.

2P PIC Poll Command

A system design can choose to use the PIC in a non-interrupting mode. In

this case, the interrupt controller can be polled for the status of pending

interrupts. In order to support this PC/AT incompatible mode of operation,

the PIC supports a special poll command which is invoked by writing

OCW3 with this bit set.

0 = Not poll command

1 = Poll command

1–0 RR

RIS Status Register Select

0 0 = No change from last state

0 1 = No change from last state

1 0 = Next port A0h read will return Interrupt Request Register (IRR)

1 1 = Next port A0h read will return In-Service Register (ISR)

Bit 4 Bit 3 Register Accessed

00OCW2

01OCW3

1xICW1

PC/AT-Compatible Direct-Mapped Registers 2-77

Slave 8259 Initial ization Co ntrol Wor d 2 Registe r I/O Ad dress 00A1h

Programming Notes

76543210

Bit T7–T3 A10–A8

Default xxxxxxxx

R/W WW

Bit Name Function

7–3 T7–T3 Bits 7–3 of Base Interrupt Vector Number for this PIC

Bits 2–0 are concatenated by PIC based on IRQ level. For example, these

bits will be programmed to 00001b for the master PIC (IRQ0 generates int

8), and 01110b for the slave PIC (IRQ8 corresponds to int 70h) in a PC/AT

Compatible system.

2–0 A10–A8 A10–A8 of Interrupt Vector

Software should write these to 0 in a PC/AT-compatible system.

PC/AT-Compatible Direct-Mapped Registers

2-78

Slave 8259 Initial ization Co ntrol Wor d 3 Registe r I/O Ad dress 00A1h

Programming Notes

76543210

Bit Reserved ID2–ID0

Default xxxxxxxx

R/W W

Bit Name Function

7–3 Reserved Reserved

Software should write these bits to 0.

2–0 ID2–ID0 Slave PIC ID 2–0

Program these bits with the binary slave 8259 ID (000b–111b) so that it

responds to the proper address on the cascade bus for a PC/AT

Compatible system.

In this design, these bits are internally fixed to ‘010b’.

PC/AT-Compatible Direct-Mapped Registers 2-79

Slave 8259 Initial ization Co ntrol Wor d 4 Registe r I/O Ad dress 00A1h

Programming Notes

76543210

Bit Reserved SFNM BUF

M/S AEOI PM

Default xxxxxxxx

R/W W WWWW

Bit Name Function

7–5 Reserved Reserved

Software should write these bits to 0.

4SFNM Special Fully Nested Mode Enable

0 = Normal nested mode

1 = Special f ully nested mode

In the ÉlanSC400 microcontroller design, this PC/AT-compatible bit is

internally fixed to ‘0b’.

3–2 BUF

M/S Buffered Mode and Master/Slave Select

0 x = Non buffered mode

1 0 = Buffered mode/slave

1 1 = Buffered mode/master

In the ÉlanSC400 microcontroller, these PC/AT-compatible bits are

internally fixed to ‘00b’.

1 AEOI Automatic EOI Mode

0 =Normal EOI

Interrupt handler must send an End of Interrupt command to the PIC(s)

1 =Auto EOI

EOI is automatically performed after the second INTA signal from the

CPU

In the ÉlanSC400 microcontroller design, this PC/AT-compatible bit is

internally fixed to ‘0b’.

0PM Micro pr oce sso r Mod e

0 = 8080/8085 mode

1 = 8086 mode

In the ÉlanSC400 microcontroller design, this PC/AT-compatible bit is

internally fixed to ‘1b’.

PC/AT-Compatible Direct-Mapped Registers

2-80

Slave 8259 Interrupt Mask Reg ister I/O Ad dress 00A1h

(also known as Operat ion Control Word 1)

Programming Notes

76543210

Bit IM15 IM14 IM13 IM12 IM11 IM10 IM9 IM8

Default xxxxxxxx

R/W R/W R/W R/W R/W R/W R/W R/W R/W

Bit Name Function

7IM15 IRQ15 Mask

0 = Unmask IRQ15

1 = Mask IRQ15

6IM14 IRQ14 Mask

0 = Unmask IRQ14

1 = Mask IRQ14

5IM13 IRQ13 Mask

0 = Unmask IRQ13

1 = Mask IRQ13

4IM12 IRQ12 Mask

0 = Unmask IRQ12

1 = Mask IRQ12

3IM11 IRQ11 Mask

0 = Unmask IRQ11

1 = Mask IRQ11

2IM10 IRQ10 Mask

0 = Unmask IRQ10

1 = Mask IRQ10

1IM9 IRQ9 Mask

0 = Unmask IRQ9

1 = Mask IRQ9

0IM8 IRQ8 Mask

0 = Unmask IRQ8

1 = Mask IRQ8

PC/AT-Compatible Direct-Mapped Registers 2-81

Master DMA Channel 4 Memory Address Register I/O Address 00C0h

Programming Notes

76543210

Bit DMA4MAR[16–1]

Default xxxxxxxx

R/W R/W

Bit Name Function

7–0 DMA4MAR[16–1] DMA Channel 4 Memory Address

Generically speaking, this register holds the lower 16 bits of memory

address for DMA Channel 4. Since the DREQ and DACK signals for this

DMA channel are used to cascade to the slave DMA controller in PC/AT

architecture, DMA Channel 4 is not used directly for DMA transfers, and

this register has no real function. It is merely documented for

completeness. For the same reason, there is no corresponding page

PC/AT-Compatible Direct-Mapped Registers

2-82

Master DMA Channel 4 Transfer Count Register I/O Address 00C2h

Programming Notes

76543210

Bit DMA4TC[15–0]

Default xxxxxxxx

R/W R/W

Bit Name Function

7–0 DMA4TC[15–0] DMA Channel 4 Transfer Count (16-Bit Register)

Generically speaking, this register holds the 16-bit transfer count for DMA

Channel 4. This register is written/read as two successive bytes for DMA

Channel 4. Since the DREQ and DACK signals for this DMA channel are

used to cascade to the slave DMA controller in PC/AT architecture, DMA

Channel 4 is not used directly for DMA transfers, and this register has no

real function. It is merely documented for completeness.

PC/AT-Compatible Direct-Mapped Registers 2-83

Master DMA Channel 5 Memory Address Register I/O Address 00C4h

Programming Notes

The ÉlanSC400 microcontroller is capable of performing 26-bit DMA accesses using the extended

DMA page registers that reside in CSC index registers D9h and DAh.

76543210

Bit DMA5MAR[16–1]

Default xxxxxxxx

R/W R/W

Bit Name Function

7–0 DMA5MAR[16–1] Lower 16-bits of DMA Channel 5 Memory Address

This register is written/read via two successive I/O accesses to/from this

port (alw ays low byt e follo wed by hig h byte imme diatel y foll owin g a reset o f

the by te pointer at direc t-mapped I/O address D8h). Whe n set up for PC/AT

compatibility (16-bit DMA transfers on the master DMA controller), this

word-aligned transfers. Because of this, software must load this register

with the desired memory address divided by 2. Use in conjunction with

DMA Page Register for Channel 5 (I/O 8Bh) to form 24-bit memory

address.

PC/AT-Compatible Direct-Mapped Registers

2-84

Master DMA Channel 5 Transfer Count Register I/O Address 00C6h

Programming Notes

76543210

Bit DMA5TC[15–0]

Default xxxxxxxx

R/W

Bit Name Function

7–0 DMA5TC[15–0] DMA Channel 5 Transfer Count (16-Bit Register)

This register is written/read via two successive I/O accesses to/from this

port (alw ays low byt e follo wed by hig h byte imme diatel y foll owin g a reset o f

the byte pointer at direct-mapped I/O address D8h). The actual number of

transfers will be one more than specified by this register. When set up for

PC/AT compatibility (16-bit DMA transfers on the master DMA controller),

each tran sfer will be one word. Thu s, a transfe r count of FF FFh will res ult in

a transfer of 128 Kbytes.

PC/AT-Compatible Direct-Mapped Registers 2-85

Master DMA Channel 6 Memory Address Register I/O Address 00C8h

Programming Notes

The ÉlanSC400 microcontroller is capable of performing 26-bit DMA accesses using the extended

DMA page registers that reside in CSC index registers D9h and DAh.

76543210

Bit DMA6MAR[16–1]

Default xxxxxxxx

R/W R/W

Bit Name Function

7–0 DMA6MAR[16–1] Lower 16-bits of DMA Channel 6 Memory Address

This register is written/read via two successive I/O accesses to/from this

port (alw ays low byt e follo wed by hig h byte imme diatel y foll owin g a reset o f

the by te pointer at direc t-mapped I/O address D8h). Whe n set up for PC/AT

compatibility (16-bit DMA transfers on the master DMA controller), this

word-aligned transfers. Because of this, software must load this register

with the desired memory address divided by 2. Use in conjunction with

DMA Page Register for Channel 6 (I/O 89h) to form 24-bit memory

address.

PC/AT-Compatible Direct-Mapped Registers

2-86

Master DMA Channel 6 Transfer Count Register I/O Addr ess 00CAh

Programming Notes

76543210

Bit DMA6TC[15–0]

Default xxxxxxxx

R/W R/W

Bit Name Function

7–0 DMA6TC[15–0] DMA Channel 6 Transfer Count (16-Bit Register)

This register is written/read via two successive I/O accesses to/from this

port (alw ays low byt e follo wed by hig h byte imme diatel y foll owin g a reset o f

the byte pointer at direct-mapped I/O address D8h). The actual number of

transfers will be one more than specified by this register. When set up for

PC/AT compatibility (16-bit DMA transfers on the master DMA controller),

each tran sfer will be one word. Thu s, a transfe r count of FF FFh will res ult in

a transfer of 128 Kbytes.

PC/AT-Compatible Direct-Mapped Registers 2-87

Master DMA Channel 7 Memory Address Register I/O Addr ess 00CCh

Programming Notes

The ÉlanSC400 microcontroller is capable of performing 26-bit DMA accesses using the extended

DMA page registers that reside in CSC index registers D9h and DAh.

76543210

Bit DMA7MAR[16–1]

Default xxxxxxxx

R/W R/W

Bit Name Function

7–0 DMA7MAR[16–1] Lower 16-bits of DMA Channel 7 Memory Address

This register is written/read via two successive I/O accesses to/from this

port (alw ays low by te follo wed by high byt e immedia tel y followi ng a reset

of the byte pointer at direct-mapped I/O address D8h). When set up for

PC/AT compatibility (16-bit DMA transfers on the master DMA

controller), this register hold address bits [16–1]. Address bit 0 is always

‘0b’ for th ese word-ali gned trans fers. Because o f this, soft ware must lo ad

this register with the desired memory address divided by 2. Use in

conjunction with DMA Page Register for Channel 7 (I/O 8Ah) to form

24-bit memory address.

PC/AT-Compatible Direct-Mapped Registers

2-88

Master DMA Channel 7 Transfer Count Register I/O Addre ss 00CEh

Programming Notes

76543210

Bit DMA7TC[15–0]

Default xxxxxxxx

R/W R/W

Bit Name Function

7–0 DMA7TC[15–0] DMA Channel 7 Transfer Count (16-Bit Register)

This register is w ritt en/read as tw o su cc es si ve bytes . T he actual nu mber of

transfers will be one more than specified by this register. When set up for

PC/AT compatibility (16-bit DMA transfers on the master DMA controller),

each tran sfer will be one word. Thu s, a transfe r count of FF FFh will res ult in

a transfer of 128 Kbytes.

PC/AT-Compatible Direct-Mapped Registers 2-89

Master DMA Status Register for Channels 4–7 I/O Addr ess 00D0h

Programming Notes

Bits 3–0 of this register are read/reset. Any read from this direct mapped port clears all of these bits.

76543210

Bit DMAR7 DMAR6 DMAR5 DMAR4 TC7 TC6 TC5 TC4

Default 00000000

R/W RRRRRRRR

Bit Name Function

7DMAR7 Channel 7 DMA Request

0 = Not pending

1 = Pending

6DMAR6 Channel 6 DMA Request

0 = Not pending

1 = Pending

5DMAR5 Channel 5 DMA Request

0 = Not pending

1 = Pending

4DMAR4 Channel 4 DMA Request

0 = Not pending

1 = Pending

3TC7 Channel 7 Terminal Count

0 = Not detected

1 = Detected

2TC6 Channel 6 Terminal Count

0 = Not detected

1 = Detected

1TC5 Channel 5 Terminal Count

0 = Not detected

1 = Detected

0TC4 Channel 4 Terminal Count

0 = Not detected

1 = Detected

PC/AT-Compatible Direct-Mapped Registers

2-90

Master DMA Control Register for Channels 4–7 I/O Addr ess 00D0h

76543210

Bit DAKSEN DRQSEN WRTSEL PRITYPE COMPTIM ENADMA ADRHEN MEM2MEM

Default 00000000

R/W WWWWWWWW

Bit Name Function

7 DAKSEN DACK(n) Sense

This bit controls the polarity of all DACK outputs from the master DMA

controller:

0 = Asserted Low

1 = Asserted high

System logic external to the DMA controller expects the DMA controller to

drive active Low DACK outputs. This bit must be written to ‘0b’ for proper

system operation.

6 DRQSEN DREQ(n) Sense

This bit controls the polarity of all DREQ inputs to the master DMA

controller:

0 = Asserted High

1 = Asserted Low

System logic external to the DMA controller expects the DMA controller to

respond to active High DREQ inputs. This bit must be written to ‘0b’ for

proper system operation.

5 WRTSEL Write Selection Control

0 = Late wri te selection

1 = Extended (ear ly) write selection

Enabling this feature will result in timing changes on the ISA bus that can

viol ate the ISA s pecification.

4 PRITYPE Priority Type

0 = Fixed priority

1 = Rotating priority

3 COMPTIM Compressed Timing

0 = Nor mal t iming

1 = Compressed timing

Enabling this feature will result in timing changes on the ISA bus that can

viol ate the ISA s pecification.

2 ENADMA Enable DMA Controller

0 = Enabled

1 = DMA requests are ignored but DMA registers are available to the CPU

The DMA controller must be disabled prior to programming it in order to

prevent unintended transfers from occurring during the DMA controller

programming operation. If an I/O DMA initiator as sert s DRE Q while the

DMA cont roller is di sa ble v ia thi s bit, abnormal sys tem o pera tio n c an oc c ur.

PC/AT-Compatible Direct-Mapped Registers 2-91

Programming Notes

1 ADRHEN Enable Channel 4 Address Hold Control (not supported)

IF bit 0 = 1, then:

0 =Disabled, Channel 0 memory address changes for each

memor y-to-memory transfer

1 =Enabled, Channel 0 memory address does not change for each

memory-to-memory transfer (not supported by the system)

ELSE this bit does nothing.

Since bit 0 should always be written to 0, this bit will be a don’t care after

the DMA controller has been initialized.

0 MEM2MEM Enable Memory-to-Memory Transfer

0 = Disabled

1 = Enabled (not supported by the system)

Memory-to-memory DMA support is not provided in an AT compatible

system. This bit should always be written to 0.

Bit Name Function

PC/AT-Compatible Direct-Mapped Registers

2-92

Master Software DR Q(n) Request Regi ster I/O Address 00D2h

Programming Notes

76543210

Bit Reserved REQDMA REQSEL1

REQSEL0

Default 00000000

R/W WW

Bit Name Function

7–3 Reserved Reserved

Software should write these bits to 0.

2 REQDMA DMA Request

0 = Reset request bit for channel selected by bits 1–0

1 = Set requ est bit for chann el selected by bits 1–0

1–0 REQSEL1

REQSEL0 DMA Channel Select

Bits 1–0 select which DMA channel will latch bit 2 internally to assert or

deassert a DMA request via software:

0 0 = Mask/unmask DMA Channel 4 mask per the REQDMA bit

0 1 = Mask/unmask DMA Channel 5 mask per the REQDMA bit

1 0 = Mask/unmask DMA Channel 6 mask per the REQDMA bit

1 1 = Mask/unmask DMA Channel 7 mask per the REQDMA bit

PC/AT-Compatible Direct-Mapped Registers 2-93

Master DMA Mask Register Channels 4–7 I/O Addr ess 00D4h

Programming Notes

The same DMA channel masks can be controlled via DMA registers D4h, DCh, and DEh.

76543210

Bit Reserved CHMASK MSKSEL1

MSKSEL0

Default 00000000

R/W WW

Bit Name Function

7–3 Reserved Reserved

Software should write these bits to 0.

2 CHMASK DMA Channel Mask

0 = Clear mask bit for channel selected by bits 1–0

1 = Set mask bit for channel selected by bits 1–0

1–0 MSKSEL1

MSKSEL0 DMA Channel Mask Select

Bits 1–0 select which DMA channel will latch bit 2 internally to mask or

unmask the DRQ signal into the specified DMA channel:

0 0 = Set/reset DMA Channel 4 mask per the CHMASK bit

0 1 = Set/reset DMA Channel 5 mask per the CHMASK bit

1 0 = Set/reset DMA Channel 6 mask per the CHMASK bit

1 1 = Set/reset DMA Channel 7 mask per the CHMASK bit

PC/AT-Compatible Direct-Mapped Registers

2-94

Master DMA Mode Register Channels 4–7 I/O Addr ess 00D6h

Programming Notes

76543210

Bit TRNMOD ADDDEC AINIT OPSEL1

OPSEL0 MODSEL1

MODSEL0

Default ????????

R/W WWWW W

Bit Name Function

7–6 TRNMOD Transfer Mode

0 0 = Demand transfer mode

0 1 = Single transfer mode

1 0 = Block transfer mode

1 1 = Cascade mode

5 ADDDEC DMA Address Mode Decrement

0 = Increment the DMA memory address after each transfer

1 = Decrement the DMA memory address after each transfer

4 AINIT Automatic Initialization Control

If enabled, the base address and transfer count registers are restored to

the values they contained prior to performing the last DMA transfer. The

channel selected by bits 0–1 of this register is then ready to perform

another DMA transfer without processor intervention as soon as the next

DRQ is detected.

0 = Aut o initialization disabled

1 = Auto initialization enabled

3–2 OPSEL1

OPSEL0 Operation Select

0 0 =Verify mode

DMA controller acts normally except that no I/O or memory

commands are generated, and no data is transferred

0 1 =Write transfer

Data will be transferred from a DMA-capable I/O device into system

memory

1 0 =Read transfer

Data will be transferred from system memory to a DMA-capable I/O

device

1 1 =Reserved

1–0 MODSEL1

MODSEL0 DMA Channel Select

Bits 7–2 of this register are latched internally for each channel. Bits 0–1

determine which of the channels will be programmed by the write to port

D6h as follows:

0 0 = Select Channel 4

0 1 = Select Channel 5

1 0 = Select Channel 6

1 1 = Select Channel 7

PC/AT-Compatible Direct-Mapped Registers 2-95

Master DMA Clear Byte Pointer Register I/O Address 00D8h

Programming Notes

76543210

Bit MASTR_CBP

Default 00000000

R/W W

Bit Name Function

7–0 MASTR_CBP Master DMA Clear Byte Pointer

The DMA Controller contains some 16-bit registers which are accessed by

writing or reading consecutive 8-bit values to the same direct-mapped I/O

location. A single byte pointer is used across the master DMA controller to

determine which byte will be accessed. Any access to one of these 16-bit

registers toggles the byte pointer between the low and high bytes. A write

of any data to I/O address D8h clears this pointer so that the next access

will be to the low byte.

PC/AT-Compatible Direct-Mapped Registers

2-96

Master DMA Controlle r Reset Register I/O Address 00DAh

Programming Notes

76543210

Bit MASTR_RST

Default 00000000

R/W W

Bit Name Function

7–0 MASTR_RST Master DMA Controller Reset

Writing data of any value to this address resets the DMA Controller to the

same state as a hardware reset.

PC/AT-Compatible Direct-Mapped Registers 2-97

Master DMA Controlle r Temporary Regi ster I/O Address 00D Ah

Programming Notes

76543210

Bit MASTR_TMP

Default 00000000

R/W R

Bit Name Function

7–0 MASTR_TMP Master DMA Controller Temporary Register

Used as a temporary storage buffer when doing memory-to-memory DMA.

Note that the memory-to-memory DMA transfer is not supported. This

PC/AT-Compatible Direct-Mapped Registers

2-98

Master DMA Reset Mask Register I/O Addr ess 00DCh

Programming Notes

The same DMA channel masks can be controlled via DMA registers D4h, DCh, and DEh.

76543210

Bit MSTR_MSK_RST

Default 00000000

R/W W

Bit Name Function

7–0 MSTR_MSK_RST Master DMA Reset Mask

Writing any data to this address resets the Mask Register, thereby

activating the four Master DMA channels.

PC/AT-Compatible Direct-Mapped Registers 2-99

Master DMA General Mask Register I/O Address 00 DEh

Programming Notes

The same DMA channel masks can be controlled via DMA registers D4h, DCh, and DEh.

76543210

Bit Reserved DIS7 DIS6 DIS5 DIS4

Default 00001111

R/W WWWW

Bit Name Function

7–4 Reserved Reserved

Software should write these bits to 0.

3DIS7 Disable DMA Channel 7 Mask

0 = Enable DMA Channel 7 for servicing DMA requests

1 = Disable DMA Channel 7 from servicing DMA requests

2DIS6 Disable DMA Channel 6 Mask

0 = Enable DMA Channel 6 for servicing DMA requests

1 = Disable DMA Channel 6 from servicing DMA requests

1DIS5 Disable DMA Channel 5 Mask

0 = Enable DMA Channel 5 for servicing DMA requests

1 = Disable DMA Channel 5 from servicing DMA requests

0DIS4 Disable DMA Channel 4 Mask

0 =Enabl e DM A C h ann el 4 f or s erv ic ing D MA req ue sts , a ls o e nab les DM A

cascading to the slave DMA controller on this channel

1 =Disable DMA Channel 4 from servicing DMA requests, also enables

DMA cascading to the slave DMA controller on this channel

PC/AT-Compatible Direct-Mapped Registers

2-100

Alternate Gate A20 Control Port I/O Address 00EEh

Programming Notes

Bits 7–0: For software compatibility and other reasons, there are several sources of GateA20 control.

These controls are effectively ORed together with the output of the OR gate driving the Enhanced

Am486 microprocessor A20M pin. Therefore, A20 will propagate if ANY of the independent sources

are forcing A20 to propagate.

76543210

Bit ALT_GA20

Default 11111111

R/W R/W

Bit Name Function

7–0 ALT_GA20 Alternate GateA20 Control

This register can be used to cause the same type of masking of the CPU

A20 signal that was historically performed by an external SCP (System

Control Processor) in a PC/AT Compatible system, but much faster. This

control defaults to

not

forcing the propagation of A20:

Dummy Read = Returns FFh, and forces the A20 signal to propagate.

Dummy Write = Deasserts the forcing of the propagation of the A20 signal

via this pa rticular c ontrol, data value written is N/A.

PC/AT-Compatible Direct-Mapped Registers 2-101

Alternate CPU Reset Control Port I/O Address 00EFh

Programming Notes

76543210

Bit ALT_CPU_RST

Default 00000000

R/W R

Bit Name Function

7–0 ALT_CPU_RST Alternate CPU Reset

Reading this register performs a soft reset on the CPU. This is the same

type of CPU core reset that was typically generated via the external SCP

on a PC/AT-compatible system. The 486 cache state, SMBASE, and

ÉlanSC400 microcontroller indexed or direct mapped registers are not

directly affected by this soft reset. Instruction execution will begin at

FFFF0h as a result of this reset.

PC/AT-Compatible Direct-Mapped Registers

2-102

Parallel Port 2 Data Regi ster I/O Address 0278h

Programming Notes

There is only one parallel port on the ÉlanSC400 microcontroller, but it can be configured to have

a base address of either 378h or 278h (LPT1/LPT2).

76543210

Bit PAR2DATA[7–0]

Default 00000000

R/W R/W

Bit Name Function

7–0 PAR2DATA[7–0] Parallel Port 2 Data

Data read from or written to the parallel port data port. Write data to this

port wh en t he DIR bit of the Paral lel C ont rol Register is cl eared. R ead dat a

from this port when the DIR bit is set. When in PC/AT Compatible mode,

the data read back is the last byte written. When in Bidirectional mode, the

data read back is that which is being driven by the remote device.

PC/AT-Compatible Direct-Mapped Registers 2-103

Parallel Port 2 Status Register (PC/AT Compatible Mode) I/O Address 0279h

Programming Notes

The default value for this register depends on the mode. For PC/AT Compatible mode, the default

value for this register is ?????xxxb. For EPP mode, the default value is ?????xx0b.

76543210

Bit BUSY ACK PE SLCT ERROR Reserved

Default ––––––––

R/W RRRRR

Bit Name Function

7BUSY Printer Busy

This bit is the inverse of the (BUSY/WAIT) pin (active Low):

0 = Printer busy

1 = Printer is ready

6ACK Printer Acknowledge

The printer pulse s this line Low w hen i t has receiv ed a byte o f data . This bit

follows the state of the ACK pin (active Low):

0 = Printer acknowledge

1 = No print er ack nowledge

5PE Paper End

This bit follows the state of the PE pin:

0 = Printer has paper

1 = Paper end (out of paper)

4SLCT Printer Selected

This bit follows the state of the SLCT pin:

0 = Printer not s elected

1 = Printer selected

3 ERROR Printer Error

This bit follows the state of ERROR pin (active Low):

0 = Printer error

1 = No printer error

2–0 Reserved Reserved

PC/AT-Compatible Direct-Mapped Registers

2-104

Parall el Port 2 Status Registe r (Bi direc tional Mode) I/O Address 0279h

Programming Notes

The default value for this register depends on the mode. For PC/AT Compatible mode, the default

value for this register is ?????xxxb. For EPP mode, the default value is ?????xx0b.

76543210

Bit BUSY ACK PE SLCT ERROR Reserved

Default ––––––––

R/W RRRRR

Bit Name Function

7BUSY Printer Busy

This bit is the inverse of the (BUSY/WAIT) pin (active Low):

0 = Printer busy

1 = Printer ready

6ACK Printer Acknowledge

The printer pulse s this line Low w hen i t has receiv ed a byte o f data . This bit

follows the state of the ACK pin (active Low):

0 = Printer acknowledge

1 = No print er ack nowledge

5PE Paper End

This bit follows the state of the PE pin:

0 = Printer has paper

1 = Paper end (out of paper)

4SLCT Printer Selected

This bit follows the state of the SLCT pin:

0 = Printer not s elected

1 = Printer selected

3 ERROR Printer Error

This bit follows the state of ERROR pin (active Low):

0 = Printer error

1 = No printer error

2–0 Reserved Reserved

PC/AT-Compatible Direct-Mapped Registers 2-105

Parallel Port 2 Status Register (EPP Mode) I/O Address 0279h

Programming Notes

76543210

Bit BUSY ACK PE SLCT ERROR Reserved EPP_TIMEO

Default 00000000

R/W RRRRR R

Bit Name Function

7BUSY Printer Busy

This bit is the inverse of the (BUSY/WAIT) pin (active Low):

0 = Printer busy

1 = Printer ready

6ACK Printer Acknowledge

The printer pulse s this line Low w hen i t has receiv ed a byte o f data . This bit

follows the state of the ACK pin (active Low):

0 = Printer acknowledge

1 = No print er ack nowledge

5PE Paper End

This bit follows the state of the PE pin:

0 = Printer has paper

1 = Paper end (out of paper)

4SLCT Printer Selected

This bit follows the state of the SLCT pin:

0 = Printer not s elected

1 = Printer selected

3 ERROR Printer Error

This bit follows the state of ERROR pin (active Low):

0 = Printer error

1 = No printer error

2–1 Reserved Reserved

0 EPP_TIMEO EPP Time-out Status

0 = No time-out

1 = EPP cycle time-out occurred

This bit is set if a time-out occurred only when EPP mode is enabled (bits

1–0 of the Paralle l Port C onfigu ration Re gister i n the CSC index ed add ress

space) = ‘01b’. This bit is reset when either the status register is read, or

when EPP mode is enabled. An EPP time-out occurs when the BUSY pin

remains in ac tiv e (l ow) for greate r th an 10s af ter e ith er SL CT IN or AFD T go

active Low in EPP mode.

PC/AT-Compatible Direct-Mapped Registers

2-106

Parallel Port 2 Control Register I/O Address 027Ah

Programming Notes

76543210

Bit Reserved DIR IRQEN SLCTIN INIT AUTOFDXT STROBE

Default 00000000

R/W R/W R/W R/W R/W R/W R/W

Bit Name Function

7–6 Reserved Reserved

Software should write these bits to 0.

5DIR Bidirectional Parallel Port Data Direction

When the parallel port is set to ope rate in eithe r Bidi rec tion al mod e or EPP

mode, this bit controls the data direction between host and peripheral. For

a parallel port data write operation where either Bidirectional mode or EPP

mode is selected:

0 = Data written to PD7–PD0

1 = Data written is latched only

For a parallel port data read operation where either Bidirectional mode or

EPP mode is selected:

0 = Internal data register read

1 = Data read from PD7–PD0

This bit is undefined when neither Bidirectional mode nor EPP mode is

selected.

4IRQEN Printer IRQ Enable

Clearing this bit clears any pending interrupts:

0 = Disable printer IRQ

1 = Enable printer IRQ

3 SLCTIN Select Printer Signal Control

This bit is the inverse of the SLCTIN pin.

0 = The SLCTIN pin is a logic 1

1 = The SLCTIN pin a l ogic 0

2INIT Printer Reset Signal Control

0 = Hold printer in res et

1 = Release printer from reset, this bit follows the INIT pin (activ e Low )

1 AUTOFDXT Auto Line Feed Signal Control

This bit is the inverse of the AFDT pin:

0 =AFDT pin is a logic 1

1 =AFDT pin is a logic 0

When connected to a printer, setting this bit causes the printer to

automatically insert a line feed when it sees a carriage return (ASCII

13) character.

0STROBE Printer Port Strobe Signal Control

This bit is the inverse of the STRB pin :

0 = STRB pin not active

1 = STRB pin active

PC/AT-Compatible Direct-Mapped Registers 2-107

Parallel Port 2 EPP Address Regi ster I/O Address 027Bh

Programming Notes

76543210

Bit EPP2ADDR[7–0]

Default 00000000

R/W R/W

Bit Name Function

7–0 EPP2ADDR[7–0] Parallel Port 2 EPP Address

When this port is written to, the value written appears on the parallel port

data lines. In addition, an automatic address strobe is generated to allow

the peripheral EPP device to latch the address.

PC/AT-Compatible Direct-Mapped Registers

2-108

Parallel Port 2 EPP 32-bit Data Register I/O Address 027C–0 27Fh

Programming Notes

Bits 31–0: A 16-bit I/O writ e to 27Ch will cause two back-to-back 8-bit bus cycles to occur to the

EPP Data Registers 27Ch and 27Dh. Two bytes of data will be presented to the parallel port data

lines in succession starting with the data written to 27Ch. An EPP data strobe will be automatically

generated for each of the bus cycles.

An 8-bit I/O write to 27Ch will cause a single 8-bit bus cycle to occur to the EPP Data Register at

27Ch. The single byte of data will be presented to the parallel port data lines along with an

automatically generated EPP data strobe.

In common practice, all write accesses to the parallel port 2 EPP Data Register (x8, x16, or x32 I/

O instructions) should be directed to port 27Ch.

76543210

Bit EPP2DATA[31–0]

Default 00000000

R/W R/W

Bit Name R/W Function

31–0 EPP2DATA[31–0] R/W Parallel Port 2 EPP 32-bit Data

A 32-bit I/O write to 27Ch will cause four back-to-back 8-bit bus

cycles to occur to the four EPP Data Registers 27Ch–27Fh. Four

bytes of data will be presented to the parallel port data lines in

succession starting with the data written to 27Ch. An EPP data

strobe will be automatically generated for each of the bus cycles.

PC/AT-Compatible Direct-Mapped Registers 2-109

COM2 Transmi t H ol di ng Register I/O Address 02F8h

Programming Notes

There is only one serial port on the ÉlanSC400 microcontroller, but it can be configured to have a

base address of either 3F8h or 2F8h (COM1/COM2).

76543210

Bit COM2THR[7–0]

Default 00000000

R/W W

Bit Name Function

7–0 COM2THR[7–0] COM2 Transmit Holding Register

When COM2 DLAB = 0, and the transmitter is not busy, write the byte to

transmit to this register.

PC/AT-Compatible Direct-Mapped Registers

2-110

COM2 Receive Buffer Register I/O Address 02F8h

Programming Notes

76543210

Bit COM2RBR[7–0]

Default 00000000

R/W R

Bit Name Function

7–0 COM2RBR[7–0] COM2 Receive Buffer

When COM2 DLAB = 0, and a received byte is available, read received

byte from this register.

PC/AT-Compatible Direct-Mapped Registers 2-111

COM2 Baud Clock Diviso r Latch LSB I/O Address 02F8h

Programming Notes

76543210

Bit COM2_DIV[7–0]

Default 00000000

R/W R/W

Bit Name Function

7–0 COM2_DIV[7–0] COM2 Baud Clock Divisor Latch

When COM2 DLAB = 1, this register holds the least significant byte of a

16-bit baud rate clock divisor that is used to generate the 16x baud clock.

PC/AT-Compatible Direct-Mapped Registers

2-112

COM2 Baud Clock Diviso r Latch MSB I/O Address 02F9h

Programming Notes

76543210

Bit COM2_DIV[15–8]

Default 00000000

R/W R/W

Bit Name Function

7–0 COM2_DIV[15–8] COM2 Baud Clock Divisor Latch

When COM2 DLAB = 1, this register holds the most significant byte of a

16-bit baud rate clock divisor that is used to generate the 16x baud clock.

PC/AT-Compatible Direct-Mapped Registers 2-113

COM2 Interrupt Enable Register I/O Address 02F9h

Programming Notes

76543210

Bit Reserved EMSI ERLSI ETHREI ERDAI

Default 00000000

R/W R/W R/W R/W R/W

Bit Name Function

7–4 Reserved Reserved

Software should write these bits to 0.

3EMSI Enable Modem Status Interrupt

0 = Disable mode m stat us interrupt

1 = Enable modem status interrupt

2ERLSI Enable Receiver Line Status Interrupt

0 = Disable receiver line status interrupt

1 = Enable receiver line status interrupt

1ETHREI Enable Transmitter Holding Register Empty Interrupt

0 = Disable transmitter holdin g register empty i nterrupt

1 = Enable transmitter holding register empty interrupt

0 ERDAI Enable Received Data Available Interrupt

0 =Disable data available interrupt in 16450-compatible mode; in

16550-compatible mode, this bit also disables time-out interrupts

1 =Enable received data available interrupt in 16450-compatible mode; in

16550-compatible mode, this bit also enables time-out interrupts

More de tail on time-out inte rrupts ca n be foun d in the Interrupt Id entifica tion

PC/AT-Compatible Direct-Mapped Registers

2-114

COM2 Inter rupt ID Register I/O Address 02FAh

76543210

Bit FIFO1

FIFO0 Reserved ID2

ID1

ID0 IP

Default 00001111

R/W RRR

Bit Name Function Priority

7–6 FIFO1

FIFO0 FIFO Feature Presence Indication

FIFO is only present when 16550-compatible mode is

enabled):

0 0 = No significance

0 1 = No significance

1 0 = 16450-co mpatible mode is ena ble d

1 1 = 16550-co mpatible mode is ena ble d

5–4 Reserved Reserved

These bits always read back ‘00b’.

3–1 ID2

ID1

ID0

Interrupt Identifica tion Bit Field

0 0 0 = Modem status Fourth (Lowest)

0 0 1 =Transmitter Holding Register Empty/Transmit

FIFO Empty (16550-compatible mode) Third

0 1 0 =Received Data Available/Receiver FIFO

trigger (16550-compatible mode) Second

0 1 1 = Receive Lin e Status First (Hi ghest)

1 0 0 = Not used

1 0 1 = Not used

1 1 0 = FIFO time-out Second

1 1 1 = Not used

In 16450-compatible mode, bit 3 always reads back

‘0b’. See the Modem Status Register (MSR) and Line

Status Register (LSR) for more detail on interrupt

events.

If two interrupt sources are pending simultaneously,

only the highest priority interrupt (as defined by the

rightmost column for bits 3–1) will be indicated by bits

3–1 of the Interrupt Identification Register (IIR). When

the inter rupt source is clear ed, a subsequ ent read from

the Interrupt Identification Register (IIR) will return the

next hig hes t pri orit y in terru pt s ourc e. Bits 3 –1 h ave no

meaning if bit 0 = ‘1b’.

A FIFO time-out occurs when the receive FIFO is not

empty, and m ore than four c ontinu ous chara cter-tim es

have tran spired without more dat a being plac ed into or

read out o f the receive FIFO. Re ading a characte r from

the receive FIFO clears the time-out interrupt.

PC/AT-Compatible Direct-Mapped Registers 2-115

Programming Notes

0IP Serial Port Interrupt Pending (Active Low)

0 = Interrupt pending

1 = No interrupt pend ing

Bit Name Function Priority

PC/AT-Compatible Direct-Mapped Registers

2-116

COM2 FIFO Control Register I/O Address 02FAh

Programming Notes

The contents of this write-only register can be read back via the Chip Setup and Control (CS C)

indexed register D3h. The on-board UART can be mapped to only one of COM1 or COM2 at any

time, and the Shadow register at CSC index D3h serves either configuration.

76543210

Bit RFRT[1–0] Reserved Reserved TFCLR RFCLR FIFOEN

Default 00000000

R/W W WWWW

Bit Name R/W Function

7–6 RFRT[1–0] W Receiver FIFO Register Trigger Bits

When in 16550-compatible mode, this bit field specifies the trigger

level at whi ch the Int errup t Identific atio n Regi st er w ill repo rt that a

received data available interrupt is pending. If received data

available interrupts are enabled in the IER, the system will be

interrupted when the receive FIFO fills to the trigger level per the

following table:

0 0 = 1 byte

0 1 = 4 bytes

1 0 = 8 bytes

1 1 = 14 bytes

When the data in the receive FIFO falls below this trigger level,

the interrupt will be cleared.

5–4 Reserved Reserved

Software should write these bits to 0.

3Reserved WReserved

Software should write this bit to 1.

2TFCLR WTransmitter FIFO Buffer Clear

Writing a ‘1b’ to this bit position clears the transmit FIFO and

resets the transmit FIFO counter logic. It does not clear the

Transmitter Shift Register. This bit is cleared by either a read of

the Interrupt ID Register, or by a write to the Transmit Holding

1RFCLR WReceiver FIFO Buffer Clear

Writi ng a ‘1b ’ to this bit pos ition c lears the receive FIFO an d resets

the recei ve FIFO counter l ogic. It does not clear the Recei ver Shift

Regis ter. This bit is self-c learing , and doe s not ne ed t o be rese t to

0 under software control.

0 FIFOEN W FIFO Enable (16550-Compatible Mode Enable )

0 =Causes UART to enter 16450-compatible mode

Disable s acc esses t o rece ive a nd tran smit FIFOs and al l FIFO

control bits, except this bit.

1 =Causes UART to enter 16550-compatible mode

Enables receive and transmit FIFOs and enables accesses to

other FIFO control bits.

The main difference between a 16450-compatible mode and

16550-compatible mode is the addition of transmit and receive

FIFOs in the 16550-compatible mode

This bit must be ‘1b’ when other FIFO control register bits are

written to or they will not be programmed. Any mode switch will

clear both FIFOs. The FIFOs must be enabled for the IrDA

interface to operate in High-Speed IrDA mode.

PC/AT-Compatible Direct-Mapped Registers 2-117

COM2 Line Control Regi ster I/O Address 02FBh

76543210

Bit DLAB SB SP EPS PE STP WLB0

WLB1

Default 00000000

R/W R/W R/W R/W R/W R/W R/W R/W

Bit Name Function

7DLAB Divisor Latch Access Bit

Set this bit to gain access to the baud rate divisor latches for this COM port.

Clear this bit to mux in the Transmit Holding Register and Receive Buffer

6SB Set Break Enable

Setting this bit causes a break condition to be transmitted to the receiving

UART.

0 =Disable set br eak

1 =Force serial output to spa c ing st ate (logic ‘0’) regardless of other

transmitter activity

The break control acts on the SOUT pin only and has no other effect on the

transmitter logic.

5SP Stick Parity Enable

Forces the parity bit to always be 0 or 1 versus dynamically changing it so

that there are an odd or even number of 1 bits in the transmitted data. If this

bit is 0, then normal parity is used if parity is enabled. If bits 5,4, and 3 = 1,

the parity bit is ge nerated/ch ec ke d a s a logical 1. If bits 5 an d 3 = 1 and b it 4

= 0, the parity bit is generated/checked as a logical 0.

4 EPS Even Parity Select

Parity must be enabled via bit 3 for this bit to have meaning:

0 =Odd parity

The parity bit will be manipulated to force an odd number of 1 bits in the

transmitted data and the same condition will be checked for in the

received data.

1 =Even parit y

The pa rity bit will be ma nipul ated to fo rce an ev en num ber of 1 bit s in the

transmitted data and the same condition will be checked for in the

received data.

Start/stop bits are not included in the parity generation/checking scheme.

3PE Asynchronous Data Parity Enable

Causes a parity bit to be generated in the transmitted data and to be

checked in the received data. The parity bit is located between the last data

word bit and the first stop bit in the bit stream.

2STP Stop Bits

Based on character length from bits 1–0 above.

If character length = 5:

0 = 1 s top bit

1 = 1.5 stop bits

If character length = 6, 7, or 8:

0 = 1 s top bit

1 = 2 s top bits

1–0 WLB0

WLB1 Transmit/Receive Character Length

0 0 = 5 bits

0 1 = 6 bits

1 0 = 7 bits

1 1 = 8 bits

PC/AT-Compatible Direct-Mapped Registers

2-118

COM2 Modem Control Regi ster I/O Address 02FCh

Programming Notes

76543210

Bit Reserved LOOP OUT2 OUT1 RTS DTR

Default 00000000

R/W R/W R/W R/W R/W R/W

Bit Name Function

7–5 Reserved Reserved

Software should write these bits to 0.

4LOOP Loopback (Diagnostic Mode) Enable

1 =Enabled

The following internal connections are made by setting this diagnostic

bit:

RTS is in ternally connected to CTS

DTR is internally connected to DSR

OUT1 is internally connected to RI

OUT2 is internally connected to DCD

0 =Loopback mo de is dis ab led

In addition, the SOUT bit is driven High, and the SIN input line is blocked.

The Transmit Shift Out Register is directly connected to the receive shift in

inactive. Modem control interrupts can be forced by enabling the

appropriate bit in the IER, and asserting one of the bits 3–0 in loopback

mode.

3OUT2 Enable COM2 Interrupts

This bit controls the OUT2 signal which is used as a master enable for

COM2 in terru pts . If th is b it i s not set, no COM po rt 2 IRQ s wi ll b e fel t at t he

Programmable Interrupt Controller (PIC).

2OUT1 OUT1 Control

This bit controls the OUT1 sign al which is not tied to anythin g. It is provided

for PC/AT compatibility and can be used as part of the loopback

diagnostics. Other than that, it has no effect on system operation and can

be used as a scratch pad during normal system operation.

1RTS Request to Send

0 = Deassert the Request To Send signal (RTS)

1 = Assert the Request To Send signal (RTS)

0DTR Data Terminal Ready

0 = Deassert the Data Terminal Ready signal (DTR)

1 = Assert the Data Terminal Ready signal (DTR)

PC/AT-Compatible Direct-Mapped Registers 2-119

COM2 Line Status Register I/O Address 02FDh

76543210

Bit 16550_ERR TEMT THRE BI FE PE OE DR

Default 01100000

R/W RRRRRR R

Bit Name Function

7 16550_ERR 16550-Mode Error

In 16450-compatible mode, this bit reads back ‘0b’.

In 16550-compatible mode, when this bit is set it indicates at least one

parity erro r, framing erro r, or break condit ion is present i n the receiv e FIFO.

This bit is cleared by a read from the Line Status Register if there are no

subsequent errors in the FIFO.

6 TEMT Transmitter Empty Indicator

In 16450-compatible mode, this bit is set when both the Transmit Holding

In 16550-compatible mode, this bit is set when both the Transmit Shift

5THRE Transmitter Holding Register (16450-Compatible Mode) or Transmit

FIFO Empty (16550-Compatible Mode)

In 16450-compatible mode, this bit indicates that the Transmit Holding

by a write to the T ransmit Holdin g Register w hen in 16450 -compatible

mode.

In 16550-compatible mode, this bit indicates that the transmit FIFO is

completely empty. When in 16550-compatible mode, this interrupt will be

cleared when either the transmit FIFO is written to, or when the Interrupt

Identification R e gis ter is read. This b it ca n be us ed to generate an i nterrupt

if programmed to do so via the Interrupt Enab le Register.

4BI Break Indicator

In 16450-compatible mode, this bit is set when the UART detects that the

sendin g UAR T is tran smitting a break c onditi on for a pe riod longer th an the

time it takes to receive start, data, parity, and stop bits.

In 16550-compatible mode, this bit is set when an entire word (start, data,

parity, stop) that has been received with break indication present into the

receive FIFO is at the top of the FIFO. Only one break indication will be

loaded into the FIFO regardless of the duration of the break condition. A

new chara cter wil l not be loaded into th e FIFO until th e next va lid st art bit i s

detected. Th is l atc hed sta tus bit is auto ma tic all y clea red b y a read f r om t he

Line Status Register.

3FE Framing Error

In 16450-compatible mode, this bit is set to indicate that a received

char act er did not hav e a vali d stop bit.

In 16550-compatible mode, this bit is set when a character that has been

receiv ed with a framing erro r into the receive FIF O is at the top of the FIF O.

This latched status bit is automatically cleared by a read from the Line

Stat us Register.

2PE Parity Error

In 16450 -comp atible mode , this bit is set up on rec eipt of dat a with i ncorrec t

parity.

In 16550-compatible mode, this bit is set when a character that has been

receiv ed with bad parity into the receive FIFO is at the top of the FIFO. Th is

latched status bit is automatically c leared by a read from the Line Status

PC/AT-Compatible Direct-Mapped Registers

2-120

Programming Notes

When a receiver line status interrupt is enabled and detected, bits 1 through 4 above will indicate

the re as on f o r t h e in te r ru pt . T h e st a t us b it s ar e va li d ev en w hen t h e re ce iv er li ne s t at u s i n te rr up t i s

not enabled.

1OE Overrun Error

In 16450-comp ati ble mo de, this b it i s s et if a new charac ter is rec eiv ed int o

the receiver buffer before a previous character was read, thus resulting in

lost data.

In 16550-compatible mode, this bit is set if a new character is completely

receiv ed into the Shift Registe r when the FIFO i s alrea dy 100% fu ll. Da ta in

the FIFO is not overwritten by this overrun. The data in the Shift Register

will be lost when the next character is r eceived. This latched status bit is

automatically cleared by a read from the Line Status Register.

0DR Data Ready

In 16450-compatible mode, when this bit is set, a character has been

received and placed in the R eceiver Buffer Register. This bi t is

automatically cleared by reading the Receiver Buffer Register.

In 16550-compatible mode, when this bit is set, a character has been

received and placed in the receive FIFO. This bit is aut omatically clea red

by reading the Receiver FIFO.

Bit Name Function

PC/AT-Compatible Direct-Mapped Registers 2-121

COM2 Modem Status Register I/O Address 02FEh

Programming Notes

Bits 7–4: Real-time status indicators for the indicated inputs to the UART.

Bits 3–0: Latched status bits that will generate an interrupt if modem status interrupts are unmasked

in the Interrupt Enable Register (IER). Reading the Modem Status Register (MSR) clears these bits

and their associated interrupt.

76543210

Bit DCD RI DSR CTS DDCD TERI DDSR DCTS

Default xxxx0000

R/W RRRRRRRR

Bit Name Function

7 DCD Data Carrier Detect

0 =DCD input signal is deasserted

1 =DCD input signal is asserted

If in loopback mode, this bit tracks bit 3 of the Modem Control Register.

6RI Ring Indicator

0 =RI input signal is deasserted

1 =RI input signal is asserted

If in loopback mode, this bit tracks bit 2 of the Modem Control Register.

5DSR Data Set Ready

0 =DSR input signal is deasserted

1 =DSR input signal is asserted

If in loopback mode, this bit tracks bit 0 of the Modem Control Register.

4CTS Clear To Send

0 =CTS input signal is deasserted

1 =CTS input signal is asserted

If in loopback mode, this bit tracks bit 1 of the Modem Control Register.

3 DDCD Delta Data Carrier Detect

0 =Indicates that the DCD signal has not changed since the Modem Status

Regis ter was las t read

1 =Ind icate s that the DCD signal changed since the Modem Status

2 TERI Trailing Edge Ring Indicator

0 =Ind icate s that the RI signal has not changed from an active to an

inactive state since the Modem Status Register was last read

1 =Ind icate s that the RI signal changed from an active to an inactive state

sinc e the Modem Status Register (MSR) was last read

1 DDSR Delta Data Set Ready

0 =Ind icate s that the DSR signal h as not chan ged s ince t he Mo dem Sta tus

Regis ter was las t read

1 =Ind icate s that the DSR signal changed since the Modem Status

0 DCTS Delta Clear To Send

0 =Ind icate s that the CTS signal has not cha nged si nce the M odem Stat us

Regis ter was las t read

1 =Ind icate s that the CT S signal changed since the Modem Status

PC/AT-Compatible Direct-Mapped Registers

2-122

COM2 Scrat ch Pad Register I/O Addr ess 02FFh

Programming Notes

76543210

Bit SCRATCH2[7–0]

Default 00000000

R/W R/W

Bit Name Function

7–0 SCRATCH2[7–0] Scratch Bit

General-purpose I/O location, not required for serial data transfer.

PC/AT-Compatible Direct-Mapped Registers 2-123

Parall el Port 1 Data Register I/O Address 0378h

Programming Notes

There is only one parallel port on the ÉlanSC400 microcontroller, but it can be configured to have

a base address of either 378h or 278h (LPT1/LPT2).

76543210

Bit PAR1_DATA[7–0]

Default 00000000

R/W R/W

Bit Name Function

7–0 PAR1_DATA[7–0] Parallel Port 1 Data

Data read from or writte n to the parallel por t data re gister . Write d ata to this

data from this register when the DIR bit is set. When in PC/AT Compatible

mode, the data read back is the last byte written. When in Bidirectional

mode, the data read back is that which is being driven by the remote

device.

PC/AT-Compatible Direct-Mapped Registers

2-124

Parallel Port 1 Status Register (PC/AT Compatible Mode) I/O Address 0379h

Programming Notes

76543210

Bit BUSY ACK PE SLCT ERROR Reserved

Default 00000000

R/W RRRRR

Bit Name Function

7BUSY Printer Busy

This bit is the inverse of the (BUSY/WAIT) pin (active Low):

0 = Printer busy

1 = Printer ready

6ACK Printer Acknowledge

The printer pulse s this line Low w hen i t has receiv ed a byte o f data . This bit

follows the state of the ACK pin (active Low):

0 = Printer acknowledge

1 = No print er ack nowledge

5PE Paper End

This bit follows the state of the PE pin:

0 = Printer has paper

1 = Paper end (out of paper)

4SLCT Printer Selected

This bit follows the state of the SLCT pin:

0 = Printer not s elected

1 = Printer selected

3 ERROR Printer Error

This bit follows the state of ERROR pin (active Low):

0 = Printer error

1 = No printer error

2–0 Reserved Reserved

PC/AT-Compatible Direct-Mapped Registers 2-125

Parall el Port 1 Status Registe r (Bi direc tional Mode) I/O Address 0379h

Programming Notes

The default value for this register depends on the mode. For PC/AT Compatible mode, the default

value for this register is ?????xxxb. For EPP mode, the default value is ?????xx0b.

76543210

Bit BUSY ACK PE SLCT ERROR Reserved

Default ––––––––

R/W RRRRR

Bit Name Function

7BUSY Printer Busy

This bit is the inverse of the (BUSY/WAIT) pin (active Low):

0 = Printer busy

1 = Printer ready

6ACK Printer Acknowledge

The printer pulse s this line Low w hen i t has receiv ed a byte o f data . This bit

follows the state of the ACK pin (active Low):

0 = Printer acknowledge

1 = No print er ack nowledge

5PE Paper End

This bit follows the state of the PE pin:

0 = Printer has paper

1 = Paper end (out of paper)

4SLCT Printer Selected

This bit follows the state of the SLCT pin:

0 = Printer not s elected

1 = Printer selected

3 ERROR Printer Error

This bit follows the state of ERROR pin (active Low):

0 = Printer error

1 = No printer error

2–0 Reserved Reserved

PC/AT-Compatible Direct-Mapped Registers

2-126

Parallel Port 1 Status Register (EPP Mode) I/O Address 0379h

Programming Notes

The default value for this register depends on the mode. For PC/AT Compatible mode, the default

value for this register is ?????xxxb. For EPP mode, the default value is ?????xx0b.

76543210

Bit BUSY ACK PE SLCT ERROR Reserved EPP_TIMEO

Default ––––––––

R/W RRRRR R

Bit Name Function

7BUSY Printer Busy

This bit is the inverse of the (BUSY/WAIT) pin (active Low):

0 = Printer busy

1 = Printer ready

6ACK Printer Acknowledge

The printer pulse s this line Low w hen i t has receiv ed a byte o f data . This bit

follows the state of the ACK pin (active Low):

0 = Printer acknowledge

1 = No print er ack nowledge

5PE Paper End

This bit follows the state of the PE pin:

0 = Printer has paper

1 = Paper end (out of paper)

4SLCT Printer Selected

This bit follows the state of the SLCT pin:

0 = Printer not s elected

1 = Printer selected

3 ERROR Printer Error

This bit follows the state of ERROR pin (active Low):

0 = Printer error

1 = No printer error

2–1 Reserved Reserved

0 EPP_TIMEO EPP Time-out Status

0 = No time-out

1 = EPP cycle time-out occurred

This bit is set if a time-out occurred only when EPP mode is enabled (bits

1–0 of the Parallel Port Configuration Register in the ÉlanSC400

microcontroller-specific indexed address space) = ‘01b’. This bit is reset

when either the status register is read, or when EPP mode is enabled. An

EPP time-out occurs when the BUSY pin remai ns inactive (Low) for gre ater

than 10µs after either SLCTIN or AFDT go active (Low) in EPP mode.

PC/AT-Compatible Direct-Mapped Registers 2-127

Parallel Port 1 Control Register I/O Address 037Ah

Programming Notes

76543210

Bit Reserved DIR IRQEN SLCTIN INIT AUTOFDXT STROBE

Default 00000000

R/W R/W R/W R/W R/W R/W R/W

Bit Name Function

7–6 Reserved Reserved

Software should write these bits to 0.

5DIR Bidirectional Parallel Port Data Direction

When the parallel port is set to ope rate in eithe r Bidi rec tion al mod e or EPP

mode, this bit controls the data direction between host and peripheral. For

a parallel port data write operation where either Bidirectional mode or EPP

mode is selected:

0 = Data written to PD7–PD0

1 = Data written is latched only

For a parallel port data read operation where either Bidirectional mode or

EPP mode is selected:

0 =Internal data register read

1 = Data read from PD7–PD0]

This bit is undefined when neither Bidirectional mode nor EPP mode is

selected.

4IRQEN Printer IRQ Enable

Clearing this bit clears any pending interrupts.

0 = Disable printer IRQ

1 = Enable printer IRQ

3 SLCTIN Select Printer Signal Control

This bit is the inverse of the SLCTIN pin.

0 = The SLCTIN pin is a logic 1

1 = The SLCTIN pin a l ogic 0

2INIT Printer Reset Signal Control

0 = Hold printer in res et

1 = Release printer from reset, this bit follows the INIT pin (activ e Low )

1 AUTOFDXT Auto Line Feed Signal Control

This bit is the inverse of the AFDT pin:

0 =AFDT pin is a logic 1

1 =AFDT pin is a logic 0

When connected to a printer, setting this bit causes the printer to

automatically insert a line feed when it sees a carriage return (ASCII

13) characters.

0STROBE Printer Port Strobe Signal Control

This bit is the inverse of the STRB pin :

0 = STRB pin not active

1 = STRB pin active

PC/AT-Compatible Direct-Mapped Registers

2-128

Parallel Port 1 EPP Address Regi ster I/O Address 037Bh

Programming Notes

76543210

Bit EPP1_ADDR[7–0]

Default 00000000

R/W R/W

Bit Name Function

7–0 EPP1_ADDR[7–0] Parallel Port 1 EPP Address

When this port is written to, the value written appears on the parallel port

data lines. In addition, an automatic address strobe is generated to allow

the peripheral EPP device to latch the address.

PC/AT-Compatible Direct-Mapped Registers 2-129

Parallel Port 1 EPP 32-bit Data Register I/O Address 037C–0 37Fh

Programming Notes

Bits 31–0: A 16-bit I/O writ e to 37Ch will cause two back-to-back 8-bit bus cycles to occur to the

EPP Data Registers 37Ch and 37Dh. Two bytes of data will be presented to the parallel port data

lines in succession starting with the data written to 37Ch. An EPP data strobe will be automatically

generated for each of the bus cycles.

An 8-bit I/O write to 37Ch will cause a single 8-bit bus cycle to occur to the EPP Data Register at

37Ch. The single byte of data will be presented to the parallel port data lines along with an

automatically generated EPP data strobe.

In common practice, all write accesses to the parallel port 1 EPP Data Register (x8, x16, or x32 I/

O instructions) should be directed to port 37Ch.

76543210

Bit EPP1_DATA[31–0]

Default 00000000

R/W R/W

Bit Name Function

31–0 EPP1_DATA[31–0] Parallel Port 1 EPP 32-bit Data

A 32-bit I/O write to 37Ch will cause four back-to-back 8-bit bus cycles to

occur to the four EPP Data Registers 37Ch–37Fh. Four bytes of data will

be presented to the parallel port data lines in succession starting with the

data written to 37Ch. An EPP data strobe will be automatically generated

for each of the bus cycles.

PC/AT-Compatible Direct-Mapped Registers

2-130

MDA/HGA Index Register I/O Address 03B4h

Programming Notes

This register is visible only when the Comp_Mod bit in the Internal Graphics Control Register A (CSC

index DDh[0]) is set (MDA compatibility).

76543210

Bit MDA_INDX[7–0]

Default 00000000

R/W R/W

Bit Name Function

7–0 MDA_INDX[7–0] MDA Index

Graphic s Contr oller Index Register w hen opera ting in Mo nochrome Display

Adapter/Hercules Display Adapter (MDA/HGA) modes.

PC/AT-Compatible Direct-Mapped Registers 2-131

MDA/HGA Data Register I/O Address 03B5h

Programming Notes

This register is visible only when the Comp_Mod bit in the Internal Graphics Control Register A (CSC

index DDh[0]) is set (MDA compatibility). In addition, if the HGA extensions to MDA are required,

CRTC index 52h[4] must be set. The B0000h and B8000h pages specified in the description for bit

7 assume that the internal graphics controller has had its display buffer base address set to reside

at B0000h. Generally speaking, setting bit 7 of this register when in HGA mode will functionally add

32 K to the shared memory base address (must be configured via graphics index registers 4Dh/4Eh).

76543210

Bit MDA_DATA[7–0]

Default xxxxxxxx

R/W R/W

Bit Name Function

7–0 MDA_DATA[7–0] MDA Data

Graphics Controller Data Register when operating in Monochrome Display

Adapter/Hercules Display Adapter (MDA/HGA) modes.

PC/AT-Compatible Direct-Mapped Registers

2-132

MDA/HGA Mode Control Register I/O Address 03B8h

Programming Notes

This register is visible only when the Comp_Mod bit in the Internal Graphics Control Register A (chip

configuration register DDh[0]) is set (MDA compatibility). In addition, if the HGA extensions to MDA

are required, CRTC index 52h[4] must be set. Also note that the B0000h and B8000h pages specified

in the description for bit 7 assume that the internal graphics controller has had its display buffer base

address set up to reside at B0000h. Generally speaking, setting bit 7 of this register when in HGA

mode will functionally add 32 Kbytes to the shared memory base address (must be configured via

graphics index registers 4Dh/4Eh).

76543210

Bit HGA_PG_SEL Reserved TXTBLNK Reserved VIDCON Reserved HGA_GR_EN TXTCON

Default 00000000

R/W R/W R/W R/W R/W R/W

Bit Name Function

7 HGA_PG_SEL HGA Page Select (HGA Mode Only)

0 = Use B0000h as the start of the display buffer

1 = Use B8000h as the start of the display buffer

6Reserved Reserved

Software should write this bit to 0.

5 TXTBLNK Text Blink Control

0 = Blinking attribute disabled

1 = Blinking attribute enabled (attribute byte bit 7 will control blinking)

4Reserved Reserved

Software should write this bit to 0.

3VIDCON Video Blanking Control

0 = Video is blanked

1 = Video is not blanked

2Reserved Reserved

Software should write this bit to 0.

1HGA_GR_EN HGA Graphics Enable (HGA Mode Only)

0 TXTCON MDA/HG A Column Select

This bit is provided for compatibility purposes only. It does not actually set

the column width. This must be d one via the CRTC index registers. The

MDA/HGA legacy values for this bit are:

0 = 40x25 text mode

1 = 80x25 text mode

PC/AT-Compatible Direct-Mapped Registers 2-133

MDA/HG A Status Register I/O Addr ess 03BAh

Programming Notes

This register is visible only when the Comp_Mod bit in the Internal Graphics Control Register A (CSC

index DDh[0]) is set (MDA compatibility).

76543210

Bit Reserved VERTRET Reserved DMSTAT

Default 1111x00x

R/W R RRR

Bit Name Function

7–4 Reserved Reserved

Reads back ‘1111b’.

3 VERTRET Vertical Retrace Status (simulated vertical sync)

0 = Raster is not in vertical retrace

1 = Raster is in vertical retrace

2–1 Reserved Reserved

0DMSTAT Display-Memory Access Status (Simulated Horizontal Sync)

This bit is prov ided for softwar e compatibil ity purpos es. Th e lega cy

meanings for this bit are as shown bel ow. In actua lity, screen sparkle will

never occur.

0 = CPU access to video buffer RAM will cause screen sparkle

1 = CPU can access video buffer RAM without causing screen sparkle

PC/AT-Compatible Direct-Mapped Registers

2-134

HGA Con f iguration Register I/O Ad dress 03BFh

Programming Notes

This register is visible only when the Comp_Mod bit in the Internal Graphics Control Register A (CSC

index DDh[0]) is set (MDA compatibility) and the Extended Feature Control Register (graphics index

52h) bit 4 is set, thus enabling HGA mode. Also, bits 1–0 can be read back via the internal graphics

controller’s Extended Feature Control Register at graphics index 52h in 3x4h/3x5h (internal graphics

controller indexed register space).

76543210

Bit Reserved PG_MEM1_EN HGA_GR_EN

Default xxxxxx00

R/W WW

Bit Name Function

7–2 Reserved Reserved

Software should write these bits to 0.

1 PG_MEM1_EN Enable Memory Page 1

0 =Prevent setting of the Page Select bit (bit 7 of the MDA/HGA Mode

Control Register)

1 =Allow setting of the Page Select bit

The read-back for the write-only PG_MEM1_EN bit is in graphics index

52h[6].

0HGA_GR_EN Enable HGA Graphics Mode

0 = Lock the chip in Hercules text mode

1 = Permit entry to Hercules Graphics mode

The read-back for the write-only HGA_GR_EN bit is in graphics index

52h[5].

PC/AT-Compatible Direct-Mapped Registers 2-135

CGA Index Register I/O Address 03D4h

Programming Notes

This register is visible only when the Comp_Mod bit in the Internal Graphics Control Register A (CSC

index DDh[0]) is cleared (CGA mode).

76543210

Bit CGA_INDX[7–0]

Default 00000000

R/W R/W

Bit Name Function

7–0 CGA_INDX[7–0] CGA Index

Graphics Controller Index Register when operating in Color Graphics

Adapter mode.

PC/AT-Compatible Direct-Mapped Registers

2-136

CGA Data Port I/O Address 03D5h

Programming Notes

This register is visible only when the Comp_Mod bit in the Internal Graphics Control Register A (CSC

index DDh[0]) is cleared (CGA mode).

76543210

Bit CGA_DATA[7–0]

Default xxxxxxxx

R/W R/W

Bit Name Function

7–0 CGA_DATA[7–0] CGA Data Port

Graphics Controller Data Register when operating in Color Graphics

Adapter mode.

PC/AT-Compatible Direct-Mapped Registers 2-137

CGA Mode Control Register I/O Address 03D8h

Programming Notes

Bits 3–0 of this register select the border color for text mode, the background color (C0 = C1 = 0)

for 320x200 graphics modes, and the foreground color (C0 = 1) for 640x200 graphics modes. This

index DDh[0]) is cleared (CGA mode).

76543210

Bit Reserved TXTBLNK GRPCON VIDCON COLBUR TGCON TXTCON

Default 00000000

R/W R/W R/W R/W R/W R/W R/W

Bit Name Function

7–6 Reserved Reserved

Software should write these bits to 0.

5 TXTBLNK Text Attribute Control

0 = Blinking attribute disabled

1 = Blinking attribute enabled (attribute byte bit 7 will control blinking)

4 GRPCON CGA Graphics Control

0 = All other modes

1 = 1bpp high-resolution APA graphics mode

3VIDCON Video Blanking Control

0 = Video is blanked

1 = Video is not blanked

2 COLBUR Color Burst Select (Affects Only Text Modes)

0 =Use color text attributes

1 =Normal graphics panels will use black and white text attributes. Color

STN panels will use monochrome gray scales

1TGCON Text/Graphics Control

0 = Text mode

1 = Graphics mode

0 TXTCON CGA Column Select

This bit is provided for compatibility purposes only. It does not actually set

the column width. This must be d one via the CRTC index registers. The

CGA legacy values for this bit are:

0 = 40x25 text mode

1 = 80x25 text mode

PC/AT-Compatible Direct-Mapped Registers

2-138

CGA Color Select Registe r I/O Address 03D9h

Programming Notes

This register is visible only when the Comp_Mod bit in the Internal Graphics Control Register A (CSC

index DDh[0]) is cleared (CGA mode).

76543210

Bit Reserved ALTPAL ALTBAK SBINT SBRED SBGREEN SBBLUE

Default 00000000

R/W R/W R/W R/W R/W R/W R/W

Bit Name Function

7–6 Reserved Reserved

Software should write these bits to 0.

5 ALTPAL Select Alternate Palette

Selects an alternate palette for the 320-column graphics mode display:

0 = Green, red, yellow palette

1 = Cyan, magenta, white palette

4 ALTBAK Select Alternate Background

0 =No intense foreground or background colors

1 =Selects intense colors in graphics, and intense background colors in

text mode

3 SBINT Select Intense Border/Background

0 =Border/ f ore grou nd not intens e

1 =Intense border in text mode, intense background in 320x200 graphics,

intense foreground in 640x200 graphics

2 SBRED Select Red Border/Background

0 =No red component

1 =Red border in text mode, red background in 320x200 graphics, red

foreground in 640x200 graphics

1 SBGREEN Select Green Border/Background

0 =No green component

1 =Green border in text mode, green background in 320x200 graphics,

green foreground in 640x200 graphics

0 SBBLUE Select Blue Border/Background

0 =No blue component

1 =Blue border text mode, blue background in 320x200 graphics, blue

foreground in 640x200 graphics

PC/AT-Compatible Direct-Mapped Registers 2-139

CGA Status Register I/O Address 03DAh

Programming Notes

This register is visible only when the Comp_Mod bit in the Internal Graphics Control Register A (CSC

index DDh[0]) is cleared.

76543210

Bit Reserved VERTRET LPENSW LPENSTAT DMSTAT

Default 1111x1xx

R/W R RRRR

Bit Name Function

7–4 Reserved Reserved

Reads back ‘1111b’.

3 VERTRET Vertical Retrace Status (Simulated Vertical Sync)

0 = Raster is not in vertical retrace

1 = Raster is in vertical retrace

2 LPENSW Light Pen Switch

Always reads back logic 1.

1 LPENSTAT Light Pen Status

This bit will read 1 if I/O address 3DC was the most recent previously

accessed, or zero if I/O address 3DB was the most recent previously

accessed.

0DMSTAT Display-Memory Access Status (Simulated Horizontal Sync)

This bit is prov ided for softwar e compatibil ity purpos es. Th e lega cy

meanings for this bit are as shown bel ow. In actua lity, screen sparkle will

never occur.

0 = CPU access to video buffer RAM will cause screen sparkle

1 = CPU can access video buffer RAM without causing screen sparkle

PC/AT-Compatible Direct-Mapped Registers

2-140

Primar y 82365-Compatible PC Card I/O Address 03E0h

Controller Ind ex Registe r

Programming Notes

76543210

Bit PCM_IDX[7–0]

Default 00000000

R/W R/W

Bit Name Function

7–0 PCM_IDX[7–0] PC Card Controller Index Register

Write the offset of the 82365-compatible index register to access to this

port.

PC/AT-Compatible Direct-Mapped Registers 2-141

Primar y 82365-Compatible PC Card I/O Address 03E1h

Controlle r Data Port

Programming Notes

76543210

Bit PCM_DATA[7–0]

Default 00000000

R/W R/W

Bit Name Function

7–0 PCM_DATA[7–0] PC Card Data

Access 82365-compatible indexed registers via this port.

PC/AT-Compatible Direct-Mapped Registers

2-142

COM1 Transmi t H ol di ng Register I/O Address 03F8h

Programming Notes

There is only one serial port on the ÉlanSC400 microcontroller, but it can be configured to have a

base address of either 3F8h or 2F8h (COM1/COM2).

76543210

Bit COM1THR[7–0]

Default 00000000

R/W W

Bit Name Function

7–0 COM1THR[7–0] COM1 Transmit Holding Register

When COM1 DLAB = 0, and the transmitter is not busy, write the byte to

transmit to this register.

PC/AT-Compatible Direct-Mapped Registers 2-143

COM1 Receive Buffer Register I/O Address 03F8h

Programming Notes

76543210

Bit COM1RBR[7–0]

Default 00000000

R/W R

Bit Name Function

7–0 COM1RBR[7–0] COM1 Receive Buffer

When COM1 DLAB = 0, and a received byte is available, read received

byte from this register.

PC/AT-Compatible Direct-Mapped Registers

2-144

COM1 Baud Clock Diviso r Latch LSB I/O Address 03F8h

Programming Notes

76543210

Bit COM1_DIV[7–0]

Default 00000000

R/W R/W

Bit Name Function

7–0 COM1_DIV[7–0] COM1 Baud Block Divisor Latch

When COM1 DLAB = 1, this register holds the least significant byte of a

16-bit baud rate clock divisor that is used to generate the 16x baud clock.

PC/AT-Compatible Direct-Mapped Registers 2-145

COM1 Baud Clock Diviso r Latch MSB I/O Address 03F9h

Programming Notes

76543210

Bit COM1_DIV[15–8]

Default 00000000

R/W R/W

Bit Name Function

7–0 COM1_DIV[15–8] COM1 Baud Clock Divisor Latch

When COM1 DLAB = 1, this register holds the most significant byte of a

16-bit baud rate clock divisor that is used to generate the 16x baud clock.

PC/AT-Compatible Direct-Mapped Registers

2-146

COM1 Interrupt Enable Register I/O Address 03F9h

Programming Notes

76543210

Bit Reserved EMSI ERLSI ETHREI ERDAI

Default 00000000

R/W R/W R/W R/W R/W

Bit Name Function

7–4 Reserved Reserved

Software should write these bits to 0.

3EMSI Enable Modem Status Interrupt

0 = Disable mode m stat us interrupt

1 = Enable modem status interrupt

2ERLSI Enable Receiver Line Status Interrupt

0 = Disable receiver line status interrupt

1 = Enable receiver line status interrupt

1ETHREI Enable Transmitter Holding Register Empty Interrupt

0 = Disable transmitter holdin g register empty i nterrupt

1 = Enable transmitter holding register empty interrupt

0 ERDAI Enable Received Data Available Interrupt

0 =Disable data available/16550 time-out interrupt

1 =Enable received data available interrupt in 16450-compatible mode; in

16550-compatible mode, this bit also enables time-out interrupts

More de tail on time-out inte rrupts ca n be foun d in the Interrupt Id entifica tion

Regist er description.

PC/AT-Compatible Direct-Mapped Registers 2-147

COM1 Inter rupt ID Register I/O Address 03FAh

Programming Notes

76543210

Bit FIFO1

FIFO0 Reserved ID2

ID1

ID0 IP

Default 00001111

R/W RRR

Bit Name Function Priority

7–6 FIFO1

FIFO0 FIFO Feature Presence Indication

FIFO is only present when 16550-compatible mode is

enabled):

0 0 = No significance

0 1 = No significance

1 0 = 16450-co mpatible mode is ena ble d

1 1 = 16550-co mpatible mode is ena ble d

5–4 Reserved Reserved

These bits always read back ‘00b’.

3–1 ID2

ID1

ID0

Interrupt Identification Bit Field

0 0 0 =Modem status Fourth (Lowest)

0 0 1 =Transmitter Holding Register Empty/Transmit

FIFO Empty (16550-compatible mode) Third

0 1 0 =Received Data Available/Receiver FIFO

trigger (16550-compatible mode) Second

0 1 1 =Receive Line Status First (Highest)

1 0 0 =Not used

1 0 1 =Not used

1 1 0 =FIFO time-out Second

1 1 1 =Not used

In 16450-compatible mode, bit 3 always reads back

‘0b’. See the Modem Status Register (MSR) and Line

Status Register (LSR) for more detail on interrupt

events.

If two interrupt sources are pending simultaneously,

only the highest priority interrupt (as defined by the

rightmost column for bits 3–1) will be indicated by bits

3–1 of the Interrupt Identification Register (IIR). When

the inter rupt source is clear ed, a subsequ ent read from

the Interrupt Identification Register will return the next

highest priority interrupt source. Bits 3–1 have no

meaning if bit 0 = ‘1b’.

A FIFO time-out occurs when the receive FIFO is not

empty, and m ore than four c ontinu ous chara cter-tim es

have tran spired without more dat a being plac ed into or

read out o f the receive FIFO. Re ading a characte r from

the receive FIFO clears the time-out interrupt.

0IP Serial Port Interrupt Pending (Active Low)

0 = Interrupt pending

1 = No interrupt pend ing

PC/AT-Compatible Direct-Mapped Registers

2-148

COM1 FIFO Control Register I/O Address 03FAh

Programming Notes

The contents of this write-only register can be read back via the shadow register at CSC index D3h.

Also note that the on board UART can be mapped to only one of COM1 or COM2 at any time, and

CSC index D3h serves either configuration.

76543210

Bit RFRT[1–0] Reserved Reserved TFCLR RFCLR FIFOEN

Default 00000000

R/W W WWWW

Bit Name Function

7–6 RFRT[1–0] Receiver FIFO Register Trigger Bits

When in 16550-compatible mode, this bit field specifies the trigger level at

which the Interrupt Identification Register will report that a received data

available interrupt is pending. If received data available interrupts are

enabled in the IER, the system will be interrupted when the receive FIFO

fills to the trigger level per the following table:

0 0 = 1 byte

0 1 = 4 bytes

1 0 = 8 bytes

1 1 = 14 bytes

When the data i n the rece ive FIFO falls be low this tri gger leve l, the int errupt

will be cleared.

5–4 Reserved Reserved

Software should write these bits to 0.

3Reserved Reserved

Software should write this bit to 1.

2TFCLR Transmitter FIFO Buffer Clear

Writing a ‘1b’ to this bit position clears the transmit FIFO, and resets the

transmi t FIFO cou nter logic . It does not cl ear the Tr ansmitter Shif t Regist er.

This bi t is c le ared by ei the r a re ad of the Inte rrup t ID Reg is ter, or by a write

to the Transmit Holding Register.

1RFCLR Receiver FIFO Buffer Clear

Writing a ‘1b’ to this bit position clears the receive FIFO, and resets the

receive FIFO counter logic. It does not clear the Receiver Shift Register.

This bit is self clearing, and does not need to be reset to 0 under software

control.

0 FIFOEN FIFO Enable (16550-Comp at ible Mo de Enable )

0 =Causes UART to enter 16450-compatible mode

Disables accesses to receive and transmit FIFOs, and all FIFO control

bits except this bit.

1 =Causes UART to enter 16550-compatible mode

Enables receive and transmit FIFOs, and enables accesses to other

FIFO control bits.

The main difference between 16450-compatible mode and

16550-compatible mode is the addition of transmit and receive FIFOs in

16550-compatible mode.

This bit must be ‘1b’ when other FIFO control register bits are written to or

they wi ll not be program med. Also note tha t any mode sw itch will c lear both

FIFOs.

PC/AT-Compatible Direct-Mapped Registers 2-149

COM1 Line Control Regi ster I/O Address 03FBh

76543210

Bit DLAB SB SP EPS PE STP WLB0

WLB1

Default 00000000

R/W R/W R/W R/W R/W R/W R/W R/W R/W

Bit Name Function

7DLAB Divisor Latch Access Bit

Set this b it to gain acce ss to the b aud rate div isor latches for this COM po rt. Clear

this bit to mux in the Transmit Holding Register and Receive Buffer Register at

port xF8h, and the Interrupt Enable Register at port xF9h.

6SB Set Break Enable

Setting this bit causes a break condition to be transmitted to the receiving UART.

0 =Disable set br eak

1 =Force serial output to spa c ing st ate (logic ‘0’) regardless of other tr ansmitter

activity

The break control acts on the SOUT pin only, and has no other effect on the

transmitter logic.

5SP Stick Parity Enable

Forces the parity bit to always be 0 or 1 versus dynamically changing it so that

there are an odd or even number of 1 bits in the transmitted data. If this bit is 0,

then norm al parity is us ed if parity is enable d. If bits 5,4, and 3 = 1, the parity bit is

generate d/c hec k ed a s a log ic al 1. If bits 5 and 3 = 1 and bit 4 = 0, th e p arit y b it i s

generated/checked as a logical 0.

4 EPS Even Parity Select

Parity must be enabled via bit 3 for this bit to have meaning:

0 =Odd parity, the parity bit will be manipulated to force an odd number of 1 bits

in the transmitted data, and the same condition will be checked for in the

received data.

1 =Even parity, the parity bit will be manipulated to force an even number of 1

bits in the transmitted data, and the same condition will be checked for in the

received data.

Start/stop bits are not included in the parity generation/checking scheme.

3PE Asynchronous Data Parity Enable

Causes a parity bit to be generated in the transmitted data, and to be checked in

the rece iv ed data. The pa rity bi t i s loc ate d b etw e en the la st data word bit and the

first stop bit in the bit stream.

2STP Stop Bits

Based on character length from bits 1–0 above.

If character length = 5:

0 = 1 s top bit

1 = 1.5 stop bits

If character length = 6, 7, or 8:

0 = 1 s top bit

1 = 2 s top bits

1–0 WLB0

WLB1 Transmit/Receive Character Length

0 0 = 5 bits

0 1 = 6 bits

1 0 = 7 bits

1 1 = 8 bits

PC/AT-Compatible Direct-Mapped Registers

2-150

COM1 Modem Control Regi ster I/O Address 03FCh

Programming Notes

76543210

Bit Reserved LOOP OUT2 OUT1 RTS DTR

Default 00000000

R/W R/W R/W R/W R/W R/W

Bit Name Function

7–5 Reserved Reserved

Software should write these bits to 0.

4LOOP Loopback (Diagnostic Mode) Enable

1 =Enabled

The following internal connections are made by setting this diagnostic

bit:

RTS is in ternally connected to CTS

DTR is internally connected to DSR

OUT1 is internally connected to RI

OUT2 is internally connected to DCD

0 =Loopback mo de is dis ab led

In addition, the SOUT bit is driven High, and the SIN input line is blocked.

The Transmit Shift Out Register is directly connected to the receive shift in

inactive. Modem control interrupts can be forced by enabling the

appropriate bit in the IER, and asserting one of the bits 3–0 in loopback

mode.

3OUT2 Enable COM2 Interrupts

This bit controls the internal OUT2 signal which is used internally as a

master enable for COM1 interrupts. If this bit is not set, no COM port 1

IRQs will be felt at the Programmable Interrupt Controller (PIC).

2OUT1 OUT1 Control

This bit controls the internal OUT1 signal which is not tied to anything

internally. It is provided for PC/AT compatibility, and can be used as part of

the loopback diagnostics. Other than that, it has no effect on system

operation, and can be used for a scratch pad during normal system

operation.

1RTS Request to Send

0 = Deassert the Request To Send signal (RTS)

1 = Assert the Request To Send signal (RTS)

0DTR Data Terminal Ready

0 = Deassert the Data Terminal Ready signal (DTR)

1 = Assert the Data Terminal Ready signal (DTR)

PC/AT-Compatible Direct-Mapped Registers 2-151

COM1 Line Status Register I/O Address 03FDh

76543210

Bit 16550_ERR TEMT THRE BI FE PE OE DR

Default 01100000

R/W RRRRRRRR

Bit Name Function

7 16550_ERR 16550-Mode Error

In 16450-compatible mode, this bit reads back ‘0b’.

In 16550-compatible mode, when this bit is set it indicates at least one

parity erro r, framing erro r, or break condit ion is present i n the receiv e FIFO.

This bit is cleared by a read from the Line Status Register if there are no

subsequent errors in the FIFO.

6 TEMT Transmitter Empty Indicator

In 16450-compatible mode, this bit is set when both the Transmit Holding

In 16550-compatible mode, this bit is set when both the Transmit Shift

5THRE Transmitter Holding Register (16450-Compatible Mode) or Transmit

FIFO Empty (16550-Compatible Mode)

In 16450-compatible mode, this bit indicates that the Transmit Holding

by a write to the T ransmit Holdin g Register w hen in 16450 -compatible

mode.

In 16550-compatible mode, this bit indicates that the transmit FIFO is

completely empty. When in 16550-compatib le mode this interrupt will be