Publication Number S71WS512/256Nx0_CS Revision A Amendment 0 Issue Date November 8, 2004
ADVANCE
INFORMATION
S71WS512Nx0/S71WS256Nx0 Based MCPs
Stacked Multi-chip Product (MCP)
256/512 Megabit (32M/16M x 16 bit) CMOS
1.8 Volt-only Simultaneous Read/Write,
Burst-mode Flash Memory with
128/64Megabit (8M/4M x 16-Bit) CosmoRAM
Distinctive Characteristics
MCP Features
Power supply voltage of 1.7 to 1.95V
Burst Speed: 54MHz
Packages: 8 x 11.6 mm, 9 x 12 mm
Operating Temperature
-25°C to +85°C
-40°C to +85°C
General Description
The S71WS Series is a product line of stacked Multi-chip Product (MCP) packages
and consists of
One or more flash memory die
CosmoRAM-compatible pSRAM
The products covered by this document are listed in the table below. For details
about their specifications, please refer to the individual constituent datasheet for
further details.
Flash Density
512Mb 256Mb 128Mb 64Mb
pSRAM Density
128Mb S71WS512ND0 S71WS256ND0
64Mb S71WS512NC0 S71WS256NC0
32Mb
16Mb
2 S71WS512Nx0/S71WS256Nx0 S71WS512/256Nx0_CSA0 November 8, 2004
Advance Information
S71WS512Nx0/S71WS256Nx0 Based MCPs
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1
MCP Features ................................................................................................... 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .4
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .6
CosmoRAM Based Pinout ..................................................................................6
MCP Look-ahead Connection Diagram .........................................................7
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . .8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .9
Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . 10
256Mb WS256N Flash + 64Mb pSRAM ........................................................ 10
256Mb - WS256N Flash + 128 pSRAM ......................................................... 10
2x 256Mb—WS512N Flash + 64Mb pSRAM .................................................11
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 12
FEA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 mm MCP
Compatible Package ........................................................................................... 12
TSD084—84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 mm MCP
Compatible Package ............................................................................................13
TLA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 11.6x8.0x1.2 mm
MCP Compatible Package ................................................................................14
S29WSxxxN MirrorBit™ Flash Family
General Description . . . . . . . . . . . . . . . . . . . . . . . 15
Application Notes ........................................................................................... 18
Specification Bulletins .................................................................................... 18
Drivers and Software Support .................................................................... 18
CAD Modeling Support ................................................................................ 18
Technical Support ........................................................................................... 18
Spansion LLC Locations ........................................................18
Table 4.2. S29WS128N Sector & Memory Address Map .......... 20
Table 4.3. S29WS064N Sector & Memory Address Map .......... 21
Table 5.4. Device Operations .............................................. 22
Table 5.7. Address Latency for 5 Wait States (
≤
68 MHz) ........ 24
Table 5.8. Address Latency for 4 Wait States (
≤
54 MHz) ........ 25
Table 5.9. Address Latency for 3 Wait States (
≤
40 MHz) ........ 25
Table 5.10. Address/Boundary Crossing Latency for 6 Wait States
(
≤
80 MHz) ....................................................................... 25
Table 5.11. Address/Boundary Crossing Latency for 5 Wait States
(
≤
68 MHz) ....................................................................... 25
Table 5.12. Address/Boundary Crossing Latency for 4 Wait States
(
≤
54 MHz) ....................................................................... 25
Table 5.13. Address/Boundary Crossing Latency for 3 Wait States
(
≤
40 MHz) ....................................................................... 25
Figure 5.2. Synchronous Read ............................................. 26
Table 5.14. Burst Address Groups ....................................... 27
Table 5.15. Configuration Register ....................................... 28
Table 5.16. Autoselect Addresses ........................................ 29
Table 5.17. Autoselect Entry ............................................... 29
Table 5.18. Autoselect Exit ................................................. 30
Figure 5.19. Single Word Program ........................................ 32
Table 5.20. Single Word Program ........................................ 33
Table 5.21. Write Buffer Program ........................................ 35
Figure 5.22. Write Buffer Programming Operation .................. 36
Table 5.23. Sector Erase .................................................... 38
Figure 5.24. Sector Erase Operation ..................................... 39
Table 5.25. Chip Erase ....................................................... 40
Table 5.26. Erase Suspend ................................................. 41
Table 5.27. Erase Resume .................................................. 41
Table 5.28. Program Suspend ............................................. 42
Table 5.29. Program Resume .............................................. 42
Table 5.30. Unlock Bypass Entry .......................................... 43
Table 5.31. Unlock Bypass Program ..................................... 44
Table 5.32. Unlock Bypass Reset ......................................... 44
Figure 5.33. Write Operation Status Flowchart....................... 46
Table 5.34. DQ6 and DQ2 Indications ................................... 48
Table 5.35. Write Operation Status ...................................... 49
Table 5.36. Reset .............................................................. 51
Figure 6.2. Lock Register Program Algorithm......................... 57
Table 8.2. SecSi Sector Entry .............................................. 62
Table 8.3. SecSi Sector Program .......................................... 63
Table 8.4. SecSi Sector Entry .............................................. 63
Figure 9.2. Maximum Positive Overshoot Waveform ............... 64
Figure 9.3. Test Setup........................................................ 65
Figure 9.4. Input Waveforms and Measurement Levels........... 66
Figure 9.5. V
CC
Power-up Diagram....................................... 66
Figure 9.6. CLK Characterization.......................................... 68
Figure 9.7. CLK Synchronous Burst Mode Read...................... 70
Figure 9.8. 8-word Linear Burst with Wrap Around ................. 71
Figure 9.9. 8-word Linear Burst without Wrap Around ............ 71
Figure 9.10. Linear Burst with RDY Set One Cycle Before Data 72
Figure 9.11. Asynchronous Mode Read ................................. 73
Figure 9.12. Reset Timings ................................................. 74
Figure 9.2. Chip/Sector Erase Operation Timings: WE# Latched
Addresses......................................................................... 76
Figure 9.13. Asynchronous Program Operation Timings: WE#
Latched Addresses............................................................. 77
Figure 9.14. Synchronous Program Operation Timings:
CLK Latched Addresses ...................................................... 78
Figure 9.15. Accelerated Unlock Bypass Programming Timing.. 79
Figure 9.16. Data# Polling Timings
(During Embedded Algorithm) ............................................. 79
Figure 9.17. Toggle Bit Timings (During Embedded Algorithm) 80
Figure 9.18. Synchronous Data Polling
Timings/Toggle Bit Timings ................................................. 80
Figure 9.19. DQ2 vs. DQ6................................................... 81
Figure 9.20. Latency with Boundary Crossing when
Frequency > 66 MHz.......................................................... 81
Figure 9.21. Latency with Boundary Crossing into Program/
Erase Bank ....................................................................... 82
Figure 9.22. Example of Wait States Insertion ....................... 83
Figure 9.23. Back-to-Back Read/Write Cycle Timings.............. 84
Table 10.2. Sector Protection Commands .............................. 89
Table 10.3. CFI Query Identification String ............................ 90
Table 10.4. System Interface String ..................................... 91
Table 10.5. Device Geometry Definition ................................ 91
Table 10.6. Primary Vendor-Specific Extended Query ............. 92
CosmoRAM
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Pin Description (32M) . . . . . . . . . . . . . . . . . . . . . . .98
Functional Description . . . . . . . . . . . . . . . . . . . . . 99
Asynchronous Operation (Page Mode) .......................................................99
Functional Description . . . . . . . . . . . . . . . . . . . . 100
Synchronous Operation (Burst Mode) ...................................................... 100
State Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Initial/Standby State ............................................................................................101
Figure 11.7. Initial Standby State Diagram ......................... 101
Asynchronous Operation State .....................................................................101
Figure 11.8. Asynchronous Operation State Diagram............ 101
Synchronous Operation State .......................................................................102
Figure 11.9. Synchronous Operation Diagram...................... 102
Functional Description . . . . . . . . . . . . . . . . . . . . 102
Power-up ..............................................................................................................102
November 8, 2004 S71WS512/256Nx0_CSA0 S71WS512Nx0/S71WS256Nx0 3
Advance Information
Configuration Register ....................................................................................102
CR Set Sequence ...............................................................................................102
Address Key ....................................................................................................... 104
Power Down ......................................................................................................105
Burst Read/Write Operation ........................................................................105
Figure 11.10. Burst Read Operation.................................... 106
Figure 11.11. Burst Write Operation ................................... 106
CLK Input Function ..........................................................................................106
ADV# Input Function ...................................................................................... 107
WAIT# Output Function ................................................................................107
Latency .................................................................................................................108
Figure 11.12. Read Latency Diagram .................................. 108
Address Latch by ADV# .................................................................................109
Burst Length .......................................................................................................109
Single Write ........................................................................................................109
Write Control .....................................................................................................110
Figure 11.13. Write Controls.............................................. 110
Burst Read Suspend ...........................................................................................110
Figure 11.14. Burst Read Suspend Diagram......................... 111
Burst Write Suspend .......................................................................................... 111
Figure 11.15. Burst Write Suspend Diagram ........................ 111
Burst Read Termination .................................................................................... 111
Figure 11.16. Burst Read Termination Diagram .................... 112
Burst Write Termination ................................................................................112
Figure 11.17. Burst Write Termination Diagram.................... 112
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 113
Recommended Operating Conditions (See
Warning Below) . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Package Pin Capacitance . . . . . . . . . . . . . . . . . . . 113
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 114
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 115
Read Operation .................................................................................................. 115
Write Operation ................................................................................................ 117
Synchronous Operation - Clock Input (Burst Mode) .............................118
Synchronous Operation - Address Latch (Burst Mode) ........................118
Synchronous Read Operation (Burst Mode) ............................................. 119
Synchronous Write Operation (Burst Mode) ..........................................120
Power Down Parameters ................................................................................121
Other Timing Parameters ...............................................................................121
AC Test Conditions .......................................................................................... 121
AC Measurement Output Load Circuit .....................................................122
Figure 11.18. Output Load Circuit....................................... 122
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 11.19. Asynchronous Read Timing #1-1 (Basic Timing) 123
Figure 11.20. Asynchronous Read Timing #1-2 (Basic Timing) 123
Figure 11.21. Asynchronous Read Timing #2 (OE# & Address
Access)........................................................................... 124
Figure 11.22. Asynchronous Read Timing #3 (LB# / UB# Byte
Access)........................................................................... 124
Figure 11.23. Asynchronous Read Timing #4 (Page Address Access
after CE1# Control Access)................................................ 125
Figure 11.24. Asynchronous Read Timing #5 (Random and Page
Address Access)............................................................... 125
Figure 11.25. Asynchronous Write
Timing #1-1 (Basic Timing) ............................................... 126
Figure 11.26. Asynchronous Write
Timing #1-2 (Basic Timing) ............................................... 126
Figure 11.27. Asynchronous Write Timing #2 (WE# Control). 127
Figure 11.28. Asynchronous Write Timing #3-1 (WE# / LB# / UB#
Byte Write Control).......................................................... 127
Figure 11.29. Asynchronous Write Timing #3-2 (WE# / LB# / UB#
Byte Write Control).......................................................... 128
Figure 11.30. Asynchronous Write Timing #3-3 (WE# / LB# / UB#
Byte Write Control).......................................................... 128
Figure 11.31. Asynchronous Write Timing #3-4 (WE# / LB# / UB#
Byte Write Control).......................................................... 129
Figure 11.32. Asynchronous Read / Write Timing #1-1 (CE1#
Control) ......................................................................... 129
Figure 11.33. Asynchronous Read / Write Timing #1-2 (CE1# /
WE# / OE# Control) ........................................................ 130
Figure 11.34. Asynchronous Read / Write Timing #2 (OE#, WE#
Control) ......................................................................... 130
Figure 11.35. Asynchronous Read / Write Timing #3 (OE,# WE#,
LB#, UB# Control)........................................................... 131
Figure 11.36. Clock Input Timing....................................... 131
Figure 11.37. Address Latch Timing (Synchronous Mode)...... 132
Figure 11.38. 32M Synchronous Read
Timing #1 (OE# Control).................................................. 133
Figure 11.39. 32M Synchronous Read
Timing #2 (CE1# Control) ................................................ 134
Figure 11.40. 32M Synchronous Read
Timing #3 (ADV# Control)................................................ 135
Figure 11.41. Synchronous Read - WAIT# Output Timing
(Continuous Read)........................................................... 136
Figure 11.42. 64M Synchronous Read
Timing #1 (OE# Control).................................................. 137
Figure 11.43. 64M Synchronous Read
Timing #2 (CE1# Control) ................................................ 138
Figure 11.44. 64M Synchronous Read
Timing #3 (ADV# Control)................................................ 139
Figure 11.45. Synchronous Write
Timing #1 (WE# Level Control) ......................................... 140
Figure 11.46. Synchronous Write Timing #2 (WE# Single Clock
Pulse Control) ................................................................. 141
Figure 11.47. Synchronous Write Timing #3 (ADV# Control) . 142
Figure 11.48. Synchronous Write Timing #4 (WE# Level Control,
Single Write)................................................................... 143
Figure 11.49. 32M Synchronous Read to Write Timing #1(CE1#
Control) ......................................................................... 144
Figure 11.50. 32M Synchronous Read to Write Timing #2(ADV#
Control) ......................................................................... 145
Figure 11.51. 64M Synchronous Read to Write Timing #1(CE1#
Control) ......................................................................... 146
Figure 11.52. 64M Synchronous Read to Write Timing #2(ADV#
Control) ......................................................................... 147
Figure 11.53. Synchronous Write to Read Timing #1 (CE1#
Control) ......................................................................... 148
Figure 11.54. Synchronous Write to Read Timing #2 (ADV#
Control) ......................................................................... 149
Figure 11.55. Power-up Timing #1..................................... 150
Figure 11.56. Power-up Timing #2.................................... 150
Figure 11.57. Power Down Entry and Exit Timing................. 150
Figure 11.58. Standby Entry Timing after Read or Write ....... 151
Figure 11.59. Configuration Register Set Timing #1 (Asynchronous
Operation) ...................................................................... 151
Figure 11.60. Configuration Register Set Timing #2 (Synchronous
Operation) ...................................................................... 152
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 153
4 S71WS512Nx0/S71WS256Nx0 S71WS512/256Nx0_CS November 8, 2004
Product Selector Guide
WS256N + 64 pSRAM
WS256N + 128 pSRAM
WS512N + 64 pSRAM
Device-Model
pSRAM
density
Flash Speed
MHz
pSRAM
speed MHz DYB Bit s - Powe r Up Supplier Package
S71WS256NC0-AU
64M 54 54
0 (Protected)
COSMORAM 1 TLA084
S71WS256NC0-AZ 1(Unprotected [Default
State])
Device-Model
pSRAM
density
Flash Speed
MHz
pSRAM
speed MHz DYB Bits - Power Up Supplier Package
S71WS256ND0-EU
128M 54 54
0 (Protected)
COSMORAM 1
TSD084
9x12x1.2
S71WS256ND0-EZ
1 (Unprotected [Default state])
Device-Model
pSRAM
density
Flash Speed
MHz
pSRAM
speed
MHz DYB Bits - Power Up Supplier Package
S71WS512NC0-AU
64Mb 54 54
0 (Protected)
COSMORAM 1 TLA084
S71WS512NC0-AZ 1(Unprotected [Default
State])
November 8, 2004 S71WS512/256Nx0_CS S71WS512Nx0/S71WS256Nx0 5
MCP Block Diagram
Notes:
1. R-CE2 is only present in Cosmoram-compatible pSRAM.
2. For 1 Flash + pSRAM, F1-CE# = CE#. For 2 Flash + pSRAM, CE# = F1-CE# and F2-CE# is the chip-enable pin for the second Flash.
3. Only needed for S71WS512N.
4. For the 128M pSRAM devices, there are 23 shared addresses.
VID
VCC
RDY
pSRAM
Flash 1
DQ15 to DQ0
Flash-only Address
Shared Address
(Note 3) F1-CE#
ACC
R-UB#
R-CE2
R-VCC
VCC VCCQ
F-VCC
22
CLK CLK
WP#
OE#
WE#
F-RST#
AVD#
CE#
ACC
WP#
OE#
WE#
RESET#
AVD# RDY
VSS
VSSQ
DQ15 to DQ0
16
I/O15 to I/O0
16
R-CE1# CE#
WE#
OE#
UB#
R-LB# LB#
22
(Note 3) F2-CE#
CLK
AVD#
Flash 2
(Note 4)
WAIT#
CE2
6 S71WS512Nx0/S71WS256Nx0 S71WS512/256Nx0_CS November 8, 2004
Connection Diagrams
CosmoRAM Based Pinout
Notes:
1. In MCP's based on a single S29WS256N (S71WS256N), ball B5 is RFU. In MCP's based on two
S29WS256N (S71WS512), ball B5 is F2-CE#.
2. Addresses are shared between Flash and RAM depending on the density of the pSRAM.
MCP Flash-only Addresses Shared Addresses
S71WS256NC0 A23-A22 A21-A0
S71WS256ND0 A23 A22-A0
S71WS512NC0 A23-A22 A21-A0
S71WS512ND0 A23 A22-A0
A7
A3
A2
DQ8 DQ14
R-CE1#
R-LB# ACC WE# A8 A11
C3 C4 C5 C6 C7 C8
A6 R-UB# F-RST# R-CE2 A19 A12 A15
D2 D3 D4 D5 D7 D8 D9
A5 A18 RDY A20 A9 A13 A21
E2 E3 E4 E5 E6 E7 E8 E9
A1 A4 A17 A10 A14 A22
F2 F3 F4 F7 F8 F9
VSS DQ1A0 DQ6 RFU A16
G3 G4G2 G7 G8 G9
F1-CE#
DQ0
OE# DQ9 DQ3 DQ4 DQ13 DQ15 RFU
H2 H3 H4 H5 H6 H7 H8 H9
DQ10 F-VCC R-VCC DQ12 DQ7 VSS
J2 J3 J4 J5 J6 J7 J8 J9
DQ2 DQ11 RFU DQ5
K3 K8
K4 K5 K6 K7
RFU A23
F5
RFU RFU
G5
F6
G6
RFU CLK F2-CE# RFU RFU RFU
B3 B4 B5 B6 B7 B8
RFU RFU F-VCC RFU RFU RFU
L3 L4 L5 L6 L7 L8
B2 B9
C9
C2
K2 K9
L9L2
AVD# RFU
RFU
RFU
RFU
F-WP#
RFU
RFU
A1 A10
M1 M10
DNU
DNU
DNU
DNU
1st RAM Only
Shared
1st Flash Only
Legend
D6
2nd Flash Only
84-ball Fine-Pitch Ball Grid Array
CosmoRAM-based Pinout (Top View, Balls Facing Down)
November 8, 2004 S71WS512/256Nx0_CS S71WS512Nx0/S71WS256Nx0 7
MCP Look-ahead Connection Diagram
Notes:
1. In a 3.0V system, the GL device used as Data has to have WP tied to VCC.
2. F1 and F2 denote XIP/Flash, F3 and F4 denote Data/Companion Flash.
J4 J5 J6 J7 J8 J9
H7 H8 H9
F7F7 F8F8 F9F9
E7 E8 E9
D5
K3K3
D6 D7
F1-CE#
J3
OE#
R1-CE1# DQ0
D2
D3
C2 C3
AVD# VSS
See Table A7 A8WE#
D-DM0/
D1, D#
C4 C5 C6 C7
D8 D9
F3-CE#A11
C8 C9
F2-OE#R-OE#F-CLK#F-VCCF2-CE#CLK
A15A12A19
A21A13A9
A22A14A10
A16 A24DQ6
H6
F6F6
R1-CE2
A20
A23
R2-CE2
H4H4 H5
G5
F4F4 F5F5
E5
F-RST#
See TableA18
R2-CE1A17
R2-VCCDQ1
R-CREDQ15DQ13DQ4DQ3DQ9
K4K4 K7K7 K8K8 K9K9
DQ7R1-VCCF-VCCDQ10
H2H2 H3H3
F2F2 F3F3
E2 E3
A6A3
A5A2
A4A1
VSSA0
L4L4 L5L5 L6L6 L7L7 L8L8
L2
L2
L3L3
M2 M3
R-VCC DQ8
A27 A26
VSSDQ12
F-WP#DQ14DQ5A25DQ11DQ2
M4 M6 M8 M9
F-VCCQR-VCCQF4-CE#F-VCCVSS DNU
DNU
DNU
Legend:
Code Flash Only
DNU
(Do Not Use)
pSRAM Only
Flash/xRAM
Shared
K6
D4
B2
DNU
DNU
A1
DNU
DNU
B9
DNU
DNU
B10
DNU
DNU
DNU
DNU
DNU
DNU
DNU
P2
DNU
E4 E6
MirrorBit Data
Only
xRAM Shared
Flash/Data
Shared
See Table
M7
D2
D5
F5
NC
WP#/
ACC
RY/
BY#
F-WP#
ACC
F-RDY/
R-WAIT#
BALL 3.0V
Vcc
1.8V
Vcc
Table
D-DM1/
D11, D#
FASL Standard
MCP Packages
7.0 x 9.0mm
8.0 x 11.6mm
9.0 x 12.0mm
11.0 x 13.0mm
N9
P9 P10
N10
N1 N2
P1
M5
K2
L2
J2
K5
G2G2 G3G3 G4G4 G6G6 G7G7 G8G8 G9G9
L9
A9 A10
B1
A2
DNU
96-ball Fine-Pitch Ball Grid Array
(Top View, Balls Facing Down)
8 S71WS512Nx0/S71WS256Nx0 S71WS512/256Nx0_CS November 8, 2004
Input/Output Descriptions
A23-A0 = Address inputs
DQ15-DQ0 = Data input/output
OE# = Output Enable input. Asynchronous relative to CLK
for the Burst mode.
WE# = Write Enable input.
VSS = Ground
NC = No Connect; not connected internally
RDY = Ready output. Indicates the status of the Burst read.
The WAIT# pin of the pSRAM is tied to RDY.
CLK = Clock input. In burst mode, after the initial word is
output, subsequent active edges of CLK increment
the internal address counter. Should be at VIL or VIH
while in asynchronous mode
AVD# = Address Valid input. Indicates to device that the
valid address is present on the address inputs.
Low = for asynchronous mode, indicates valid
address; for burst mode, causes starting address to
be latched.
High = device ignores address inputs
F-RST# = Hardware reset input. Low = device resets and
returns to reading array data
F-WP# = Hardware write protect input. At VIL, disables
program and erase functions in the four outermost
sectors. Should be at VIH for all other conditions.
F-ACC = Accelerated input. At VHH, accelerates
programming; automatically places device in unlock
bypass mode. At VIL, disables all program and erase
functions. Should be at VIH for all other conditions.
R-CE1# = Chip-enable input for pSRAM.
R-CE2 = Chip-enable 2 for CosmoRAM only.
F1-CE# = Chip-enable input for Flash 1. Asynchronous relative
to CLK for Burst Mode.
F2-CE# = Chip-enable input for Flash 2. Asynchronous relative
to CLK for Burst Mode. This applies to the 512Mb
MCP only.
F-VCC = Flash 1.8 Volt-only single power supply.
R-VCC = pSRAM Power Supply.
R-UB# = Upper Byte Control (pSRAM).
R-LB# = Lower Byte Control (pSRAM).
DNU = Do Not Use.
November 8, 2004 S71WS512/256Nx0_CS S71WS512Nx0/S71WS256Nx0 9
Ordering Information
The order number (Valid Combination) is formed by the following:
S71WS 256 N C 0 BA W A U 0
PACKING TYPE
0=Tray
1=Tube
2 = 7” Tape and Reel
3=13” Tape and Reel
SUPPLIER, DYB, SPEED COMBINATION
U = 1 = COSMORAM 1, 0, 54MHz
Z = 1 = COSMORAM 1, 1, 54MHz
PACKAGE MODIFIER
A = 1.2mm, 8 x 11.6, 84-ball FBGA
Y = 1.4mm, 9 x 12, 84-ball FBGA
E = 1.2mm, 9 x 12, 84-ball FBGA
TEMPERATURE RANGE
W = Wireless (-25
°
C to +85
°
C)
I = Industrial (–40
°
C to +85
°
C)
PACKAGE TYPE
BA = Very Thin Fine-Pitch BGA
Lead (Pb)-free Compliant Package
BF = Very Thin Fine-Pitch BGA
Lead (Pb)-free Package
CHIP CONTENTS—2
No second content
CHIP CONTENTS—1
C = 64Mb
D = 128Mb
PROCESS TECHNOLOGY
N = 110nm MirrorBit™ Technology
FLASH DENSITY
512 = 512Mb (2x256Mb)
256 = 256Mb
DEVICE FAMILY
S71WS= Multi-Chip Product
1.8 Volt-only Simultaneous Read/Write Burst Mode
Flash Memory + xRAM
10 S71WS512Nx0/S71WS256Nx0 S71WS512/256Nx0_CS November 8, 2004
Valid Combinations
256Mb WS256N Flash + 64Mb pSRAM
256Mb - WS256N Flash + 128 pSRAM
Order Number Package Marking
Temperature
Range °C
Burst
Speed DYB Power- up State
Material
Set Supplier
S71WS256NC0BAWAU 71WS256NC0BAWAU
-25° to +85°C
54MHz
0(Protected)
Pb-free
compliant
CosmoRAM 1
S71WS256NC0BAWAZ 71WS256NC0BAWAZ 1(Unprotected [Default
State])
S71WS256NC0BAIAU 71WS256NC0BAIAU
-40° to +85°C
0(Sectors Protected)
CosmoRAM 1
S71WS256NC0BAIAZ 71WS256NC0BAIAZ 1(Unprotected [Default
State])
S71WS256NC0BFWAU 71WS256NC0BFWAU
-25° to +85°C
0(Protected)
Pb-free
CosmoRAM 1
S71WS256NC0BFWAZ 71WS256NC0BFWAZ 1(Unprotected [Default
State])
S71WS256NC0BFIAU 71WS256NC0BFIAU
-40° to +85°C
0(Protected)
CosmoRAM 1
S71WS256NC0BFIAZ 71WS256NC0BFIAZ 1(Unprotected [Default
State])
Order Number Package Marking
Temperature
Range °C
Burst
Speed DYB Power- up State
Material
Set Supplier
S71WS256ND0BAWEU 71WS256ND0BAWEU
-25° to +85°C
54MHz
0(Protected)
Pb-free
compliant
CosmoRAM 1
S71WS256ND0BAWEZ 71WS256ND0BAWEZ 1(Unprotected [Default
State])
S71WS256ND0BAIEU 71WS256ND0BAIEU
-40° to +85°C
0(Protected)
CosmoRAM 1
S71WS256ND0BAIEZ 71WS256ND0BAIEZ 1(Unprotected [Default
State])
S71WS256ND0BFWEU 71WS256ND0BFWEU
-25° to +85°C
0(Protected)
Pb-free
CosmoRAM 1
S71WS256ND0BFWEZ 71WS256ND0BFWEZ 1(Unprotected [Default
State])
S71WS256ND0BFIEU 71WS256ND0BFIEU
-40° to +85°C
0(Protected)
CosmoRAM 1
S71WS256ND0BFIEZ 71WS256ND0BFIEZ 1(Unprotected [Default
State])
November 8, 2004 S71WS512/256Nx0_CS S71WS512Nx0/S71WS256Nx0 11
2x 256Mb—WS512N Flash + 64Mb pSRAM
Order Number Package Marking
Temperature
Range °C
Burst
Speed DYB Power- up State
Material
Set Supplier
S71WS512NC0BAWAU 71WS512NC0BAWAU
-25° to +85°C
54MHz
0(Protected)
Pb-free
compliant
CosmoRAM 1
S71WS512NC0BAWAZ 71WS512NC0BAWAZ 1(Unprotected [Default
State])
S71WS512NC0BAIAU 71WS512NC0BAIAU
-40° to +85°C
0(Protected)
CosmoRAM 1
S71WS512NC0BAIAZ 71WS512NC0BAIAZ 1(Unprotected [Default
State])
S71WS512NC0BFWAU 71WS512NC0BFWAU
-25° to +85°C
0(Protected)
Pb-free
CosmoRAM 1
S71WS512NC0BFWAZ 71WS512NC0BFWAZ 1(Unprotected [Default
State])
S71WS512NC0BFIAU 71WS512NC0BFIAU
-40° to +85°C
0(Protected)
CosmoRAM 1
S71WS512NC0BFIAZ 71WS512NC0BFIAZ 1(Unprotected [Default
State])
12 S71WS512Nx0/S71WS256Nx0 S71WS512/256Nx0_CS November 8, 2004
Physical Dimensions
FEA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 mm MCP
Compatible Package
3423 \ 16-038.21a
PACKAGE FEA 084
JEDEC N/A
D x E 12.00 mm x 9.00 mm NOTE
PACKAGE
SYMBOL MIN NOM MAX
A --- --- 1.40 PROFILE
A1 0.10 --- --- BALL HEIGHT
A2 1.11 --- 1.26 BODY THICKNESS
D 12.00 BSC. BODY SIZE
E 9.00 BSC. BODY SIZE
D1 8.80 BSC. MATRIX FOOTPRINT
E1 7.20 BSC. MATRIX FOOTPRINT
MD 12 MATRIX SIZE D DIRECTION
ME 10 MATRIX SIZE E DIRECTION
n 84 BALL COUNT
Ø b 0.35 0.40 0.45 BALL DIAMETER
eE 0.80 BSC. BALL PITCH
eD 0.80 BSC BALL PITCH
SD / SE 0.40 BSC. SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALLS
B1,B10,C1,C10,D1,D10
E1,E10,F1,F10,G1,G10
H1,H10,J1,J10,K1,K10,L1,L10
M2,M3,M4,M5,M6,M7,M8,M9
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
4. e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
C
0.08
0.20 C
A
E
B
C
0.15
(2X)
C
D
C
0.15
(2X)
INDEX MARK
10
6
b
TOP VIEW
SIDE VIEW
CORNER
84X
A1
A2
A
PIN A1
ML
E1
7
SE
A
D1
eD
DCEFGHJ
K
10
8
9
7
6
4
3
2
1
eE
5
B
PIN A1
CORNER
7
SD
BOTTOM VIEW
0.15 C A BM
CM
0.08
November 8, 2004 S71WS512/256Nx0_CS S71WS512Nx0/S71WS256Nx0 13
TSD084—84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 mm MCP
Compatible Package
3426\ 16-038.22
PACKAGE TSD 084
JEDEC N/A
D x E 12.00 mm x 9.00 mm
PACKAGE
SYMBOL MIN NOM MAX NOTE
A --- --- 1.20 PROFILE
A1 0.17 --- --- BALL HEIGHT
A2 0.81 --- 0.94 BODY THICKNESS
D 12.00 BSC. BODY SIZE
E 9.00 BSC. BODY SIZE
D1 8.80 BSC. MATRIX FOOTPRINT
E1 7.20 BSC. MATRIX FOOTPRINT
MD 12 MATRIX SIZE D DIRECTION
ME 10 MATRIX SIZE E DIRECTION
n 84 BALL COUNT
φb 0.35 0.40 0.45 BALL DIAMETER
eE 0.80 BSC. BALL PITCH
eD 0.80 BSC BALL PITCH
SD / SE 0.40 BSC. SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,7,A8,A9 DEPOPULATED SOLDER BALLS
B1,B10,C1,C10,D1,D10
E1,E10,F1,F10,G1,G10
H1,H10,J1,J10,K1,K10,L1,L10
M2,M3,M4,M5,M6,M7,M8,M9
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
4. e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
C
0.08
0.20 C
A
E
B
C
0.15
(2X)
C
D
C
0.15
(2X)
INDEX MARK
10
6
b
TOP VIEW
SIDE VIEW
CORNER
84X
A1
A2
A
0.15 M C
MC
AB
0.08
PIN A1
BOTTOM VIEW
ML
E1
7
SE
A
D1
eD
DCEFGHJ
K
10
8
9
7
6
4
3
2
1
eE
5
B
PIN A1
CORNER
7
SD
14 S71WS512Nx0/S71WS256Nx0 S71WS512/256Nx0_CS November 8, 2004
TLA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 11.6x8.0x1.2 mm MCP
Compatible Package
Note: BSC is an ANSI standard for Basic Space Centering
3372-2 \ 16-038.22a
PACKAGE TLA 084
JEDEC N/A
D x E 11.60 mm x 8.00 mm
PACKAGE
SYMBOL MIN NOM MAX NOTE
A --- --- 1.20 PROFILE
A1 0.17 --- --- BALL HEIGHT
A2 0.81 --- 0.97 BODY THICKNESS
D 11.60 BSC. BODY SIZE
E 8.00 BSC. BODY SIZE
D1 8.80 BSC. MATRIX FOOTPRINT
E1 7.20 BSC. MATRIX FOOTPRINT
MD 12 MATRIX SIZE D DIRECTION
ME 10 MATRIX SIZE E DIRECTION
n 84 BALL COUNT
Ø b 0.35 0.40 0.45 BALL DIAMETER
eE 0.80 BSC. BALL PITCH
eD 0.80 BSC BALL PITCH
SD / SE 0.40 BSC. SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALLS
B1,B10,C1,C10,D1,D10,
E1,E10,F1,F10,G1,G10,
H1,H10,J1,J10,K1,K10,L1,L10,
M2,M3,M4,M5,M6,M7,M8,M9
NOTES:
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
4. e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
C
0.08
0.20 C
A
E
B
C
0.15
(2X)
C
D
C
0.15
(2X)
INDEX MARK
10
6
b
TOP VIEW
SIDE VIEW
CORNER
84X
A1
A2
A
0.15 C A BM
CM
0.08
PIN A1
ML
E1
7
SE
A
D1
eD
DCEFGHJ
K
10
8
9
7
6
4
3
2
1
eE
5
B
PIN A1
CORNER
7
SD
BOTTOM VIEW
Publication Number S29WSxxxN_M0 Revision F Amendment 0 Issue Date November 4, 2004
General Description
The Spansion S29WS256/128/064N are MirrorbitTM Flash products fabricated on 110 nm process technology. These burst
mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate
banks using separate data and address pins. They operate up to 80 MHz and use a single VCC of 1.7–1.95 volts that
makes them ideal for today’s demanding wireless applications requiring higher density, better performance and lowered
power consumption.
Distinctive Characteristics
Single 1.8 V read/program/erase (1.70–1.95 V)
110 nm MirrorBit™ Technology
Simultaneous Read/Write operation with zero
latency
32-word Write Buffer
Sixteen-bank architecture consisting of 16/8/4
Mbit for WS256N/128N/064N, respectively
Four 16 Kword sectors at both top and bottom of
memory array
254/126/62 64 Kword sectors (WS256N/128N/
064N)
Programmable burst read modes
— Linear for 32, 16 or 8 words linear read with or
without wrap-around
— Continuous sequential read mode
SecSi™ (Secured Silicon) Sector region consisting
of 128 words each for factory and customer
20-year data retention (typical)
Cycling Endurance: 100,000 cycles per sector
(typical)
RDY output indicates data available to system
Command set compatible with JEDEC standards
Hardware (WP#) protection of top and bottom
sectors
Dual boot sector configuration (top and bottom)
Offered Packages
— WS064N: 80-ball FBGA (7 mm x 9 mm)
— WS256N/128N: 84-ball FBGA (8 mm x 11.6 mm)
Low VCC write inhibit
Persistent and Password methods of Advanced
Sector Protection
Write operation status bits indicate program and
erase operation completion
Suspend and Resume commands for Program and
Erase operations
Unlock Bypass program command to reduce
programming time
Synchronous or Asynchronous program operation,
independent of burst control register settings
ACC input pin to reduce factory programming time
Support for Common Flash Interface (CFI)
Industrial Temperature range (contact factory)
Performance Characteristics
S29WSxxxN MirrorBit™ Flash Family
S29WS256N, S29WS128N, S29WS064N
256/128/64 Megabit (16/8/4 M x 16-Bit) CMOS 1.8 Volt-only
Simultaneous Read/Write, Burst Mode Flash Memory
Data Sheet PRELIMINARY
Read Access Times
Speed Option (MHz) 806654
Max. Synch. Latency, ns (tIACC) 696969
Max. Synch. Burst Access, ns (tBACC) 9 11.2 13.5
Max. Asynch. Access Time, ns (tACC) 707070
Max CE# Access Time, ns (tCE) 707070
Max OE# Access Time, ns (tOE) 11.2 11.2 13.5
Current Consumption (typical values)
Continuous Burst Read @ 66 MHz 35 mA
Simultaneous Operation (asynchronous) 50 mA
Program (asynchronous) 19 mA
Erase (asynchronous) 19 mA
Standby Mode (asynchronous) 20 µA
Typical Program & Erase Times
Single Word Programming 40 µs
Effective Write Buffer Programming (VCC) Per Word 9.4 µs
Effective Write Buffer Programming (VACC) Per Word 6 µs
Sector Erase (16 Kword Sector) 150 ms
Sector Erase (64 Kword Sector) 600 ms
16 S29WSxxxN MirrorBit™ Flash Family S29WSxxxN_M0F0 November 4, 2004
Preliminary
1 Input/Output Descriptions & Logic Symbol
Table identifies the input and output package connections provided on the device.
Table 1.1. Input/Output Descriptions
Symbol Type Description
A23–A0 Input Address lines for WS256N (A22-A0 for WS128 and A21-A0 for WS064N).
DQ15–DQ0 I/O Data input/output.
CE# Input Chip Enable. Asynchronous relative to CLK.
OE# Input Output Enable. Asynchronous relative to CLK.
WE# Input Write Enable.
VCC Supply Device Power Supply.
VIO Input VersatileIO Input. Should be tied to VCC.
VSS I/O Ground.
NC No Connect Not connected internally.
RDY Output Ready. Indicates when valid burst data is ready to be read.
CLK Input
Clock Input. In burst mode, after the initial word is output, subsequent active edges of CLK
increment the internal address counter. Should be at VIL or VIH while in asynchronous
mode.
AVD# Input
Address Valid. Indicates to device that the valid address is present on the address inputs.
When low during asynchronous mode, indicates valid address; when low during burst
mode, causes starting address to be latched at the next active clock edge.
When high, device ignores address inputs.
RESET# Input Hardware Reset. Low = device resets and returns to reading array data.
WP# Input Write Protect. At VIL, disables program and erase functions in the four outermost sectors.
Should be at VIH for all other conditions.
ACC Input
Acceleration Input. At VHH, accelerates programming; automatically places device in
unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for
all other conditions.
RFU Reserved Reserved for future use (see MCP look-ahead pinout for use with MCP).
November 4, 2004 S29WSxxxN_M0_F0 S29WSxxxN MirrorBit™ Flash Family 17
Preliminary
2 Block Diagram
Figure 2.1. S29WSxxxN Block Diagram
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
V
CC
Detector
State
Control
Command
Register
V
CC
V
SS
V
IO
WE#
RESET#
WP#
ACC
CE#
OE#
DQ15–DQ0
Data
Latch
Y-Gating
Cell Matrix
Address Latch
A
max
–A0*
RDY
Buffer RDY
Burst
State
Control
Burst
Address
Counter
AVD#
CLK
* WS256N: A23-A0
WS128N: A22-A0
WS064N: A21-A0
18 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
3 Additional Resources
Visit www.amd.com and www.fujitsu.com to obtain the following related documents:
Application Notes
Using the Operation Status Bits in AMD Devices
Understanding Burst Mode Flash Memory Devices
Simultaneous Read/Write vs. Erase Suspend/Resume
MirrorBit™ Flash Memory Write Buffer Programming and Page Buffer Read
Design-In Scalable Wireless Solutions with Spansion Products
Common Flash Interface Version 1.4 Vendor Specific Extensions
Specification Bulletins
Contact your local sales office for details.
Drivers and Software Support
Spansion low-level drivers
Enhanced Flash drivers
Flash file system
CAD Modeling Support
VHDL and Verilog
IBIS
ORCAD
Technical Support
Contact your local sales office or contact Spansion LLC directly for additional technical
support:
Email
US and Canada: HW.support@amd.com
Asia Pacific: asia.support@amd.com
Europe, Middle East, and Africa
Japan: http://edevice.fujitsu.com/jp/support/tech/#b7
Frequently Asked Questions (FAQ)
http://ask.amd.com/
http://edevice.fujitsu.com/jp/support/tech/#b7
Phone
US: (408) 749-5703
Japan (03) 5322-3324
Spansion LLC Locations
915 DeGuigne Drive, P.O. Box 3453
Sunnyvale, CA 94088-3453, USA
Telephone: 408-962-2500 or
1-866-SPANSION
Spansion Japan Limited
4-33-4 Nishi Shinjuku, Shinjuku-ku
Tokyo, 160-0023
Telephone: +81-3-5302-2200
Facsimile: +81-3-5302-2674
http://www.spansion.com
November 4, 2004 S29WSxxxN_M0_F0 19
Preliminary
4 Product Overview
The S29WSxxxN family consists of 256, 128 and 64Mbit, 1.8 volts-only, simultaneous read/
write burst mode Flash device optimized for today’s wireless designs that demand a large
storage array, rich functionality, and low power consumption. These devices are organized in
16, 8 or 4 Mwords of 16 bits each and are capable of continuous, synchronous (burst) read
or linear read (8-, 16-, or 32-word aligned group) with or without wrap around. These prod-
ucts also offer single word programming or a 32-word buffer for programming with program/
erase and suspend functionality. Additional features include:
Advanced Sector Protection methods for protecting sectors as required
256 words of secured silicon (SecSi™) area for storing customer and factory secured in-
formation. The SecSi Sector is One Time Programmable and Protectable (OTTP).
4.1 Memory Map
The S29WS256/128/064N Mbit devices consist of 16 banks organized as shown in Tables 4.1–
4.3.
Note: This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their
address ranges that are not explicitly listed (such as SA005–SA017) have sector starting and ending addresses that form the same
pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000h–xxFFFFh.
Table 4.1. S29WS256N Sector & Memory Address Map
Bank
Size
Sector
Count
Sector Size
(KB) Bank
Sector/
Sector Range Address Range Notes
2 MB 432 0
SA000 000000h–003FFFh
Contains four smaller sectors at
bottom of addressable memory.
SA001 004000h–007FFFh
SA002 008000h–00BFFFh
SA003 00C000h–00FFFFh
15 128 SA004 to SA018 010000h–01FFFFh to 0F0000h–0FFFFFh
All 128 KB sectors.
Pattern for sector address range
is xx0000h–xxFFFFh.
(see note)
2 MB 16 128 1 SA019 to SA034 100000h–10FFFFh to 1F0000h–1FFFFFh
2 MB 16 128 2 SA035 to SA050 200000h–20FFFFh to 2F0000h–2FFFFFh
2 MB 16 128 3 SA051 to SA066 300000h–30FFFFh to 3F0000h–3FFFFFh
2 MB 16 128 4 SA067 to SA082 400000h–40FFFFh to 4F0000h–4FFFFFh
2 MB 16 128 5 SA083 to SA098 500000h–50FFFFh to 5F0000h–5FFFFFh
2 MB 16 128 6 SA099 to SA114 600000h–60FFFFh to 6F0000h–6FFFFFh
2 MB 16 128 7 SA115 to SA130 700000h–70FFFFh to 7F0000h–7FFFFFh
2 MB 16 128 8 SA131 to SA146 800000h–80FFFFh to 8F0000h–8FFFFFh
2 MB 16 128 9 SA147 to SA162 900000h–90FFFFh to 9F0000h–9FFFFFh
2 MB 16 128 10 SA163 to SA178 A00000h–A0FFFFh to AF0000h–AFFFFFh
2 MB 16 128 11 SA179 to SA194 B00000h–B0FFFFh to BF0000h–BFFFFFh
2 MB 16 128 12 SA195 to SA210 C00000h–C0FFFFh to CF0000h–CFFFFFh
2 MB 16 128 13 SA211 to SA226 D00000h–D0FFFFh to DF0000h–DFFFFFh
2 MB 16 128 14 SA227 to SA242 E00000h–E0FFFFh to EF0000h–EFFFFFh
2 MB
15 128
15
SA243 to SA257 F00000h–F0FFFFh to FE0000h–FEFFFFh
432
SA258 FF0000h–FF3FFFh
Contains four smaller sectors at
top of addressable memory.
SA259 FF4000h–FF7FFFh
SA260 FF8000h–FFBFFFh
SA261 FFC000h–FFFFFFh
20 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
Note: This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their
address ranges that are not explicitly listed (such as SA005–SA009) have sector starting and ending addresses that form the same
pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000h–xxFFFFh.
Table 4.2. S29WS128N Sector & Memory Address Map
Bank Size
Sector
Count
Sector Size
(KB) Bank
Sector/
Sector Range Address Range Notes
1 MB 4
32
0
SA000 000000h–003FFFh
Contains four smaller sectors at
bottom of addressable memory.
32 SA001 004000h–007FFFh
32 SA002 008000h–00BFFFh
32 SA003 00C000h–00FFFFh
7128 SA004 to SA010 010000h–01FFFFh to 070000h–07FFFFh
All 128 KB sectors.
Pattern for sector address range
is xx0000h–xxFFFFh.
(see note)
1 MB 8128 1 SA011 to SA018 080000h–08FFFFh to 0F0000h–0FFFFFh
1 MB 8128 2 SA019 to SA026 100000h–10FFFFh to 170000h–17FFFFh
1 MB 8128 3 SA027 to SA034 180000h–18FFFFh to 1F0000h–1FFFFFh
1 MB 8128 4 SA035 to SA042 200000h–20FFFFh to 270000h–27FFFFh
1 MB 8128 5 SA043 to SA050 280000h–28FFFFh to 2F0000h–2FFFFFh
1 MB 8128 6 SA051 to SA058 300000h–30FFFFh to 370000h–37FFFFh
1 MB 8128 7 SA059 to SA066 380000h–38FFFFh to 3F0000h–3FFFFFh
1 MB 8128 8 SA067 to SA074 400000h–40FFFFh to 470000h–47FFFFh
1 MB 8128 9 SA075 to SA082 480000h–48FFFFh to 4F0000h–4FFFFFh
1 MB 8128 10 SA083 to SA090 500000h–50FFFFh to 570000h–57FFFFh
1 MB 8128 11 SA091 to SA098 580000h–58FFFFh to 5F0000h–5FFFFFh
1 MB 8128 12 SA099 to SA106 600000h–60FFFFh to 670000h–67FFFFh
1 MB 8128 13 SA107 to SA114 680000h–68FFFFh to 6F0000h–6FFFFFh
1 MB 8128 14 SA115 to SA122 700000h–70FFFFh to 770000h–77FFFFh
1 MB
7128
15
SA123 to SA129 780000h–78FFFFh to 7E0000h–7EFFFFh
4
32 SA130 7F0000h–7F3FFFh
Contains four smaller sectors at
top of addressable memory.
32 SA131 7F4000h–7F7FFFh
32 SA132 7F8000h–7FBFFFh
32 SA133 7FC000h–7FFFFFh
November 4, 2004 S29WSxxxN_M0_F0 21
Preliminary
Note: This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their
address ranges that are not explicitly listed (such as SA008–SA009) have sector starting and ending addresses that form the same
pattern as all other sectors of that size. For example, all 128 KB sectors have the pattern xx00000h–xxFFFFh.
Table 4.3. S29WS064N Sector & Memory Address Map
Bank Size
Sector
Count
Sector Size
(KB) Bank
Sector/
Sector Range Address Range Notes
0.5 MB
432
0
SA000 000000h–003FFFh
Contains four smaller sectors at
bottom of addressable memory.
SA001 004000h–007FFFh
SA002 008000h–00BFFFh
SA003 00C000h–00FFFFh
3
128
SA004 010000h–01FFFFh
All 128 KB sectors.
Pattern for sector address range is
xx0000h–xxFFFFh.
(see note)
SA005 020000h–02FFFFh
SA006 030000h–03FFFFh
0.5 MB 4128 1 SA007–SA010 040000h–04FFFFh to 070000h–07FFFFh
0.5 MB 4128 2 SA011–SA014 080000h–08FFFFh to 0B0000h–0BFFFFh
0.5 MB 4128 3 SA015–SA018 0C0000h–0CFFFFh to 0F0000h–0FFFFFh
0.5 MB 4128 4 SA019–SA022 100000h–10FFFFh to 130000h–13FFFFh
0.5 MB 4128 5 SA023–SA026 140000h–14FFFFh to 170000h–17FFFFh
0.5 MB 4128 6 SA027–SA030 180000h–18FFFFh to 1B0000h–1BFFFFh
0.5 MB 4128 7 SA031–SA034 1C0000h–1CFFFFh to 1F0000h–1FFFFFh
0.5 MB 4128 8 SA035–SA038 200000h–20FFFFh to 230000h–23FFFFh
0.5 MB 4128 9 SA039–SA042 240000h–24FFFFh to 270000h–27FFFFh
0.5 MB 4128 10 SA043–SA046 280000h–28FFFFh to 2B0000h–2BFFFFh
0.5 MB 4128 11 SA047–SA050 2C0000h–2CFFFFh to 2F0000h–2FFFFFh
0.5 MB 4128 12 SA051–SA054 300000h–30FFFFh to 330000h–33FFFFh
0.5 MB 4128 13 SA055–SA058 340000h–34FFFFh to 370000h–37FFFFh
0.5 MB 4128 14 SA059–SA062 380000h–38FFFFh to 3B0000h–3BFFFFh
0.5 MB
3128
15
SA063 3C0000h–3CFFFFh
SA064 3D0000h–3DFFFFh
SA065 3E0000h–3EFFFFh
432
SA066 3F0000h–3F3FFFh
Contains four smaller sectors at top
of addressable memory.
SA067 3F4000h–3F7FFFh
SA068 3F8000h–3FBFFFh
SA069 3FC000h–3FFFFFh
22 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
5 Device Operations
This section describes the read, program, erase, simultaneous read/write operations, hand-
shaking, and reset features of the Flash devices.
Operations are initiated by writing specific commands or a sequence with specific address and
data patterns into the command registers (see Tables 10.1 and 10.2). The command register
itself does not occupy any addressable memory location; rather, it is composed of latches that
store the commands, along with the address and data information needed to execute the
command. The contents of the register serve as input to the internal state machine and the
state machine outputs dictate the function of the device. Writing incorrect address and data
values or writing them in an improper sequence may place the device in an unknown state,
in which case the system must write the reset command to return the device to the reading
array data mode.
5.1 Device Operation Table
The device must be setup appropriately for each operation. Tab le 5. 4 describes the required
state of each control pin for any particular operation.
Ta b l e 5 . 4 . Device Operations
Legend: L = Logic 0, H = Logic 1, X = Don’t Care, I/O = Input/Output.
5.2 Asynchronous Read
All memories require access time to output array data. In an asynchronous read operation,
data is read from one memory location at a time. Addresses are presented to the device in
random order, and the propagation delay through the device causes the data on its outputs
to arrive asynchronously with the address on its inputs.
The device defaults to reading array data asynchronously after device power-up or hardware
reset. To read data from the memory array, the system must first assert a valid address on
Amax–A0, while driving AVD# and CE# to VIL. WE# should remain at VIH. The rising edge of
AVD# latches the address and data will appear on DQ15–DQ0 after address access time
(tACC), which is equal to the delay from stable addresses to valid output data. The chip enable
Operation
CE# OE# WE# Addresses DQ15–0 RESET# CLK AVD#
Asynchronous Read - Addresses Latched L L H Addr In Data Out H X
Asynchronous Read - Addresses Steady State L L H Addr In Data Out H X L
Asynchronous Write L H L Addr In I/O HX L
Synchronous Write L H L Addr In I/O H
Standby (CE#) H X X X HIGH Z H X X
Hardware Reset X X X X HIGH Z L X X
Burst Read Operations (Synchronous)
Load Starting Burst Address L X H Addr In X H
Advance Burst to next address with appropriate
Data presented on the Data Bus L L H X Burst
Data Out H H
Terminate current Burst read cycle H X H X HIGH Z H X
Terminate current Burst read cycle via RESET# X X H X HIGH Z L X X
Terminate current Burst read cycle and start new
Burst read cycle L X H Addr In I/O H
November 4, 2004 S29WSxxxN_M0_F0 23
Preliminary
access time (tCE) is the delay from the stable CE# to valid data at the outputs. The output
enable access time (tOE) is the delay from the falling edge of OE# to valid data at the output.
5.3 Synchronous (Burst) Read Mode &
Configuration Register
When a series of adjacent addresses needs to be read from the device (in order from lowest
to highest address), the synchronous (or burst read) mode can be used to significantly reduce
the overall time needed for the device to output array data. After an initial access time re-
quired for the data from the first address location, subsequent data is output synchronized to
a clock input provided by the system.
The device offers both continuous and linear methods of burst read operation, which are dis-
cussed in subsections 5.3.1 and 5.3.2, and 5.3.3.
Since the device defaults to asynchronous read mode after power-up or a hardware reset, the
configuration register must be set to enable the burst read mode. Other Configuration Regis-
ter settings include the number of wait states to insert before the initial word (tIACC) of each
burst access, the burst mode in which to operate, and when RDY will indicate data is ready
to be read. Prior to entering the burst mode, the system should first determine the configu-
ration register settings (and read the current register settings if desired via the Read
Configuration Register command sequence), and then write the configuration register com-
mand sequence. See Section 5.3.4, Configuration Register, and Table 10.1, Memory Array
Commands for further details.
Figure 5.1. Synchronous/Asynchronous State Diagram
The device outputs the initial word subject to the following operational conditions:
tIACC specification: the time from the rising edge of the first clock cycle after addresses
are latched to valid data on the device outputs.
configuration register setting CR13–CR11: the total number of clock cycles (wait states)
that occur before valid data appears on the device outputs. The effect is that tIACC is
lengthened.
Power-up/
Hardware Reset
Asynchronous Read
Mode Only
Synchronous Read
Mode Only
Set Burst Mode
Configuration Register
Command for
Synchronous Mode
(CR15 = 0)
Set Burst Mode
Configuration Register
Command for
Asynchronous Mode
(CR15 = 1)
24 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
The device outputs subsequent words tBACC after the active edge of each successive clock cy-
cle, which also increments the internal address counter. The device outputs burst data at this
rate subject to the following operational conditions:
starting address: whether the address is divisible by four (where A[1:0] is 00). A divisi-
ble-by-four address incurs the least number of additional wait states that occur after the
initial word. The number of additional wait states required increases for burst operations
in which the starting address is one, two, or three locations above the divisible-by-four
address (i.e., where A[1:0] is 01, 10, or 11).
boundary crossing: a physical aspect of the device that exists every 128 words, starting
at address 00007Fh. Higher operational speeds require one additional wait state. Refer to
Tab les 5.10–5.13 for details. Figure 9.20 shows the effects of boundary crossings at higher
frequencies.
clock frequency: the speed at which the device is expected to burst data. Higher speeds
require additional wait states after the initial word for proper operation. Ta b l es 5.7–5.13
show the effects of frequency on burst operation.
In all cases, with or without latency, the RDY output indicates when the next data is available
to be read.
Ta b le 5. 5 shows the latency that occurs in the S29WS256N device when (x indicates the rec-
ommended number of wait states for various operating frequencies, as shown in Table 5.15,
configuration register bits CR13-CR11).
Table s 5.7–5.9 show the effects of various combinations of the starting address, operating
frequency, and wait state setting (configuration register bits CR13–CR11) for the S29WS128N
and S29WS064N devices. Tables 5.10–5.13 includes the wait state that occurs when crossing
the internal boundary.
Table 5.5. Address Latency for x Wait States (≤ 80 MHz, WS256N only)
Ta b l e 5 . 6 . Address Latency for 6 Wait States (≤ 80 MHz)
Ta b l e 5 . 7 . Address Latency for 5 Wait States (≤ 68 MHz)
Word Wait States Cycle
0 x ws D0 D1 D2 D3 D4 D5 D6 D7 D8
1 x ws D1 D2 D3 1 ws D4 D5 D6 D7 D8
2 x ws D2 D3 1 ws 1 ws D4 D5 D6 D7 D8
3 x ws D3 1 ws 1 ws 1 ws D4 D5 D6 D7 D8
Word Wait States Cycle
0 6 ws D0 D1 D2 D3 D4 D5 D6 D7 D8
1 6 ws D1 D2 D3 1 ws D4 D5 D6 D7 D8
2 6 ws D2 D3 1 ws 1 ws D4 D5 D6 D7 D8
3 6 ws D3 1 ws 1 ws 1 ws D4 D5 D6 D7 D8
Word Wait States Cycle
0 5 ws D0 D1 D2 D3 D4 D5 D6 D7 D8
1 5 ws D1 D2 D3 D4 D5 D6 D7 D8 D9
2 5 ws D2 D3 1 ws D4 D5 D6 D7 D8 D9
3 5 ws D3 1 ws 1 ws D4 D5 D6 D7 D8 D9
November 4, 2004 S29WSxxxN_M0_F0 25
Preliminary
Ta b l e 5 . 8 . Address Latency for 4 Wait States (≤ 54 MHz)
Ta b l e 5 . 9 . Address Latency for 3 Wait States (≤ 40 MHz)
Ta b l e 5 . 1 0 . Address/Boundary Crossing Latency for 6 Wait States (≤ 80 MHz)
Ta b l e 5 . 1 1 . Address/Boundary Crossing Latency for 5 Wait States (≤ 68 MHz)
Ta b l e 5 . 1 2 . Address/Boundary Crossing Latency for 4 Wait States (≤ 54 MHz)
Ta b l e 5 . 1 3 . Address/Boundary Crossing Latency for 3 Wait States (≤ 40 MHz)
Word Wait States Cycle
0 4 ws D0 D1 D2 D3 D4 D5 D6 D7 D8
1 4 ws D1 D2 D3 D4 D5 D6 D7 D8 D9
2 4 ws D2 D3 D4 D5 D6 D7 D8 D9 D10
3 4 ws D3 1 ws D4 D5 D6 D7 D8 D9 D10
Word Wait States Cycle
0 3 ws D0 D1 D2 D3 D4 D5 D6 D7 D8
1 3 ws D1 D2 D3 D4 D5 D6 D7 D8 D9
2 3 ws D2 D3 D4 D5 D6 D7 D8 D9 D10
3 3 ws D3 D4 D5 D6 D7 D8 D9 D10 D11
Word Wait States Cycle
0 6 ws D0 D1 D2 D3 1 ws D4 D5 D6 D7
1 6 ws D1 D2 D3 1 ws 1 ws D4 D5 D6 D7
2 6 ws D2 D3 1 ws 1 ws 1 ws D4 D5 D6 D7
3 6 ws D3 1 ws 1 ws 1 ws 1 ws D4 D5 D6 D7
Word Wait States Cycle
0 5 ws D0 D1 D2 D3 D4 D5 D6 D7 D8
1 5 ws D1 D2 D3 1 ws D4 D5 D6 D7 D8
2 5 ws D2 D3 1 ws 1 ws D4 D5 D6 D7 D8
3 5 ws D3 1 ws 1 ws 1 ws D4 D5 D6 D7 D8
Word Wait States Cycle
0 4 ws D0 D1 D2 D3 D4 D5 D6 D7 D8
1 4 ws D1 D2 D3 D4 D5 D6 D7 D8 D9
2 4 ws D2 D3 1 ws D4 D5 D6 D7 D8 D9
3 4 ws D3 1 ws 1 ws D4 D5 D6 D7 D8 D9
Word Wait States Cycle
0 3 ws D0 D1 D2 D3 D4 D5 D6 D7 D8
1 3 ws D1 D2 D3 D4 D5 D6 D7 D8 D9
2 3 ws D2 D3 D4 D5 D6 D7 D8 D9 D10
3 3 ws D3 1 ws D4 D5 D6 D7 D8 D9 D10
26 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
Figure 5.2. Synchronous Read
5.3.1 Continuous Burst Read Mode
In the continuous burst read mode, the device outputs sequential burst data from the starting
address given and then wrap around to address 000000h when it reaches the highest addres-
sable memory location. The burst read mode will continue until the system drives CE# high,
RESET# low, or AVD# low in conjunction with a new address.
If the address being read crosses a 128-word line boundary and the subsequent word line is
not programming or erasing, additional latency cycles are required as shown in Tables 5.10–
5.13.
If the address crosses a bank boundary while the subsequent bank is programming or eras-
ing, the device will provide read status information and the clock will be ignored. Upon
completion of status read or program or erase operation, the host can restart a burst read
operation using a new address and AVD# pulse.
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Write Set Configuration Register
Command and Settings:
Address 555h, Data D0h
Address X00h, Data CR
Load Initial Address
Address = RA
Read Initial Data
RD = DQ[15:0]
Read Next Data
RD = DQ[15:0]
Wait tIACC +
Programmable Wait State Setting
Wait X Clocks:
Additional Latency Due to Starting
Address, Clock Frequency, and
Boundary Crossing
End of Data?
Yes
Crossing
Boundary?
No
Yes
Completed
Delay X Clocks
Unlock Cycle 1
Unlock Cycle 2
RA = Read Address
RD = Read Data
Command Cycle
CR = Configuration Register Bits CR15-CR0
CR13-CR11 sets initial access time
(from address latched to
valid data) from 2 to 7 clock cycles
See Tables 5.6–5.13 to determine total
number of clocks required for X.
November 4, 2004 S29WSxxxN_M0_F0 27
Preliminary
5.3.2 8-, 16-, 32-Word Linear Burst Read with Wrap Around
In a linear burst read operation, a fixed number of words (8, 16, or 32 words) are read from
consecutive addresses that are determined by the group within which the starting address
falls. The groups are sized according to the number of words read in a single burst sequence
for a given mode (see Table 5.14).
For example, if the starting address in the 8-word mode is 3Ch, the address range to be read
would be 38-3Fh, and the burst sequence would be 3C-3D-3E-3F-38-39-3A-3Bh. Thus, the
device outputs all words in that burst address group until all word are read, regardless of
where the starting address occurs in the address group, and then terminates the burst read.
In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence
on the starting address written to the device, then wrap back to the first address in the se-
lected address group.
Note that in this mode the address pointer does not cross the boundary that occurs every 128
words; thus, no wait states are inserted (except during the initial access).
Ta b l e 5 . 1 4 . Burst Address Groups
5.3.3 8-, 16-, 32-Word Linear Burst without Wrap Around
If wrap around is not enabled for linear burst read operations, the 8-word, 16-word, or 32-
word burst will execute up to the maximum memory address of the selected number of words.
The burst will stop after 8, 16, or 32 addresses and will not wrap around to the first address
of the selected group.
For example, if the starting address in the 8- word mode is 3Ch, the address range to be read
would be 39-40h, and the burst sequence would be 3C-3D-3E-3F-40-41-42-43h if wrap
around is not enabled. The next address to be read will require a new address and AVD#
pulse. Note that in this burst read mode, the address pointer may cross the boundary that
occurs every 128 words.
5.3.4 Configuration Register
The configuration register sets various operational features, most of which are associated
with burst mode. Upon power-up or hardware reset, the device defaults to the asynchronous
read mode, and the configuration register settings are in their default state. The host system
should determine the proper settings for the entire configuration register, and then execute
the Set Configuration Register command sequence, before attempting burst operations. The
configuration register is not reset after deasserting CE#. The Configuration Register can also
be read using a command sequence (see Ta b le 1 0 .1 ). The following list describes the register
settings.
Mode Group Size
Group Address Ranges
8-word 8 words 0-7h, 8-Fh, 10-17h,...
16-word 16 words 0-Fh, 10-1Fh, 20-2Fh,...
32-word 32 words 00-1Fh, 20-3Fh, 40-5Fh,...
28 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
Ta b l e 5 . 1 5 . Configuration Register
Reading the Configuration Table. The configuration register can be read with a four-cycle
command sequence. See Table 10.1 for sequence details. Once the data has been read from
the configuration register, a software reset command is required to set the device into the
correct state.
5.4 Autoselect
The Autoselect mode provides manufacturer and device identification, and sector protection
verification, through identifier codes output from the internal register (separate from the
memory array) on DQ15-DQ0. This mode is primarily intended for programming equipment
to automatically match a device to be programmed with its corresponding programming al-
gorithm. The Autoselect codes can also be accessed in-system. When verifying sector
protection, the sector address must appear on the appropriate highest order address bits (see
Tables 5.17 to 5.16). The remaining address bits are don't care. When all necessary bits have
been set as required, the programming equipment may then read the corresponding identifier
code on DQ15-DQ0. The Autoselect codes can also be accessed in-system through the com-
mand register. Note that if a Bank Address (BA) on the four uppermost address bits is
asserted during the third write cycle of the Autoselect command, the host system can read
Autoselect data from that bank and then immediately read array data from the other bank,
without exiting the Autoselect mode.
CR Bit Function
Settings (Binary)
CR15 Set Device Read Mode 0 = Synchronous Read (Burst Mode) Enabled
1 = Asynchronous Read Mode (default) Enabled
CR14 Boundary Crossing
0 = No extra boundary crossing latency
1 = With extra boundary crossing latency (default)
Must be set to “1” at higher operating frequencies. See Tables 5.10–5.13.
CR13
CR12
CR11
Programmable
Wait State
000 = Data valid on 2nd active CLK edge after addresses latched
001 = Data valid on 3rd active CLK edge after addresses latched
010 = Data valid on 4th active CLK edge after addresses latched (recommended for 54 MHz)
011 = Data valid on 5th active CLK edge after addresses latched (recommended for 66 MHz)
100 = Data valid on 6th active CLK edge after addresses latched (recommended for 80 MHz)
101 = Data valid on 7th active CLK edge after addresses latched (default)
110 = Reserved
111 = Reserved
Inserts wait states before initial data is available. Setting greater number of wait states before initial data
reduces latency after initial data. See Tables 5.6–5.13.
CR10 RDY Polarity 0 = RDY signal active low
1 = RDY signal active high (default)
CR9 Reserved 1 = default
CR8 RDY
0 = RDY active one clock cycle before data
1 = RDY active with data (default)
When CR13-CR11 are set to 000, RDY will be active with data regardless of CR8 setting.
CR7 Reserved 1 = default
CR6 Reserved 1 = default
CR5 Reserved 0 = default
CR4 Reserved 0 = default
CR3 Burst Wrap Around 0 = No Wrap Around Burst
1 = Wrap Around Burst (default)
CR2
CR1
CR0
Burst Length
000 = Continuous (default)
010 = 8-Word Linear Burst
011 = 16-Word Linear Burst
100 = 32-Word Linear Burst
(All other bit settings are reserved)
Note: Configuration Register will be in the default state upon power-up or hardware reset.
November 4, 2004 S29WSxxxN_M0_F0 29
Preliminary
To access the Autoselect codes, the host system must issue the Autoselect command.
The Autoselect command sequence may be written to an address within a bank that is
either in the read or erase-suspend-read mode.
The Autoselect command may not be written while the device is actively programming or
erasing in the other bank. Autoselect does not support simultaneous operations or burst
mode.
The system must write the reset command to return to the read mode (or erase-suspend-
read mode if the bank was previously in Erase Suspend).
See Tabl e 10 .1 for command sequence details.
Ta b l e 5 . 1 6 . Autoselect Addresses
Description Address Read Data
Manufacturer ID (BA) + 00h 0001h
Device ID, Word 1 (BA) + 01h 227Eh
Device ID, Word 2 (BA) + 0Eh
2230 (WS256N)
2231 (WS128N)
2232 (WS064N)
Device ID, Word 3 (BA) + 0Fh 2200
Indicator Bits
(See Note) (BA) + 03h
DQ15 - DQ8 = Reserved
DQ7 (Factory Lock Bit): 1 = Locked, 0 = Not Locked
DQ6 (Customer Lock Bit): 1 = Locked, 0 = Not Locked
DQ5 (Handshake Bit): 1 = Reserved, 0 = Standard Handshake
DQ4, DQ3 (WP# Protection Boot Code): 00 = WP# Protects both Top Boot and
Bottom Boot Sectors. 01, 10, 11 = Reserved
DQ2 = Reserved
DQ1 (DYB Power up State [Lock Register DQ4]): 1 = Unlocked (user option),
0 = Locked (default)
DQ0 (PPB Eraseability [Lock Register DQ3]): 1 = Erase allowed,
0 = Erase disabled
Sector Block Lock/
Unlock (SA) + 02h 0001h = Locked, 0000h = Unlocked
Note: For WS128N and WS064, DQ1 and DQ0 will be reserved.
Software Functions and Sample Code
Table 5.17. Autoselect Entry
(LLD Function = lld_AutoselectEntryCmd)
Cycle Operation Byte Address Word Address Data
Unlock Cycle 1 Write BAxAAAh BAx555h 0x00AAh
Unlock Cycle 2 Write BAx555h BAx2AAh 0x0055h
Autoselect Command Write BAxAAAh BAx555h 0x0090h
30 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
Notes:
1. Any offset within the device will work.
2. BA = Bank Address. The bank address is required.
3. base = base address.
The following is a C source code example of using the autoselect function to read the manu-
facturer ID. Refer to the Spansion Low Level Driver User’s Guide (available on www.amd.com
and www.fujitsu.com) for general information on Spansion Flash memory software develop-
ment guidelines.
/* Here is an example of Autoselect mode (getting manufacturer ID) */
/* Define UINT16 example: typedef unsigned short UINT16; */
UINT16 manuf_id;
/* Auto Select Entry */
*( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)bank_addr + 0x555 ) = 0x0090; /* write autoselect command */
/* multiple reads can be performed after entry */
manuf_id = *( (UINT16 *)bank_addr + 0x000 ); /* read manuf. id */
/* Autoselect exit */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* exit autoselect (write reset command) */
Table 5.18. Autoselect Exit
(LLD Function = lld_AutoselectExitCmd)
Cycle Operation Byte Address Word Address Data
Unlock Cycle 1 Write base + XXXh base + XXXh 0x00F0h
November 4, 2004 S29WSxxxN_M0_F0 31
Preliminary
5.5 Program/Erase Operations
These devices are capable of several modes of programming and or erase operations which
are described in details during the following sections. However, prior to any programming and
or erase operation, devices must be setup appropriately as outlined in Tab le 5 .4 .
During a synchronous write operation, to write a command or command sequence (which in-
cludes programming data to the device and erasing sectors of memory), the system must
drive AVD# and CE# to VIL, and OE# to VIH when providing an address to the device, and
drive WE# and CE# to VIL, and OE# to VIH when writing commands or data.
During an asynchronous write operation, the system must drive CE# and WE# to VIL and OE#
to VIH when providing an address, command, and data. Addresses are latched on the last fall-
ing edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE#.
Note the following:
When the Embedded Program algorithm is complete, the device then returns to the read
mode.
The system can determine the status of the program operation by using DQ7 or DQ6.
Refer to the Write Operation Status section for information on these status bits.
A “0” cannot be programmed back to a “1.” Attempting to do so will cause the device to
set DQ5 = 1 (halting any further operation and requiring a reset command). A succeeding
read will show that the data is still “0.”
Only erase operations can convert a “0” to a “1.”
Any commands written to the device during the Embedded Program Algorithm are ig-
nored except the Program Suspend command.
SecSi Sector, Autoselect, and CFI functions are unavailable when a program operation is
in progress.
A hardware reset immediately terminates the program operation and the program com-
mand sequence should be reinitiated once the device has returned to the read mode, to
ensure data integrity.
Programming is allowed in any sequence and across sector boundaries for single word
programming operation.
Programming to the same word address multiple times without intervening erases is lim-
ited. For such application requirements, please contact your local Spansion representa-
tive.
5.5.1. Single Word Programming
Single word programming mode is the simplest method of programming. In this mode, four
Flash command write cycles are used to program an individual Flash address. The data for
this programming operation could be 8-, 16- or 32-bits wide. While this method is supported
by all Spansion devices, in general it is not recommended for devices that support Write
Buffer Programming. See Tab le 1 0. 1 for the required bus cycles and Figure 5.19 for the
flowchart.
When the Embedded Program algorithm is complete, the device then returns to the read
mode and addresses are no longer latched. The system can determine the status of the pro-
gram operation by using DQ7 or DQ6. Refer to the Write Operation Status section for
information on these status bits.
During programming, any command (except the Suspend Program command) is ignored.
The SecSi Sector, Autoselect, and CFI functions are unavailable when a program opera-
tion is in progress.
32 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
A hardware reset immediately terminates the program operation. The program command
sequence should be reinitiated once the device has returned to the read mode, to ensure
data integrity.
Programming to the same address multiple times continuously (for example, “walking” a
bit within a word) for an extended period is not recommended. For more information,
contact your local sales office.
Figure 5.19. Single Word Program
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Write Program Command:
Address 555h, Data A0h
Program Data to Address:
PA, PD
Unlock Cycle 1
Unlock Cycle 2
Setup Command
Program Address (PA),
Program Data (PD)
FAIL. Issue reset command
to return to read array mode.
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Yes
No
No
Polling Status
= Busy?
Polling Status
= Done?
Error condition
(Exceeded Timing Limits)
PASS. Device is in
read mode.
November 4, 2004 S29WSxxxN_M0_F0 33
Preliminary
Note: Base = Base Address.
The following is a C source code example of using the single word program function. Refer to
the Spansion Low Level Driver User’s Guide (available on www.amd.com and
www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
/* Example: Program Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)base_addr + 0x555 ) = 0x00A0; /* write program setup command */
*( (UINT16 *)pa ) = data; /* write data to be programmed */
/* Poll for program completion */
5.5.2 Write Buffer Programming
Write Buffer Programming allows the system to write a maximum of 32 words in one pro-
gramming operation. This results in a faster effective word programming time than the
standard “word” programming algorithms. The Write Buffer Programming command se-
quence is initiated by first writing two unlock cycles. This is followed by a third write cycle
containing the Write Buffer Load command written at the Sector Address in which program-
ming will occur. At this point, the system writes the number of “word locations minus 1” that
will be loaded into the page buffer at the Sector Address in which programming will occur.
This tells the device how many write buffer addresses will be loaded with data and therefore
when to expect the “Program Buffer to Flash” confirm command. The number of locations to
program cannot exceed the size of the write buffer or the operation will abort. (Number
loaded = the number of locations to program minus 1. For example, if the system will pro-
gram 6 address locations, then 05h should be written to the device.)
The system then writes the starting address/data combination. This starting address is the
first address/data pair to be programmed, and selects the “write-buffer-page” address. All
subsequent address/data pairs must fall within the elected-write-buffer-page.
The “write-buffer-page” is selected by using the addresses AMAX - A5.
The “write-buffer-page” addresses must be the same for all address/data pairs loaded into
the write buffer. (This means Write Buffer Programming cannot be performed across multiple
“write-buffer-pages.” This also means that Write Buffer Programming cannot be performed
across multiple sectors. If the system attempts to load programming data outside of the se-
lected “write-buffer-page”, the operation will ABORT.)
After writing the Starting Address/Data pair, the system then writes the remaining address/
data pairs into the write buffer.
Note that if a Write Buffer address location is loaded multiple times, the “address/data pair”
counter will be decremented for every data load operation. Also, the last data loaded at a lo-
cation before the “Program Buffer to Flash” confirm command will be programmed into the
Software Functions and Sample Code
Ta b l e 5 . 2 0 . S i n g l e Wo r d P r o g r a m
(LLD Function = lld_ProgramCmd)
Cycle Operation Byte Address Word Address Data
Unlock Cycle 1 Write Base + AAAh Base + 555h 00AAh
Unlock Cycle 2 Write Base + 554h Base + 2AAh 0055h
Program Setup Write Base + AAAh Base + 555h 00A0h
Program Write Word Address Word Address Data Word
34 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
device. It is the software's responsibility to comprehend ramifications of loading a write-buffer
location more than once. The counter decrements for each data load operation, NOT for each
unique write-buffer-address location. Once the specified number of write buffer locations
have been loaded, the system must then write the “Program Buffer to Flash” command at the
Sector Address. Any other address/data write combinations will abort the Write Buffer Pro-
gramming operation. The device will then “go busy.” The Data Bar polling techniques should
be used while monitoring the last address location loaded into the write buffer. This eliminates
the need to store an address in memory because the system can load the last address loca-
tion, issue the program confirm command at the last loaded address location, and then data
bar poll at that same address. DQ7, DQ6, DQ5, DQ2, and DQ1 should be monitored to deter-
mine the device status during Write Buffer Programming.
The write-buffer “embedded” programming operation can be suspended using the standard
suspend/resume commands. Upon successful completion of the Write Buffer Programming
operation, the device will return to READ mode.
The Write Buffer Programming Sequence is ABORTED under any of the following conditions:
Load a value that is greater than the page buffer size during the “Number of Locations to
Program” step.
Write to an address in a sector different than the one specified during the Write-Buffer-
Load command.
Write an Address/Data pair to a different write-buffer-page than the one selected by the
“Starting Address” during the “write buffer data loading” stage of the operation.
Write data other than the “Confirm Command” after the specified number of “data load”
cycles.
The ABORT condition is indicated by DQ1 = 1, DQ7 = DATA# (for the “last address location
loaded”), DQ6 = TOGGLE, DQ5 = 0. This indicates that the Write Buffer Programming Oper-
ation was ABORTED. A “Write-to-Buffer-Abort reset” command sequence is required when
using the write buffer Programming features in Unlock Bypass mode. Note that the SecSITM
sector, autoselect, and CFI functions are unavailable when a program operation is in progress.
Write buffer programming is allowed in any sequence of memory (or address) locations.
These flash devices are capable of handling multiple write buffer programming operations on
the same write buffer address range without intervening erases. However, programming the
same word address multiple times without intervening erases requires a modified program-
ming method. Please contact your local SpansionTM representative for details.
Use of the write buffer is strongly recommended for programming when multiple words are
to be programmed. Write buffer programming is approximately eight times faster than pro-
gramming one word at a time.
November 4, 2004 S29WSxxxN_M0_F0 35
Preliminary
Notes:
1. Base = Base Address.
2. Last = Last cycle of write buffer program operation; depending on number of
words written, the total number of cycles may be from 6 to 37.
3. For maximum efficiency, it is recommended that the write buffer be loaded with
the highest number of words (N words) possible.
The following is a C source code example of using the write buffer program function. Refer to
the Spansion Low Level Driver User’s Guide (available on www.amd.com and
www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
/* Example: Write Buffer Programming Command */
/* NOTES: Write buffer programming limited to 16 words. */
/* All addresses to be written to the flash in */
/* one operation must be within the same flash */
/* page. A flash page begins at addresses */
/* evenly divisible by 0x20. */
UINT16 *src = source_of_data; /* address of source data */
UINT16 *dst = destination_of_data; /* flash destination address */
UINT16 wc = words_to_program -1; /* word count (minus 1) */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)sector_address ) = 0x0025; /* write write buffer load command */
*( (UINT16 *)sector_address ) = wc; /* write word count (minus 1) */
loop:
*dst = *src; /* ALL dst MUST BE SAME PAGE */ /* write source data to destination */
dst++; /* increment destination pointer */
src++; /* increment source pointer */
if (wc == 0) goto confirm /* done when word count equals zero */
wc--; /* decrement word count */
goto loop; /* do it again */
confirm:
*( (UINT16 *)sector_address ) = 0x0029; /* write confirm command */
/* poll for completion */
/* Example: Write Buffer Abort Reset */
*( (UINT16 *)addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)addr + 0x555 ) = 0x00F0; /* write buffer abort reset */
Software Functions and Sample Code
Table 5.21. Write Buffer Program
(LLD Functions Used = lld_WriteToBufferCmd, lld_ProgramBufferToFlashCmd)
Cycle Description Operation Byte Address Word Address Data
1 Unlock Write Base + AAAh Base + 555h 00AAh
2 Unlock Write Base + 554h Base + 2AAh 0055h
3 Write Buffer Load Command Write Program Address 0025h
4 Write Word Count Write Program Address Word Count (N–1)h
Number of words (N) loaded into the write buffer can be from 1 to 32 words.
5 to 36 Load Buffer Word N Write Program Address, Word N Word N
Last Write Buffer to Flash Write Sector Address 0029h
36 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
Figure 5.22. Write Buffer Programming Operation
5.5.3 Sector Erase
The sector erase function erases one or more sectors in the memory array. (See Table 10.1,
Memory Array Commands; and Figure 5.24, Sector Erase Operation.) The device does not
require the system to preprogram prior to erase. The Embedded Erase algorithm automati-
cally programs and verifies the entire memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of no less than tSEA occurs.
During the time-out period, additional sector addresses and sector erase commands may be
written. Loading the sector erase buffer may be done in any sequence, and the number of
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Issue
Write Buffer Load Command:
Address 555h, Data 25h
Load Word Count to Program
Program Data to Address:
SA = wc
Unlock Cycle 1
Unlock Cycle 2
wc = number of words – 1
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
wc = 0?
Write Buffer
Abort Desired?
Write Buffer
Abort?
Polling Status
= Done?
Error?
FAIL. Issue reset command
to return to read array mode.
Write to a Different
Sector Address to Cause
Write Buffer Abort
PASS. Device is in
read mode.
Confirm command:
SA 29h
Wait 4 µs
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Write Next Word,
Decrement wc:
PA data , wc = wc – 1
RESET. Issue Write Buffer
Abort Reset Command
November 4, 2004 S29WSxxxN_M0_F0 37
Preliminary
sectors may be from one sector to all sectors. The time between these additional cycles must
be less than tSEA. Any sector erase address and command following the exceeded time-out
(tSEA) may or may not be accepted. Any command other than Sector Erase or Erase Suspend
during the time-out period resets that bank to the read mode. The system can monitor DQ3
to determine if the sector erase timer has timed out (See the “DQ3: Sector Erase Timer” sec-
tion.) The time-out begins from the rising edge of the final WE# pulse in the command
sequence.
When the Embedded Erase algorithm is complete, the bank returns to reading array data and
addresses are no longer latched. Note that while the Embedded Erase operation is in
progress, the system can read data from the non-erasing banks. The system can determine
the status of the erase operation by reading DQ7 or DQ6/DQ2 in the erasing bank. Refer to
“Write Operation Status” for information on these status bits.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All
other commands are ignored. However, note that a hardware reset immediately terminates
the erase operation. If that occurs, the sector erase command sequence should be reinitiated
once that bank has returned to reading array data, to ensure data integrity.
Figure 5.24 illustrates the algorithm for the erase operation. Refer to the “Erase/Program Op-
erations” section for parameters and timing diagrams.
38 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
The following is a C source code example of using the sector erase function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Sector Erase Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)base_addr + 0x555 ) = 0x0080; /* write setup command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write additional unlock cycle 1 */
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write additional unlock cycle 2 */
*( (UINT16 *)sector_address ) = 0x0030; /* write sector erase command */
Software Functions and Sample Code
Table 5.23. Sector Erase
(LLD Function = lld_SectorEraseCmd)
Cycle Description Operation Byte Address Word Address Data
1 Unlock Write Base + AAAh Base + 555h 00AAh
2 Unlock Write Base + 554h Base + 2AAh 0055h
3 Setup Command Write Base + AAAh Base + 555h 0080h
4 Unlock Write Base + AAAh Base + 555h 00AAh
5 Unlock Write Base + 554h Base + 2AAh 0055h
6 Sector Erase Command Write Sector Address Sector Address 0030h
Unlimited additional sectors may be selected for erase; command(s) must be written within t
SEA
.
November 4, 2004 S29WSxxxN_M0_F0 39
Preliminary
Figure 5.24. Sector Erase Operation
No
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Write Sector Erase Cycles:
Address 555h, Data 80h
Address 555h, Data AAh
Address 2AAh, Data 55h
Sector Address, Data 30h
Write Additional
Sector Addresses
FAIL. Write reset command
to return to reading array.
PASS. Device returns
to reading array.
Wait 4 µs
Perform Write Operation
Status Algorithm
Select
Additional
Sectors?
Unlock Cycle 1
Unlock Cycle 2
Yes
Yes
Yes
Yes
Yes
No
No
No
No
Last Sector
Selected?
Done?
DQ5 = 1?
Command Cycle 1
Command Cycle 2
Command Cycle 3
Specify first sector for erasure
Error condition (Exceeded Timing Limits)
Status may be obtained by reading DQ7, DQ6 and/or DQ2.
Poll DQ3.
DQ3 = 1?
• Each additional cycle must be written within tSEA timeout
• Timeout resets after each additional cycle is written
• The host system may monitor DQ3 or wait tSEA to ensure
acceptance of erase commands
• No limit on number of sectors
• Commands other than Erase Suspend or selecting
additional sectors for erasure during timeout reset device
to reading array data
Notes:
1. See Table 10.1 for erase command sequence.
2. See the section on DQ3 for information on the sector erase timeout.
(see Figure 5.33)
40 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
5.5.4 Chip Erase Command Sequence
Chip erase is a six-bus cycle operation as indicated by Table 10.1. These commands invoke
the Embedded Erase algorithm, which does not require the system to preprogram prior to
erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations. The “Command Definition” section
in the appendix shows the address and data requirements for the chip erase command
sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read mode and
addresses are no longer latched. The system can determine the status of the erase operation
by using DQ7 or DQ6/DQ2. Refer to “Write Operation Status” for information on these status
bits.
Any commands written during the chip erase operation are ignored. However, note that a
hardware reset immediately terminates the erase operation. If that occurs, the chip erase
command sequence should be reinitiated once that bank has returned to reading array data,
to ensure data integrity.
The following is a C source code example of using the chip erase function. Refer to the Span-
sion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for
general information on Spansion Flash memory software development guidelines.
/* Example: Chip Erase Command */
/* Note: Cannot be suspended */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)base_addr + 0x555 ) = 0x0080; /* write setup command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write additional unlock cycle 1 */
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write additional unlock cycle 2 */
*( (UINT16 *)base_addr + 0x000 ) = 0x0010; /* write chip erase command */
5.5.5 Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase operation and
then read data from, or program data to, any sector not selected for erasure. The bank ad-
dress is required when writing this command. This command is valid only during the sector
erase operation, including the minimum tSEA time-out period during the sector erase com-
mand sequence. The Erase Suspend command is ignored if written during the chip erase
operation.
When the Erase Suspend command is written during the sector erase operation, the device
requires a maximum of tESL (erase suspend latency) to suspend the erase operation. How-
Software Functions and Sample Code
Table 5.25. Chip Erase
(LLD Function = lld_ChipEraseCmd)
Cycle Description Operation Byte Address Word Address Data
1 Unlock Write Base + AAAh Base + 555h 00AAh
2 Unlock Write Base + 554h Base + 2AAh 0055h
3 Setup Command Write Base + AAAh Base + 555h 0080h
4 Unlock Write Base + AAAh Base + 555h 00AAh
5 Unlock Write Base + 554h Base + 2AAh 0055h
6 Chip Erase Command Write Base + AAAh Base + 555h 0010h
November 4, 2004 S29WSxxxN_M0_F0 41
Preliminary
ever, when the Erase Suspend command is written during the sector erase time-out, the
device immediately terminates the time-out period and suspends the erase operation.
After the erase operation has been suspended, the bank enters the erase-suspend-read
mode. The system can read data from or program data to any sector not selected for erasure.
(The device “erase suspends” all sectors selected for erasure.) Reading at any address within
erase-suspended sectors produces status information on DQ7-DQ0. The system can use DQ7,
or DQ6, and DQ2 together, to determine if a sector is actively erasing or is erase-suspended.
Refer to Ta b l e 5 .3 5 for information on these status bits.
After an erase-suspended program operation is complete, the bank returns to the erase-sus-
pend-read mode. The system can determine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard program operation.
In the erase-suspend-read mode, the system can also issue the Autoselect command se-
quence. Refer to the “Write Buffer Programming Operation” section and the “Autoselect
Command Sequence” section for details.
To resume the sector erase operation, the system must write the Erase Resume command.
The bank address of the erase-suspended bank is required when writing this command. Fur-
ther writes of the Resume command are ignored. Another Erase Suspend command can be
written after the chip has resumed erasing.
The following is a C source code example of using the erase suspend function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Erase suspend command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x00B0; /* write suspend command */
The following is a C source code example of using the erase resume function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Erase resume command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x0030; /* write resume command */
/* The flash needs adequate time in the resume state */
5.5.6 Program Suspend/Program Resume Commands
The Program Suspend command allows the system to interrupt an embedded programming
operation or a “Write to Buffer” programming operation so that data can read from any non-
suspended sector. When the Program Suspend command is written during a programming
process, the device halts the programming operation within tPSL (program suspend latency)
Software Functions and Sample Code
Table 5.26. Erase Suspend
(LLD Function = lld_EraseSuspendCmd)
Cycle Operation Byte Address Word Address Data
1 Write Bank Address Bank Address 00B0h
Table 5.27. Erase Resume
(LLD Function = lld_EraseResumeCmd)
Cycle Operation Byte Address Word Address Data
1 Write Bank Address Bank Address 0030h
42 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
and updates the status bits. Addresses are “don't-cares” when writing the Program Suspend
command.
After the programming operation has been suspended, the system can read array data from
any non-suspended sector. The Program Suspend command may also be issued during a pro-
gramming operation while an erase is suspended. In this case, data may be read from any
addresses not in Erase Suspend or Program Suspend. If a read is needed from the SecSi Sec-
tor area, then user must use the proper command sequences to enter and exit this region.
The system may also write the Autoselect command sequence when the device is in Program
Suspend mode. The device allows reading Autoselect codes in the suspended sectors, since
the codes are not stored in the memory array. When the device exits the Autoselect mode,
the device reverts to Program Suspend mode, and is ready for another valid operation. See
“Autoselect Command Sequence” for more information.
After the Program Resume command is written, the device reverts to programming. The sys-
tem can determine the status of the program operation using the DQ7 or DQ6 status bits, just
as in the standard program operation. See “Write Operation Status” for more information.
The system must write the Program Resume command (address bits are “don't care”) to exit
the Program Suspend mode and continue the programming operation. Further writes of the
Program Resume command are ignored. Another Program Suspend command can be written
after the device has resumed programming.
The following is a C source code example of using the program suspend function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Program suspend command */
*( (UINT16 *)base_addr + 0x000 ) = 0x00B0; /* write suspend command */
The following is a C source code example of using the program resume function. Refer to the
Spansion Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com)
for general information on Spansion Flash memory software development guidelines.
/* Example: Program resume command */
*( (UINT16 *)base_addr + 0x000 ) = 0x0030; /* write resume command */
5.5.7 Accelerated Program/Chip Erase
Accelerated single word programming, write buffer programming, sector erase, and chip
erase operations are enabled through the ACC function. This method is faster than the stan-
dard chip program and erase command sequences.
Software Functions and Sample Code
Table 5.28. Program Suspend
(LLD Function = lld_ProgramSuspendCmd)
Cycle Operation Byte Address Word Address Data
1 Write Bank Address Bank Address 00B0h
Table 5.29. Program Resume
(LLD Function = lld_ProgramResumeCmd)
Cycle Operation Byte Address Word Address Data
1 Write Bank Address Bank Address 0030h
November 4, 2004 S29WSxxxN_M0_F0 43
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The accelerated chip program and erase functions must not be used more than 10
times per sector. In addition, accelerated chip program and erase should be performed at
room temperature (25°C ±10°C).
If the system asserts VHH on this input, the device automatically enters the aforementioned
Unlock Bypass mode and uses the higher voltage on the input to reduce the time required for
program and erase operations. The system can then use the Write Buffer Load command se-
quence provided by the Unlock Bypass mode. Note that if a “Write-to-Buffer-Abort Reset” is
required while in Unlock Bypass mode, the full 3-cycle RESET command sequence must be
used to reset the device. Removing VHH from the ACC input, upon completion of the embed-
ded program or erase operation, returns the device to normal operation.
Sectors must be unlocked prior to raising ACC to VHH.
The ACC pin must not be at VHH for operations other than accelerated programming and
accelerated chip erase, or device damage may result.
The ACC pin must not be left floating or unconnected; inconsistent behavior of the device
may result.
tACC locks all sector if set to VIL; tACC should be set to VIH for all other conditions.
5.5.8 Unlock Bypass
The device features an Unlock Bypass mode to facilitate faster word programming. Once the
device enters the Unlock Bypass mode, only two write cycles are required to program data,
instead of the normal four cycles.
This mode dispenses with the initial two unlock cycles required in the standard program com-
mand sequence, resulting in faster total programming time. The “Command Definition
Summary” section shows the requirements for the unlock bypass command sequences.
During the unlock bypass mode, only the Read, Unlock Bypass Program and Unlock Bypass
Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-
cycle unlock bypass reset command sequence. The first cycle must contain the bank address
and the data 90h. The second cycle need only contain the data 00h. The bank then returns
to the read mode.
The following are C source code examples of using the unlock bypass entry, program, and exit
functions. Refer to the Spansion Low Level Driver User’s Guide (available soon on
www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory
software development guidelines.
/* Example: Unlock Bypass Entry Command */
*( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)bank_addr + 0x555 ) = 0x0020; /* write unlock bypass command */
/* At this point, programming only takes two write cycles. */
/* Once you enter Unlock Bypass Mode, do a series of like */
/* operations (programming or sector erase) and then exit */
/* Unlock Bypass Mode before beginning a different type of */
/* operations. */
Software Functions and Sample Code
Table 5.30. Unlock Bypass Entry
(LLD Function = lld_UnlockBypassEntryCmd)
Cycle Description Operation Byte Address Word Address Data
1 Unlock Write Base + AAAh Base + 555h 00AAh
2 Unlock Write Base + 554h Base + 2AAh 0055h
3 Entry Command Write Base + AAAh Base + 555h 0020h
44 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
/* Example: Unlock Bypass Program Command */
/* Do while in Unlock Bypass Entry Mode! */
*( (UINT16 *)bank_addr + 0x555 ) = 0x00A0; /* write program setup command */
*( (UINT16 *)pa ) = data; /* write data to be programmed */
/* Poll until done or error. */
/* If done and more to program, */
/* do above two cycles again. */
/* Example: Unlock Bypass Exit Command */
*( (UINT16 *)base_addr + 0x000 ) = 0x0090;
*( (UINT16 *)base_addr + 0x000 ) = 0x0000;
5.5.9 Write Operation Status
The device provides several bits to determine the status of a program or erase operation. The
following subsections describe the function of DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7.
DQ7: Data# Polling. The Data# Polling bit, DQ7, indicates to the host system whether an
Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in
Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the com-
mand sequence. Note that the Data# Polling is valid only for the last word being programmed
in the write-buffer-page during Write Buffer Programming. Reading Data# Polling status on
any word other than the last word to be programmed in the write-buffer-page will return false
status information.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the
datum programmed to DQ7. This DQ7 status also applies to programming during Erase Sus-
pend. When the Embedded Program algorithm is complete, the device outputs the datum
programmed to DQ7. The system must provide the program address to read valid status in-
formation on DQ7. If a program address falls within a protected sector, Data# polling on DQ7
is active for approximately tPSP
, then that bank returns to the read mode.
During the Embedded Erase Algorithm, Data# polling produces a “0” on DQ7. When the Em-
bedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data#
Polling produces a “1” on DQ7. The system must provide an address within any of the sectors
selected for erasure to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected,
Data# Polling on DQ7 is active for approximately tASP
, then the bank returns to the read
mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the un-
protected sectors, and ignores the selected sectors that are protected. However, if the system
reads DQ7 at an address within a protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change
asynchronously with DQ6-DQ0 while Output Enable (OE#) is asserted low. That is, the device
may change from providing status information to valid data on DQ7. Depending on when the
Table 5.31. Unlock Bypass Program
(LLD Function = lld_UnlockBypassProgramCmd)
Cycle Description Operation Byte Address Word Address Data
1 Program Setup Command Write Base + xxxh Base +xxxh 00A0h
2 Program Command Write Program Address Program Address Program Data
Table 5.32. Unlock Bypass Reset
(LLD Function = lld_UnlockBypassResetCmd)
Cycle Description Operation Byte Address Word Address Data
1 Reset Cycle 1 Write Base + xxxh Base +xxxh 0090h
2 Reset Cycle 2 Write Base + xxxh Base +xxxh 0000h
November 4, 2004 S29WSxxxN_M0_F0 45
Preliminary
system samples the DQ7 output, it may read the status or valid data. Even if the device has
completed the program or erase operation and DQ7 has valid data, the data outputs on DQ6-
DQ0 may be still invalid. Valid data on DQ7-D00 will appear on successive read cycles.
See the following for more information: Ta b l e 5 . 3 5 , Write Operation Status, shows the out-
puts for Data# Polling on DQ7. Figure 5.33, Write Operation Status Flowchart, shows the
Data# Polling algorithm; and Figure 9.16, Data# Polling Timings
(During Embedded Algorithm), shows the Data# Polling timing diagram.
46 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
Figure 5.33. Write Operation Status Flowchart
START
Read 1
DQ7=valid
data?
YES
NO
Read 1
DQ5=1?
YES
NO
Write Buffer
Programming?
YES
NO
Device BUSY,
Re-Poll
Read3
DQ1=1?
YES
NO
Read 2
Read 3
Read 2
Read 3
Read 2
Read 3
Read3
DQ1=1
AND DQ7 ≠
Valid Data?
YES
NO
(Note 4)
Write Buffer
Operation
Failed
DQ6
toggling?
YES
NO
TIMEOUT
(Note 1)
(Note 3)
Programming
Operation?
DQ6
toggling?
YES
NO
YES
NO
DQ2
toggling?
YES
NO
Erase
Operation
Complete
Device in
Erase/Suspend
Mode
Program
Operation
Failed
DEVICE
ERROR
Erase
Operation
Complete
Read3=
valid data?
YES
NO
Notes:
1) DQ6 is toggling if Read2 DQ6 does not equal Read3 DQ6.
2) DQ2 is toggling if Read2 DQ2 does not equal Read3 DQ2.
3) May be due to an attempt to program a 0 to 1. Use the RESET
command to exit operation.
4) Write buffer error if DQ1 of last read =1.
5) Invalid state, use RESET command to exit operation.
6) Valid data is the data that is intended to be programmed or all 1's for
an erase operation.
7) Data polling algorithm valid for all operations except advanced sector
protection.
Device BUSY,
Re-Poll
Device BUSY,
Re-Poll
Device BUSY,
Re-Poll
(Note 1)
(Note 2)
(Note 6)
(Note 5)
November 4, 2004 S29WSxxxN_M0_F0 47
Preliminary
DQ6: Toggle Bit I . Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase
algorithm is in progress or complete, or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address in the same bank, and is valid after the rising
edge of the final WE# pulse in the command sequence (prior to the program or erase opera-
tion), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any ad-
dress cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected,
DQ6 toggles for approximately tASP [all sectors protected toggle time], then returns to read-
ing array data. If not all selected sectors are protected, the Embedded Erase algorithm erases
the unprotected sectors, and ignores the selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing
or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase al-
gorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6
stops toggling. However, the system must also use DQ2 to determine which sectors are eras-
ing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7:
Data# Polling).
If a program address falls within a protected sector, DQ6 toggles for approximately tPAP after
the program command sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Em-
bedded Program Algorithm is complete.
See the following for additional information: Figure 5.33, Write Operation Status Flowchart;
Figure 9.17, Toggle Bit Timings (During Embedded Algorithm), and Tables 5.34 and 5.35.
Toggle Bit I on DQ6 requires either OE# or CE# to be de-asserted and reasserted to show the
change in state.
DQ2: Toggle Bit II . The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a
particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or
whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final
WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses
within those sectors that have been selected for erasure. But DQ2 cannot distinguish whether
the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether
the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are
selected for erasure. Thus, both status bits are required for sector and mode information.
Refer to Ta bl e 5. 34 to compare outputs for DQ2 and DQ6. See the following for additional in-
formation: Figure 5.33, the “DQ6: Toggle Bit I” section, and Figures 9.16–9.19.
48 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
Ta b l e 5 . 3 4 . DQ6 and DQ2 Indications
Reading Toggle Bits DQ6/DQ2. Whenever the system initially begins reading toggle bit sta-
tus, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is
toggling. Typically, the system would note and store the value of the toggle bit after the first
read. After the second read, the system would compare the new value of the toggle bit with
the first. If the toggle bit is not toggling, the device has completed the program or erases
operation. The system can read array data on DQ7–DQ0 on the following read cycle. However,
if after the initial two read cycles, the system determines that the toggle bit is still toggling,
the system also should note whether the value of DQ5 is high (see the section on DQ5). If it
is, the system should then determine again whether the toggle bit is toggling, since the toggle
bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or erases operation. If it is still toggling,
the device did not complete the operation successfully, and the system must write the reset
command to return to reading array data. The remaining scenario is that the system initially
determines that the toggle bit is toggling and DQ5 has not gone high. The system may con-
tinue to monitor the toggle bit and DQ5 through successive read cycles, determining the
status as described in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algorithm when it
returns to determine the status of the operation. Refer to Figure 5.33 for more details.
DQ5: Exceeded Timing Limits. DQ5 indicates whether the program or erase time has ex-
ceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,”
indicating that the program or erase cycle was not successfully completed. The device may
output a “1” on DQ5 if the system tries to program a “1” to a location that was previously
programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this con-
dition, the device halts the operation, and when the timing limit has been exceeded, DQ5
produces a “1.”Under both these conditions, the system must write the reset command to re-
turn to the read mode (or to the erase-suspend-read mode if a bank was previously in the
erase-suspend-program mode).
DQ3: Sector Erase Timeout State Indicator. After writing a sector erase command se-
quence, the system may read DQ3 to determine whether or not erasure has begun. (The
sector erase timer does not apply to the chip erase command.) If additional sectors are se-
lected for erasure, the entire time-out also applies after each additional sector erase
command. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the
time between additional sector erase commands from the system can be assumed to be less
than tSEA, the system need not monitor DQ3. See Sector Erase Command Sequence for more
details.
If device is and the system reads then DQ6 and DQ2
programming, at any address, toggles, does not toggle.
actively erasing,
at an address within a sector
selected for erasure, toggles, also toggles.
at an address within sectors not
selected for erasure, toggles, does not toggle.
erase suspended,
at an address within a sector
selected for erasure, does not toggle, toggles.
at an address within sectors not
selected for erasure, returns array data,
returns array data. The system can
read from any sector not selected for
erasure.
programming in
erase suspend at any address, toggles, is not applicable.
November 4, 2004 S29WSxxxN_M0_F0 49
Preliminary
After the sector erase command is written, the system should read the status of DQ7 (Data#
Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence,
and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further com-
mands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is
“0,” the device will accept additional sector erase commands. To ensure the command has
been accepted, the system software should check the status of DQ3 prior to and following
each sub-sequent sector erase command. If DQ3 is high on the second status check, the last
command might not have been accepted. Ta b l e 5 . 3 5 shows the status of DQ3 relative to the
other status bits.
DQ1: Write to Buffer Abort. DQ1 indicates whether a Write to Buffer operation was aborted.
Under these conditions DQ1 produces a “1”. The system must issue the Write to Buffer Abort
Reset command sequence to return the device to reading array data. See Write Buffer Pro-
gramming Operation for more details.
Ta b l e 5 . 3 5 . Write Operation Status
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the
section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. Data are invalid for addresses in a Program Suspended sector.
4. DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations.
5. The data-bar polling algorithm should be used for Write Buffer Programming operations. Note that DQ7# during Write Buffer Programming
indicates the data-bar for DQ7 data for the LAST LOADED WRITE-BUFFER ADDRESS location.
Status
DQ7
(Note 2) DQ6
DQ5
(Note 1) DQ3
DQ2
(Note 2)
DQ1
(Note 4)
Standard
Mode
Embedded Program Algorithm
DQ7# Toggle 0N/A No toggle 0
Embedded Erase Algorithm 0Toggle 0 1 Toggle N/A
Program
Suspend
Mode
(Note 3)
Reading within Program Suspended Sector
INVALID
(Not
Allowed)
INVALID
(Not
Allowed)
INVALID
(Not
Allowed)
INVALID
(Not
Allowed)
INVALID
(Not
Allowed)
INVALID
(Not
Allowed)
Reading within Non-Program Suspended
Sector Data Data Data Data Data Data
Erase
Suspend
Mode
Erase-Suspend-
Read
Erase
Suspended Sector 1No toggle 0N/A Toggle N/A
Non-Erase Suspended
Sector Data Data Data Data Data Data
Erase-Suspend-Program DQ7# Toggle 0N/A N/A N/A
Write to
Buffer
(Note 5)
BUSY State DQ7# Toggle 0N/A N/A 0
Exceeded Timing Limits DQ7# Toggle 1N/A N/A 0
ABORT State DQ7# Toggle 0N/A N/A 1
50 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
5.6 Simultaneous Read/Write
The simultaneous read/write feature allows the host system to read data from one bank of
memory while programming or erasing another bank of memory. An erase operation may also
be suspended to read from or program another location within the same bank (except the
sector being erased). Figure 9.23, Back-to-Back Read/Write Cycle Timings, shows how read
and write cycles may be initiated for simultaneous operation with zero latency. Refer to the
DC Characteristics (CMOS Compatible) table for read-while-program and read-while-erase
current specification.
5.7 Writing Commands/Command Sequences
When the device is configured for Asynchronous read, only Asynchronous write operations are
allowed, and CLK is ignored. When in the Synchronous read mode configuration, the device
is able to perform both Asynchronous and Synchronous write operations. CLK and AVD# in-
duced address latches are supported in the Synchronous programming mode. During a
synchronous write operation, to write a command or command sequence (which includes pro-
gramming data to the device and erasing sectors of memory), the system must drive AVD#
and CE# to VIL, and OE# to VIH when providing an address to the device, and drive WE# and
CE# to VIL, and OE# to VIH when writing commands or data. During an asynchronous write
operation, the system must drive CE# and WE# to VIL and OE# to VIH when providing an
address, command, and data. Addresses are latched on the last falling edge of WE# or CE#,
while data is latched on the 1st rising edge of WE# or CE#. An erase operation can erase one
sector, multiple sectors, or the entire device. Tables 4.1–4.3 indicate the address space that
each sector occupies. The device address space is divided into sixteen banks: Banks 1
through 14 contain only 64 Kword sectors, while Banks 0 and 15 contain both 16 Kword boot
sectors in addition to 64 Kword sectors. A “bank address” is the set of address bits required
to uniquely select a bank. Similarly, a “sector address” is the address bits required to uniquely
select a sector. ICC2 in “DC Characteristics” represents the active current specification for the
write mode. “AC Characteristics-Synchronous” and “AC Characteristics-Asynchronous” con-
tain timing specification tables and timing diagrams for write operations.
5.8 Handshaking
The handshaking feature allows the host system to detect when data is ready to be read by
simply monitoring the RDY (Ready) pin, which is a dedicated output and controlled by CE#.
When the device is configured to operate in synchronous mode, and OE# is low (active), the
initial word of burst data becomes available after either the falling or rising edge of the RDY
pin (depending on the setting for bit 10 in the Configuration Register). It is recommended
that the host system set CR13–CR11 in the Configuration Register to the appropriate number
of wait states to ensure optimal burst mode operation (see Table 5.15, Configuration
Register).
Bit 8 in the Configuration Register allows the host to specify whether RDY is active at the same
time that data is ready, or one cycle before data is ready.
November 4, 2004 S29WSxxxN_M0_F0 51
Preliminary
5.9 Hardware Reset
The RESET# input provides a hardware method of resetting the device to reading array data.
When RESET# is driven low for at least a period of tRP
, the device immediately terminates any
operation in progress, tristates all outputs, resets the configuration register, and ignores all
read/write commands for the duration of the RESET# pulse. The device also resets the inter-
nal state machine to reading array data.
To ensure data integrity the operation that was interrupted should be reinitiated once the de-
vice is ready to accept another command sequence.
When RESET# is held at VSS, the device draws CMOS standby current (ICC4). If RESET# is
held at VIL, but not at VSS, the standby current will be greater.
RESET# may be tied to the system reset circuitry which enables the system to read the boot-
up firmware from the Flash memory upon a system reset.
See Figures 9.5 and 9.12 for timing diagrams.
5.10 Software Reset
Software reset is part of the command set (see Ta bl e 1 0. 1 ) that also returns the device to
array read mode and must be used for the following conditions:
1. to exit Autoselect mode
2. when DQ5 goes high during write status operation that indicates program or erase cycle
was not successfully completed
3. exit sector lock/unlock operation.
4. to return to erase-suspend-read mode if the device was previously in Erase Suspend
mode.
5. after any aborted operations
Note: Base = Base Address.
The following is a C source code example of using the reset function. Refer to the Spansion
Low Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for general
information on Spansion Flash memory software development guidelines.
/* Example: Reset (software reset of Flash state machine) */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0;
The following are additional points to consider when using the reset command:
This command resets the banks to the read and address bits are ignored.
Reset commands are ignored once erasure has begun until the operation is complete.
Once programming begins, the device ignores reset commands until the operation is
complete
The reset command may be written between the cycles in a program command sequence
before programming begins (prior to the third cycle). This resets the bank to which the
system was writing to the read mode.
Software Functions and Sample Code
Table 5.36. Reset
(LLD Function = lld_ResetCmd)
Cycle Operation Byte Address Word Address Data
Reset Command Write Base + xxxh Base + xxxh 00F0h
52 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
If the program command sequence is written to a bank that is in the Erase Suspend
mode, writing the reset command returns that bank to the erase-suspend-read mode.
The reset command may be also written during an Autoselect command sequence.
If a bank has entered the Autoselect mode while in the Erase Suspend mode, writing the
reset command returns that bank to the erase-suspend-read mode.
If DQ1 goes high during a Write Buffer Programming operation, the system must write
the "Write to Buffer Abort Reset" command sequence to RESET the device to reading
array data. The standard RESET command will not work during this condition.
To exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset
command sequence [see command table for details].
November 4, 2004 S29WSxxxN_M0_F0 53
Preliminary
6 Advanced Sector Protection/Unprotection
The Advanced Sector Protection/Unprotection feature disables or enables programming or
erase operations in any or all sectors and can be implemented through software and/or hard-
ware methods, which are independent of each other. This section describes the various
methods of protecting data stored in the memory array. An overview of these methods in
shown in Figure 6.1.
Figure 6.1. Advanced Sector Protection/Unprotection
Hardware Methods Software Methods
ACC = V
IL
(
All sectors locked)
WP# = V
IL
(All boot
sectors locked)
Password Method
(DQ2)
Persistent Method
(DQ1)
Lock Register
(One Time Programmable)
PPB Lock Bit
1,2,3
64-bit Password
(One Time Protect)
1 = PPBs Unlocked
0 = PPBs Locked
Memory Array
Sector 0
Sector 1
Sector 2
Sector N-2
Sector N-1
Sector N
3
PPB 0
PPB 1
PPB 2
PPB N-2
PPB N-1
PPB N
Persistent
Protection Bit
(PPB)
4,5
DYB 0
DYB 1
DYB 2
DYB N-2
DYB N-1
DYB N
Dynamic
Protection Bit
(PPB)
6,7,8
6. 0 = Sector Protected,
1 = Sector Unprotected.
7. Protect effective only if PPB Lock Bit
is unlocked and corresponding PPB
is “1” (unprotected).
8. Volatile Bits: defaults to user choice
upon power-up (see ordering
options).
4. 0 = Sector Protected,
1 = Sector Unprotected.
5. PPBs programmed individually,
but cleared collectively
1. Bit is volatile, and defaults to “1” on
reset.
2. Programming to “0” locks all PPBs to
their current state.
3. Once programmed to “0”, requires
hardware reset to unlock.
3. N = Highest Address Sector.
54 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
6.1 Lock Register
As shipped from the factory, all devices default to the persistent mode when power is applied,
and all sectors are unprotected, unless otherwise chosen through the DYB ordering option.
The device programmer or host system must then choose which sector protection method to
use. Programming (setting to “0”) any one of the following two one-time programmable, non-
volatile bits locks the part permanently in that mode:
Lock Register Persistent Protection Mode Lock Bit (DQ1)
Lock Register Password Protection Mode Lock Bit (DQ2)
Table 6.1. Lock Register
For programming lock register bits refer to Tab le 10. 2 .
Notes
1. If the password mode is chosen, the password must be programmed before setting the cor-
responding lock register bit.
2. After the Lock Register Bits Command Set Entry command sequence is written, reads and
writes for Bank 0 are disabled, while reads from other banks are allowed until exiting this
mode.
3. If both lock bits are selected to be programmed (to zeros) at the same time, the operation
will abort.
4. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently
disabled, and no changes to the protection scheme are allowed. Similarly, if the Persistent
Mode Lock Bit is programmed, the Password Mode is permanently disabled.
After selecting a sector protection method, each sector can operate in any of the following
three states:
1. Constantly locked. The selected sectors are protected and can not be reprogrammed
unless PPB lock bit is cleared via a password, hardware reset, or power cycle.
2. Dynamically locked. The selected sectors are protected and can be altered via software
commands.
3. Unlocked. The sectors are unprotected and can be erased and/or programmed.
These states are controlled by the bit types described in Sections 6.2–6.6.
6.2 Persistent Protection Bits
The Persistent Protection Bits are unique and nonvolatile for each sector and have the same
endurances as the Flash memory. Preprogramming and verification prior to erasure are han-
dled by the device, and therefore do not require system monitoring.
Notes
1. Each PPB is individually programmed and all are erased in parallel.
2. Entry command disables reads and writes for the bank selected.
3. Reads within that bank will return the PPB status for that sector.
4. Reads from other banks are allowed while writes are not allowed.
Device DQ15-05 DQ4 DQ3 DQ2 DQ1 DQ0
S29WS256N 1 1 1
Password
Protection
Mode Lock Bit
Persistent
Protection
Mode Lock Bit
Customer
SecSi Sector
Protection Bit
S29WS128N/
S29WS064N Undefined
DYB Lock Boot Bit
0 = sectors
power up
protected
1 = sectors
power up
unprotected
PPB One-Time
Programmable Bit
0 = All PPB erase
command disabled
1 = All PPB Erase
command enabled
Password
Protection
Mode Lock Bit
Persistent
Protection
Mode Lock Bit
SecSi Sector
Protection Bit
November 4, 2004 S29WSxxxN_M0_F0 55
Preliminary
5. All Reads must be performed using the Asynchronous mode.
6. The specific sector address (A23-A14 WS256N, A22-A14 WS128N, A21-A14 WS064N)
are written at the same time as the program command.
7. If the PPB Lock Bit is set, the PPB Program or erase command will not execute and will
time-out without programming or erasing the PPB.
8. There are no means for individually erasing a specific PPB and no specific sector address
is required for this operation.
9. Exit command must be issued after the execution which resets the device to read mode
and re-enables reads and writes for Bank 0
10. The programming state of the PPB for a given sector can be verified by writing a PPB
Status Read Command to the device as described by the flow chart below.
6.3 Dynamic Protection Bits
Dynamic Protection Bits are volatile and unique for each sector and can be individually mod-
ified. DYBs only control the protection scheme for unprotected sectors that have their PPBs
cleared (erased to “1”). By issuing the DYB Set or Clear command sequences, the DYBs will
be set (programmed to “0”) or cleared (erased to “1”), thus placing each sector in the pro-
tected or unprotected state respectively. This feature allows software to easily protect sectors
against inadvertent changes yet does not prevent the easy removal of protection when
changes are needed.
Notes
1. The DYBs can be set (programmed to “0”) or cleared (erased to “1”) as often as needed.
When the parts are first shipped, the PPBs are cleared (erased to “1”) and upon power up or
reset, the DYBs can be set or cleared depending upon the ordering option chosen.
2. If the option to clear the DYBs after power up is chosen, (erased to “1”), then the sectors
may be modified depending upon the PPB state of that sector (see Tab l e 6. 2).
3. The sectors would be in the protected state If the option to set the DYBs after power up
is chosen (programmed to “0”).
4. It is possible to have sectors that are persistently locked with sectors that are left in the
dynamic state.
5. The DYB Set or Clear commands for the dynamic sectors signify protected or unpro-
tectedstate of the sectors respectively. However, if there is a need to change the status
of the persistently locked sectors, a few more steps are required. First, the PPB Lock Bit
must be cleared by either putting the device through a power-cycle, or hardware reset.
The PPBs can then be changed to reflect the desired settings. Setting the PPB Lock Bit
once again will lock the PPBs, and the device operates normally again.
6. To achieve the best protection, it is recommended to execute the PPB Lock Bit Set com-
mand early in the boot code and protect the boot code by holding WP# = VIL. Note that
the PPB and DYB bits have the same function when ACC = VHH as they do when ACC
=VIH.
6.4 Persistent Protection Bit Lock Bit
The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set (pro-
grammed to “0”), this bit locks all PPB and when cleared (programmed to “1”), unlocks each
sector. There is only one PPB Lock Bit per device.
Notes
1. No software command sequence unlocks this bit unless the device is in the password
protection mode; only a hardware reset or a power-up clears this bit.
2. The PPB Lock Bit must be set (programmed to “0”) only after all PPBs are configured to
the desired settings.
56 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
6.5 Password Protection Method
The Password Protection Method allows an even higher level of security than the Persistent
Sector Protection Mode by requiring a 64 bit password for unlocking the device PPB Lock Bit.
In addition to this password requirement, after power up and reset, the PPB Lock Bit is set
“0” to maintain the password mode of operation. Successful execution of the Password Unlock
command by entering the entire password clears the PPB Lock Bit, allowing for sector PPBs
modifications.
Notes
1. There is no special addressing order required for programming the password. Once the
Password is written and verified, the Password Mode Locking Bit must be set in order to
prevent access.
2. The Password Program Command is only capable of programming “0”s. Programming a
“1” after a cell is programmed as a “0” results in a time-out with the cell as a “0”.
3. The password is all “1”s when shipped from the factory.
4. All 64-bit password combinations are valid as a password.
5. There is no means to verify what the password is after it is set.
6. The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the
data bus and further password programming.
7. The Password Mode Lock Bit is not erasable.
8. The lower two address bits (A1–A0) are valid during the Password Read, Password Pro-
gram, and Password Unlock.
9. The exact password must be entered in order for the unlocking function to occur.
10. The Password Unlock command cannot be issued any faster than 1 µs at a time to pre-
vent a hacker from running through all the 64-bit combinations in an attempt to
correctly match a password.
11. Approximately 1 µs is required for unlocking the device after the valid 64-bit password
is given to the device.
12. Password verification is only allowed during the password programming operation.
13. All further commands to the password region are disabled and all operations are
ignored.
14. If the password is lost after setting the Password Mode Lock Bit, there is no way to clear
the PPB Lock Bit.
15. Entry command sequence must be issued prior to any of any operation and it disables
reads and writes for Bank 0. Reads and writes for other banks excluding Bank 0 are
allowed.
16. If the user attempts to program or erase a protected sector, the device ignores the com-
mand and returns to read mode.
17. A program or erase command to a protected sector enables status polling and returns
to read mode without having modified the contents of the protected sector.
18. The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by
writing individual status read commands DYB Status, PPB Status, and PPB Lock Status
to the device.
November 4, 2004 S29WSxxxN_M0_F0 57
Preliminary
Figure 6.2. Lock Register Program Algorithm
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Write
Enter Lock Register Command:
Address 555h, Data 40h
Program Lock Register Data
Address XXXh, Data A0h
Address 77h*, Data PD
Unlock Cycle 1
Unlock Cycle 2
XXXh = Address don’t care
* Not on future devices
Program Data (PD): See text for Lock Register
definitions
Caution: Lock data may only be progammed once.
Wait 4 µs
PASS. Write Lock Register
Exit Command:
Address XXXh, Data 90h
Address XXXh, Data 00h
Device returns to reading array.
Perform Polling Algorithm
(see Write Operation Status
flowchart)
Yes
Yes
No
No
Done?
DQ5 = 1? Error condition (Exceeded Timing Limits)
FAIL. Write rest command
to return to reading array.
58 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
6.6 Advanced Sector Protection Software Examples
Ta b le 6. 2 contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the
status of the sector. In summary, if the PPB Lock Bit is locked (set to “0”), no changes to the
PPBs are allowed. The PPB Lock Bit can only be unlocked (reset to “1”) through a hardware
reset or power cycle. See also Figure 6.1 for an overview of the Advanced Sector Protection
feature.
6.7 Hardware Data Protection Methods
The device offers two main types of data protection at the sector level via hardware control:
When WP# is at VIL, the four outermost sectors are locked (device specific).
When ACC is at VIL, all sectors are locked.
There are additional methods by which intended or accidental erasure of any sectors can be
prevented via hardware means. The following subsections describes these methods:
6.7.1. WP# Method
The Write Protect feature provides a hardware method of protecting the four outermost sec-
tors. This function is provided by the WP# pin and overrides the previously discussed Sector
Protection/Unprotection method.
If the system asserts VIL on the WP# pin, the device disables program and erase functions in
the “outermost” boot sectors. The outermost boot sectors are the sectors containing both the
lower and upper set of sectors in a dual-boot-configured device.
If the system asserts VIH on the WP# pin, the device reverts to whether the boot sectors were
last set to be protected or unprotected. That is, sector protection or unprotection for these
sectors depends on whether they were last protected or unprotected.
Note that the WP# pin must not be left floating or unconnected as inconsistent behavior of
the device may result.
The WP# pin must be held stable during a command sequence execution
6.7.2 ACC Method
This method is similar to above, except it protects all sectors. Once ACC input is set to VIL,
all program and erase functions are disabled and hence all sectors are protected.
Table 6.2. Sector Protection Schemes
Unique Device PPB Lock Bit
0 = locked
1 = unlocked
Sector PPB
0 = protected
1 = unprotected
Sector DYB
0 = protected
1 = unprotected
Sector Protection Status
Any Sector 0 0 x Protected through PPB
Any Sector 0 0 x Protected through PPB
Any Sector 0 1 1 Unprotected
Any Sector 0 1 0 Protected through DYB
Any Sector 1 0 x Protected through PPB
Any Sector 1 0 x Protected through PPB
Any Sector 1 1 0 Protected through DYB
Any Sector 1 1 1 Unprotected
November 4, 2004 S29WSxxxN_M0_F0 59
Preliminary
6.7.3 Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data
during VCC power-up and power-down.
The command register and all internal program/erase circuits are disabled, and the device
resets to reading array data. Subsequent writes are ignored until VCC is greater than VLKO.
The system must provide the proper signals to the control inputs to prevent unintentional
writes when VCC is greater than VLKO.
6.7.4 Write Pulse “Glitch Protection”
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
6.7.5 Power-Up Write Inhibit
If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept
commands on the rising edge of WE#. The internal state machine is automatically reset to
the read mode on power-up.
60 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
7 Power Conservation Modes
7.1 Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby
mode. In this mode, current consumption is greatly reduced, and the outputs are placed in
the high impedance state, independent of the OE# input. The device enters the CMOS
standby mode when the CE# and RESET# inputs are both held at VCC ± 0.2 V. The device
requires standard access time (tCE) for read access, before it is ready to read data. If the de-
vice is deselected during erasure or programming, the device draws active current until the
operation is completed. ICC3 in “DC Characteristics” represents the standby current
specification
7.2 Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption while in asynchronous
mode. the device automatically enables this mode when addresses remain stable for tACC +
20 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals.
Standard address access timings provide new data when addresses are changed. While in
sleep mode, output data is latched and always available to the system. While in synchronous
mode, the automatic sleep mode is disabled. Note that a new burst operation is required to
provide new data. ICC6 in “DC Characteristics” represents the automatic sleep mode current
specification.
7.3 Hardware RESET# Input Operation
The RESET# input provides a hardware method of resetting the device to reading array data.
When RESET# is driven low for at least a period of tRP
, the device immediately terminates any
operation in progress, tristates all outputs, resets the configuration register, and ignores all
read/write commands for the duration of the RESET# pulse. The device also resets the inter-
nal state machine to reading array data. The operation that was interrupted should be
reinitiated once the device is ready to accept another command sequence to ensure data
integrity.
When RESET# is held at VSS ± 0.2 V, the device draws CMOS standby current (ICC4). If RE-
SET# is held at VIL but not within VSS ± 0.2 V, the standby current will be greater.
RESET# may be tied to the system reset circuitry and thus, a system reset would also reset
the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
7.4 Output Disable (OE#)
When the OE# input is at VIH, output from the device is disabled. The outputs are placed in
the high impedance state.
November 4, 2004 S29WSxxxN_M0_F0 61
Preliminary
8 SecSiTM (Secured Silicon) Sector Flash Memory Region
The SecSi (Secured Silicon) Sector provides an extra Flash memory region that enables per-
manent part identification through an Electronic Serial Number (ESN). The SecSi Sector is
256 words in length that consists of 128 words for factory data and 128 words for customer-
secured areas. All SecSi reads outside of the 256-word address range will return invalid data.
The Factory Indicator Bit, DQ7, (at Autoselect address 03h) is used to indicate whether or not
the Factory SecSi Sector is locked when shipped from the factory. The Customer Indicator Bit
(DQ6) is used to indicate whether or not the Customer SecSi Sector is locked when shipped
from the factory.
Please note the following general conditions:
While SecSi Sector access is enabled, simultaneous operations are allowed except for
Bank 0.
On power-up, or following a hardware reset, the device reverts to sending commands to
the normal address space.
Reads can be performed in the Asynchronous or Synchronous mode.
Burst mode reads within SecSi Sector will wrap from address FFh back to address 00h.
Reads outside of sector 0 will return memory array data.
Continuous burst read past the maximum address is undefined.
Sector 0 is remapped from memory array to SecSi Sector array.
Once the SecSi Sector Entry Command is issued, the SecSi Sector Exit command must
be issued to exit SecSi Sector Mode.
The SecSi Sector is not accessible when the device is executing an Embedded Program
or Embedded Erase algorithm.
Ta b l e 8 . 1 . S e c S i TM Sector Addresses
8.1 Factory SecSiTM Sector
The Factory SecSi Sector is always protected when shipped from the factory and has the Fac-
tory Indicator Bit (DQ7) permanently set to a “1”. This prevents cloning of a factory locked
part and ensures the security of the ESN and customer code once the product is shipped to
the field.
These devices are available pre programmed with one of the following:
A random, 8 Word secure ESN only within the Factory SecSi Sector
Customer code within the Customer SecSi Sector through the SpansionTM programming
service.
Both a random, secure ESN and customer code through the Spansion programming ser-
vice.
Customers may opt to have their code programmed through the Spansion programming ser-
vices. Spansion programs the customer's code, with or without the random ESN. The devices
are then shipped from the Spansion factory with the Factory SecSi Sector and Customer SecSi
Sector permanently locked. Contact your local representative for details on using Spansion
programming services.
Sector Sector Size Address Range
Customer 128 words 000080h-0000FFh
Factory 128 words 000000h-00007Fh
62 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
8.2 Customer SecSiTM Sector
The Customer SecSi Sector is typically shipped unprotected (DQ6 set to “0”), allowing cus-
tomers to utilize that sector in any manner they choose. If the security feature is not required,
the Customer SecSi Sector can be treated as an additional Flash memory space.
Please note the following:
Once the Customer SecSi Sector area is protected, the Customer Indicator Bit will be per-
manently set to “1.”
The Customer SecSi Sector can be read any number of times, but can be programmed
and locked only once. The Customer SecSi Sector lock must be used with caution as once
locked, there is no procedure available for unlocking the Customer SecSi Sector area and
none of the bits in the Customer SecSi Sector memory space can be modified in any way.
The accelerated programming (ACC) and unlock bypass functions are not available when
programming the Customer SecSi Sector, but reading in Banks 1 through 15 is available.
Once the Customer SecSi Sector is locked and verified, the system must write the Exit
SecSi Sector Region command sequence which return the device to the memory array at
sector 0.
8.3 SecSiTM Sector Entry and SecSi Sector Exit
Command Sequences
The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector
command sequence. The device continues to access the SecSi Sector region until the system
issues the four-cycle Exit SecSi Sector command sequence.
See Command Definition Table [SecSiTM Sector Command Table, Appendix
Table 10.1 for address and data requirements for both command sequences.
The SecSi Sector Entry Command allows the following commands to be executed
Read customer and factory SecSi areas
Program the customer SecSi Sector
After the system has written the Enter SecSi Sector command sequence, it may read the
SecSi Sector by using the addresses normally occupied by sector SA0 within the memory ar-
ray. This mode of operation continues until the system issues the Exit SecSi Sector command
sequence, or until power is removed from the device.
The following are C functions and source code examples of using the SecSi Sector Entry, Pro-
gram, and exit commands. Refer to the Spansion Low Level Driver User’s Guide (available
soon on www.amd.com and www.fujitsu.com) for general information on Spansion Flash
memory software development guidelines.
Note: Base = Base Address.
/* Example: SecSi Sector Entry Command */
Software Functions and Sample Code
Table 8.2. SecSi Sector Entry
(LLD Function = lld_SecSiSectorEntryCmd)
Cycle Operation Byte Address Word Address Data
Unlock Cycle 1 Write Base + AAAh Base + 555h 00AAh
Unlock Cycle 2 Write Base + 554h Base + 2AAh 0055h
Entry Cycle Write Base + AAAh Base + 555h 0088h
November 4, 2004 S29WSxxxN_M0_F0 63
Preliminary
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)base_addr + 0x555 ) = 0x0088; /* write Secsi Sector Entry Cmd */
Note: Base = Base Address.
/* Once in the SecSi Sector mode, you program */
/* words using the programming algorithm. */
Note: Base = Base Address.
/* Example: SecSi Sector Exit Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
*( (UINT16 *)base_addr + 0x555 ) = 0x0090; /* write SecSi Sector Exit cycle 3 */
*( (UINT16 *)base_addr + 0x000 ) = 0x0000; /* write SecSi Sector Exit cycle 4 */
Table 8.3. SecSi Sector Program
(LLD Function = lld_ProgramCmd)
Cycle Operation Byte Address Word Address Data
Unlock Cycle 1 Write Base + AAAh Base + 555h 00AAh
Unlock Cycle 2 Write Base + 554h Base + 2AAh 0055h
Program Setup Write Base + AAAh Base + 555h 00A0h
Program Write Word Address Word Address Data Word
Table 8.4. SecSi Sector Entry
(LLD Function = lld_SecSiSectorExitCmd)
Cycle Operation Byte Address Word Address Data
Unlock Cycle 1 Write Base + AAAh Base + 555h 00AAh
Unlock Cycle 2 Write Base + 554h Base + 2AAh 0055h
Exit Cycle Write Base + AAAh Base + 555h 0090h
64 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
9 Electrical Specifications
9.1 Absolute Maximum Ratings
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +150°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +125°C
Voltage with Respect to Ground:
All Inputs and I/Os except
as noted below (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VIO + 0.5 V
VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +2.5 V
VIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +2.5 V
ACC (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +9.5 V
Output Short Circuit Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Notes:
1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or
I/Os may undershoot VSS to –2.0 V for periods of up to 20 ns. See Figure 9.1.
Maximum DC voltage on input or I/Os is VCC + 0.5 V. During voltage transitions
outputs may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 9.2.
2. Minimum DC input voltage on pin ACC is -0.5V. During voltage transitions, ACC may
overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 9.1. Maximum DC
voltage on pin ACC is +9.5 V, which may overshoot to 10.5 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short
circuit should not be greater than one second.
4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
data sheet is not implied. Exposure of the device to absolute maximum rating conditions
for extended periods may affect device reliability.
Figure 9.1. Maximum Negative Overshoot
Waveform
Figure 9.2. Maximum Positive Overshoot
Waveform
20 ns
20 ns
+0.8 V
–0.5 V
20 ns
–2.0 V
20 ns
20 ns
V
CC
+2.0 V
V
CC
+0.5 V
20 ns
1.0 V
November 4, 2004 S29WSxxxN_M0_F0 65
Preliminary
9.2 Operating Ranges
Wireless (W) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Supply Voltages
VCC Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.70 V to +1.95 V
VIO Supply Voltages: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.70 V to +1.95 V
(Contact local sales office for VIO = 1.35 to +1.70 V.)
Notes: Operating ranges define those limits between which the functionality of the device
is guaranteed.
9.3 Test Conditions
Table 9.1. Test Specifications
Test Condition All Speed Options Unit
Output Load Capacitance, C
L
(including jig capacitance) 30 pF
Input Rise and Fall Times 3.0 @ 54, 66 MHz
2.5 @ 80 MHz ns
Input Pulse Levels 0.0–V
IO
V
Input timing measurement
reference levels V
IO
/2 V
Output timing measurement
reference levels V
IO
/2 V
C
L
Device
Under
Test
Figure 9.3. Test Setup
66 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
9.4 Key to Switching Waveforms
9.5 Switching Waveforms
9.6 VCC Power-up
Notes:
1. VCC >= VIO - 100mV and VCC ramp rate is > 1V / 100µs
2. VCC ramp rate <1V / 100µs, a Hardware Reset will be required.
Figure 9.5. VCC Power-up Diagram
Parameter Description Test Setup Speed Unit
t
VCS
V
CC
Setup Time Min 1 ms
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
VIO
0.0 V
OutputMeasurement LevelInput VIO/2 VIO/2All Inputs and Outputs
Figure 9.4. Input Waveforms and Measurement Levels
VCC
VIO
RESET#
tVCS
November 4, 2004 S29WSxxxN_M0_F0 67
Preliminary
9.7 DC Characteristics (CMOS Compatible)
Notes:
1. Maximum ICC specifications are tested with VCC = VCCmax.
2. VCC= VIO.
3. CE# must be set high when measuring the RDY pin.
4. The ICC current listed is typically less than 3 mA/MHz, with OE# at VIH.
5. ICC active while Embedded Erase or Embedded Program is in progress.
6. Device enters automatic sleep mode when addresses are stable for tACC + 20 ns.
Typical sleep mode current is equal to ICC3.
7. VIH = VCC ± 0.2 V and VIL > –0.1 V.
8. Total current during accelerated programming is the sum of VACC and VCC
currents.
9. VACC = VHH on ACC input.
Parameter Description (Notes) Test Conditions (Notes 1, 2, 9) Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC, VCC = VCCmax ±1 µA
ILO Output Leakage Current (3) VOUT = VSS to VCC, VCC = VCCmax ±1 µA
ICCB VCC Active burst Read Current
CE# = VIL, OE# = VIH, WE#
= VIH, burst length = 8
54 MHz 27 54 mA
66 MHz 28 60 mA
80 MHz 30 66 mA
CE# = VIL, OE# = VIH, WE#
= VIH, burst length = 16
54 MHz 28 48 mA
66 MHz 30 54 mA
80 MHz 32 60 mA
CE# = VIL, OE# = VIH, WE#
= VIH, burst length = 32
54 MHz 29 42 mA
66 MHz 32 48 mA
80 MHz 34 54 mA
CE# = VIL, OE# = VIH, WE#
= VIH, burst length =
Continuous
54 MHz 32 36 mA
66 MHz 35 42 mA
80 MHz 38 48 mA
IIO1 VIO Non-active Output OE# = VIH 20 30 µA
ICC1
VCC Active Asynchronous
Read Current (4)
CE# = VIL, OE# = VIH, WE#
= VIH
10 MHz 27 36 mA
5 MHz 13 18 mA
1 MHz 3 4 mA
ICC2 VCC Active Write Current (5) CE# = VIL, OE# = VIH, ACC
= VIH
VACC 15µA
VCC 19 52.5 mA
ICC3 VCC Standby Current (6, 7) CE# = RESET# =
VCC ± 0.2 V
VACC 15µA
VCC 20 40 µA
ICC4 VCC Reset Current (7) RESET# = VIL, CLK = VIL 70 150 µA
ICC5
VCC Active Current
(Read While Write) (7) CE# = VIL, OE# = VIH, ACC = VIH 50 60 mA
ICC6 VCC Sleep Current (7) CE# = VIL, OE# = VIH 240µA
IACC Accelerated Program Current (8) CE# = VIL, OE# = VIH,
VACC = 9.5 V
VACC 620mA
VCC 14 20 mA
VIL Input Low Voltage VIO = 1.8 V –0.5 0.4 V
VIH Input High Voltage VIO = 1.8 V VIO – 0.4 VIO + 0.4 V
VOL Output Low Voltage IOL = 100 µA, VCC = VCC min = VIO 0.1 V
VOH Output High Voltage IOH = –100 µA, VCC = VCC min = VIO VIO – 0.1 V
VHH Voltage for Accelerated Program 8.5 9.5 V
VLKO Low VCC Lock-out Voltage 1.0 1.4 V
68 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
9.8 AC Characteristics
9.8.1. CLK Characterization
Figure 9.6. CLK Characterization
Parameter Description 54 MHz 66 MHz 80 MHz Unit
f
CLK
CLK Frequency Max 54 66 80 MHz
t
CLK
CLK Period Min 18.5 15.1 12.5 ns
t
CH
CLK High Time
Min 7.4 6.1 5.0 ns
t
CL
CLK Low Time
t
CR
CLK Rise Time
Max 3 3 2.5 ns
t
CF
CLK Fall Time
tCLK
tCL
tCH
tCR tCF
CLK
November 4, 2004 S29WSxxxN_M0_F0 69
Preliminary
9.8.2 Synchronous/Burst Read
Notes:
1. Addresses are latched on the first rising edge of CLK.
2. Not 100% tested.
Parameter
Description 54 MHz 66 MHz 80 MHz UnitJEDEC Standard
t
IACC
Latency Max 69 ns
t
BACC
Burst Access Time Valid Clock to Output Delay Max 13.5 11.2 9 ns
t
ACS
Address Setup Time to CLK (Note 1) Min 5 4 ns
t
ACH
Address Hold Time from CLK (Note 1) Min 7 6 ns
t
BDH
Data Hold Time from Next Clock Cycle Min 4 3 ns
t
CR
Chip Enable to RDY Valid Max 13.5 11.2 9 ns
t
OE
Output Enable to Output Valid Max 13.5 11.2 ns
t
CEZ
Chip Enable to High Z (Note 2) Max 10 ns
t
OEZ
Output Enable to High Z (Note 2) Max 10 ns
t
CES
CE# Setup Time to CLK Min 4 ns
t
RDYS
RDY Setup Time to CLK Min 5 4 3.5 ns
t
RACC
Ready Access Time from CLK Max 13.5 11.2 9 ns
t
CAS
CE# Setup Time to AVD# Min 0 ns
t
AVC
AVD# Low to CLK Min 4 ns
t
AVD
AVD# Pulse Min 8 ns
t
AOE
AVD Low to OE# Low Max 38.4 ns
70 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
9.8.3 Timing Diagrams
Notes:
1. Figure shows total number of wait states set to five cycles. The total number of
wait states can be programmed from two cycles to seven cycles.
2. If any burst address occurs at “address + 1”, “address + 2”, or “address + 3”,
additional clock delay cycles are inserted, and are indicated by RDY.
3. The device is in synchronous mode.
Figure 9.7. CLK Synchronous Burst Mode Read
Da Da + 1 Da + n
OE#
Data (n)
Addresses
Aa
AVD#
RDY (n)
CLK
CE#
t
CES
t
ACS
t
AVC
t
AVD
t
ACH
t
OE
t
RACC
t
OEZ
t
CEZ
t
IACC
t
AOE
t
BDH
5 cycles for initial access shown.
18.5 ns typ. (54 MHz)
Hi-Z
Hi-Z Hi-Z
12 3456 7
t
RDYS
t
BACC
Da + 3
Da + 2
Da Da + 1 Da + n
Data (n + 1)
RDY (n + 1)
Hi-Z
Hi-Z Hi-Z
Da + 2
Da + 2
Da Da + 1 Da + n
Data (n + 2)
RDY (n + 2)
Hi-Z
Hi-Z Hi-Z
Da + 1
Da + 1
Da Da Da + n
Data (n + 3)
RDY (n + 3)
Hi-Z
Hi-Z Hi-Z
Da
Da
t
CR
November 4, 2004 S29WSxxxN_M0_F0 71
Preliminary
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven
cycles.
2. If any burst address occurs at “address + 1”, “address + 2”, or “address + 3”, additional clock delay cycles are inserted, and are indicated
by RDY.
3. The device is in synchronous mode with wrap around.
4. D8–DF in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure
is the 4th address in range (0-F).
Figure 9.8. 8-word Linear Burst with Wrap Around
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven
cycles. Clock is set for active rising edge.
2. If any burst address occurs at “address + 1”, “address + 2”, or “address + 3”, additional clock delay cycles are inserted, and are indicated
by RDY.
3. The device is in asynchronous mode with out wrap around.
4. DC–D13 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure
is the 1st address in range (c-13).
Figure 9.9. 8-word Linear Burst without Wrap Around
DC DD
OE#
Data
Addresses
Ac
AVD#
RDY
CLK
CE#
t
CES
t
ACS
t
AVC
t
AVD
t
ACH
t
OE
t
IACC
t
AOE
t
BDH
DE DF DB
7 cycles for initial access shown.
Hi-Z
t
RACC
1234567
t
RDYS
t
BACC
t
CR
D8
t
RACC
DC DD
OE#
Data
Addresses Ac
AVD#
RDY
CLK
CE#
tCES
tACS
tAVC
tAVD
tACH
tOE
tIACC
tBDH
DE DF D13
Hi-Z
tRACC
1234567
tRDYS
tBACC
tCR
D10
tRACC
tAOE
7 cycles for initial access shown.
72 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
Notes:
1. Figure assumes 6 wait states for initial access and synchronous read.
2. The Set Configuration Register command sequence has been written with CR8=0; device will output RDY one
cycle before valid data.
Figure 9.10. Linear Burst with RDY Set One Cycle Before Data
9.8.4 AC Characteristics—Asynchronous Read
Note: Not 100% tested.
Parameter
Description 54 MHz 66 MHz
80
MHz UnitJEDEC Standard
t
CE
Access Time from CE# Low Max 70 ns
t
ACC
Asynchronous Access Time Max 70 ns
t
AVDP
AVD# Low Time Min 8 ns
t
AAVDS
Address Setup Time to Rising Edge of AVD# Min 4 ns
t
AAVDH
Address Hold Time from Rising Edge of AVD# Min 7 6 ns
t
OE
Output Enable to Output Valid Max 13.5 11.2 ns
t
OEH
Output Enable Hold Time
Read Min 0 ns
Toggle and Data# Polling Min 10 ns
t
OEZ
Output Enable to High Z (see Note) Max 10 ns
t
CAS
CE# Setup Time to AVD# Min 0 ns
Da+1Da Da+2 Da+3 Da + n
OE#
Data
Addresses Aa
AVD#
RDY
CLK
CE#
tCES
tACS
tAVC
tAVD
tACH
tOE
tRACC
tOEZ
tCEZ
tIACC
tAOE tBDH
6 wait cycles for initial access shown.
Hi-Z
Hi-Z Hi-Z
123456
tRDYS
tBACC
tCR
November 4, 2004 S29WSxxxN_M0_F0 73
Preliminary
Note:
RA = Read Address, RD = Read Data.
Figure 9.11. Asynchronous Mode Read
tCE
WE#
Addresses
CE#
OE#
Valid RD
tACC
tOEH
tOE
Data
tOEZ
tAAVDH
tAVDP
tAAVDS
AVD#
RA
tCAS
November 4, 2004 S29WSxxxN_M0_F0 75
Preliminary
9.8.6 Erase/Program Timing
Notes:
1. Not 100% tested.
2. Asynchronous read mode allows Asynchronous program operation only. Synchronous read mode allows both Asynchronous and
Synchronous program operation.
3. In asynchronous program operation timing, addresses are latched on the falling edge of WE#. In synchronous program operation timing,
addresses are latched on the rising edge of CLK.
4. See the “Erase and Programming Performance” section for more information.
5. Does not include the preprogramming time.
Parameter
Description 54 MHz 66 MHz 80 MHz UnitJEDEC Standard
tAVAV tWC Write Cycle Time (Note 1) Min 70 ns
tAVWL tAS Address Setup Time (Notes 2, 3) Synchronous Min 5ns
Asynchronous 0 ns
tWLAX tAH Address Hold Time (Notes 2, 3) Synchronous Min 9ns
Asynchronous 20
tAVDP AVD# Low Time Min 8 ns
tDVWH tDS Data Setup Time Min 45 20 ns
tWHDX tDH Data Hold Time Min 0 ns
tGHWL tGHWL Read Recovery Time Before Write Min 0 ns
tCAS CE# Setup Time to AVD# Min 0 ns
tWHEH tCH CE# Hold Time Min 0 ns
tWLWH tWP Write Pulse Width Min 30 ns
tWHWL tWPH Write Pulse Width High Min 20 ns
tSR/W Latency Between Read and Write Operations Min 0 ns
tVID VACC Rise and Fall Time Min 500 ns
tVIDS VACC Setup Time (During Accelerated Programming) Min 1 µs
tVCS VCC Setup Time Min 50 µs
tELWL tCS CE# Setup Time to WE# Min 5 ns
tAVSW AVD# Setup Time to WE# Min 5 ns
tAVHW AVD# Hold Time to WE# Min 5 ns
tAVSC AVD# Setup Time to CLK Min 5 ns
tAVHC AVD# Hold Time to CLK Min 5 ns
tCSW Clock Setup Time to WE# Min 5 ns
tWEP Noise Pulse Margin on WE# Max 3 ns
tSEA Sector Erase Accept Time-out Max 50 µs
tESL Erase Suspend Latency Max 20 µs
tPSL Program Suspend Latency Max 20 µs
tASP Toggle Time During Sector Protection Typ 100 µs
tPSP Toggle Time During Programming Within a Protected Sector Typ 1 µs
76 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
Figure 9.2. Chip/Sector Erase Operation Timings: WE# Latched Addresses
OE#
CE#
Data
Addresses
AVD#
WE#
CLK
VCC
tAS
tWP
tAH
tWC
tWPH
SA
tVCS
tCS
tDH
tCH
In
Progress
tWHWH2
VA
Complete
VA
Erase Command Sequence (last two cycles) Read Status Data
tDS
10h for
chip erase
555h for
chip erase
VIH
VIL
tAVDP
55h
2AAh
30h
November 4, 2004 S29WSxxxN_M0_F0 77
Preliminary
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A23–A14 for the WS256N (A22–A14 for the WS128N, A21–A14 for the WS064N) are don’t care during
command sequence unlock cycles.
4. CLK can be either VIL or VIH.
5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the
Configuration Register.
Figure 9.13. Asynchronous Program Operation Timings: WE# Latched Addresses
OE#
CE#
Data
Addresses
AVD
WE#
CLK
VCC
555h
PD
tAS
tAVSW
tAVHW
tAH
tWC
tWPH
PA
tVCS
tWP
tDH
tCH
In
Progress
tWHWH1
VA
Complete
VA
Program Command Sequence (last two cycles) Read Status Data
tDS
VIH
VIL
tAVDP
A0h
tCS
tCAS
78 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A23–A14 for the WS256N (A22–A14 for the WS128N, A21–A14 for the WS064N) are don’t care during
command sequence unlock cycles.
4. Addresses are latched on the first rising edge of CLK.
5. Either CE# or AVD# is required to go from low to high in between programming command sequences.
6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration
Register. The Configuration Register must be set to the Synchronous Read Mode.
Figure 9.14. Synchronous Program Operation Timings: CLK Latched Addresses
OE#
CE#
Data
Addresses
AVD
WE#
CLK
VCC
555h
PD
tWC
tWPH
tWP
PA
tVCS
tDH
tCH
In
Progress
tWHWH1
VA
Complete
VA
Program Command Sequence (last two cycles) Read Status Data
tDS
tAVDP
A0h
tAS
tCAS
tAH
tAVCH
tCSW
tAVSC
November 4, 2004 S29WSxxxN_M0_F0 79
Preliminary
Note: Use setup and hold times from conventional program operation.
Figure 9.15. Accelerated Unlock Bypass Programming Timing
Notes:
1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, and Data#
Polling will output true data.
Figure 9.16. Data# Polling Timings (During Embedded Algorithm)
CE#
AVD#
WE#
Addresses
Data
OE#
ACC
Don't Care Don't CareA0h Don't Care
PA
PD
VID
VIL or VIH
t
VID
t
VIDS
WE#
CE#
OE#
High Z
t
OE
High Z
Addresses
AVD#
t
OEH
t
CE
t
CH
t
OEZ
t
CEZ
Status Data Status Data
t
ACC
VA VA
Data
80 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
Notes:
1. Status reads in figure are shown as asynchronous.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits
will stop toggling.
Figure 9.17. Toggle Bit Timings (During Embedded Algorithm)
Notes:
1. The timings are similar to synchronous read timings.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits
will stop toggling.
3. RDY is active with data (D8 = 1 in the Configuration Register). When D8 = 0 in the Configuration Register, RDY is active one clock cycle before
data.
Figure 9.18. Synchronous Data Polling Timings/Toggle Bit Timings
WE#
CE#
OE#
High Z
t
OE
High Z
Addresses
AVD#
t
OEH
t
CE
t
CH
t
OEZ
t
CEZ
Status Data Status Data
t
ACC
VA VA
Data
CE#
CLK
AVD#
Addresses
OE#
Data
RDY
Status Data Status Data
VA VA
t
IACC
t
IACC
November 4, 2004 S29WSxxxN_M0_F0 81
Preliminary
Notes:
1. RDY(1) active with data (D8 = 1 in the Configuration Register).
2. RDY(2) active one clock cycle before data (D8 = 0 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60.
4. Figure shows the device not crossing a bank in the process of performing an erase or program.
5. RDY will not go low and no additional wait states will be required if the Burst frequency is <=66 MHz and the Boundary Crossing bit (D14)
in the Configuration Register is set to 0
Figure 9.20. Latency with Boundary Crossing when Frequency > 66 MHz
Enter
Erase
Erase
Erase
Enter Erase
Suspend Program
Erase Suspend
Read Erase Suspend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#
to toggle DQ2 and DQ6.
Figure 9.19. DQ2 vs. DQ6
CLK
Address (hex)
C124 C125 C126 C127 C127 C128 C129 C130 C131
D124 D125 D126 D127 D128 D129 D130
(stays high)
AVD#
RDY(1)
Data
OE#,
CE# (stays low)
Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
7C 7D 7E 7F 7F 80 81 82 83
latency
RDY(2) latency
tRACC tRACC
tRACC
tRACC
82 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
Notes:
1. RDY(1) active with data (D8 = 1 in the Configuration Register).
2. RDY(2) active one clock cycle before data (D8 = 0 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60.
4. Figure shows the device crossing a bank in the process of performing an erase or program.
5. RDY will not go low and no additional wait states will be required if the Burst frequency is < 66 MHz and the Boundary Crossing bit (D14) in
the Configuration Register is set to 0.
Figure 9.21. Latency with Boundary Crossing into Program/Erase Bank
CLK
Address (hex)
C124 C125 C126 C127 C127
D124 D125 D126 D127 Read Status
(stays high)
AVD#
RDY(1)
Data
OE#,
CE# (stays low)
Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
7C 7D 7E 7F 7F
latency
RDY(2) latency
t
RACC
t
RACC
t
RACC
t
RACC
November 4, 2004 S29WSxxxN_M0_F0 83
Preliminary
Wait State Configuration Register Setup:
D13, D12, D11 = “111” ⇒ Reserved
D13, D12, D11 = “110” ⇒ Reserved
D13, D12, D11 = “101” ⇒ 5 programmed, 7 total
D13, D12, D11 = “100” ⇒ 4 programmed, 6 total
D13, D12, D11 = “011” ⇒ 3 programmed, 5 total
D13, D12, D11 = “010” ⇒ 2 programmed, 4 total
D13, D12, D11 = “001” ⇒ 1 programmed, 3 total
D13, D12, D11 = “000” ⇒ 0 programmed, 2 total
Note: Figure assumes address D0 is not at an address boundary, and wait state is set to “101”.
Figure 9.22. Example of Wait States Insertion
Data
AVD#
OE#
CLK
12345
D0 D1
01
6
2
7
3
total number of clock cycles
following addresses being latched
Rising edge of next clock cycle
following last wait state triggers
next burst data
number of clock cycles
programmed
45
84 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
Note: Breakpoints in waveforms indicate that system may alternately read array data from the “non-busy bank” while
checking the status of the program or erase operation in the “busy” bank. The system should read status twice to ensure
valid information.
Figure 9.23. Back-to-Back Read/Write Cycle Timings
OE#
CE#
WE#
tOEH
Data
Addresses
AVD#
PD/30h AAh
RA
PA/SA
tWC
tDS tDH
tRC tRC
tOE
tAS
tAH
tACC
tOEH
tWP
tGHWL
tOEZ
tWC
tSR/W
Last Cycle in
Program or
Sector Erase
Command Sequence
Read status (at least two cycles) in same bank
and/or array data from other bank
Begin another
write or program
command sequence
RD
RA 555h
RD
tWPH
November 4, 2004 S29WSxxxN_M0_F0 85
Preliminary
9.8.7 Erase and Programming Performance
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 1.8 V VCC, 10,000
cycles; checkerboard data pattern.
2. Under worst case conditions of 90°C, VCC = 1.70 V, 100,000 cycles.
3. Typical chip programming time is considerably less than the maximum chip programming
time listed, and is based on single word programming.
4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed
to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence
for the program command. See the Appendix for further information on command
definitions.
6. Contact the local sales office for minimum cycling endurance values in specific applications
and operating conditions.
7. Refer to Application Note “Erase Suspend/Resume Timing” for more details.
8. Word programming specification is based upon a single word programming operation not
utilizing the write buffer.
Parameter
Typ (Note 1) Max (Note 2) Unit Comments
Sector Erase Time
64 Kword V
CC
0.6 3.5
s
Excludes 00h
programming prior
to erasure (Note 4)
16 Kword V
CC
<0.15 2
Chip Erase Time
V
CC
153.6 (WS256N)
77.4 (WS128N)
39.3 (WS064N)
308 (WS256N)
154 (WS128N)
78 (WS064N)
s
ACC
130.6 (WS256N)
65.8 (WS128N)
33.4 (WS064N)
262 (WS256N)
132 (WS128N)
66 (WS064N)
Single Word Programming Time
(Note 8)
V
CC
40 400
µs
ACC 24 240
Effective Word Programming Time
utilizing Program Write Buffer
V
CC
9.4 94
µs
ACC 6 60
Total 32-Word Buffer Programming
Time
V
CC
300 3000
µs
ACC 192 1920
Chip Programming Time (Note 3)
V
CC
157.3 (WS256N)
78.6 (WS128N)
39.3 (WS064N)
314.6 (WS256N)
157.3 (WS128N)
78.6 (WS064N)
s
Excludes system
level overhead
(Note 5)
ACC
100.7 (WS256N)
50.3 (WS128N)
25.2 (WS064N)
201.3 (WS256N)
100.7 (WS128N)
50.3 (WS064N)
86 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
9.8.8 BGA Ball Capacitance
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C; f = 1.0 MHz.
Parameter
Symbol Parameter Description Test Setup Typ. Max Unit
C
IN
Input Capacitance V
IN
= 0 5.3 6.3 pF
C
OUT
Output Capacitance V
OUT
= 0 5.8 6.8 pF
C
IN2
Control Pin Capacitance V
IN
= 0 6.3 7.3 pF
November 4, 2004 S29WSxxxN_M0_F0 87
Preliminary
10 Appendix
This section contains information relating to software control or interfacing with the Flash de-
vice. For additional information and assistance regarding software, see the Additional
Resources section on page 18, or explore the Web at www.amd.com and www.fujitsu.com.
88 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
Table 10.1. Memory Array Commands
Command Sequence
(Notes)
Cycles
Bus Cycles (Notes 1–5)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Asynchronous Read (6) 1 RA RD
Reset (7) 1 XXX F0
Auto-
select (8)
Manufacturer ID 4 555 AA 2AA 55 [BA]555 90 [BA]X00 0001
Device ID (9) 6 555 AA 2AA 55 [BA]555 90 [BA]X01 227E BA+X0E Data BA+X0F 2200
Indicator Bits (10) 4 555 AA 2AA 55 [BA]555 90 [BA]X03 Data
Program 4 555 AA 2AA 55 555 A0 PA PD
Write to Buffer (11) 6 555 AA 2AA 55 PA 25 PA WC PA PD WBL PD
Program Buffer to Flash 1 SA 29
Write to Buffer Abort Reset (12) 3 555 AA 2AA 55 555 F0
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Erase/Program Suspend (13) 1 BA B0
Erase/Program Resume (14) 1 BA 30
Set Configuration Register (18) 4 555 AA 2AA 55 555 D0 X00 CR
Read Configuration Register 4 555 AA 2AA 55 555 C6 X00 CR
CFI Query (15) 1 [BA]555 98
Unlock Bypass
Mode
Entry 3 555 AA 2AA 55 555 20
Program (16) 2 XXX A0 PA PD
CFI (16) 1 XXX 98
Reset 2 XXX 90 XXX 00
SecSi Sector
Entry 3 555 AA 2AA 55 555 88
Program (17) 4 555 AA 2AA 55 555 A0 PA PD
Read (17) 1 00 Data
Exit (17) 4 555 AA 2AA 55 555 90 XXX 00
Legend:
X = Don’t care.
RA = Read Address.
RD = Read Data.
PA = Program Address. Addresses latch on the rising edge of the
AVD# pulse or active edge of CLK, whichever occurs first.
PD = Program Data. Data latches on the rising edge of WE# or CE#
pulse, whichever occurs first.
SA = Sector Address. WS256N = A23–A14; WS128N = A22–A14;
WS064N = A21–A14.
BA = Bank Address. WS256N = A23–A20; WS128N = A22–A20;
WS064N = A21–A18.
CR = Configuration Register data bits D15–D0.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
Notes:
1. See Table 5.4 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells indicate read cycles.
4. Address and data bits not specified in table, legend, or notes are
don’t cares (each hex digit implies 4 bits of data).
5. Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state.
The system must write the reset command to return the device
to reading array data.
6. No unlock or command cycles required when bank is reading
array data.
7. Reset command is required to return to reading array data (or to
the erase-suspend-read mode if previously in Erase Suspend)
when a bank is in the autoselect mode, or if DQ5 goes high
(while the bank is providing status information) or performing
sector lock/unlock.
8. The system must provide the bank address. See Autoselect
section for more information.
9. Data in cycle 5 is 2230 (WS256N), 2232 (WS064N), or 2231
(WS128N).
10. See Table 5.16 for indicator bit values.
11. Total number of cycles in the command sequence is determined
by the number of words written to the write buffer. The number
of cycles in the command sequence is 37 for full page
programming (32 words). Less than 32 word programming is not
recommended.
12. Command sequence resets device for next command after write-
to-buffer operation.
13. System may read and program in non-erasing sectors, or enter
the autoselect mode, when in the Erase Suspend mode. The
Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
14. Erase Resume command is valid only during the Erase Suspend
mode, and requires the bank address.
15. Command is valid when device is ready to read array data or
when device is in autoselect mode. Address will equal 55h on all
future devices, but 555h for WS256N/128N/064N.
16. Requires Entry command sequence prior to execution. Unlock
Bypass Reset command is required to return to reading array
data.
17. Requires Entry command sequence prior to execution. SecSi
Sector Exit Reset command is required to exit this mode; device
may otherwise be placed in an unknown state.
18. Requires reset command to configure the Configuration Register.
November 4, 2004 S29WSxxxN_M0_F0 89
Preliminary
Table 10.2. Sector Protection Commands
Command Sequence
(Notes)
Cycles
Bus Cycles (Notes 1–4)
First Second Third Fourth Fifth Sixth Seventh
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Lock
Register
Bits
Command Set Entry (5) 3 555 AA 2AA 55 555 40
Program (6) 2 XX A0 77 data
Read (6) 1 77 data
Command Set Exit (7) 2 XX 90 XX 00
Password
Protection
Command Set Entry (5) 3 555 AA 2AA 55 555 60
Program [0-3] (8) 2 XX A0 00 PWD[0-3]
Read (9) 4 0...00 PWD0 0...01 PWD1 0...02 PWD2 0...03 PWD3
Unlock 7 00 25 00 03 00 PWD0 01 PWD1 02 PWD2 03 PWD3 00 29
Command Set Exit (7) 2 XX 90 XX 00
Non-Volatile
Sector
Protection (PPB)
Command Set Entry (5) 3 555 AA 2AA 55 [BA]555 C0
PPB Program (10) 2 XX A0 SA 00
All PPB Erase (10, 11) 2 XX 80 00 30
PPB Status Read 1 SA RD(0)
Command Set Exit (7) 2 XX 90 XX 00
Global
Volatile Sector
Protection
Freeze
(PPB Lock)
Command Set Entry (5) 3 555 AA 2AA 55 [BA]555 50
PPB Lock Bit Set 2 XX A0 XX 00
PPB Lock Bit Status Read 1 BA RD(0)
Command Set Exit (7) 2 XX 90 XX 00
Volatile Sector
Protection
(DYB)
Command Set Entry (5) 3 555 AA 2AA 55 [BA]555 E0
DYB Set 2 XX A0 SA 00
DYB Clear 2 XX A0 SA 01
DYB Status Read 1 SA RD(0)
Command Set Exit (7) 2 XX 90 XX 00
L
egen
d
:
X = Don’t care.
RA = Address of the memory location to be read.
PD(0) = SecSi Sector Lock Bit. PD(0), or bit[0].
PD(1) = Persistent Protection Mode Lock Bit. PD(1), or bit[1], must
be set to ‘0’ for protection while PD(2), bit[2] must be left as ‘1’.
PD(2) = Password Protection Mode Lock Bit. PD(2), or bit[2], must
be set to ‘0’ for protection while PD(1), bit[1] must be left as ‘1’.
PD(3) = Protection Mode OTP Bit. PD(3) or bit[3].
SA = Sector Address. WS256N = A23–A14; WS128N = A22–A14;
WS064N = A21–A14.
BA = Bank Address. WS256N = A23–A20; WS128N = A22–A20;
WS064N = A21–A18.
PWD3–PWD0 = Password Data. PD3–PD0 present four 16 bit
combinations that represent the 64-bit Password
PWA = Password Address. Address bits A1 and A0 are used to select
each 16-bit portion of the 64-bit entity.
PWD = Password Data.
RD(0), RD(1), RD(2) = DQ0, DQ1, or DQ2 protection indicator bit. If
protected, DQ0, DQ1, or DQ2 = 0. If unprotected, DQ0, DQ1,
DQ2 = 1.
Notes:
1. All values are in hexadecimal.
2. Shaded cells indicate read cycles.
3. Address and data bits not specified in table, legend, or notes are
don’t cares (each hex digit implies 4 bits of data).
4. Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state.
The system must write the reset command to return the device
to reading array data.
5. Entry commands are required to enter a specific mode to enable
instructions only available within that mode.
6. If both the Persistent Protection Mode Locking Bit and the
Password Protection Mode Locking Bit are set at the same time,
the command operation will abort and return the device to the
default Persistent Sector Protection Mode during 2nd bus cycle.
Note that on all future devices, addresses will equal 00h, but are
currently 77h for WS256N, WS128N, and WS064N. See Tables
6.1 and 6.2 for explanation of lock bits.
7. Exit command must be issued to reset the device into read
mode; device may otherwise be placed in an unknown state.
8. Entire two bus-cycle sequence must be entered for each portion
of the password.
9. Full address range is required for reading password.
10. See Figure 6.2 for details.
11. “All PPB Erase” command will pre-program all PPBs before
erasure to prevent over-erasure.
90 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
10.1 Common Flash Memory Interface
The Common Flash Interface (CFI) specification outlines device and host system software in-
terrogation handshake, which allows specific vendor-specified soft-ware algorithms to be
used for entire families of devices. Software support can then be device-independent, JEDEC
ID-independent, and forward- and back-ward-compatible for the specified flash device fami-
lies. Flash vendors can standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h,
to address (BA)555h any time the device is ready to read array data. The system can read
CFI information at the addresses given in Tables 10.3–10.6) within that bank. All reads out-
side of the CFI address range, within the bank, will return non-valid data. Reads from other
banks are allowed, writes are not. To terminate reading CFI data, the system must write the
reset command.
The following is a C source code example of using the CFI Entry and Exit functions. Refer to
the Spansion Low Level Driver User’s Guide (available on www.amd.com and
www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
/* Example: CFI Entry command */
*( (UINT16 *)bank_addr + 0x555 ) = 0x0098; /* write CFI entry command */
/* Example: CFI Exit command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x00F0; /* write cfi exit command */
For further information, please refer to the CFI Specification (see JEDEC publications JEP137-
A and JESD68.01and CFI Publication 100). Please contact your sales office for copies of these
documents.
Table 10.3. CFI Query Identification String
Addresses Data Description
10h
11h
12h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
0002h
0000h Primary OEM Command Set
15h
16h
0040h
0000h Address for Primary Extended Table
17h
18h
0000h
0000h Alternate OEM Command Set (00h = none exists)
19h
1Ah
0000h
0000h Address for Alternate OEM Extended Table (00h = none exists)
November 4, 2004 S29WSxxxN_M0_F0 91
Preliminary
Table 10.4. System Interface String
Addresses Data Description
1Bh 0017h VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch 0019h VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh 0000h VPP Min. voltage (00h = no VPP pin present)
1Eh 0000h VPP Max. voltage (00h = no VPP pin present)
1Fh 0006h Typical timeout per single byte/word write 2N µs
20h 0009h Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h 000Ah Typical timeout per individual block erase 2N ms
22h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)
23h 0004h Max. timeout for byte/word write 2N times typical
24h 0004h Max. timeout for buffer write 2N times typical
25h 0003h Max. timeout per individual block erase 2N times typical
26h 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 10.5. Device Geometry Definition
Addresses Data Description
27h
0019h (WS256N)
0018h (WS128N)
0017h (WS064N)
Device Size = 2
N
byte
28h
29h
0001h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
0006h
0000h
Max. number of bytes in multi-byte write = 2
N
(00h = not supported)
2Ch 0003h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
0003h
0000h
0080h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
00FDh (WS256N)
007Dh (WS128N)
003Dh (WS064N)
Erase Block Region 2 Information
32h
33h
34h
0000h
0000h
0002h
35h
36h
37h
38h
0003h
0000h
0080h
0000h
Erase Block Region 3 Information
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
Erase Block Region 4 Information
92 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
Table 10.6. Primary Vendor-Specific Extended Query
Addresses Data Description
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h 0031h
Major version number, ASCII
44h 0034h
Minor version number, ASCII
45h 0100h
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
Silicon Technology (Bits 5-2) 0100 = 0.11 µm
46h 0002h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h 0001h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
48h 0000h
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h 0008h
Sector Protect/Unprotect scheme
08 = Advanced Sector Protection
4Ah
00F3h (WS256N)
006Fh (WS128N)
0037h (WS064N)
Simultaneous Operation
Number of Sectors in all banks except boot bank
4Bh 0001h
Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch 0000h
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page, 04 = 16 Word
Page
4Dh 0085h
ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
4Eh 0095h
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
4Fh 0001h
Top/Bottom Boot Sector Flag
0001h = Dual Boot Device
50h 0001h
Program Suspend. 00h = not supported
51h 0001h
Unlock Bypass
00 = Not Supported, 01=Supported
52h 0007h
SecSi Sector (Customer OTP Area) Size 2
N
bytes
53h 0014h
Hardware Reset Low Time-out during an embedded algorithm to read
mode Maximum 2
N
ns
54h 0014h
Hardware Reset Low Time-out not during an embedded algorithm to read
mode Maximum 2
N
ns
55h 0005h
Erase Suspend Time-out Maximum 2
N
ns
56h 0005h
Program Suspend Time-out Maximum 2
N
ns
57h 0010h
Bank Organization: X = Number of banks
58h
0013h (WS256N)
000Bh (WS128N)
0007h (WS064N)
Bank 0 Region Information. X = Number of sectors in bank
November 4, 2004 S29WSxxxN_M0_F0 93
Preliminary
59h
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
Bank 1 Region Information. X = Number of sectors in bank
5Ah
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
Bank 2 Region Information. X = Number of sectors in bank
5Bh
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
Bank 3 Region Information. X = Number of sectors in bank
5Ch
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
Bank 4 Region Information. X = Number of sectors in bank
5Dh
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
Bank 5 Region Information. X = Number of sectors in bank
5Eh
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
Bank 6 Region Information. X = Number of sectors in bank
5Fh
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
Bank 7 Region Information. X = Number of sectors in bank
60h
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
Bank 8 Region Information. X = Number of sectors in bank
61h
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
Bank 9 Region Information. X = Number of sectors in bank
62h
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
Bank 10 Region Information. X = Number of sectors in bank
63h
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
Bank 11 Region Information. X = Number of sectors in bank
64h
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
Bank 12 Region Information. X = Number of sectors in bank
65h
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
Bank 13 Region Information. X = Number of sectors in bank
66h
0010h (WS256N)
0008h (WS128N)
0004h (WS064N)
Bank 14 Region Information. X = Number of sectors in bank
67h
0013h (WS256N)
000Bh (WS128N)
0007h (WS064N)
Bank 15 Region Information. X = Number of sectors in bank
Table 10.6. Primary Vendor-Specific Extended Query (Continued)
Addresses Data Description
94 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
11 Commonly Used Terms
Term Definition
ACC
ACCelerate.
A special purpose input signal which allows for faster programming or
erase operation when raised to a specified voltage above V
CC
. In some devices ACC
may protect all sectors when at a low voltage.
A
max
Most significant bit of the address input [A23 for 256Mbit, A22 for128Mbit, A21 for
64Mbit]
A
min
Least significant bit of the address input signals (A0 for all devices in this document).
Asynchronous Operation where signal relationships are based only on propagation delays and are
unrelated to synchronous control (clock) signal.
Autoselect Read mode for obtaining manufacturer and device information as well as sector
protection status.
Bank
Section of the memory array consisting of multiple consecutive sectors. A read
operation in one bank, can be independent of a program or erase operation in a
different bank for devices that offer simultaneous read and write feature.
Boot sector
Smaller size sectors located at the top and or bottom of Flash device address space.
The smaller sector size allows for finer granularity control of erase and protection for
code or parameters used to initiate system operation after power-on or reset.
Boundary Location at the beginning or end of series of memory locations.
Burst Read See synchronous read.
Byte 8 bits
CFI
Common Flash Interface. A Flash memory industry standard specification [JEDEC 137-
A and JESD68.01] designed to allow a system to interrogate the Flash to determine its
size, type and other performance parameters.
Clear Zero (Logic Low Level)
Configuration Register Special purpose register which must be programmed to enable synchronous read
mode
Continuous Read
Synchronous method of burst read whereby the device will read continuously until it is
stopped by the host, or it has reached the highest address of the memory array, after
which the read address wraps around to the lowest memory array address
Erase Returns bits of a Flash memory array to their default state of a logical One (High Level).
Erase Suspend/Erase Resume Halts an erase operation to allow reading or programming in any sector that is not
selected for erasure
BGA
Ball Grid Array package. Spansion LLC offers two variations: Fortified Ball Grid Array
and Fine-pitch Ball Grid Array. See the specific package drawing or connection diagram
for further details.
Linear Read Synchronous (burst) read operation in which 8, 16, or 32 words of sequential data with
or without wraparound before requiring a new initial address
.
MCP Multi-Chip Package. A method of combining integrated circuits in a single package by
“stacking” multiple die of the same or different devices.
Memory Array The programmable area of the product available for data storage.
MirrorBit™ Technology Spansion™ trademarked technology for storing multiple bits of data in the same
transistor.
November 4, 2004 S29WSxxxN_M0_F0 95
Preliminary
Page Group of words that may be accessed more rapidly as a group than if the words were
accessed individually.
Page Read
Asynchronous read operation of several words in which the first word of the group
takes a longer initial access time and subsequent words in the group take less “page”
access time to be read. Different words in the group are accessed by changing only the
least significant address lines.
Password Protection Sector protection method which uses a programmable password, in addition to the
Persistent Protection method, for protection of sectors in the Flash memory device
.
Persistent Protection
Sector protection method that uses commands and only the standard core voltage
supply to control protection of sectors in the Flash memory device. This method
replaces a prior technique of requiring a 12V supply to control the protection method.
Program Stores data into a Flash memory by selectively clearing bits of the memory array in
order to leave a data pattern of “ones” and “zeros”.
Program Suspend/Program
Resume
Halts a programming operation to read data from any location that is not selected for
programming or erase.
Read Host bus cycle that causes the Flash to output data onto the data bus.
Registers Dynamic storage bits for holding device control information or tracking the status of
an operation.
SecSi™
Secured Silicon. An area consisting of 256 bytes in which any word may be
programmed once, and the entire area may be protected once from any future
programming. Information in this area may be programmed at the factory or by the
user. Once programmed and protected there is no way to change the secured
information. This area is often used to store a software readable identification such as
a serial number.
Sector Protection
Use of one or more control bits per sector to indicate whether each sector may be
programmed or erased. If the Protection bit for a sector is set the embedded
algorithms for program or erase will ignore program or erase commands related to that
sector.
Sector An Area of the memory array in which all bits must be erased together by an erase
operation.
Simultaneous Operation
Mode of operation in which a host system may issue a program or erase command to
one bank, that embedded algorithm operation may then proceed while the host
immediately follows the embedded algorithm command with reading from another
bank.
Reading may continue concurrently in any bank other than the one executing
the embedded algorithm operation.
Synchronous Operation Operation that progresses only when a timing signal, known as a clock, transitions
between logic levels (that is, at a clock edge).
VersatileIO™ (V
IO
)
Separate power supply or voltage reference signal that allows the host system to set
the voltage levels that the device generates at its data outputs and the voltages
tolerated at its data inputs.
Unlock Bypass
Mode that facilitates faster program times by reducing the number of command bus
cycles required to issue a write operation command. In this mode the initial two
“Unlock” write cycles, of the usual 4 cycle Program command, are not required –
reducing all Program commands to two bus cycles while in this mode.
Word
Two contiguous bytes (16 bits) located at an even byte boundary. A double word is two
contiguous words located on a two word boundary. A quad word is four contiguous
words located on a four word boundary.
Term Definition
96 S29WSxxxN_M0_F0 November 4, 2004
Preliminary
Wraparound
Special burst read mode where the read address “wraps” or returns back to the lowest
address boundary in the selected range of words, after reading the last Byte or Word
in the range, e.g. for a 4 word range of 0 to 3, a read beginning at word 2 would read
words in the sequence 2, 3, 0, 1.
Write
Interchangeable term for a program/erase operation where the content of a register
and or memory location is being altered. The term write is often associated with
“writing command cycles” to enter or exit a particular mode of operation.
Write Buffer
Multi-word area in which multiple words may be programmed as a single operation
.
A
Write Buffer may be 16 to 32 words long and is located on a 16 or 32 word boundary
respectively.
Write Buffer Programming
Method of writing multiple words, up to the maximum size of the Write Buffer, in one
operation. Using Write Buffer Programming will result in
≥
8 times faster programming
time than by using single word at a time programming commands.
Write Operation Status Allows the host system to determine the status of a program or erase operation by
reading several special purpose register bits
.
Term Definition
October 5, 2004 CosmoRAM_00_A0 CosmoRAM 97
Preliminary
CosmoRAM
32Mbit (2M word x 16-bit)
64Mbit (4M word x 16-bit)
Features
Asynchronous SRAM Interface
Fast Access Time
—t
CE = tAA = 70ns max
8 words Page Access Capability
—t
PAA = 20ns max
Low Voltage Operating Condition
—V
DD = +1.65V to +1.95V (32M)
— +1.70V to +1.95V (64M)
Wide Operating Temperature
— TA = -30°C to +85°C
Byte Control by LB# and UB#
Low Power Consumption
—I
DDA1 = 30mA max (32M), TBDmA max (64M)
—I
DDS1 = 80mA max (32M), TBDmA max (64M)
Various Power Down mode
— Sleep, 4M-bit Partial or 8M-bit Partial (32M)
— Sleep, 8M-bit Partial or 16M-bit Partial (64M)
98 CosmoRAM CosmoRAM_00_A0 October 5, 2004
Preliminary
Pin Description (32M)
Pin Name Description
A
21
to A
0
Address Input: A
20
to A
0
for 32M, A
21
to A
0
for 64M
CE1# Chip Enable (Low Active)
CE2 Chip Enable (High Active)
WE# Write Enable (Low Active)
OE# Output Enable (Low Active)
UB# Upper Byte Control (Low Active)
LB# Lower Byte Control (Low Active)
CLK Clock Input
ADV# Address Valid Input (Low Active)
WAIT# Wait Signal Output
DQ
16
-
9
Upper Byte Data Input/Output
DQ
8
-
1
Lower Byte Data Input/Output
V
DD
Power Supply
V
SS
Ground
October 5, 2004 CosmoRAM_00_A0 CosmoRAM 99
Preliminary
Functional Description
Asynchronous Operation (Page Mode)
Legend:L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance.
Notes:
1. Should not be kept at this logic condition longer than 1µs.
2. Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. Data retention depends on the
selection of Partial Size. Refer to the "Power Down" section in the Functional Description for details.
3. “L” for address pass through and “H” for address latch on the rising edge of ADV#.
4. OE# can be VIL during Write operation if the following conditions are satisfied:
(1) Write pulse is initiated by CE1# (refer to CE1# Controlled Write timing), or cycle time of the previous operation cycle is
satisfied.
(2) OE# stays VIL during Write cycle
5. Can be either VIL or VIH but must be valid before Read or Write.
6. Output is either Valid or High-Z depending on the level of UB# and LB# input.
Mode CE2 CE1# CLK ADV# WE# OE# LB# UB# A21-0 DQ8-1 DQ16-9 WAIT#
Standby (Deselect) H H X X X X X X X High-Z High-Z High-Z
Output Disable (Note 1)
HL
X
(Note 3)
H H X X Note 5 High-Z High-Z High-Z
Output Disable (No Read) X
HL
H H Valid High-Z High-Z High-Z
Read (Upper Byte) X H L Valid High-Z Output Valid High-Z
Read (Lower Byte) X L H Valid Output Valid High-Z High-Z
Read (Word) X L L Valid Output Valid Output Valid High-Z
Page Read X L/H L/H Valid Note 6 Note 6 High-Z
No Write X
LH
(Note 4)
H H Valid Invalid Invalid High-Z
Write (Upper Byte) X H L Valid Invalid Input Valid High-Z
Write (Lower Byte) X L H Valid Input Valid Invalid High-Z
Write (Word) X L L Valid Input Valid Input Valid High-Z
Power Down (Note 2) L X X X X X X X X High-Z High-Z High-Z
100 CosmoRAM CosmoRAM_00_A0 October 5, 2004
Preliminary
Functional Description
Synchronous Operation (Burst Mode)
Legend:L = VIL, H = VIH, X can be either VIL or VIH, VE = Valid Edge, PELP = Positive Edge of Low Pulse, High-
Z = High Impedance.
Notes:
1. Should not be kept this logic condition longer than the specified time of 8µs for 32M and 4µs for 64M.
2. Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. Data retention depends on the
selection of Partial Size. Refer to the "Power Down" section for details.F
3. Valid clock edge shall be set on either positive or negative edge through CR Set. CLK must be started and stable prior to
memory access.
4. Can be either VIL or VIH except for the case the both of OE# and WE# are VIL. It is prohibited to bring the both of OE# and
WE# to VIL.
5. When device is operating in “WE# Single Clock Pulse Control” mode, WE# is don’t care once write operation is determined by
WE# Low Pulse at the beginning of write access together with address latching. Write suspend feature is not supported in
“WE# Single Clock Pulse Control” mode.
6. Can be either VIL or VIH but must be valid before Read or Write is determined. And once UB# and LB# inputs are
determined, they must not be changed until the end of burst.
7. Once valid address is determined, input address must not be changed during ADV#=L.
8. If OE#=L, output is either Invalid or High-Z depending on the level of UB# and LB# input. If WE#=L, Input is Invalid. If
OE#=WE#=H, output is High-Z.
9. Output is either Valid or High-Z depending on the level of UB# and LB# input.
10. Input is either Valid or Invalid depending on the level of UB# and LB# input.
11. Output is either High-Z or Invalid depending on the level of OE# and WE# input.
12. Keep the level from previous cycle except for suspending on last data. Refer to “WAIT# Output Function” for details.
13. WAIT# output is driven in High level during write operation.
Mode CE2 CE1# CLK ADV# WE# OE# LB# UB# A21-0 DQ8-1 DQ16-9 WAIT#
Standby (Deselect)
H
H X X X X X X X High-Z High-Z High-Z
Start Address
Latch
(Note 1)
L
VE
(Note 3) PELP X
(Note 4)
X
(Note 4)
X
(Note 6)
X
(Note 6)
Valid
(Note 7)
High-Z
(Note 8)
High-Z
(Note 8)
High-Z
(Note 11)
Advance Burst
Read to Next
Address (Note 1)
VE
(Note 3)
H
H
L
X
Output
Valid
(Note 9)
Output
Valid
(Note 9)
Output
Valid
Burst Read
Suspend
(Note 1)
VE
(Note 3) H High-Z High-Z High
(Note 12)
Advance Burst
Write to Next
Address (Note 1)
VE
(Note 3)
L
(Note 5)
H
Input
Valid
(Note 10)
Input
Valid
(Note
10)
High
(Note 13)
Burst Write
Suspend (Note 1)
VE
(Note 3)
H
(Note 5)
Iput
Invalid
Iput
Invalid
High
(Note 12)
Terminate Burst
Read VE X H X High-Z High-Z High-Z
Terminate Burst
Write VE X X H High-Z High-Z High-Z
Power Down
(Note 2) L X X X X X X X X High-Z High-Z High-Z
October 5, 2004 CosmoRAM_00_A0 CosmoRAM 101
Preliminary
State Diagrams
Initial/Standby State
Asynchronous Operation State
Figure 11.7. Initial Standby State Diagram
Figure 11.8. Asynchronous Operation State Diagram
CR Set
Power
Down
StandbyStandby
Power Up
Pause Time
CE2=L
CE2= H
Power
Down
CE2=H
@RP=1
CE2=L
@M=0@M=1
CE2=H
@RP=0 (64M Only)
Common State
Synchronous Operation
(Burst Mode)
Asynchronous Operation
(Page Mode)
Write
Byte Control
Standby
CE1# = L &
WE# = L
Byte Control @ OE# = L
Read
WE# = L
CE2 = CE1# = H
Output
Disable
WE# = H
OE# = H
CE1# = H
CE1# = L
CE1# = H
CE1# = H
OE# = L
CE1# = L &
OE# = L
Address Change
or Byte Control
102 CosmoRAM CosmoRAM_00_A0 October 5, 2004
Preliminary
Synchronous Operation State
Notes:
1. Assumes all the parameters specified in the "AC Characteristics" section are satisfied. Refer to the "Functional Description"
section, "AC Characteristics" section, and the "Timing Diagrams" section for details. RP (Reset to Page) mode is available
only for 64M.
Functional Description
This device supports asynchronous page read & normal write operation and syn-
chronous burst read & burst write operation for faster memory access and
features three kinds of power down modes for power saving as a user config-
urable option.
Power-up
It is required to follow the power-up timing to start executing proper device op-
eration. Refer to POWER-UP Timing. After Power-up, the device defaults to
asynchronous page read & normal write operation mode with sleep power down
feature.
Configuration Register
The Configuration Register (CR) is used to configure the type of device function
among optional features. Each selection of features is set through CR Set se-
quence after Power-up. If CR Set sequence is not performed after power-up, the
device is configured for asynchronous operation with sleep power down feature
as default configuration.
CR Set Sequence
The CR Set requires total 6 read/write operations with unique address. Between
each read/write operation requires the device to be in standby mode. The follow-
ing table shows the detail sequence.
Figure 11.9. Synchronous Operation Diagram
Cycle # Operation Address Data
1st Read 3FFFFFh (MSB) Read Data (RDa)
2nd Write 3FFFFFh RDa
CE2 = CE1# = H
CE1# = H
CE1# = L
ADV# Low Pulse
& OE# = L
ADV# Low Pulse
OE# = L
OE# = H
CE1# = H
Write
Suspend
WE# = L
WE# = H
ADV# Low Pulse Write
CE1# = L
ADV# Low Pulse
& WE# = L
ADV# Low Pulse
(@BL = 8 or 16, and after burst
o
p
eration is com
p
leted
)
Read
Standby
Read
Suspend
CE1# = H
CE1# = H
October 5, 2004 CosmoRAM_00_A0 CosmoRAM 103
Preliminary
The first cycle is to read from most significant address (MSB).
The second and third cycle are to write to MSB. If the second or third cycle is writ-
ten into the different address, the CR Set is cancelled and the data written by the
second or third cycle is valid as a normal write operation. It is recommended to
write back the data (RDa) read by first cycle to MSB in order to secure the data.
The forth and fifth cycle is to write to MSB. The data of forth and fifth cycle is
don’t-care. If the forth or fifth cycle is written into different address, the CR Set
is also cancelled but write data may not be written as normal write operation.
The last cycle is to read from specific address key for mode selection. And read
data (RDb) is invalid.
Once this CR Set sequence is performed from an initial CR set to the other new
CR set, the written data stored in memory cell array may be lost. So, CR Set se-
quence should be performed prior to regular read/write operation if necessary to
change from default configuration.
3rd Write 3FFFFFh RDa
4th Write 3FFFFFh X
5th Write 3FFFFFh X
6th Read Address Key Read Data (RDb)
Cycle # Operation Address Data
104 CosmoRAM CosmoRAM_00_A0 October 5, 2004
Preliminary
Address Key
The address key has the following format.
Notes:
1. A21 and A6 to A0 must be all “1” in any case.
2. It is prohibited to apply this key.
3. If M=0, all the registers must be set with appropriate Key input at the same time.
4. If M=1, PS must be set with appropriate Key input at the same time. Except for PS, all the other key inputs must be “1”.
5. Burst Read & Single Write is not supported at WE# Single Clock Pulse Control.
6. Effective only when PS=11. RP (Reset to Page) mode is available only for 64M.
Address
Pin
Register
Name Function Key
Description Note
32M 64M
A21 — — 1 — Unused bits muse be 1 1
A20-A19 PS Partial Size
00 8M Partial 16M Partial
01 4M Partial 8M Partial
10 Reserved for future use 2
11 Sleep [Default]
A18-A16 BL Burst Length
000 to 001 Reserved for future use 2
010 8 words
011 16 words
100 to 110 Reserved for future use 2
111 Continuous
A15 M Mode
0 Synchronous Mode (Burst Read / Write) 3
1 Asynchronous Mode [Default] (Page Read / Normal Write) 4
A14-A12 RL Read Latency
000 Reserved for future use 2
001 3 clocks
010 4 clocks
011 5 clocks
100 Reserved for future use 6 clocks
101 to 111 Reserved for future use 2
A11 BS Burst
Sequence
0 Reserved for future use 2
1 Sequential
A10 SW Single Write
0 Burst Read & Burst Write
1 Burst Read & Single Write 5
A9 VE Valid Clock
Edge
0 Falling Clock Edge
1 Rising Clock Edge
A8 RP Reset to Page
0
Unused bits must be 1
Reset to Page mode 6
1 Remain the previous mode
A7 WC Write Control
0WE# Single Clock Pulse Control without Write Suspend
Function 5
1 WE# Level Control with Write Suspend Function
A6-A0 — — 1 Unused bits muse be 1 1
October 5, 2004 CosmoRAM_00_A0 CosmoRAM 105
Preliminary
Power Down
The Power Down is low power idle state controlled by CE2. CE2 Low drives the
device in power down mode and maintains low power idle state as long as CE2 is
kept Low. CE2 High resumes the device from power down mode. These devices
have three power down mode. These can be programmed by series of read/write
operations. Each mode has following features.
The default state is Sleep and it is the lowest power consumption but all data will
be lost once CE2 is brought to Low for Power Down. It is not required to program
to Sleep mode after power-up.
64M supports Reset to Page (RP) mode. When RP=0, Power Down comprehends
a function to reset the device to default configuration (asynchronous mode). After
resuming from power down mode, the device is back in default configurations.
This is effective only when PS is set on Sleep mode. When Partial mode is se-
lected, RP=0 is not effective.
Burst Read/Write Operation
Synchronous burst read/write operation provides faster memory access that syn-
chronized to microcontroller or system bus frequency. Configuration Register Set
is required to perform burst read & write operation after power-up. Once CR Set
sequence is performed to select synchronous burst mode, the device is config-
ured to synchronous burst read/write operation mode with corresponding RL and
BL that is set through CR Set sequence together with operation mode. In order
to perform synchronous burst read & write operation, it is required to control new
signals, CLK, ADV# and WAIT# that Low Power SRAMs don’t have.
32M 64M
Mode Data Retention Size Retention Address Mode Data Retention Size Retention Address
Sleep (default) No N/A Sleep (default) No N/A
4M Partial 4M bit 000000h to 03FFFFh 8M Partial 8M bit 000000h to 07FFFFh
8M Partial 8M bit 000000h to 07FFFFh 16M Partial 16M bit 000000h to 0FFFFFh
106 CosmoRAM CosmoRAM_00_A0 October 5, 2004
Preliminary
CLK Input Function
The CLK is input signal to synchronize memory to microcontroller or system bus
frequency during synchronous burst read & write operation. The CLK input incre-
ments device internal address counter and the valid edge of CLK is referred for
latency counts from address latch, burst write data latch, and burst read data out.
During synchronous operation mode, CLK input must be supplied except for
standby state and power down state. CLK is don’t care during asynchronous
operation.
Figure 11.10. Burst Read Operation
Figure 11.11. Burst Write Operation
A
DDRESS
ADV#
CLK
DQ
Valid
CE1#
OE#
WAIT# High-Z
High-Z
RL
BL
Q2QBLQ1
WE#
High
A
DDRESS
ADV#
CLK
DQ
Valid
CE1#
OE#
WAIT# High-Z
High-Z RL-1
BL
D2DBLD1
WE#
High
October 5, 2004 CosmoRAM_00_A0 CosmoRAM 107
Preliminary
ADV# Input Function
The ADV# is input signal to indicate valid address presence on address inputs. It
is applicable to synchronous operation as well as asynchronous operation. ADV#
input is active during CE1#=L and CE1#=H disables ADV# input. All addresses
are determined on the positive edge of ADV#.
During synchronous burst read/write operation, ADV#=H disables all address in-
puts. Once ADV# is brought to High after valid address latch, it is inhibited to
bring ADV# Low until the end of burst or until burst operation is terminated.
ADV# Low pulse is mandatory for synchronous burst read/write operation mode
to latch the valid address input.
During asynchronous operation, ADV#=H also disables all address inputs. ADV#
can be tied to Low during asynchronous operation and it is not necessary to con-
trol ADV# to High.
WAIT# Output Function
The WAIT# is output signal to indicate data bus status when the device is oper-
ating in synchronous burst mode.
During burst read operation, WAIT# output is enabled after specified time dura-
tion from OE#=L or CE1#=L whichever occurs last. WAIT# output Low indicates
data out at next clock cycle is invalid, and WAIT# output becomes High one clock
cycle prior to valid data out. During OE# read suspend, WAIT# output doesn’t
indicate data bus status but carries the same level from previous clock cycle (kept
High) except for read suspend on the final data output. If final read data out is
suspended, WAIT# output become high impedance after specified time duration
from OE#=H.
In case of continuous burst read operation of 32M, an additional output delay may
occur when a burst sequence crosses it’s device-row boundary. The WAIT# out-
put indicates this delay. Refer to the "Burst Length" section for the additional
delay cycles in details.
During burst write operation, WAIT# output is enabled to High level after speci-
fied time duration from WE#=L or CE1#=L whichever occurs last and kept High
for entire write cycles including WE# write suspend. The actual write data latch-
ing starts on the appropriate clock edge with respect to Valid Clock Edge, Read
Latency and Burst Length. During WE# write suspend, WAIT# output doesn’t in-
dicate data bus status but carries the same level from previous clock cycle (kept
High) except for write suspend on the final data input. If final write data in is sus-
pended, WAIT# output become high impedance after specified time duration
from WE#=H.
The burst write operation of 32M and the both burst read/write operation of 64M
are always started after fixed latency with respect to Read Latency set in CR.
When the device is operating in asynchronous mode, WAIT# output is always in
High Impedance.
108 CosmoRAM CosmoRAM_00_A0 October 5, 2004
Preliminary
Latency
Read Latency (RL) is the number of clock cycles between the address being
latched and first read data becoming available during synchronous burst read op-
eration. It is set through CR Set sequence after power-up. Once specific RL is set
through CR Set sequence, write latency, that is the number of clock cycles be-
tween address being latched and first write data being latched, is automatically
set to RL-1.The burst operation is always started after fixed latency with respect
to Read Latency set in CR. RL=6 is available only for 64M.
Figure 11.12. Read Latency Diagram
ADDRESS
ADV#
CLK
Valid
Q1 Q2 Q3
D1 D2 D3 D4
012345
RL=3
Q4
D5
DQ [Out]
DQ [In]
CE1#
OE# or WE#
WAIT#
WAIT#
6
Q5
D5
Q1 Q2
D1 D2 D3
RL=4
Q3
D4
DQ [Out]
DQ [In]
WAIT#
WAIT#
Q4
D5
Q1
D1 D2
RL=5
Q2
D3
DQ [Out]
DQ [In]
WAIT#
WAIT#
Q3
D4
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
D1
RL=6
Q1
D2
DQ [Out]
DQ [In]
WAIT#
WAIT#
Q2
D3
High-Z
High-Z
October 5, 2004 CosmoRAM_00_A0 CosmoRAM 109
Preliminary
Address Latch by ADV#
The ADV# indicates valid address presence on address inputs. During synchro-
nous burst read/write operation mode, all the address are determined on the
positive edge of ADV# when CE1#=L. The specified minimum value of ADV#=L
setup time and hold time against valid edge of clock where RL count begin must
be satisfied for appropriate RL counts. Valid address must be determined with
specified setup time against either the negative edge of ADV# or negative edge
of CE1# whichever comes late. And the determined valid address must not be
changed during ADV#=L period.
Burst Length
Burst Length is the number of word to be read or write during synchronous burst
read/write operation as the result of a single address latch cycle. It can be set on
8, 16 words boundary or continuous for entire address through CR Set sequence.
The burst type is sequential that is incremental decoding scheme within a bound-
ary address. Starting from initial address being latched, device internal address
counter assign +1 to the previous address until reaching the end of boundary ad-
dress and then wrap round to least significant address (=0). After completing
read data out or write data latch for the set burst length, operation automatically
ended except for continuous burst length. When continuous burst length is set,
read/write is endless unless it is terminated by the positive edge of CE1#.
During continuous burst read of 32M, an additional output delay may occur when
a burst sequence cross it’s device-row boundary. This is the case when A0 to A6
of starting address is either 7Dh, 7Eh, or 7Fh as shown in the following table. The
WAIT# signal indicates this delay. The 64M device has no additional output delay.
Note: Read address in Hexadecimal.
Single Write
Single Write is synchronous write operation with Burst Length =1. The device can
be configured either to “Burst Read & Single Write” or to “Burst Read & Burst
Write” through CR set sequence. Once the device is configured to “Burst Read &
Single Write” mode, the burst length for synchronous write operation is always
fixed 1 regardless of BL values set in CR, while burst length for read is in accor-
dance with BL values set in CR.
Start Address
(A6-A0)
Read Address Sequence
BL = 8 BL = 16 Continuous
00h 00-01-02-...-06-07 00-01-02-...-0E-0F 00-01-02-03-04-...
01h 01-02-03-...-07-00 01-02-03-...-0F-00 01-02-03-04-05-...
02h 02-03-...-07-00-01 02-03-...-0F-00-01 02-03-04-05-06-...
03h 03-...-07-00-01-02 03-...-0F-00-01-02 03-04-05-06-07-...
... ... ... ...
7Ch 7C-...-7F-78-...-7B 7C-...-7F-70-...-7B 7C-7D-7E-7F-80-81-...
7Dh 7D-7E-7F-78-...-7C 7D-7E-7F-70-...-7C 7D-7E-7F-
WAIT
-80-81-...
7Eh 7E-7F-78-79-...-7D 7E-7F-70-71-...-7D 7E-7F-
WAIT
-
WAIT
-80-81-...
7Fh 7F-78-79-7A-...-7E 7F-70-71-72-...-7E 7F-
WAIT
-
WAIT
-
WAIT
-80-81
110 CosmoRAM CosmoRAM_00_A0 October 5, 2004
Preliminary
Write Control
The device has two types of WE# signal control method, “WE# Level Control” and
“WE# Single Clock Pulse Control”, for synchronous write operation. It is config-
ured through CR set sequence.
Burst Read Suspend
Burst read operation can be suspended by OE# High pulse. During burst read op-
eration, OE# brought to High suspends burst read operation. Once OE# is
brought to High with the specified set up time against clock where the data being
suspended, the device internal counter is suspended, and the data output be-
come high impedance after specified time duration. It is inhibited to suspend the
first data out at the beginning of burst read.
OE# brought to Low resumes burst read operation. Once OE# is brought to Low,
data output become valid after specified time duration, and internal address
counter is reactivated. The last data out being suspended as the result of OE#=H
and first data out as the result of OE#=L are from the same address.
In order to guarantee to output last data before suspension and first data after
resumption, the specified minimum value of OE#=L hold time and setup time
against clock edge must be satisfied respectively.
Figure 11.13. Write Controls
ADDRESS
ADV#
CLK
Valid
012345
CE1#
WE#
6
D1 D2
RL=5
D3
DQ [In]
WAIT#
D4
WE#
D1 D2 D3
DQ [In]
WAIT#
D4
High-Z
tWLD
High-Z
tWSCK
tCKWH
tWLTH
tCLTH
WE# Level Control
WE# Single Clock Pulse Control
tWLTH
October 5, 2004 CosmoRAM_00_A0 CosmoRAM 111
Preliminary
Burst Write Suspend
Burst write operation can be suspended by WE# High pulse. During burst write
operation, WE# brought to High suspends burst write operation. Once WE# is
brought to High with the specified set up time against clock where the data being
suspended, device internal counter is suspended, data input is ignored. It is in-
hibited to suspend the first data input at the beginning of burst write.
WE# brought to Low resumes burst write operation. Once WE# is brought to Low,
data input become valid after specified time duration, and internal address
counter is reactivated. The write address of the cycle where data being sus-
pended and the first write address as the result of WE#=L are the same address.
In order to guarantee to latch the last data input before suspension and first data
input after resumption, the specified minimum value of WE#=L hold time and
setup time against clock edge must be satisfied respectively. Burst write suspend
function is available when the device is operating in WE# level controlled burst
write only.
Burst Read Termination
Burst read operation can be terminated by CE1# brought to High. If BL is set on
Continuous, burst read operation is continued endless unless terminated by
Figure 11.14. Burst Read Suspend Diagram
Figure 11.15. Burst Write Suspend Diagram
Q
2
DQ
OE#
CLK
Q
1
t
AC
t
CKQX
t
OLZ
t
AC
Q
2
t
CKQX
t
AC
Q
3
t
CKQX
t
AC
t
CKOH
t
OSCK
t
CKOH
t
OSCK
t
OHZ
WAIT#
t
CKTV
Q
4
DQ
WE#
D
1
t
DHCK
t
DSCK
t
DSCK
D
2
t
DHCK
t
DSCK
t
DSCK
D
3
t
DHCK
t
DSCK
t
DSCK
t
CKWH
t
WSCK
t
CKWH
t
WSCK
D
2
D
4
WAIT# High
CLK
112 CosmoRAM CosmoRAM_00_A0 October 5, 2004
Preliminary
CE1#=H. It is inhibited to terminate burst read before first data out is completed.
In order to guarantee last data output, the specified minimum value of CE1#=L
hold time from clock edge must be satisfied. After termination, the specified min-
imum recovery time is required to start new access.
Burst Write Termination
Burst write operation can be terminated by CE1# brought to High. If BL is set on
Continuous, burst write operation is continued endless unless terminated by
CE1#=H. It is inhibited to terminate burst write before first data in is completed.
In order to guarantee last write data being latched, the specified minimum values
of CE1#=L hold time from clock edge must be satisfied. After termination, the
specified minimum recovery time is required to start new access.
Figure 11.16. Burst Read Termination Diagram
Figure 11.17. Burst Write Termination Diagram
A
DDRESS
ADV#
DQ
OE#
CLK
Valid
CE1#
WAIT#
Q1Q2
tAC
tCKQX
tCKCLH
tTRB
tCKOH
tCHZ
High-Z
tCHTZ
tOHZ
A
DDRESS
ADV#
DQ
WE#
CLK
Valid
CE1#
WAIT#
tCKCLH
tTRB
tCKWH
tCHTZ High-Z
D2D1
tDHCKtDHCK
tDSCKtDSCK
tCHCK
October 5, 2004 CosmoRAM_00_A0 CosmoRAM 113
Preliminary
Absolute Maximum Ratings
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions (See Warning Below)
Notes:
1. Maximum DC voltage on input and I/O pins are VDD+0.2V. During voltage transitions, inputs may positive overshoot to
VDD+1.0V for periods of up to 5 ns.
2. Minimum DC voltage on input or I/O pins are -0.3V. During voltage transitions, inputs may negative overshoot VSS to -1.0V
for periods of up to 5ns.
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the de-
vice’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may
adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet.
Package Pin Capacitance
Test conditions: TA = 25°C, f = 1.0 MHz
Item Symbol Value Unit
Voltage of V
DD
Supply Relative to V
SS
V
DD
-0.5 to +3.6 V
Voltage at Any Pin Relative to V
SS
V
IN
, V
OUT
-0.5 to +3.6 V
Short Circuit Output Current I
OUT
±50 mA
Storage temperature T
STG
-55 to +125 °C
Parameter Symbol
32M 64M
UnitMin Max Min Max
Supply Voltage
V
DD
1.65 1.95 1.7 1.95 V
V
SS
0 0 0 0 V
High Level Input Voltage (Note 1) V
IH
V
DD
x 0.8 V
DD
+0.2 V
DD
x 0.8 V
DD
+0.2 V
High Level Input Voltage (Note 2) V
IL
-0.3 V
DD
x 0.2 -0.3 V
DD
x 0.2 V
Ambient Temperature T
A
-30 85 -30 85 °C
Symbol Description Te s t S e t u p Ty p Max Unit
C
IN1
Address Input Capacitance V
IN
= 0V — 5 pF
C
IN2
Control Input Capacitance V
IN
= 0V — 5 pF
C
IO
Data Input/Output Capacitance V
IO
= 0V — 8 pF
114 CosmoRAM CosmoRAM_00_A0 October 5, 2004
Preliminary
DC Characteristics
(Under Recommended Conditions Unless Otherwise Noted)
Notes:
1. All voltages are referenced to VSS.
2. DC Characteristics are measured after following POWER-UP timing.
3. IOUT depends on the output load conditions.
Parameter Symbol Test Conditions
32M 64M
Unit
Min. Max. Min. Max.
Input Leakage
Current ILI VIN = VSS to VDD -1.0 +1.0 -1.0 +1.0 µA
Output Leakage
Current ILO VOUT = VSS to VDD, Output Disable -1.0 +1.0 -1.0 +1.0 µA
Output High Voltage
Level VOH VDD = VDD(min), IOH = –0.5mA 2.4 — 2.4 — V
Output Low Voltage
Level VOL IOL = 1mA — 0.4 — 0.4 V
VDD Power Down
Current
IDDPS
VDD = VDD max.,
VIN = VIH or VIL,
CE2 ≤ 0.2V
SLEEP — 10 — TBD µA
IDDP4 4M Partial — 40 N/A µA
IDDP8 8M Partial — 50 — TBD µA
IDDP16 16M Partial N/A — TBD
VDD Standby
Current
IDDS
VDD = VDD max.,
VIN (including CLK)= VIH or VIL,
CE1# = CE2 = VIH
—1.5—TBDmA
IDDS1
VDD = VDD max.,
VIN (including CLK) ≤ 0.2V or
VIN (including CLK) ≥ VDD – 0.2V,
CE1# = CE2 ≥ VDD – 0.2V
TA ≤ +85°C — 80 — TBD µA
TA ≤ +40°C — 80 — TBD µA
VDD = VDD max., tCK=min.
VIN ≤ 0.2V or VIN ≥ VDD – 0.2V,
CE1# = CE2 ≥ VDD – 0.2V
— 200 — TBD µA
VDD Active Current
IDDA1 VDD = VDD max.,
VIN = VIH or VIL,
CE1# = VIL and CE2= VIH,
IOUT=0mA
tRC / tWC =
minimum —30—35mA
IDDA2
tRC / tWC =
1µs—3—5mA
VDD Page Read
Current IDDA3
VDD = VDD max., VIN = VIH or VIL,
CE1# = VIL and CE2= VIH,
IOUT=0mA, tPRC = min.
—10—TBDmA
VDD Burst Access
Current IDDA4
VDD = VDD max., VIN = VIH or VIL,
CE1# = VIL and CE2= VIH,
tCK = tCK min., BL = Continuous,
IOUT=0mA
—15—TBDmA
October 5, 2004 CosmoRAM_00_A0 CosmoRAM 115
Preliminary
AC Characteristics
(Under Recommended Operating Conditions Unless Otherwise Noted)
Read Operation
Notes:
1. Maximum value is applicable if CE#1 is kept at Low without change of address input of A3 to A21.
2. Address should not be changed within minimum tRC.
3. The output load 50pF with 50ohm termination to VDD*0.5 V.
Parameter Symbol
32M 64M
Unit NotesMin. Max. Min. Max.
Read Cycle Time t
RC
70 1000 70 1000 ns 1, 2
CE1# Access Time t
CE
—70 —70 ns 3
OE# Access Time t
OE
—40 —40 ns 3
Address Access Time t
AA
—70 —70 ns 3, 5
ADV# Access Time t
AV
70 70 ns 3
LB# / UB# Access Time t
BA
—30 —30 ns 3
Page Address Access Time t
PAA
—20 —20 ns 3,6
Page Read Cycle Time t
PRC
20 1000 20 1000 ns 1, 6, 7
Output Data Hold Time t
OH
5 — 5 — ns 3
CE1# Low to Output Low-Z t
CLZ
5 — 5 — ns 4
OE# Low to Output Low-Z t
OLZ
10 — 0 — ns 4
LB# / UB# Low to Output Low-Z t
BLZ
0 — 0 — ns 4
CE1# High to Output High-Z t
CHZ
—20 —20 ns 3
OE# High to Output High-Z t
OHZ
—20 —20 ns 3
LB# / UB# High to Output High-Z t
BHZ
—20 —20 ns 3
Address Setup Time to CE1# Low t
ASC
–5 —–5 —ns
Address Setup Time to OE# Low t
ASO
10 —10 —ns
ADV# Low Pulse Width t
VPL
10 —10 —ns 8
ADV# High Pulse Width t
VPH
15 —15 —ns 8
Address Setup Time to ADV High t
ASV
5 — 5 — ns
Address Hold Time from ADV# High t
AHV
10 — 5 — ns
Address Invalid Time t
AX
—10 —10 ns 5, 9
Address Hold Time from CE1# High t
CHAH
–5 —–5 —ns 10
Address Hold Time from OE# High t
OHAH
–5 —–5 —ns 10
WE# High to OE# Low Time for Read t
WHOL
15 1000 25 1000 ns 11
CE1# High Pulse Width t
CP
15 —15 —ns
116 CosmoRAM CosmoRAM_00_A0 October 5, 2004
Preliminary
4. The output load 5pF without any other load.
5. Applicable to A3 to A21 when CE1# is kept at Low.
6. Applicable only to A0, A1 and A2 when CE1# is kept at Low for the page address access.
7. In case Page Read Cycle is continued with keeping CE1# stays Low, CE1# must be brought to High within 4µs. In other
words, Page Read Cycle must be closed within 4µs.
8. tVPL is specified from the negative edge of either CE1# or ADV# whichever comes late. The sum of tVPL and tVPH must be
equal or greater than tRC for each access.
9. Applicable to address access when at least two of address inputs are switched from previous state.
10. tRC(min) and tPRC(min) must be satisfied.
11. If actual value of tWHOL is shorter than specified minimum values, the actual tAA of following Read may become longer by the
amount of subtracting actual value from specified minimum value.
October 5, 2004 CosmoRAM_00_A0 CosmoRAM 117
Preliminary
Write Operation
Notes:
1. Maximum value is applicable if CE1# is kept at Low without any address change.
2. Minimum value must be equal or greater than the sum of write pulse (tCW, tWP or tBW) and write recovery time (tWR).
3. Write pulse is defined from High to Low transition of CE1#, WE#, or LB# / UB#, whichever occurs last.
4. tVPL is specified from the negative edge of either CE#1 or ADV# whichever comes late. The sum of tVPL and tVPH must be
equal or greater than tWC for each access.
5. Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1# or WE# whichever
occurs last.
6. Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1# or WE# whichever
occurs first.
7. Write recovery is defined from Low to High transition of CE1#, WE#, or LB# / UB#, whichever occurs first.
8. If OE# is Low after minimum tOHCL, read cycle is initiated. In other words, OE# must be brought to High within 5ns after
CE1# is brought to Low. Once read cycle is initiated, new write pulse should be input after minimum tRC is met.
9. If OE# is Low after new address input, read cycle is initiated. In other word, OE# must be brought to High at the same time
or before new address valid. Once read cycle is initiated, new write pulse should be input after minimum tRC is met and data
bus is in High-Z.
Parameter Symbol
32M 64M
Unit NotesMin. Max. Min. Max.
Write Cycle Time t
WC
70 1000 70 1000 ns 1, 2
Address Setup Time t
AS
0 — 0 — ns 3
ADV# Low Pulse Width t
VPL
10 —10 —ns 4
ADV# High Pulse Width t
VPH
15 —15 —ns
Address Setup Time to ADV# High t
ASV
5 — 5 — ns
Address Hold Time from ADV# High t
AHV
10 — 5 — ns
CE1# Write Pulse Width t
CW
45 —45 —ns 3
WE# Write Pulse Width t
WP
45 —45 —ns 3
LB# / UB# Write Pulse Width t
BW
45 —45 —ns 3
LB# / UB# Byte Mask Setup Time t
BS
-5 —-5 —ns 5
LB# / UB# Byte Mask Hold Time t
BH
-5 —-5 —ns 6
CE1# Write Recovery Time t
WRC
15 —15 —ns 7
Write Recovery Time t
WR
15 1000 15 1000 ns 7
CE1# High Pulse Width t
CP
15 —15 —ns
WE# High Pulse Width t
WHP
15 1000 15 1000 ns
LB# / UB# High Pulse Width t
BHP
15 1000 15 1000 ns
Data Setup Time t
DS
15 —15 —ns
Data Hold Time t
DH
0 — 0 — ns
OE# High to CE1# Low Setup Time for Write t
OHCL
-5 —-5 —ns 8
OE# High to Address Setup Time for Write t
OES
0 — 0 — ns 9
LB# / UB# Write Pulse Overlap t
BWO
30 —30 —ns
118 CosmoRAM CosmoRAM_00_A0 October 5, 2004
Preliminary
Synchronous Operation - Clock Input (Burst Mode)
Notes:
1. Clock period is defined between valid clock edges.
2. Clock rise/fall time is defined between VIH Min. and VIL Max.
Synchronous Operation - Address Latch (Burst Mode)
Notes:
1. tASCL is applicable if CE1# is brought to Low after ADV# is brought to Low.
2. tASVL is applicable if ADV# is brought to Low after CE1# is brought to Low.
3. tVPL is specified from the negative edge of either CE1# or ADV# whichever comes late.
4. Applicable to the 1st valid clock edge.
Parameter Symbol
32M 64M
Unit NotesMin. Max. Min. Max.
Clock Period
RL = 6
t
CK
N/A 13 —ns
1
RL = 5 15 —15 —ns
RL = 4 20 —18 —ns
RL = 3 30 —30 ns
Clock High Time t
CKH
5 — 4 — ns
Clock Low Time t
CKL
5 — 4 — ns
Clock Rise/Fall Time t
CKT
— 3 — 3 ns 2
Parameter Symbol
32M 64M
Unit NotesMin. Max. Min. Max.
Address Setup Time to ADV# Low t
ASVL
-5 —-5 —ns 1
Address Setup Time to CE1# Low t
ASCL
-5 —-5 —ns 2
Address Hold Time from ADV# High t
AHV
10 — 5 — ns
ADV# Low Pulse Width t
VPL
10 —10 —ns 3
ADV# Low Setup Time to CLK
RL = 6, 5
t
VSCK
7
— 5 — ns 4
RL = 4, 3 — 7 — ns 4
CE1 Low Setup Time to CLK
RL = 6, 5
t
CLCK
7
— 5 — ns 4
RL = 4, 3 — 7 — ns 4
ADV# Low Hold Time from CLK t
CKVH
1 — 1 — ns 4
Burst End ADV# High Hold Time from CLK t
VHVL
15 —13 —ns
October 5, 2004 CosmoRAM_00_A0 CosmoRAM 119
Preliminary
Synchronous Read Operation (Burst Mode)
Notes:
1. The output load 50pF with 50ohm termination to VDD*0.5 V.
2. WAIT# drives High at the beginning depending on OE# falling edge timing.
3. tCKTV is guaranteed after tOLTL (max) from OE# falling edge and tOSCK must be satisfied.
4. The output load is 5pF without any other load.
5. Once they are determined, they must not be changed until the end of burst.
6. Defined from the Low to High transition of CE1# to the High to Low transition of either ADV# or CE1# whichever occurs late.
Parameter Symbol
32M 64M
Unit NotesMin. Max. Min. Max.
Burst Read Cycle Time t
RCB
—8000 —4000 ns
CLK Access Time
RL = 6, 5
t
AC
—12
—10 ns 1
RL = 4, 3 —12 ns 1
Output Hold Time from CLK t
CKQX
3 — 3 — ns 1
CE1# Low to WAIT# Low t
CLTL
520 520 ns 1
OE# Low to WAIT# Low t
OLTL
020 020 ns 1, 2
ADV# Low to WAIT# Low t
VLTL
N/A 020 ns 1
CLK to WAIT# Valid Time t
CKTV
—12 —10 ns 1, 3
WAIT# Valid Hold Time from CLK t
CKTX
3 — 3 — ns 1
CE1# Low to Output Low-Z t
CLZ
5 — 5 — ns 4
OE# Low to Output Low-Z t
OLZ
10 —10 —ns 4
LB#, UB# Low to Output Low-Z t
BLZ
0 — 0 — ns 4
CE1# High to Output High-Z t
CHZ
—14 —20 ns 1
OE# High to Output High-Z t
OHZ
—14 —20 ns 1
LB#, UB# High to Output High-Z t
BHZ
—14 —20 ns 1
CE1# High to WAIT High-Z t
CHTZ
—20 —20 ns 1
OE# High to WAIT High-Z t
OHTZ
—20 —20 ns 1
OE# Low Setup Time to 1st Data-out t
OLQ
30 —30 —ns
UB#, LB# Setup Time to 1st Data-out t
BLQ
30 —26 —ns 5
OE# Setup Time to CLK t
OSCK
5 — 5 — ns
OE# Hold Time from CLK t
CKOH
5 — 5 — ns
Burst End CE1# Low Hold Time from CLK t
CKCLH
5 — 5 — ns
Burst End UB#, LB# Hold Time from CLK t
CKBH
5 — 5 — ns
Burst Terminate Recovery Time
BL=8, 16
t
TRB
30 —26 —ns 6
BL=Continuous 70 —70 —ns 6
120 CosmoRAM CosmoRAM_00_A0 October 5, 2004
Preliminary
Synchronous Write Operation (Burst Mode)
Notes:
1. Defined from the valid input edge to the High to Low transition of either ADV#, CE1#, or WE#, whichever occurs last. And
once they are determined, they must not be changed until the end of burst.
2. The output load 50pF with 50ohm termination to VDD*0.5 V.
3. Defined from the valid clock edge where last data-in being latched at the end of burst write to the High to Low transition of
either ADV# or CE1# whichever occurs late for the next access.
4. Defined from the Low to High transition of CE1# to the High to Low transition of either ADV# or CE1# whichever occurs late
for the next access.
Parameter Symbol
32M 64M
Unit NotesMin. Max. Min. Max.
Burst Write Cycle Time t
WCB
—8000 —4000 ns
Data Setup Time to Clock t
DSCK
7 — 5 — ns
Data Hold Time from CLK t
DHCK
3 — 3 — ns
WE# Low Setup Time to 1st Data In t
WLD
30 —30 —ns
UB#, LB# Setup Time for Write t
BS
-5 —-5 —ns 1
WE# Setup Time to CLK t
WSCK
5 — 5 — ns
WE# Hold Time from CLK t
CKWH
5 — 5 — ns
CE1# Low to WAIT# High t
CLTH
520 520 ns 2
WE# Low to WAIT# High t
WLTH
020 020 ns 2
CE1# High to WAIT# High-Z t
CHTZ
—20 —20 ns 2
WE# High to WAIT# High-Z t
WHTZ
—20 —20 ns 2
Burst End CE1# Low Hold Time from CLK t
CKCLH
5 — 5 — ns
Burst End CE1# High Setup Time to next CLK t
CHCK
5 — 5 — ns
Burst End UB#, LB# Hold Time from CLK t
CKBH
5 — 5 — ns
Burst Write Recovery Time t
WRB
30 26 ns
Burst Terminate Recovery Time
BL=8, 16 t
TRB
30 —26 —ns 3
BL=Continuous t
TRB
70 —70 —ns 4
October 5, 2004 CosmoRAM_00_A0 CosmoRAM 121
Preliminary
Power Down Parameters
Notes:
1. Applicable when RP=0 (Reset to Page mode). RP (Reset to Page) mode is available only for 64M.
2. Applicable also to power-up.
3. Applicable when Partial mode is set.
Other Timing Parameters
Notes:
1. Some data might be written into any address location if tCHWX(min) is not satisfied.
2. Except for clock input transition time.
3. The Input Transition Time (tT) at AC testing is 5ns for Asynchronous operation and 3ns for Synchronous operation
respectively. If actual tT is longer than 5ns or 3ns specified as AC test condition, it may violate AC specification of some
timing parameters. See the "AC Test Conditions" section
AC Test Conditions
Parameter Symbol
32M 64M
Unit NotesMin. Max. Min. Max.
CE2 Low Setup Time for Power Down Entry t
CSP
20 —10 —ns
CE2 Low Hold Time after Power Down Entry t
C2LP
70 —70 —ns
CE2 Low Hold Time for Reset to Asynchronous Mode t
C2LPR
N/A 50 —µs 1
CE1# High Hold Time following CE2 High after Power
Down Exit [SLEEP mode only] t
CHH
300 —300 —µs 2
CE1# High Hold Time following CE2 High after Power
Down Exit [not in SLEEP mode] t
CHHP
70 —70 —µs 3
CE1# High Setup Time following CE2 High after Power
Down Exit t
CHS
0 — 0 — ns 2
Parameter Symbol
32M 64M
Unit NotesMin. Max. Min. Max.
CE1 High to OE Invalid Time for Standby Entry t
CHOX
10 —10 —ns
CE1 High to WE Invalid Time for Standby Entry t
CHWX
10 —10 —ns 1
CE2 Low Hold Time after Power-up t
C2LH
50 —50 —µs
CE1 High Hold Time following CE2 High after Power-up t
CHH
300 —300 —µs
Input Transition Time t
T
125 125 ns 2
Symbol Description Te s t S e t u p Value Unit Note
V
IH
Input High Level V
DD
* 0.8 V
V
IL
Input Low Level V
DD
* 0.2 V
V
REF
Input Timing Measurement Level V
DD
* 0.5 V
t
T
Input Transition Time
Async.
Between V
IL
and V
IH
5ns
Sync. 3ns
122 CosmoRAM CosmoRAM_00_A0 October 5, 2004
Preliminary
AC Measurement Output Load Circuit
Figure 11.18. Output Load Circuit
DEVICE
UNDER
TEST
VDD
VDD*0.5V
VSS
OUT
0.1µF
50pF
50ohm
October 5, 2004 CosmoRAM_00_A0 CosmoRAM 123
Preliminary
Timing Diagrams
Note: This timing diagram assumes CE2=H and WE#=H.
Note: This timing diagram assumes CE2=H and WE#=H.
Figure 11.19. Asynchronous Read Timing #1-1 (Basic Timing)
Figure 11.20. Asynchronous Read Timing #1-2 (Basic Timing)
tCE
VALID DATA OUTPUT
ADDRESS
CE1#
DQ
(Output)
OE#
tCHZ
tRC
tOLZ
tCHAH
tCP
ADDRESS VALID
tASCtASC
tOHZ
tOH
tBHZ
tOE
tBA
tBLZ
ADV# Low
LB# / UB#
tCE
VALID DATA OUTPUT
ADDRESS
CE1#
DQ
(Output)
OE#
tCHZ
tRC
tOLZ
tCP
tASCtASC
tOHZ
tOH
tBHZ
tOE
tBA
tBLZ
ADV#
ADDRESS VALID
tAHV
tVPL
tAV
LB# / UB#
124 CosmoRAM CosmoRAM_00_A0 October 5, 2004
Preliminary
Note: This timing diagram assumes CE2=H, ADV#=L and WE#=H.
Note: This timing diagram assumes CE2=H, ADV#=L and WE#=H.
Figure 11.21. Asynchronous Read Timing #2 (OE# & Address Access)
Figure 11.22. Asynchronous Read Timing #3 (LB# / UB# Byte Access)
tAA
VALID DATA OUTPUT
ADDRESS
CE1#
DQ
(Output)
tOHZ
tOE
tRC
tOLZ
ADDRESS VALID
VALID DATA OUTPUT
ADDRESS VALID
tRC
tOH
tOH
OE#
tAX
Low
tAA tOHAH
tASO
LB# / UB#
tAA
VALID DATA
OUTPUT
ADDRESS
DQ1-8
(Output)
UB# tBHZ
tBA
tRC
tBLZ
ADDRESS VALID
VALID DATA
OUTPUT
tBHZ
tOH
LB#
tAX
Low
tBA
tAX
DQ9-16
(Output)
tBLZ
tBA
tBLZ tOH
tBHZ
tOH
VALID DATA OUTPUT
CE1#, OE#
October 5, 2004 CosmoRAM_00_A0 CosmoRAM 125
Preliminary
Note: This timing diagram assumes CE2=H and WE#=H.
Notes:
1. This timing diagram assumes CE2=H, ADV#=L and WE#=H.
2. Either or both LB# and UB# must be Low when both CE1# and OE# are Low.
Figure 11.23. Asynchronous Read Timing #4 (Page Address Access after CE1# Control Access)
Figure 11.24. Asynchronous Read Timing #5 (Random and Page Address
Access)
VALID DATA OUTPUT
(Normal Access)
ADDRESS
(A2-A0)
CE1#
DQ
(Output)
OE#
tCHZ
tCE
tRC
tCLZ
ADDRESS VALID
VALID DATA OUTPUT
(Page Access)
ADDRESS
VALID
tPRC
tOH tOH
tCHAH
tPAA
ADDRESS
(A21-A3) ADDRESS VALID
tPAA
tOH
tPRC
tPAA
tPRC
tOH
ADDRESS
VALID ADDRESS
VALID
tRC
ADV#
tASC
LB# / UB#
VALID DATA OUTPUT
(Normal Access)
ADDRESS
(A2-A0)
CE1#
DQ
(Output)
OE#
tOE
tRC
tOLZ
tBLZ
tAA
VALID DATA OUTPUT
(Page Access)
ADDRESS
VALID
tPRC
tOH tOH
tRC
tPAA
ADDRESS
(A21-A3) ADDRESS VALID
tAA
tOH
ADDRESS VALID
tRC
tPAA
tPRC
tOH
ADDRESS
VALID ADDRESS
VALID
tRC
tAXtAX
tBA
ADDRESS
VALID
Low
tASO
LB# / UB#
126 CosmoRAM CosmoRAM_00_A0 October 5, 2004
Preliminary
Note: This timing diagram assumes CE2=H and ADV#=L.
Note: This timing diagram assumes CE2=H.
Figure 11.25. Asynchronous Write Timing #1-1 (Basic Timing)
Figure 11.26. Asynchronous Write Timing #1-2 (Basic Timing)
tAS
VALID DATA INPUT
ADDRESS
CE1#
DQ
(Input)
WE#
tDHtDS
tWC
tWRC
tWP
tCW
tAStBW
ADDRESS VALID
tAS
tAS
tBR
OE#
tOHCL
tAS
tAS
tWR
ADV# Low
LB#, UB#
tAS
VALID DATA INPUT
A
DDRESS
CE1#
DQ
(Input)
WE#
tDHtDS
tWC
tWRC
tWP
tCW
tAStBW
ADDRESS VALID
tAS
tAS
tBR
OE#
tOHCL
tAS
tAS
tWR
ADV# tVPL tAHV
LB#, UB#
October 5, 2004 CosmoRAM_00_A0 CosmoRAM 127
Preliminary
Note: This timing diagram assumes CE2=H and ADV#=L.
Note: This timing diagram assumes CE2=H, ADV#=L and OE#=H.
Figure 11.27. Asynchronous Write Timing #2 (WE# Control)
Figure 11.28. Asynchronous Write Timing #3-1 (WE# / LB# / UB# Byte Write Control)
tAS
ADDRESS
WE#
CE1#
tWC
tWRtWP
ADDRESS VALID
tAS tWRtWP
VALID DATA INPUT
DQ
(Input)
tDHtDS
OE#
tOES
tOHZ
tWC
VALID DATA INPUT
tDHtDS
Low
ADDRESS VALID
tOHAH
UB#, LB#
tAS
A
DDRESS
WE#
CE1#
tWC
tBR
tWP
LB#
ADDRESS VALID
tAS
tBR
tWP
VALID DATA INPUT
DQ1-8
(Input)
tDHtDS
UB#
tWC
VALID DATA INPUT
tDHtDS
Low
ADDRESS VALID
DQ9-16
(Input)
tBS tBH
tBS
tBH
128 CosmoRAM CosmoRAM_00_A0 October 5, 2004
Preliminary
Note: This timing diagram assumes CE2=H, ADV#=L and OE#=H.
Note: This timing diagram assumes CE2=H, ADV#=L and OE#=H.
Figure 11.29. Asynchronous Write Timing #3-2 (WE# / LB# / UB# Byte Write Control)
Figure 11.30. Asynchronous Write Timing #3-3 (WE# / LB# / UB# Byte Write Control)
tAS
A
DDRESS
WE#
CE1#
tWC
tWR
tBW
LB#
ADDRESS VALID
tAS
tWR
tBW
VALID DATA INPUT
DQ1-8
(Input)
tDHtDS
UB#
tWC
VALID DATA INPUT
tDHtDS
Low
ADDRESS VALID
DQ9-16
(Input)
tBS tBH
tBS tBH
tAS
A
DDRESS
WE#
CE1#
tWC
tBRtBW
LB#
ADDRESS VALID
tAS tBRtBW
VALID DATA INPUT
DQ1-8
(Input)
tDHtDS
UB#
tWC
VALID DATA INPUT
tDHtDS
Low
ADDRESS VALID
DQ9-16
(Input)
tBS tBH
tBS tBH
October 5, 2004 CosmoRAM_00_A0 CosmoRAM 129
Preliminary
Note: This timing diagram assumes CE2=H, ADV#=L and OE#=H.
Notes:
1. This timing diagram assumes CE2=H and ADV#=L.
2. Write address is valid from either CE1# or WE# of last falling edge.
Figure 11.31. Asynchronous Write Timing #3-4 (WE# / LB# / UB# Byte Write Control)
Figure 11.32. Asynchronous Read / Write Timing #1-1 (CE1# Control)
tAS
A
DDRESS
WE#
CE1#
tWC
tBRtBW
LB#
ADDRESS VALID
tAS tBR
tBW
DQ1-8
(Input)
tDH
tDS
UB#
tWC
tDHtDS
Low
ADDRESS VALID
DQ9-16
(Input)
tDHtDS
tAS tBRtBW
tAS tBRtBW
tDHtDS
VALID
DATA INPUT VALID
DATA INPUT
VALID
DATA INPUT VALID
DATA INPUT
tBWO
tBWO
READ DATA OUTPUT
ADDRESS
CE1#
DQ
WE#
tWC
tCW
OE#
tOHCL
tCHAH
tCP
WRITE ADDRESS
tAS
tRC
WRITE DATA INPUT
tDS
tCHZ
tOH
tCP
tCEtASC
READ ADDRESS
tWRC tCHAH
tDH tCLZ tOH
UB#, LB#
130 CosmoRAM CosmoRAM_00_A0 October 5, 2004
Preliminary
Notes:
1. This timing diagram assumes CE2=H and ADV#=L.
2. OE# can be fixed Low during write operation if it is CE1# controlled write at Read-Write-Read Sequence.
Notes:
1. This timing diagram assumes CE2=H and ADV#=L.
2. CE1# can be tied to Low for WE# and OE# controlled operation.
Figure 11.33. Asynchronous Read / Write Timing #1-2 (CE1# / WE# / OE# Control)
Figure 11.34. Asynchronous Read / Write Timing #2 (OE#, WE# Control)
READ DATA OUTPUT
ADDRESS
CE1#
DQ
WE#
tWC
tWP
OE
tOHCL tOE
tCHAH
tCP
WRITE ADDRESS
tAS
tRC
WRITE DATA INPUT
tDS
tCHZ
tOH
tCP
tCEtASC
READ ADDRESS
tWR tCHAH
tDH tOLZ tOH
READ DATA OUTPUT
UB#, LB#
READ DATA OUTPUT
ADDRESS
CE1#
DQ
WE#
tWC
tWP
OE#
tOE
WRITE ADDRESS
tAS
tRC
WRITE DATA INPUT
tDS
tOHZ
tOH
tAA
READ ADDRESS
tWR
tDH tOLZ tOH
READ DATA OUTPUT
tOHZ
Low
tASO
tOHAH
tOES
tOHAH
UB#, LB#
October 5, 2004 CosmoRAM_00_A0 CosmoRAM 131
Preliminary
Notes:
1. This timing diagram assumes CE2=H and ADV#=L.
2. CE1# can be tied to Low for WE# and OE# controlled operation.
Notes:
1. Stable clock input must be required during CE1#=L.
2. tCK is defined between valid clock edges.
3. tCKT is defined between VIH Min. and VIL Max
Figure 11.35. Asynchronous Read / Write Timing #3 (OE,# WE#, LB#, UB# Control)
Figure 11.36. Clock Input Timing
READ DATA OUTPUT
A
DDRESS
CE1#
DQ
WE#
tWC
tBW
OE#
tBA
WRITE ADDRESS
tAS
tRC
WRITE DATA INPUT
tDS
tBHZ
tOH
tAA
READ ADDRESS
tBR
tDH tBLZ tOH
READ DATA OUTPUT
tBHZ
Low
tASO
tOHAHtOHAH
tOES
UB#, LB#
CLK
tCK tCKH tCKL tCKT tCKT
tCK
132 CosmoRAM CosmoRAM_00_A0 October 5, 2004
Preliminary
Notes:
1. Case #1 is the timing when CE1# is brought to Low after ADV# is brought to Low. Case #2 is the timing when ADV# is
brought to Low after CE1# is brought to Low.
2. tVPL is specified from the negative edge of either CE1# or ADV# whichever comes late. At least one valid clock edge must be
input during ADV#=L.
3. tVSCK and tCLCK are applied to the 1st valid clock edge during ADV#=L.
Figure 11.37. Address Latch Timing (Synchronous Mode)
CLK
ADV#
A
DDRESS
CE1#
tAHV
tVPL
tASVL
Valid
Case #1 Case #2
tVSCKtAHV
tVPL
tVLCL
Valid
tVSCK
tCLCK
tASCL
Low
tCKVHtCKVH
October 5, 2004 CosmoRAM_00_A0 CosmoRAM 133
Preliminary
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
Figure 11.38. 32M Synchronous Read Timing #1 (OE# Control)
ADV#
DQ
WE#
OE#
Valid
tASVL tAHV
tVPL
tCLCK
tASCL
WAIT#
Q1
tOLQ
tAC
tCKQX
tOLTL tAC
tCKTV
High
QBL
High-Z
RL=5
tVSCK
tOHTZ
tOLZ
tAC
tCKQX
tOHZ
tRCB
tCKOH
tCKTV
Valid
tVSCK
tCLCK
tCP
tVPL
tVHVL
High-Z
tBLQ
tCKBH
tASCL
tASVL
tCKTX tCKTX
tCKVH
tCKVH
CE1#
LB#, UB#
ADDRESS
CLK
134 CosmoRAM CosmoRAM_00_A0 October 5, 2004
Preliminary
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
Figure 11.39. 32M Synchronous Read Timing #2 (CE1# Control)
ADDRESS
ADV#
DQ
WE#
OE#
LB#, UB#
CLK
Valid
CE1#
tASVL tAHV
tVPL
tCLCK
tASCL
WAIT#
Q1
tAC
tCKQX
tAC
tCKTV
RL=5
tVSCK
tAC
tRCB
Valid
tVSCK
tCLCK
tCP
tVPL
tVHVL
tCLTL
High
tCLZ
tCKCLH
tASCL
tAHV
QBL
tCHTZ
tCLZ
tCKQX
tCHZ
tCKTV
tCLTL
tCKBH
tASVL
tCKTX tCKTX
tCKVH tCKVH
October 5, 2004 CosmoRAM_00_A0 CosmoRAM 135
Preliminary
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
Figure 11.40. 32M Synchronous Read Timing #3 (ADV# Control)
ADDRESS
ADV#
DQ
WE#
OE#
LB#, UB#
CLK
Valid
CE1#
tASVL tAHV
tVPL
WAIT#
Q1
tAC
tCKQX
tAC
tCKTV
RL=5
tVSCK
tAC
tRCB
Valid
tASVL
tVSCK
tVPL
tVHVL
High
tAHV
QBL
tCKQX
tCKTV
Low
Low
tCKTX tCKTX
tCKVH tCKVH
136 CosmoRAM CosmoRAM_00_A0 October 5, 2004
Preliminary
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
Figure 11.41. Synchronous Read - WAIT# Output Timing (Continuous Read)
XXX7Fh
tASVL tAHV
tVPL
tCLCK
tASCL
Q1
tOLQ
tAC
tCKQX
tOLTL tAC
tCKTV
High
High-Z
RL=5
tVSCK
tOLZ
tCKTV
High-Z Q2
tCKQX
Q3
tCKQX
tAC tAC
tCKTV
tAC
tBLQ
tCKTX
tCKTX
tCKTX
tCKVH
CLK
ADDRESS
ADV#
CE1#
OE#
WE#
LB#, UB#
WAIT#
DQ
October 5, 2004 CosmoRAM_00_A0 CosmoRAM 137
Preliminary
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
Figure 11.42. 64M Synchronous Read Timing #1 (OE# Control)
tAHV
ADDRESS
ADV#
DQ
WE#
OE#
CLK
Valid
CE1#
tASVL
tVPL
tCLCK
tASCL
WAIT#
Q1
tOLQ
tAC
tCKQX
tOLTL tAC
tCKTV
High
QBL
High-Z
RL=5
tVSCK
tOHTZ
tOLZ
tAC
tCKQX
tOHZ
tRCB
tCKOH
Valid
tVSCK
tCLCK
tCP
tVPL
tVHVL
High-Z
tBLQ
tCKBH
tASCL
tASVL
tCKTX
tCKVH
tCKVH
LB#, UB#
138 CosmoRAM CosmoRAM_00_A0 October 5, 2004
Preliminary
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
Figure 11.43. 64M Synchronous Read Timing #2 (CE1# Control)
ADDRESS
ADV#
DQ
WE#
OE#
CLK
Valid
CE1#
tASVL tAHV
tVPL
tCLCK
tASCL
WAIT#
Q1
tAC
tCKQX
tAC
tCKTV
RL=5
tVSCK
tAC
tRCB
Valid
tVSCK
tCLCK
tCP
tVPL
tVHVL
tCLTL
High
tCLZ
tCKCLH
tASCL
tAHV
QBL
tCHTZ
tCLZ
tCKQX
tCHZ
tCLTL
tCKBH
tASVL
tCKTX
tCKVH tCKVH
LB#, UB#
October 5, 2004 CosmoRAM_00_A0 CosmoRAM 139
Preliminary
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
Figure 11.44. 64M Synchronous Read Timing #3 (ADV# Control)
ADDRESS
ADV#
DQ
WE#
OE#
LB#, UB#
CLK
Valid
CE1#
tASVL tAHV
tVPL
WAIT#
Q1
tAC
tCKQX
tAC
tCKTV
RL=5
tVSCK
tAC
tRCB
Valid
tASVL
tVSCK
tVPL
tVHVL
High
tAHV
QBL
tCKQX
Low
Low
tCKTX
tVLTLtVLTL
tCKVH tCKVH
140 CosmoRAM CosmoRAM_00_A0 October 5, 2004
Preliminary
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
Figure 11.45. Synchronous Write Timing #1 (WE# Level Control)
ADDRESS
ADV#
DQ
WE#
OE#
CLK
Valid
CE1#
tASVL tAHV
tVPL
tCLCK
tASCL
WAIT#
High
High-Z
RL=5
tBS
D1D2
tDHCK
DBL
tDSCK
tDHCK
tDSCK tDSCK
tWCB
tCKWH
tWLD
Valid
tAHV
tVPL
tCLCK
tASCL
tVSCK
tBS
tCP
tWRB
tVSCK
tVHVL
tCKBH
tWLTH tWHTZ
tCKVH tCKVH
tASVL
LB#, UB#
October 5, 2004 CosmoRAM_00_A0 CosmoRAM 141
Preliminary
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
Figure 11.46. Synchronous Write Timing #2 (WE# Single Clock Pulse
Control)
ADDRESS
ADV#
DQ
WE#
OE#
CLK
Valid
CE1#
tASVL tAHV
tVPL
tCLCK
tASCL
WAIT#
High
High-Z
RL=5
tBS
D1D2
tDHCK
DBL
tDSCK
tDHCK
tDSCK tDSCK
tWCB
tCKCLH
Valid
tASVL tAHV
tVPL
tCLCK
tASCL
tVSCK
tBS
tCP
tWRB
tVSCK
tVHVL
tCKBH
tWLTH tCHTZ tWLTH
tWSCK tCKWH tCKWHtWSCK
tCKVH tCKVH
LB#, UB#
142 CosmoRAM CosmoRAM_00_A0 October 5, 2004
Preliminary
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
Figure 11.47. Synchronous Write Timing #3 (ADV# Control)
ADDRESS
ADV#
DQ
WE#
OE#
CLK
Valid
CE1#
tASVL tAHV
tVPL
WAIT#
High
RL=5
tBS
D1D2
tDHCK
DBL
tDSCK
tDHCK
tDSCK tDSCK
tWCB
Valid
tASVL tAHV
tVPL
tVSCK
tBS
tWRB
tVSCK
tVHVL
tCKBH
High
tCKVH tCKVH
LB#, UB#
October 5, 2004 CosmoRAM_00_A0 CosmoRAM 143
Preliminary
Notes:
1. This timing diagram assumes CE2=H, the valid clock edge on rising edge and single write operation.
2. Write data is latched on the valid clock edge.
Figure 11.48. Synchronous Write Timing #4 (WE# Level Control, Single
Write)
ADDRESS
ADV#
DQ
WE#
OE#
CLK
Valid
CE1#
tASVL tAHV
tVPL
tCLCK
tASCL
WAIT#
High
High-Z
RL=5
tBS
D1
tDHCK
tDSCK
tWCB
tCKWH
tWLD
Valid
tAHV
tVPL
tCLCKtASCL
tVSCK
tBS
tCP
tWRB
tVSCK
tVHVL
tCKBH
tWLTH tWHTZ tWLTH
tCKVH tCKVH
tASVL
LB#, UB#
144 CosmoRAM CosmoRAM_00_A0 October 5, 2004
Preliminary
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
Figure 11.49. 32M Synchronous Read to Write Timing #1(CE1# Control)
ADDRESS
ADV#
DQ
WE#
OE#
CLK
Valid
CE1#
tASVL tAHV
tVPL
tCLCK
tASCL
WAIT#
tVSCK
tBS
tCP
RL=5
D1D2
tDHCK tDHCK
tDSCK tDSCK
DBL
tDHCK
tDSCK
D3
tDSCK
tDHCK
QBL-1 QBL
tCHTZ
tAC
tCKQX
tCHZ
tCKQX
tCKCLH
tCKCLH
tCKTV
tVHVL
tCKBHtCKBH
tCKTX
tWCB
tCKVH
tCLTH
LB#, UB#
October 5, 2004 CosmoRAM_00_A0 CosmoRAM 145
Preliminary
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
Figure 11.50. 32M Synchronous Read to Write Timing #2(ADV# Control)
ADDRESS
ADV#
DQ
WE#
OE#
CLK
Valid
CE1#
tASVL tAHV
tVPL
WAIT#
tVSCK
tBS
RL=5
tCKWH
D1D2
tDHCK tDHCK
tDSCK tDSCK
DBL
tDHCK
tDSCK
D3
tDSCK
tDHCK
QBL-1 QBL
tOHTZ
tAC
tCKQX
tOHZ
tCKQX
tWLD
tCKOH
tCKTV
tVHVL
tCKBHtCKBH
tCKTX
tCKVH
tWLTH
LB#, UB#
146 CosmoRAM CosmoRAM_00_A0 October 5, 2004
Preliminary
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
Figure 11.51. 64M Synchronous Read to Write Timing #1(CE1# Control)
ADDRESS
ADV#
DQ
WE#
OE#
LB#, UB#
CLK
Valid
CE1#
tASVL tAHV
tVPL
tCLCK
tASCL
WAIT#
tVSCK
tBS
tCP
RL=5
D1D2
tDHCK tDHCK
tDSCK tDSCK
DBL
tDHCK
tDSCK
D3
tDSCK
tDHCK
QBL-1 QBL
tCHTZ
tAC
tCKQX
tCHZ
tCKQX
tCKCLH
tCKCLH
tVHVL
tCKBHtCKBH
tWCB
tCLTH
tCKVH
October 5, 2004 CosmoRAM_00_A0 CosmoRAM 147
Preliminary
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
Figure 11.52. 64M Synchronous Read to Write Timing #2(ADV# Control)
ADDRESS
ADV#
DQ
WE#
OE#
LB#, UB#
CLK
Valid
CE1#
tASVL tAHV
tVPL
WAIT#
tBS
RL=5
tCKWH
D1D2
tDHCK tDHCK
tDSCK tDSCK
DBL
tDHCK
tDSCK
D3
tDSCK
tDHCK
QBL-1 QBL
tOHTZ
tAC
tCKQX
tOHZ
tCKQX
tWLD
tCKOH
tVHVL
tCKBHtCKBH
tWLTH
tCKVH
tVSCK
148 CosmoRAM CosmoRAM_00_A0 October 5, 2004
Preliminary
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
Figure 11.53. Synchronous Write to Read Timing #1 (CE1# Control)
DBL
ADDRESS
ADV#
DQ
WE#
OE#
CLK
Valid
CE1#
tASVL tAHV
tVPL
tCKT
tCLCK
tASCL
WAIT#
tVSCK
tCP
RL=5
tCKCLH
DBL-1
tDHCKtDHCK
tDSCKtDSCK
Q1Q2
tAC
tCKQX
tAC
tCKQX
tCKTV
tCLTL
tCLZ
tWRB
tCKBH
tCKTX
tCKVH
tCHTZ
High-Z
LB#, UB#
October 5, 2004 CosmoRAM_00_A0 CosmoRAM 149
Preliminary
Note: This timing diagram assumes CE2=H, the valid clock edge on rising edge and BL=8 or 16.
Figure 11.54. Synchronous Write to Read Timing #2 (ADV# Control)
DBL
ADDRESS
ADV#
DQ
WE#
OE#
CLK
Valid
CE1#
tASVL tAHV
tVPL
tCKT
WAIT#
Low
tVSCK
RL=5
tCKWH
DBL-1
tDHCKtDHCK
tDSCKtDSCK
Q1Q2
tAC
tCKQX
tAC
tCKQX
tCKTV
tOLTL
tOLZ
tOLQ
tWRB
tBLQ
tCKBH
tCKTX
tCKVH
tWHTZ
High-Z
LB#, UB#
150 CosmoRAM CosmoRAM_00_A0 October 5, 2004
Preliminary
Note: The tC2LH specifies after VDD reaches specified minimum level.
Note: The tCHH specifies after VDD reaches specified minimum level and applicable to both CE1# and CE2.
Note: This Power Down mode can be also used as a reset timing if the POWER-UP timing above could not be satisfied
and Power-Down program was not performed prior to this reset.
Figure 11.55. Power-up Timing #1
Figure 11.56. Power-up Timing #2
Figure 11.57. Power Down Entry and Exit Timing
tC2LH
CE1#
V
DD
V
DD
min
0V
CE2
tCHH
tCHS
CE1#
VDD VDD min
0V
CE2
tCHH
t
CSP
CE1#
Power Down Entry
CE2
t
C2LP
t
CHH
(t
CHHP
)
Power Down Mode Power Down Exit
t
CHS
DQ High-Z
October 5, 2004 CosmoRAM_00_A0 CosmoRAM 151
Preliminary
Note: Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes
tRC (min) period for Standby mode from CE1# Low to High transition.
Notes:
1. The all address inputs must be High from Cycle #1 to #5.
2. The address key must confirm the format specified in the "Functional Description" section. If not, the operation and data are
not guaranteed.
3. After tCP or tRC following Cycle #6, the Configuration Register Set is completed and returned to the normal operation. tCP and
tRC are applicable to returning to asynchronous mode and to synchronous mode respectively.
4. Byte read or write is available in addition to Word read or write. At least one byte control signal (LB# or UB#) need to be
Low.
Figure 11.58. Standby Entry Timing after Read or Write
Figure 11.59. Configuration Register Set Timing #1 (Asynchronous Operation)
t
CHOX
CE1#
OE#
WE#
Active (Read) Standby Active (Write) Standby
t
CHWX
ADDRESS
CE1#
DQ*3
WE#
tRC
OE#
RDa
MSB*1MSB*1MSB*1MSB*1MSB*1Key*2
tWC tWC tWC tWC tRC
tCP tCP tCP tCP tCP
Cycle #1 Cycle #2 Cycle #3 Cycle #4 Cycle #5 Cycle #6
RDa RDa X X RDb
tCP*3
(tRC)
LB#, UB#
152 CosmoRAM CosmoRAM_00_A0 October 5, 2004
Preliminary
Notes:
1. The all address inputs must be High from Cycle #1 to #5.
2. The address key must confirm the format specified in the "Functional Description" section. If not, the operation and data are
not guaranteed.
3. After tTRB following Cycle #6, the Configuration Register Set is completed and returned to the normal operation.
4. Byte read or write is available in addition to Word read or write. At least one byte control signal (LB# or UB#) need to be
Low.
Figure 11.60. Configuration Register Set Timing #2 (Synchronous Operation)
ADDRESS
ADV#
DQ
WE#
OE#
CLK
CE1#
WAIT#
RDa
MSB
RDa
MSB
RDa
MSB
X
MSB
X
MSB
RDb
Key
tRCB tWCB tWCB tWCB tWCB tRCB
tTRB tTRB tTRB tTRB tTRB
Cycle#1 Cycle#2 Cycle#3 Cycle#4 Cycle#5 Cycle#6
tTRB
RL RL-1 RL-1 RL-1 RL-1 RL
LB#, UB#
November 8, 2004 S71WS512/256Nx0_CS S71WS512Nx0/S71WS256Nx0 153
Preliminary
Revision Summary
Revision A0 (November 8, 2004)
Initial release.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and
artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-men-
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The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by
Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
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