BUK9230-100B/T3 - NXP Semiconductors / Philips Semiconductors

BUK9230-100B

TrenchMOS™ logic level FET

Rev. 01 — 22 January 2004 Product data

M3D300

1. Product proﬁle

1.1 Description

N-channel enhancement mode ﬁeld-effect power transistor in a plastic package using

Philips High-Performance Automotive (HPA) TrenchMOS™ technology.

1.2 Features

1.3 Applications

1.4 Quick reference data

2. Pinning information

[1] It is not possible to make connection to pin 2 of the SOT428 package.

■Very low on-state resistance ■Q101 compliant

■185 °C rated ■Logic level compatible.

■Automotive systems ■12 V, 24 V, and 42 V loads

■Motors, lamps and solenoids ■General purpose power switching.

■EDS(AL)S ≤150 mJ ■RDSon =25mΩ(typ)

■ID≤47 A ■Ptot ≤167 W.

Table 1: Pinning - SOT428 (D-PAK), simpliﬁed outline and symbol

Pin Description Simpliﬁed outline Symbol

1 gate (g)

SOT428 (D-PAK)

2 drain (d) [1]

3 source (s)

mb mounting base;

connected to

drain (d)

MBK091

Top view

MBB076

Philips Semiconductors BUK9230-100B

TrenchMOS™ logic level FET

Product data Rev. 01 — 22 January 2004 2 of 12

3. Ordering information

4. Limiting values

Table 2: Ordering information

Type number Package

Name Description Version

BUK9230-100B D-PAK Plastic single-ended surface mounted package (Philips version of D-PAK);

3 leads (one lead cropped). SOT428

Table 3: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDS drain-source voltage (DC) - 100 V

VDGR drain-gate voltage (DC) RGS =20kΩ- 100 V

VGS gate-source voltage (DC) - ±15 V

IDdrain current (DC) Tmb =25°C; VGS =5V;

Figure 2 and 3-47A

Tmb = 100 °C; VGS =5V;Figure 2 -33A

IDM peak drain current Tmb =25°C; pulsed; tp≤10 µs;

Figure 3 - 185 A

Ptot total power dissipation Tmb =25°C; Figure 1 - 167 W

Tstg storage temperature −55 +185 °C

Tjjunction temperature −55 +185 °C

Source-drain diode

IDR reverse drain current (DC) Tmb =25°C - 47 A

IDRM peak reverse drain current Tmb =25°C; pulsed; tp≤10 µs - 185 A

Avalanche ruggedness

EDS(AL)S non-repetitive drain-source

avalanche energy unclampedinductiveload;ID=47A;

VDS ≤100 V; VGS =5V;

RGS =50Ω; starting Tj=25°C

- 150 mJ

Philips Semiconductors BUK9230-100B

TrenchMOS™ logic level FET

Product data Rev. 01 — 22 January 2004 3 of 12

VGS ≥5V

Fig 1. Normalized total power dissipation as a

function of mounting base temperature. Fig 2. Continuous drain current as a function of

mounting base temperature.

Tmb =25°C; IDM single pulse.

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.

03no96

120

0 50 100 150 200

Tmb (°C)

Pder

(%)

03no40

0 50 100 150 200

(A)

Tmb (°C)

Pder Ptot

Ptot 25 C

()

----------------------- 100%×=

03no39

102

103

1 10 102 103

VDS (V)

(A)

100 ms

10 ms

Limit RDSon = VDS / ID

1 ms

tp = 10 µs

100 µs

Philips Semiconductors BUK9230-100B

TrenchMOS™ logic level FET

Product data Rev. 01 — 22 January 2004 4 of 12

5. Thermal characteristics

5.1 Transient thermal impedance

Table 4: Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

Rth(j-a) thermal resistance from junction to

ambient - 71.4 - K/W

Rth(j-mb) thermal resistance from junction to

mounting base Figure 4 - - 0.95 K/W

Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.

03nk52

singl e shot

0.2

0.1

0.05

0.02

10-3

10-2

10-1

10-6 10-5 10-4 10-3 10-2 10-1 1

tp (s)

Zth(j-mb)

(K/W)

δ = 0.5

δ =

Philips Semiconductors BUK9230-100B

TrenchMOS™ logic level FET

Product data Rev. 01 — 22 January 2004 5 of 12

6. Characteristics

Table 5: Characteristics

=25

C unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Static characteristics

V(BR)DSS drain-source breakdown

voltage ID= 0.25 mA; VGS =0V

Tj=25°C 100 - - V

Tj=−55 °C89--V

VGS(th) gate-source threshold voltage ID= 1 mA; VDS =V

GS;

Figure 9

Tj=25°C 1.1 1.5 2 V

Tj= 185 °C 0.4 - - V

Tj=−55 °C - - 2.3 V

IDSS drain-source leakage current VDS = 100 V; VGS =0V

Tj=25°C - 0.02 1 µA

Tj= 185 °C - - 500 µA

IGSS gate-source leakage current VGS =±15 V; VDS = 0 V - 2 100 nA

RDSon drain-source on-state

resistance VGS =5V; I

D=25A;

Figure 7 and 8

Tj=25°C - 25 30 mΩ

Tj= 185 °C--78mΩ

VGS = 4.5 V; ID=25A - - 33 mΩ

VGS =10V;I

D=25A - 24 28 mΩ

Dynamic characteristics

Qg(tot) total gate charge VGS =5V; V

DS =80V;

ID=25A;Figure 14 -33-nC

Qgs gate-source charge - 7 - nC

Qgd gate-drain (Miller) charge - 13 - nC

Ciss input capacitance VGS =0V; V

DS =25V;

f = 1 MHz; Figure 12 - 2854 3805 pF

Coss output capacitance - 232 278 pF

Crss reverse transfer capacitance - 81 110 pF

td(on) turn-on delay time VDS = 30 V; RL= 1.2 Ω;

VGS =5V; R

G=10Ω-30-nS

trrise time - 86 - nS

td(off) turn-off delay time - 96 - nS

tffall time - 46 - nS

Ldinternal drain inductance measured from drain to

center of die - 2.5 - nH

Lsinternal source inductance measured from source lead

to source bond pad - 7.5 - nH

Source-drain diode

VSD source-drain (diode forward)

voltage IS= 25 A; VGS =0V;

Figure 15 - 0.85 1.2 V

trr reverse recovery time IS=20A;dI

S/dt = −100 A/µs

VGS =−10 V; VDS =30V - 114 - ns

Qrrecovered charge - 196 - nC

Philips Semiconductors BUK9230-100B

TrenchMOS™ logic level FET

Product data Rev. 01 — 22 January 2004 6 of 12

Tj=25°C; tp= 300 µsT

j=25°C; ID=25A

Fig 5. Output characteristics: drain current as a

function of drain-source voltage; typical values. Fig 6. Drain-source on-state resistance as a function

of gate-source voltage; typical values.

Tj=25°C; tp= 300 µs

Fig 7. Drain-source on-state resistance as a function

of drain current; typical values. Fig 8. Normalized drain-source on-state resistance

factor as a function of junction temperature.

03no36

105

140

0246810

VDS (V)

(A)

Label is VGS (V)

4.2

3.8

3.6

3.4

3.2

2.8

2.6

4.6

4.4 10

03no35

3 7 11 15

VGS (V)

RDSon

(mΩ)

03no37

0 35 70 105 140

ID (A)

RDSon

(mΩ)

Label is VGS (V)

3.4 3.6 3.8 4 5 10

03np02

0.7

1.4

2.1

2.8

-60 10 80 150 220

Tj (°C)

aRDSon

RDSon 25 C

()

-----------------------------

Philips Semiconductors BUK9230-100B

TrenchMOS™ logic level FET

Product data Rev. 01 — 22 January 2004 7 of 12

ID= 1 mA; VDS =V

GS Tj=25°C; VDS =V

Fig 9. Gate-source threshold voltage as a function of

junction temperature. Fig 10. Sub-threshold drain current as a function of

gate-source voltage.

Tj=25°C; VDS =25V V

GS = 0 V; f = 1 MHz

Fig 11. Forward transconductance as a function of

drain current; typical values. Fig 12. Input, output and reverse transfer capacitances

as a function of drain-source voltage; typical

values.

03no99

0.0

0.5

1.0

1.5

2.0

2.5

-60 10 80 150 220

Tj (°C)

VGS(th)

(V)

max

typ

min

03ng53

10-6

10-5

10-4

-3

-2

-1

0 0.5 1 1.5 2 2.5 3

VGS (V)

(A)

maxtypmin

03no33

0 1020304050

ID (A)

gfs

(S)

03no38

1250

2500

3750

5000

10-1 1 10 102

VDS (V)

(pF) Ciss

Coss

Crss

Philips Semiconductors BUK9230-100B

TrenchMOS™ logic level FET

Product data Rev. 01 — 22 January 2004 8 of 12

VDS =25V T

j=25°C; ID=25A

Fig 13. Transfer characteristics: drain current as a

function of gate-source voltage; typical values. Fig 14. Gate-source voltage as a function of gate

charge; typical values.

VGS =0V

Fig 15. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values.

03no34

01234

VGS (V)

(A)

Tj = 185 °C

Tj = 25 °C

03no32

0 10203040

QG (nC)

VGS

(V)

VDD = 80 VVDD = 14 V

03no31

100

0.0 0.3 0.6 0.9 1.2

VSD (V)

(A)

Tj = 185 °C

Tj = 25 °C

Philips Semiconductors BUK9230-100B

TrenchMOS™ logic level FET

Product data Rev. 01 — 22 January 2004 9 of 12

7. Package outline

Fig 16. SOT428 (D-PAK)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT428 TO-252 SC-63 99-09-13

01-12-11

0 10 20 mm

scale

Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads

(one lead cropped) SOT428

b2E1

wAM

Note

1. Measured from heatsink back to lead.

AA2

seating plane

mounting

base

A1(1) D

bE1

Ewy

max.

A2b2

b1cD1

min. ee

1L1

min. L2

UNIT

DIMENSIONS (mm are the original dimensions)

0.2 0.2

mm 2.38

2.22 0.65

0.45 0.93

0.73 0.89

0.71 1.1

0.9 5.46

5.26 0.4

0.2 6.22

5.98 4.81

4.45 2.285 4.57 10.4

9.6 0.5 0.9

0.5

6.73

6.47

4.0 2.95

2.55

Philips Semiconductors BUK9230-100B

TrenchMOS™ logic level FET

Product data Rev. 01 — 22 January 2004 10 of 12

8. Revision history

Table 6: Revision history

Rev Date CPCN Description

01 20040122 - Product data (9397 750 12237)

9397 750 12237

Philips Semiconductors BUK9230-100B

TrenchMOS™ logic level FET

Product data Rev. 01 — 22 January 2004 11 of 12

9397 750 12237

Philips Semiconductors BUK9230-100B

TrenchMOS™ logic level FET

Product data Rev. 01 — 22 January 2004 11 of 12

Contact information

For additional information, please visit http://www.semiconductors.philips.com.

For sales ofﬁce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.Fax: +31 40 27 24825

9. Data sheet status

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

10. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

11. Disclaimers

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

licence or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

12. Trademarks

TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.

Level Data sheet status[1] Product status[2][3] Deﬁnition

I Objective data Development This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II Preliminary data Qualiﬁcation This datasheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III Product data Production This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

Printed in The Netherlands

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner.

The information presented in this document does not form part of any quotation or

contract, is believed to be accurate and reliable and may be changed without notice. No

liability will be accepted by the publisher for any consequence of its use. Publication

thereof does not convey nor imply any license under patent- or other industrial or

intellectual property rights.

Date of release: 22 January 2004 Document order number: 9397 750 12237

Contents

Philips Semiconductors BUK9230-100B

TrenchMOS™ logic level FET

1 Product proﬁle . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.4 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1

2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4

5.1 Transient thermal impedance . . . . . . . . . . . . . . 4

6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5

7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9

8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10

9 Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 11

10 Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

11 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11