DIONICS INC. 2N2484 2N2483 NPN SILICON TRANSISTOR CHIPS DESIGNED FOR HYBRID CIRCUIT APPLICATIONS 12.0 ey = B49 + "a SS QQ THEREON 4 NS N UL LIL VM Dimensions in P= iy Seigar = Alumni LT. La _ hickness ae 1 Mil Min, Gimensian Acs: Bonding Pads 40 Mile Min, Separation elwcert Banding Pads. 0.0 Mila Distance from Bonding Pads to Edge ol Chip 2.26 Mils Detailed Specifications on Reverse Side.DIONICS INC. BS AUSHMONE St WESTOUPY, WY Tap Spe gars rate 2N2484 2N2483 NPN SILICON TRANSISTOR CHIPS DESIGNED FOR HYBRID CIRCUIT APPLICATIONS LOW LEAKAGE CHARACTERISTICS # OVERSIZED BONDING PADS NO BETA DEGRADATION DURING PROLONGED HIGH TEMPERATURE ASSEMBLY Unique surface stabilization processing results in lower leakage currents and improved beta stability. These devices are therefare free from the beta degradation frequently encountered during the extended high termperature assembly operations required for complex hybrid canstructian. The large area banding pads are positioned for maximum flexibility af substrate layout. Chips are gold backed for eutectic die-attach, and have aluminum bonding pads for all conven- tional wire bonding techniques. Ge. CURRENT GAIN PULSED TYPICAL FE le ae TOLLECTOR CURRENT 14 MILUAMPERES m1 14 19 20 0 <_____ 100%: Probe Tested to These Parameters @ 25C _>< Guaranteed Pry (tasted on sample baals) View Veen Viens les Cos i Vie Vv Volia Min. Valts Min. Volls Min. m&iMax., 9 Wer (304T.) pF Max. MMH; Min, oo BL Gly aly- Ver Wolts Klax. Gro SV i lp- Sowa Gl- Sle ly TA Toma. 10.4 ao Gls: Ima Ir 8 Vic SM 10 TOW Tm Ie le 0 Loo hog le: WOO 1 T0KH: 1 30M Sheed 100 175280 4 : : an aie 60 60 6 10 O95 6 60 2N2aB3 oe te cag a0 6 10 035 6 60 120 Min = Min Demensional Drawing on Reverse Side