REVISIONS
LTR DESCRIPTION DATE (YR-MO-DA) APPROVED
A Revise for āQDā certification. New boilerplate. Editorial changes t hroughout. -ljs 00-02-24 Ray mond Monnin
The original first page of this drawing has been replaced.
REV
SHEET
REV
SHEET
REV STATUS REV AAAAAA AAA AAAAA
OF SHEETS SHEET 123456 7891011121314
PMIC N/A PREPARED BY
Larry T. Gauder
DEFENSE SUPPLY CENTER COLUMBUS
STANDARD
MICROCIRCUIT
DRAWING
CHECKED BY
Ray Monnin COLUMBUS, OHIO 43216
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
APPROVED BY
Michael A. Frye MICROCI RCUIT, DIGITAL,BIPOLAR, ADVANCED
SCHOTTKY, 8-BIT BIDIRECTIONAL BINARY
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE
13 March 1989 COUNTER, MONOLITHIC SILICON
AMSC N/A REVISION LEVELASIZE
ACAGE CODE
67268 5962-89545
SHEET 1 OF 14
DSCC FORM 2233
APR 97 5962-E143-00
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
STANDARD
MICROCI RCUIT DRAWING
SIZE
A5962-89545
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000 REVISION LEVEL
ASHEET 2
DSCC FORM 2234
APR 97
1. SCOPE
1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in
accordance with MIL-PRF-38535, appendix A.
1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example:
5962-89545 01 R X
īīīī
īīīī
īīīī
ī
ī
ī
ī
Drawing number Device type Case outline Lead finish
(see 1.2.1) (see 1.2.2) (see 1.2.3)
1.2.1 Device type(s). The device type(s) identify the circuit function as follows:
Device type Generic number Circuit function
01 54F579 8-bit bidirectional binary counter,
with three-state outputs
1.2.2 Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows:
Outline letter Descriptive designator Terminals Package style
R GDIP1-T20 or CDIP2-T20 20 dual-in-line
S GDFP2-F20 or GDFP3-F20 20 flat package
2 CQCC1-N20 20 square chip carrier
1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A.
1.3 Absolute maximum ratings.
Supply voltage range .......................................................... -0.5 V dc minimum to 7.0 V dc maximum
Input voltage range ............................................................ -0.5 V dc minimum to 7.0 V dc maximum
Input current range ............................................................ -30 mA minimum to +5.0 mA maximum
Voltage applied to output in high output state ................... -0.5 V dc to + 5.5 V
Current applied to output in low output state ..................... 40 mA
Storage temperature range................................................. -65
ī
C to +150
ī
C
Maximum power dissipation (PD) 1/.................................... 825 mW
Lead temperature (soldering, 10 seconds) ........................ +300
ī
C
Thermal resistance, junction-to-case (
ī
JC) ........................ See MIL-STD-1835
Junction temperature (TJ) .................................................. +175
ī
C
1.4 Recommended operating conditions.
Supply voltage range (VCC) ............................................... 4.5 V dc minimum to 5.5 V dc maximum
High level input voltage (VIH) ............................................. 2.0 V dc
Low level input voltage (VIL) .............................................. 0.8 V dc
Case operating temperature range (TC) ............................ -55
ī
C to +125
ī
C
1/ Must withstand the added PD due to short circuit-test, e.g., IOS.
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APR 97
1.4 Recommended operating conditions ā Continued. 2/
Minimum setup time, I/On to CP (tS(H), tS(L)):
TC = +25
ī
C ..................................................................... 3.0 ns
TC = -55
ī
C, +125
ī
C ......................................................... 4.0 ns
Minimum hold time, I/On to CP (th(H), th(L)):
TC = +25
ī
C ..................................................................... 0.0 ns
TC = -55
ī
C, +125
ī
C ......................................................... 0.0 ns
Minimum setup time,PE , SR , or CS to CP, (tS(H)):
TC = +25
ī
C ..................................................................... 9.5 ns
TC = -55
ī
C, +125
ī
C ......................................................... 11.0 ns
Minimum setup time,PE , SR , or CS to CP, (tS(L)):
TC = +25
ī
C ..................................................................... 9.5 ns
TC = -55
ī
C, +125
ī
C ......................................................... 13.0 ns
Minimum hold time,PE , SR , or CS to CP, (tS(H), th(L)):
TC = +25
ī
C ..................................................................... 0.0 ns
TC = -55
ī
C, +125
ī
C ......................................................... 0.0 ns
Minimum setup time, CEP or CET to CP, (tS(H)):
TC = +25
ī
C ..................................................................... 5.0 ns
TC = -55
ī
C, +125
ī
C ......................................................... 7.5 ns
Minimum setup time, CEP or CET to CP, (tS(L)):
TC = +25
ī
C ..................................................................... 9.0 ns
TC = -55
ī
C, +125
ī
C ......................................................... 11.5 ns
Minimum setup time, CEP or CET to CP, (tS(H), th(L)):
TC = +25
ī
C ..................................................................... 0.0 ns
TC = -55
ī
C, +125
ī
C ......................................................... 0.0 ns
Minimum clock pulse width, (tW(H), tW(L)):
TC = +25
ī
C ..................................................................... 4.5 ns
TC = -55
ī
C, +125
ī
C ......................................................... 6.0 ns
Minimum MR pulse width, (tW(L)):
TC = +25
ī
C ..................................................................... 3.0 ns
TC = -55
ī
C, +125
ī
C ......................................................... 3.0 ns
Minimum recovery time, (tREC):
TC = +25
ī
C ..................................................................... 4.0 ns
TC = -55
ī
C, +125
ī
C ......................................................... 5.0 ns
2/ See figure 4, waveform 5.
STANDARD
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SIZE
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APR 97
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a
part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed
in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in
the solicitation.
SPECIFICATION
DEPARTMENT OF DEFENSE
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
STANDARDS
DEPARTMENT OF DEFENSE
MIL-STD-883 - Test Method Standard Microcircuits.
MIL-STD-973 - Configuration Management.
MIL-STD-1835 - Interface Standard For Microcircuit Case Outlines.
HANDBOOKS
DEPARTMENT OF DEFENSE
MIL-HDBK-103 - List of Standard Microcircuit Drawings (SMD's).
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization
Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-
JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer
Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-
PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying
activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan
may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device.
These modifications shall not affect the PIN as described herein. A "Q" or "QML" certification mark in accordance with MIL-
PRF-38535 is required to identify when the QML flow option is used. This drawing has been modified to allow the
manufacturer to use the alternate die/fabrication requirements of paragraph A.3.2.2 of MIL-PRF-38535 or other alternative
approved by the Qualifying Activity.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as
specified in MIL-PRF-38535, appendix A and herein.
3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Truth table. The truth table shall be as specified on figure 2.
3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3.
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3.2.4 Test circuit and switching waveforms. The test circuit and switching waveforms shall be as specified on figure 4.
3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are
as specified in table I and shall apply over the full case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical
tests for each subgroup are described in table I.
3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN
listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked as listed in MIL-HDBK-103 (see 6.6 herein). For
packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the
option of not marking the "5962-" on the device.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as
required in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535,
appendix A. For class Q product built in accordance with A.3.2.2 of MIL-PRF-38535, or as modified in the manufacturerās
Quality Management (QM) Plan, the āQDā certification mark shall be used in place of the āQMLā or āQā certification mark.
3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an
approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to
listing as an approved source of supply shall affirm that the manufacturer's product meets the requirements of MIL-PRF-
38535, appendix A and the requirements herein.
3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided
with each lot of microcircuits delivered to this drawing.
3.8 Notification of change. Notification of change to DSCC-VA shall be required in accordance with MIL-PRF-38535,
appendix A.
3.9 Verification and review. DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's
facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the
reviewer.
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SIZE
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APR 97
TABLE I. Electrical performance characteristics.
Test Symbol
Conditions
-55
ī
C
ī
TC
ī
+125
ī
C
unless otherwise specified
Group A
sub
g
roups Limits Unit
Min Max
High level output voltage
TC VOH1 VCC = 4.5 V, VIL = 0.8 V
VIH = 2.0 V, IOH = -1.0 mA 1, 2, 3 2.5 V
IOH = -3.0 2.4High level output voltage
I/OnVOH2 VCC = 4.5 V, VIL = 0.8 V
VIH = 2.0 V IOH = -1.0 1, 2, 3 2.5 V
Low level output voltage VOL VCC = 4.5 V, IOL = 20 mA
VIL = 0.8 V, VIH = 2.0 V 1, 2, 3 0.50 V
Input clamp voltage VIK VCC = 4.5 V IIN = -18 mA 1, 2, 3 -1.2 V
VCC = 5.5 V, VIN = 5.5 V I/On1, 2, 3 1.0 mAInput current at maximum
input voltage IIH1
VCC = 5.5 V, VIN = 7.0 V All others 1, 2, 3 100
ī
A
High level input current,
except I/OnIIH2 VCC = 5.5 V, VIN = 2.7 V 1, 2, 3 20
ī
A
Low level input current,
except I/OnIIL1 VCC = 5.5 V, VIN = 0.5 V 1, 2, 3 0.6 mA
Off state current high level
voltage applied to I/OnIOZH VCC = 5.5 V, VIN = 2.7 V
VIH = 2.0 V 1, 2, 3 70
ī
A
Off state current low level
voltage applied to I/OnIOZL VCC = 5.5 V, VIN = 0.5 V
VIH = 2.0 V 1, 2, 3 -600
ī
A
Short circuit output current IOS VCC = 5.5 V, VOUT = GND 1/ 1, 2, 3 -60 -150 mA
Supply current (total) ICCH VCC = 5.5 V 1, 2, 3 135 mA
ICCL 1, 2, 3 145
ICCZ 1, 2, 3 150
Functional tests See 4.3.1c 7, 8
Maximum clock frequency fMAX See waveform 1 2/ 9
10, 11 100
80 MHz
Propagation delay tPLH1 VCC = 5.0 V See Waveform 1 9, 10, 11 ns
CP to I/OntPHL1 CL = 50 pF 9, 10, 11
Propagation delay tPLH2 RL = 500
ī
See Waveform 1 9, 10, 11 ns
CP to TC tPHL2 9, 10, 11
Propagation delay tPLH3 See figure 4 See Waveform 4 9, 10, 11 ns
U/ D to TC tPHL3 9, 10, 11
Propagation delay tPLH4 See Waveform 3 9, 10, 11 ns
CET to TC tPHL4 9, 10, 11
Propagation delay tPHL5 See Waveform 2 9, 10, 11 ns
MR to I/On
See footnotes at end of table.
STANDARD
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SIZE
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DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics ā Continued.
Test Symbol
Conditions
-55
ī
C
ī
TC
ī
+125
ī
C
unless otherwise specified
Group A
sub
g
roups Limits Unit
Min Max
Output disable time from
high to low level tPHZ1 VCC = 5.0 V
CL = 50 pF See Waveform 6 9
10, 11 3.0
3.0 7.5
10.0 ns
CS , PE , to I/OntPLZ1 RL = 500
ī
See Waveform 7 9
10, 11 6.5
5.5 9.5
12.0 ns
Output enable time to
high to low level tPZH2 See figure 4 See Waveform 6 9
10, 11 5.0
3.5 10.5
12.5 ns
CS , PE , to I/OntPZL2 See Waveform 7 9
10, 11 6.5
5.5 10.5
13.0 ns
Output disable time from
high to low level tPHZ3 See Waveform 6 9
10, 11 1.0
1.0 4.0
8.0 ns
OE to I/OntPLZ3 See Waveform 7 9
10, 11 2.5
2.0 7.0
10.0 ns
Output enable time to
high to low level tPZH4 See Waveform 6 9
10, 11 4.0
3.5 8.5
11.0 ns
OE to I/OntPZL4 See Waveform 7 9
10, 11 5.0
4.5 9.5
11.5 ns
1/ Not more than one output should be shorted at a time. For testing I OS, the use of high-speed test apparatus, sample-
and-hold techniques, or both are preferable in order to minimize internal heating and more accurately reflect operational
values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby
cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
Case
outlines R and S 2 Case
outlines R and S 2
Terminal
number Terminal symbol Terminal
number Terminal symbol
1CP CET 11 OE I/O4
2I/O0CEP 12 CS I/O5
3I/O1SR 13 PE I/O6
4I/O2MR 14 U/ DI/O7
5I/O3CP 15 TC OE
6GND I/O016 VCC CS
7I/O4I/O117 CET PE
8I/O5I/O218 CEP U/ D
9I/O6I/O319 SR TC
10 I/O7GND 20 MR VCC
FIGURE 1. Terminal connections.
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Inputs Operating mode
MR SR CS PE CEP CET U/ DOE CP
XXHXXXXXX
I/O0 to I/O7 in high impedance (PE disabled)
XXLHXXXHXI/O
0
to I/O7 in high impedance
X X L H X X X L X Flip-flop output appears on I/O lines
L X X X X X X X X Asynchronous reset for all flip-flops
HLXXXXXX
ī
Synchronous reset for all flip-flops
HHLLXXXX
ī
Parallel load all flip-flops
H H (not LL) H X X X
ī
Hold
H H (not LL) X H X X
ī
Hold (TC held high)
H H (not LL) L L H X
ī
Count up
H H (not LL) L L L X
ī
Count down
H = High voltage level
L = Low voltage level
X = Irrelevant
ī
= Low to high clock transition
(not LL) = CS and PE should never be low voltage level at the same time.
FIGURE 2. Truth table.
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FIGURE 3. Logic diagram.
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Test Switch
tPLZ Closed
tPZL Closed
All others OPEN
NOTES:
1. Input pulse characteristics: PRR = 1 MHz, tW = 500 ns, tTLH = tTHL
ī
2.5 ns, duty cycle = 50 percent.
2. RT = Termination resistance should be equal to ZOUT of the pulse generator.
3. VX = Unlocked pins must be held at
ī
0.8 V,
ī
2.7 V, or open.
FIGURE 4. Test circuit and switching waveforms.
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FIGURE 4. Test circuit and switching waveforms ā Continued.
Waveform 1.
Propagation delay, clock input to output,
clock pulse width and maximum clock frequency
Waveform 2.
Master reset pulse width,
master reset output delay
and master reset to clock recovery time
Waveform 3.
Propagation delay
CET input to terminal count output.
Waveform 4.
Propagation delay
U/ D input to terminal count output
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Waveform 5.
Data setup and hold times
Waveform 6.
Three-state output enable time to high level
and output disable time from high level
Waveform 7.
Three-state output enable time to low level
and output disable time from low level
FIGURE 4. Test circuit and switching waveforms ā Continued.
STANDARD
MICROCI RCUIT DRAWING
SIZE
A5962-89545
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DSCC FORM 2234
APR 97
4. QUALITY ASSURANCE PROVISIONS
4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535,
appendix A.
4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices
prior to quality conformance inspection. The following additional criteria shall apply:
a. Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition A, B, C or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
test method 1015 of MIL-STD-883.
(2) TA = +125
ī
C, minimum.
b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter
tests prior to burn-in are optional at the discretion of the manufacturer.
TABLE II. Electrical test requirements.
MIL-STD-883 test requirements Subgroups
(in accordance with
MIL-STD-883, method 5005,
table I)
Interim electrical parameters
(method 5004) ---
Final electrical test parameters
(method 5004) 1*, 2, 3, 7, 8, 9, 10, 11
Group A test requirements
(method 5005) 1, 2, 3, 7, 8, 9, 10, 11
Groups C and D end-point
electrical parameters
(method 5005)
1, 2, 3
* PDA applies to subgroup 1.
4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of
MIL-STD-883 including groups A, B, C, and D inspections. The following additional criteria shall apply.
4.3.1 Group A inspection.
a. Tests shall be as specified in table II herein.
b. Subgroups 4, 5, and 6 in table I, method 5005 of MIL-STD-883 shall be omitted.
c. Subgroups 7 and 8 shall include verification of the truth table.
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APR 97
4.3.2 Groups C and D inspections.
a. End-point electrical parameters shall be as specified in table II herein.
b. Steady-state life test conditions, method 1005 of MIL-STD-883.
(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision
level control and shall be made available to the preparing or acquiring activity upon request. The test circuit
shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent
specified in test method 1005 of MIL-STD-883.
(2) TA = +125
ī
C, minimum.
(3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535, appendix A.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a
contractor-prepared specification or drawing.
6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished in accordance with MIL-STD-973 using DD Form 1692,
Engineering Change Proposal.
6.4 Record of users. Military and industrial users shall inform Defense Supply Center Columbus when a system application
requires configuration control and the applicable SMD. DSCC will maintain a record of users and this list will be used for
coordination and distribution of changes to the drawings. Users of drawings covering microelectronics devices (FSC 5962)
should contact DSCC-VA, telephone (614) 692-0525.
6.5 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43216-5000, or telephone
(614) 692-0674.
6.6 Approved sources of supply. Approved sources of supply are listed in MIL-HDBK-103. The vendors listed in MIL-
HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted
by DSCC-VA.
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 00-02-24
Approved sources of supply for SMD 5962-89545 are listed below for immediate acquisition information only and
shall be added to MIL-HDBK-103 and QML 38535 during the next revision. MIL-HDBK-103 and QML 38535 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been submitted to and accepted by DSCC-VA. This bulletin is superseded by the next
dated revision of MIL-HDBK-103.and QML 38535.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-8954501RA OC7V7
3/
54F579/RA
54F579/BRA
5962-8954501SA OC7V7
3/
54F579/SA
54F579/BSA
5962-89545012A OC7V7
3/
54F579/2A
54F579/B2A
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
3/ Not available from an approved source.
Vendor CAGE Vendor name
number and address
0C7V7 QP Labs
3605 Kifer Road
Santa Clara, CA 95051
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.
