935262880112 - NXP SEMICONDUCTORS

DATA SH EET

Product specification

Supersedes data of 2000 April 18 2001 Feb 02

INTEGRATED CIRCUITS

UDA1330ATS

Low-cost stereo filter DAC

2001 Feb 02 2

NXP Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

FEATURES

General

•Low power cons umption

•Power supply voltage from 2.7 to 5.5 V

•Selectable control via L3 microcontroller interface or via

static pin control

•System clock frequencies of 256fs, 384fsand 512fs

selectable via L3 interfac e or 256fsand 384fs via static

pin control

•Supports sampling frequencies (fs) from 8to55kHz

•Integrated digital filter plus non inverting

Digital-to-An alo g Co nverter (DAC)

•No analog post filtering required for DAC

•Slave mode only applications

•Easy application

•Small package size (SSOP16)

•TTL tolerant input pads

•Pin and function compatible with the UDA1320ATS.

Multiple format input interface

•L3 mode: I2S-bus, MSB-justified or LSB-justified

16, 18 and 20 bits format compatible

•Static pin mode: I2S-bus and LSB-justified

16, 18 and 20 bits format compatible

•1fsinput format data rate.

DAC digital sound processing

•Digital logarithmic volume control in L3 mode

•Digital de-emphasis for 32, 44.1 and 48 kHz sampling

frequencies in L3 mode or 44.1 kHz sampling frequency

in static pin mode

•Soft mute control both in static pin mode and L3 mode.

Advanced audio configuration

•Stereo line output (volume control in L3 mode)

•High linearity, wide dynamic range and low distortion.

APPLICATIONS

•PC audio applications

•Car radio application s.

GENERAL DESCRIPTION

The UDA1330ATS is a single-chip stereo DAC employing

bitstream conversion techniq ues.

The UDA1330ATS supports the I2S-bus data format with

word lengths of up to 20 bits, the MSB-justified data format

with word lengths of up to 20 bits and the LSB-justified

serial data format with word lengths of 16, 18 and 20 bits.

The UDA1330ATS can be used in two modes: L3 mode or

the static pin mode.

In the L3 mod e, all digital soun d processing fe atures must

be controlled via the L3 interface, including the selection of

the system clock setting.

In the two static modes, the UDA1330ATS can be

operated in the 256fsand 384fs system clock mode.

Muting, de-emphasis for 44.1 kHz and four digital input

formats (I2S-bu s or LSB-justified 16, 18, and 20 bits) can

be selected via s ta tic pins. The L3 interface cannot be

used in this application mode, so volume control is not

available in this mode.

ORDERING INFORMATION

TYPE NUMBER PACKAGE

NAME DESCRIPTION VERSION

UDA1330ATS SSOP16 plastic shrink small outline package; 16 leads ; bod y wi dth 4.4 mm SOT369-1

2001 Feb 02 3

NXP Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

QUICK REFERENCE DATA

Note

1. The output voltage scales linearly with the power supply voltage.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

VDDA DAC analog supply voltage 2.7 5.0 5.5 V

VDDD digital supply voltage 2.7 5.0 5.5 V

IDDA DAC analog supply current VDDA =5.0V

operating −9.5 −mA

power-down −400 −μA

VDDA =3.3V

operating −7.0 −mA

power-down −250 −μA

IDDD digital supply current VDDD =5.0V −5.5 −mA

VDDD =3.3V −3.0 −mA

Tamb ambient temperature −40 −+85 °C

Digital-to-analog converter (VDDA =V

DDD =5.0V)

Vo(rms) output voltage (RMS value) note 1 −1.45 −V

(THD + N) /S total harmonic distortion-plus-noise to

signal ratio at 0 dB −−90 −85 dB

at −60 dB; A-weighted −−40 −35 dB

S/N signal-to-noise ratio code = 0; A-weighted −100 95 dB

αcs channel separation −100 −dB

Digital-to-analog converter (VDDA =V

DDD =3.3V)

Vo(rms) output voltage (RMS value) note 1 −1.0 −V

(THD + N) /S total harmonic distortion-plus-noise to

signal ratio at 0 dB −−85 −dB

at −60 dB; A-weighted −−38 −dB

S/N signal-to-noise ratio code = 0; A-weighted −100 −dB

αcs channel separation −100 −dB

Power dissipation

P power dissipation playback mode

VDDA =V

DDD =5.0V −75 −mW

VDDA =V

DDD =3.3V −33 −mW

2001 Feb 02 4

NXP Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

MGL401

DAC

UDA1330ATS

NOISE SHAPER

INTERPOLATION FILTER

VOLUME/MUTE/DE-EMPHASIS

CONTROL

INTERFACE

DAC

DIGITAL INTERFACE

13 12

VOUTR

BCK

VSSA

VOUTL

DATAI

VDDA

VDDD

Vref(DAC)

VSSD

APPL0

SYSCLK

APPL1

APPSEL

APPL2

APPL3

Fig.1 Block diagram.

PINNING

SYMBOL PIN DESCRIPTION

BCK 1 bit clock input

WS 2 word select inpu t

DATAI 3 data input

VDDD 4 digital supply voltage

VSSD 5 digital ground

SYSCLK 6 system clock input: 256fs,384f

and 512fs

APPSEL 7 application mode select input

APPL3 8 application input 3

APPL2 9 application input 2

APPL1 10 application input 1

APPL0 11 application input 0

Vref(DAC) 12 DAC reference voltage

VDDA 13 analog supply v oltage for DAC

VOUTL 14 left channel output

VSSA 15 analog ground

VOUTR 16 right channel output Fig.2 Pin configuration.

handbook, halfpage

UDA1330ATS

MGL402

VOUTRBCK

VSSA

VOUTL

DATAI

VDDA

VDDD

Vref(DAC)

VSSD

APPL0SYSCLK

APPL1APPSEL

APPL2APPL3

2001 Feb 02 5

NXP Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

FUNCTIONAL DESCRIPTION

System clock

The UDA1330ATS op erates in slave mode only.

Therefore, in all applications the system devices must

provide the system clock. The system frequency (fsys) is

selectable and dep ends on the application mode. The

options are: 256fs,384f

sand 512fs for the L3 mode and

256fsor 384fs for the static pin mode. The system clock

must be locked in frequency to the digita l interface input

signals.

The UDA1330ATS supports sampling frequencies from

8to55kHz.

Application modes

The application mode c an be set with the three-level

pin APPSEL (see Table 1):

•L3 mode

•Static pin mode with fsys =384f

•Static pin mode with fsys =256f

Table 1 Selecting application mode and system clock

frequency via pin APPSEL

The function of an application input pin (active HIGH)

depends on the application mode (see Table 2).

Table 2 Functions of applicatio n input pins

For example, in the static pin mode the outpu t si gnal can

be soft muted by setting pin APPL0 to HIGH.

De-emphasis can be switched on for 44.1 kHz by setting

pin APPL1 to HIGH; setting pin APPL1 to LOW will disable

de-emphasis.

In the L3 mode, pin APPL0 must be set to LOW. It should

be noted that when the L3 mode is used, an initialization

must be performed wh en the IC is powered-up.

Multiple format input interface

DATA FORMATS

The digital interface of the UDA1330ATS supports multiple

format inputs (see Fig.3).

Left and right data-channel words are time multiplexed.

The WS signal must have a 50 % duty fac t or for all

LSB-justified formats.

The BCK clock can be up to 64fs, or in other words the

BCK frequency is 64 times the Word Se lect ( WS)

frequency or less: fBCK ≤64 ×fWS.

Important: the WS e dg e MUST fall on the negative edge

of the BCK at all times for proper operation of the digital

interface.

The UDA1330ATS al so accepts double speed data for

double speed data monitoring purposes

L3 MODE

This mode supports the following input formats:

•I2S-bus format with data word length of up to 20 bits

•MSB-justified format with data word length up to 20 bits

•LSB-justified format with data word length of

16, 18 or 20 bits.

STATIC PIN MODE

This mode supports the following input formats:

•I2S-bus format with data word length of up to 20 bits

•LSB-justified format with data word length of

16, 18 or 20 bits.

These four formats are selectable via the static pin codes

SF0 and SF1 (see Table 3).

Table 3 Input for mat selection using SF0 and SF 1

VOLTAGE ON

PIN APPSEL MODE fsys

VSSD L3 mode 256fs,384f

sor 512fs

0.5VDDD static pin mode 384fs

VDDD 256fs

PIN FUNCTION

L3 MODE STATIC PIN MODE

APPL0 TEST MUTE

APPL1 L3CLOCK DEEM

APPL2 L3MODE SF0

APPL3 L3DATA SF1 FORMAT SF0 SF1

I2S-bus 0 0

LSB-justified 16 bits 0 1

LSB-justified 18 bits 1 0

LSB-justified 20 bits 1 1

2001 Feb 02 6

NXP Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

Interpolation filter (DAC)

The digital filter interpolates from 1fsto 128fs by cascading

a recursive filter and an FIR filter (see Table 4).

Table 4 Interpolation filter characteristics

Noise shaper

The 3rd-order no ise shaper operates at 128fs. It shifts

in-band quantization noise to frequencies well above the

audio band. This noise sh aping technique enables high

signal-to-noise ratios to be achieved. The noise shaper

output is converted into an analog signal using a Filter

Stream DAC (FSDAC).

Filter stream DAC

The FSDAC is a semi-digital reconstruction filter that

converts the 1-bit data stream of the noise shaper to an

analog output voltage. The filter coefficients are

implemented as current sources and are summed at virtual

ground of the output operational amplifier. In this way very

high signal-to-noise performance and low clock jitter

sensitivity is achie ve d. A pos t- f ilter is not needed due to

the inherent filt er function of the DAC. On-board amplifiers

convert the FSDAC output current to an output v oltag e

signal capable of d riving a line output.

The output voltage of the FSDAC scales linearly with the

power supply voltage.

Pin compatibility

In the L3 mode the UDA1330ATS can be used on boards

that are designed for the UDA1320ATS.

Remark: It should be noted that the UDA1330 AT S is

designed for 5 V operation while the UDA1320ATS is

designed for 3 V operation. This means that the

UDA1330ATS can be used with the UDA1320ATS supply

voltage range, but the UDA1320ATS can not be used with

the 5 V supply voltage.

ITEM CONDITION VALUE (dB)

Pass-band ripple 0 to 0.45fs±0.1

Stop band >0.55fs−50

Dynamic range 0 to 0.45fs108

2001 Feb 02 7

NXP Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

boo

k, full pagewidth

MSB B2 B3 B4 B5 B6

LEFT

LSB-JUSTIFIED FORMAT 20 BITS

ATA

RIGHT

1518 1720 19 2 1

B19 LSB

MSB B2 B3 B4 B5 B6

1518 1720 19 2 1

B19 LSB

MSB MSBB2

21> = 812 3

LEFT

I2S-BUS FORMAT

BCK

ATA

RIGHT

3> = 8

MSB B2

MBL14

MSB B2

LEFT

LSB-JUSTIFIED FORMAT 16 BITS

ATA

RIGHT

15 2 1

B15 LSB

MSB B2

15 2 1

B15 LSB

MSB B2 B3 B4

LEFT

LSB-JUSTIFIED FORMAT 18 BITS

ATA

RIGHT

1518 17 2 1

MSB B2 B3 B4

B17 LSB

16 1518 17 2 1

B17 LSB

MSB-JUSTIFIED FORMAT

SLEFT RIGHT

321321

MSB B2 MSBLSB LSB MSB B2B2

> = 8 > = 8

ATA

Fig.3 Digital interface input fo rmat data format.Fig.3 Digital interface input fo rmat data format.

2001 Feb 02 8

NXP Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

L3 INTERFACE

The following system and digital sound processing

features can be contro lled in the L3 mod e of the

UDA1330ATS:

•System clock frequency

•Data input format

•De-emphasis for 32, 44.1 and 48 kHz

•Volume

•Soft mute.

The exchange of data and control information between the

microcontroller and the UDA1330ATS is accomplished

through a serial interface comprising the following signals:

•L3DATA

•L3MODE

•L3CLOCK.

Information transfer through the microcontroller bus is

organized in accordance with the L3 interface format, in

which two different mod es of operation can be

distinguished: address mode and data transfer mode.

Address mode

The address mode (see Fig.4) is required to select a

device communicating via the L3 inter face and to define

the destination registers for the data trans f er mode.

Data bits 7 to 2 represent a 6-bit device address wher e

bit 7 is the MSB. The address of the UDA1330ATS is

000101 (bit 7 to bit 2). If the UD A1330ATS receives a

different address, it will deselect its microcontroller

interface logic.

Data transfer mode

The selected address remains active during subsequent

data transfers until the UDA1330ATS receives a new

address comman d.

The fundamental timing of data transfers (see Fig.5) is

essentially the same as the address mode. The maximum

input clock frequency and data rate is 64fs.

Data transfer can only be in one direction, consisting of

input to the UDA1330ATS to program sound processing

and other functional features. All data transfers are by 8-bit

bytes. Data will be stored in the UDA1330ATS after

reception of a comple te byte.

A multibyte transfer is illustrated in Fig.6.

Registers

The sound processing and other feature values are stored

in independent registers. The first selection of the registers

is achieved by the ch oic e of data type that is transferred.

This is performed in the address mode using bit 1 and bit 0

(see Table 5).

Table 5 Selection of data transfer

The second selection is perfo rmed by the 2 MSBs of the

data byte (bit 7 and bit 6). The other bits in the data byte

(bit 5 to bit 0) represent the value that is placed in the

selected reg i sters.

The ‘status’ settings are given in Table 6 and the ‘data’

settings are given in Table 7.

BIT 1 BIT 0 TRANSFER

0 0 data (volume, de-emphasis, mute)

0 1 not used

1 0 status (system clock frequency,

data input format)

1 1 not used

2001 Feb 02 9

NXP Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

handbook, full pagewidth

th(L3)A

th(L3)DA

tsu(L3)DA

Tcy(CLK)(L3)

BIT 0

L3MODE

L3CLOCK

L3DATA BIT 7

MGL723

tCLK(L3)H

tCLK(L3)L

tsu(L3)A

th(L3)A

Fig.4 Timing address mode.

handbook, full pagewidth tstp(L3) tstp(L3)

tsu(L3)D

tsu(L3)DA th(L3)DA

th(L3)D

MGL882

Tcy(CLK)L3

L3MODE

L3CLOCK

tCLK(L3)H

tCLK(L3)L

BIT 0

L3DATA

WRITE BIT 7

Fig.5 Timing data transfer mode.

2001 Feb 02 10

NXP Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

handbook, full pagewidth tstp(L3)

address

L3DATA

L3CLOCK

L3MODE

addressdata byte #1 data byte #2 MGL725

Fig.6 Multibyte data transfer.

Programming the features

When the data transfer of type ‘status’ is selected, the features for the system clock frequency and the data input format

can be controlled.

Table 6 Data transfer of type ‘status’

When the data transfer of type ‘data’ is selected , the features for volume, de-emphasis and mute can be co ntrolled.

Table 7 Data transfer of type ‘data’

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 REGISTER SELECTED

0 0 SC1 SC0 IF2 IF1 IF0 0 SC = system clock frequency (2 bits); see Table 8

IF = data input format (3 bits); see Table 9

10000000not used

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 REGISTER SELECTED

0 0 VC5 VC4 VC3 VC2 VC1 VC0 VC = volume control (6 bits); see Table 11

01000000not used

1 0 0 DE1 DE0 MT 0 0 DE = de-emphasis (2 bits); see Table 10

MT=mute(1bit); seeTable12

11000001default setting

2001 Feb 02 11

NXP Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

SYSTEM CLOCK FREQUENCY

The system clock frequency is a 2-bit value to select the

external clock freq uency.

Table 8 System clock settings

DATA FORMAT

The data format is a 3-bit value to select the used data

format.

Table 9 Data input format settings

DE-EMPHASIS

De-emphasis is a 2-bit value to enable the digital

de-emphasis filter .

Table 10 De-emphasis settings

VOLUME CONTROL

The volume control is a 6-bit value to program the volume

attenuation from 0 to −60 dB and −∞ dB in steps of 1 dB.

Table 11 Volume settings

MUTE

Mute is a 1-bit value to enable the digital mute.

Table 12 Mute setting

SC1 SC0 FUNCTION

0 0 512fs

0 1 384fs

1 0 256fs

1 1 not used

IF2 IF1 IF0 FORMAT

000I

2S-bus

0 0 1 LSB-justified 16 bits

0 1 0 LSB-justified 18 bits

0 1 1 LSB-justified 20 bits

1 0 0 MSB-justified

1 0 1 not used

1 1 0 not used

1 1 1 not used

DE1 DE0 FUNCTION

0 0 no de-empha sis

0 1 de-empha sis, 32 kHz

1 0 de-empha s is, 44.1 kHz

1 1 de-empha sis, 48 kHz

VC5 VC4 VC3 VC2 VC1 VC0 VOLUME (dB)

000000 0

000001 0

000010 −1

000011 −2

:::::: :

110011 −51

110100

110101 −52

110110

110111 −54

111000

111001

−57111010

111011

111100 −60

111101

111110 −∞

111111

MT FUNCTION

0 no muting

1muting

2001 Feb 02 12

NXP Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

Notes

1. All supply connections must be made to the same power supply .

2. Equivalent to discha rging a 100 pF capacitor via a 1.5 kΩ series resistor .

3. Equivalent to discha rging a 200 pF capacitor via a 2.5 μH series inductor.

4. Short-circuit test at Tamb =0°C and VDDA = 3 V. DAC operation after short-c i rc uiting cannot be warranted.

HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is

desirabl e to tak e no rmal precautions ap propriate to hand ling MOS devices.

THERMAL CHARACTE RISTICS

QUALITY SPECIFICATION

In accordance with “SNW-FQ-611-E”.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VDDD digital supply voltage note 1 −6.0 V

VDDA analog supply voltage note 1 −6.0 V

Txtal(max) maximum crystal temperature −150 °C

Tstg storage temperature −65 +125 °C

Tamb ambient temperature −40 +85 °C

Ves electrostatic handlin g voltage note 2 −3000 +3000 V

note 3 −250 +250 V

Isc(DAC) short-circuit current of DAC note 4

output short-circuited to VSSA(DAC) −450 mA

output short-circuited to VDDA(DAC) −300 mA

SYMBOL PARAMETER CONDITIONS VALUE UNIT

Rth(j-a) thermal resistance from junction to ambient in free air 190 K/W

2001 Feb 02 13

NXP Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

DC CHARACTERISTICS

VDDD =V

DDA =5.0V; T

amb =25°C; RL=5kΩ; all voltages referenced to groun d (pins VSSA and VSSD); unless

otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

VDDA DAC analog supply voltage note 1 2.7 5.0 5.5 V

VDDD digital supply voltage note 1 2.7 5.0 5.5 V

IDDA DAC analog supply current VDDA =5.0V

operating −9.5 −mA

power-down −400 −μA

VDDA =3.3V

operating −7.0 −mA

power-down −250 −μA

IDDD digital su pp ly current VDDD =5.0V −5.5 −mA

VDDD =3.3V −3.0 −mA

Power dissipation

P power dissipation playback mode

VDDA =V

DDD =5.0V −75 −mW

VDDA =V

DDD =3.3V −33 −mW

Digital inputs: pins BCK, WS, DATAI, SYSCLK, APPL0, APPL1, APPL2 and APPL3 (note 2)

VIH HIGH-level input voltage VDDD = 5.0 V 2.2 −−V

VDDD = 3.3 V 1.45 −−V

VIL LOW-level input voltage VDDD =5.0V −−0.8 V

VDDD =3.3V −−0.5 V

⎪ILI⎪input leakage current −−1μA

Ciinput capacitance −−10 pF

Three-level input: APPSEL

VIH HIGH-level input voltage 0.9VDDD −VDDD +0.5 V

VIM MIDDLE-level input

voltage 0.4VDDD −0.6VDDD V

VIL LOW-level input voltage −0.5 −+0.1VDDD V

2001 Feb 02 14

NXP Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

Notes

1. All supply connections must be made to the same external power supply unit.

2. The digita l inpu t pads are TTL compatible at 5 V, but the pads are not 5 V tolerant in the voltage range between

2.7 and 4.5 V.

3. When the DAC drives a cap ac itive load above 50 pF, a series re sistance of 100 Ω must be used to prevent

oscillations in the output operational amplifier.

AC CHARACTERISTICS

fi= 1 kHz; Tamb =25°C; RL=5kΩ; all voltages referenced to ground (pins VSSA and VSSD); unless otherwis e specified.

DAC

Vref(DAC) reference voltage with respect to VSSA 0.45VDDA 0.5VDDA 0.55VDDA V

Io(max) maximum output current (THD + N)/S < 0.1%;

RL=5kΩ

−0.36 −mA

Rooutput resistance −0.15 2.0 Ω

RLload resistance 3 −−kΩ

CLload capacitance note 3 −−50 pF

SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT

Digital-to-analog converter (VDDA =V

DDD =5.0V)

Vo(rms) output voltage (RMS value) 1.45 −V

ΔVounbalance between channels 0.1 −dB

(THD + N)/S total harmonic distortion-p lus-noise to

signal ratio at 0 dB −90 −85 dB

at −60 dB; A-weighted −40 −35 dB

S/N signal-to-noise ratio code = 0; A-weighted 100 9 5 dB

αcs channel separation 100 −dB

Digital-to-analog converter (VDDA =V

DDD =3.3V)

Vo(rms) output voltage (RMS value) 1.0 −V

ΔVounbalance between channels 0.1 −dB

(THD + N)/S total harmonic distortion-p lus-noise to

signal ratio at 0 dB −85 −dB

at −60 dB; A-weighted −38 −dB

S/N signal-to-noise ratio code = 0; A-weighted 100 −dB

αcs channel separation 100 −dB

PSRR power supply ripple rejection fripple =1kHz;

Vripple = 100 mV (p-p) 60 −dB

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

2001 Feb 02 15

NXP Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

TIMING

VDDD =V

DDA = 4.5 to 5.5 V; Tamb =−40 to +85 °C; RL=5kΩ; all voltages referenced to ground (pins VSSA and VSSD);

unless otherwise sp ecified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

System clock (see Fig.7)

Tsys system clock cycle time fsys = 256fs71 88 488 ns

fsys = 384fs47 59 325 ns

fsys = 512fs36 44 244 ns

tCWL LOW-level system clock pulse width fsys < 19.2 MHz 0.3Tsys −0.7Tsys ns

fsys ≥19.2 MHz 0.4Tsys −0.6Tsys ns

tCWH HIGH-lev el system clock pulse width fsys < 19.2 MHz 0.3Tsys −0.7Tsys ns

fsys ≥19.2 MHz 0.4Tsys −0.6Tsys ns

Digital interface (s ee Fig.8)

Tcy(BCK) bit clock cycle time 300 −−ns

tBCKH bit clock HIGH time 100 −−ns

tBCKL bit clock LOW time 100 −−ns

trrise time −−20 ns

tffall time −−20 ns

tsu(DATAI) data input set-up time 20 −−ns

th(DATAI) data input hold time 0 −−ns

tsu(WS) word select set-up time 20 −−ns

th(WS) word select hold time 10 −−ns

Control interface L3 mode (see Figs 4 and 5)

Tcy(CLK)L3 L3CLOCK cycle time 500 −−ns

tCLK(L3)H L3CLOCK HIGH time 250 −−ns

tCLK(L3)L L3CLOCK LOW time 250 −−ns

tsu(L3)A L3MODE set-up time for address mode 190 −−ns

th(L3)A L3MODE ho ld time for ad dr ess mode 190 −−ns

tsu(L3)D L3MODE set-up time for data transfer

mode 190 −−ns

th(L3)D L3MODE hold time for data transfer

mode 190 −−ns

tsu(L3)DA L3DA TA set-up time for data transfer and

address mode 190 −−ns

th(L3)DA L3DATA hold time for data transfer and

address mode 30 −−ns

tstp(L3) L3MODE stop time for data transfer

mode 190 −−ns

2001 Feb 02 16

NXP Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

handbook, full pagewidth

MGR984

Tsys

tCWH

tCWL

Fig.7 System clock timing.

handbook, full pagewidth

MGL880

th(WS)

tsu(WS)

tsu(DATAI) th(DATAI)

tBCKH

tBCKL

Tcy(BCK)

BCK

DATAI

Fig.8 Serial interface timing.

2001 Feb 02 17

NXP Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

APPLICATION INFORMATION

Fig.9 Application diagra m.

handbook, full pagewidth

MGL403

47 Ω

UDA1330ATS

SYSCLK

system

clock

BCK

DATAI

14 VOUTL R4

100 Ω

10 kΩ

16 VOUTR R6

100 Ω

10 kΩ

APPSEL

APPL1

APPL2

APPL3

APPL0

47 μF

(16 V)

47 μF

(16 V)

C2 left

output

right

output

12 Vref(DAC)

47 μF

(16 V)

100 nF

(63 V)

VDDD

VSSD

1 Ω

digital

supply voltage

15 13

VSSA VDDA

1 Ω

100 μF

(16 V)

100 nF

(63 V) 100 nF

(63 V)

analog

supply voltage

2001 Feb 02 18

NXP Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

PACKAGE OUTLINE

UNIT A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.00 1.4

1.2 0.32

0.20 0.25

0.13 5.3

5.1 4.5

4.3 0.65 6.6

6.2 0.65

0.45 0.48

0.18 10

0.130.2 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.

0.75

0.45

SOT369-1 MO-152 99-12-27

03-02-19

yHE

detail X

vMA

(A )

0.25

16 9

pin 1 index

0 2.5 5 mm

scale

SOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369

-1

max.

1.5

2001 Feb 02 19

NXP Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

SOLDERING

Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.

A more in-depth acco un t of sold er ing ICs can be found in

our “Data Handbook IC26; Integra te d Circuit Packages”

(document order number 9398 652 90011).

There is no soldering method tha t is idea l for all surface

mount IC packages. Wave soldering is not always suitable

for surface mount ICs, or for printed-circuit boards with

high population dens ities. In these situations reflow

soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-s yringe dispensin g before package placement.

Several methods exist for reflowing; for example,

infrared/convection heating in a conveyor type oven.

Throughput times (preheating, soldering and cooling) vary

between 100 and 2 00 seconds depending on heating

method.

Typical reflow peak temperatur es range from

215to250°C. The top-surface temperature of the

packages sh ould preferable be k ept below 230 °C.

Wave soldering

Conventional single wave soldering is not recommended

for surface mount devices (SMDs) or printed-circuit boards

with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering

method was specifically developed.

If wave soldering is used the following conditions must be

observed for optimal results:

•Use a double-wa ve soldering method comprising a

turbulent wave with high up ward pressure followed by a

smooth laminar wave.

•For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint

longitudinal axi s is preferred to be parallel to the

transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the

printed-circuit board .

The footprint must incorporate solder thieves at the

downstream end.

•For packages with leads on four sides, the footprint must

be plac ed at a 45° angle to the transp ort direction of the

printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

During placement and before soldering, the package must

be fixed with a droplet of adh esive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will elim inate the need for removal

of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two

diagonally-opposite end leads. Use a low voltage (24 V or

less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 s ec on ds at up to

300 °C.

When using a dedicated tool, all other leads ca n be

soldered in one ope ration within 2 to 5 seco nds between

270 and 320 °C.

2001 Feb 02 20

NXP Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with res pect to time) and body size of the package, there is a risk that internal or external pack age

cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the “Data Handbook IC26; Integrated Cir cu i t Pac kages; Section: Packing Methods”.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is con sid ered, then the package must be p lace d at a 45° angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side cor ners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

PACKAGE SOLDERING METHOD

WAVE REFLOW(1)

BGA, LFBGA, SQFP, TFBGA not suitable suitable

HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable(2) suitable

PLCC(3), SO, SOJ suitable suitable

LQFP, QFP, TQFP not recommended(3)(4) suitable

SSOP, TSSOP, VSO not recommended(5) suitable

2001 Feb 02 21

NXP Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

DATA SHEET STATUS

Notes

1. Please consult the most recently issued docu ment before initiating or completing a des ign.

2. The prod uct status of device(s) described in this document may have changed since this do cument was published

and may differ in case of multiple devices. The latest product status information is available on the Internet at

URL http://www.nxp.com.

DOCUMENT

STATUS(1) PRODUCT

STATUS(2) DEFINITION

Objective data sheet Development This document contains data from the objective s pe cification for product

development.

Preliminary data sheet Qualification This document contains data from the preliminary specification.

Product data sheet Production This document contains the product specific ation.

DISCLAIMERS

Limited warranty and liability ⎯ Information in this

document is believed to be accurate and reliab le .

However, NXP Semiconduc tors does not give any

representations or warranties, expressed or implied, as to

the accuracy or completeness of such information and

shall have no liability for the consequences of use of such

information.

In no event shall NXP Semiconductors be liable for any

indirect, incidental, punitive, special or consequential

damages (including - without limitation - lost profits, lost

savings, busin es s interru ption, costs related to the

removal or replacement of any products or rework

charges) whether or not such damages are based on tort

(including negligence), warranty, breach of contract or any

other legal theory.

Notwithstanding any damages that customer might incur

for any reason whatsoever, NXP Semiconductors’

aggregate and cu mulative liability towards customer for

the products described herein shall be limited in

accordance with the Terms and conditio ns of commercial

sale of NXP Semiconductors.

Right to make changes ⎯ NXP Semiconductors

reserves the right to make changes to informa t ion

published in this doc ument, including without limitation

specifications and product descriptions, at any time and

without notice. This document supersedes and replaces all

information supplied prior to the publication hereof.

Suitability for use ⎯ NXP Semiconduct ors pr oduc ts are

not designed, au thorized or warran ted to be suitable for

use in life support, life-critical or safety-critical systems or

equipment, nor in applications where failure or malfunction

of an NXP Semiconductors product can reason ably be

expected to result in pe rs onal injury, death or severe

property or environmental damage. NXP Semiconductors

accepts no liability for inclusion and/or use of NXP

Semiconductor s pr oducts in such equipme nt or

application s and therefore such inclusion and /or use is at

the customer’s own risk.

Applications ⎯ Applications that are described herein for

any of these products are for illustrative purposes only.

NXP Semiconductors makes no representation or

warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of

their applications and products using NXP

Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or

customer product design. It is customer’s sole

responsibility to determine whether the NXP

Semiconductors pro du ct is su itable and fit for the

customer’s applications and products planned, as well as

for the planned a pplication and use of custom er’s third

party customer(s). Customers should provide appropriate

design and opera t ing saf eg ua rd s to minimize the risks

associated with their applications and products.

NXP Semiconduc tors does n ot a ccept any liabil ity rela ted

to any default, damage, costs or problem which is based

on any weakne ss or default in t he customer’s applic ations

or products, or the application or use by customer’s third

party customer( s) . C us to m er is responsible for doin g all

necessary testing for the customer’s applications and

products using NXP Semiconductors products in order to

avoid a default of the applic ations and the products or of

the application or use by customer’s third p arty

customer(s). NXP does not accept any liability in this

respect.

2001 Feb 02 22

NXP Semiconductors Product specification

Low-cost stereo filter DAC UDA1330ATS

Limiting values ⎯ Stress above one or more limiting

values (as defined in the Absolute Maximum Ratings

System of IEC 60134) will cause permanent damage to

the device. Limiting values are stress ratin gs only and

(proper) operation of the device at these or any other

conditions abo ve those given in the Recommended

operating conditions section (if present) or the

Characteristics sections of this document is not warranted.

Constant or repeated exposure to limiting values will

permanently and irreversibly affect the quality and

reliability of the device.

Terms and conditions of commercial sale ⎯ NXP

Semiconductors products are sold subject to the general

terms and conditio ns of commercial sale, as published at

http://www.nxp.com/profile/terms, unless other wis e

agreed in a valid written ind i vidual agreemen t. In cas e an

individual agreeme nt is co nc luded only the terms and

conditions of the resp ective agreement shall apply. NXP

Semiconductors hereby expressly objects to apply i ng the

customer’s general terms and conditions with regard to the

purchase of NXP Semicon ductors produc ts by customer.

No offer to sell or license ⎯ Nothing in this document

may be interpreted or construed as an offer to sell products

that is open for acceptance or the grant, conveyan ce or

implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control ⎯ This document as well as the item(s)

described he re in may be subject to export con tro l

regulations. Export might require a prior authorization from

national auth or itie s.

Quick refer ence data ⎯ The Quick reference data is an

extract of th e product data given in the Limiting values an d

Characteristics sections of this document, an d as such is

not complete, exhaus tive or legally binding.

Non-automotive qualified products ⎯ Unless this data

sheet expressly states that this specific NXP

Semiconductors product is au tomotive qualified, the

product is not suitable for automotive use. It is neither

qualified nor te sted in accordanc e with automot ive testing

or application requirements. NXP Semiconductors accepts

no liability for inclusion and/or use of non-automotive

qualified prod ucts in automotive equip m en t or

applications.

In the event that customer uses the product for design-in

and use in automotive applications to automotive

specifications and standards, customer (a) shall use the

product without NXP Semiconductors’ warranty of the

product for such au t omo tive applications, use and

specifications, and (b) whenever customer uses the

product for automotive applications beyond NXP

Semiconductors’ specifications such use shall be solely at

customer’s own ris k, and (c) customer fully indemnifies

NXP Semiconductors for any liability, damages or failed

product clai ms r esult ing fr om custo mer desi gn an d us e o f

the product for automotive ap plic ations beyond NXP

Semiconductors ’ st andard warranty and NXP

Semiconductors’ product specifications.

NXP Semiconductors

provides High Performance Mixed Signal and Standard Product

solutions that leverage its leading RF, Analog, Power Management,

Interface, Security and Digital Processing expertise

Contact information

For additional information p lease visit: http://www.nxp.com

For sales offices addresses send e- mail to: salesaddresses@nxp.com

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information pr e sent ed in this document does not form p art of any quotation or co nt ra ct, is b elieve d to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other ind us trial or intellectual property rights.

Customer notification

This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal

definitions and disclaimer s. No changes were made to the technical content, except for package outline

drawings which were updated to the latest version.

Printed in The Netherlands 753503/05/pp23 Date of release: 2001 Feb 02 Document order number: 9397 750 07939