Switching Characteristics
V
CC
=5.0V, T
A
=25˚C (See Section 1 for Waveforms and Load Configuations)
C
L
=15 pF
Symbol Parameter R
L
=100ΩUnits
Min Max
t
PLH
Propagation Delay 50 ns
t
PHL
A
n
to a–g 75
t
PLH
Propagation Delay 70 ns
t
PHL
LE to a–g 90
Functional Description
The ’68 is a 7-segment decoder driver designed to drive
7-segment common cathode LED displays. The ’68 drives
any common cathode LED display rated at a nominal 20 mA
at 1.7V per segment without need for current limiting resis-
tors.
This device accepts a 4-bit binary code and produces output
drive to the appropriate segments of the 7-segment display.
It has a hexadecimal decode format which produces numeric
codes “0” thru “9” and alpha codes “A” through “F” using up-
per and lower case fonts.
Latches on the four data inputs are controlled by an active
LOW latch enable LE. When the LE is LOW, the state of the
outputs is determined by the input data. When the LE goes
HIGH, the last data present at the inputs is stored in the
latches and the outputs remain stable. The LE pulse width
necessary to accept and store data is typically 30 ns which
allows data to be strobed into the ’68 at normal TTL speeds.
This feature means that data can be routed directly from high
speed counters and frequency dividers into the display with-
out slowing down the system clock or providing intermediate
data storage.
Another feature of the ’68 is that the unit loading on the data
inputs is very low (−100 µA Max) when the latch enable is
HIGH. This allows ’68s to be driven from an MOS device in
multiplex mode without the need for drivers on the data lines.
The ’68 also has provision for automatic blanking of the lead-
ing and/or trailing edge zeros in a multidigit decimal number,
resulting in an easily readable decimal display conforming to
normal writing practice. In an eight digit mixed integer frac-
tion decimal representation, using the automatic blanking ca-
pability, 0060.0300 would be displayed as 60.03. Leading
edge zero suppression is obtained by connecting the Ripple
Blanking Output (RBO) of a decoder to the Ripple Blanking
Input (RBI) of the next lower stage device. The most signifi-
cant decoder stage should have the RBI input grounded; and
since suppression of the least significant integer zero in a
number is not usually desired, the RBI input of this decoder
stage should be left open. A similar procedure for the frac-
tional part of a display will provide automatic suppression of
trailing edge zeros. The RBO terminal of the decoder can be
OR-tied with a modulating signal via an isolating buffer to
achieve pulse duration intensity modulation.Asuitable signal
can be generated for this purpose by forming a variable fre-
quency multivibrator with a cross coupled pair of TTL or DTL
gates.
Logic Symbol
DS009796-2
VCC =Pin 16
GND =PIN 8
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