11 GHz to 20 GHz, Tunable Band-Pass Filter ADMV8420 Data Sheet NIC 6 13 NIC NIC 12 14 NIC NIC 11 15 GND NIC 5 NIC 10 GND 4 8 16 RFOUT 9 17 GND NIC GND 2 RFIN 3 NIC = NOT INTERNALLY CONNECTED. PACKAGE BASE GND 17199-001 20 NIC 21 NIC 22 NIC 23 NIC 19 NIC 18 NIC ADMV8420 VFCTL Test and measurement equipment Military radar and electronic warfare systems Very small aperture terminal (VSAT) communications NIC 1 7 APPLICATIONS 24 NIC FUNCTIONAL BLOCK DIAGRAM Amplitude settling time: 200 ns Wideband rejection: 20 dB Single-chip implementation 24-lead, 4 mm x 4 mm, RoHS-compliant LFCSP NIC FEATURES Figure 1. GENERAL DESCRIPTION The ADMV8420 is a monolithic microwave integrated circuit (MMIC), tunable band-pass filter that features a user-selectable pass band frequency. The 3 dB filter bandwidth is approximately 20%, and the 20 dB filter bandwidth is approximately 40%. Additionally, the center frequency (fCENTER) varies between 11 GHz to 20 GHz by applying a center frequency control Rev. A voltage between 0 V to 15 V. This tunable filter is a smaller alternative to switched filter banks and cavity tuned filters. The ADMV8420 has minimal microphonics due to the monolithic design and provides a dynamically adjustable solution in advanced communications applications. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADMV8420 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Interface Schematics .....................................................................5 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................6 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 10 General Description ......................................................................... 1 Applications Information .............................................................. 11 Revision History ........................................................................... 2 Typical Application Circuit ....................................................... 11 Specifications..................................................................................... 3 Evaluation Printed Circuit Board (PCB) ................................ 12 Absolute Maximum Ratings............................................................ 4 Outline Dimensions ....................................................................... 14 ESD Caution .................................................................................. 4 Ordering Guide .......................................................................... 14 Pin Configuration and Function Descriptions ............................. 5 REVISION HISTORY 8/2019--Rev. 0 to Rev. A Changes to Figure 1 .......................................................................... 1 Changes to Table 1 ............................................................................ 3 Changes to Figure 2 and Table 3 ..................................................... 5 Changes to Figure 7, Figure 8, and Figure 9.................................. 6 Changes to Figure 16 ........................................................................ 7 Changes to Figure 25 ........................................................................ 9 Changes to Typical Application Circuit Section and Figure 26 ................................................................................... 11 Changes to Figure 28 ...................................................................... 12 Added Figure 29; Renumbered Sequentially .............................. 13 Moved Table 4 ................................................................................. 13 Change to Ordering Guide ............................................................ 14 6/2019--Revision 0: Initial Version Rev. A | Page 2 of 14 Data Sheet ADMV8420 SPECIFICATIONS TA = 25C, center frequency control voltage (VFCTL) is swept from 0 V to 15 V. Table 1. Parameter FREQUENCY RANGE fCENTER F3dB (3 dB Cutoff Frequency) BANDWIDTH 3 dB REJECTION Low-Side High-Side Reentry LOSS Insertion Loss Return Loss DYNAMIC PERFORMANCE Input Power at 5 Shift in Insertion Phase (VFCTL = 0 V) Input Third-Order Intercept (IP3) Group Delay Phase Sensitivity Amplitude Settling Drift Rate RESIDUAL PHASE NOISE 1 MHz Offset TUNING VFCTL Center Frequency Control Current (IFCTL) Min Typ 11 9.75 Max Unit 20 22 GHz GHz 20 % 0.8 x fCENTER 1.2 x fCENTER 2.3 x fCENTER 0 Test Conditions/Comments GHz GHz GHz 5 8.5 dB dB 10 31 0.5 1.3 200 dBm dBm ns Rad/V ns -1.1 MHz/C -161 dBc/Hz 15 1 Rev. A | Page 3 of 14 V mA 20 dB 20 dB 30 dB At VFCTL = 7 V Time to settle to minimum insertion loss, within 0.5 dB of static insertion loss ADMV8420 Data Sheet ABSOLUTE MAXIMUM RATINGS ESD CAUTION Table 2. Parameter Tuning VFCTL IFCTL Radio Frequency (RF) Input Power Operating Temperature Range Storage Temperature Range Junction Temperature for 1 Million Mean Time to Failure (MTTF) Nominal Junction Temperature (Temperature at Ground Pad = 85C, Input Power (PIN) = 27 dBm) Electrostatic Discharge (ESD) Rating Human Body Model (HBM) Field Induced Charge Device Model (FICDM) Moisture Sensitivity Level (MSL) Rating Rating -0.5 V to +15 V 1 mA 27 dBm -40C to +85C -65C to +150C 150C 108C 1000 V 1250 V MSL3 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. A | Page 4 of 14 Data Sheet ADMV8420 20 NIC 19 NIC 22 NIC 21 NIC 24 NIC 23 NIC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NIC 1 18 NIC GND 2 17 GND RFIN 3 ADMV8420 16 RFOUT GND 4 TOP VIEW (Not to Scale) 15 GND NIC 5 14 NIC NIC 6 NOTES 1. NIC = NOT INTERNALLY CONNECTED. THESE PINS ARE NOT CONNECTED INTERNALLY. HOWEVER, ALL DATA SHOWN HEREIN WAS MEASURED WITH THESE CONNECTED TO RF AND DC GROUND. 2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO RF AND DC GROUND. 17199-002 NIC 11 NIC 12 NIC 10 VFCTL 9 NIC 7 NIC 8 13 NIC Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1, 5 to 8, 10 to 14, and 18 to 24 Mnemonic NIC 2, 4, 15, and 17 3 GND RFIN 9 16 VFCTL RFOUT Description Not Internally Connected. These pins are not connected internally. All data shown is measured with these pins connected to the RF and dc ground. Ground. These pins must be connected to the radio frequency (RF) and dc ground. RF Input. This pin is dc-coupled and matched to 50 . Do not apply an external voltage to this pin. Center Frequency Control Voltage. This pin controls the fCENTER of the device. RF Output. This pin is dc-coupled and matched to 50 . Do not apply an external voltage to this pin. Exposed Pad. The exposed pad must be connected to RF and dc ground. EPAD INTERFACE SCHEMATICS RFIN 100 20pF 27pF 17199-005 0.4nH Figure 3. VFCTL Interface Schematic Figure 5. RFIN Interface Schematic RFOUT 17199-004 GND 17199-006 4 17199-003 VFCTL Figure 6. RFOUT Interface Schematic Figure 4. GND Interface Schematic Rev. A | Page 5 of 14 ADMV8420 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0 0 0V 7V 15V -5 -20 -30 -40 -50 -60 -15 -20 -25 -30 S11, 0V S22, 0V S11, 7V S22, 7V S11, 15V S22, 15V -35 -70 0 5 10 15 20 25 30 35 40 RF FREQUENCY (GHz) -40 17199-107 -80 -10 Figure 7. Broadband Insertion Loss vs. RF Frequency at Various Voltages 0 5 10 15 20 25 30 35 40 RF FREQUENCY (GHz) 17199-110 BROADBAND RETURN LOSS (dB) INSERTION LOSS (dB) -10 Figure 10. Broadband Return Loss vs. RF Frequency at Various Voltages 0 0 0V 7V 15V -5 -5 -15 -20 -20 -25 S11, 0V S22, 0V S11, 7V S22, 7V S11, 15V S22, 15V -30 -25 -35 5 10 15 20 25 30 RF FREQUENCY (GHz) -40 17199-108 7 9 11 13 15 17 19 21 25 27 Figure 11. Return Loss vs. RF Frequency at Various Voltages Figure 8. Insertion Loss vs. RF Frequency at Various Voltages 0 0 -40C +25C +85C -5 -2 RETURN LOSS (dB) -4 -10 -15 -20 -6 -8 -10 -12 -14 S11, -40C S22, -40C S11, +25C S22, +25C S11, +85C S22, +85C -16 -25 -18 5 10 15 20 RF FREQUENCY (GHz) 25 30 -20 17199-109 -30 23 RF FREQUENCY (GHz) Figure 9. Minimum Insertion Loss vs. RF Frequency at Various Temperatures, VFCTL = 7 V 10 12 14 16 18 20 22 RF FREQUENCY (GHz) 24 26 28 30 17199-112 -30 INSERTION LOSS (dB) -15 17199-111 RETURN LOSS (dB) INSERTION LOSS (dB) -10 -10 Figure 12. Return Loss vs. RF Frequency at Various Temperatures, VFCTL = 7 V Rev. A | Page 6 of 14 Data Sheet 25 ADMV8420 0 -40C +25C +85C -2 INSERTION LOSS (dB) 15 10 5 30 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -12 0 MAXIMUM RETURN LOSS (dB) 15 10 5 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VFCTL (V) 3 4 5 6 7 8 9 10 11 12 13 14 15 -40C +25C +85C -6 -9 -12 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VFCTL (V) Figure 14. 3 dB Bandwidth vs. VFCTL at Various Temperatures 1.00 2 -3 -15 17199-114 1 1 Figure 16. Minimum Insertion Loss vs. VFCTL at Various Temperatures 20 0 0 VFCTL (V) -40C +25C +85C 25 3dB BANDWIDTH (%) -8 17199-116 1 17199-113 0 Figure 13. fCENTER vs. VFCTL at Various Temperatures Figure 17. Maximum Return Loss in a 2 dB Bandwidth vs. VFCTL at Various Temperatures -40C +25C +85C 1.40 0.95 -40C +25C +85C 1.35 HIGH-SIDE REJECTION RATIO LOW-SIDE REJECTION RATIO -6 -10 VFCTL (V) 0 -4 17199-117 fCENTER (GHz) 20 0 -40C +25C +85C 0.90 0.85 0.80 0.75 1.30 1.25 1.20 1.15 1.10 1 2 3 4 5 6 7 8 VFCTL (V) 9 10 11 12 13 14 15 1.00 0 1 2 3 4 5 6 7 8 VFCTL (V) Figure 15. Low-Side Rejection Ratio vs. VFCTL at Various Temperatures 9 10 11 12 13 14 15 17199-118 0 17199-115 1.05 0.70 Figure 18. High-Side Rejection Ratio vs. VFCTL at Various Temperatures Rev. A | Page 7 of 14 ADMV8420 Data Sheet 1200 0.8 -40C +25C +85C 0.7 GROUP DELAY (ns) 800 600 400 200 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VFCTL (V) 0.4 0.2 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 RF FREQUENCY (GHz) Figure 22. Group Delay vs. RF Frequency at Various Voltages Figure 19. Tuning Sensitivity vs. VFCTL at Various Temperatures 40 1.0 -40C +25C +85C 35 0.8 30 INPUT IP3 (dBm) GROUP DELAY (ns) 0.5 0.3 17199-119 0 0.6 17199-122 TUNING SENSITIVITY (MHz/V) 1000 0V 7V 15V 0.6 0.4 25 20 15 10 0.2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VFCTL (V) 0 17199-120 0 RESIDUAL PHASE NOISE (dBc/Hz) -120 -130 -140 -150 -160 10 100 1k 10k 100k 1M OFFSET FREQUENCY (Hz) 10M 100M 17199-121 -170 -180 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Figure 23. Input IP3 vs. VFCTL at Various Temperatures, PIN = 20 dBm 0V 7V 15V -110 1 VFCTL (V) Figure 20. Group Delay vs. VFCTL at Various Temperatures -100 0 17199-123 -40C +25C +85C 5 Figure 21. Residual Phase Noise vs. Offset Frequency at Various VFCTL Voltages Rev. A | Page 8 of 14 Data Sheet 10 0 -10 -20 -30 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 INPUT POWER 5.0 APPROXIMATE fCENTER 18 4.5 16 4.0 14 3.5 12 3.0 10 2.5 2.0 8 DELTA PHI 6 1.5 4 1.0 2 0.5 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VFCTL Figure 24. Phase Shift vs. Input Power (dBm) Figure 25. Phase Sensitivity vs. VFCTL Voltages Rev. A | Page 9 of 14 DELTA PHI (RAD/V) 20 20 17199-124 PHASE SHIFT (Degrees) 30 5.5 22 = 0V = 1V = 3V = 7V = 10V = 15V 0 17199-125 VFCTL VFCTL VFCTL VFCTL VFCTL VFCTL APPROXIMATE fCENTER (GHz) 40 ADMV8420 ADMV8420 Data Sheet THEORY OF OPERATION The ADMV8420 is a MMIC band-pass filter that features a user-selectable pass band frequency. Varying the applied analog tuning voltage between 0 V and 15 V at VFCTL varies the fCENTER between 11 GHz and 20 GHz. Rev. A | Page 10 of 14 Data Sheet ADMV8420 19 21 20 1 Rev. A | Page 11 of 14 5 14 6 13 PACKAGE BASE GND VFCTL Figure 26. Typical Application Circuit 17199-026 C3 100pF RFOUT 12 15 11 16 4 10 On the VFCTL control port, the C3 decoupling capacitor is shown with 100 pF as the typical value. However, the selection of the C3 capacitor is determined based on the system design criteria for phase noise and tuning speed. That is, there is a baseband noise characteristic for a particular control voltage, which can translate into additive phase noise within the filter. Minimizing baseband noise on the control voltage can be done by capacitive means at the expense of voltage rise time, which impacts the tuning speed of the filter. Carefully consider the control voltage baseband noise and rise time performance to ensure that system performance metrics are met. C2 100pF 17 3 8 RFIN 18 ADMV8420 2 9 C1 100pF 7 Figure 26 shows the typical application circuit for the ADMV8420. The RFIN and RFOUT pins are dc-coupled and external voltage must not be applied. It is recommended to install 100 pF series capacitors (C1 and C2) on the RF traces to prevent any prestage or poststage interaction with the filter. 22 24 TYPICAL APPLICATION CIRCUIT 23 APPLICATIONS INFORMATION ADMV8420 Data Sheet PRIMARY SILKSCREEN EVALUATION PRINTED CIRCUIT BOARD (PCB) PRIMARY SOLDER MASK NOMINAL FINISHED BOARD THICKNESS 0.062" 10% 0.5oz Cu PRIMARY SIDE (LAYER 1) ARLON OR ROGERS CORE 10MILS 1MIL (CRITICAL) 0.5oz Cu L2_GND PLANE PREPREG AS REQUIRED 0.5oz Cu L3_GND PLANE 370HR 0.5oz Cu (LAYER 2) (LAYER 3) SECONDARY SIDE (LAYER 4) Figure 27. The Cross Sectional View of the ADMV8420-EV ALZ PCB Layers 17199-126 The circuit board in this application uses RF circuit design techniques. Signal lines must have 50 impedance. The package ground leads and exposed pad must connect directly to the ground plane (see Figure 27). A sufficient number of via holes connect the top and bottom ground planes. The evaluation circuit board shown in Figure 28 is available from Analog Devices, Inc. upon request. Figure 28. Evaluation PCB Layout, Top View Rev. A | Page 12 of 14 17199-028 All RF traces are routed on Layer 1 (primary side). The remaining three layers are ground planes that provide a solid ground for RF transmission lines, as shown in Figure 27. The top dielectric material is Rogers 4350, which offers low loss performance. The prepreg material in Layer 2 attaches the Isola 370HR core layer to copper traces layers. Both the prepreg material and the Isola 370HR core layer achieve the required board finish thickness. ADMV8420 PAD NIC NIC NIC NIC NIC NIC PAD 24 23 22 21 20 19 Data Sheet 2 3 4 1492-04A-5 18 17 16 15 GND 14 NIC 13 NIC ADMV8420 NIC GND U1 RFOUT J2 1492-04A-5 1 4 3 2 AGND 7 8 9 10 11 12 AGND NIC GND RFIN GND NIC NIC NIC NIC VFCTL NIC NIC NIC 1 1 2 3 4 5 6 J1 AGND DNI DNI J8 WHT DNI P + C1 4.7F N AGND J5 WHT DNI DNI DNI C3 1000pF AGND C4 100pF DNI C6 100pF AGND AGND 1492-04A-5 DNI P + C9 C7 4.7F 1000pF N AGND AGND P + C8 4.7F N AGND C5 1000pF AGND C2 100pF AGND Figure 29. ADMV8420-EVALZ Evaluation Board Schematic Table 4. Bill of Materials for the ADMV8420-EVALZ Reference Designator J1 and J2 J7 and GND C2 C5 C8 U1 PCB1 1 2 Description PCB mount, southwest 2.4 mm connector Test points Capacitor, 100 pF, 0402 Capacitor, 1000 pF, 0603 Capacitor, 4.7 F, 3216 ADMV8420 08-0512982 evaluation PCB Circuit board material is Arlon 25FR or Rogers 25FR. Rogers 4350 is the laminate on top of Arlon 25FR or Rogers 25FR. The raw, bare PCB identifier is 08-051298. Rev. A | Page 13 of 14 17199-127 J7 WHT ADMV8420 Data Sheet OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 0.30 0.25 0.18 P IN 1 IN D IC ATO R AR E A OP T IO N S (SEE DETAIL A) 24 19 1 18 0.50 BSC 2.70 2.60 SQ 2.50 EXPOSED PAD 13 TOP VIEW 0.80 0.75 0.70 SIDE VIEW PKG-004273/5069 SEATING PLANE 0.50 0.40 0.30 6 12 7 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8 09-07-2018-A PIN 1 INDICATOR AREA 4.10 4.00 SQ 3.90 Figure 30. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm x 4 mm Body and 0.75 mm Package Height (CP-24-15) Dimensions shown in millimeters ORDERING GUIDE Model1 ADMV8420ACPZ ADMV8420ACPZ-R5 ADMV8420-EVALZ 1 Temperature Range -40C to +85C -40C to +85C Package Description 24-Lead LFCSP 24-Lead LFCSP, 7" Tape and Reel Evaluation Board All models are RoHS-compliant parts. (c)2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D17199-0-8/19(A) Rev. A | Page 14 of 14 Package Option CP-24-15 CP-24-15