11 GHz to 20 GHz, Tunable
Band-Pass Filter
Data Sheet ADMV8420
Rev. A Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2019 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Amplitude settling time: 200 ns
Wideband rejection: ≥20 dB
Single-chip implementation
24-lead, 4 mm × 4 mm, RoHS-compliant LFCSP
APPLICATIONS
Test and measurement equipment
Military radar and electronic warfare systems
Very small aperture terminal (VSAT) communications
FUNCTIONAL BLOCK DIAGRAM
2
1
3
4
5
6
18
17
16
15
14
13
NIC
NIC
GND
RFIN
GND
NIC
NIC
NIC
GND
RFOUT
GND
NIC
8
9
10
11
7
NIC
V
FCTL
NIC
NIC
12
NIC
NIC
20
19
21
NIC
NIC
NIC
22 NIC
23 NIC
24 NIC
ADMV8420
17199-001
NIC = NOT INTERNALLY CONNECTED.
PACKAGE
BASE
GND
Figure 1.
GENERAL DESCRIPTION
The ADMV8420 is a monolithic microwave integrated circuit
(MMIC), tunable band-pass filter that features a user-selectable
pass band frequency. The 3 dB filter bandwidth is approximately
20%, and the 20 dB filter bandwidth is approximately 40%.
Additionally, the center frequency (fCENTER) varies between
11 GHz to 20 GHz by applying a center frequency control
voltage between 0 V to 15 V. This tunable filter is a smaller
alternative to switched filter banks and cavity tuned filters. The
ADMV8420 has minimal microphonics due to the monolithic
design and provides a dynamically adjustable solution in
advanced communications applications.
ADMV8420 Data Sheet
Rev. A | Page 2 of 14
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ........................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
ESD Caution .................................................................................. 4
Pin Configuration and Function Descriptions ............................. 5
Interface Schematics .....................................................................5
Typical Performance Characteristics ..............................................6
Theory of Operation ...................................................................... 10
Applications Information .............................................................. 11
Typical Application Circuit ....................................................... 11
Evaluation Printed Circuit Board (PCB) ................................ 12
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
8/2019—Rev. 0 to Rev. A
Changes to Figure 1 .......................................................................... 1
Changes to Table 1 ............................................................................ 3
Changes to Figure 2 and Table 3 ..................................................... 5
Changes to Figure 7, Figure 8, and Figure 9.................................. 6
Changes to Figure 16 ........................................................................ 7
Changes to Figure 25 ........................................................................ 9
Changes to Typical Application Circuit Section
and Figure 26 ................................................................................... 11
Changes to Figure 28 ...................................................................... 12
Added Figure 29; Renumbered Sequentially .............................. 13
Moved Table 4 ................................................................................. 13
Change to Ordering Guide ............................................................ 14
6/2019—Revision 0: Initial Version
Data Sheet ADMV8420
Rev. A | Page 3 of 14
SPECIFICATIONS
TA = 25°C, center frequency control voltage (VFCTL) is swept from 0 V to 15 V.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
FREQUENCY RANGE
fCENTER 11 20 GHz
F3dB (3 dB Cutoff Frequency) 9.75 22 GHz
BANDWIDTH
3 dB 20 %
REJECTION
Low-Side 0.8 × fCENTER GHz ≥20 dB
High-Side 1.2 × fCENTER GHz ≥20 dB
Reentry 2.3 × fCENTER GHz ≤30 dB
LOSS
Insertion Loss 5 dB
Return Loss 8.5 dB
DYNAMIC PERFORMANCE
Input Power at 5° Shift in Insertion Phase (VFCTL = 0 V) 10 dBm
Input Third-Order Intercept (IP3) 31 dBm
Group Delay 0.5 ns
Phase Sensitivity 1.3 Rad/V At VFCTL = 7 V
Amplitude Settling 200 ns Time to settle to minimum insertion loss,
within ≤0.5 dB of static insertion loss
Drift Rate −1.1 MHz/°C
RESIDUAL PHASE NOISE
1 MHz Offset −161 dBc/Hz
TUNING
VFCTL 0 15 V
Center Frequency Control Current (IFCTL) ±1 mA
ADMV8420 Data Sheet
Rev. A | Page 4 of 14
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Tuning
VFCTL −0.5 V to +15 V
IFCTL ±1 mA
Radio Frequency (RF) Input Power 27 dBm
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature for 1 Million Mean
Time to Failure (MTTF)
150°C
Nominal Junction Temperature
(Temperature at Ground Pad = 85°C,
Input Power (PIN) = 27 dBm)
108°C
Electrostatic Discharge (ESD) Rating
Human Body Model (HBM) 1000 V
Field Induced Charge Device Model
(FICDM)
1250 V
Moisture Sensitivity Level (MSL) Rating MSL3
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress rating
only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum
operating conditions for extended periods may affect product
reliability.
ESD CAUTION
Data Sheet ADMV8420
Rev. A | Page 5 of 14
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
17199-002
2
1
3
4
5
6
18
17
16
15
14
13
NIC
NIC
GND
RFIN
GND
NIC
NIC
NIC
GND
RFOUT
GND
NIC
8
9
10
11
7
NIC
V
FCTL
NIC
NIC
12
NIC
NIC
20
19
21
NIC
NIC
NIC
22 NIC
23 NIC
24 NIC
ADMV8420
TOP VIEW
(Not to Scale)
NOTES
1. NIC = NOT INTERNALLY CONNECTED. THESE PINS ARE NOT CONNECTED INTERNALLY.
HOWEVER, ALL DATA SHOWN HEREIN WAS MEASURED WITH THESE CONNECTED
TO RF AND DC GROUND.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED TO RF AND DC GROUND.
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1, 5 to 8, 10 to 14, and 18 to 24 NIC Not Internally Connected. These pins are not connected internally. All data shown is
measured with these pins connected to the RF and dc ground.
2, 4, 15, and 17 GND Ground. These pins must be connected to the radio frequency (RF) and dc ground.
3 RFIN
RF Input. This pin is dc-coupled and matched to 50 Ω. Do not apply an external voltage
to this pin.
9 VFCTL Center Frequency Control Voltage. This pin controls the fCENTER of the device.
16 RFOUT
RF Output. This pin is dc-coupled and matched to 50 Ω. Do not apply an external voltage
to this pin.
EPAD Exposed Pad. The exposed pad must be connected to RF and dc ground.
INTERFACE SCHEMATICS
4Ω100Ω
27pF
V
FCTL
0.4nH
20pF
17199-003
Figure 3. VFCTL Interface Schematic
GND
17199-004
Figure 4. GND Interface Schematic
RFIN
17199-005
Figure 5. RFIN Interface Schematic
RFOUT
17199-006
Figure 6. RFOUT Interface Schematic
ADMV8420 Data Sheet
Rev. A | Page 6 of 14
TYPICAL PERFORMANCE CHARACTERISTICS
0
–80
–70
–60
–50
–40
–30
–20
–10
0 5 10 15 20 25 30 35 40
INSERTION LOSS (dB)
RF FREQUENCY (GHz)
17199-107
0V
7V
15V
Figure 7. Broadband Insertion Loss vs. RF Frequency at Various Voltages
0
–30
–25
–20
–15
–10
–5
5 10152025 30
INSERTION LOSS (dB)
RF FREQUENCY (GHz)
17199-108
0V
7V
15V
Figure 8. Insertion Loss vs. RF Frequency at Various Voltages
0
–30
–25
–20
–15
–10
–5
5 10152025 30
INSERTION LOSS (dB)
RF FREQUENCY (GHz)
17199-109
–40°C
+25°C
+85°C
Figure 9. Minimum Insertion Loss vs. RF Frequency at Various Temperatures,
VFCTL = 7 V
–40
–35
–30
–25
–20
–15
–10
–5
0
0 5 10 15 20 25 30 35 40
BROADBAND RETURN LOSS (dB)
RF FREQUENCY (GHz)
S11, 0V
S22, 0V
S11, 7V
S22, 7V
S11, 15V
S22, 15V
17199-110
Figure 10. Broadband Return Loss vs. RF Frequency at Various Voltages
–40
–35
–30
–25
–20
–15
–10
–5
0
7 9 11 13 15 17 19 21 23 25 27
RETURN LOSS (dB)
RF FREQUENCY (GHz)
S11, 0V
S22, 0V
S11, 7V
S22, 7V
S11, 15V
S22, 15V
17199-111
Figure 11. Return Loss vs. RF Frequency at Various Voltages
–20
–18
–16
–14
–12
–10
–8
–6
–4
–2
0
10 12 14 16 18 20 22 24 26 28 30
RETURN LOSS (dB)
RF FREQUENCY (GHz)
S11, –40°C
S22, –40°C
S11, +25°C
S22, +25°C
S11, +85°C
S22, +85°C
17199-112
Figure 12. Return Loss vs. RF Frequency at Various Temperatures, VFCTL = 7 V
Data Sheet ADMV8420
Rev. A | Page 7 of 14
0
5
10
15
20
25
0123456789101112131415
fCENTER (GHz)
VFCTL (V)
–40°C
+25°C
+85°C
17199-113
Figure 13. fCENTER vs. VFCTL at Various Temperatures
0
5
10
15
20
25
30
0123456789101112131415
3dB BANDWIDTH (%)
V
FCTL
(V)
–40°C
+25°C
+85°C
17199-114
Figure 14. 3 dB Bandwidth vs. VFCTL at Various Temperatures
0.70
0.75
0.80
0.85
0.90
0.95
1.00
0123456789101112131415
L
O
W-SIDE REJECTION
R
A
TI
O
V
FCTL
(V)
–40°C
+25°C
+85°C
17199-115
Figure 15. Low-Side Rejection Ratio vs. VFCTL at Various Temperatures
0
–12
–10
–8
–6
–4
–2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
INSERTION LOSS (dB)
V
FCTL
(V)
17199-116
–40°C
+25°C
+85°C
Figure 16. Minimum Insertion Loss vs. VFCTL at Various Temperatures
–15
–12
–9
–6
–3
0
0123456789101112131415
MAXIMUM RETURN LOSS (dB)
V
FCTL
(V)
–40°C
+25°C
+85°C
17199-117
Figure 17. Maximum Return Loss in a 2 dB Bandwidth vs. VFCTL at Various
Temperatures
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
0123456789101112131415
HIGH-SIDE REJECTION R
A
TI
O
V
FCTL
(V)
–40°C
+25°C
+85°C
17199-118
Figure 18. High-Side Rejection Ratio vs. VFCTL at Various Temperatures
ADMV8420 Data Sheet
Rev. A | Page 8 of 14
0
200
400
600
800
1000
1200
0123456789101112131415
TUNING SENSITIVITY (MHz/V)
V
FCTL
(V)
–40°C
+25°C
+85°C
17199-119
Figure 19. Tuning Sensitivity vs. VFCTL at Various Temperatures
0
0.2
0.4
0.6
0.8
1.0
0123456789101112131415
GROUP DEL
A
Y (ns)
V
FCTL
(V)
–40°C
+25°C
+85°C
17199-120
Figure 20. Group Delay vs. VFCTL at Various Temperatures
–180
–160
–140
–120
–
100
–110
–130
–150
–170
10 100 1k 10k 100k 1M 10M 100M
RESIDU
A
L PHASE NOISE (dBc/Hz)
OFFSET FREQUENCY (Hz)
0V
7V
15V
17199-121
Figure 21. Residual Phase Noise vs. Offset Frequency at Various VFCTL Voltages
0.2
0.3
0.4
0.5
0.6
0.7
0.8
89 1112 14
15
16 24
GROUP DEL
A
Y (ns)
10 13 17 18 19 20 21 22 23 25
RF FREQUENCY (GHz)
0V
7V
15V
17199-122
Figure 22. Group Delay vs. RF Frequency at Various Voltages
0
5
10
15
20
25
30
35
40
0123456789101112131415
INPUT IP3 (dBm)
V
FCTL
(V)
–40°C
+25°C
+85°C
17199-123
Figure 23. Input IP3 vs. VFCTL at Various Temperatures, PIN = 20 dBm
Data Sheet ADMV8420
Rev. A | Page 9 of 14
–30
–20
–10
0
10
20
30
40
0123456789
INPUT POWER
10 11 12 13 14 15 16 17 18
V
FCTL
= 0V
V
FCTL
= 1V
V
FCTL
= 3V
V
FCTL
= 7V
V
FCTL
= 10V
V
FCTL
= 15V
PHASE SHIFT (Degrees)
17199-124
Figure 24. Phase Shift vs. Input Power (dBm)
0
0.5
1.0
1.5
2.0
3.0
4.0
4.5
5.5
0
2
4
6
8
10
12
14
16
18
20
22
01234567
VFCTL
8 9 10 11 12 13 14 15
APPROXIMATE fCENTER (GHz)
DELTA PHI (RAD/V)
5.0
3.5
2.5
APPROXIMATE
fCENTER
DELTA PHI
17199-125
Figure 25. Phase Sensitivity vs. VFCTL Voltages
Data Sheet ADMV8420
Rev. A | Page 11 of 14
APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUIT
Figure 26 shows the typical application circuit for the
ADMV8420. The RFIN and RFOUT pins are dc-coupled and
external voltage must not be applied. It is recommended to
install 100 pF series capacitors (C1 and C2) on the RF traces to
prevent any prestage or poststage interaction with the filter.
On the VFCTL control port, the C3 decoupling capacitor is shown
with 100 pF as the typical value. However, the selection of the
C3 capacitor is determined based on the system design criteria
for phase noise and tuning speed. That is, there is a baseband
noise characteristic for a particular control voltage, which can
translate into additive phase noise within the filter. Minimizing
baseband noise on the control voltage can be done by capacitive
means at the expense of voltage rise time, which impacts the
tuning speed of the filter. Carefully consider the control voltage
baseband noise and rise time performance to ensure that system
performance metrics are met.
V
FCTL
C2
100pF
C1
100pF
C3
100pF
RFOUTRFIN
2
1
3
4
5
6
18
17
16
15
14
13
8
9
10
11
7
12
20
19
21
22
23
24
ADMV8420
PACKAGE
BASE
GND
17199-026
Figure 26. Typical Application Circuit
ADMV8420 Data Sheet
Rev. A | Page 12 of 14
EVALUATION PRINTED CIRCUIT BOARD (PCB)
All RF traces are routed on Layer 1 (primary side). The remaining
three layers are ground planes that provide a solid ground for RF
transmission lines, as shown in Figure 27. The top dielectric
material is Rogers 4350, which offers low loss performance. The
prepreg material in Layer 2 attaches the Isola 370HR core layer to
copper traces layers. Both the prepreg material and the Isola
370HR core layer achieve the required board finish thickness.
NOMINAL
FINISHED
BOARD
T
HICKNESS 0.062"
±10%
PRIMARY SILKSCREEN
PRIMARY SOLDER MASK
PRIMARY SIDE (LAYER 1)
L2_GND PLANE (LAYER 2)
L3_GND PLANE (LAYER 3)
SECONDARY SIDE (LAYER 4)
0.5oz Cu
ARLON OR ROG ERS CORE 10MIL S ±1MIL ( CRIT ICAL)
0.5oz Cu
PREPREG AS REQUIRED
0.5oz Cu
370HR
0.5oz Cu
17199-028
Figure 27. The Cross Sectional View of the ADMV8420-EV ALZ PCB Layers
The circuit board in this application uses RF circuit design
techniques. Signal lines must have 50 Ω impedance. The package
ground leads and exposed pad must connect directly to the ground
plane (see Figure 27). A sufficient number of via holes connect the
top and bottom ground planes. The evaluation circuit board shown
in Figure 28 is available from Analog Devices, Inc. upon request.
17199-126
Figure 28. Evaluation PCB Layout, Top View
Data Sheet ADMV8420
Rev. A | Page 13 of 14
432
ADMV8420
U1
8NIC
7NIC
9V
FCTL
10 NIC
11 NIC
1
3
4
NIC
RFIN
2GND
GND
5NIC
23
NIC
24
PAD
NIC
PAD
22
NIC 21
NIC 20
NIC
17
16
15
GND
18
NIC
RFOUT
GND 14
NIC
19
NIC
12 NIC
234
1
+
1
AGND
AGND AGND
1492-04A-5 1492-04A-5
1492-04A-5
J2J1
DNI
DNI DNIDNI
AGND
P
N
C9
4.7µF
AGND
C7
1000pF
AGND
C6
100pF
DNI DNIDNI
AGND
C4
100pF
AGND
C3
1000pF
+
AGND
P
N
C1
4.7µF
6NIC 13
NIC
J5
WHT
DNI
J8
WHT
AGND
C2
100pF
AGND
C5
1000pF
+
AGND
P
N
C8
4.7µF
J7
WHT
17199-127
Figure 29. ADMV8420-EVALZ Evaluation Board Schematic
Table 4. Bill of Materials for the ADMV8420-EVALZ
Reference Designator Description
J1 and J2 PCB mount, southwest 2.4 mm connector
J7 and GND Test points
C2 Capacitor, 100 pF, 0402
C5 Capacitor, 1000 pF, 0603
C8 Capacitor, 4.7 μF, 3216
U1 ADMV8420
PCB1 08-0512982 evaluation PCB
1 Circuit board material is Arlon 25FR or Rogers 25FR. Rogers 4350 is the laminate on top of Arlon 25FR or Rogers 25FR.
2 The raw, bare PCB identifier is 08-051298.
ADMV8420 Data Sheet
Rev. A | Page 14 of 14
OUTLINE DIMENSIONS
0.80
0.75
0.70
PKG-004273/5069
0.50
BSC
0.50
0.40
0.30
COMPLIANT
TO
JEDEC STANDARDS MO-220-WGGD-8
BOTTOM VIEW
TOP VIEW
SIDE VIEW
4.10
4.00 SQ
3.90
0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
1
24
712
13
18
19
6
09-07-2018-A
0.30
0.25
0.18
0.20 MIN
2.70
2.60 SQ
2.50
EXPOSED
PAD
PIN 1
INDICATORAREAOPTIONS
(SEEDETAILA)
DETAIL A
(JEDEC 95)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
PIN 1
INDICATOR
AREA
SEATING
PLANE
Figure 30. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-15)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADMV8420ACPZ −40°C to +85°C 24-Lead LFCSP CP-24-15
ADMV8420ACPZ-R5 −40°C to +85°C 24-Lead LFCSP, 7” Tape and Reel CP-24-15
ADMV8420-EVALZ Evaluation Board
1 All models are RoHS-compliant parts.
©2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D17199-0-8/19(A)
