Preliminary W26A041
256K
×
16 CMOS STATIC RAM
Publication Release Date: April 19, 2002
- 1 - Revision A1
GENERAL DESCRIPTION
The W26A041 is a normal-speed, very low-power CMOS static RAM organized as 262144 x 16 bits
that operates on a wide voltage range from 1.65V to 1.95V power supply. The W26A041, W26A041-LE
and W26A041-LI, can meet the requirement of various operating temperature. This device is
manufactured using Winbond’s high performance CMOS technology.
FEATURES
• Low power consumption
• Access time: 70 nS
• 1.65V to 1.95V supply voltage
• Fully static operation
• All inputs and outputs directly TTL compatible
• Three-state outputs
• Battery back-up operation capability
• Data retention voltage: 1.5V (min.)
• Data byte control
− #LB (I/O1 − I/O8), #UB (I/O9 − I/O16)
• Available packages: 44-pin type two TSOP,
and TFBGA
PIN CONFIGURATIONS
TFBGA TOP VIEW
32
28
22
21
20
19
18
17
1
44-pin
TSOP
3
4
5
6
7
8
9
10
11
12
13
14
15
16
2
A10
#OE
I/O16
A12
44
43 A6
A7
A5
A8
A11
A9
#UB
42
41
40
39
35
31
30
29
27
26
25
24
23
38
37
36
34
33
#LB
I/O15
I/O14
I/O13
I/O1
0
I/O1
1
I/O12
V
DD
VSS
I/O
9
A3
A2
A1
A0
I/O7
I/O6
I/O5
I/O4
I/O8
VSS
I/O3
I/O2
I/O1
A13
A4
#WE
A15
V
DD
A14
A16
A17
#CS1
CS2
A
B
C
D
E
F
G
H
1 2 3 4 5 6
A0 A1
NC
A3 A6
A8
I/O5
A2
A4
A7
I/O1
I/O6
I/O2
VSS VDD
VDD VSS
I/O7
NC
I/O3
I/O9
A16
A15
I/O4
A9 A10 A11
A12 A13
A17
#OE #CS1
#WE I/O8
I/O10
A14
I/O11
I/O15
I/O16
I/O12
I/O13
I/O14
A5
NC
NC
#LB CS2
#UB
BLOCK DIAGRAM
CORE CELL ARRAY
1024 ROWS
256 X 16 COLUMNS
DATA
CNTRL.
CLK
GEN.
R
O
W
D
E
C
O
D
E
R
A6
I/O CKT.
COLUMN DECODER
#WE
#OE
CLK GEN. PRECHARGE CKT.
A5
A4
A3
A2
A1
A0
#CS1
A17
A16
A15
A14
A13
A12A10
A8
A7
I/O1
I/O16
:
A9 A11
#UB
#LB
CS2
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 − A17 Address Inputs
I/O1 − I/O16 Data Inputs/Outputs
#CS1 Chip Select Input 1, Low Active
CS2 Chip Select Input 2, High Active
#WE Write Enable Input
#LB Lower byte select
#UB Upper byte select
#OE Output Enable Input
VDD Power Supply
VSS Ground
NC No Connection
Preliminary W26A041
- 2 -
TRUTH TABLE
#CS1
CS2
#OE
#WE
#LB
#UB
MODE I/O1
−
I/O8
I/O9
−
I/O16
VDD
CURRENT
H X X X X X Not Selected High Z High Z ISB, ISB1
X L X X X X Not Selected High Z High Z ISB, ISB1
X X X X H H Not Selected High Z High Z ISB, ISB1
L H H H X X Output Disable High Z High Z IDD
L H L H L L 2 Bytes Read DOUT DOUT IDD
L H L H L H Lower Byte Read
DOUT High Z IDD
L H L H H L Upper Byte Read
High Z DOUT IDD
L H X L L L 2 Bytes Write DIN DIN IDD
L H X L L H Lower Byte Write
DIN High Z IDD
L H X L H L Upper Byte Write
High Z DIN IDD
Preliminary W26A041
Publication Release Date: April 19, 2002
- 3 - Revision A1
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER RATING UNIT
Supply Voltage to VSS Potential -0.5 to +4.6 V
Input/Output to VSS Potential -0.5 to VDD +0.5 V
Allowable Power Dissipation 1.0 W
Storage Temperature -65 to +150 °C
Operating Temperature LE -20 to 85 °C
LI -40 to 85 °C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
Operating Characteristics
(VSS = 0V; TA (°C) = -20 to 85 for LE, -40 to 85 for LI)
PARAMETER SYM.
TEST W26A041 UNIT
CONDITIONS MIN.
MAX.
Operating Power Voltage VDD - 1.65
1.95 V
Input Low Voltage VIL - -0.2 +0.4 V
Input High Voltage VIH - +1.4
VDD +0.2
V
Input Leakage Current ILI VIN = VSS to VDD -1 +1 µA
Output Leakage Current ILO VI/O = VSS to VDD; #CS1 = VIH (min.)
or CS2 = VIL (max.) or #OE = VIH (min.)
or #WE = VIL (max.) -1 +1 µA
Output Low Voltage VOL IOL = +0.1 mA - 0.2 V
Output High Voltage VOH IOH = -0.1 mA 1.4 - V
Operating Power Supply
Current IDD #CS1= VIL (max.) and CS2 = VIH (min.),
I/O = 0 mA; Cycle = min. Duty = 100% - 25 mA
ISB #CS1 = VIH (min.) or CS2 = VIL (max.) - 0.3 mA
Standby Power Supply
Current ISB1 #CS1 ≥ VDD -0.2V, CS2 ≥ VDD -0.2V or
#CS1 ≤ 0.2V, CS2 ≤ 0.2V - 10 µA
Preliminary W26A041
- 4 -
CAPACITANCE
(TA = 25° C, f = 1 MHz)
PARAMETER SYM. CONDITIONS MAX. UNIT
Input Capacitance CIN VIN = 0V 8 pF
Input/Output Capacitance CI/O VOUT = 0V 10 pF
Note: These parameters are sampled but not 100% tested.
AC CHARACTERISTICS
AC Test Conditions
PARAMETER CONDITIONS
Input Pulse Levels 0V to 1.6V
Input Rise and Fall Times 5 nS
Input and Output Timing Reference Level 0.9V
Output Load See the drawing below
AC Test Loads and Waveform
90% 90%
5 nS
10%
5 nS 10%
OUTPUT OUTPUT
1.6V
0V
30 pF
Including
Jig and
Scope
5 pF
Including
Jig and
Scope
1 TTL 1 TTL
CLZ, OLZ, CHZ, OHZ, WHZ, OW
(For T T T T T T )
Preliminary W26A041
Publication Release Date: April 19, 2002
- 5 - Revision A1
AC Characteristics, continued
(VSS = 0V; TA (°C) = -20 to 85 for LE, -40 to 85 for LI)
Read Cycle
PARAMETER SYM. W26A041 UNIT
MIN. MAX.
Read Cycle Time TRC 70 - nS
Address Access Time TAA - 70 nS
Chip Select Access Time TACS - 70 nS
Output Enable to Output Valid TAOE - 35 nS
#UB, #LB Access Tim TBA - 70 nS
Chip Selection to Output in Low Z TCLZ* 10 - nS
Output Enable to Output in Low Z TOLZ* 5 - nS
#UB, #LB Enable to Output in Low Z TBLZ* 5 - nS
Chip Deselection to Output in High Z TCHZ* - 30 nS
Output Disable to Output in High Z TOHZ* - 30 nS
#UB, #LB Disable to Output in High Z TBHZ* - 30 nS
Output Hold from Address Change TOH 10 - nS
∗These parameters are sampled but not 100% tested
Write Cycle
PARAMETER SYM. W26A041 UNIT
MIN. MAX.
Write Cycle Time TWC 70 - nS
Chip Selection to End of Write TCW 60 - nS
Address Valid to End of Write TAW 60 - nS
#UB, #LB Select to End of Write TBW 60 - nS
Address Setup Time TAS 0 - nS
Write Pulse Width TWP 55 - nS
Write Recovery Time #CS1, CS2, #WE TWR 0 - nS
Data Valid to End of Write TDW 40 - nS
Data Hold from End of Write TDH 0 - nS
Write to Output in High Z TWHZ* - 30 nS
Output Disable to Output in High Z TOHZ* - 30 nS
Output Active from End of Write TOW 5 - nS
∗These parameters are sampled but not 100% tested
Preliminary W26A041
- 6 -
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
Address
TRC
TAA
TOH TOH
DOUT
Read Cycle 2
(Chip Select Controlled, #OE = VIL, #WE= VIH)
Address
RC
T
#CS1
TACS TCHZ
#UB / #LB
TCLZ
DTBLZ
OUT
TBHZ
T
#OE
OHZ
TOLZ TBA
TAOE
HIGH-Z
HIGH-Z
CS2
Preliminary W26A041
Publication Release Date: April 19, 2002
- 7 - Revision A1
Timing Waveforms, continued
Read Cycle 3
(Output Enable
Controlled)
Address
TRC
C
#CS1
TAA
#OE
TAOE
TOLZ
TOH
D
TACS
OUT CLZ
TCHZ
TTOHZ
CS2
Write Cycle 1
(#OE Clock)
Address
#OE
TWC
TWR
#CS1 TCW
#WE
D
D
OUT
IN
TAW TWP
TAS
TDW TDH
BW
T
#UB/#LB
CS2
Preliminary W26A041
- 8 -
Timing Waveforms, continued
Write Cycle 2
(#OE = VIL Fixed)
Address
TWC
T T
#CS1
CW WR
TBW
#WE
D
D
TT
T
T
T
T
(2) (3)
T
T
AW
WP
OW
WHZ (1, 4)
DW DH
OH
AS
OUT
IN
#UB/#LB
CS2
Notes:
1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.
2. The data output from DOUT are the same as the data written to DIN during the write cycle.
3. DOUT provides the read data for the next address.
4. Transition is measured ±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.
Preliminary W26A041
Publication Release Date: April 19, 2002
- 9 - Revision A1
DATA RETENTION CHARACTERISTICS
(TA (°C) = -20 to 85 for LE; -40 to 85 for LI)
PARAMETER SYM.
TEST CONDITIONS MIN.
TYP.
MAX.
UNIT
VDD for Data Retention VDR #CS1 ≥ VDD-0.2V or
CS2 ≤ 0.2V 1.5 - - V
Data Retention Current IDDDR
#CS1 ≥ VDD -0.2V or
CS2 ≤ 0.2V, VDD = 3.0V - - 10 µA
Chip Deselect to Data
Retention Time TCDR
See data retention waveform 0 - - nS
Operation Recovery Time TR TRC*
- - nS
* Read Cycle Time
DATA RETENTION WAVEFORM
TCDR
VDD
TR
#CS1
VDR 1.5V
=
>
-0.2V
DD
V
#CS1
=
>
0.9 x DD
V0.9 x DD
V
CS2 CS2 0.2V
=
<
ORDERING INFORMATION
PART NO. ACCESS
TIME
(nS)
OPERATING VOLTAGE (V)
STANDBY CURRENT (µA)
OPERATING
TEMPERATURE
(
°
C) PACKAGE
W26A041B70LE 70 1.8V/10 µA -20 to 85 TFBGA
W26A041H70LE 70 1.8V/10 µA -20 to 85 TSOP(II)
W26A041B70LI 70 1.8V/10 µA -40 to 85 TFBGA
W26A041H70LI 70 1.8V/10 µA -40 to 85 TSOP(II)
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.
Preliminary W26A041
- 10 -
PACKAGE DIMENSIONS
44-pin Standard Type Two TSOP
L
L1
c
E
D
HD
b
eM
0.10 (0.004)
AA1
Y
A
2
θ
1.20
0.05
1.051.00
0.95
0.25
0.12
18.31
10.06
11.56
0.40
0.35 0.45
0.15 0.17
18.41 18.51
10.16 10.26
11.76 11.96
0.50 0.60
0.80
0.10
0.047
0.0410.0390.037
0.010 0.014 0.018
0.005 0.006 0.007
0.721 0.725 0.729
0.396 0.400 0.404
0.455 0.463 0.471
0.80
0.031
0.016 0.020 0.024
0.031
0.004
0.002
Dimension in inches
Min. Nom. Max. Min. Nom. Max.
Symbol
A
A
b
1
2
A
c
D
E
e
L
L
Y1
HD
Dimension in mm
θ0 50 5
oooo
TFBGA
Preliminary W26A041
Publication Release Date: April 19, 2002
- 11 - Revision A1
VERSION HISTORY
VERSION DATE PAGE DESCRIPTION
A1 April 19, 2002 - Initial Issued
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/
Taipei Office
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
Winbond Electronics Corporation America
2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798
Winbond Electronics (H.K.) Ltd.
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
FAX: 852-27552064
Unit 9-15, 22F, Millennium City,
TEL: 852-27513100
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
Winbond Electronics (Shanghai) Ltd.
200336 China
FAX: 86-21-62365998
27F, 2299 Yan An W. Rd. Shanghai,
TEL: 86-21-62365999
Winbond Electronics Corporation Japan
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
FAX: 81-45-4781800
7F Daini-ueno BLDG, 3-7-18
TEL: 81-45-4781881
9F, No.480, Rueiguang Rd.,
Neihu Chiu, Taipei, 114,
Taiwan, R.O.C.
