19-5472; Rev 1; 1/11 TION KIT EVALUA BLE IL AVA A Power-Management ICs for ICERA E400/E450 Platform Features The MAX8982A/MAX8982X are complete power-management ICs for the latest LTE/WCDMA/GSM/GPRS/ EDGE data card based on the new ICERA platform (E400/ E450). The MAX8982A operates from a 4.1V to 5.5V supply and contains four efficient step-down converters, nine low dropout linear regulators (LDOs) to power all RF and baseband circuitry, three current regulators with programmable current up to 24mA and embedded flash timers, and an I2C serial interface to program individual regulator output voltages as well as on/off control for flexibility. The linear regulators provide greater than 60dB PSRR, less than 45FV of output noise, and minimal cross coupling noise between LDOs. S 4 High-Efficiency Buck Converters 0.9V at 1.2A for CORE with DVS Function (0.6V to 1.2V in 25mV Steps) and Slew Rate Control 1.8V at 600mA for System IO 3.2V at 600mA for All LDO Inputs (2.9V to 3.65V in 50mV Steps) (MAX8982A Only) 3.4V at 1.8A for GSM/WCDMA PA (3.0V to 3.75V in 50mV Steps) (MAX8982A Only) The MAX8982X operates from a 2.9V to 5.5V supply. The MAX8982X has the same features as the MAX8982A, except it does not have BUCK3, BUCK4, and LDO8. All buck converters and LDOs are enabled/disabled by either I2C or PWR_REQ control signal after power-up. This feature provides more flexibility in system design. Applications GSM, GPRS, EDGE, WCDMA, and LTE Data Card with New ICERA Platform (E400/E450) Ordering Information PART TEMP RANGE PIN-PACKAGE MAX8982AEWO+T -40C to +85C 42 WLP MAX8982XEWO+T -40C to +85C 42 WLP +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. These devices have a minimum order increment of 1k pieces. S 9 LDO Linear Regulators 2.7V at 300mA on LDO1 for RF Transceiver 1.8V at 150mA on LDO2 for RF Transceiver 2.8V at 150mA on LDO3 for Analogue BB 0.9V at 50mA on LDO4 for BB PLL with the Separate Input for a Higher Efficiency 3.0V at 150mA on LDO5 for SD Card 2.7V at 150mA on LDO6 for TCXO 1.8V or 3.0V at 150mA on LDO7 for SIM 3.0V at 150mA on LDO8 for USB with the Separate Input (MAX8982A Only) 0.9V at 50mA on LDO9 for BB with the Separate Input for a Higher Efficiency S 32 Programmable Voltage Options and External Input on BUCK1 (0.9V Default) for DVS S 16 Programmable Voltage Options for BUCK3 (MAX8982A Only) S 16 Programmable Voltage Options on BUCK4 (MAX8982A Only) S Programmable Voltage Options for All LDOs (LDO8 for MAX8982A Only) S BUCK2, BUCK3 (MAX8982A Only), LDO3, and Internal 32kHz Clock Default On at Initial Startup S Some Buck Converters and LDOs are Enabled by Either I2C or Power Request Control (PWR_REQ) After Power-Up S 3 Current Regulators with 8 Dimming Current Options Up to 24mA with Embedded Flash Timer ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. MAX8982A/MAX8982X General Description MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform Table of Contents General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 General Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Buck1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Buck2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Buck3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Buck4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 OUT1 (LDO1) Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 OUT2 (LDO2) Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 OUT3 (LDO3) Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 OUT4 (LDO4) Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 OUT5 (LDO5) Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 OUT6 (LDO6) Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VSIM (LDO7) Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 OUT8 (LDO8) Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 OUT9 (LDO9) Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 RESET Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 IRQ Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Current Regulator Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Flash Timer Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 N32kHz Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Power-On/Off Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PWR_REQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Active Discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 BUCK1, BUCK2, and BUCK3 Step-Down Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Setting the Output Voltage on BUCK1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Dynamic Voltage Scaling (DVS) Function on Buck 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2 Power-Management ICs for ICERA E400/E450 Platform Ramp-Up/Down Slope Control on BUCK1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Setting the Output Voltage on BUCK2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Setting the Output Voltage on BUCK3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 BUCK4 Step-Down Converter for PA (Power Amplifier) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Setting the Output Voltage on BUCK4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Linear Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Reference Bypass (REFBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Overvoltage Protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Current Regulators (DR1, DR2, DR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Embedded Flash Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 IRQ Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 RESET SIGNAL to B/B Chipset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Chip Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3 MAX8982A/MAX8982X Table of Contents (continued) MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform Table of Contents (continued) List of Figures Figure 1. MAX8982A Typical Application Circuit and Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 2. MAX8982X Typical Application Circuit and Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 3. Power-On/Off State Diagram with IN3 Connected to BUCK2 Output and IN4 Connected to IN1_. Default PWR_REQ Regulators Are Shown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 4. MAX8982A/MAX8982X Power-On Timing Diagram at Initial Startup with EN Connected to IN1_. BUCK3 and OUT8 Are for the MAX8982A Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 5. MAX8982A/MAX8982X Power-On Timing Diagram in PWR_REQ ON Mode After Power-Up . . . . . . . . . . . 37 Figure 6. Frequency Variation vs. Load Current with a 5V Input Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 7. DVS1 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 8. BUCK1 Ramp-Up/Down Slope Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 9. POR State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 10. Adding Series Resistors to Adjust LED Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 11. Flash Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 12. I2C Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 13. START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 14. Master/Slave Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 15. I2C Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 16. I2C Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 17. Writing to the ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 18. Reading from the ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 List of Tables Table 1. Summary of Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 2. External Component List for Figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 3. External Component List for Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 4. BUCK1 Ramp-Up/Down Slope Control Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 6. CHIPID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 7. IRQM Register (Interrupt Mask) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 8. IRQ Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 9. STATUS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 10. LED1FT1 Register (LED1 (DR1) Flash Timer On/Off and TON Adjust) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 11. LED1FT2 Register (LED1 (DR1) Flash Timer t1 Setting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 12. LED1FT3 Register (LED1 (DR1) Flash Timer t2 Setting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 13. LED1FT4 Register (LED1 (DR1) Flash Timer t3 Setting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4 Power-Management ICs for ICERA E400/E450 Platform Table 14. LED1FT5 Register (LED1 (DR1) Flash Timer t4 Setting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 15. LED1FT6 Register (LED1 (DR1) Flash Timer tP Setting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 16. LED2FT1 Register (LED2 (DR2) Flash Timer On/Off and tON Adjust) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 17. LED2FT2 Register (LED2 (DR2) Flash Timer t1 Setting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 18. LED2FT3 Register (LED2 (DR2) Flash Timer t2 Setting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 19. LED2FT4 Register (LED2 (DR2) Flash Timer t3 Setting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 20. LED2FT5 Register (LED2 (DR2) Flash Timer t4 Setting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 21. LED2FT6 Register (LED2 (DR2) Flash Timer tP Setting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 22. LED3FT1 Register (LED3 (DR3) Flash Timer On/Off and tON Adjust) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 23. LED3FT2 Register (LED3 (DR3) Flash Timer t1 Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 24. LED3FT3 Register (LED3 (DR3) Flash Timer t2 Setting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 25. LED3FT4 Register (LED3 (DR3) Flash Timer t3 Setting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 26. LED3FT5 Register (LED3 (DR3) Flash Timer t4 Setting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 27. LED3FT6 Register (LED3 (DR3) Flash Timer tP Setting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 28. BUCK1 Register (On/Off Control for BUCK1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 29. BUCK1DVS1 Register (Output Voltage Setting for BUCK1 (DVS1 = Low)) . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 30. BUCK1DVS2 Register (Output Voltage Setting for BUCK1 (DVS1 = High)) . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 31. BUCK2 Register (On/Off Control for BUCK2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 32. LDO1 Register (On/Off Control for LDO1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 33. LDO1V Register (Output Voltage Setting for OUT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 34. LDO2 Register (ON/OFF Control for LDO2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 35. LDO2V Register (Output Voltage Setting for OUT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 36. LDO3 Register (On/Off Control for LDO3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 37. LDO3V Register (Output Voltage Setting for OUT3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 38. LDO4 Register (On/Off Control for LDO4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 39. LDO4V Register (Output Voltage Setting for OUT4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 40. LDO5 Register (On/Off Control for LDO5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 41. LDO5V Register (Output Voltage Setting for OUT5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 42. LDO6 Register (On/Off Control for LDO6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 43. LDO6V Register (Output Voltage Setting for OUT6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 44. VSIM Register (On/Off Control for VSIM (LDO7)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 45. VSIMV Register (Output Voltage Setting for VSIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 46. LDO8 Register (On/Off Control for LDO8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 47. LDO8V Register (Output Voltage Setting for OUT8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 48. LDO9 Register (On/Off Control for LDO9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 49. LDO9V Register (Output Voltage Setting for OUT9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 50. LED_EN Register (On/Off Control for 3 Current Regulators) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5 MAX8982A/MAX8982X Table of Contents (continued) MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform Table of Contents (continued) Table 51. On/Off Register (On/Off Control for BUCK3, BUCK4, and the Internal 32kHz Clock) . . . . . . . . . . . . . . . . . 64 Table 52. BUCK3 Register (Output Voltage Setting for BUCK3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 53. BUCK4 Register (Output Voltage Setting for BUCK4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 54. CURRENTREG1 Register (Current Setting for Current Regulators DR1 and DR2) . . . . . . . . . . . . . . . . . . . . 66 Table 55. CURRENTREG2 Register (Current Setting for Current Regulator DR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 56. RAMP Register (Slope Setting for BUCK1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 57. BUCK1-4ADIS Register (Active Discharge Settings for BUCK1-BUCK4) . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 58. LDO1-8ADIS Register (Active Discharge Settings for LDO1-LDO8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 59. LDO9ADIS Register (Active Discharge Setting for LDO9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 60. Recommended Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6 Power-Management ICs for ICERA E400/E450 Platform LX1 Continuous Current (Note 1)....................................1200mA LX2, LX3 Continuous Current (Note 1).............................600mA LX4 Continuous Current (Note 1)....................................1800mA Continuous Power Dissipation (TA = +70NC) 7x6 42-Bump WLP, 0.5mm Pitch, 3.75mm x 3.20mm (derate 27.8mW/NC above +70NC).................................2.22W Junction-to-Ambient Thermal Resistance (BJA) (Note 2).........................................................................36NC/W Operating Temperature Range........................... -40NC to +85NC Junction Temperature......................................................+150NC Storage Temperature Range............................. -65NC to +150NC Soldering Temperature (reflow).......................................+260NC Note 1: LX1-LX4 have internal clamp diodes to PGND_, IN1A, and IN1B. Applications that forward bias this diode should take care not to exceed the power dissipation limits of the device. Note 2: Package thermal resistance was obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic/thermal-tutorial. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. General Electrical Characteristics (MAX8982A: VIN1A = VIN1B = +5.0V and COUT1,2,3+CIN_ = 1000FF, MAX8982X: VIN1A = VIN1B = +3.3V and COUT1,2,3+CIN_ = 20FF, CREFBP = 0.1FF, TA = -40NC to +85NC. Typical values are at TA = +25NC, unless otherwise noted.) (Note 3) PARAMETER CONDITIONS IN1A, IN1B, IN4 ESD Protection Module level ESD protection, in-circuit tested with 0.1FF ceramic capacitor Shutdown Supply Current (Note 4) EN = GND No Load Supply Current Loaded Supply Current MIN TYP MAX kV Q10 10 MAX8982A, VEN = VIN1_, BUCK3 and OUT3 on (default output), all other regulators off 300 MAX8982X, VEN = VIN1_, OUT3 on (default output), all other regulators off 300 MAX8982A, VEN = VIN1_, BUCK1 on (default output), BUCK2 on (default output), BUCK3 on (default output), all LDOs (except LDO8) default output ON 600 MAX8982X, VEN = VIN1_, BUCK1 on (default output), BUCK2 on (default output), all LDOs (except LDO8) default output ON 600 MAX8982A, VEN = VIN1_, 32kHz clock on, BUCK2 on (default output) with 200FA load, BUCK3 on (default output), OUT3 on (default output) with 20FA load, OUT2 on (default output) with 100FA load, VVSIM = 3.0V with 50FA load, OUT8 on (default output) with 100FA load 1000 MAX8982X, VEN = VIN1_, 32kHz clock on, BUCK2 on (default output) with 200FA load, OUT3 on (default output) with 20FA load, OUT2 on (default output) with 100FA load, VVSIM = 3.0V with 50FA load 1000 UNITS FA FA FA 7 MAX8982A/MAX8982X Absolute Maximum Ratings VDDA, VDDB, IN4, IN1A, IN1B to GND.....................-0.3V to +6V REFBP, BUCK1, BUCK2, BUCK3, BUCK4, EN to GND................................-0.3V to (VIN1A, VIN1B + 0.3V) SDA, SCL, PWR_REQ, DVS1, IRQ, RESET, IN3, N32kHz to GND............................... -0.3V to (VBUCK2 + 0.3V) OUT1, OUT2 to GND.............................. -0.3V to (VDDA + 0.3V) OUT3, OUT5, OUT6, VSIM to GND........ -0.3V to (VDDB + 0.3V) OUT8 to GND............................................ -0.3V to (VIN4 + 0.3V) OUT4, OUT9 to GND................................ -0.3V to (VIN3 + 0.3V) PGND1, PGND2, PGND3, PGND4 to GND..........-0.3V to +0.3V DR1, DR2, DR3 to GND...........................-0.3V to (VIN1_ + 0.3V) MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform General ELECTRICAL CHARACTERISTICS (continued) (MAX8982A: VIN1A = VIN1B = +5.0V and COUT1,2,3+CIN_ = 1000FF, MAX8982X: VIN1A = VIN1B = +3.3V and COUT1,2,3+CIN_ = 20FF, CREFBP = 0.1FF, TA = -40NC to +85NC. Typical values are at TA = +25NC, unless otherwise noted.) (Note 3) PARAMETER CONDITIONS MIN TYP MAX UNITS OPERATING VOLTAGE IN1A, IN1B Operating Voltage Undervoltage Lockout MAX8982A 4.1 5.5 MAX8982X 2.9 5.5 MAX8982A, VIN1_ rising 3.5 MAX8982A, VIN1_ falling MAX8982X, VIN1_ rising 3.8 4.1 3.5 2.5 2.7 MAX8982X, VIN1_ falling 2.4 VIN1_ rising 5.75 V 2.9 V OVERVOLTAGE LOCKOUT (OVP) Overvoltage Lockout (Shutdown All Outputs Including LDO7) IN1A, IN1B Overvoltage Hysteresis 5.93 V 250 mV 160 NC 10 NC +125 NC THERMAL SHUTDOWN Threshold TJ rising Hysteresis HOT TEMPERATURE DETECTION Threshold Interrupt enabled, TJ rising, typical hysteresis = +10NC REFERENCE REFBP Output Voltage 0 P IREFBP P 1FA 0.788 4.1V P VIN1_ P 5.5V LOGIC AND CONTROL INPUTS (SDA, SCL, EN, DVS1, PWR_REQ) Input Low Level TA = +25NC Input High Level TA = +25NC 1.2 0V < VIN1_ < 5.5V, TA = +25NC -1 Logic Input Current 0.80 0.812 0.2 Supply Rejection 0.3 0V < VIN1_ < 5.5V, TA = +85NC V mV V V +1 0.1 FA LOGIC AND CONTROL OUTPUTS SDA Output Low Level ISDA = 6mA 0.4 V 400 kHz I2C INTERFACE (VSCL = VSDA = 1.8V, Note 2, Figure 16) Clock Frequency Bus Free Time Between START and STOP (tBUF) 1.3 Fs Hold Time Repeated START Condition (tHD_STA) 0.6 Fs SCL Low Period (tLOW) 1.3 Fs SCL High Period (tHIGH) 0.6 Fs Setup Time Repeated START Condition (tSU_STA) 0.6 Fs SDA Hold Time (tHD_DAT) 0 Fs SDA Setup Time (tSU_DAT) 100 ns 8 Power-Management ICs for ICERA E400/E450 Platform (MAX8982A: VIN1A = VIN1B = +5.0V and COUT1,2,3+CIN_ = 1000FF, MAX8982X: VIN1A = VIN1B = +3.3V and COUT1,2,3+CIN_ = 20FF, CREFBP = 0.1FF, TA = -40NC to +85NC. Typical values are at TA = +25NC, unless otherwise noted.) (Note 3) PARAMETER CONDITIONS MIN Maximum Pulse Width of Spikes that Must be Suppressed by the Input Filter of Both SDA and SCL Signals TYP MAX 50 Setup Time for STOP Condition (tSU_STO) UNITS ns 0.6 Fs Buck1 Electrical Characteristics (MAX8982A: VIN1A = VIN1B = +5.0V and COUT1,2,3+CIN_ = 1000F, MAX8982X: VIN1A = VIN1B = +3.3V and COUT1,2,3+CIN_ = 20F, CREFBP = 0.1F, COUT = 10F, L = 2.2H, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER Supply Current (Note 4) CONDITIONS MIN No load, no switching TYP MAX 65 ILOAD = 100mA Output Voltage Accuracy ILOAD = 100mA, VBUCK1 tested at 0.6V, 0.775V, 1V, 1.2V in production (0.6V to 1.2V in 25mV steps) Maximum Output Current VBUCK1 = 0.9V, TA = +25NC 1200 pFET switch 1400 1800 2500 nFET rectifier 1000 1400 1900 On-Resistance -3 0.3 nFET rectifier, ILX1 = 150mA 0.15 Same for both up and down V +3 % mA I 5 RASD1[0:1] = 01 10 RASD1[0:1] = 10 12.5 (default) RASD1[0:1] = 11 25 Rectifier Off Current Threshold 0.927 mA pFET switch, ILX1 = -150mA RASD1[0:1] = 00 Ramp-Up/Down Rate Control 0.9 FA Default Output Voltage Current Limit 0.873 UNITS mV/ Fs 40 mA Minimum On-Time tON 40 ns Minimum Off-Time tOFF 40 ns Efficiency (Note 4) VBUCK1 = 0.9V, ILOAD = 400mA 85 % Shutdown Output Resistance (Active Discharge Resistance) I2C programmable, default OFF 1 kI Output Load Regulation Equal to inductor DC resistance divided by 4 RL/4 V/A 9 MAX8982A/MAX8982X GENERAL ELECTRICAL CHARACTERISTICS (continued) MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform Buck2 Electrical Characteristics (MAX8982A: VIN1A = VIN1B = +5.0V and COUT1,2,3+CIN_ = 1000FF, MAX8982X: VIN1A = VIN1B = +3.3V and COUT1,2,3+CIN_ = 20FF, CREFBP = 0.1FF, COUT = 2.2FF, L = 1FH, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER CONDITIONS MIN TYP MAX Supply Current (Note 4) No load, no switching Output Voltage ILOAD = 100mA Output Current VBUCK2 = 1.8V, TA = +25NC pFET switch 600 700 1100 1500 nFET rectifier 500 750 1200 Current Limit On-Resistance 26 1.746 1.8 FA 1.854 V mA pFET switch, ILX2 = -150mA 0.65 nFET rectifier, ILX2 = 150mA 0.3 Rectifier Off Current Threshold UNITS mA I 40 mA Minimum On-Time tON 70 ns Minimum Off-Time tOFF 70 ns Efficiency (Note 4) VBUCK2 = 1.8V, ILOAD = 250mA 85 % Shutdown Output Resistance (Active Discharge Resistance) I2C programmable, default ON 100 I Output Load Regulation Equal to inductor DC resistance divided by 4 RL/4 V/A Buck3 Electrical Characteristics (MAX8982A only, VIN1A = VIN1B = +5.0V, COUT1,2,3+CIN_ = 1000FF, CREFBP = 0.1FF, COUT = 2.2FF, L = 2.2FH, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER CONDITIONS Supply Current (Note 4) No load, no switching Default Output Voltage ILOAD = 100mA Programmable Output Voltage ILOAD = 100mA, programmable output voltage step = 50mV Maximum Output Current Efficiency (Note 4) 10 VBUCK3 = 3.2V, TA = +25NC VBUCK3 = 3.2V, ILOAD = 300mA MIN TYP MAX 40 3.10 3.2 2.90 2.95 3.00 3.05 3.10 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50 3.55 3.60 3.65 600 UNITS FA 3.29 V V mA 90 % Power-Management ICs for ICERA E400/E450 Platform (MAX8982A only, VIN1A = VIN1B = +5.0V, COUT1,2,3+CIN_ = 1000FF, CREFBP = 0.1FF, COUT = 2.2FF, L = 2.2FH, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER Current Limit On-Resistance CONDITIONS MIN TYP pFET switch 700 1100 1500 nFET rectifier 500 750 1200 pFET switch, ILX3 = -150mA 0.65 nFET rectifier, ILX3 = 150mA 0.3 Rectifier Off Current Threshold MAX UNITS mA I 80 mA Minimum On-Time tON 70 ns Minimum Off-Time tOFF 70 ns Shutdown Output Resistance (Active Discharge Resistance) I2C programmable, default off 1 kI Buck4 Electrical Characteristics (MAX8982A only, VIN1A = VIN1B = +5.0V, COUT1,2,3+CIN_ = 1000FF, CREFBP = 0.1FF, COUT = 20FF, L = 1FH, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER CONDITION Default Output Voltage ILOAD = 100mA Programmable Output Voltage ILOAD = 100mA, programmable output voltage step = 50mV Efficiency (Note 4) VBUCK4 = 3.4V, ILOAD = 500mA Maximum Output Current MIN TYP MAX UNITS 3.298 3.40 3.00 3.05 3.10 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50 3.55 3.60 3.65 3.70 3.75 90 3.502 V V % 1800 p-Channel On-Resistance ILX4 = 150mA n-Channel On-Resistance ILX4 = 150mA mA 100 mI 100 mI p-Channel Current-Limit Threshold 2700 mA n-Channel Negative Current Limit 1500 mA Maximum Duty Cycle 100 % Minimum Duty Cycle 16.5 % PWM Frequency fOSC Shutdown Output Resistance (Active Discharge Resistance) I2C programmable, default off 1.8 2.0 1 2.2 MHz kI 11 MAX8982A/MAX8982X Buck3 ELECTRICAL CHARACTERISTICS (continued) MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform OUT1 (LDO1) Electrical Characteristics (MAX8982A: VDDA = +3.2V and CVDD_ = 10FF, MAX8982X: VDDA = +3.3V and CVDD_ = 20FF, CREFBP = 0.1FF, COUT1 = 4.7FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER Default Output Voltage CONDITION ILOAD = 50mA Maximum Output Current MIN TYP MAX UNITS 2.619 2.70 2.781 V 550 940 100 300 310 mA Current Limit (Note 4) VOUT1 = 90% of its regulation Dropout Voltage (Note 4) ILOAD = 200mA, TA = +85NC 50 mA Line Regulation 2.9V P VDDA P 3.65V, ILOAD = 150mA 1mA < ILOAD < 300mA 2.4 mV mV 12 mV Transient Response di/dt = IMAX/0.1Fs, 1kHz < 1/T < 0.5MHz, where T is the period of step load, 1mA to 300mA 50 mV Power-Supply Rejection DVOUT/DVIN f = 10Hz to 10kHz, ILOAD = 30mA 60 dB Output Noise Voltage 100Hz to 100kHz, ILOAD = 30mA FVRMS Programmable Output Voltages ILOAD = 50mA 45 2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00 Startup Time from Shutdown (Note 4) ILOAD = 300mA 40 100 Fs Startup Transient Overshoot (Note 4) ILOAD = 300mA 3 50 mV Shutdown Output Impedance (Active Discharge Resistance) I2C programmable, default off Load Regulation V 100 I OUT2 (LDO2) Electrical Characteristics (MAX8982A: VDDA = +3.2V and CVDD_ = 10FF, MAX8982X: VDDA = +3.3V and CVDD_ = 20FF, CREFBP = 0.1FF, COUT2 = 1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER Default Output Voltage CONDITION ILOAD = 50mA Maximum Output Current MIN TYP MAX UNITS 1.746 1.80 1.854 V 360 650 mA 300 150 VOUT2 = 90% of its nominal regulation voltage Dropout Voltage (Note 4) ILOAD = 100mA, TA =+85NC 150 Line Regulation 2.9V P VDDA P 3.65V, ILOAD = 100mA 50FA < ILOAD < 150mA 2.4 mV 25 mV Power-Supply Rejection DVOUT/DVIN f = 10Hz to 10kHz, ILOAD = 30mA 60 dB Output Noise Voltage 100Hz to 100kHz, ILOAD = 30mA 45 FVRMS Load Regulation 12 165 mA Current Limit (Note 4) mV Power-Management ICs for ICERA E400/E450 Platform (MAX8982A: VDDA = +3.2V and CVDD_ = 10FF, MAX8982X: VDDA = +3.3V and CVDD_ = 20FF, CREFBP = 0.1FF, COUT2 = 1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER CONDITION MIN TYP 1.50 1.80 2.70 1.70 MAX UNITS Programmable Output Voltages ILOAD = 50mA Startup Time from Shutdown (Note 4) ILOAD = 150mA 40 100 Fs Startup Transient Overshoot (Note 4) ILOAD = 150mA 3 50 mV Shutdown Output Impedance (Active Discharge Resistance) I2C programmable, default off V 100 I OUT3 (LDO3) Electrical Characteristics (MAX8982A: VDDB = +3.2V and CVDD_ = 10FF, MAX8982X: VDDB = +3.3V and CVDD_ = 20FF, CREFBP = 0.1FF, COUT3 = 1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER Default Output Voltage CONDITION ILOAD = 50mA Maximum Output Current MIN TYP MAX 2.716 2.800 2.884 150 165 UNITS V mA Current Limit (Note 4) VOUT3 = 90% of its regulation 360 650 Dropout Voltage ILOAD = 100mA, TA = +85NC 150 300 Line Regulation 3.2V P VDDB P 3.65V, ILOAD = 100mA 2.4 mV Load Regulation 50FA < ILOAD < 150mA 25 mV Power-Supply Rejection DVOUT/DVIN f = 10Hz to 10kHz, ILOAD = 30mA 60 dB Output Noise Voltage 100Hz to 100kHz, ILOAD = 30mA FVRMS Programmable Output Voltage ILOAD = 50mA 45 2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00 Startup Time from Shutdown (Note 4) ILOAD = 150mA 100 Fs Startup Transient Overshoot (Note 4) ILOAD = 150mA 50 mV Shutdown Output Impedance (Active Discharge Resistance) I2C programmable, default off 100 mA mV V I 13 MAX8982A/MAX8982X OUT2 (LDO2) ELECTRICAL CHARACTERISTICS (continued) MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform OUT4 (LDO4) Electrical Characteristics (MAX8982A/MAX8982X: VIN3 = VBUCK2 = 1.8V, CIN3 = 2.2FF, CREFBP = 0.1FF, COUT4 = 2.2FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER Default Output Voltage CONDITION ILOAD = 10mA Maximum Output Current MIN TYP MAX 0.873 0.9 0.927 50 55 UNITS V mA Current Limit (Note 4) VOUT4 = 90% of its regulation 120 220 mA Load Regulation 50FA < ILOAD < 10mA 25 mV Power-Supply Rejection DVOUT/DVIN f = 10Hz to 10kHz, ILOAD = 10mA 60 dB Output Noise Voltage 100Hz to 100kHz, ILOAD = 10mA FVRMS Programmable Output Voltage ILOAD = 10mA 45 0.80 0.90 1.00 1.10 1.20 Startup Time from Shutdown (Note 4) ILOAD = 50mA 100 Fs Startup Transient Overshoot (Note 4) ILOAD = 50mA 50 mV Shutdown Output Impedance (Active Discharge Resistance) I2C programmable, default off V 100 I OUT5 (LDO5) Electrical Characteristics (MAX8982A: VDDB = +3.2V and CVDD_ = 10FF, MAX8982X: VDDB = +3.3V and CVDD_ = 20FF, CREFBP = 0.1FF, COUT5 = 1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER Default Output Voltage CONDITION ILOAD = 50mA Maximum Output Current MIN TYP MAX 2.91 3.00 3.09 150 V mA Current Limit (Note 4) VOUT5 = 90% of its regulation 360 650 mA Dropout Voltage (Note 4) 150 300 mV Line Regulation ILOAD = 100mA, TA = +85NC 3.2V P VDDB P 3.65V, ILOAD = 100mA 2.4 mV Load Regulation 50FA < ILOAD < 150mA, VOUT = 2.8V 25 mV Power-Supply Rejection DVOUT/DVIN f = 10Hz to 10kHz, ILOAD = 30mA 60 dB Output Noise Voltage 100Hz to 100kHz, ILOAD = 30mA FVRMS Programmable Output Voltage ILOAD = 50mA, VDDB = 3.4V for VOUT = 3.2V 45 2.80 2.90 3.00 3.20 Startup Time from Shutdown (Note 4) ILOAD = 150mA 100 Fs Startup Transient Overshoot (Note 4) ILOAD = 150mA 50 mV Shutdown Output Impedance (Active Discharge Resistance) I2C programmable, default off 14 165 UNITS 100 V I Power-Management ICs for ICERA E400/E450 Platform (MAX8982A: VDDB = +3.2V and CVDD_ = 10FF, MAX8982X: VDDB = +3.3V and CVDD_ = 20FF, CREFBP = 0.1FF, COUT6 = 1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER Default Output Voltage CONDITION ILOAD = 50mA Maximum Output Current MIN TYP MAX 2.619 2.70 2.781 150 165 UNITS V mA Current Limit (Note 4) VOUT6 = 90% of its regulation 360 650 mA Dropout Voltage (Note 4) 150 300 mV Line Regulation ILOAD = 100mA, TA = +85NC 2.90V P VDDB P 3.65V, ILOAD = 100mA 2.2 mV Load Regulation 50FA < ILOAD < 150mA 25 mV Power-Supply Rejection DVOUT/DVIN f = 10Hz to 10kHz, ILOAD = 30mA 60 dB Output Noise Voltage 100Hz to 100kHz, ILOAD = 30mA FVRMS Programmable Output Voltage ILOAD = 50mA 45 2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00 Startup Time from Shutdown (Note 4) ILOAD = 150mA 100 Fs Startup Transient Overshoot (Note 4) ILOAD = 150mA 50 mV Shutdown Output Impedance (Active Discharge Resistance) I2C programmable, default off V 100 I VSIM (LDO7) Electrical Characteristics (MAX8982A: VDDB = +3.2V and CVDD_ = 10FF, MAX8982X: VDDB = +3.3V and CVDD_ = 20FF, CREFBP = 0.1FF, COUT = 1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER MIN TYP MAX 50FA < ILOAD < 20mA, 1.8V mode 1.746 1.80 1.854 2.91 3.00 3.09 Maximum Output Current 50FA < ILOAD < 20mA, 3.0V mode (default) 2.9V P VDDB P 3.65V, 1.8V mode Current Limit (Note 4) VVSIM = 90% of 1.8V mode 165 360 650 mA Dropout Voltage (Note 4) ILOAD = 20mA, 3V mode 120 200 mV Line Regulation 0.1 mV Load Regulation 2.9V P VDDB P 3.65V, ILOAD = 50FA (1.8V mode) 50FA < ILOAD < 20mA (1.8V mode) 25 mV Power-Supply Rejection f = 10kHz, ILOAD = 10mA 57 dB Output Noise Voltage 100Hz to 100kHz, ILOAD = 10mA 80 FV VSIM Discharge Resistance (Active Discharge Resistance) I2C programmable, default off 100 I Output Voltage CONDITION 150 UNITS V mA 15 MAX8982A/MAX8982X OUT6 (LDO6) Electrical Characteristics MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform OUT8 (LDO8) Electrical Characteristics (MAX8982A only, VIN4 = VIN1_ = +5.0V, CIN4 = 1.0FF, CREFBP = 0.1FF, COUT8 = 1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER CONDITION Input Operating Range Guaranteed by output voltage accuracy Overvoltage Lockout (Shutdown LDO8 Output) VIN4 rising, VIN1_ = VIN4 MIN 3.0 5.75 Overvoltage Hysteresis Default Output Voltage TYP MAX UNITS 5.5 V 5.93 V 250 ILOAD = 50mA 2.91 Maximum Output Current mV 3.00 3.09 360 650 300 150 mA Current Limit (Note 4) VOUT8 = 90% of its regulation Dropout Voltage (Note 4) 100mA, TA = +85NC 150 Line Regulation 3.4V P VIN4 P 5.5V, VOUT8 = 3.1V, ILOAD = 100mA 50FA < ILOAD < 150mA 2.2 mV 25 mV Power-Supply Rejection DVOUT/DVIN f = 10Hz to 10kHz, ILOAD = 30mA 60 dB Output Noise Voltage (RMS) 100Hz to 100kHz, ILOAD = 30mA FVRMS Programmable Output Voltage ILOAD = 50mA 45 3.00 3.10 3.20 3.30 Startup Time from Shutdown (Note 4) ILOAD = 150mA 100 Fs Startup Transient Overshoot (Note 4) ILOAD = 150mA 50 mV Shutdown Output Impedance (Active Discharge Resistance) I2C programmable, default off Load Regulation 165 V mA mV V 100 I OUT9 (LDO9) Electrical Characteristics (MAX8982A/MAX8982X: VIN3 = VBUCK2 = 1.8V, CIN3 = 2.2FF, CREFBP = 0.1FF, COUT9 = 2.2FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER Default Output Voltage CONDITION ILOAD = 10mA, VIN3 = 1.8V Maximum Output Current MIN TYP MAX 0.873 0.900 0.927 50 V mA Current Limit (Note 4) VOUT9 = 90% of its regulation Load Regulation Power-Supply Rejection DVOUT/DVIN Output Noise Voltage 50FA < ILOAD < 50mA 25 mV f = 10Hz to 10kHz, ILOAD = 10mA 60 dB 100Hz to 100kHz, ILOAD = 10mA FVRMS Programmable Output Voltage ILOAD = 10mA 45 0.80 0.90 1.00 1.10 1.20 Startup Time from Shutdown (Note 4) ILOAD = 50mA 16 55 UNITS 120 220 mA V 100 Fs Power-Management ICs for ICERA E400/E450 Platform (MAX8982A/MAX8982X: VIN3 = VBUCK2 = 1.8V, CIN3 = 2.2FF, CREFBP = 0.1FF, COUT9 = 2.2FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER Startup Transient Overshoot (Note 4) Shutdown Output Impedance (Active Discharge Resistance) CONDITION MIN TYP ILOAD = 50mA I2C programmable, default off MAX UNITS 50 mV 100 I RESET Electrical Characteristics (MAX8982A: VIN1A = VIN1B = +5V, MAX8982X: VIN1A = VIN1B = +3.3V, VBUCK2 = 1.8V, CBUCK2 = 2.2FF, CREFBP = 0.1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER CONDITION Output High Voltage Internal logic supply ISOURCE = 0FA Output Low Voltage RESET Enabled (Note 4) Internal logic supply ISINK = 500FA From BUCK2 enable (Figure 4) RESET Disabled (Note 4) With respect to IRQ = low Pullup Resistance to BUCK2 MIN TYP MAX VBUCK2 - 0.3V V 0.3 625 26 8 UNITS 14 V Fs 78 Fs 22 kI IRQ Electrical Characteristics (MAX8982A: VIN1A = VIN1B = +5.0V, MAX8982X: VIN1A = VIN1B = +3.3V, VBUCK2 = 1.8V, CBUCK2 = 2.2FF, CREFBP = 0.1FF, TA = -40NC to +85NC. Typical values are at TA = +25NC, unless otherwise specified.) (Note 3) PARAMETER CONDITION Output High Voltage Internal logic supply ISOURCE = 0FA Output Low Voltage Internal logic supply ISINK = 500FA Pullup Resistance to BUCK2 MIN TYP MAX VBUCK2 - 0.3V 100 UNITS V 200 0.3 V 400 kI Current Regulator Electrical Characteristics (MAX8982A: VIN1A = VIN1B = +5V and VDD_ = 3.2V, MAX8982X: VIN1A = VIN1B = +3.3V and VDD_ = 3.3V, CREFBP = 0.1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER CONDITION DR_ Sink Current Range DR_ Current Sink Programmable MIN TYP 3 DR_[2:0] = 000 3 DR_[2:0] = 001 6 DR_[2:0] = 010 9 DR_[2:0] = 011 12 DR_[2:0] = 100 15 DR_[2:0] = 101 18 DR_[2:0] = 110 21 DR_[2:0] = 111 (default) 24 MAX UNITS 24 mA mA DR_ Sink Current Accuracy (Note 4) TA = +25NC -10 +10 TA = -40NC to +85NC -15 +15 VDR_ Voltage Drop IDR_ = 24mA 60 120 % mV 17 MAX8982A/MAX8982X OUT9 (LDO9) ELECTRICAL CHARACTERISTICS (continued) MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform Flash Timer Electrical Characteristics (MAX8982A: VIN1A = VIN1B = +5V and VDD_ = +3.2V, MAX8982X: VIN1A = VIN1B = +3.3V and VDD_ = +3.3V, CREFBP = 0.1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 4, Figure 11) PARAMETER CONDITIONS MIN Flash Timer Resolution TYP 0 Pattern Period, tP 7-bit programmable in 25ms steps 7-bit programmable in 25ms steps 7-bit programmable in 25ms steps 0 18 7-bit programmable in 25ms steps ms 3175 0 (0000000) 25 (0000001) 50 . . 3175 (1111111) 7-bit programmable in 25ms steps ms 3175 0 (0000000) 25 (0000001) 50 . . 3175 (1111111) 0 Time for Flash to Turn On, t4 ms 3175 0 (0000000) 25 (0000001) 50 . . 3175 (1111111) 0 Time for Flash to Turn On, t3 3175 4 0 Time for Flash to Turn On, t2 UNITS ms 0 (0000000) 25 (0000001) 50 75 . . 3175 (1111111) Number of Programmable On Threshold Time for Flash to Turn On, t1 MAX 25 ms 3175 0 (0000000) 25 (0000001) 50 . . 3175 (1111111) ms Power-Management ICs for ICERA E400/E450 Platform (MAX8982A: VIN1A = VIN1B = +5V and VDD_ = +3.2V, MAX8982X: VIN1A = VIN1B = +3.3V and VDD_ = +3.3V, CREFBP = 0.1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 4, Figure 11) PARAMETER CONDITIONS MIN TYP 25 Programmable On-Time, tON MAX 25 (0000) 50 (0001) 75 . . 400 (1111) 4-bit programmable in 25ms steps, same for each flash timer UNITS 400 ms N32kHz Electrical Characteristics (MAX8982A: VDD_ = +3.2V, MAX8982X: VDD_ = +3.3V, VBUCK2 = 1.8V, CBUCK2 = 2.2FF, CREFBP = 0.1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER CONDITION MIN Output High Voltage Internal logic supply ISOURCE = 2mA Output Low Voltage Internal logic supply ISINK = 2mA Including initial startup, 20% tolerance Startup Time From BUCK2 enable (Figure 4) MAX VBUCK2 - 0.45V Output Duty Cycle Output Frequency Range TYP UNITS V 0.45 V 30 50 70 % 25.6 32 38.4 kHz 225 Fs 10 ns Edge Jitter (Note 4) Note 3: Limits are 100% production tested at TA = +25NC, unless otherwise noted. Limits over the temperature range are guaranteed by design. Note 4: Guaranteed by design, not production tested. Typical Operating Characteristics (MAX8982A: VIN1A = VIN1B = 5V, MAX8982X: VIN1A = VIN1B = VDDA = VDDB = VIN4 = 3.3V, CREFBP = 0.1F, TA = -40C to +85C, Circuits of Figures 2 and 3, unless otherwise noted. Typical values are at TA = +25C. Limits are 100% production tested at TA = +25NC, unless otherwise noted. Limits over the temperature range are guaranteed by design.) 2.5 2.0 1.5 1.0 0.5 3.0 2.5 2.0 1.5 1.0 4.5 5.0 INPUT VOLTAGE (V) 5.5 260 240 220 200 180 160 120 100 0 4.0 BUCK3, OUT3 ON ALL OTHER OUTPUTS OFF 280 140 0.5 0 MAX8982A toc03 3.5 300 SHUTDOWN CURRENT (A) 3.0 MAX8982A toc02 SHUTDOWN CURRENT (A) 3.5 4.0 SHUTDOWN CURRENT (A) MAX8982A toc01 4.0 NO LOAD SUPPLY CURRENT vs. INPUT VOLTAGE (MAX8982A) SHUTDOWN CURRENT vs. INPUT VOLTAGE (MAX8982X) SHUTDOWN CURRENT vs. INPUT VOLTAGE (MAX8982A) 3.0 3.5 4.0 4.5 INPUT VOLTAGE (V) 5.0 5.5 4.0 4.5 5.0 5.5 INPUT VOLTAGE (V) 19 MAX8982A/MAX8982X Flash Timer Electrical Characteristics (continued) Typical Operating Characteristics (continued) (MAX8982A: VIN1A = VIN1B = 5V, MAX8982X: VIN1A = VIN1B = VDDA = VDDB = VIN4 = 3.3V, CREFBP = 0.1F, TA = -40C to +85C, Circuits of Figures 2 and 3, unless otherwise noted. Typical values are at TA = +25C. Limits are 100% production tested at TA = +25NC, unless otherwise noted. Limits over the temperature range are guaranteed by design.) NO LOAD SUPPLY CURRENT vs. INPUT VOLTAGE (MAX8982X) BUCK1 LOAD REGULATION L = 2.2H, HITACHI METALS LTD KSLI-252012AG-2R2 DCR = 100mI 0.925 OUTPUT VOLTAGE (V) SHUTDOWN CURRENT (uA) 260 240 220 200 180 160 140 MAX8982A toc05 OUT3 ON ALL OTHER OUTPUTS OFF 280 0.950 MAX8982A toc04 300 0.900 0.875 0.850 0.825 120 100 3.5 4.0 4.5 5.0 0.800 5.5 200 0 700 1200 INPUT VOLTAGE (V) LOAD CURRENT (mA) BUCK1 LOAD TRANSIENT BUCK1 EFFICIENCY vs. LOAD CURRENT 100 MAX8982A toc06 VIN = 4.5V 90 AC-COUPLED 200mV/div 1.2A VIN = 4.1V 80 EFFICIENCY (%) VBUCK1 MAX8982A toc07 3.0 70 60 VIN = 5V 50 VOUT = 1V COUT = 10F IBUCK1 40 1mA VIN = 5.5V VOUT = 0.9V 30 1 100s/div 10 1000 100 LOAD CURRENT (mA) BUCK1 SWITCHING FREQUENCY vs. TEMPERATURE BUCK1 SWITCHING FREQUENCY vs. LOAD CURRENT 1.5 1.0 0.5 MAX8982A toc09 2.0 2.200 2.150 SWITCHING FREQUENCY (MHz) MAX8982A toc08 2.5 SWITCHING FREQUENCY (MHz) MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform 2.100 2.050 2.000 1.950 1.900 1.850 1.800 1.750 0 0 200 700 LOAD CURRENT (mA) 20 1200 -40 -15 10 35 TEMPERATURE (C) 60 85 Power-Management ICs for ICERA E400/E450 Platform (MAX8982A: VIN1A = VIN1B = 5V, MAX8982X: VIN1A = VIN1B = VDDA = VDDB = VIN4 = 3.3V, CREFBP = 0.1F, TA = -40C to +85C, Circuits of Figures 2 and 3, unless otherwise noted. Typical values are at TA = +25C. Limits are 100% production tested at TA = +25NC, unless otherwise noted. Limits over the temperature range are guaranteed by design.) BUCK1 RAMP-UP TRANSITION BUCK1 RAMP-DOWN TRANSITION MAX8982A toc10 MAX8982A toc11 1.2V VBUCK1 1.2V VBUCK1 0.6V 0.6V NO LOAD 12.5mV/s RAMP RATE IOUT = 1.2A 12.5mV/s RAMP RATE 20s/div 20s/div BUCK2 LOAD REGULATION BUCK2 LOAD TRANSIENT 1.800 OUTPUT VOLTAGE (V) MAX8982A toc13 MAX8982A toc12 1.820 AC-COUPLED 100mV/div VBUCK2 1.780 1.760 600mA 1.740 IBUCK2 L = 1.0H, MURATA LQM2MPN1R0NG0 DCR = 85mI 1.720 0 200 400 1mA VOUT = 1.8V 40s/div 600 LOAD CURRENT (mA) VIN = 4.1V EFFICIENCY (%) 90 3.300 80 VIN = 5V 70 VIN = 5.5V 60 L = 2.2H, HITACHI METALS LTD KSLI-252012AG-2R2 DCR = 100mI 3.250 OUTPUT VOLTAGE (V) VIN = 4.5V MAX8982A toc14 100 MAX8982A toc15 BUCK3 LOAD REGULATION (MAX8982A ONLY) BUCK2 EFFICIENCY vs. LOAD CURRENT 3.200 3.150 3.100 3.050 50 3.000 40 1 10 100 LOAD CURRENT (mA) 1000 0 100 200 300 400 500 600 LOAD CURRENT (mA) 21 MAX8982A/MAX8982X Typical Operating Characteristics (continued) Typical Operating Characteristics (continued) (MAX8982A: VIN1A = VIN1B = 5V, MAX8982X: VIN1A = VIN1B = VDDA = VDDB = VIN4 = 3.3V, CREFBP = 0.1F, TA = -40C to +85C, Circuits of Figures 2 and 3, unless otherwise noted. Typical values are at TA = +25C. Limits are 100% production tested at TA = +25NC, unless otherwise noted. Limits over the temperature range are guaranteed by design.) MAX8982A toc16 100 VOUT = 3.2V COUT = 10F AC-COUPLED 100mV/div 90 EFFICIENCY (%) VBUCK3 85 VIN = 5V 80 VIN = 5.5V 75 70 65 600mA IBUCK3 VIN = 4.5V VIN = 4.1V 95 MAX8982A toc17 BUCK3 EFFICIENCY vs. LOAD CURRENT (MAX8982A ONLY) BUCK3 LOAD TRANSIENT (MAX8982A ONLY) 60 1mA 55 VOUT = 3.2V 50 1 20s/div 10 100 1000 LOAD CURRENT (mA) BUCK4 LOAD REGULATION (MAX8982A ONLY) BUCK4 LOAD TRANSIENT (MAX8982A ONLY) MAX8982A toc19 MAX8982A toc18 3.410 OUTPUT VOLTAGE (V) 3.400 3.390 AC-COUPLED 50mV/div VBUCK4 3.380 3.370 3.360 1.5A 3.350 L = TAIYO YUDEN NR3015T1R0N DCR = 30mI 3.340 IBUCK4 0 100 200 300 400 500 1mA VOUT = 3.4V 1mA TO 1.5A 3.330 600 20s/div LOAD CURRENT (mA) BUCK4 EFFICIENCY vs. LOAD CURRENT (MAX8982A ONLY) 70 VIN = 4.5V 60 VIN = 5V 50 VIN = 5.5V 40 30 20 VOUT = 3.4V 10 1 10 100 1000 LOAD CURRENT (mA) 22 10,000 MAX8982A toc21 VIN = 4.1V 2.5 SWITCHING FREQUENCY (MHz) 90 80 BUCK4 SWITCHING FREQUENCY vs. LOAD CURRENT (MAX8982A ONLY) MAX8982A toc20 100 EFFICIENCY (%) MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform 2.0 1.5 1.0 0.5 0 0 200 400 LOAD CURRENT (mA) 600 Power-Management ICs for ICERA E400/E450 Platform (MAX8982A: VIN1A = VIN1B = 5V, MAX8982X: VIN1A = VIN1B = VDDA = VDDB = VIN4 = 3.3V, CREFBP = 0.1F, TA = -40C to +85C, Circuits of Figures 2 and 3, unless otherwise noted. Typical values are at TA = +25C. Limits are 100% production tested at TA = +25NC, unless otherwise noted. Limits over the temperature range are guaranteed by design.) BUCK4 SWITCHING FREQUENCY vs. TEMPERATURE (MAX8982A ONLY) 2.00 1.95 2.702 2.701 2.700 1.90 2.699 1.85 2.698 1.80 2.697 -15 -40 10 35 60 85 1.806 1.804 1.802 1.800 1.798 1.796 1.792 1.790 50 100 150 200 250 50 0 300 LDO3 LOAD REGULATION 150 LDO4 LOAD REGULATION OUTPUT VOLTAGE (V) 2.810 2.805 2.800 MAX8982A toc26 0.903 MAX8982A toc25 2.815 100 LOAD CURRENT (mA) LOAD CURRENT (mA) 2.820 OUTPUT VOLTAGE (V) 1.808 1.794 0 TEMPERATURE (C) 1.810 OUTPUT VOLTAGE (V) 2.05 2.703 MAX8982A toc24 2.704 OUTPUT VOLTAGE (V) 2.10 LDO2 LOAD REGULATION 1.812 MAX8982A toc23 2.15 0.902 2.795 2.790 0.901 0 50 100 150 0 LDO5 LOAD REGULATION 30 40 50 LDO6 LOAD REGULATION 3.000 2.990 2.980 MAX8982A toc28 2.715 OUTPUT VOLTAGE (V) 3.010 20 2.720 MAX8982A toc27 3.020 10 LOAD CURRENT (mA) LOAD CURRENT (mA) OUTPUT VOLTAGE (V) SWITCHING FREQUENCY (MHz) LDO1 LOAD REGULATION 2.705 MAX8982A toc22 2.20 2.710 2.705 2.700 2.695 2.970 2.690 2.960 0 50 100 LOAD CURRENT (mA) 150 0 50 100 150 LOAD CURRENT (mA) 23 MAX8982A/MAX8982X Typical Operating Characteristics (continued) Typical Operating Characteristics (continued) (MAX8982A: VIN1A = VIN1B = 5V, MAX8982X: VIN1A = VIN1B = VDDA = VDDB = VIN4 = 3.3V, CREFBP = 0.1F, TA = -40C to +85C, Circuits of Figures 2 and 3, unless otherwise noted. Typical values are at TA = +25C. Limits are 100% production tested at TA = +25NC, unless otherwise noted. Limits over the temperature range are guaranteed by design.) LDO8 LOAD REGULATION (MAX8982A ONLY) LDO7 LOAD REGULATION 3.015 3.010 OUTPUT VOLTAGE (V) 3.015 MAX8982A toc30 3.020 3.010 3.005 3.000 3.005 3.000 2.995 2.995 2.990 2.990 2.985 2.985 20 40 60 80 0 100 20 40 60 80 LOAD CURRENT (mA) LOAD CURRENT (mA) LDO9 LOAD REGULATION LED CURRENT ACCURACY vs. LED CURRENT SETTING MAX8982A toc31 0.902 100 10 LUMEX SML-LX2832SISUGSBC LED CURRENT ACCURACY (%) 0 8 MAX8982A toc32 OUTPUT VOLTAGE (V) 3.020 MAX8982A toc29 3.025 OUTPUT VOLTAGE (V) MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform 6 LED3 4 2 0 LED2 -2 -4 0.900 0 20 40 60 80 0 100 5 10 15 25 OVERVOLTAGE PROTECTION LED FLASH WAVEFORMS MAX8982A toc34 MAX8982A toc33 5V/div VIN_ 24mA 0V 1V/div VBUCK1 0A ILED2 20 LED CURRENT (mA) LOAD CURRENT (mA) 24mA 0V VBUCK2 1V/div 0V ILED3 0A VLDO1 2V/div 0V 1s/div 24 400s/div Power-Management ICs for ICERA E400/E450 Platform TOP VIEW (BUMP ON BOTTOM) MAX8982A 1 2 3 4 5 6 7 A N32 kHz OUT9 GND REF BP OUT6 OUT3 OUT2 B OUT4 DR1 DR2 OUT8 VSIM VDDB VDDA C IN3 DR3 RESET OUT5 SCL IRQ OUT1 D LX2 BUCK2 DVS1 SDA PWR_ REQ BUCK3 LX3 E PGND2 BUCK1 EN IN1B LX4 BUCK4 PGND3 F PGND1 LX1 IN4 IN1A LX4 PGND4 PGND4 WLP 25 MAX8982A/MAX8982X Pin Configurations Power-Management ICs for ICERA E400/E450 Platform MAX8982A/MAX8982X Pin Configurations (continued) TOP VIEW (BUMP ON BOTTOM) MAX8982X 1 2 3 4 5 6 7 A N32 kHz OUT9 GND REF BP OUT6 OUT3 OUT2 B OUT4 DR1 DR2 DNC VSIM VDDB VDDA C IN3 DR3 RESET OUT5 SCL IRQ OUT1 D LX2 BUCK2 DVS1 SDA PWR_ REQ DNC DNC E PGND2 BUCK1 EN IN1B DNC DNC PGND3 F PGND1 LX1 IN4 IN1A DNC PGND4 PGND4 WLP 26 Power-Management ICs for ICERA E400/E450 Platform PIN NAME MAX8982A MAX8982X FUNCTION GROUND A3 GND GND F1 PGND1 PGND1 Power Ground for BUCK1 Analog Ground E1 PGND2 PGND2 Power Ground for BUCK2 E7 PGND3 PGND3 Power Ground for BUCK3 F6, F7 PGND4 PGND4 Power Ground for BUCK4 INPUT SUPPLY Input Supply to the IC. The operating voltage range for the MAX8982A is 4.1V to 5.5V. Connect three 330FF tantalum capacitors as close as possible to IN1A and IN1B. Connect IN1A to IN1B. IN1A -- -- IN1A Input Supply to the IC. The operating voltage range for the MAX8982X is 2.9V to 5.5V. Bypass with a 22FF ceramic capacitor as close as possible to IN1A and IN1B. Connect IN1A to IN1B. E4 IN1B IN1B Input Supply to the IC. Connect IN1B to IN1A. C1 IN3 IN3 IN4 -- -- IN4 VDDA -- -- VDDA F4 F3 B7 VDDB B6 -- BUCK CONVERTERS -- VDDB Input Supply for LDO4 and LDO9. Connect IN3 to the BUCK2 output. Bypass IN3 with a 2.2FF ceramic capacitor as close as possible to IN3. Input Supply for LDO8. Bypass with a 1FF ceramic capacitor as close as possible to IN4. The IN4 operating range is from 3.0V to 5.5V. Connect IN4 to either IN1A and IN1B. Connect IN4 to Both IN1A and IN1B Power Input for LDO1 and LDO2. Connect VDDA to VDDB. Bypass VDDA with a 10FF ceramic capacitor as close as possible to VDDA. Power Input for LDO1 and LDO2. Connect VDDA to VDDB, IN1A, and IN1B. Power Input for LDO3, LDO5, LDO6, and LDO7. Connect VDDB to VDDA. Power Input for LDO3, LDO5, LDO6, and LDO7. Connect VDDB to VDDA, IN1A, and IN1B. F2 LX1 LX1 BUCK1 Inductor Connection. LX1 connects to the drains of the internal p-channel and n-channel MOSFETs. D1 LX2 LX2 BUCK2 Inductor Connection. LX2 connects to the drains of the internal p-channel and n-channel MOSFETs. LX3 -- BUCK3 Inductor Connection. LX3 connects to the drains of the internal p-channel and n-channel MOSFETs. -- DNC LX4 -- -- BUCK1 BUCK2 BUCK3 -- BUCK4 -- DNC BUCK1 BUCK2 -- DNC -- DNC D7 E5, F5 E2 D2 D6 E6 Do Not Connect BUCK4 Inductor Connection. LX4 connects to the drains of the internal p-channel and n-channel MOSFETs. Connect the two LX4 bumps together externally. Do Not Connect BUCK1 Output Feedback BUCK2 Output Feedback BUCK3 Output Feedback Do Not Connect BUCK4 Output Feedback Do Not Connect 27 MAX8982A/MAX8982X Pin Description MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform Pin Description (continued) NAME MAX8982A MAX8982X LDO REGULATORS PIN FUNCTION C7 OUT1 OUT1 LDO1 Output. Bypass OUT1 with a 4.7FF ceramic capacitor. OUT1 supplies loads up to 300mA. The default output voltage is 2.7V. A7 OUT2 OUT2 LDO2 Output. Bypass OUT2 with a 1FF ceramic capacitor. OUT2 supplies loads up to 150mA. The default output voltage is 1.8V. A6 OUT3 OUT3 LDO3 Output. Bypass OUT3 with a 1FF ceramic capacitor. OUT3 supplies loads up to 150mA. The default output voltage is 2.8V. B1 OUT4 OUT4 LDO4 Output. Bypass OUT4 with a 2.2FF ceramic capacitor. OUT4 supplies loads up to 50mA. The default output voltage is 0.9V. C4 OUT5 OUT5 LDO5 Output. Bypass OUT5 with a 1FF ceramic capacitor. OUT5 supplies loads up to 150mA. The default output voltage is 3.0V. A5 OUT6 OUT6 LDO6 Output. Bypass OUT6 with a 1FF ceramic capacitor. OUT6 supplies loads up to 150mA. The default output voltage is 2.7V. B5 VSIM VSIM LDO7 Output. Bypass VSIM with a 1FF ceramic capacitor. VSIM supplies loads up to 150mA. The default output voltage is 3V. OUT8 -- LDO8 Output. Bypass OUT8 with a 1FF ceramic capacitor. OUT8 supplies loads up to 150mA. The default output voltage is 3V. -- DNC Do Not Connect OUT9 OUT9 LDO9 Output. Bypass OUT9 with a 2.2FF ceramic capacitor. OUT9 supplies loads up to 50mA. The default output voltage is 0.9V. D4 SDA SDA I2C Data. SDA is high impedance when off. C5 SCL SCL I2C Clock. SCL is high impedance when off. DR1 Current Regulated Driver 1. Typically used to drive an LED. DR1 can be programmed to sink 3mA to 24mA in 8 steps (24mA default). If the flash timer is activated, the LED can be programmed to turn on/off in a preprogrammed pattern. See the Embedded Flash Timer section. DR2 Current Regulated Driver 2. Typically used to drive an LED. DR2 can be programmed to sink 3mA to 24mA in 8 steps (24mA default). If the flash timer is activated, the LED can be programmed to turn on/off in a preprogrammed pattern. See the Embedded Flash Timer section. DR3 DR3 Current Regulated Driver 3. Typically used to drive an LED. DR3 can be programmed to sink 3mA to 24mA in 8 steps (24mA default). If the flash timer is activated, the LED can be programmed to turn on/off in a preprogrammed pattern. See the Embedded Flash Timer section. EN EN B4 A2 I2C INTERFACE CURRENT REGULATORS B2 DR1 B3 DR2 C2 LOGIC INPUTS E3 D5 D3 28 PWR_REQ PWR_REQ DVS1 DVS1 Active-High IC Enable Input Active-High to Enable All Designated Step-Down Regulators and LDOs in Sequence. Active-high/low to enable/disable all step-down converters and LDOs after power-on. The values in the BUCK1DVS1 and BUCK1DVS2 registers are reset to their defaults when PWR_REQ goes low in normal operation. BUCK1 Output Selection Input for DVS Function Power-Management ICs for ICERA E400/E450 Platform NAME MAX8982A MAX8982X LOGIC OUTPUTS PIN C6 IRQ C3 RESET REFERENCE OUTPUT A4 FUNCTION IRQ RESET Active-Low, Open-Drain Interrupt Output. Internal pullup resistor, 200kI, to BUCK2. Active-Low, Open-Drain Reset Output. There is an internal 14kI pullup resistor to BUCK2. REFBP REFBP Reference Bypass. Connect the reference bypass capacitor from REFBP to GND. See Table 3. High impedance in off condition. VREFBP is 0.8V (typ). Do not use to provide power to external circuitry. N32kHz N32kHz 32kHz Clock Output. This output is supplied from BUCK2. 32kHz CLOCK A1 Table 1. Summary of Power Supplies BUCK2 Function Core System IO LDO INPUT PA RF RF Analog PLL SD TCXO SIM USB BB 0.9 1.8 3.2 3.4 2.7 1.8 2.8 0.9 3.0 2.7 3.00 3.0 0.9 1200 600 600 1800 300 150 150 50 150 150 150 150 50 0.600 N/A 2.90 3.00 2.65 1.5 2.65 0.8 2.80 2.65 1.80 3.00 0.8 2.95 3.05 2.70 1.8 2.70 0.9 2.90 2.70 3.00 3.10 0.9 3.00 3.10 2.75 2.7 2.75 1.0 3.00 2.75 3.20 1.0 3.05 3.15 2.80 1.7 2.80 1.1 3.20 2.80 3.30 1.1 3.10 3.20 2.85 2.85 1.2 3.15 3.25 2.90 2.90 2.90 3.20 3.30 2.95 2.95 2.95 3.00 3.00 3.00 Default Voltage (V) Continuous Output Current (mA) Programmable Voltage Options (V) 25mV step 1.20 BUCK3* BUCK4* OUT1 OUT2 3.25 3.35 3.30 3.40 3.35 3.45 3.40 3.50 3.45 3.55 3.50 3.60 3.55 3.65 3.60 3.70 3.65 3.75 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8* OUT9 (VSIM) PARAMETER BUCK1 2.85 1.2 *BUCK3, BUCK4, and OUT8 are for the MAX8982A only. 29 MAX8982A/MAX8982X Pin Description (continued) MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform Table 1. Summary of Power Supplies (continued) PARAMETER BUCK1 BUCK2 BUCK3* BUCK4* OUT1 OUT2 OUT3 Default ON at Initial Startup PWR_ REQ ON ON OFF PWR_ PWR_ REQ REQ ON ON/OFF Control After Power-Up I2C or PWR_ REQ I2C or PWR_ REQ I2C or PWR_ REQ I2C or PWR_ REQ I 2C I2C or or PWR_ PWR_ REQ REQ I2C or PWR_ REQ OFF ON OFF OFF Default Active Discharge Resistor *BUCK3, BUCK4, and OUT8 are for the MAX8982A only. 30 OFF OFF OFF OUT7 OUT8* OUT9 (VSIM) OUT4 OUT5 OUT6 PWR_ REQ PWR_ REQ OFF I2C or PWR_ REQ I2C or PWR_ REQ OFF OFF OFF I 2C I2C or or PWR_ PWR_ REQ REQ OFF OFF ON ON I2C I2C or or PWR_ PWR_ REQ REQ OFF OFF Power-Management ICs for ICERA E400/E450 Platform IN1_ ON/OFF SEQUENCE STEP-DOWN CONVERTER 4 (1.8A) OVP 330F * 3 SHUTDOWN SIGNAL LX4 0.9V 3.4V (DEFAULT) 3.0V TO 3.75V IN 50mV STEPS 2.2F GSM PA/ UMTS PA PGND4 PGND4 GND BB 2.2H N 5.75V REFBP LX4 P 3.8V IN1B 0.1F IN1A UVLO IN1A 5V DD+ G MAX8982A/MAX8982X USB INPUT BUCK4 IN3 OUT9 IN1A 2.2F P LDO9 (50mA) STEP-DOWN DC-DC 1 CONVERTER (1.2A) IN1B N UVLO (3.8V) LX1 REF (0.8V) 2.2H 0.9V (DEFAULT) 0.6V TO 1.2V IN 25mV STEPS CORE 2.2F N PGND1 BUCK1 VDDB 2.7V TCXO OUT6 1F THERMAL SHUTDOWN +160C DVS1 LDO6 (50mA) P 1H LX2 STEP-DOWN DC-DC 2 CONVERTER (DEFAULT ON, 600mA) N ON/OFF SEQUENCE DCDC 1 SEL IN1A VCC_IO PGND2 BUCK2 16ms TIMER IN3 SHUTDOWN SIGNAL BB CHIPSET ICE8060 ON E400 PLATFORM 2.2F OUT4 IN1_ 1.8V 2.2F N EN N 200kI BB CHIPSET ICE 8060 ON E400 PLATFORM IRQ INTERRUPT ON/OFF CONTROL AND I2C INTERFACE SDA SDA BUCK2 625s 14kI POR_N RTBON IN1A SCL P STEP-DOWN DC-DC 3 CONVERTER (DEFAULT ON) PWR_REQ PWR_REQ BUCK2 RESET RESET SCL PLL 2.2F LDO4 (50mA) BUCK2 0.9V LX3 2.2H 3.2V (DEFAULT) 2.9V TO 3.65V IN 50mV STEPS 2.2F N PGND3 IN1_ BUCK3 IN4 1F VDDB INPUT 3.0V HS USB TRANSCEIVER VDDA LDO MAX8982A 10F 2.8V OUT3 OUT8 1F LDO8 (DEFAULT ON) 150mA REF VDDB LDO3 DEFAULT ON 150mA ANALOG BASEBAND 1F N N 1.8V OUT2 32kHz OSCILLATOR VDDA 1F LDO2 (150mA) RF1V8 RF CHIPSET ICE 8260 N BUCK2 OUT1 N32kHz BB OSC 32kI VDDA LDO1 (300mA) IN1_ DR1 DR2 3-CHANNEL CURRENT REGULATOR (24mA, DEFAULT) 2.7V N 3.0V OUT5 FLASH TIMER VDDB N VSIM VDDB (3--24mA IN 3mA STEPS) SD CARD 1F LDO5 (150mA) DR3 OPTIONAL RESISTORS RF2V7 4.7F 1.8V/3.0V SIM LDO (LDO7) 150mA USIM 1F N Figure 1. MAX8982A Typical Application Circuit and Functional Block Diagram 31 MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform Table 2. External Component List for Figure 1 LOCATION IN1A, IN1B EXTERNAL COMPONENTS NOTES IN3 3 x 330FF tantalum capacitors 2.2FF Buck stability and GSM PA supply IN4 1.0FF Input for LDO8 OUT1 4.7FF LDO compensation and load transient response OUT2 1.0FF LDO compensation OUT3 1.0FF LDO compensation OUT4 2.2FF LDO compensation OUT5 1.0FF LDO compensation OUT6 1.0FF LDO compensation VSIM (OUT7) 1.0FF LDO compensation OUT8 1.0FF LDO compensation OUT9 2.2FF LDO compensation VDDA, VDDB Total capacitance R total output capacitance for LDO1, LDO2, LDO3, LDO5, LDO6, and VSIM. Use a 10FF capacitor on VDDA/VDDB as recommended. All LDOs stability BUCK1 for BB Core 2.2FF For low noise, 1.2A continuous load BUCK2 for BB System IO 2.2FF For low noise BUCK3 as LDO Input 2.2FF For low noise BUCK4 for GSM PA/UMTS PA 2 x 22FF Supply for both GSM PA and UMTS PA LX1 1FH to 4.7FH 2.2FH recommended (Table 60) LX2 1FH to 4.7FH 1.0FH recommended (Table 60) LX3 1FH to 4.7FH 2.2FH recommended (Table 60) LX4 1FH to 4.7FH 2.2FH recommended (Table 60) REFBP 0.1FF Noise filter EN A pulldown resistor, if necessary. Any Bump Required to Pass 8kV Module Level ESD 0.1FF Input for LDO4 and LDO9 Absorb ESD energy Note: Input/output capacitance should be as close as possible to the IC. All capacitors are ceramic X5R or X7R, unless otherwise noted. 32 Power-Management ICs for ICERA E400/E450 Platform MAX8982A/MAX8982X IN1A VDDB P VDDA 3.3V INPUT OVP IN1A 22F STEP-DOWN DC-DC 1 CONVERTER (1.2A) SHUTDOWN SIGNAL 5.75V IN1B UVLO IN4 LX1 2.2H 0.9V (DEFAULT) 0.6V TO 1.2V IN 25mV STEPS CORE 2.2F N PGND1 ON/OFF SEQUENCE 2.7V BUCK1 DVS1 REFBP DCDC 1 SEL IN1A 0.1F GND 0.9V VCC_USB P IN3 OUT9 2.2F STEP-DOWN DC-DC 2 CONVERTER (DEFAULT ON, 600mA) IN1B LDO9 (50mA) UVLO (2.7V) N REF (0.8V) 1H LX2 1.8V VCC_IO 2.2F N PGND2 BUCK2 VDDB 2.7V TCXO OUT6 1F THERMAL SHUTDOWN +160C IN3 2.2F OUT4 LDO6 (50mA) N BB CHIPSET ICE8060 ON E400 PLATFORM LDO4 (50mA) SHUTDOWN SIGNAL IN1_ 16ms TIMER N 14kI BUCK2 RTBON ON/OFF CONTROL AND I2C INTERFACE 200kI VDDB IRQ LDO3 DEFAULT ON 150mA 1.8V OUT2 1F LDO2 (150mA) SCL OUT1 VDDA RF1V8 RF CHIPSET ICE 82 xx N MAX8982X PWR_REQ ANALOG BASEBAND N VDDA PWR_REQ 2.8V 1F SDA SCL POR_N OUT3 BUCK2 SDA BB CHIPSET ICE 8060 ON E400 PLATFORM RESET RESET EN INTERRUPT VCC_PLL 1F ON = BUCK 2EN + 625s ON/OFF SEQUENCE 0.9V 2.7V RF2V7 4.7F LDO1 (300mA) 32kHz OSCILLATOR N BUCK2 VDDB LDO5 (150mA) DR2 DR3 OPTIONAL RESISTORS 3-CHANNEL CURRENT REGULATOR (24mA, DEFAULT) N FLASH TIMER VSIM VDDB SD CARD 1F 3.3V INPUT DR1 3.0V OUT5 N32kHz BB OSC 32kI 1.8V/3.0V SIM LDO (LDO7) 150mA 1.8V USIM 1F N (3--24mA IN 3mA STEPS) Figure 2. MAX8982X Typical Application Circuit and Functional Block Diagram 33 MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform Table 3. External Component List for Figure 2 LOCATION EXTERNAL COMPONENTS IN1A, IN1B NOTES Buck stability 22FF 2.2FF IN3 Input for LDO4 and LDO9 IN4 Connect to IN1A and IN1B OUT1 4.7FF LDO compensation and load transient response OUT2 1.0FF LDO compensation OUT3 1.0FF LDO compensation OUT4 2.2FF LDO compensation OUT5 1.0FF LDO compensation OUT6 1.0FF LDO compensation VSIM (OUT7) 1.0FF LDO compensation OUT9 2.2FF LDO compensation VDDA, VDDB Total capacitance R total output capacitance for LDO1, LDO2, LDO3, LDO5, LDO6, and VSIM. All LDOs stability. Connect VDDA and VDDB to IN1A and IN1B. BUCK1 for BB Core 2.2FF For low noise, 1.2A continuous load BUCK2 for BB System IO 2.2FF For low noise LX1 1FH to 4.7FH 2.2FH recommended (Table 60) LX2 1FH to 4.7FH 1.0FH recommended (Table 60) REFBP 0.1FF Noise filter EN A pulldown resistor, if necessary Any Bump Required to Pass 8kV Module Level ESD 0.1FF Absorb ESD energy Note: Input/output capacitance should be as close as possible to the IC. All capacitors are ceramic X5R or X7R, unless otherwise noted. Detailed Description Power-On/Off Control The power-on/off state diagram is shown in Figure 3. When the IN1_ supply voltage is valid and EN is high, the default power supplies turn on in sequence (Figure 4). Once powered up, any step-down or LDO output can be enabled or disabled through I2C, or they can be programmed to be controlled by the PWR_REQ logic input. PWR_REQ PWR_REQ is a control input from baseband chipset used to enable/disable specified regulators. After power-up, when PWR_REQ goes logic-high, any step-down or LDO output programmed for PWR_REQ control is enabled in a predefined sequence. The regulators are powered up in four groups as shown in Figure 5. See the following for the regulators belonging to each group. When PWR_REQ goes logic-low, all regulators programmed for PWR_REQ control are turned off simultaneously. 34 Any regulator that is set to on or off though I2C is not affected by PWR_REQ, except for BUCK1. The programmed values in BUCK1DVS1 and BUCK1DVS2 are reset to their defaults when PWR_REQ goes low even in normal operation. Group A: BUCK3 (MAX8982A only) LDO2 (default is PWR_REQ On mode) BUCK2 Group B: LDO1 (default is PWR_REQ On mode) LDO3 BUCK4 (MAX8982A only) Group C: LDO6 (default is PWR_REQ On mode) LDO5 LDO7 LDO8 (MAX8982A only) Group D: BUCK1 (default is PWR_REQ On mode) LDO4 (default is PWR_REQ On mode) LDO9 Power-Management ICs for ICERA E400/E450 Platform SHUTDOWN ALL REGULATORS DISABLED I2C HIGH IMPEDANCE REF DISABLED 32kHz DISABLED enable this discharge resistor, set the appropriate bit in the BUCK1-4ADIS, LDO1-8ADIS, or LDO9ADIS register. The active discharge resistor values are specified in the General Electrical Characteristics table. VIN1_ < 3.5V (MAX8982A) OR VIN1_ < 2.4V (MAX8982X) OR VIN1_ > 5.75V OR EN = LOW FROM ANY STATE VIN1_ > 3.8V (TYP) (MAX8982A) VIN1_ > 2.7V (TYP) (MAX8982X) AND EN = HIGH NOTE: ENABLE OF BUCKS AND LDOS AND CONTROL OF BUCKS AND LDOS BY PWR_REQ CAN BE MODIFIED AFTER STARTUP THROUGH I2C. POWER-UP BUCK3 ENABLED (MAX8982A) BUCK2 ENABLED LDO3 ENABLED LDO8 ENABLED (MAX8982A) LDO9 ENABLED RESET = HIGH VREFBP = 0.8V I2C ENABLED 32kHz CLOCK ENABLED BUCK1 ENABLED LDO1 ENABLED LDO2 ENABLED LDO4 ENABLED LDO6 ENABLED RESET = HIGH VREFBP = 0.8V I2C ENABLE 32kHz CLOCK ENABLED PWR_REQ = HIGH PWR_REQ = HIGH PWR_REQ = LOW BUCK1 DISABLED LDO1 DISABLED LDO2 DISABLED LDO4 DISABLED LDO6 DISABLED RESET = HIGH VREFBP = 0.8V I2C ENABLED 32kHz CLOCK ENABLED Figure 3. Power-On/Off State Diagram with IN3 Connected to BUCK2 Output and IN4 Connected to IN1_. Default PWR_REQ Regulators Are Shown. 35 MAX8982A/MAX8982X Active Discharge All regulators include an internal resistor for discharging the output when the regulator is shut down. In the default state (except BUCK2), this resistor is not connected so the output decay depends only on the applied load. To MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform EN AND IN1_ UVLO RISING ON SEQUENCING RESTARTS WHEN INPUT IS ABOVE UVLO RISING THRESHOLD UVLO FALLING ~16ms BUCK 3 (3.2V) 125s BUCK 2 FOR IO (1.8V) 225s 32kHz OUTPUT CONTINUOUS OUT 3 FOR ANALOG (2.8V) 375s OUT 8 125s FOR USB (3.0V) OUT 9 125s FOR BB (0.9V) 625s RESET OTHER ONREGULATORS 31s 31s TO 62s IRQ OPERATING STATE OFF POWER-ON SEQUENCE ON OFF POWER-ON SEQUENCE Figure 4. MAX8982A/MAX8982X Power-On Timing Diagram at Initial Startup with EN Connected to IN1_. BUCK3 and OUT8 Are for the MAX8982A Only. 36 Power-Management ICs for ICERA E400/E450 Platform MAX8982A/MAX8982X PWR_REQ GROUP A : OUT 2,* ~10s BUCK 2, BUCK 3** (BUILT-IN TIME DELAY TO ENABLE REGULATORS) OUTPUT DECAY DEPENDS ON THE LOAD GROUP B : LDO1,* 100s OUT 3, BUCK 4** GROUP C : OUT6,* 200s OUT5, OUT7, OUT8** GROUP D : BUCK 1*, OUT4,* 375s OUT9 *THESE REGULATORS DEFAULT TO PWR_REQ CONTROL. THE OTHERS MUST BE PROGRAMED TO PWR_REQ CONTROL BY I2C. **BUCK3, BUCK4, AND OUT8 ARE FOR THE MAX8982A ONLY. Figure 5. MAX8982A/MAX8982X Power-On Timing Diagram in PWR_REQ ON Mode After Power-Up BUCK1, BUCK2, and BUCK3 Step-Down Converters The step-down converters are optimized for high efficiency over a wide load range, small external component size, low output ripple, and excellent transient response. The step-down converters also feature an internal MOSFET switch with optimized on-resistance and an internal synchronous rectifier to maximize the efficiency and reduce the number of external components. The ICs use a proprietary hysteretic PWM control scheme that switches with a nearly fixed frequency. Figure 6 shows the frequency variation versus load current with a 5V input supply and at TA = +25C. Setting the Output Voltage on BUCK1 The default output is 0.9V. The BUCK1 voltage is programmable through I2C from 0.6V to 1.2V in 25mV increments. Dynamic Voltage Scaling (DVS) Function on Buck 1 BUCK1 includes DVS that allows two output voltages to be programmed through I2C, and an external control input to select between the two voltages. Toggling DVS1 changes the BUCK1 output voltage on-the-fly between the two programmed voltages (Figure 7). Each BUCK1DVS_ register specifies a voltage in the 0.6V to 1.2V range in 25mV increments. FREQUENCY (MHz) FREQUENCY vs. LOAD AT 5V INPUT 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 BUCK1DVS1 (0X3F) (DEFAULT = 0.9V) I2C INTERFACE BUCK1 BUCK2 BUCK3 BUCK1 OUTPUT (DEFAULT = 0.9V) 0.6V TO 1.2V IN 25mV STEPS BUCK1DVS2 (0X40) (DEFAULT = 0.9V) DVS1 Truth Table 1 10 50 100 200 300 400 500 LOAD (mA) Figure 6. Frequency Variation vs. Load Current with a 5V Input Supply DVS1 BUCK1 OUTPUT High Set by BUCK1DVS2 register Low Set by BUCK1DVS1 register Figure 7. DVS1 Logic Diagram 37 MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform Ramp-Up/Down Slope Control on BUCK1 Reference Bypass (REFBP) BUCK1 uses a controlled ramp rate when it is enabled and when changing between output voltage settings. Four programmable slew rates are available for BUCK1. The default value is 12.5mV/Fs (Table 4). The same slew rate is applied for ramp-up/down. The reference bypass is for low noise filtering only and must not be loaded. Bypass REFBP with a 0.1FF ceramic capacitor. The REFBP voltage is 0.8V (typ). Do not use REFBP to provide power to external circuitry. Setting the Output Voltage on BUCK2 If the internal die temperature of any LDOs or stepdown regulators reaches +160NC, the ICs shut down the regulator locally. The regulator is reenabled after it cools by 10NC. The ICs also contain a single +125NC thermal detector located in the center of the die. When the temperature at the center of the die exceeds +125NC, this detector triggers and activates an interrupt. The BUCK2 output voltage is fixed at 1.8V. No programmable output is available. Setting the Output Voltage on BUCK3 The BUCK3 default output is 3.2V. The BUCK3 output voltage is programmable from 2.9V to 3.65V in 50mV increments through I2C. BUCK3 is only available on the MAX8982A. BUCK4 Step-Down Converter for PA (Power Amplifier) BUCK4 is a 2MHz fixed-frequency PWM step-down converter, typically used to supply the power amplifier (PA). The BUCK4 load capability is 1.8A. BUCK4 is only available on the MAX8982A. Setting the Output Voltage on BUCK4 The default output voltage is 3.4V. The BUCK4 output voltage is programmable between 3.0V and 3.75V in 50mV increments through I2C. Linear Regulators All linear regulators are designed for low-drop, low noise, high PSRR, and low quiescent current to minimize power consumption. If the input voltage is above UVLO threshold and power-on is logic-high, the default linear regulator (LDO3) turns on. The other LDOs are turned on and off by the baseband processor through the I2C interface or PWR_REQ control signal. All LDO output voltages are programmable through the I2C interface within option voltages. Thermal Overload Protection Undervoltage Lockout (UVLO) The ICs monitor the voltage at the IN1_ power input. When this voltage drops below 3.5V (MAX8982A) or 2.4V (MAX8982X), the ICs shut down. The ICs turn on when this voltage rises above 3.8V (MAX8982A) or 2.7V (MAX8982X) and EN is high. After a UVLO event, all registers are reset to their POR value. Overvoltage Protection (OVP) If the voltage on the IN1_ or IN4 inputs exceeds 5.75V (typ), the ICs shut down. When the supply voltage returns to within the valid operating range and EN is high, the ICs turn on and go through a normal power-up sequence. All registers are reset to their default poweron reset (POR) value. Power-On Reset (POR) Power-on reset (POR) for I2C occurs when the ICs turn off due to UVLO, OVP, or EN = low. This condition puts the IC into shutdown and then clears all previously programmed output voltages in the internal registers. The programmed values in BUCK1DVS1 and BUCK1DVS2 are also reset to their defaults when PWR_REQ goes low in normal operation mode. Table 4. BUCK1 Ramp-Up/Down Slope Control Settings RASD1[1] RASD1[0] SLEW RATE (mV/s) 0 0 5 0 1 10 1 0 12.5 (default) 1 1 25 38 DOWN SLOPE CONTROL VBUCK1 UP SLOPE CONTROL Figure 8. BUCK1 Ramp-Up/Down Slope Control Power-Management ICs for ICERA E400/E450 Platform EN = HIGH AND IN1_ VALID EN = LOW OR IN1_ INVALID I2C ENABLED THE VALUES IN THE BUCK1DVS1 AND BUCK1DVS2 REGISTERS ARE RESET TO THEIR DEFAULTS WHEN PWR_REQ GOES LOW PWR _REQ = LOW Figure 9. POR State Diagram Current Regulators (DR1, DR2, DR3) The ICs have three current regulators that can handle up to 24mA. The sink current for each current regulator is set from 3mA to 24mA in 3mA increments through I2C. The default set current is 24mA on each channel. If a current other than the programmable options is required, a series resistor can be added to set a current from 0mA to 24mA (Figure 10). The resistor forces the current regulator to operate in dropout. Set the resistor value to (VIN1_ - VF)/ILED, where VF is the forward voltage of the LED at the desired current and ILED is the desired LED current. ILED must be less than the programmed current (24mA default). Each current regulator has an embedded flash timer. The flash time is programmable through the I2C interface. This feature allows the system designer to generate a desired pattern on LED. Embedded Flash Timer The flash generator is clocked by the internal 32kHz oscillator. It consists of a counter that wraps at a programmable value to provide a configurable sequence period (tP). Up to four on-pulses can be programmed in this sequence and the start time for each pulse is programmed individually (t1-t4). The programmable LED on-time (tON) for each pulse is the same for each pulse. The flash timing is shown in Figure 11. The dimming current can be changed at any time. IRQ Description The ICs use the IRQ to indicate to the baseband processor that their status has changed. The IRQ signal is asserted (pulls low) whenever an interrupt is triggered. The baseband controller shall read the interrupt register to find sources of interrupt. IRQ is cleared (high) as soon as the read sequence of the last IRQ register that contains an active interrupt starts. If an interrupt is captured during the read sequence, IRQ becomes active (low) after minimum 24 cycles of the I2C clock. An interrupt can be masked to prevent IRQ from being asserted for the masked event. A mask bit in the IRQM register implements masking. For UVLO interrupt bit, the bit status is only maintained as long as VBUS is higher than 2.0V in any conditions. tP VIN1_ DR 1 DR 2 3-CHANNEL CURRENT REGULATOR (24mA, DEFAULT) DR 3 tON tON tON tON t1 t2 t3 t4 Figure 10. Adding Series Resistors to Adjust LED Current Figure 11. Flash Timing Diagram 39 MAX8982A/MAX8982X POR ON ALL REGISTERS IN MAX8982A/ MAX8982X MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform SDA SCL DATA LINE STABLE DATA VALID CHANGE OF DATA ALLOWED Figure 12. I2C Bit Transfer RESET SIGNAL to B/B Chipset The ICs include one dedicated reset output called RESET. This is the reset signal for the core and RTB (real-time block) in baseband. RESET goes high after the ICs' power-up sequence is complete. RESET is pulled low when the ICs are shut down (due to input supply out of range or EN goes low). SDA I2C Serial Interface An I2C-compatible, 2-wire serial interface is used for regulator on/off control, setting output voltages, LED control, and other functions. See Table 5 for the complete register map. The I2C serial bus consists of a bidirectional serial-data line (SDA) and a serial-clock line (SCL). I2C is an opendrain bus. SDA and SCL require pullup resistors (500I or greater). Optional 24I resistors in series with SDA and SCL help to protect the device inputs from high-voltage spikes on the bus lines. Series resistors also minimize crosstalk and undershoot on bus lines. Bit Transfer One data bit is transferred for each SCL clock cycle. The data on SDA must remain stable during the high portion of the SCL clock pulse (Figure 12). Changes in SDA while SCL is high are control signals (START and STOP conditions). START and STOP Conditions Each transmit sequence is framed by a START (S) condition and a STOP (P) condition. Each packet is 9 bits long; 8 bits of data followed by the acknowledge bit. The ICs support data transfer rates with a SCL frequency up to 400kHz. 40 SCL START CONDITION STOP CONDITION Figure 13. START and STOP Conditions Both SDA and SCL remain high when the bus is not busy. The master device initiates communication by issuing a START condition. A START condition is a high-to-low transition of SDA, while SCL is high. A STOP condition is a low-to-high transition of the data line while SCL is high (Figure 13). A START condition from the master signals the beginning of a transmission to the ICs. The master terminates transmission by issuing a not acknowledge followed by a STOP condition. See the Acknowledge section for more information. The STOP condition frees the bus. To issue a series of commands to the slave, the master can issue Power-Management ICs for ICERA E400/E450 Platform Acknowledge The number of data bytes between the START and STOP conditions for the transmitter and receiver are unlimited. Each 8-bit byte is followed by an acknowledge bit. The acknowledge bit is a high-level signal put on SDA by the transmitter during which time the master generates an extra acknowledge-related clock pulse. A slave receiver that is addressed must generate an acknowledge after each byte it receives. Also, a master receiver must generate an acknowledge after each byte it receives that has been clocked out of the slave transmitter. See Figure 15. When a STOP condition or incorrect address is detected, the ICs internally disconnect SCL from the serial interface until the next START condition, minimizing digital noise and feedthrough. System Configuration A device on the I2C bus that generates a message is called a transmitter, and a device that receives the message is a receiver. The device that controls the message is the master, and the devices that are controlled by the master are called slaves (Figure 14). The device that acknowledges must pull down the DATA line during the acknowledge clock pulse, so that the DATA line is stable low during the high period of the acknowledge clock pulse (setup and hold times must also be met). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case, the transmitter must leave SDA high to enable the master to generate a STOP condition. The ICs are slave transmitter/receiver devices, and the B/B chipset is a master transmitter/receiver. The master initiates data transfer on the bus and generates SCL to permit data transfer. SDA SCL MASTER TRANSMITTER/RECEIVER SLAVE TRANSMITTER/RECEIVER SLAVE RECEIVER Figure 14. Master/Slave Configuration SDA OUTPUT FROM TRANSMITTER D7 D6 D0 NOT ACKNOWLEDGE SDA OUTPUT FROM RECEIVER SCL FROM MASTER START CONDITION ACKNOWLEDGE 1 2 8 9 CLOCK PULSE FOR ACKNOWLEDGEMENT Figure 15. I2C Acknowledge 41 MAX8982A/MAX8982X REPEATED START (Sr) commands instead of a STOP command to maintain control of the bus. In general, a REPEATED START command is functionally equivalent to a regular START command. MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform SDA tLOW tBUF tSU_STA tSU_DAT tHD_STA tSU_STO tHD_DAT tHIGH SCL tHD_STA tF tR START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 16. I2C Timing Diagram LEGEND MASTER TO SLAVE SLAVE TO MASTER a) WRITING TO A SINGLE REGISTER WITH THE WRITE BYTE PROTOCOL 7 1 S SLAVE ADDRESS 1 1 8 1 8 1 1 0 A REGISTER POINTER A DATA A P NUMBER OF BITS R/W b) WRITING TO MULTIPLE REGISTERS 1 7 1 1 8 1 8 1 8 1 S SLAVE ADDRESS 0 A REGISTER POINTER X A DATA X A DATA X+1 A 1 8 1 NUMBER OF BITS A DATA X+n R/W 8 ... DATA X+n-1 NUMBER OF BITS ... A P Figure 17. Writing to the ICs Slave Address The ICs act as a slave transmitter/receiver. The slave address of the ICs is: Write Operations Use the following procedure to write to a sequential block of registers (Figure 17): 10000010 (0x82) for write operations 1) The master sends a start command. 10000011 (0x83) for read operations 2) The master sends the 7-bit slave address followed by a write bit (0x82). 3) The addressed slave asserts an acknowledge by pulling SDA low. The least significant bit is the read/write indicator. 1 42 0 0 0 0 0 1 R/W Power-Management ICs for ICERA E400/E450 Platform The master sends the 8-bit register pointer of the first register to write. 4) The master sends an 8-bit register pointer of the first register in the block. 5) The slave acknowledges the register pointer. 5) The slave acknowledges the register pointer. 6) The master sends a data byte. 6) The master sends a repeated START condition. 7) The slave acknowledges the data byte. 7) 8) The slave updates with the new data. The master sends the 7-bit slave address followed by a read bit. 9) Steps 6 to 8 are repeated for as many registers in the block, with the register pointer automatically incremented each time. 8) The slave asserts an acknowledge by pulling SDA low. 9) The slave sends the 8-bit data (contents of the register). 10) The master asserts an acknowledge by pulling SDA low when there is more data to read, or a not acknowledge by keeping SDA high when all data has been read. 10) The master sends a STOP condition. Read Operations Use the following method to read a sequential block of registers (Figure 18): 1) The master sends a start command. 2) The master sends the 7-bit slave address followed by a write bit (0x83). 3) The addressed slave asserts an acknowledge by pulling SDA low. 11) Steps 9 and 10 are repeated for as many registers in the block, with the register pointer automatically incremented each time. 12) The master sends a STOP condition. The register pointer can be omitted from the above procedure when starting from register 0x00. LEGEND MASTER TO SLAVE SLAVE TO MASTER a) READING A SINGLE REGISTER 1 S 7 SLAVE ADDRESS 1 1 8 0 A REGISTER POINTER 1 1 A Sr 7 1 1 SLAVE ADDRESS 1 A R/W 1 1 DATA 8 A P 8 1 DATA X A NUMBER OF BITS R/W b) READING MULTIPLE REGISTERS 1 7 1 1 8 1 1 7 S SLAVE ADDRESS 0 A REGISTER POINTER X A Sr SLAVE ADDRESS R/W 8 ... DATA X+1 1 A ... 8 DATA X+n-1 1 1 R/W 1 A 1 A 8 DATA X+n 1 1 NUMBER OF BITS ... NUMBER OF BITS A P Figure 18. Reading from the ICs 43 MAX8982A/MAX8982X 4) MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform Table 5. Register Map ADDRESS POR R/W (HEX) (HEX) 44 NAME BIT 7 (MSB) BIT 6 Reserved Reserved BIT 5 BIT 4 PASS[1:0] BIT 3 BIT 2 BIT 1 BIT 0 (LSB) 02 -- R CHIPID Reserved Reserved Reserved VOPTION 03 00 R/W IRQM Reserved Reserved Reserved Reserved Reserved Reserved 13 00 R/W IRQ Reserved Reserved Reserved Reserved Reserved Reserved UVLOF HIGHTMP 14 N/A R STATUS Reserved Reserved Reserved Reserved Reserved Reserved UVLOF HIGHTMP 18 00 R/W LED1FT1 Reserved Reserved Reserved FLASHEN LD1TON[3:0] 19 00 R/W LED1FT2 Reserved LD1T1[6:0] 1A 00 R/W LED1FT3 Reserved LD1T2[6:0] 1B 00 R/W LED1FT4 Reserved LD1T3[6:0] 1C 00 R/W LED1FT5 Reserved LD1T4[6:0] LD1TP[6:0] 1D 00 R/W LED1FT6 Reserved 20 00 R/W LED2FT1 Reserved Reserved Reserved FLASHEN 21 00 R/W LED2FT2 Reserved LD2T1[6:0] 22 00 R/W LED2FT3 Reserved LD2T2[6:0] 23 00 R/W LED2FT4 Reserved LD2T3[6:0] 24 00 R/W LED2FT5 Reserved LD2T4[6:0] 25 00 R/W LED2FT6 Reserved LD2TP[6:0] 28 00 R/W LED3FT1 Reserved Reserved Reserved FLASHEN 29 00 R/W LED3FT2 Reserved LD3T1[6:0] 2A 00 R/W LED3FT3 Reserved LD4T2[6:0] 2B 00 R/W LED3FT4 Reserved LD4T3[6:0] 2C 00 R/W LED3FT5 Reserved LD4T4[6:0] 2D 00 R/W LED3FT6 Reserved LD4TP[6:0] BUCK1 3D 47 R/W 3F 0C R/W BUCK1DVS1 UVLOFM HIGHTMPM LD2TON[3:0] LD3TON[3:0] Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SD1[4:0] SD1[4:0] BUCK1[1:0] 40 0C R/W BUCK1DVS2 Reserved Reserved Reserved 45 45 R/W BUCK2 Reserved Reserved Reserved Reserved Reserved Reserved BUCK2[1:0] 4C 03 R/W LDO1 Reserved Reserved Reserved Reserved Reserved Reserved LDO1[1:0] 4D 04 R/W LDO1V 4E 03 R/W LDO2 4F 04 R/W LDO2V 50 01 R/W LDO3 51 07 R/W LDO3V 52 03 R/W LDO4 53 00 R/W LDO4V 54 00 R/W LDO5 55 07 R/W LDO5V 56 01 R/W LDO6 57 07 R/W LDO6V 58 00 R/W VSIM 59 0B R/W VSIMV Reserved Reserved Reserved L1[4:0] Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved LDO6[1:0] L6[4:0] Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved LDO5[1:0] L5[4:0] Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved LDO4[1:0] L4[4:0] Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved LDO3[1:0] L3[4:0] Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved LDO2[1:0] L2[4:0] L7[4:0] LDO7[1:0] Power-Management ICs for ICERA E400/E450 Platform ADDRESS POR R/W (HEX) (HEX) 5A BIT 7 (MSB) NAME 01 R/W LDO8 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved BIT 0 (LSB) LDO8[1:0] 5B 06 R/W LDO8V 5C 01 R/W LDO9 L8[4:0] 5D 00 R/W LDO9V Reserved Reserved Reserved 6B 00 R/W LED_EN Reserved Reserved Reserved Reserved Reserved 70 03 R/W ON/OFF Reserved Reserved Reserved 72 06 R/W BUCK3 Reserved Reserved Reserved Reserved SD3[3:0] BUCK4 Reserved Reserved Reserved Reserved SD4[3:0] Reserved Reserved Reserved Reserved Reserved Reserved LDO9[1:0] L9[4:0] BUCK4[1:0] LED3EN LED2EN BUCK3[1:0] LED1EN 32KCLK 73 08 R/W 75 3F R/W CURRENTREG1 Reserved Reserved 76 07 R/W CURRENTREG2 Reserved Reserved Reserved Reserved Reserved 77 02 R/W 78 04 R/W BUCK1-4ADIS Reserved Reserved Reserved Reserved SD1ADIS 79 00 R/W LDO1-8ADIS LDO1ADIS LDO2ADIS LDO3ADIS LDO4ADIS LDO5ADIS LDO6ADIS LDO7ADIS LDO8ADIS 7A 00 R/W Reserved Reserved Reserved Reserved Reserved Reserved Reserved LDO9ADIS RAMP DR1[2:0] DR2[2:0] DR3[2:0] Reserved Reserved Reserved Reserved Reserved Reserved LDO9ADIS SD2ADIS RASD1[1:0] SD3ADIS SD4ADIS Table 6. CHIPID Register ADDRESS (HEX) POR (HEX) R/W BIT 7 BIT 6 02 -- R Reserved Reserved BIT 5 BIT 4 PASS[1:0] NAME POR VOPTION -- 0: 5V input option (MAX8982A) 1: 3.3V input option (MAX8982X) PASS[1:0] -- Chip revision version BIT 3 BIT 2 BIT 1 BIT 0 Reserved Reserved Reserved VOPTION DESCRIPTION Table 7. IRQM Register (Interrupt Mask) ADDRESS (HEX) POR (HEX) R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 03 00 R/W Reserved Reserved Reserved Reserved Reserved Reserved UVLOFM HIGH TMPM NAME POR DESCRIPTION HIGH TMPM 0 0: Interrupt enabled. 1: Mask HIGHTMP interrupt. UVLOFM 0 0: Interrupt enabled. 1: Mask UVLOF interrupt. Note: The IRQM register is effective only as long as IN1A and IN1B are higher than the falling UVLO threshold. If the IN1A and IN1B are below the falling UVLO threshold, this IRQM register resets to the POR value. 45 MAX8982A/MAX8982X Table 5. Register Map (continued) MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform Table 8. IRQ Register ADDRESS (HEX) POR (HEX) R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 13 00 R/W Reserved Reserved Reserved Reserved Reserved Reserved UVLOF HIGH TMP NAME POR DESCRIPTION HIGH TMP 0 0: No high temperature event detected. 1: Temperature sensor detects +125NC. UVLOF 0 0: No UVLO event detected. 1: UVLO falling is detected. Note: The IRQ register is effective only as long as IN1A and IN1B are higher than 2.0V. If the IN1A and IN1B are below 2.0V, these registers reset to the POR value. Table 9. STATUS Register ADDRESS (HEX) POR (HEX) R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 14 N/A R Reserved Reserved Reserved Reserved Reserved Reserved UVLOF HIGH TMP NAME POR DESCRIPTION HIGHTMP -- 0: TJ < +125NC 1: TJ > +125NC UVLOF -- 0: Falling UVLO threshold is not detected. 1: Falling UVLO threshold is detected. Table 10. LED1FT1 Register (LED1 (DR1) Flash Timer On/Off and TON Adjust) ADDRESS (HEX) POR (HEX) R/W BIT 7 BIT 6 BIT 5 BIT 4 18 00 R/W Reserved Reserved Reserved FLASHEN NAME POR FLASHEN 0 BIT 3 BIT 2 0000 LD1TON[3:0] 1: Flasher is enabled. 0: Flasher is disabled. tON (ms) 3 2 1 0 0 0 0 0 25 0 . . 1 0 . . 1 0 . . 1 1 . . 1 50 . . 400 From 25ms to 400ms in 25ms increments. 46 BIT 0 DESCRIPTION BIT LD1TON[3:0] BIT 1 Power-Management ICs for ICERA E400/E450 Platform ADDRESS (HEX) POR (HEX) R/W BIT 7 19 00 R/W Reserved NAME BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 t1 TIME (ms) LD1T1[6:0] POR DESCRIPTION BIT LD1T1[0:6] 0000000 MAX8982A/MAX8982X Table 11. LED1FT2 Register (LED1 (DR1) Flash Timer t1 Setting) 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 25 . . . . . . . . . . . . . . . . 1 1 1 1 1 1 1 3175 BIT 2 BIT 1 BIT 0 From 0ms to 3175ms in 25ms increments. Table 12. LED1FT3 Register (LED1 (DR1) Flash Timer t2 Setting) ADDRESS (HEX) POR (HEX) R/W BIT 7 1A 00 R/W Reserved NAME BIT 6 BIT 5 BIT 4 BIT 3 LD1T2[6:0] POR DESCRIPTION BIT LD1T2[0:6] 0000000 6 5 4 3 2 1 0 t2 TIME (ms) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 0 0 0 0 0 1 0 50 . . . . . . . . . . . . . . . . 1 1 1 1 1 1 1 3175 BIT 2 BIT 1 BIT 0 1 0 t3 TIME (ms) From 0ms to 3175ms in 25ms increments. Table 13. LED1FT4 Register (LED1 (DR1) Flash Timer t3 Setting) ADDRESS (HEX) POR (HEX) R/W BIT 7 1B 00 R/W Reserved NAME BIT 6 BIT 5 BIT 4 BIT 3 LD1T3[6:0] POR DESCRIPTION BIT 6 LD1T3[6:0] 0000000 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 25 0 0 0 0 0 1 0 50 . . . . . . . . . . . . . . . . 1 1 1 1 1 1 1 3175 From 0ms to 3175ms in 25ms increments. 47 MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform Table 14. LED1FT5 Register (LED1 (DR1) Flash Timer t4 Setting) ADDRESS (HEX) POR (HEX) R/W BIT 7 1C 00 R/W Reserved NAME BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 1 0 t4 TIME (ms) LD1T4[6:0] POR DESCRIPTION BIT 6 LD1T4[6:0] 0000000 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 25 0 0 0 0 0 1 0 50 . . . . . . . . . . . . . . . . 1 1 1 1 1 1 1 3175 BIT 2 BIT 1 BIT 0 1 0 tP TIME (ms) From 0ms to 3175ms in 25ms increments. Table 15. LED1FT6 Register (LED1 (DR1) Flash Timer tP Setting) ADDRESS (HEX) POR (HEX) R/W BIT 7 1D 00 R/W Reserved NAME BIT 6 BIT 5 BIT 4 BIT 3 LD1TP[6:0] POR DESCRIPTION BIT 6 LD1TP[6:0] 0000000 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 25 0 0 0 0 0 1 0 50 0 . . 1 0 . . 1 0 . . 1 0 . . 1 0 . . 1 1 . . 1 1 . . 1 75 . . 3175 From 0ms to 3175ms in 25ms increments. Table 16. LED2FT1 Register (LED2 (DR2) Flash Timer On/Off and tON Adjust) ADDRESS (HEX) POR (HEX) R/W BIT 7 BIT 6 BIT 5 BIT 4 20 00 R/W Reserved Reserved Reserved Flash EN NAME POR BIT 3 BIT 2 BIT 1 BIT 0 LD2TON[3:0] DESCRIPTION 1: Flasher is enabled. 0: Flasher is disabled. BIT 3 LD2TON[3:0] 0000 2 0 tON TIME (ms) 0 0 0 0 25 0 0 0 1 50 . . . . . . . . . . 1 1 1 1 400 From 25ms to 400ms in 25ms increments. 48 1 Power-Management ICs for ICERA E400/E450 Platform ADDRESS (HEX) POR (HEX) R/W BIT 7 21 00 R/W Reserved NAME BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 t1 TIME (ms) LD2T1[6:0] POR DESCRIPTION BIT LD2T1[6:0] 0000000 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 . . 1 0 . . 1 0 . . 1 0 . . 1 0 . . 1 0 . . 1 1 . . 1 25 . . 3175 BIT 2 BIT 1 BIT 0 t2 TIME (ms) From 0ms to 3175ms in 25ms increments. Table 18. LED2FT3 Register (LED2 (DR2) Flash Timer t2 Setting) ADDRESS (HEX) POR (HEX) R/W BIT 7 22 00 R/W Reserved NAME BIT 6 BIT 5 BIT 4 BIT 3 LD2T2[6:0] POR DESCRIPTION BIT LD2T2[6:0] 0000000 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 . . 1 0 . . 1 0 . . 1 0 . . 1 0 . . 1 0 . . 1 1 . . 1 25 . . 3175 BIT 2 BIT 1 BIT 0 1 0 t3 TIME (ms) From 0ms to 3175ms in 25ms increments. Table 19. LED2FT4 Register (LED2 (DR2) Flash Timer t3 Setting) ADDRESS (HEX) POR (HEX) R/W BIT 7 23 00 R/W Reserved NAME BIT 6 BIT 5 BIT 4 BIT 3 LD2T3[6:0] POR DESCRIPTION BIT 6 LD2T3[6:0] 0000000 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 25 0 0 0 0 0 1 0 50 . . . . . . . . . . . . . . . . 1 1 1 1 1 1 1 3175 From 0ms to 3175ms in 25ms increments. 49 MAX8982A/MAX8982X Table 17. LED2FT2 Register (LED2 (DR2) Flash Timer t1 Setting) MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform Table 20. LED2FT5 Register (LED2 (DR2) Flash Timer t4 Setting) ADDRESS (HEX) POR (HEX) R/W BIT 7 24 00 R/W Reserved NAME BIT 6 BIT 5 BIT 3 BIT 4 BIT 2 BIT 1 1 0 0 1 . . 1 0 0 1 0 . . 1 BIT 2 BIT 1 BIT 0 LD2T4[6:0] POR DESCRIPTION BIT LD2T4[6:0] 0000000 BIT 0 6 5 4 3 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . 1 1 1 1 2 0 0 0 . . 1 t4 TIME (ms) 0 25 50 . . 3175 From 0ms to 3175ms in 25ms increments. Table 21. LED2FT6 Register (LED2 (DR2) Flash Timer tP Setting) ADDRESS (HEX) POR (HEX) R/W BIT 7 25 00 R/W Reserved NAME BIT 6 BIT 5 BIT 4 BIT 3 LD2TP[6:0] POR DESCRIPTION BIT LD2TP[6:0] 0000000 6 5 4 3 2 1 0 tP TIME (ms) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 25 0 0 0 0 0 1 0 50 . . . . . . . . . . . . . . . . 1 1 1 1 1 1 1 3175 From 0ms to 3175ms in 25ms increments. Table 22. LED3FT1 Register (LED3 (DR3) Flash Timer On/Off and tON Adjust) ADDRESS (HEX) POR (HEX) R/W BIT 7 BIT 6 BIT 5 BIT 4 28 00 R/W Reserved Reserved Reserved FLASHEN NAME FLASHEN POR 0 BIT 3 BIT 2 0000 DESCRIPTION 1: Flasher is enabled. 0: Flasher is disabled. tON TIME (ms) 3 2 1 0 0 0 0 0 25 0 . . 1 0 . . 1 0 . . 1 1 . . 1 50 . . 400 From 25ms to 400ms in 25ms increments. 50 BIT 0 LD3TON[3:0] BIT LD3TON[3:0] BIT 1 Power-Management ICs for ICERA E400/E450 Platform ADDRESS (HEX) POR (HEX) R/W BIT 7 29 00 R/W Reserved NAME BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 t1 TIME (ms) LD3T1[6:0] POR DESCRIPTION BIT LD3T1[6:0] 0000000 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 25 0 0 0 0 0 1 0 50 . . . . . . . . . . . . . . . . 1 1 1 1 1 1 1 3175 BIT 2 BIT 1 BIT 0 t2 TIME (ms) From 0ms to 3175ms in 25ms increments. Table 24. LED3FT3 Register (LED3 (DR3) Flash Timer t2 Setting) ADRESS (HEX) POR (HEX) R/W BIT 7 2A 00 R/W Reserved NAME BIT 6 BIT 5 BIT 4 BIT 3 LD3T2[6:0] POR DESCRIPTION BIT LD3T2[6:0] 0000000 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 25 . . . . . . . . . . . . . . . . 1 1 1 1 1 1 1 3175 BIT 2 BIT 1 BIT 0 From 0ms to 3175ms in 25ms increments. Table 25. LED3FT4 Register (LED3 (DR3) Flash Timer t3 Setting) ADDRESS (HEX) POR (HEX) R/W BIT 7 2B 00 R/W Reserved NAME BIT 6 BIT 5 BIT 4 BIT 3 LD3T3[6:0] POR DESCRIPTION BIT LD3T3[6:0] 0000000 6 5 4 3 2 1 0 t3 TIME (ms) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 25 0 0 0 0 0 1 0 50 . . . . . . . . . . . . . . . . 1 1 1 1 1 1 1 3175 From 0ms to 3175ms in 25ms increments. 51 MAX8982A/MAX8982X Table 23. LED3FT2 Register (LED3 (DR3) Flash Timer t1 Setting MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform Table 26. LED3FT5 Register (LED3 (DR3) Flash Timer t4 Setting) ADDRESS (HEX) POR (HEX) R/W BIT 7 2C 00 R/W Reserved NAME BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 LD3T4[6:0] POR DESCRIPTION BIT LD3T4[6:0] 0000000 6 5 4 3 2 1 0 t4 TIME (ms) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 25 0 0 0 0 0 1 0 50 . . . . . . . . . . . . . . . . 1 1 1 1 1 1 1 3175 BIT 2 BIT 1 BIT 0 tP TIME (ms) From 0ms to 3175ms in 25ms increments. Table 27. LED3FT6 Register (LED3 (DR3) Flash Timer tP Setting) ADDRESS (HEX) POR (HEX) R/W BIT 7 2D 00 R/W Reserved NAME BIT 6 BIT 5 BIT 4 BIT 3 LD3TP[6:0] POR DESCRIPTION BIT LD3TP[6:0] 0000000 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 25 0 0 0 0 0 1 0 50 0 0 0 0 0 1 1 75 . . . . . . . . . . . . . . . . 1 1 1 1 1 1 1 3175 BIT 1 BIT 0 From 0ms to 3175ms in 25ms increments. Table 28. BUCK1 Register (On/Off Control for BUCK1) ADDRESS (HEX) POR (HEX) R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 3D 47 R/W Reserved Reserved Reserved Reserved Reserved Reserved BITS 7:2 52 Reserved, write 010001 to these bits. BIT 1 BIT 0 0 0 BUCK1 off (in I2C on mode). DESCRIPTION 0 1 BUCK1 on (in I2C on mode). 1 0 BUCK1 on (in PWR_REQ on mode) (Group D). 1 1 BUCK1 on (in PWR_REQ on mode) (Group D). BUCK1[1:0] Power-Management ICs for ICERA E400/E450 Platform ADDRESS (HEX) POR (HEX) R/W BIT 7 BIT 6 BIT 5 3F 0C R/W Reserved Reserved Reserved BITS 7:5 BIT 4 BIT 3 BIT 2 BIT 1 MAX8982A/MAX8982X Table 29. BUCK1DVS1 Register (Output Voltage Setting for BUCK1 (DVS1 = Low)) BIT 0 SD1[4:0] Reserved, write 000 to these bits. DESCRIPTION BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 VPROG (V) 0 0 0 0 0 0.600 0 0 0 0 1 0.625 0 0 0 1 0 0.650 0 0 0 1 1 0.675 0 0 1 0 0 0.700 0 0 1 0 1 0.725 0 0 1 1 0 0.750 0 0 1 1 1 0.775 0 1 0 0 0 0.800 0 1 0 0 1 0.825 0 1 0 1 0 0.850 0 1 0 1 1 0.875 0 1 1 0 0 0.900 0 1 1 0 1 0.925 0 1 1 1 0 0.950 0 1 1 1 1 0.975 1 0 0 0 0 1.000 1 0 0 0 1 1.025 1 0 0 1 0 1.050 1 0 0 1 1 1.075 1 0 1 0 0 1.100 1 0 1 0 1 1.125 1 0 1 1 0 1.150 1 0 1 1 1 1.175 1 1 X X X 1.200 X = Don't care. 53 MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform Table 30. BUCK1DVS2 Register (Output Voltage Setting for BUCK1 (DVS1 = High)) ADDRESS (HEX) POR (HEX) 40 0C BITS 7:5 R/W BIT 7 BIT 6 BIT 5 BIT 4 R/W Reserved Reserved Reserved BIT 3 BIT 2 BIT 1 SD1[4:0] Reserved, write 000 to these bits. DESCRIPTION BIT 4 BIT 2 BIT 1 BIT 0 VPROG (V) 0 0 0 0 0 0.600 0 0 0 0 1 0.625 0 0 0 1 0 0.650 0 0 0 1 1 0.675 0 0 1 0 0 0.700 0 0 1 0 1 0.725 0 0 1 1 0 0.750 0 0 1 1 1 0.775 0 1 0 0 0 0.800 0 1 0 0 1 0.825 0 1 0 1 0 0.850 0 1 0 1 1 0.875 0 1 1 0 0 0.900 0 1 1 0 1 0.925 0 1 1 1 0 0.950 0 1 1 1 1 0.975 1 0 0 0 0 1.000 1 0 0 0 1 1.025 1 0 0 1 0 1.050 1 0 0 1 1 1.075 1 0 1 0 0 1.100 1 0 1 0 1 1.125 1 0 1 1 0 1.150 1 0 1 1 1 1.175 1 1 X X X 1.200 X = Don't care. 54 BIT 3 BIT 0 Power-Management ICs for ICERA E400/E450 Platform ADDRESS (HEX) POR (HEX) R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 45 45 R/W Reserved Reserved Reserved Reserved Reserved Reserved BITS 7:2 BIT 1 MAX8982A/MAX8982X Table 31. BUCK2 Register (On/Off Control for BUCK2) BIT 0 BUCK2[1:0] Reserved, write 010001 to these bits. BIT 1 BIT 0 0 0 DESCRIPTION BUCK2 off (in I2C on mode). 0 1 BUCK2 on (in I2C on mode). 1 0 BUCK2 on (in PWR_REQ on mode) (Group A). 1 1 BUCK2 on (in PWR_REQ on mode) (Group A). Table 32. LDO1 Register (On/Off Control for LDO1) ADDRESS (HEX) 4C POR R/W (HEX) 03 R/W BITS 7:2 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 Reserved Reserved Reserved Reserved Reserved Reserved BIT 1 BIT 0 LDO1[1:0] Reserved, write 000000 to these bits. BIT 1 BIT 0 DESCRIPTION I2C on mode). 0 0 LDO1 off (in 0 1 LDO1 on (in I2C on mode). 1 0 LDO1 on (in PWR_REQ on mode) (Group B). 1 1 LDO1 on (in PWR_REQ on mode) (Group B). Table 33. LDO1V Register (Output Voltage Setting for OUT1) ADDRESS (HEX) POR (HEX) R/W BIT 7 BIT 6 BIT 5 4D 04 R/W Reserved Reserved Reserved BITS 7:5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 L1[4:0] Reserved, write 000 to these bits. DESCRIPTION BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 VPROG (V) 0 0 0 0 0 2.65 0 0 0 0 1 2.65 0 0 0 1 0 2.65 0 0 0 1 1 2.65 0 0 1 0 0 2.70 0 0 1 0 1 2.70 0 0 1 1 0 2.75 0 0 1 1 1 2.80 0 1 0 0 0 2.85 0 1 0 0 1 2.90 0 1 0 1 0 2.95 0 1 0 1 1 3.00 0 1 1 X X 3.00 1 X X X X 3.00 X = Don't care. 55 MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform Table 34. LDO2 Register (ON/OFF Control for LDO2) ADDRESS (HEX) POR (HEX) R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 4E 03 R/W Reserved Reserved Reserved Reserved Reserved Reserved BITS 7:2 BIT 1 BIT 0 LDO2[1:0] Reserved, write 000000 to these bits. BIT 1 BIT 0 0 0 LDO2 off (in I2C on mode). DESCRIPTION 0 1 LDO2 on (in I2C on mode). 1 0 LDO2 on (in PWR_REQ on mode) (Group A). 1 1 LDO2 on (in PWR_REQ on mode) (Group A). Table 35. LDO2V Register (Output Voltage Setting for OUT2) ADDRESS (HEX) POR (HEX) R/W 4F 04 R/W BITS 7:5 BIT 7 BIT 6 BIT 5 BIT 4 Reserved Reserved Reserved BIT 3 BIT 2 BIT 1 BIT 0 L2[4:0] Reserved, write 000 to these bits. DESCRIPTION BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 VPROG (V) 0 0 0 0 0 1.50 0 0 0 0 1 1.50 0 0 0 1 0 1.50 0 0 0 1 1 1.50 0 0 1 0 0 1.80 0 0 1 0 1 2.70 0 0 1 1 0 2.70 0 0 1 1 1 2.70 0 1 0 0 0 2.70 0 1 0 0 1 2.70 0 1 0 1 0 2.70 0 1 0 1 1 1.70 0 1 1 X X 1.70 1 X X X X 1.70 X = Don't care. Table 36. LDO3 Register (On/Off Control for LDO3) ADDRESS (HEX) POR (HEX) R/W 50 01 R/W BITS 7:2 56 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved, write 000000 to these bits. BIT 1 BIT 0 0 0 LDO3 off (in I2C on mode). DESCRIPTION 0 1 LDO3 on (in I2C on mode). 1 0 LDO3 on (in PWR_REQ on mode) (Group B). 1 1 LDO3 on (in PWR_REQ on mode) (Group B). BIT 1 BIT 0 LDO3[1:0] Power-Management ICs for ICERA E400/E450 Platform ADDRESS (HEX) POR (HEX) R/W BIT 7 BIT 6 BIT 5 51 07 R/W Reserved Reserved Reserved BITS 7:5 BIT 4 BIT 3 BIT 2 BIT 1 MAX8982A/MAX8982X Table 37. LDO3V Register (Output Voltage Setting for OUT3) BIT 0 L3[4:0] Reserved, write 000 to these bits. DESCRIPTION BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 VPROG (V) 0 0 0 0 0 2.65 0 0 0 0 1 2.65 0 0 0 1 0 2.65 0 0 0 1 1 2.65 0 0 1 0 0 2.70 0 0 1 0 1 2.70 0 0 1 1 0 2.75 0 0 1 1 1 2.80 0 1 0 0 0 2.85 0 1 0 0 1 2.90 0 1 0 1 0 2.95 0 1 0 1 1 3.00 0 1 1 X X 3.00 1 X X X X 3.00 X = Don't care. Table 38. LDO4 Register (On/Off Control for LDO4) ADDRESS (HEX) POR (HEX) R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 52 03 R/W Reserved Reserved Reserved Reserved Reserved Reserved BITS 7:2 BIT 1 BIT 0 LDO4[1:0] Reserved, write 000000 to these bits. BIT 1 BIT 0 0 0 LDO4 off (in I2C on mode). DESCRIPTION 0 1 LDO4 on (in I2C on mode). 1 0 LDO4 on (in PWR_REQ on mode) (Group D). 1 1 LDO4 on (in PWR_REQ on mode) (Group D). 57 MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform Table 39. LDO4V Register (Output Voltage Setting for OUT4) ADDRESS (HEX) POR (HEX) R/W 53 00 R/W BITS 7:5 BIT 7 BIT 6 BIT 5 BIT 4 Reserved Reserved Reserved BIT 3 BIT 2 BIT 1 BIT 0 L4[4:0] Reserved, write 000 to these bits. DESCRIPTION BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 VPROG (V) 0 0 0 0 0 0.90 0 0 0 0 1 1.00 0 0 0 1 0 1.20 0 0 0 1 1 1.10 X X 1 X X 0.80 X 1 X X X 0.80 1 X X X X 0.80 X = Don't care. Table 40. LDO5 Register (On/Off Control for LDO5) ADDRESS (HEX) POR (HEX) R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 54 00 R/W Reserved Reserved Reserved Reserved Reserved Reserved BITS 7:2 58 Reserved, write 000000 to these bits. BIT 1 BIT 0 0 0 LDO5 off (in I2C on mode). DESCRIPTION 0 1 LDO5 on (in I2C on mode). 1 0 LDO5 on (in PWR_REQ on mode) (Group C). 1 1 LDO5 on (in PWR_REQ on mode) (Group C). BIT 1 BIT 0 LDO5[1:0] Power-Management ICs for ICERA E400/E450 Platform ADDRESS (HEX) POR (HEX) R/W BIT 7 BIT 6 BIT 5 55 07 R/W Reserved Reserved Reserved BITS 7:5 BIT 4 BIT 3 BIT 2 BIT 1 MAX8982A/MAX8982X Table 41. LDO5V Register (Output Voltage Setting for OUT5) BIT 0 L5[4:0] Reserved, write 000 to these bits. DESCRIPTION BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 VPROG (V) 0 0 0 0 0 3.20 0 0 0 0 1 3.20 0 0 0 1 0 3.20 0 0 0 1 1 3.20 0 0 1 0 0 3.20 0 0 1 0 1 2.80 0 0 1 1 0 2.80 0 0 1 1 1 3.00 0 1 0 0 0 3.00 0 1 0 0 1 2.90 0 1 0 1 0 2.90 0 1 0 1 1 3.00 0 1 1 X X 3.00 1 X X X X 3.00 X = Don't care. Table 42. LDO6 Register (On/Off Control for LDO6) ADDRESS (HEX) POR (HEX) R/W 56 01 R/W BITS 7:2 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 Reserved Reserved Reserved Reserved Reserved Reserved BIT 1 BIT 0 LDO6[1:0] Reserved, write 000000 to these bits. BIT 1 BIT 0 DESCRIPTION 0 0 LDO6 on (in PWR_REQ on mode) (Group C). 0 1 LDO6 on (in PWR_REQ on mode) (Group C). 1 0 LDO6 off (in I2C off mode). 1 1 LDO6 on (in I2C on mode). Note: The enable mapping for LDO6 is different from all other LDOs. 59 MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform Table 43. LDO6V Register (Output Voltage Setting for OUT6) ADDRESS (HEX) POR (HEX) R/W BIT 7 BIT 6 BIT 5 57 07 R/W Reserved Reserved Reserved BITS 7:5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 L6[4:0] Reserved, write 000 to these bits. DESCRIPTION BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 VPROG (V) 0 0 0 0 0 2.65 0 0 0 0 1 2.65 0 0 0 1 0 2.65 0 0 0 1 1 2.65 0 0 1 0 0 2.65 0 0 1 0 1 2.70 0 0 1 1 0 2.70 0 0 1 1 1 2.70 0 1 0 0 0 2.75 0 1 0 0 1 2.80 0 1 0 1 0 2.85 0 1 0 1 1 2.90 0 1 1 0 0 2.95 0 1 1 0 1 3.00 0 1 1 1 X 3.00 1 X X X X 3.00 X = Don't care. Table 44. VSIM Register (On/Off Control for VSIM (LDO7)) ADDRESS (HEX) POR (HEX) R/W 58 00 R/W BITS 7:2 BIT 1 60 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved, write 000000 to these bits. BIT 0 DESCRIPTION I2C off mode). 0 0 LDO7 off (in 0 1 LDO7 on (in I2C on mode). 1 0 LDO7 on (in PWR_REQ on mode) (Group C). 1 1 LDO7 on (in PWR_REQ on mode) (Group C). BIT 1 BIT 0 LDO7[1:0] Power-Management ICs for ICERA E400/E450 Platform ADDRESS (HEX) POR (HEX) R/W BIT 7 BIT 6 BIT 5 59 0B R/W Reserved Reserved Reserved BITS 7:5 BIT 4 BIT 3 BIT 2 BIT 1 MAX8982A/MAX8982X Table 45. VSIMV Register (Output Voltage Setting for VSIM) BIT 0 L7[4:0] Reserved, write 000 to these bits. DESCRIPTION BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 VPROG (V) 0 0 0 0 0 1.80 0 0 0 0 1 1.80 0 0 0 1 0 1.80 0 0 0 1 1 1.80 0 0 1 0 0 1.80 0 0 1 0 1 1.80 0 0 1 1 0 1.80 0 0 1 1 1 1.80 0 1 0 0 0 1.80 0 1 0 0 1 1.80 0 1 0 1 0 1.80 0 1 0 1 1 3.00 0 1 1 X X 3.00 X X X X 3.00 1 X = Don't care. Table 46. LDO8 Register (On/Off Control for LDO8) ADDRESS (HEX) POR (HEX) R/W 5A 01 R/W BITS 7:2 BIT 1 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 Reserved Reserved Reserved Reserved Reserved Reserved BIT 1 BIT 0 LDO8[1:0] Reserved, write 000000 to these bits. BIT 0 DESCRIPTION I2C off mode). 0 0 LDO8 off (in 0 1 LDO8 on (in I2C on mode). 1 0 LDO8 on (in PWR_REQ on mode) (Group C). 1 1 LDO8 on (in PWR_REQ on mode) (Group C). Note: This register is not used by the MAX8982X. 61 MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform Table 47. LDO8V Register (Output Voltage Setting for OUT8) ADDRESS (HEX) POR (HEX) R/W BIT 7 BIT 6 BIT 5 5B 06 R/W Reserved Reserved Reserved BITS 7:5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 L8[4:0] Reserved, write 000 to these bits. DESCRIPTION BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 VPROG (V) 0 0 0 0 0 3.00 0 0 0 0 1 3.00 0 0 0 1 0 3.00 0 0 0 1 1 3.00 0 0 1 0 0 3.00 0 0 1 0 1 3.00 0 0 1 1 0 3.00 0 0 1 1 1 3.10 0 1 0 0 0 3.20 0 1 0 0 1 3.20 0 1 0 1 0 3.20 0 1 0 1 1 3.20 0 1 1 0 0 3.20 0 1 1 0 1 3.20 0 1 1 1 0 3.20 0 1 1 1 1 3.20 1 0 0 0 0 3.20 1 0 0 0 1 3.20 1 0 0 1 X 3.30 1 0 1 X X 3.30 1 1 X X X 3.30 Note: This register is not used by the MAX8982X. X = Don't care. Table 48. LDO9 Register (On/Off Control for LDO9) ADDRESS (HEX) POR (HEX) R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 5C 01 R/W Reserved Reserved Reserved Reserved Reserved Reserved BITS 7:2 62 Reserved, write 000000 to these bits. BIT 1 BIT 0 0 0 LDO9 off (in I2C off mode). DESCRIPTION 0 1 LDO9 on (in I2C on mode). 1 0 LDO9 on (in PWR_REQ on mode) (Group D). 1 1 LDO9 on (in PWR_REQ on mode) (Group D). BIT 1 BIT 0 LDO9[1:0] Power-Management ICs for ICERA E400/E450 Platform ADDRESS (HEX) POR (HEX) R/W BIT 7 BIT 6 BIT 5 5D 00 R/W Reserved Reserved Reserved BITS 7:5 BIT 4 BIT 3 BIT 2 BIT 1 MAX8982A/MAX8982X Table 49. LDO9V Register (Output Voltage Setting for OUT9) BIT 0 L9[4:0] Reserved, write 000 to these bits. DESCRIPTION BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 VPROG (V) 0 0 0 0 0 0.90 0 0 0 0 1 1.00 0 0 0 1 0 1.20 0 0 0 1 1 1.10 X X 1 X X 0.80 X 1 X X X 0.80 1 X X X X 0.80 X = Don't care. Table 50. LED_EN Register (On/Off Control for 3 Current Regulators) ADDRESS (HEX) POR (HEX) R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 6B 00 R/W Reserved Reserved Reserved Reserved Reserved LED3 EN LED2 EN LED1 EN NAME POR DESCRIPTION LED3EN 0 1: Turn on LED3. 0: Turn off LED3. LED2EN 0 1: Turn on LED2. 0: Turn off LED2. LED1EN 0 1: Turn on LED1. 0: Turn off LED1. 63 MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform Table 51. On/Off Register (On/Off Control for BUCK3, BUCK4, and the Internal 32kHz Clock) ADDRESS (HEX) POR (HEX) R/W 70 03 R/W BITS 7:5 BIT 7 BIT 6 BIT 5 Reserved Reserved Reserved BIT 4 BIT 3 BUCK4[1:0] BIT 2 BIT 1 BUCK3[1:0] BIT 0 32KCLK Reserved, write 000 to these bits. NAME DESCRIPTION BUCK4[1] BUCK4[0] 0 0 BUCK4 off (in I2C on mode). 0 1 BUCK4 on (in I2C on mode). 1 0 BUCK4 on (in PWR_REQ on mode) (Group B). 1 1 BUCK4 on (in PWR_REQ on mode) (Group B). BUCK3[1] BUCK3[0] DESCRIPTION I 2C on mode). 0 0 BUCK3 OFF (in 0 1 BUCK3 ON (in I2C on mode). 1 0 BUCK3 ON (in PWR_REQ on mode). 1 1 BUCK3 ON (in PWR_REQ on mode). NAME POR 32KCLK DESCRIPTION 1: Turn on 32kHz. 0: Turn off 32kHz. 1 Note: The BUCK3 and BUCK4 bits are not used by the MAX8982X. Table 52. BUCK3 Register (Output Voltage Setting for BUCK3) ADDRESS (HEX) POR (HEX) R/W BIT 7 BIT 6 BIT 5 BIT 4 72 06 R/W Reserved Reserved Reserved Reserved BITS 7:4 BIT 3 BIT 2 BIT 1 SD3[3:0] Reserved, write 0000 to these bits. DESCRIPTION BIT 2 BIT 1 BIT 0 0 0 0 0 2.90 0 0 0 1 2.95 0 0 1 0 3.00 0 0 1 1 3.05 0 1 0 0 3.10 0 1 0 1 3.15 0 1 1 0 3.20 0 1 1 1 3.25 1 0 0 0 3.30 1 0 0 1 3.35 1 0 1 0 3.40 1 0 1 1 3.45 1 1 0 0 3.50 1 1 0 1 3.55 1 1 1 0 3.60 1 1 3.65 1 1 Note: This register is not used by the MAX8982X. 64 VPROG (V) BIT 3 BIT 0 Power-Management ICs for ICERA E400/E450 Platform ADDRESS (HEX) POR (HEX) R/W BIT 7 BIT 6 BIT 5 BIT 4 73 08 R/W Reserved Reserved Reserved Reserved BITS 7:4 BIT 3 BIT 2 BIT 1 MAX8982A/MAX8982X Table 53. BUCK4 Register (Output Voltage Setting for BUCK4) BIT 0 SD4[3:0] Reserved, write 0000 to these bits. DESCRIPTION BIT 3 BIT 2 BIT 1 BIT 0 VPROG (V) 0 0 0 0 3.00 0 0 0 1 3.05 0 0 1 0 3.10 0 0 1 1 3.15 0 1 0 0 3.20 0 1 0 1 3.25 0 1 1 0 3.30 0 1 1 1 3.35 1 0 0 0 3.40 1 0 0 1 3.45 1 0 1 0 3.50 1 0 1 1 3.55 1 1 0 0 3.60 1 1 0 1 3.65 1 1 1 0 3.70 1 1 1 1 3.75 Note: This register is not used by the MAX8982X. 65 MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform Table 54. CURRENTREG1 Register (Current Setting for Current Regulators DR1 and DR2) ADDRESS (HEX) POR (HEX) R/W BIT 7 BIT 6 75 3F R/W Reserved Reserved BITS 7:6 BIT 5 BIT 4 BIT 3 BIT 2 DR1[2:0] BIT 1 BIT 0 DR2[2:0] Reserved, write 00 to these bits. DESCRIPTION DR1[2] DR1[1] DR1[0] IDR1 PROG (mA) 0 0 0 3 0 0 1 6 0 1 0 9 0 1 1 12 1 0 0 15 1 0 1 18 1 1 0 21 1 1 1 24 DR2[2] DR2[1] DR2[0] IDR2 PROG (mA) 0 0 0 3 0 0 1 6 0 1 0 9 0 1 1 12 1 0 0 15 1 0 1 18 1 1 0 21 1 1 1 24 Table 55. CURRENTREG2 Register (Current Setting for Current Regulator DR3) ADDRESS (HEX) POR (HEX) R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 76 07 R/W Reserved Reserved Reserved Reserved Reserved BITS 7:3 BIT 2 BIT 1 BIT 0 DR3[2:0] Reserved, write 00000 to these bits. DESCRIPTION 66 IDR3 PROG (mA) DR3[2] DR3[1] DR3[0] 0 0 0 3 0 0 1 6 0 1 0 9 0 1 1 12 1 0 0 15 1 0 1 18 1 1 0 21 1 1 1 24 Power-Management ICs for ICERA E400/E450 Platform ADDRESS (HEX) POR (HEX) R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 77 02 R/W Reserved Reserved Reserved Reserved Reserved Reserved BITS 7:2 BIT 1 MAX8982A/MAX8982X Table 56. RAMP Register (Slope Setting for BUCK1) BIT 0 RASD1[1:0] Reserved, write 000000 to these bits. DESCRIPTION SLEW RATE (mV/s) BIT 1 BIT 0 0 0 5 0 1 10 1 0 12.5 1 1 25 Table 57. BUCK1-4ADIS Register (Active Discharge Settings for BUCK1-BUCK4) ADDRESS (HEX) POR (HEX) R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 78 04 R/W Reserved Reserved Reserved Reserved SD1 ADIS SD2 ADIS SD3 ADIS SD4 ADIS BITS 7:4 Reserved, write 0000 to these bits. DESCRIPTION SD1ADIS 0 1: Enable BUCK1 active discharge. 0: Disable BUCK1 active discharge. SD2ADIS 1 1: Enable BUCK2 active discharge. 0: Disable BUCK2 active discharge. SD3ADIS 0 1: Enable BUCK3 active discharge. 0: Disable BUCK3 active discharge. SD4ADIS 0 1: Enable BUCK4 active discharge. 0: Disable BUCK4 active discharge. Note: The SD3ADIS and SD4ADIS bits are not used by the MAX8982X. 67 MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform Table 58. LDO1-8ADIS Register (Active Discharge Settings for LDO1-LDO8) ADDRESS (HEX) POR (HEX) R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 79 00 R/W LDO1 ADIS LDO2 ADIS LDO3 ADIS LDO4 ADIS LDO5 ADIS LDO6 ADIS LDO7 ADIS LDO8 ADIS DESCRIPTION LDO1ADIS 0 1: Enable LDO1 active discharge. 0: Disable LDO1 active discharge. LDO2ADIS 0 1: Enable LDO2 active discharge. 0: Disable LDO2 active discharge. LDO3ADIS 0 1: Enable LDO3 active discharge. 0: Disable LDO3 active discharge. LDO4ADIS 0 1: Enable LDO4 active discharge. 0: Disable LDO4 active discharge. LDO5ADIS 0 1: Enable LDO5 active discharge. 0: Disable LDO5 active discharge. LDO6ADIS 0 1: Enable LDO6 active discharge. 0: Disable LDO6 active discharge. LDO7ADIS 0 1: Enable LDO7 active discharge. 0: Disable LDO7 active discharge. LDO8ADIS 0 1: Enable LDO8 active discharge. 0: Disable LDO8 active discharge. Note: The LDO8ADIS bit is not used by the MAX8982X. Table 59. LDO9ADIS Register (Active Discharge Setting for LDO9) ADDRESS (HEX) POR (HEX) R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 7A 00 R/W Reserved Reserved Reserved Reserved Reserved Reserved Reserved LDO9 ADIS BITS 7:1 Reserved, write 0000000 to these bits. DESCRIPTION LDO9ADIS 68 0 1: Enable LDO9 active discharge. 0: Disable LDO9 active discharge. Power-Management ICs for ICERA E400/E450 Platform Inductor Selection The step-down converters operate with inductors of 1FH to 4.7FH. Low inductance values are physically smaller, but require faster switching, which results in some efficiency loss. The inductor's DC current rating only needs to match the maximum load current of the application plus 100mA because the step-down converters feature zero current overshoot during startup and load transients. For optimum voltage positioning load transients, choose an inductor with DC series resistance in the 30mW to 100mW range. For higher efficiency at heavy load (above 200mA) or minimal load regulation (but some transient overshoot), the resistance should be kept below 100mW. For light load applications up to 200mA, a higher resistance is acceptable with very little impact on performance. Recommended inductors are listed in Table 60. Table 60. Recommended Inductors MANUFACTURER SERIES MDT2520-CR TOKO DE2810C Flat Wire DE2812C Flat Wire DEM3518C DEM2818C* KSLI-252010AG Hitachi-Metals KSLI-201610AG KSLI-201210AG KSLI-252012AG-2R2** INDUCTANCE (FH) DC RESISTANCE (I typ) CURRENT RATING (mA) DT = +40NC RISE 1.0 1.5 2.2 3.3 1.5 2.2 3.3 4.7 1.5 2.0 3.3 4.7 2.2 2.2 1 0.06 0.08 0.09 0.10 0.06 0.085 0.130 0.180 0.050 0.067 0.100 0.130 0.040 0.039 0.050 1550 1400 1350 1300 2000 1600 1300 1100 2600 2300 1700 1500 2550 2200 2600 2.2 0.100 1800 3.3 0.100 1800 4.7 0.115 1700 1 0.090 1900 2.2 0.140 1500 3.3 0.180 1300 4.7 0.200 1300 1 0.120 1500 2.2 0.190 1300 3.3 0.230 1200 4.7 0.270 1100 2.2 0.1 1900 DIMENSIONS L x W x H (mm) 2.5 x 2.0 x 1.0 3.0 x 2.8 x 1.0 3.0 x 2.8 x 1.2 3.9 x 3.7 x 1.8 3.0 x 3.0 x 1.8 2.5 x 2.0 x 1.0 2.0 x 1.6 x 1.0 2.0 x 1.2 x 1.0 2.5 x 2.0 x 1.2 69 MAX8982A/MAX8982X Applications Information MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform Table 60. Recommended Inductors (continued) MANUFACTURER INDUCTANCE (FH) DC RESISTANCE (I typ) CURRENT RATING (mA) DT = +40NC RISE 1.5 0.070 1500 2.2 0.080 1300 3.3 0.100 1200 4.7 0.110 1100 1.5 0.110 1100 2.2 0.110 1100 3.3 0.130 1000 4.7 0.160 900 1.0 0.090 1100 2.2 0.230 700 3.3 0.190 800 LQM2HP_G0 4.7 1.0 2.2 3.3 4.7 1.0 0.230 0.055 0.80 0.100 0.110 0.190 700 1500 1300 1200 1100 800 2.5 x 2.0 x 1.0 LQM21P 1.5 0.260 700 2.0 x 1.25 x 0.50 2.2 1.0 2.2 3.3 4.7 1.0 1.0 2.2 3.3 4.7 2.2 0.340 0.085 0.110 0.120 0.140 0.030 0.080 0.090 0.120 0.150 0.090 600 1400 1200 1200 1100 2100 1400 1300 1200 1100 1000 1.0 0.080 1500 2.2 0.110 1200 4.7 1.0 2.2 3.3 4.7 1.0 2.2 3.3 4.7 0.110 0.060 0.080 0.100 0.110 0.130 0.200 0.250 0.300 1000 1500 1300 1200 1100 1050 810 730 650 SERIES MIPF2520D FDK MIPF2016D*** MIPF2012D Murata LQM2MPN*** NR3015T1R0N*** Taiyo Yuden CKP2520 MLP2520S2R2M TDK MLP2520S_S CIG22L_ Samsung ElectroMechanics CIG21W_ *Recommended for BUCK4. **Recommended for BUCK1. ***Recommended for BUCK2 and BUCK3. 70 DIMENSIONS L x W x H (mm) 2.5 x 2.0 x 1.0 2.0 x 1.6 x 1.0 2.0 x 1.2 x 1.0 2.0 x 1.6 x 1.0 3.0 x 3.0 x 1.5 2.5 x 2.0 x 1.0 2.5 x 2.0 x 1.0 2.5 x 2.0 x 1.2 2.5 x 2.0 x 1.0 2.0 x 1.25 x 1.0 Power-Management ICs for ICERA E400/E450 Platform PCB Layout Guidelines Due to fast switching waveforms and high current paths, careful PCB layout is required to achieve optimal performance. Minimize trace lengths between the IC and the inductor, the input capacitor, and the output capacitor for each step-down converter. Keep these traces short, direct, and wide. Route noise sensitive traces away from the switching nodes (LX_). Refer to the MAX8982A/MAX8982X EV Kit for a PCB layout example. Input Capacitor Selection The input capacitor, CIN1_ or CIN_, reduces the current peaks drawn from the input power source and reduces switching noise in the IC. The impedance of CIN2 at the switching frequency should be kept very low. Ceramic capacitors with X5R or X7R temperature characteristics are highly recommended due to their small size, low ESR, and small temperature coefficients. Recommended capacitor values are shown in Figures 1 and 2. Chip Information PROCESS: BiCMOS 71 MAX8982A/MAX8982X Output Capacitor Selection The output capacitor, COUT, is required to keep the output voltage ripple small and to ensure regulation loop stability. COUT must have low impedance at the switching frequency. Ceramic capacitors with X5R or X7R temperature characteristics are highly recommended due to their small size, low ESR, and small temperature coefficients. Due to the unique feedback network, the output capacitance can be very low. Recommended capacitor values are shown in Figures 1 and 2. MAX8982A/MAX8982X Power-Management ICs for ICERA E400/E450 Platform Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. 72 PACKAGE TYPE PACKAGE CODE OUTLINE No. LAND PATTERN NO. 42 WLP W423D3+1 21-0440 -- Power-Management ICs for ICERA E400/E450 Platform REVISION NUMBER REVISION DATE 0 12/10 Initial release -- 1 1/11 Added 42 WLP package diagram 72 DESCRIPTION PAGES CHANGED Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2011 Maxim Integrated Products 73 Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX8982A/MAX8982X Revision History